if_sip.c revision 1.174
1 /* $NetBSD: if_sip.c,v 1.174 2019/07/09 08:46:59 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999 Network Computer, Inc. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of Network Computer, Inc. nor the names of its 45 * contributors may be used to endorse or promote products derived 46 * from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * Device driver for the Silicon Integrated Systems SiS 900, 63 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 64 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 65 * controllers. 66 * 67 * Originally written to support the SiS 900 by Jason R. Thorpe for 68 * Network Computer, Inc. 69 * 70 * TODO: 71 * 72 * - Reduce the Rx interrupt load. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.174 2019/07/09 08:46:59 msaitoh Exp $"); 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/callout.h> 81 #include <sys/mbuf.h> 82 #include <sys/malloc.h> 83 #include <sys/kernel.h> 84 #include <sys/socket.h> 85 #include <sys/ioctl.h> 86 #include <sys/errno.h> 87 #include <sys/device.h> 88 #include <sys/queue.h> 89 #include <sys/rndsource.h> 90 91 #include <net/if.h> 92 #include <net/if_dl.h> 93 #include <net/if_media.h> 94 #include <net/if_ether.h> 95 #include <net/bpf.h> 96 97 #include <sys/bus.h> 98 #include <sys/intr.h> 99 #include <machine/endian.h> 100 101 #include <dev/mii/mii.h> 102 #include <dev/mii/miivar.h> 103 #include <dev/mii/mii_bitbang.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 109 #include <dev/pci/if_sipreg.h> 110 111 /* 112 * Transmit descriptor list size. This is arbitrary, but allocate 113 * enough descriptors for 128 pending transmissions, and 8 segments 114 * per packet (64 for DP83820 for jumbo frames). 115 * 116 * This MUST work out to a power of 2. 117 */ 118 #define GSIP_NTXSEGS_ALLOC 16 119 #define SIP_NTXSEGS_ALLOC 8 120 121 #define SIP_TXQUEUELEN 256 122 #define MAX_SIP_NTXDESC \ 123 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 124 125 /* 126 * Receive descriptor list size. We have one Rx buffer per incoming 127 * packet, so this logic is a little simpler. 128 * 129 * Actually, on the DP83820, we allow the packet to consume more than 130 * one buffer, in order to support jumbo Ethernet frames. In that 131 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 132 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 133 * so we'd better be quick about handling receive interrupts. 134 */ 135 #define GSIP_NRXDESC 256 136 #define SIP_NRXDESC 128 137 138 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 139 140 /* 141 * Control structures are DMA'd to the SiS900 chip. We allocate them in 142 * a single clump that maps to a single DMA segment to make several things 143 * easier. 144 */ 145 struct sip_control_data { 146 /* 147 * The transmit descriptors. 148 */ 149 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 150 151 /* 152 * The receive descriptors. 153 */ 154 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 155 }; 156 157 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 158 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 159 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 160 161 /* 162 * Software state for transmit jobs. 163 */ 164 struct sip_txsoft { 165 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 166 bus_dmamap_t txs_dmamap; /* our DMA map */ 167 int txs_firstdesc; /* first descriptor in packet */ 168 int txs_lastdesc; /* last descriptor in packet */ 169 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 170 }; 171 172 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 173 174 /* 175 * Software state for receive jobs. 176 */ 177 struct sip_rxsoft { 178 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 179 bus_dmamap_t rxs_dmamap; /* our DMA map */ 180 }; 181 182 enum sip_attach_stage { 183 SIP_ATTACH_FIN = 0 184 , SIP_ATTACH_CREATE_RXMAP 185 , SIP_ATTACH_CREATE_TXMAP 186 , SIP_ATTACH_LOAD_MAP 187 , SIP_ATTACH_CREATE_MAP 188 , SIP_ATTACH_MAP_MEM 189 , SIP_ATTACH_ALLOC_MEM 190 , SIP_ATTACH_INTR 191 , SIP_ATTACH_MAP 192 }; 193 194 /* 195 * Software state per device. 196 */ 197 struct sip_softc { 198 device_t sc_dev; /* generic device information */ 199 device_suspensor_t sc_suspensor; 200 pmf_qual_t sc_qual; 201 202 bus_space_tag_t sc_st; /* bus space tag */ 203 bus_space_handle_t sc_sh; /* bus space handle */ 204 bus_size_t sc_sz; /* bus space size */ 205 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 206 pci_chipset_tag_t sc_pc; 207 bus_dma_segment_t sc_seg; 208 struct ethercom sc_ethercom; /* ethernet common data */ 209 210 const struct sip_product *sc_model; /* which model are we? */ 211 int sc_gigabit; /* 1: 83820, 0: other */ 212 int sc_rev; /* chip revision */ 213 214 void *sc_ih; /* interrupt cookie */ 215 216 struct mii_data sc_mii; /* MII/media information */ 217 218 callout_t sc_tick_ch; /* tick callout */ 219 220 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 221 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 222 223 /* 224 * Software state for transmit and receive descriptors. 225 */ 226 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 227 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 228 229 /* 230 * Control data structures. 231 */ 232 struct sip_control_data *sc_control_data; 233 #define sc_txdescs sc_control_data->scd_txdescs 234 #define sc_rxdescs sc_control_data->scd_rxdescs 235 236 #ifdef SIP_EVENT_COUNTERS 237 /* 238 * Event counters. 239 */ 240 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 241 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 242 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 243 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 244 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 245 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 246 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 247 struct evcnt sc_ev_rxpause; /* PAUSE received */ 248 /* DP83820 only */ 249 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 250 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 251 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 252 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 253 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 254 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 255 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 256 #endif /* SIP_EVENT_COUNTERS */ 257 258 uint32_t sc_txcfg; /* prototype TXCFG register */ 259 uint32_t sc_rxcfg; /* prototype RXCFG register */ 260 uint32_t sc_imr; /* prototype IMR register */ 261 uint32_t sc_rfcr; /* prototype RFCR register */ 262 263 uint32_t sc_cfg; /* prototype CFG register */ 264 265 uint32_t sc_gpior; /* prototype GPIOR register */ 266 267 uint32_t sc_tx_fill_thresh; /* transmit fill threshold */ 268 uint32_t sc_tx_drain_thresh; /* transmit drain threshold */ 269 270 uint32_t sc_rx_drain_thresh; /* receive drain threshold */ 271 272 int sc_flowflags; /* 802.3x flow control flags */ 273 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 274 int sc_paused; /* paused indication */ 275 276 int sc_txfree; /* number of free Tx descriptors */ 277 int sc_txnext; /* next ready Tx descriptor */ 278 int sc_txwin; /* Tx descriptors since last intr */ 279 280 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 281 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 282 283 /* values of interface state at last init */ 284 struct { 285 /* if_capenable */ 286 uint64_t if_capenable; 287 /* ec_capenable */ 288 int ec_capenable; 289 /* VLAN_ATTACHED */ 290 int is_vlan; 291 } sc_prev; 292 293 short sc_if_flags; 294 295 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 296 int sc_rxdiscard; 297 int sc_rxlen; 298 struct mbuf *sc_rxhead; 299 struct mbuf *sc_rxtail; 300 struct mbuf **sc_rxtailp; 301 302 int sc_ntxdesc; 303 int sc_ntxdesc_mask; 304 305 int sc_nrxdesc_mask; 306 307 const struct sip_parm { 308 const struct sip_regs { 309 int r_rxcfg; 310 int r_txcfg; 311 } p_regs; 312 313 const struct sip_bits { 314 uint32_t b_txcfg_mxdma_8; 315 uint32_t b_txcfg_mxdma_16; 316 uint32_t b_txcfg_mxdma_32; 317 uint32_t b_txcfg_mxdma_64; 318 uint32_t b_txcfg_mxdma_128; 319 uint32_t b_txcfg_mxdma_256; 320 uint32_t b_txcfg_mxdma_512; 321 uint32_t b_txcfg_flth_mask; 322 uint32_t b_txcfg_drth_mask; 323 324 uint32_t b_rxcfg_mxdma_8; 325 uint32_t b_rxcfg_mxdma_16; 326 uint32_t b_rxcfg_mxdma_32; 327 uint32_t b_rxcfg_mxdma_64; 328 uint32_t b_rxcfg_mxdma_128; 329 uint32_t b_rxcfg_mxdma_256; 330 uint32_t b_rxcfg_mxdma_512; 331 332 uint32_t b_isr_txrcmp; 333 uint32_t b_isr_rxrcmp; 334 uint32_t b_isr_dperr; 335 uint32_t b_isr_sserr; 336 uint32_t b_isr_rmabt; 337 uint32_t b_isr_rtabt; 338 339 uint32_t b_cmdsts_size_mask; 340 } p_bits; 341 int p_filtmem; 342 int p_rxbuf_len; 343 bus_size_t p_tx_dmamap_size; 344 int p_ntxsegs; 345 int p_ntxsegs_alloc; 346 int p_nrxdesc; 347 } *sc_parm; 348 349 void (*sc_rxintr)(struct sip_softc *); 350 351 krndsource_t rnd_source; /* random source */ 352 }; 353 354 #define sc_bits sc_parm->p_bits 355 #define sc_regs sc_parm->p_regs 356 357 static const struct sip_parm sip_parm = { 358 .p_filtmem = OTHER_RFCR_NS_RFADDR_FILTMEM 359 , .p_rxbuf_len = MCLBYTES - 1 /* field width */ 360 , .p_tx_dmamap_size = MCLBYTES 361 , .p_ntxsegs = 16 362 , .p_ntxsegs_alloc = SIP_NTXSEGS_ALLOC 363 , .p_nrxdesc = SIP_NRXDESC 364 , .p_bits = { 365 .b_txcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 366 , .b_txcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 367 , .b_txcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 368 , .b_txcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 369 , .b_txcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 370 , .b_txcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 371 , .b_txcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 372 , .b_txcfg_flth_mask = 0x00003f00 /* Tx fill threshold */ 373 , .b_txcfg_drth_mask = 0x0000003f /* Tx drain threshold */ 374 375 , .b_rxcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 376 , .b_rxcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 377 , .b_rxcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 378 , .b_rxcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 379 , .b_rxcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 380 , .b_rxcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 381 , .b_rxcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 382 383 , .b_isr_txrcmp = 0x02000000 /* transmit reset complete */ 384 , .b_isr_rxrcmp = 0x01000000 /* receive reset complete */ 385 , .b_isr_dperr = 0x00800000 /* detected parity error */ 386 , .b_isr_sserr = 0x00400000 /* signalled system error */ 387 , .b_isr_rmabt = 0x00200000 /* received master abort */ 388 , .b_isr_rtabt = 0x00100000 /* received target abort */ 389 , .b_cmdsts_size_mask = OTHER_CMDSTS_SIZE_MASK 390 } 391 , .p_regs = { 392 .r_rxcfg = OTHER_SIP_RXCFG, 393 .r_txcfg = OTHER_SIP_TXCFG 394 } 395 }, gsip_parm = { 396 .p_filtmem = DP83820_RFCR_NS_RFADDR_FILTMEM 397 , .p_rxbuf_len = MCLBYTES - 8 398 , .p_tx_dmamap_size = ETHER_MAX_LEN_JUMBO 399 , .p_ntxsegs = 64 400 , .p_ntxsegs_alloc = GSIP_NTXSEGS_ALLOC 401 , .p_nrxdesc = GSIP_NRXDESC 402 , .p_bits = { 403 .b_txcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 404 , .b_txcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 405 , .b_txcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 406 , .b_txcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 407 , .b_txcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 408 , .b_txcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 409 , .b_txcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 410 , .b_txcfg_flth_mask = 0x0000ff00 /* Fx fill threshold */ 411 , .b_txcfg_drth_mask = 0x000000ff /* Tx drain threshold */ 412 413 , .b_rxcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 414 , .b_rxcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 415 , .b_rxcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 416 , .b_rxcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 417 , .b_rxcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 418 , .b_rxcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 419 , .b_rxcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 420 421 , .b_isr_txrcmp = 0x00400000 /* transmit reset complete */ 422 , .b_isr_rxrcmp = 0x00200000 /* receive reset complete */ 423 , .b_isr_dperr = 0x00100000 /* detected parity error */ 424 , .b_isr_sserr = 0x00080000 /* signalled system error */ 425 , .b_isr_rmabt = 0x00040000 /* received master abort */ 426 , .b_isr_rtabt = 0x00020000 /* received target abort */ 427 , .b_cmdsts_size_mask = DP83820_CMDSTS_SIZE_MASK 428 } 429 , .p_regs = { 430 .r_rxcfg = DP83820_SIP_RXCFG, 431 .r_txcfg = DP83820_SIP_TXCFG 432 } 433 }; 434 435 static inline int 436 sip_nexttx(const struct sip_softc *sc, int x) 437 { 438 return (x + 1) & sc->sc_ntxdesc_mask; 439 } 440 441 static inline int 442 sip_nextrx(const struct sip_softc *sc, int x) 443 { 444 return (x + 1) & sc->sc_nrxdesc_mask; 445 } 446 447 /* 83820 only */ 448 static inline void 449 sip_rxchain_reset(struct sip_softc *sc) 450 { 451 sc->sc_rxtailp = &sc->sc_rxhead; 452 *sc->sc_rxtailp = NULL; 453 sc->sc_rxlen = 0; 454 } 455 456 /* 83820 only */ 457 static inline void 458 sip_rxchain_link(struct sip_softc *sc, struct mbuf *m) 459 { 460 *sc->sc_rxtailp = sc->sc_rxtail = m; 461 sc->sc_rxtailp = &m->m_next; 462 } 463 464 #ifdef SIP_EVENT_COUNTERS 465 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 466 #else 467 #define SIP_EVCNT_INCR(ev) /* nothing */ 468 #endif 469 470 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 471 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 472 473 static inline void 474 sip_cdtxsync(struct sip_softc *sc, const int x0, const int n0, const int ops) 475 { 476 int x, n; 477 478 x = x0; 479 n = n0; 480 481 /* If it will wrap around, sync to the end of the ring. */ 482 if (x + n > sc->sc_ntxdesc) { 483 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 484 SIP_CDTXOFF(x), sizeof(struct sip_desc) * 485 (sc->sc_ntxdesc - x), ops); 486 n -= (sc->sc_ntxdesc - x); 487 x = 0; 488 } 489 490 /* Now sync whatever is left. */ 491 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 492 SIP_CDTXOFF(x), sizeof(struct sip_desc) * n, ops); 493 } 494 495 static inline void 496 sip_cdrxsync(struct sip_softc *sc, int x, int ops) 497 { 498 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 499 SIP_CDRXOFF(x), sizeof(struct sip_desc), ops); 500 } 501 502 #if 0 503 #ifdef DP83820 504 uint32_t sipd_bufptr; /* pointer to DMA segment */ 505 uint32_t sipd_cmdsts; /* command/status word */ 506 #else 507 uint32_t sipd_cmdsts; /* command/status word */ 508 uint32_t sipd_bufptr; /* pointer to DMA segment */ 509 #endif /* DP83820 */ 510 #endif /* 0 */ 511 512 static inline volatile uint32_t * 513 sipd_cmdsts(struct sip_softc *sc, struct sip_desc *sipd) 514 { 515 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 1 : 0]; 516 } 517 518 static inline volatile uint32_t * 519 sipd_bufptr(struct sip_softc *sc, struct sip_desc *sipd) 520 { 521 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 0 : 1]; 522 } 523 524 static inline void 525 sip_init_rxdesc(struct sip_softc *sc, int x) 526 { 527 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 528 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 529 530 sipd->sipd_link = htole32(SIP_CDRXADDR(sc, sip_nextrx(sc, x))); 531 *sipd_bufptr(sc, sipd) = htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 532 *sipd_cmdsts(sc, sipd) = htole32(CMDSTS_INTR | 533 (sc->sc_parm->p_rxbuf_len & sc->sc_bits.b_cmdsts_size_mask)); 534 sipd->sipd_extsts = 0; 535 sip_cdrxsync(sc, x, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 536 } 537 538 #define SIP_CHIP_VERS(sc, v, p, r) \ 539 ((sc)->sc_model->sip_vendor == (v) && \ 540 (sc)->sc_model->sip_product == (p) && \ 541 (sc)->sc_rev == (r)) 542 543 #define SIP_CHIP_MODEL(sc, v, p) \ 544 ((sc)->sc_model->sip_vendor == (v) && \ 545 (sc)->sc_model->sip_product == (p)) 546 547 #define SIP_SIS900_REV(sc, rev) \ 548 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 549 550 #define SIP_TIMEOUT 1000 551 552 static int sip_ifflags_cb(struct ethercom *); 553 static void sipcom_start(struct ifnet *); 554 static void sipcom_watchdog(struct ifnet *); 555 static int sipcom_ioctl(struct ifnet *, u_long, void *); 556 static int sipcom_init(struct ifnet *); 557 static void sipcom_stop(struct ifnet *, int); 558 559 static bool sipcom_reset(struct sip_softc *); 560 static void sipcom_rxdrain(struct sip_softc *); 561 static int sipcom_add_rxbuf(struct sip_softc *, int); 562 static void sipcom_read_eeprom(struct sip_softc *, int, int, 563 uint16_t *); 564 static void sipcom_tick(void *); 565 566 static void sipcom_sis900_set_filter(struct sip_softc *); 567 static void sipcom_dp83815_set_filter(struct sip_softc *); 568 569 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 570 const struct pci_attach_args *, uint8_t *); 571 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 572 static void sipcom_sis900_read_macaddr(struct sip_softc *, 573 const struct pci_attach_args *, uint8_t *); 574 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 575 const struct pci_attach_args *, uint8_t *); 576 577 static int sipcom_intr(void *); 578 static void sipcom_txintr(struct sip_softc *); 579 static void sip_rxintr(struct sip_softc *); 580 static void gsip_rxintr(struct sip_softc *); 581 582 static int sipcom_dp83820_mii_readreg(device_t, int, int, uint16_t *); 583 static int sipcom_dp83820_mii_writereg(device_t, int, int, uint16_t); 584 static void sipcom_dp83820_mii_statchg(struct ifnet *); 585 586 static int sipcom_sis900_mii_readreg(device_t, int, int, uint16_t *); 587 static int sipcom_sis900_mii_writereg(device_t, int, int, uint16_t); 588 static void sipcom_sis900_mii_statchg(struct ifnet *); 589 590 static int sipcom_dp83815_mii_readreg(device_t, int, int, uint16_t *); 591 static int sipcom_dp83815_mii_writereg(device_t, int, int, uint16_t); 592 static void sipcom_dp83815_mii_statchg(struct ifnet *); 593 594 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 595 596 static int sipcom_match(device_t, cfdata_t, void *); 597 static void sipcom_attach(device_t, device_t, void *); 598 static void sipcom_do_detach(device_t, enum sip_attach_stage); 599 static int sipcom_detach(device_t, int); 600 static bool sipcom_resume(device_t, const pmf_qual_t *); 601 static bool sipcom_suspend(device_t, const pmf_qual_t *); 602 603 int gsip_copy_small = 0; 604 int sip_copy_small = 0; 605 606 CFATTACH_DECL3_NEW(gsip, sizeof(struct sip_softc), 607 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 608 DVF_DETACH_SHUTDOWN); 609 CFATTACH_DECL3_NEW(sip, sizeof(struct sip_softc), 610 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 611 DVF_DETACH_SHUTDOWN); 612 613 /* 614 * Descriptions of the variants of the SiS900. 615 */ 616 struct sip_variant { 617 int (*sipv_mii_readreg)(device_t, int, int, uint16_t *); 618 int (*sipv_mii_writereg)(device_t, int, int, uint16_t); 619 void (*sipv_mii_statchg)(struct ifnet *); 620 void (*sipv_set_filter)(struct sip_softc *); 621 void (*sipv_read_macaddr)(struct sip_softc *, 622 const struct pci_attach_args *, uint8_t *); 623 }; 624 625 static uint32_t sipcom_mii_bitbang_read(device_t); 626 static void sipcom_mii_bitbang_write(device_t, uint32_t); 627 628 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 629 sipcom_mii_bitbang_read, 630 sipcom_mii_bitbang_write, 631 { 632 EROMAR_MDIO, /* MII_BIT_MDO */ 633 EROMAR_MDIO, /* MII_BIT_MDI */ 634 EROMAR_MDC, /* MII_BIT_MDC */ 635 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 636 0, /* MII_BIT_DIR_PHY_HOST */ 637 } 638 }; 639 640 static const struct sip_variant sipcom_variant_dp83820 = { 641 sipcom_dp83820_mii_readreg, 642 sipcom_dp83820_mii_writereg, 643 sipcom_dp83820_mii_statchg, 644 sipcom_dp83815_set_filter, 645 sipcom_dp83820_read_macaddr, 646 }; 647 648 static const struct sip_variant sipcom_variant_sis900 = { 649 sipcom_sis900_mii_readreg, 650 sipcom_sis900_mii_writereg, 651 sipcom_sis900_mii_statchg, 652 sipcom_sis900_set_filter, 653 sipcom_sis900_read_macaddr, 654 }; 655 656 static const struct sip_variant sipcom_variant_dp83815 = { 657 sipcom_dp83815_mii_readreg, 658 sipcom_dp83815_mii_writereg, 659 sipcom_dp83815_mii_statchg, 660 sipcom_dp83815_set_filter, 661 sipcom_dp83815_read_macaddr, 662 }; 663 664 665 /* 666 * Devices supported by this driver. 667 */ 668 static const struct sip_product { 669 pci_vendor_id_t sip_vendor; 670 pci_product_id_t sip_product; 671 const char *sip_name; 672 const struct sip_variant *sip_variant; 673 int sip_gigabit; 674 } sipcom_products[] = { 675 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 676 "NatSemi DP83820 Gigabit Ethernet", 677 &sipcom_variant_dp83820, 1 }, 678 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 679 "SiS 900 10/100 Ethernet", 680 &sipcom_variant_sis900, 0 }, 681 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 682 "SiS 7016 10/100 Ethernet", 683 &sipcom_variant_sis900, 0 }, 684 685 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 686 "NatSemi DP83815 10/100 Ethernet", 687 &sipcom_variant_dp83815, 0 }, 688 689 { 0, 0, 690 NULL, 691 NULL, 0 }, 692 }; 693 694 static const struct sip_product * 695 sipcom_lookup(const struct pci_attach_args *pa, bool gigabit) 696 { 697 const struct sip_product *sip; 698 699 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 700 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 701 PCI_PRODUCT(pa->pa_id) == sip->sip_product && 702 sip->sip_gigabit == gigabit) 703 return sip; 704 } 705 return NULL; 706 } 707 708 /* 709 * I really hate stupid hardware vendors. There's a bit in the EEPROM 710 * which indicates if the card can do 64-bit data transfers. Unfortunately, 711 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 712 * which means we try to use 64-bit data transfers on those cards if we 713 * happen to be plugged into a 32-bit slot. 714 * 715 * What we do is use this table of cards known to be 64-bit cards. If 716 * you have a 64-bit card who's subsystem ID is not listed in this table, 717 * send the output of "pcictl dump ..." of the device to me so that your 718 * card will use the 64-bit data path when plugged into a 64-bit slot. 719 * 720 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 721 * June 30, 2002 722 */ 723 static int 724 sipcom_check_64bit(const struct pci_attach_args *pa) 725 { 726 static const struct { 727 pci_vendor_id_t c64_vendor; 728 pci_product_id_t c64_product; 729 } card64[] = { 730 /* Asante GigaNIX */ 731 { 0x128a, 0x0002 }, 732 733 /* Accton EN1407-T, Planex GN-1000TE */ 734 { 0x1113, 0x1407 }, 735 736 /* Netgear GA621 */ 737 { 0x1385, 0x621a }, 738 739 /* Netgear GA622 */ 740 { 0x1385, 0x622a }, 741 742 /* SMC EZ Card 1000 (9462TX) */ 743 { 0x10b8, 0x9462 }, 744 745 { 0, 0} 746 }; 747 pcireg_t subsys; 748 int i; 749 750 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 751 752 for (i = 0; card64[i].c64_vendor != 0; i++) { 753 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 754 PCI_PRODUCT(subsys) == card64[i].c64_product) 755 return 1; 756 } 757 758 return 0; 759 } 760 761 static int 762 sipcom_match(device_t parent, cfdata_t cf, void *aux) 763 { 764 struct pci_attach_args *pa = aux; 765 766 if (sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0) != NULL) 767 return 1; 768 769 return 0; 770 } 771 772 static void 773 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 774 { 775 uint32_t reg; 776 int i; 777 778 /* 779 * Cause the chip to load configuration data from the EEPROM. 780 */ 781 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 782 for (i = 0; i < 10000; i++) { 783 delay(10); 784 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 785 PTSCR_EELOAD_EN) == 0) 786 break; 787 } 788 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 789 PTSCR_EELOAD_EN) { 790 printf("%s: timeout loading configuration from EEPROM\n", 791 device_xname(sc->sc_dev)); 792 return; 793 } 794 795 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 796 797 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 798 if (reg & CFG_PCI64_DET) { 799 printf("%s: 64-bit PCI slot detected", device_xname(sc->sc_dev)); 800 /* 801 * Check to see if this card is 64-bit. If so, enable 64-bit 802 * data transfers. 803 * 804 * We can't use the DATA64_EN bit in the EEPROM, because 805 * vendors of 32-bit cards fail to clear that bit in many 806 * cases (yet the card still detects that it's in a 64-bit 807 * slot; go figure). 808 */ 809 if (sipcom_check_64bit(pa)) { 810 sc->sc_cfg |= CFG_DATA64_EN; 811 printf(", using 64-bit data transfers"); 812 } 813 printf("\n"); 814 } 815 816 /* 817 * XXX Need some PCI flags indicating support for 818 * XXX 64-bit addressing. 819 */ 820 #if 0 821 if (reg & CFG_M64ADDR) 822 sc->sc_cfg |= CFG_M64ADDR; 823 if (reg & CFG_T64ADDR) 824 sc->sc_cfg |= CFG_T64ADDR; 825 #endif 826 827 if (reg & (CFG_TBI_EN | CFG_EXT_125)) { 828 const char *sep = ""; 829 printf("%s: using ", device_xname(sc->sc_dev)); 830 if (reg & CFG_EXT_125) { 831 sc->sc_cfg |= CFG_EXT_125; 832 printf("%s125MHz clock", sep); 833 sep = ", "; 834 } 835 if (reg & CFG_TBI_EN) { 836 sc->sc_cfg |= CFG_TBI_EN; 837 printf("%sten-bit interface", sep); 838 sep = ", "; 839 } 840 printf("\n"); 841 } 842 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 843 (reg & CFG_MRM_DIS) != 0) 844 sc->sc_cfg |= CFG_MRM_DIS; 845 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 846 (reg & CFG_MWI_DIS) != 0) 847 sc->sc_cfg |= CFG_MWI_DIS; 848 849 /* 850 * Use the extended descriptor format on the DP83820. This 851 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 852 * checksumming. 853 */ 854 sc->sc_cfg |= CFG_EXTSTS_EN; 855 } 856 857 static int 858 sipcom_detach(device_t self, int flags) 859 { 860 int s; 861 862 s = splnet(); 863 sipcom_do_detach(self, SIP_ATTACH_FIN); 864 splx(s); 865 866 return 0; 867 } 868 869 static void 870 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 871 { 872 int i; 873 struct sip_softc *sc = device_private(self); 874 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 875 876 /* 877 * Free any resources we've allocated during attach. 878 * Do this in reverse order and fall through. 879 */ 880 switch (stage) { 881 case SIP_ATTACH_FIN: 882 sipcom_stop(ifp, 1); 883 pmf_device_deregister(self); 884 #ifdef SIP_EVENT_COUNTERS 885 /* 886 * Attach event counters. 887 */ 888 evcnt_detach(&sc->sc_ev_txforceintr); 889 evcnt_detach(&sc->sc_ev_txdstall); 890 evcnt_detach(&sc->sc_ev_txsstall); 891 evcnt_detach(&sc->sc_ev_hiberr); 892 evcnt_detach(&sc->sc_ev_rxintr); 893 evcnt_detach(&sc->sc_ev_txiintr); 894 evcnt_detach(&sc->sc_ev_txdintr); 895 if (!sc->sc_gigabit) { 896 evcnt_detach(&sc->sc_ev_rxpause); 897 } else { 898 evcnt_detach(&sc->sc_ev_txudpsum); 899 evcnt_detach(&sc->sc_ev_txtcpsum); 900 evcnt_detach(&sc->sc_ev_txipsum); 901 evcnt_detach(&sc->sc_ev_rxudpsum); 902 evcnt_detach(&sc->sc_ev_rxtcpsum); 903 evcnt_detach(&sc->sc_ev_rxipsum); 904 evcnt_detach(&sc->sc_ev_txpause); 905 evcnt_detach(&sc->sc_ev_rxpause); 906 } 907 #endif /* SIP_EVENT_COUNTERS */ 908 909 rnd_detach_source(&sc->rnd_source); 910 911 ether_ifdetach(ifp); 912 if_detach(ifp); 913 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 914 915 /*FALLTHROUGH*/ 916 case SIP_ATTACH_CREATE_RXMAP: 917 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 918 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 919 bus_dmamap_destroy(sc->sc_dmat, 920 sc->sc_rxsoft[i].rxs_dmamap); 921 } 922 /*FALLTHROUGH*/ 923 case SIP_ATTACH_CREATE_TXMAP: 924 for (i = 0; i < SIP_TXQUEUELEN; i++) { 925 if (sc->sc_txsoft[i].txs_dmamap != NULL) 926 bus_dmamap_destroy(sc->sc_dmat, 927 sc->sc_txsoft[i].txs_dmamap); 928 } 929 /*FALLTHROUGH*/ 930 case SIP_ATTACH_LOAD_MAP: 931 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 932 /*FALLTHROUGH*/ 933 case SIP_ATTACH_CREATE_MAP: 934 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 935 /*FALLTHROUGH*/ 936 case SIP_ATTACH_MAP_MEM: 937 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 938 sizeof(struct sip_control_data)); 939 /*FALLTHROUGH*/ 940 case SIP_ATTACH_ALLOC_MEM: 941 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 942 /* FALLTHROUGH*/ 943 case SIP_ATTACH_INTR: 944 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 945 /* FALLTHROUGH*/ 946 case SIP_ATTACH_MAP: 947 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 948 break; 949 default: 950 break; 951 } 952 return; 953 } 954 955 static bool 956 sipcom_resume(device_t self, const pmf_qual_t *qual) 957 { 958 struct sip_softc *sc = device_private(self); 959 960 return sipcom_reset(sc); 961 } 962 963 static bool 964 sipcom_suspend(device_t self, const pmf_qual_t *qual) 965 { 966 struct sip_softc *sc = device_private(self); 967 968 sipcom_rxdrain(sc); 969 return true; 970 } 971 972 static void 973 sipcom_attach(device_t parent, device_t self, void *aux) 974 { 975 struct sip_softc *sc = device_private(self); 976 struct pci_attach_args *pa = aux; 977 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 978 struct mii_data * const mii = &sc->sc_mii; 979 pci_chipset_tag_t pc = pa->pa_pc; 980 pci_intr_handle_t ih; 981 const char *intrstr = NULL; 982 bus_space_tag_t iot, memt; 983 bus_space_handle_t ioh, memh; 984 bus_size_t iosz, memsz; 985 int ioh_valid, memh_valid; 986 int i, rseg, error; 987 const struct sip_product *sip; 988 uint8_t enaddr[ETHER_ADDR_LEN]; 989 pcireg_t csr; 990 pcireg_t memtype; 991 bus_size_t tx_dmamap_size; 992 int ntxsegs_alloc; 993 cfdata_t cf = device_cfdata(self); 994 char intrbuf[PCI_INTRSTR_LEN]; 995 996 callout_init(&sc->sc_tick_ch, 0); 997 998 sip = sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0); 999 if (sip == NULL) { 1000 aprint_error("\n"); 1001 panic("%s: impossible", __func__); 1002 } 1003 sc->sc_dev = self; 1004 sc->sc_gigabit = sip->sip_gigabit; 1005 pmf_self_suspensor_init(self, &sc->sc_suspensor, &sc->sc_qual); 1006 sc->sc_pc = pc; 1007 1008 if (sc->sc_gigabit) { 1009 sc->sc_rxintr = gsip_rxintr; 1010 sc->sc_parm = &gsip_parm; 1011 } else { 1012 sc->sc_rxintr = sip_rxintr; 1013 sc->sc_parm = &sip_parm; 1014 } 1015 tx_dmamap_size = sc->sc_parm->p_tx_dmamap_size; 1016 ntxsegs_alloc = sc->sc_parm->p_ntxsegs_alloc; 1017 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 1018 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 1019 sc->sc_nrxdesc_mask = sc->sc_parm->p_nrxdesc - 1; 1020 1021 sc->sc_rev = PCI_REVISION(pa->pa_class); 1022 1023 aprint_naive("\n"); 1024 aprint_normal(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 1025 1026 sc->sc_model = sip; 1027 1028 /* 1029 * XXX Work-around broken PXE firmware on some boards. 1030 * 1031 * The DP83815 shares an address decoder with the MEM BAR 1032 * and the ROM BAR. Make sure the ROM BAR is disabled, 1033 * so that memory mapped access works. 1034 */ 1035 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1036 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1037 ~PCI_MAPREG_ROM_ENABLE); 1038 1039 /* 1040 * Map the device. 1041 */ 1042 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 1043 PCI_MAPREG_TYPE_IO, 0, 1044 &iot, &ioh, NULL, &iosz) == 0); 1045 if (sc->sc_gigabit) { 1046 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 1047 switch (memtype) { 1048 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1049 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1050 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1051 memtype, 0, &memt, &memh, NULL, &memsz) == 0); 1052 break; 1053 default: 1054 memh_valid = 0; 1055 } 1056 } else { 1057 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1058 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 1059 &memt, &memh, NULL, &memsz) == 0); 1060 } 1061 1062 if (memh_valid) { 1063 sc->sc_st = memt; 1064 sc->sc_sh = memh; 1065 sc->sc_sz = memsz; 1066 } else if (ioh_valid) { 1067 sc->sc_st = iot; 1068 sc->sc_sh = ioh; 1069 sc->sc_sz = iosz; 1070 } else { 1071 aprint_error_dev(self, "unable to map device registers\n"); 1072 return; 1073 } 1074 1075 sc->sc_dmat = pa->pa_dmat; 1076 1077 /* 1078 * Make sure bus mastering is enabled. Also make sure 1079 * Write/Invalidate is enabled if we're allowed to use it. 1080 */ 1081 csr = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1082 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 1083 csr |= PCI_COMMAND_INVALIDATE_ENABLE; 1084 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1085 csr | PCI_COMMAND_MASTER_ENABLE); 1086 1087 /* Power up chip */ 1088 error = pci_activate(pa->pa_pc, pa->pa_tag, self, pci_activate_null); 1089 if (error != 0 && error != EOPNOTSUPP) { 1090 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 1091 return; 1092 } 1093 1094 /* 1095 * Map and establish our interrupt. 1096 */ 1097 if (pci_intr_map(pa, &ih)) { 1098 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 1099 return; 1100 } 1101 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1102 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, sipcom_intr, sc, 1103 device_xname(self)); 1104 if (sc->sc_ih == NULL) { 1105 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 1106 if (intrstr != NULL) 1107 aprint_error(" at %s", intrstr); 1108 aprint_error("\n"); 1109 sipcom_do_detach(self, SIP_ATTACH_MAP); 1110 return; 1111 } 1112 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1113 1114 SIMPLEQ_INIT(&sc->sc_txfreeq); 1115 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1116 1117 /* 1118 * Allocate the control data structures, and create and load the 1119 * DMA map for it. 1120 */ 1121 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1122 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 1123 &rseg, 0)) != 0) { 1124 aprint_error_dev(sc->sc_dev, 1125 "unable to allocate control data, error = %d\n", error); 1126 sipcom_do_detach(self, SIP_ATTACH_INTR); 1127 return; 1128 } 1129 1130 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 1131 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 1132 BUS_DMA_COHERENT)) != 0) { 1133 aprint_error_dev(sc->sc_dev, 1134 "unable to map control data, error = %d\n", error); 1135 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 1136 } 1137 1138 if ((error = bus_dmamap_create(sc->sc_dmat, 1139 sizeof(struct sip_control_data), 1, 1140 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 1141 aprint_error_dev(self, "unable to create control data DMA map" 1142 ", error = %d\n", error); 1143 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 1144 } 1145 1146 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1147 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 1148 0)) != 0) { 1149 aprint_error_dev(self, "unable to load control data DMA map" 1150 ", error = %d\n", error); 1151 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 1152 } 1153 1154 /* 1155 * Create the transmit buffer DMA maps. 1156 */ 1157 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1158 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 1159 sc->sc_parm->p_ntxsegs, MCLBYTES, 0, 0, 1160 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1161 aprint_error_dev(self, "unable to create tx DMA map %d" 1162 ", error = %d\n", i, error); 1163 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 1164 } 1165 } 1166 1167 /* 1168 * Create the receive buffer DMA maps. 1169 */ 1170 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1171 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1172 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1173 aprint_error_dev(self, "unable to create rx DMA map %d" 1174 ", error = %d\n", i, error); 1175 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 1176 } 1177 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1178 } 1179 1180 /* 1181 * Reset the chip to a known state. 1182 */ 1183 sipcom_reset(sc); 1184 1185 /* 1186 * Read the Ethernet address from the EEPROM. This might 1187 * also fetch other stuff from the EEPROM and stash it 1188 * in the softc. 1189 */ 1190 sc->sc_cfg = 0; 1191 if (!sc->sc_gigabit) { 1192 if (SIP_SIS900_REV(sc, SIS_REV_635) || 1193 SIP_SIS900_REV(sc, SIS_REV_900B)) 1194 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1195 1196 if (SIP_SIS900_REV(sc, SIS_REV_635) || 1197 SIP_SIS900_REV(sc, SIS_REV_960) || 1198 SIP_SIS900_REV(sc, SIS_REV_900B)) 1199 sc->sc_cfg |= 1200 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1201 CFG_EDBMASTEN); 1202 } 1203 1204 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1205 1206 aprint_normal_dev(self, "Ethernet address %s\n",ether_sprintf(enaddr)); 1207 1208 /* 1209 * Initialize the configuration register: aggressive PCI 1210 * bus request algorithm, default backoff, default OW timer, 1211 * default parity error detection. 1212 * 1213 * NOTE: "Big endian mode" is useless on the SiS900 and 1214 * friends -- it affects packet data, not descriptors. 1215 */ 1216 if (sc->sc_gigabit) 1217 sipcom_dp83820_attach(sc, pa); 1218 1219 /* 1220 * Initialize our media structures and probe the MII. 1221 */ 1222 mii->mii_ifp = ifp; 1223 mii->mii_readreg = sip->sip_variant->sipv_mii_readreg; 1224 mii->mii_writereg = sip->sip_variant->sipv_mii_writereg; 1225 mii->mii_statchg = sip->sip_variant->sipv_mii_statchg; 1226 sc->sc_ethercom.ec_mii = mii; 1227 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 1228 sipcom_mediastatus); 1229 1230 /* 1231 * XXX We cannot handle flow control on the DP83815. 1232 */ 1233 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1234 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 1235 MII_OFFSET_ANY, 0); 1236 else 1237 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 1238 MII_OFFSET_ANY, MIIF_DOPAUSE); 1239 if (LIST_FIRST(&mii->mii_phys) == NULL) { 1240 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 1241 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 1242 } else 1243 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1244 1245 ifp = &sc->sc_ethercom.ec_if; 1246 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1247 ifp->if_softc = sc; 1248 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1249 sc->sc_if_flags = ifp->if_flags; 1250 ifp->if_ioctl = sipcom_ioctl; 1251 ifp->if_start = sipcom_start; 1252 ifp->if_watchdog = sipcom_watchdog; 1253 ifp->if_init = sipcom_init; 1254 ifp->if_stop = sipcom_stop; 1255 IFQ_SET_READY(&ifp->if_snd); 1256 1257 /* 1258 * We can support 802.1Q VLAN-sized frames. 1259 */ 1260 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1261 1262 if (sc->sc_gigabit) { 1263 /* 1264 * And the DP83820 can do VLAN tagging in hardware, and 1265 * support the jumbo Ethernet MTU. 1266 */ 1267 sc->sc_ethercom.ec_capabilities |= 1268 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1269 sc->sc_ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 1270 1271 /* 1272 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1273 * in hardware. 1274 */ 1275 ifp->if_capabilities |= 1276 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1277 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1278 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1279 } 1280 1281 /* 1282 * Attach the interface. 1283 */ 1284 if_attach(ifp); 1285 if_deferred_start_init(ifp, NULL); 1286 ether_ifattach(ifp, enaddr); 1287 ether_set_ifflags_cb(&sc->sc_ethercom, sip_ifflags_cb); 1288 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1289 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1290 sc->sc_prev.if_capenable = ifp->if_capenable; 1291 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 1292 RND_TYPE_NET, RND_FLAG_DEFAULT); 1293 1294 /* 1295 * The number of bytes that must be available in 1296 * the Tx FIFO before the bus master can DMA more 1297 * data into the FIFO. 1298 */ 1299 sc->sc_tx_fill_thresh = 64 / 32; 1300 1301 /* 1302 * Start at a drain threshold of 512 bytes. We will 1303 * increase it if a DMA underrun occurs. 1304 * 1305 * XXX The minimum value of this variable should be 1306 * tuned. We may be able to improve performance 1307 * by starting with a lower value. That, however, 1308 * may trash the first few outgoing packets if the 1309 * PCI bus is saturated. 1310 */ 1311 if (sc->sc_gigabit) 1312 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1313 else 1314 sc->sc_tx_drain_thresh = 1504 / 32; 1315 1316 /* 1317 * Initialize the Rx FIFO drain threshold. 1318 * 1319 * This is in units of 8 bytes. 1320 * 1321 * We should never set this value lower than 2; 14 bytes are 1322 * required to filter the packet. 1323 */ 1324 sc->sc_rx_drain_thresh = 128 / 8; 1325 1326 #ifdef SIP_EVENT_COUNTERS 1327 /* 1328 * Attach event counters. 1329 */ 1330 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1331 NULL, device_xname(sc->sc_dev), "txsstall"); 1332 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1333 NULL, device_xname(sc->sc_dev), "txdstall"); 1334 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1335 NULL, device_xname(sc->sc_dev), "txforceintr"); 1336 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1337 NULL, device_xname(sc->sc_dev), "txdintr"); 1338 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1339 NULL, device_xname(sc->sc_dev), "txiintr"); 1340 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1341 NULL, device_xname(sc->sc_dev), "rxintr"); 1342 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1343 NULL, device_xname(sc->sc_dev), "hiberr"); 1344 if (!sc->sc_gigabit) { 1345 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1346 NULL, device_xname(sc->sc_dev), "rxpause"); 1347 } else { 1348 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1349 NULL, device_xname(sc->sc_dev), "rxpause"); 1350 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1351 NULL, device_xname(sc->sc_dev), "txpause"); 1352 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1353 NULL, device_xname(sc->sc_dev), "rxipsum"); 1354 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1355 NULL, device_xname(sc->sc_dev), "rxtcpsum"); 1356 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1357 NULL, device_xname(sc->sc_dev), "rxudpsum"); 1358 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1359 NULL, device_xname(sc->sc_dev), "txipsum"); 1360 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1361 NULL, device_xname(sc->sc_dev), "txtcpsum"); 1362 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1363 NULL, device_xname(sc->sc_dev), "txudpsum"); 1364 } 1365 #endif /* SIP_EVENT_COUNTERS */ 1366 1367 if (pmf_device_register(self, sipcom_suspend, sipcom_resume)) 1368 pmf_class_network_register(self, ifp); 1369 else 1370 aprint_error_dev(self, "couldn't establish power handler\n"); 1371 } 1372 1373 static inline void 1374 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1375 uint64_t capenable) 1376 { 1377 uint32_t extsts; 1378 #ifdef DEBUG 1379 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1380 #endif 1381 /* 1382 * If VLANs are enabled and the packet has a VLAN tag, set 1383 * up the descriptor to encapsulate the packet for us. 1384 * 1385 * This apparently has to be on the last descriptor of 1386 * the packet. 1387 */ 1388 1389 /* 1390 * Byte swapping is tricky. We need to provide the tag 1391 * in a network byte order. On a big-endian machine, 1392 * the byteorder is correct, but we need to swap it 1393 * anyway, because this will be undone by the outside 1394 * htole32(). That's why there must be an 1395 * unconditional swap instead of htons() inside. 1396 */ 1397 if (vlan_has_tag(m0)) { 1398 sc->sc_txdescs[lasttx].sipd_extsts |= 1399 htole32(EXTSTS_VPKT | 1400 (bswap16(vlan_get_tag(m0)) & 1401 EXTSTS_VTCI)); 1402 } 1403 1404 /* 1405 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1406 * checksumming, set up the descriptor to do this work 1407 * for us. 1408 * 1409 * This apparently has to be on the first descriptor of 1410 * the packet. 1411 * 1412 * Byte-swap constants so the compiler can optimize. 1413 */ 1414 extsts = 0; 1415 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1416 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1417 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1418 extsts |= htole32(EXTSTS_IPPKT); 1419 } 1420 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1421 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1422 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1423 extsts |= htole32(EXTSTS_TCPPKT); 1424 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1425 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1426 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1427 extsts |= htole32(EXTSTS_UDPPKT); 1428 } 1429 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1430 } 1431 1432 /* 1433 * sip_start: [ifnet interface function] 1434 * 1435 * Start packet transmission on the interface. 1436 */ 1437 static void 1438 sipcom_start(struct ifnet *ifp) 1439 { 1440 struct sip_softc *sc = ifp->if_softc; 1441 struct mbuf *m0; 1442 struct mbuf *m; 1443 struct sip_txsoft *txs; 1444 bus_dmamap_t dmamap; 1445 int error, nexttx, lasttx, seg; 1446 int ofree = sc->sc_txfree; 1447 #if 0 1448 int firsttx = sc->sc_txnext; 1449 #endif 1450 1451 /* 1452 * If we've been told to pause, don't transmit any more packets. 1453 */ 1454 if (!sc->sc_gigabit && sc->sc_paused) 1455 ifp->if_flags |= IFF_OACTIVE; 1456 1457 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1458 return; 1459 1460 /* 1461 * Loop through the send queue, setting up transmit descriptors 1462 * until we drain the queue, or use up all available transmit 1463 * descriptors. 1464 */ 1465 for (;;) { 1466 /* Get a work queue entry. */ 1467 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1468 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1469 break; 1470 } 1471 1472 /* 1473 * Grab a packet off the queue. 1474 */ 1475 IFQ_POLL(&ifp->if_snd, m0); 1476 if (m0 == NULL) 1477 break; 1478 m = NULL; 1479 1480 dmamap = txs->txs_dmamap; 1481 1482 /* 1483 * Load the DMA map. If this fails, the packet either 1484 * didn't fit in the alloted number of segments, or we 1485 * were short on resources. 1486 */ 1487 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1488 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1489 /* In the non-gigabit case, we'll copy and try again. */ 1490 if (error != 0 && !sc->sc_gigabit) { 1491 MGETHDR(m, M_DONTWAIT, MT_DATA); 1492 if (m == NULL) { 1493 printf("%s: unable to allocate Tx mbuf\n", 1494 device_xname(sc->sc_dev)); 1495 break; 1496 } 1497 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1498 if (m0->m_pkthdr.len > MHLEN) { 1499 MCLGET(m, M_DONTWAIT); 1500 if ((m->m_flags & M_EXT) == 0) { 1501 printf("%s: unable to allocate Tx " 1502 "cluster\n", 1503 device_xname(sc->sc_dev)); 1504 m_freem(m); 1505 break; 1506 } 1507 } 1508 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1509 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1510 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1511 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1512 if (error) { 1513 printf("%s: unable to load Tx buffer, error = " 1514 "%d\n", device_xname(sc->sc_dev), error); 1515 break; 1516 } 1517 } else if (error == EFBIG) { 1518 /* 1519 * For the too-many-segments case, we simply 1520 * report an error and drop the packet, 1521 * since we can't sanely copy a jumbo packet 1522 * to a single buffer. 1523 */ 1524 printf("%s: Tx packet consumes too many DMA segments, " 1525 "dropping...\n", device_xname(sc->sc_dev)); 1526 IFQ_DEQUEUE(&ifp->if_snd, m0); 1527 m_freem(m0); 1528 continue; 1529 } else if (error != 0) { 1530 /* 1531 * Short on resources, just stop for now. 1532 */ 1533 break; 1534 } 1535 1536 /* 1537 * Ensure we have enough descriptors free to describe 1538 * the packet. Note, we always reserve one descriptor 1539 * at the end of the ring as a termination point, to 1540 * prevent wrap-around. 1541 */ 1542 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1543 /* 1544 * Not enough free descriptors to transmit this 1545 * packet. We haven't committed anything yet, 1546 * so just unload the DMA map, put the packet 1547 * back on the queue, and punt. Notify the upper 1548 * layer that there are not more slots left. 1549 * 1550 * XXX We could allocate an mbuf and copy, but 1551 * XXX is it worth it? 1552 */ 1553 ifp->if_flags |= IFF_OACTIVE; 1554 bus_dmamap_unload(sc->sc_dmat, dmamap); 1555 if (m != NULL) 1556 m_freem(m); 1557 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1558 break; 1559 } 1560 1561 IFQ_DEQUEUE(&ifp->if_snd, m0); 1562 if (m != NULL) { 1563 m_freem(m0); 1564 m0 = m; 1565 } 1566 1567 /* 1568 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1569 */ 1570 1571 /* Sync the DMA map. */ 1572 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1573 BUS_DMASYNC_PREWRITE); 1574 1575 /* 1576 * Initialize the transmit descriptors. 1577 */ 1578 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1579 seg < dmamap->dm_nsegs; 1580 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1581 /* 1582 * If this is the first descriptor we're 1583 * enqueueing, don't set the OWN bit just 1584 * yet. That could cause a race condition. 1585 * We'll do it below. 1586 */ 1587 *sipd_bufptr(sc, &sc->sc_txdescs[nexttx]) = 1588 htole32(dmamap->dm_segs[seg].ds_addr); 1589 *sipd_cmdsts(sc, &sc->sc_txdescs[nexttx]) = 1590 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) 1591 | CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1592 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1593 lasttx = nexttx; 1594 } 1595 1596 /* Clear the MORE bit on the last segment. */ 1597 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) &= 1598 htole32(~CMDSTS_MORE); 1599 1600 /* 1601 * If we're in the interrupt delay window, delay the 1602 * interrupt. 1603 */ 1604 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1605 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1606 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) |= 1607 htole32(CMDSTS_INTR); 1608 sc->sc_txwin = 0; 1609 } 1610 1611 if (sc->sc_gigabit) 1612 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1613 1614 /* Sync the descriptors we're using. */ 1615 sip_cdtxsync(sc, sc->sc_txnext, dmamap->dm_nsegs, 1616 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1617 1618 /* 1619 * The entire packet is set up. Give the first descrptor 1620 * to the chip now. 1621 */ 1622 *sipd_cmdsts(sc, &sc->sc_txdescs[sc->sc_txnext]) |= 1623 htole32(CMDSTS_OWN); 1624 sip_cdtxsync(sc, sc->sc_txnext, 1, 1625 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1626 1627 /* 1628 * Store a pointer to the packet so we can free it later, 1629 * and remember what txdirty will be once the packet is 1630 * done. 1631 */ 1632 txs->txs_mbuf = m0; 1633 txs->txs_firstdesc = sc->sc_txnext; 1634 txs->txs_lastdesc = lasttx; 1635 1636 /* Advance the tx pointer. */ 1637 sc->sc_txfree -= dmamap->dm_nsegs; 1638 sc->sc_txnext = nexttx; 1639 1640 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1641 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1642 1643 /* Pass the packet to any BPF listeners. */ 1644 bpf_mtap(ifp, m0, BPF_D_OUT); 1645 } 1646 1647 if (txs == NULL || sc->sc_txfree == 0) { 1648 /* No more slots left; notify upper layer. */ 1649 ifp->if_flags |= IFF_OACTIVE; 1650 } 1651 1652 if (sc->sc_txfree != ofree) { 1653 /* 1654 * Start the transmit process. Note, the manual says 1655 * that if there are no pending transmissions in the 1656 * chip's internal queue (indicated by TXE being clear), 1657 * then the driver software must set the TXDP to the 1658 * first descriptor to be transmitted. However, if we 1659 * do this, it causes serious performance degredation on 1660 * the DP83820 under load, not setting TXDP doesn't seem 1661 * to adversely affect the SiS 900 or DP83815. 1662 * 1663 * Well, I guess it wouldn't be the first time a manual 1664 * has lied -- and they could be speaking of the NULL- 1665 * terminated descriptor list case, rather than OWN- 1666 * terminated rings. 1667 */ 1668 #if 0 1669 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1670 CR_TXE) == 0) { 1671 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1672 SIP_CDTXADDR(sc, firsttx)); 1673 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1674 } 1675 #else 1676 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1677 #endif 1678 1679 /* Set a watchdog timer in case the chip flakes out. */ 1680 /* Gigabit autonegotiation takes 5 seconds. */ 1681 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1682 } 1683 } 1684 1685 /* 1686 * sip_watchdog: [ifnet interface function] 1687 * 1688 * Watchdog timer handler. 1689 */ 1690 static void 1691 sipcom_watchdog(struct ifnet *ifp) 1692 { 1693 struct sip_softc *sc = ifp->if_softc; 1694 1695 /* 1696 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1697 * If we get a timeout, try and sweep up transmit descriptors. 1698 * If we manage to sweep them all up, ignore the lack of 1699 * interrupt. 1700 */ 1701 sipcom_txintr(sc); 1702 1703 if (sc->sc_txfree != sc->sc_ntxdesc) { 1704 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1705 ifp->if_oerrors++; 1706 1707 /* Reset the interface. */ 1708 (void) sipcom_init(ifp); 1709 } else if (ifp->if_flags & IFF_DEBUG) 1710 printf("%s: recovered from device timeout\n", 1711 device_xname(sc->sc_dev)); 1712 1713 /* Try to get more packets going. */ 1714 sipcom_start(ifp); 1715 } 1716 1717 /* If the interface is up and running, only modify the receive 1718 * filter when setting promiscuous or debug mode. Otherwise fall 1719 * through to ether_ioctl, which will reset the chip. 1720 */ 1721 static int 1722 sip_ifflags_cb(struct ethercom *ec) 1723 { 1724 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1725 == (sc)->sc_ethercom.ec_capenable) \ 1726 && ((sc)->sc_prev.is_vlan == \ 1727 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1728 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1729 struct ifnet *ifp = &ec->ec_if; 1730 struct sip_softc *sc = ifp->if_softc; 1731 int change = ifp->if_flags ^ sc->sc_if_flags; 1732 1733 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0 || !COMPARE_EC(sc) || 1734 !COMPARE_IC(sc, ifp)) 1735 return ENETRESET; 1736 /* Set up the receive filter. */ 1737 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1738 return 0; 1739 } 1740 1741 /* 1742 * sip_ioctl: [ifnet interface function] 1743 * 1744 * Handle control requests from the operator. 1745 */ 1746 static int 1747 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1748 { 1749 struct sip_softc *sc = ifp->if_softc; 1750 struct ifreq *ifr = (struct ifreq *)data; 1751 int s, error; 1752 1753 s = splnet(); 1754 1755 switch (cmd) { 1756 case SIOCSIFMEDIA: 1757 /* Flow control requires full-duplex mode. */ 1758 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1759 (ifr->ifr_media & IFM_FDX) == 0) 1760 ifr->ifr_media &= ~IFM_ETH_FMASK; 1761 1762 /* XXX */ 1763 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1764 ifr->ifr_media &= ~IFM_ETH_FMASK; 1765 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1766 if (sc->sc_gigabit && 1767 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1768 /* We can do both TXPAUSE and RXPAUSE. */ 1769 ifr->ifr_media |= 1770 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1771 } else if (ifr->ifr_media & IFM_FLOW) { 1772 /* 1773 * Both TXPAUSE and RXPAUSE must be set. 1774 * (SiS900 and DP83815 don't have PAUSE_ASYM 1775 * feature.) 1776 * 1777 * XXX Can SiS900 and DP83815 send PAUSE? 1778 */ 1779 ifr->ifr_media |= 1780 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1781 } 1782 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1783 } 1784 /*FALLTHROUGH*/ 1785 default: 1786 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1787 break; 1788 1789 error = 0; 1790 1791 if (cmd == SIOCSIFCAP) 1792 error = (*ifp->if_init)(ifp); 1793 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1794 ; 1795 else if (ifp->if_flags & IFF_RUNNING) { 1796 /* 1797 * Multicast list has changed; set the hardware filter 1798 * accordingly. 1799 */ 1800 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1801 } 1802 break; 1803 } 1804 1805 /* Try to get more packets going. */ 1806 sipcom_start(ifp); 1807 1808 sc->sc_if_flags = ifp->if_flags; 1809 splx(s); 1810 return error; 1811 } 1812 1813 /* 1814 * sip_intr: 1815 * 1816 * Interrupt service routine. 1817 */ 1818 static int 1819 sipcom_intr(void *arg) 1820 { 1821 struct sip_softc *sc = arg; 1822 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1823 uint32_t isr; 1824 int handled = 0; 1825 1826 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 1827 return 0; 1828 1829 /* Disable interrupts. */ 1830 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1831 1832 for (;;) { 1833 /* Reading clears interrupt. */ 1834 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1835 if ((isr & sc->sc_imr) == 0) 1836 break; 1837 1838 rnd_add_uint32(&sc->rnd_source, isr); 1839 1840 handled = 1; 1841 1842 if ((ifp->if_flags & IFF_RUNNING) == 0) 1843 break; 1844 1845 if (isr & (ISR_RXORN | ISR_RXIDLE | ISR_RXDESC)) { 1846 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1847 1848 /* Grab any new packets. */ 1849 (*sc->sc_rxintr)(sc); 1850 1851 if (isr & ISR_RXORN) { 1852 printf("%s: receive FIFO overrun\n", 1853 device_xname(sc->sc_dev)); 1854 1855 /* XXX adjust rx_drain_thresh? */ 1856 } 1857 1858 if (isr & ISR_RXIDLE) { 1859 printf("%s: receive ring overrun\n", 1860 device_xname(sc->sc_dev)); 1861 1862 /* Get the receive process going again. */ 1863 bus_space_write_4(sc->sc_st, sc->sc_sh, 1864 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1865 bus_space_write_4(sc->sc_st, sc->sc_sh, 1866 SIP_CR, CR_RXE); 1867 } 1868 } 1869 1870 if (isr & (ISR_TXURN | ISR_TXDESC | ISR_TXIDLE)) { 1871 #ifdef SIP_EVENT_COUNTERS 1872 if (isr & ISR_TXDESC) 1873 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1874 else if (isr & ISR_TXIDLE) 1875 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1876 #endif 1877 1878 /* Sweep up transmit descriptors. */ 1879 sipcom_txintr(sc); 1880 1881 if (isr & ISR_TXURN) { 1882 uint32_t thresh; 1883 int txfifo_size = (sc->sc_gigabit) 1884 ? DP83820_SIP_TXFIFO_SIZE 1885 : OTHER_SIP_TXFIFO_SIZE; 1886 1887 printf("%s: transmit FIFO underrun", 1888 device_xname(sc->sc_dev)); 1889 thresh = sc->sc_tx_drain_thresh + 1; 1890 if (thresh <= __SHIFTOUT_MASK(sc->sc_bits.b_txcfg_drth_mask) 1891 && (thresh * 32) <= (txfifo_size - 1892 (sc->sc_tx_fill_thresh * 32))) { 1893 printf("; increasing Tx drain " 1894 "threshold to %u bytes\n", 1895 thresh * 32); 1896 sc->sc_tx_drain_thresh = thresh; 1897 (void) sipcom_init(ifp); 1898 } else { 1899 (void) sipcom_init(ifp); 1900 printf("\n"); 1901 } 1902 } 1903 } 1904 1905 if (sc->sc_imr & (ISR_PAUSE_END | ISR_PAUSE_ST)) { 1906 if (isr & ISR_PAUSE_ST) { 1907 sc->sc_paused = 1; 1908 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1909 ifp->if_flags |= IFF_OACTIVE; 1910 } 1911 if (isr & ISR_PAUSE_END) { 1912 sc->sc_paused = 0; 1913 ifp->if_flags &= ~IFF_OACTIVE; 1914 } 1915 } 1916 1917 if (isr & ISR_HIBERR) { 1918 int want_init = 0; 1919 1920 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1921 1922 #define PRINTERR(bit, str) \ 1923 do { \ 1924 if ((isr & (bit)) != 0) { \ 1925 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1926 printf("%s: %s\n", \ 1927 device_xname(sc->sc_dev), str); \ 1928 want_init = 1; \ 1929 } \ 1930 } while (/*CONSTCOND*/0) 1931 1932 PRINTERR(sc->sc_bits.b_isr_dperr, "parity error"); 1933 PRINTERR(sc->sc_bits.b_isr_sserr, "system error"); 1934 PRINTERR(sc->sc_bits.b_isr_rmabt, "master abort"); 1935 PRINTERR(sc->sc_bits.b_isr_rtabt, "target abort"); 1936 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1937 /* 1938 * Ignore: 1939 * Tx reset complete 1940 * Rx reset complete 1941 */ 1942 if (want_init) 1943 (void) sipcom_init(ifp); 1944 #undef PRINTERR 1945 } 1946 } 1947 1948 /* Re-enable interrupts. */ 1949 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1950 1951 /* Try to get more packets going. */ 1952 if_schedule_deferred_start(ifp); 1953 1954 return handled; 1955 } 1956 1957 /* 1958 * sip_txintr: 1959 * 1960 * Helper; handle transmit interrupts. 1961 */ 1962 static void 1963 sipcom_txintr(struct sip_softc *sc) 1964 { 1965 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1966 struct sip_txsoft *txs; 1967 uint32_t cmdsts; 1968 1969 if (sc->sc_paused == 0) 1970 ifp->if_flags &= ~IFF_OACTIVE; 1971 1972 /* 1973 * Go through our Tx list and free mbufs for those 1974 * frames which have been transmitted. 1975 */ 1976 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1977 sip_cdtxsync(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1978 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1979 1980 cmdsts = le32toh(*sipd_cmdsts(sc, 1981 &sc->sc_txdescs[txs->txs_lastdesc])); 1982 if (cmdsts & CMDSTS_OWN) 1983 break; 1984 1985 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1986 1987 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1988 1989 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1990 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1991 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1992 m_freem(txs->txs_mbuf); 1993 txs->txs_mbuf = NULL; 1994 1995 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1996 1997 /* Check for errors and collisions. */ 1998 if (cmdsts & (CMDSTS_Tx_TXA | CMDSTS_Tx_TFU | CMDSTS_Tx_ED | 1999 CMDSTS_Tx_EC)) { 2000 ifp->if_oerrors++; 2001 if (cmdsts & CMDSTS_Tx_EC) 2002 ifp->if_collisions += 16; 2003 if (ifp->if_flags & IFF_DEBUG) { 2004 if (cmdsts & CMDSTS_Tx_ED) 2005 printf("%s: excessive deferral\n", 2006 device_xname(sc->sc_dev)); 2007 if (cmdsts & CMDSTS_Tx_EC) 2008 printf("%s: excessive collisions\n", 2009 device_xname(sc->sc_dev)); 2010 } 2011 } else { 2012 /* Packet was transmitted successfully. */ 2013 ifp->if_opackets++; 2014 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 2015 } 2016 } 2017 2018 /* 2019 * If there are no more pending transmissions, cancel the watchdog 2020 * timer. 2021 */ 2022 if (txs == NULL) { 2023 ifp->if_timer = 0; 2024 sc->sc_txwin = 0; 2025 } 2026 } 2027 2028 /* 2029 * gsip_rxintr: 2030 * 2031 * Helper; handle receive interrupts on gigabit parts. 2032 */ 2033 static void 2034 gsip_rxintr(struct sip_softc *sc) 2035 { 2036 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2037 struct sip_rxsoft *rxs; 2038 struct mbuf *m; 2039 uint32_t cmdsts, extsts; 2040 int i, len; 2041 2042 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2043 rxs = &sc->sc_rxsoft[i]; 2044 2045 sip_cdrxsync(sc, i, 2046 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2047 2048 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2049 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 2050 len = CMDSTS_SIZE(sc, cmdsts); 2051 2052 /* 2053 * NOTE: OWN is set if owned by _consumer_. We're the 2054 * consumer of the receive ring, so if the bit is clear, 2055 * we have processed all of the packets. 2056 */ 2057 if ((cmdsts & CMDSTS_OWN) == 0) { 2058 /* 2059 * We have processed all of the receive buffers. 2060 */ 2061 break; 2062 } 2063 2064 if (__predict_false(sc->sc_rxdiscard)) { 2065 sip_init_rxdesc(sc, i); 2066 if ((cmdsts & CMDSTS_MORE) == 0) { 2067 /* Reset our state. */ 2068 sc->sc_rxdiscard = 0; 2069 } 2070 continue; 2071 } 2072 2073 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2074 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2075 2076 m = rxs->rxs_mbuf; 2077 2078 /* 2079 * Add a new receive buffer to the ring. 2080 */ 2081 if (sipcom_add_rxbuf(sc, i) != 0) { 2082 /* 2083 * Failed, throw away what we've done so 2084 * far, and discard the rest of the packet. 2085 */ 2086 ifp->if_ierrors++; 2087 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2088 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2089 sip_init_rxdesc(sc, i); 2090 if (cmdsts & CMDSTS_MORE) 2091 sc->sc_rxdiscard = 1; 2092 if (sc->sc_rxhead != NULL) 2093 m_freem(sc->sc_rxhead); 2094 sip_rxchain_reset(sc); 2095 continue; 2096 } 2097 2098 sip_rxchain_link(sc, m); 2099 2100 m->m_len = len; 2101 2102 /* 2103 * If this is not the end of the packet, keep 2104 * looking. 2105 */ 2106 if (cmdsts & CMDSTS_MORE) { 2107 sc->sc_rxlen += len; 2108 continue; 2109 } 2110 2111 /* 2112 * Okay, we have the entire packet now. The chip includes 2113 * the FCS, so we need to trim it. 2114 */ 2115 m->m_len -= ETHER_CRC_LEN; 2116 2117 *sc->sc_rxtailp = NULL; 2118 len = m->m_len + sc->sc_rxlen; 2119 m = sc->sc_rxhead; 2120 2121 sip_rxchain_reset(sc); 2122 2123 /* If an error occurred, update stats and drop the packet. */ 2124 if (cmdsts & (CMDSTS_Rx_RXA | CMDSTS_Rx_RUNT | 2125 CMDSTS_Rx_ISE | CMDSTS_Rx_CRCE | CMDSTS_Rx_FAE)) { 2126 ifp->if_ierrors++; 2127 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2128 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2129 /* Receive overrun handled elsewhere. */ 2130 printf("%s: receive descriptor error\n", 2131 device_xname(sc->sc_dev)); 2132 } 2133 #define PRINTERR(bit, str) \ 2134 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2135 (cmdsts & (bit)) != 0) \ 2136 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2137 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2138 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2139 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2140 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2141 #undef PRINTERR 2142 m_freem(m); 2143 continue; 2144 } 2145 2146 /* 2147 * If the packet is small enough to fit in a 2148 * single header mbuf, allocate one and copy 2149 * the data into it. This greatly reduces 2150 * memory consumption when we receive lots 2151 * of small packets. 2152 */ 2153 if (gsip_copy_small != 0 && len <= (MHLEN - 2)) { 2154 struct mbuf *nm; 2155 MGETHDR(nm, M_DONTWAIT, MT_DATA); 2156 if (nm == NULL) { 2157 ifp->if_ierrors++; 2158 m_freem(m); 2159 continue; 2160 } 2161 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2162 nm->m_data += 2; 2163 nm->m_pkthdr.len = nm->m_len = len; 2164 m_copydata(m, 0, len, mtod(nm, void *)); 2165 m_freem(m); 2166 m = nm; 2167 } 2168 #ifndef __NO_STRICT_ALIGNMENT 2169 else { 2170 /* 2171 * The DP83820's receive buffers must be 4-byte 2172 * aligned. But this means that the data after 2173 * the Ethernet header is misaligned. To compensate, 2174 * we have artificially shortened the buffer size 2175 * in the descriptor, and we do an overlapping copy 2176 * of the data two bytes further in (in the first 2177 * buffer of the chain only). 2178 */ 2179 memmove(mtod(m, char *) + 2, mtod(m, void *), 2180 m->m_len); 2181 m->m_data += 2; 2182 } 2183 #endif /* ! __NO_STRICT_ALIGNMENT */ 2184 2185 /* 2186 * If VLANs are enabled, VLAN packets have been unwrapped 2187 * for us. Associate the tag with the packet. 2188 */ 2189 2190 /* 2191 * Again, byte swapping is tricky. Hardware provided 2192 * the tag in the network byte order, but extsts was 2193 * passed through le32toh() in the meantime. On a 2194 * big-endian machine, we need to swap it again. On a 2195 * little-endian machine, we need to convert from the 2196 * network to host byte order. This means that we must 2197 * swap it in any case, so unconditional swap instead 2198 * of htons() is used. 2199 */ 2200 if ((extsts & EXTSTS_VPKT) != 0) { 2201 vlan_set_tag(m, bswap16(extsts & EXTSTS_VTCI)); 2202 } 2203 2204 /* 2205 * Set the incoming checksum information for the 2206 * packet. 2207 */ 2208 if ((extsts & EXTSTS_IPPKT) != 0) { 2209 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2210 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2211 if (extsts & EXTSTS_Rx_IPERR) 2212 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2213 if (extsts & EXTSTS_TCPPKT) { 2214 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2215 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2216 if (extsts & EXTSTS_Rx_TCPERR) 2217 m->m_pkthdr.csum_flags |= 2218 M_CSUM_TCP_UDP_BAD; 2219 } else if (extsts & EXTSTS_UDPPKT) { 2220 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2221 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2222 if (extsts & EXTSTS_Rx_UDPERR) 2223 m->m_pkthdr.csum_flags |= 2224 M_CSUM_TCP_UDP_BAD; 2225 } 2226 } 2227 2228 m_set_rcvif(m, ifp); 2229 m->m_pkthdr.len = len; 2230 2231 /* Pass it on. */ 2232 if_percpuq_enqueue(ifp->if_percpuq, m); 2233 } 2234 2235 /* Update the receive pointer. */ 2236 sc->sc_rxptr = i; 2237 } 2238 2239 /* 2240 * sip_rxintr: 2241 * 2242 * Helper; handle receive interrupts on 10/100 parts. 2243 */ 2244 static void 2245 sip_rxintr(struct sip_softc *sc) 2246 { 2247 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2248 struct sip_rxsoft *rxs; 2249 struct mbuf *m; 2250 uint32_t cmdsts; 2251 int i, len; 2252 2253 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2254 rxs = &sc->sc_rxsoft[i]; 2255 2256 sip_cdrxsync(sc, i, 2257 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2258 2259 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2260 2261 /* 2262 * NOTE: OWN is set if owned by _consumer_. We're the 2263 * consumer of the receive ring, so if the bit is clear, 2264 * we have processed all of the packets. 2265 */ 2266 if ((cmdsts & CMDSTS_OWN) == 0) { 2267 /* 2268 * We have processed all of the receive buffers. 2269 */ 2270 break; 2271 } 2272 2273 /* If any collisions were seen on the wire, count one. */ 2274 if (cmdsts & CMDSTS_Rx_COL) 2275 ifp->if_collisions++; 2276 2277 /* 2278 * If an error occurred, update stats, clear the status 2279 * word, and leave the packet buffer in place. It will 2280 * simply be reused the next time the ring comes around. 2281 */ 2282 if (cmdsts & (CMDSTS_Rx_RXA | CMDSTS_Rx_RUNT | 2283 CMDSTS_Rx_ISE | CMDSTS_Rx_CRCE | CMDSTS_Rx_FAE)) { 2284 ifp->if_ierrors++; 2285 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2286 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2287 /* Receive overrun handled elsewhere. */ 2288 printf("%s: receive descriptor error\n", 2289 device_xname(sc->sc_dev)); 2290 } 2291 #define PRINTERR(bit, str) \ 2292 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2293 (cmdsts & (bit)) != 0) \ 2294 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2295 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2296 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2297 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2298 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2299 #undef PRINTERR 2300 sip_init_rxdesc(sc, i); 2301 continue; 2302 } 2303 2304 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2305 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2306 2307 /* 2308 * No errors; receive the packet. Note, the SiS 900 2309 * includes the CRC with every packet. 2310 */ 2311 len = CMDSTS_SIZE(sc, cmdsts) - ETHER_CRC_LEN; 2312 2313 #ifdef __NO_STRICT_ALIGNMENT 2314 /* 2315 * If the packet is small enough to fit in a 2316 * single header mbuf, allocate one and copy 2317 * the data into it. This greatly reduces 2318 * memory consumption when we receive lots 2319 * of small packets. 2320 * 2321 * Otherwise, we add a new buffer to the receive 2322 * chain. If this fails, we drop the packet and 2323 * recycle the old buffer. 2324 */ 2325 if (sip_copy_small != 0 && len <= MHLEN) { 2326 MGETHDR(m, M_DONTWAIT, MT_DATA); 2327 if (m == NULL) 2328 goto dropit; 2329 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2330 memcpy(mtod(m, void *), 2331 mtod(rxs->rxs_mbuf, void *), len); 2332 sip_init_rxdesc(sc, i); 2333 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2334 rxs->rxs_dmamap->dm_mapsize, 2335 BUS_DMASYNC_PREREAD); 2336 } else { 2337 m = rxs->rxs_mbuf; 2338 if (sipcom_add_rxbuf(sc, i) != 0) { 2339 dropit: 2340 ifp->if_ierrors++; 2341 sip_init_rxdesc(sc, i); 2342 bus_dmamap_sync(sc->sc_dmat, 2343 rxs->rxs_dmamap, 0, 2344 rxs->rxs_dmamap->dm_mapsize, 2345 BUS_DMASYNC_PREREAD); 2346 continue; 2347 } 2348 } 2349 #else 2350 /* 2351 * The SiS 900's receive buffers must be 4-byte aligned. 2352 * But this means that the data after the Ethernet header 2353 * is misaligned. We must allocate a new buffer and 2354 * copy the data, shifted forward 2 bytes. 2355 */ 2356 MGETHDR(m, M_DONTWAIT, MT_DATA); 2357 if (m == NULL) { 2358 dropit: 2359 ifp->if_ierrors++; 2360 sip_init_rxdesc(sc, i); 2361 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2362 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2363 continue; 2364 } 2365 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2366 if (len > (MHLEN - 2)) { 2367 MCLGET(m, M_DONTWAIT); 2368 if ((m->m_flags & M_EXT) == 0) { 2369 m_freem(m); 2370 goto dropit; 2371 } 2372 } 2373 m->m_data += 2; 2374 2375 /* 2376 * Note that we use clusters for incoming frames, so the 2377 * buffer is virtually contiguous. 2378 */ 2379 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2380 2381 /* Allow the receive descriptor to continue using its mbuf. */ 2382 sip_init_rxdesc(sc, i); 2383 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2384 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2385 #endif /* __NO_STRICT_ALIGNMENT */ 2386 2387 m_set_rcvif(m, ifp); 2388 m->m_pkthdr.len = m->m_len = len; 2389 2390 /* Pass it on. */ 2391 if_percpuq_enqueue(ifp->if_percpuq, m); 2392 } 2393 2394 /* Update the receive pointer. */ 2395 sc->sc_rxptr = i; 2396 } 2397 2398 /* 2399 * sip_tick: 2400 * 2401 * One second timer, used to tick the MII. 2402 */ 2403 static void 2404 sipcom_tick(void *arg) 2405 { 2406 struct sip_softc *sc = arg; 2407 int s; 2408 2409 s = splnet(); 2410 #ifdef SIP_EVENT_COUNTERS 2411 if (sc->sc_gigabit) { 2412 /* Read PAUSE related counts from MIB registers. */ 2413 sc->sc_ev_rxpause.ev_count += 2414 bus_space_read_4(sc->sc_st, sc->sc_sh, 2415 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2416 sc->sc_ev_txpause.ev_count += 2417 bus_space_read_4(sc->sc_st, sc->sc_sh, 2418 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2419 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2420 } 2421 #endif /* SIP_EVENT_COUNTERS */ 2422 mii_tick(&sc->sc_mii); 2423 splx(s); 2424 2425 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2426 } 2427 2428 /* 2429 * sip_reset: 2430 * 2431 * Perform a soft reset on the SiS 900. 2432 */ 2433 static bool 2434 sipcom_reset(struct sip_softc *sc) 2435 { 2436 bus_space_tag_t st = sc->sc_st; 2437 bus_space_handle_t sh = sc->sc_sh; 2438 int i; 2439 2440 bus_space_write_4(st, sh, SIP_IER, 0); 2441 bus_space_write_4(st, sh, SIP_IMR, 0); 2442 bus_space_write_4(st, sh, SIP_RFCR, 0); 2443 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2444 2445 for (i = 0; i < SIP_TIMEOUT; i++) { 2446 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2447 break; 2448 delay(2); 2449 } 2450 2451 if (i == SIP_TIMEOUT) { 2452 printf("%s: reset failed to complete\n", 2453 device_xname(sc->sc_dev)); 2454 return false; 2455 } 2456 2457 delay(1000); 2458 2459 if (sc->sc_gigabit) { 2460 /* 2461 * Set the general purpose I/O bits. Do it here in case we 2462 * need to have GPIO set up to talk to the media interface. 2463 */ 2464 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2465 delay(1000); 2466 } 2467 return true; 2468 } 2469 2470 static void 2471 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2472 { 2473 uint32_t reg; 2474 bus_space_tag_t st = sc->sc_st; 2475 bus_space_handle_t sh = sc->sc_sh; 2476 /* 2477 * Initialize the VLAN/IP receive control register. 2478 * We enable checksum computation on all incoming 2479 * packets, and do not reject packets w/ bad checksums. 2480 */ 2481 reg = 0; 2482 if (capenable & 2483 (IFCAP_CSUM_IPv4_Rx | IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 2484 reg |= VRCR_IPEN; 2485 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2486 reg |= VRCR_VTDEN | VRCR_VTREN; 2487 bus_space_write_4(st, sh, SIP_VRCR, reg); 2488 2489 /* 2490 * Initialize the VLAN/IP transmit control register. 2491 * We enable outgoing checksum computation on a 2492 * per-packet basis. 2493 */ 2494 reg = 0; 2495 if (capenable & 2496 (IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx)) 2497 reg |= VTCR_PPCHK; 2498 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2499 reg |= VTCR_VPPTI; 2500 bus_space_write_4(st, sh, SIP_VTCR, reg); 2501 2502 /* 2503 * If we're using VLANs, initialize the VLAN data register. 2504 * To understand why we bswap the VLAN Ethertype, see section 2505 * 4.2.36 of the DP83820 manual. 2506 */ 2507 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2508 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2509 } 2510 2511 /* 2512 * sip_init: [ ifnet interface function ] 2513 * 2514 * Initialize the interface. Must be called at splnet(). 2515 */ 2516 static int 2517 sipcom_init(struct ifnet *ifp) 2518 { 2519 struct sip_softc *sc = ifp->if_softc; 2520 bus_space_tag_t st = sc->sc_st; 2521 bus_space_handle_t sh = sc->sc_sh; 2522 struct sip_txsoft *txs; 2523 struct sip_rxsoft *rxs; 2524 struct sip_desc *sipd; 2525 int i, error = 0; 2526 2527 if (device_is_active(sc->sc_dev)) { 2528 /* 2529 * Cancel any pending I/O. 2530 */ 2531 sipcom_stop(ifp, 0); 2532 } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 2533 !device_is_active(sc->sc_dev)) 2534 return 0; 2535 2536 /* 2537 * Reset the chip to a known state. 2538 */ 2539 if (!sipcom_reset(sc)) 2540 return EBUSY; 2541 2542 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2543 /* 2544 * DP83815 manual, page 78: 2545 * 4.4 Recommended Registers Configuration 2546 * For optimum performance of the DP83815, version noted 2547 * as DP83815CVNG (SRR = 203h), the listed register 2548 * modifications must be followed in sequence... 2549 * 2550 * It's not clear if this should be 302h or 203h because that 2551 * chip name is listed as SRR 302h in the description of the 2552 * SRR register. However, my revision 302h DP83815 on the 2553 * Netgear FA311 purchased in 02/2001 needs these settings 2554 * to avoid tons of errors in AcceptPerfectMatch (non- 2555 * IFF_PROMISC) mode. I do not know if other revisions need 2556 * this set or not. [briggs -- 09 March 2001] 2557 * 2558 * Note that only the low-order 12 bits of 0xe4 are documented 2559 * and that this sets reserved bits in that register. 2560 */ 2561 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2562 2563 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2564 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2565 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2566 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2567 2568 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2569 } 2570 2571 /* 2572 * Initialize the transmit descriptor ring. 2573 */ 2574 for (i = 0; i < sc->sc_ntxdesc; i++) { 2575 sipd = &sc->sc_txdescs[i]; 2576 memset(sipd, 0, sizeof(struct sip_desc)); 2577 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, sip_nexttx(sc, i))); 2578 } 2579 sip_cdtxsync(sc, 0, sc->sc_ntxdesc, 2580 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2581 sc->sc_txfree = sc->sc_ntxdesc; 2582 sc->sc_txnext = 0; 2583 sc->sc_txwin = 0; 2584 2585 /* 2586 * Initialize the transmit job descriptors. 2587 */ 2588 SIMPLEQ_INIT(&sc->sc_txfreeq); 2589 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2590 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2591 txs = &sc->sc_txsoft[i]; 2592 txs->txs_mbuf = NULL; 2593 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2594 } 2595 2596 /* 2597 * Initialize the receive descriptor and receive job 2598 * descriptor rings. 2599 */ 2600 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2601 rxs = &sc->sc_rxsoft[i]; 2602 if (rxs->rxs_mbuf == NULL) { 2603 if ((error = sipcom_add_rxbuf(sc, i)) != 0) { 2604 printf("%s: unable to allocate or map rx " 2605 "buffer %d, error = %d\n", 2606 device_xname(sc->sc_dev), i, error); 2607 /* 2608 * XXX Should attempt to run with fewer receive 2609 * XXX buffers instead of just failing. 2610 */ 2611 sipcom_rxdrain(sc); 2612 goto out; 2613 } 2614 } else 2615 sip_init_rxdesc(sc, i); 2616 } 2617 sc->sc_rxptr = 0; 2618 sc->sc_rxdiscard = 0; 2619 sip_rxchain_reset(sc); 2620 2621 /* 2622 * Set the configuration register; it's already initialized 2623 * in sip_attach(). 2624 */ 2625 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2626 2627 /* 2628 * Initialize the prototype TXCFG register. 2629 */ 2630 if (sc->sc_gigabit) { 2631 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2632 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2633 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2634 SIP_SIS900_REV(sc, SIS_REV_960) || 2635 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2636 (sc->sc_cfg & CFG_EDBMASTEN)) { 2637 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_64; 2638 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_64; 2639 } else { 2640 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2641 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2642 } 2643 2644 sc->sc_txcfg |= TXCFG_ATP | 2645 __SHIFTIN(sc->sc_tx_fill_thresh, sc->sc_bits.b_txcfg_flth_mask) | 2646 sc->sc_tx_drain_thresh; 2647 bus_space_write_4(st, sh, sc->sc_regs.r_txcfg, sc->sc_txcfg); 2648 2649 /* 2650 * Initialize the receive drain threshold if we have never 2651 * done so. 2652 */ 2653 if (sc->sc_rx_drain_thresh == 0) { 2654 /* 2655 * XXX This value should be tuned. This is set to the 2656 * maximum of 248 bytes, and we may be able to improve 2657 * performance by decreasing it (although we should never 2658 * set this value lower than 2; 14 bytes are required to 2659 * filter the packet). 2660 */ 2661 sc->sc_rx_drain_thresh = __SHIFTOUT_MASK(RXCFG_DRTH_MASK); 2662 } 2663 2664 /* 2665 * Initialize the prototype RXCFG register. 2666 */ 2667 sc->sc_rxcfg |= __SHIFTIN(sc->sc_rx_drain_thresh, RXCFG_DRTH_MASK); 2668 /* 2669 * Accept long packets (including FCS) so we can handle 2670 * 802.1q-tagged frames and jumbo frames properly. 2671 */ 2672 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2673 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2674 sc->sc_rxcfg |= RXCFG_ALP; 2675 2676 /* 2677 * Checksum offloading is disabled if the user selects an MTU 2678 * larger than 8109. (FreeBSD says 8152, but there is emperical 2679 * evidence that >8109 does not work on some boards, such as the 2680 * Planex GN-1000TE). 2681 */ 2682 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2683 (ifp->if_capenable & 2684 (IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2685 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2686 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx))) { 2687 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2688 "disabled.\n", device_xname(sc->sc_dev)); 2689 ifp->if_capenable &= 2690 ~(IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2691 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2692 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx); 2693 ifp->if_csum_flags_tx = 0; 2694 ifp->if_csum_flags_rx = 0; 2695 } 2696 2697 bus_space_write_4(st, sh, sc->sc_regs.r_rxcfg, sc->sc_rxcfg); 2698 2699 if (sc->sc_gigabit) 2700 sipcom_dp83820_init(sc, ifp->if_capenable); 2701 2702 /* 2703 * Give the transmit and receive rings to the chip. 2704 */ 2705 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2706 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2707 2708 /* 2709 * Initialize the interrupt mask. 2710 */ 2711 sc->sc_imr = sc->sc_bits.b_isr_dperr | 2712 sc->sc_bits.b_isr_sserr | 2713 sc->sc_bits.b_isr_rmabt | 2714 sc->sc_bits.b_isr_rtabt | 2715 ISR_RXSOVR | ISR_TXURN | ISR_TXDESC | ISR_TXIDLE | ISR_RXORN | 2716 ISR_RXIDLE | ISR_RXDESC; 2717 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2718 2719 /* Set up the receive filter. */ 2720 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2721 2722 /* 2723 * Tune sc_rx_flow_thresh. 2724 * XXX "More than 8KB" is too short for jumbo frames. 2725 * XXX TODO: Threshold value should be user-settable. 2726 */ 2727 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2728 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2729 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2730 2731 /* 2732 * Set the current media. Do this after initializing the prototype 2733 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2734 * control. 2735 */ 2736 if ((error = ether_mediachange(ifp)) != 0) 2737 goto out; 2738 2739 /* 2740 * Set the interrupt hold-off timer to 100us. 2741 */ 2742 if (sc->sc_gigabit) 2743 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2744 2745 /* 2746 * Enable interrupts. 2747 */ 2748 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2749 2750 /* 2751 * Start the transmit and receive processes. 2752 */ 2753 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2754 2755 /* 2756 * Start the one second MII clock. 2757 */ 2758 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2759 2760 /* 2761 * ...all done! 2762 */ 2763 ifp->if_flags |= IFF_RUNNING; 2764 ifp->if_flags &= ~IFF_OACTIVE; 2765 sc->sc_if_flags = ifp->if_flags; 2766 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2767 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2768 sc->sc_prev.if_capenable = ifp->if_capenable; 2769 2770 out: 2771 if (error) 2772 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 2773 return error; 2774 } 2775 2776 /* 2777 * sip_drain: 2778 * 2779 * Drain the receive queue. 2780 */ 2781 static void 2782 sipcom_rxdrain(struct sip_softc *sc) 2783 { 2784 struct sip_rxsoft *rxs; 2785 int i; 2786 2787 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2788 rxs = &sc->sc_rxsoft[i]; 2789 if (rxs->rxs_mbuf != NULL) { 2790 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2791 m_freem(rxs->rxs_mbuf); 2792 rxs->rxs_mbuf = NULL; 2793 } 2794 } 2795 } 2796 2797 /* 2798 * sip_stop: [ ifnet interface function ] 2799 * 2800 * Stop transmission on the interface. 2801 */ 2802 static void 2803 sipcom_stop(struct ifnet *ifp, int disable) 2804 { 2805 struct sip_softc *sc = ifp->if_softc; 2806 bus_space_tag_t st = sc->sc_st; 2807 bus_space_handle_t sh = sc->sc_sh; 2808 struct sip_txsoft *txs; 2809 uint32_t cmdsts = 0; /* DEBUG */ 2810 2811 /* 2812 * Stop the one second clock. 2813 */ 2814 callout_stop(&sc->sc_tick_ch); 2815 2816 /* Down the MII. */ 2817 mii_down(&sc->sc_mii); 2818 2819 if (device_is_active(sc->sc_dev)) { 2820 /* 2821 * Disable interrupts. 2822 */ 2823 bus_space_write_4(st, sh, SIP_IER, 0); 2824 2825 /* 2826 * Stop receiver and transmitter. 2827 */ 2828 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2829 } 2830 2831 /* 2832 * Release any queued transmit buffers. 2833 */ 2834 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2835 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2836 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2837 (le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])) & 2838 CMDSTS_INTR) == 0) 2839 printf("%s: sip_stop: last descriptor does not " 2840 "have INTR bit set\n", device_xname(sc->sc_dev)); 2841 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2842 #ifdef DIAGNOSTIC 2843 if (txs->txs_mbuf == NULL) { 2844 printf("%s: dirty txsoft with no mbuf chain\n", 2845 device_xname(sc->sc_dev)); 2846 panic("sip_stop"); 2847 } 2848 #endif 2849 cmdsts |= /* DEBUG */ 2850 le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 2851 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2852 m_freem(txs->txs_mbuf); 2853 txs->txs_mbuf = NULL; 2854 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2855 } 2856 2857 /* 2858 * Mark the interface down and cancel the watchdog timer. 2859 */ 2860 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2861 ifp->if_timer = 0; 2862 2863 if (disable) 2864 pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); 2865 2866 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2867 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2868 printf("%s: sip_stop: no INTR bits set in dirty tx " 2869 "descriptors\n", device_xname(sc->sc_dev)); 2870 } 2871 2872 /* 2873 * sip_read_eeprom: 2874 * 2875 * Read data from the serial EEPROM. 2876 */ 2877 static void 2878 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2879 uint16_t *data) 2880 { 2881 bus_space_tag_t st = sc->sc_st; 2882 bus_space_handle_t sh = sc->sc_sh; 2883 uint16_t reg; 2884 int i, x; 2885 2886 for (i = 0; i < wordcnt; i++) { 2887 /* Send CHIP SELECT. */ 2888 reg = EROMAR_EECS; 2889 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2890 2891 /* Shift in the READ opcode. */ 2892 for (x = 3; x > 0; x--) { 2893 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2894 reg |= EROMAR_EEDI; 2895 else 2896 reg &= ~EROMAR_EEDI; 2897 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2898 bus_space_write_4(st, sh, SIP_EROMAR, 2899 reg | EROMAR_EESK); 2900 delay(4); 2901 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2902 delay(4); 2903 } 2904 2905 /* Shift in address. */ 2906 for (x = 6; x > 0; x--) { 2907 if ((word + i) & (1 << (x - 1))) 2908 reg |= EROMAR_EEDI; 2909 else 2910 reg &= ~EROMAR_EEDI; 2911 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2912 bus_space_write_4(st, sh, SIP_EROMAR, 2913 reg | EROMAR_EESK); 2914 delay(4); 2915 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2916 delay(4); 2917 } 2918 2919 /* Shift out data. */ 2920 reg = EROMAR_EECS; 2921 data[i] = 0; 2922 for (x = 16; x > 0; x--) { 2923 bus_space_write_4(st, sh, SIP_EROMAR, 2924 reg | EROMAR_EESK); 2925 delay(4); 2926 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2927 data[i] |= (1 << (x - 1)); 2928 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2929 delay(4); 2930 } 2931 2932 /* Clear CHIP SELECT. */ 2933 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2934 delay(4); 2935 } 2936 } 2937 2938 /* 2939 * sipcom_add_rxbuf: 2940 * 2941 * Add a receive buffer to the indicated descriptor. 2942 */ 2943 static int 2944 sipcom_add_rxbuf(struct sip_softc *sc, int idx) 2945 { 2946 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2947 struct mbuf *m; 2948 int error; 2949 2950 MGETHDR(m, M_DONTWAIT, MT_DATA); 2951 if (m == NULL) 2952 return ENOBUFS; 2953 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2954 2955 MCLGET(m, M_DONTWAIT); 2956 if ((m->m_flags & M_EXT) == 0) { 2957 m_freem(m); 2958 return ENOBUFS; 2959 } 2960 2961 /* XXX I don't believe this is necessary. --dyoung */ 2962 if (sc->sc_gigabit) 2963 m->m_len = sc->sc_parm->p_rxbuf_len; 2964 2965 if (rxs->rxs_mbuf != NULL) 2966 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2967 2968 rxs->rxs_mbuf = m; 2969 2970 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2971 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2972 BUS_DMA_READ | BUS_DMA_NOWAIT); 2973 if (error) { 2974 printf("%s: can't load rx DMA map %d, error = %d\n", 2975 device_xname(sc->sc_dev), idx, error); 2976 panic("%s", __func__); /* XXX */ 2977 } 2978 2979 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2980 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2981 2982 sip_init_rxdesc(sc, idx); 2983 2984 return 0; 2985 } 2986 2987 /* 2988 * sip_sis900_set_filter: 2989 * 2990 * Set up the receive filter. 2991 */ 2992 static void 2993 sipcom_sis900_set_filter(struct sip_softc *sc) 2994 { 2995 bus_space_tag_t st = sc->sc_st; 2996 bus_space_handle_t sh = sc->sc_sh; 2997 struct ethercom *ec = &sc->sc_ethercom; 2998 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2999 struct ether_multi *enm; 3000 const uint8_t *cp; 3001 struct ether_multistep step; 3002 uint32_t crc, mchash[16]; 3003 3004 /* 3005 * Initialize the prototype RFCR. 3006 */ 3007 sc->sc_rfcr = RFCR_RFEN; 3008 if (ifp->if_flags & IFF_BROADCAST) 3009 sc->sc_rfcr |= RFCR_AAB; 3010 if (ifp->if_flags & IFF_PROMISC) { 3011 sc->sc_rfcr |= RFCR_AAP; 3012 goto allmulti; 3013 } 3014 3015 /* 3016 * Set up the multicast address filter by passing all multicast 3017 * addresses through a CRC generator, and then using the high-order 3018 * 6 bits as an index into the 128 bit multicast hash table (only 3019 * the lower 16 bits of each 32 bit multicast hash register are 3020 * valid). The high order bits select the register, while the 3021 * rest of the bits select the bit within the register. 3022 */ 3023 3024 memset(mchash, 0, sizeof(mchash)); 3025 3026 /* 3027 * SiS900 (at least SiS963) requires us to register the address of 3028 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 3029 */ 3030 crc = 0x0ed423f9; 3031 3032 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3033 SIP_SIS900_REV(sc, SIS_REV_960) || 3034 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3035 /* Just want the 8 most significant bits. */ 3036 crc >>= 24; 3037 } else { 3038 /* Just want the 7 most significant bits. */ 3039 crc >>= 25; 3040 } 3041 3042 /* Set the corresponding bit in the hash table. */ 3043 mchash[crc >> 4] |= 1 << (crc & 0xf); 3044 3045 ETHER_LOCK(ec); 3046 ETHER_FIRST_MULTI(step, ec, enm); 3047 while (enm != NULL) { 3048 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3049 /* 3050 * We must listen to a range of multicast addresses. 3051 * For now, just accept all multicasts, rather than 3052 * trying to set only those filter bits needed to match 3053 * the range. (At this time, the only use of address 3054 * ranges is for IP multicast routing, for which the 3055 * range is big enough to require all bits set.) 3056 */ 3057 ETHER_UNLOCK(ec); 3058 goto allmulti; 3059 } 3060 3061 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3062 3063 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3064 SIP_SIS900_REV(sc, SIS_REV_960) || 3065 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3066 /* Just want the 8 most significant bits. */ 3067 crc >>= 24; 3068 } else { 3069 /* Just want the 7 most significant bits. */ 3070 crc >>= 25; 3071 } 3072 3073 /* Set the corresponding bit in the hash table. */ 3074 mchash[crc >> 4] |= 1 << (crc & 0xf); 3075 3076 ETHER_NEXT_MULTI(step, enm); 3077 } 3078 ETHER_UNLOCK(ec); 3079 3080 ifp->if_flags &= ~IFF_ALLMULTI; 3081 goto setit; 3082 3083 allmulti: 3084 ifp->if_flags |= IFF_ALLMULTI; 3085 sc->sc_rfcr |= RFCR_AAM; 3086 3087 setit: 3088 #define FILTER_EMIT(addr, data) \ 3089 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3090 delay(1); \ 3091 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3092 delay(1) 3093 3094 /* 3095 * Disable receive filter, and program the node address. 3096 */ 3097 cp = CLLADDR(ifp->if_sadl); 3098 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 3099 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 3100 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 3101 3102 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3103 /* 3104 * Program the multicast hash table. 3105 */ 3106 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 3107 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 3108 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 3109 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 3110 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 3111 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 3112 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 3113 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 3114 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3115 SIP_SIS900_REV(sc, SIS_REV_960) || 3116 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3117 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 3118 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 3119 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 3120 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 3121 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 3122 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 3123 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 3124 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 3125 } 3126 } 3127 #undef FILTER_EMIT 3128 3129 /* 3130 * Re-enable the receiver filter. 3131 */ 3132 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3133 } 3134 3135 /* 3136 * sip_dp83815_set_filter: 3137 * 3138 * Set up the receive filter. 3139 */ 3140 static void 3141 sipcom_dp83815_set_filter(struct sip_softc *sc) 3142 { 3143 bus_space_tag_t st = sc->sc_st; 3144 bus_space_handle_t sh = sc->sc_sh; 3145 struct ethercom *ec = &sc->sc_ethercom; 3146 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3147 struct ether_multi *enm; 3148 const uint8_t *cp; 3149 struct ether_multistep step; 3150 uint32_t crc, hash, slot, bit; 3151 #define MCHASH_NWORDS_83820 128 3152 #define MCHASH_NWORDS_83815 32 3153 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3154 uint16_t mchash[MCHASH_NWORDS]; 3155 int i; 3156 3157 /* 3158 * Initialize the prototype RFCR. 3159 * Enable the receive filter, and accept on 3160 * Perfect (destination address) Match 3161 * If IFF_BROADCAST, also accept all broadcast packets. 3162 * If IFF_PROMISC, accept all unicast packets (and later, set 3163 * IFF_ALLMULTI and accept all multicast, too). 3164 */ 3165 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3166 if (ifp->if_flags & IFF_BROADCAST) 3167 sc->sc_rfcr |= RFCR_AAB; 3168 if (ifp->if_flags & IFF_PROMISC) { 3169 sc->sc_rfcr |= RFCR_AAP; 3170 goto allmulti; 3171 } 3172 3173 /* 3174 * Set up the DP83820/DP83815 multicast address filter by 3175 * passing all multicast addresses through a CRC generator, 3176 * and then using the high-order 11/9 bits as an index into 3177 * the 2048/512 bit multicast hash table. The high-order 3178 * 7/5 bits select the slot, while the low-order 4 bits 3179 * select the bit within the slot. Note that only the low 3180 * 16-bits of each filter word are used, and there are 3181 * 128/32 filter words. 3182 */ 3183 3184 memset(mchash, 0, sizeof(mchash)); 3185 3186 ifp->if_flags &= ~IFF_ALLMULTI; 3187 ETHER_FIRST_MULTI(step, ec, enm); 3188 if (enm == NULL) 3189 goto setit; 3190 while (enm != NULL) { 3191 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3192 /* 3193 * We must listen to a range of multicast addresses. 3194 * For now, just accept all multicasts, rather than 3195 * trying to set only those filter bits needed to match 3196 * the range. (At this time, the only use of address 3197 * ranges is for IP multicast routing, for which the 3198 * range is big enough to require all bits set.) 3199 */ 3200 goto allmulti; 3201 } 3202 3203 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3204 3205 if (sc->sc_gigabit) { 3206 /* Just want the 11 most significant bits. */ 3207 hash = crc >> 21; 3208 } else { 3209 /* Just want the 9 most significant bits. */ 3210 hash = crc >> 23; 3211 } 3212 3213 slot = hash >> 4; 3214 bit = hash & 0xf; 3215 3216 /* Set the corresponding bit in the hash table. */ 3217 mchash[slot] |= 1 << bit; 3218 3219 ETHER_NEXT_MULTI(step, enm); 3220 } 3221 sc->sc_rfcr |= RFCR_MHEN; 3222 goto setit; 3223 3224 allmulti: 3225 ifp->if_flags |= IFF_ALLMULTI; 3226 sc->sc_rfcr |= RFCR_AAM; 3227 3228 setit: 3229 #define FILTER_EMIT(addr, data) \ 3230 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3231 delay(1); \ 3232 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3233 delay(1) 3234 3235 /* 3236 * Disable receive filter, and program the node address. 3237 */ 3238 cp = CLLADDR(ifp->if_sadl); 3239 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3240 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3241 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3242 3243 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3244 int nwords = 3245 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3246 /* 3247 * Program the multicast hash table. 3248 */ 3249 for (i = 0; i < nwords; i++) { 3250 FILTER_EMIT(sc->sc_parm->p_filtmem + (i * 2), mchash[i]); 3251 } 3252 } 3253 #undef FILTER_EMIT 3254 #undef MCHASH_NWORDS 3255 #undef MCHASH_NWORDS_83815 3256 #undef MCHASH_NWORDS_83820 3257 3258 /* 3259 * Re-enable the receiver filter. 3260 */ 3261 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3262 } 3263 3264 /* 3265 * sip_dp83820_mii_readreg: [mii interface function] 3266 * 3267 * Read a PHY register on the MII of the DP83820. 3268 */ 3269 static int 3270 sipcom_dp83820_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3271 { 3272 struct sip_softc *sc = device_private(self); 3273 3274 if (sc->sc_cfg & CFG_TBI_EN) { 3275 bus_addr_t tbireg; 3276 3277 if (phy != 0) 3278 return -1; 3279 3280 switch (reg) { 3281 case MII_BMCR: tbireg = SIP_TBICR; break; 3282 case MII_BMSR: tbireg = SIP_TBISR; break; 3283 case MII_ANAR: tbireg = SIP_TANAR; break; 3284 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3285 case MII_ANER: tbireg = SIP_TANER; break; 3286 case MII_EXTSR: 3287 /* 3288 * Don't even bother reading the TESR register. 3289 * The manual documents that the device has 3290 * 1000baseX full/half capability, but the 3291 * register itself seems read back 0 on some 3292 * boards. Just hard-code the result. 3293 */ 3294 *val = (EXTSR_1000XFDX | EXTSR_1000XHDX); 3295 return 0; 3296 3297 default: 3298 return 0; 3299 } 3300 3301 *val = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3302 if (tbireg == SIP_TBISR) { 3303 /* LINK and ACOMP are switched! */ 3304 int sr = *val; 3305 3306 *val = 0; 3307 if (sr & TBISR_MR_LINK_STATUS) 3308 *val |= BMSR_LINK; 3309 if (sr & TBISR_MR_AN_COMPLETE) 3310 *val |= BMSR_ACOMP; 3311 3312 /* 3313 * The manual claims this register reads back 0 3314 * on hard and soft reset. But we want to let 3315 * the gentbi driver know that we support auto- 3316 * negotiation, so hard-code this bit in the 3317 * result. 3318 */ 3319 *val |= BMSR_ANEG | BMSR_EXTSTAT; 3320 } 3321 3322 return 0; 3323 } 3324 3325 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg, 3326 val); 3327 } 3328 3329 /* 3330 * sip_dp83820_mii_writereg: [mii interface function] 3331 * 3332 * Write a PHY register on the MII of the DP83820. 3333 */ 3334 static int 3335 sipcom_dp83820_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3336 { 3337 struct sip_softc *sc = device_private(self); 3338 3339 if (sc->sc_cfg & CFG_TBI_EN) { 3340 bus_addr_t tbireg; 3341 3342 if (phy != 0) 3343 return -1; 3344 3345 switch (reg) { 3346 case MII_BMCR: tbireg = SIP_TBICR; break; 3347 case MII_ANAR: tbireg = SIP_TANAR; break; 3348 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3349 default: 3350 return 0; 3351 } 3352 3353 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3354 return 0; 3355 } 3356 3357 return mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, 3358 val); 3359 } 3360 3361 /* 3362 * sip_dp83820_mii_statchg: [mii interface function] 3363 * 3364 * Callback from MII layer when media changes. 3365 */ 3366 static void 3367 sipcom_dp83820_mii_statchg(struct ifnet *ifp) 3368 { 3369 struct sip_softc *sc = ifp->if_softc; 3370 struct mii_data *mii = &sc->sc_mii; 3371 uint32_t cfg, pcr; 3372 3373 /* 3374 * Get flow control negotiation result. 3375 */ 3376 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3377 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3378 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3379 mii->mii_media_active &= ~IFM_ETH_FMASK; 3380 } 3381 3382 /* 3383 * Update TXCFG for full-duplex operation. 3384 */ 3385 if ((mii->mii_media_active & IFM_FDX) != 0) 3386 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3387 else 3388 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3389 3390 /* 3391 * Update RXCFG for full-duplex or loopback. 3392 */ 3393 if ((mii->mii_media_active & IFM_FDX) != 0 || 3394 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3395 sc->sc_rxcfg |= RXCFG_ATX; 3396 else 3397 sc->sc_rxcfg &= ~RXCFG_ATX; 3398 3399 /* 3400 * Update CFG for MII/GMII. 3401 */ 3402 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3403 cfg = sc->sc_cfg | CFG_MODE_1000; 3404 else 3405 cfg = sc->sc_cfg; 3406 3407 /* 3408 * 802.3x flow control. 3409 */ 3410 pcr = 0; 3411 if (sc->sc_flowflags & IFM_FLOW) { 3412 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3413 pcr |= sc->sc_rx_flow_thresh; 3414 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3415 pcr |= PCR_PSEN | PCR_PS_MCAST; 3416 } 3417 3418 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3419 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3420 sc->sc_txcfg); 3421 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3422 sc->sc_rxcfg); 3423 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3424 } 3425 3426 /* 3427 * sip_mii_bitbang_read: [mii bit-bang interface function] 3428 * 3429 * Read the MII serial port for the MII bit-bang module. 3430 */ 3431 static uint32_t 3432 sipcom_mii_bitbang_read(device_t self) 3433 { 3434 struct sip_softc *sc = device_private(self); 3435 3436 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3437 } 3438 3439 /* 3440 * sip_mii_bitbang_write: [mii big-bang interface function] 3441 * 3442 * Write the MII serial port for the MII bit-bang module. 3443 */ 3444 static void 3445 sipcom_mii_bitbang_write(device_t self, uint32_t val) 3446 { 3447 struct sip_softc *sc = device_private(self); 3448 3449 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3450 } 3451 3452 /* 3453 * sip_sis900_mii_readreg: [mii interface function] 3454 * 3455 * Read a PHY register on the MII. 3456 */ 3457 static int 3458 sipcom_sis900_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3459 { 3460 struct sip_softc *sc = device_private(self); 3461 uint32_t enphy; 3462 3463 /* 3464 * The PHY of recent SiS chipsets is accessed through bitbang 3465 * operations. 3466 */ 3467 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3468 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3469 phy, reg, val); 3470 3471 #ifndef SIS900_MII_RESTRICT 3472 /* 3473 * The SiS 900 has only an internal PHY on the MII. Only allow 3474 * MII address 0. 3475 */ 3476 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3477 return -1; 3478 #endif 3479 3480 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3481 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3482 ENPHY_RWCMD | ENPHY_ACCESS); 3483 do { 3484 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3485 } while (enphy & ENPHY_ACCESS); 3486 3487 *val = (enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT; 3488 return 0; 3489 } 3490 3491 /* 3492 * sip_sis900_mii_writereg: [mii interface function] 3493 * 3494 * Write a PHY register on the MII. 3495 */ 3496 static int 3497 sipcom_sis900_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3498 { 3499 struct sip_softc *sc = device_private(self); 3500 uint32_t enphy; 3501 3502 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3503 return mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3504 phy, reg, val); 3505 } 3506 3507 #ifndef SIS900_MII_RESTRICT 3508 /* 3509 * The SiS 900 has only an internal PHY on the MII. Only allow 3510 * MII address 0. 3511 */ 3512 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3513 return -1; 3514 #endif 3515 3516 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3517 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3518 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3519 do { 3520 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3521 } while (enphy & ENPHY_ACCESS); 3522 3523 return 0; 3524 } 3525 3526 /* 3527 * sip_sis900_mii_statchg: [mii interface function] 3528 * 3529 * Callback from MII layer when media changes. 3530 */ 3531 static void 3532 sipcom_sis900_mii_statchg(struct ifnet *ifp) 3533 { 3534 struct sip_softc *sc = ifp->if_softc; 3535 struct mii_data *mii = &sc->sc_mii; 3536 uint32_t flowctl; 3537 3538 /* 3539 * Get flow control negotiation result. 3540 */ 3541 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3542 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3543 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3544 mii->mii_media_active &= ~IFM_ETH_FMASK; 3545 } 3546 3547 /* 3548 * Update TXCFG for full-duplex operation. 3549 */ 3550 if ((mii->mii_media_active & IFM_FDX) != 0) 3551 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3552 else 3553 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3554 3555 /* 3556 * Update RXCFG for full-duplex or loopback. 3557 */ 3558 if ((mii->mii_media_active & IFM_FDX) != 0 || 3559 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3560 sc->sc_rxcfg |= RXCFG_ATX; 3561 else 3562 sc->sc_rxcfg &= ~RXCFG_ATX; 3563 3564 /* 3565 * Update IMR for use of 802.3x flow control. 3566 */ 3567 if (sc->sc_flowflags & IFM_FLOW) { 3568 sc->sc_imr |= (ISR_PAUSE_END | ISR_PAUSE_ST); 3569 flowctl = FLOWCTL_FLOWEN; 3570 } else { 3571 sc->sc_imr &= ~(ISR_PAUSE_END | ISR_PAUSE_ST); 3572 flowctl = 0; 3573 } 3574 3575 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3576 sc->sc_txcfg); 3577 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3578 sc->sc_rxcfg); 3579 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3580 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3581 } 3582 3583 /* 3584 * sip_dp83815_mii_readreg: [mii interface function] 3585 * 3586 * Read a PHY register on the MII. 3587 */ 3588 static int 3589 sipcom_dp83815_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3590 { 3591 struct sip_softc *sc = device_private(self); 3592 uint32_t data; 3593 3594 /* 3595 * The DP83815 only has an internal PHY. Only allow 3596 * MII address 0. 3597 */ 3598 if (phy != 0) 3599 return -1; 3600 3601 /* 3602 * Apparently, after a reset, the DP83815 can take a while 3603 * to respond. During this recovery period, the BMSR returns 3604 * a value of 0. Catch this -- it's not supposed to happen 3605 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3606 * PHY to come back to life. 3607 * 3608 * This works out because the BMSR is the first register 3609 * read during the PHY probe process. 3610 */ 3611 do { 3612 data = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3613 } while (reg == MII_BMSR && data == 0); 3614 3615 *val = data & 0xffff; 3616 return 0; 3617 } 3618 3619 /* 3620 * sip_dp83815_mii_writereg: [mii interface function] 3621 * 3622 * Write a PHY register to the MII. 3623 */ 3624 static int 3625 sipcom_dp83815_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3626 { 3627 struct sip_softc *sc = device_private(self); 3628 3629 /* 3630 * The DP83815 only has an internal PHY. Only allow 3631 * MII address 0. 3632 */ 3633 if (phy != 0) 3634 return -1; 3635 3636 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3637 3638 return 0; 3639 } 3640 3641 /* 3642 * sip_dp83815_mii_statchg: [mii interface function] 3643 * 3644 * Callback from MII layer when media changes. 3645 */ 3646 static void 3647 sipcom_dp83815_mii_statchg(struct ifnet *ifp) 3648 { 3649 struct sip_softc *sc = ifp->if_softc; 3650 3651 /* 3652 * Update TXCFG for full-duplex operation. 3653 */ 3654 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3655 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3656 else 3657 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3658 3659 /* 3660 * Update RXCFG for full-duplex or loopback. 3661 */ 3662 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3663 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3664 sc->sc_rxcfg |= RXCFG_ATX; 3665 else 3666 sc->sc_rxcfg &= ~RXCFG_ATX; 3667 3668 /* 3669 * XXX 802.3x flow control. 3670 */ 3671 3672 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3673 sc->sc_txcfg); 3674 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3675 sc->sc_rxcfg); 3676 3677 /* 3678 * Some DP83815s experience problems when used with short 3679 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3680 * sequence adjusts the DSP's signal attenuation to fix the 3681 * problem. 3682 */ 3683 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3684 uint32_t reg; 3685 3686 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3687 3688 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3689 reg &= 0x0fff; 3690 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3691 delay(100); 3692 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3693 reg &= 0x00ff; 3694 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3695 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3696 0x00e8); 3697 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3698 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3699 reg | 0x20); 3700 } 3701 3702 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3703 } 3704 } 3705 3706 static void 3707 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3708 const struct pci_attach_args *pa, uint8_t *enaddr) 3709 { 3710 uint16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3711 uint8_t cksum, *e, match; 3712 int i; 3713 3714 /* 3715 * EEPROM data format for the DP83820 can be found in 3716 * the DP83820 manual, section 4.2.4. 3717 */ 3718 3719 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3720 3721 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3722 match = ~(match - 1); 3723 3724 cksum = 0x55; 3725 e = (uint8_t *)eeprom_data; 3726 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3727 cksum += *e++; 3728 3729 if (cksum != match) 3730 printf("%s: Checksum (%x) mismatch (%x)", 3731 device_xname(sc->sc_dev), cksum, match); 3732 3733 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3734 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3735 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3736 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3737 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3738 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3739 } 3740 3741 static void 3742 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3743 { 3744 int i; 3745 3746 /* 3747 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3748 * a reason, but I don't know it. 3749 */ 3750 for (i = 0; i < 10; i++) 3751 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3752 } 3753 3754 static void 3755 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3756 const struct pci_attach_args *pa, uint8_t *enaddr) 3757 { 3758 uint16_t myea[ETHER_ADDR_LEN / 2]; 3759 3760 switch (sc->sc_rev) { 3761 case SIS_REV_630S: 3762 case SIS_REV_630E: 3763 case SIS_REV_630EA1: 3764 case SIS_REV_630ET: 3765 case SIS_REV_635: 3766 /* 3767 * The MAC address for the on-board Ethernet of 3768 * the SiS 630 chipset is in the NVRAM. Kick 3769 * the chip into re-loading it from NVRAM, and 3770 * read the MAC address out of the filter registers. 3771 */ 3772 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3773 3774 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3775 RFCR_RFADDR_NODE0); 3776 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3777 0xffff; 3778 3779 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3780 RFCR_RFADDR_NODE2); 3781 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3782 0xffff; 3783 3784 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3785 RFCR_RFADDR_NODE4); 3786 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3787 0xffff; 3788 break; 3789 3790 case SIS_REV_960: 3791 { 3792 #define SIS_SET_EROMAR(x, y) \ 3793 bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3794 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3795 3796 #define SIS_CLR_EROMAR(x, y) \ 3797 bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3798 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3799 3800 int waittime, i; 3801 3802 /* Allow to read EEPROM from LAN. It is shared 3803 * between a 1394 controller and the NIC and each 3804 * time we access it, we need to set SIS_EECMD_REQ. 3805 */ 3806 SIS_SET_EROMAR(sc, EROMAR_REQ); 3807 3808 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3809 /* Force EEPROM to idle state. */ 3810 3811 /* 3812 * XXX-cube This is ugly. 3813 * I'll look for docs about it. 3814 */ 3815 SIS_SET_EROMAR(sc, EROMAR_EECS); 3816 sipcom_sis900_eeprom_delay(sc); 3817 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3818 SIS_SET_EROMAR(sc, EROMAR_EESK); 3819 sipcom_sis900_eeprom_delay(sc); 3820 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3821 sipcom_sis900_eeprom_delay(sc); 3822 } 3823 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3824 sipcom_sis900_eeprom_delay(sc); 3825 bus_space_write_4(sc->sc_st, sc->sc_sh, 3826 SIP_EROMAR, 0); 3827 3828 if (bus_space_read_4(sc->sc_st, sc->sc_sh, 3829 SIP_EROMAR) & EROMAR_GNT) { 3830 sipcom_read_eeprom(sc, 3831 SIP_EEPROM_ETHERNET_ID0 >> 1, 3832 sizeof(myea) / sizeof(myea[0]), 3833 myea); 3834 break; 3835 } 3836 DELAY(1); 3837 } 3838 3839 /* 3840 * Set SIS_EECTL_CLK to high, so a other master 3841 * can operate on the i2c bus. 3842 */ 3843 SIS_SET_EROMAR(sc, EROMAR_EESK); 3844 3845 /* Refuse EEPROM access by LAN */ 3846 SIS_SET_EROMAR(sc, EROMAR_DONE); 3847 } break; 3848 3849 default: 3850 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3851 sizeof(myea) / sizeof(myea[0]), myea); 3852 } 3853 3854 enaddr[0] = myea[0] & 0xff; 3855 enaddr[1] = myea[0] >> 8; 3856 enaddr[2] = myea[1] & 0xff; 3857 enaddr[3] = myea[1] >> 8; 3858 enaddr[4] = myea[2] & 0xff; 3859 enaddr[5] = myea[2] >> 8; 3860 } 3861 3862 /* Table and macro to bit-reverse an octet. */ 3863 static const uint8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3864 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3865 3866 static void 3867 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3868 const struct pci_attach_args *pa, uint8_t *enaddr) 3869 { 3870 uint16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3871 uint8_t cksum, *e, match; 3872 int i; 3873 3874 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3875 sizeof(eeprom_data[0]), eeprom_data); 3876 3877 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3878 match = ~(match - 1); 3879 3880 cksum = 0x55; 3881 e = (uint8_t *)eeprom_data; 3882 for (i = 0; i < SIP_DP83815_EEPROM_CHECKSUM; i++) 3883 cksum += *e++; 3884 3885 if (cksum != match) 3886 printf("%s: Checksum (%x) mismatch (%x)", 3887 device_xname(sc->sc_dev), cksum, match); 3888 3889 /* 3890 * Unrolled because it makes slightly more sense this way. 3891 * The DP83815 stores the MAC address in bit 0 of word 6 3892 * through bit 15 of word 8. 3893 */ 3894 ea = &eeprom_data[6]; 3895 enaddr[0] = ((*ea & 0x1) << 7); 3896 ea++; 3897 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3898 enaddr[1] = ((*ea & 0x1FE) >> 1); 3899 enaddr[2] = ((*ea & 0x1) << 7); 3900 ea++; 3901 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3902 enaddr[3] = ((*ea & 0x1FE) >> 1); 3903 enaddr[4] = ((*ea & 0x1) << 7); 3904 ea++; 3905 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3906 enaddr[5] = ((*ea & 0x1FE) >> 1); 3907 3908 /* 3909 * In case that's not weird enough, we also need to reverse 3910 * the bits in each byte. This all actually makes more sense 3911 * if you think about the EEPROM storage as an array of bits 3912 * being shifted into bytes, but that's not how we're looking 3913 * at it here... 3914 */ 3915 for (i = 0; i < 6 ;i++) 3916 enaddr[i] = bbr(enaddr[i]); 3917 } 3918 3919 /* 3920 * sip_mediastatus: [ifmedia interface function] 3921 * 3922 * Get the current interface media status. 3923 */ 3924 static void 3925 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3926 { 3927 struct sip_softc *sc = ifp->if_softc; 3928 3929 if (!device_is_active(sc->sc_dev)) { 3930 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 3931 ifmr->ifm_status = 0; 3932 return; 3933 } 3934 ether_mediastatus(ifp, ifmr); 3935 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) | 3936 sc->sc_flowflags; 3937 } 3938
Indexes created Tue Sep 30 11:09:46 GMT 2025