if_sip.c revision 1.177
1 /* $NetBSD: if_sip.c,v 1.177 2020/02/04 05:44:14 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999 Network Computer, Inc. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of Network Computer, Inc. nor the names of its 45 * contributors may be used to endorse or promote products derived 46 * from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * Device driver for the Silicon Integrated Systems SiS 900, 63 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 64 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 65 * controllers. 66 * 67 * Originally written to support the SiS 900 by Jason R. Thorpe for 68 * Network Computer, Inc. 69 * 70 * TODO: 71 * 72 * - Reduce the Rx interrupt load. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.177 2020/02/04 05:44:14 thorpej Exp $"); 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/callout.h> 81 #include <sys/mbuf.h> 82 #include <sys/malloc.h> 83 #include <sys/kernel.h> 84 #include <sys/socket.h> 85 #include <sys/ioctl.h> 86 #include <sys/errno.h> 87 #include <sys/device.h> 88 #include <sys/queue.h> 89 #include <sys/rndsource.h> 90 91 #include <net/if.h> 92 #include <net/if_dl.h> 93 #include <net/if_media.h> 94 #include <net/if_ether.h> 95 #include <net/bpf.h> 96 97 #include <sys/bus.h> 98 #include <sys/intr.h> 99 #include <machine/endian.h> 100 101 #include <dev/mii/mii.h> 102 #include <dev/mii/miivar.h> 103 #include <dev/mii/mii_bitbang.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 109 #include <dev/pci/if_sipreg.h> 110 111 /* 112 * Transmit descriptor list size. This is arbitrary, but allocate 113 * enough descriptors for 128 pending transmissions, and 8 segments 114 * per packet (64 for DP83820 for jumbo frames). 115 * 116 * This MUST work out to a power of 2. 117 */ 118 #define GSIP_NTXSEGS_ALLOC 16 119 #define SIP_NTXSEGS_ALLOC 8 120 121 #define SIP_TXQUEUELEN 256 122 #define MAX_SIP_NTXDESC \ 123 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 124 125 /* 126 * Receive descriptor list size. We have one Rx buffer per incoming 127 * packet, so this logic is a little simpler. 128 * 129 * Actually, on the DP83820, we allow the packet to consume more than 130 * one buffer, in order to support jumbo Ethernet frames. In that 131 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 132 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 133 * so we'd better be quick about handling receive interrupts. 134 */ 135 #define GSIP_NRXDESC 256 136 #define SIP_NRXDESC 128 137 138 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 139 140 /* 141 * Control structures are DMA'd to the SiS900 chip. We allocate them in 142 * a single clump that maps to a single DMA segment to make several things 143 * easier. 144 */ 145 struct sip_control_data { 146 /* 147 * The transmit descriptors. 148 */ 149 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 150 151 /* 152 * The receive descriptors. 153 */ 154 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 155 }; 156 157 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 158 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 159 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 160 161 /* 162 * Software state for transmit jobs. 163 */ 164 struct sip_txsoft { 165 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 166 bus_dmamap_t txs_dmamap; /* our DMA map */ 167 int txs_firstdesc; /* first descriptor in packet */ 168 int txs_lastdesc; /* last descriptor in packet */ 169 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 170 }; 171 172 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 173 174 /* 175 * Software state for receive jobs. 176 */ 177 struct sip_rxsoft { 178 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 179 bus_dmamap_t rxs_dmamap; /* our DMA map */ 180 }; 181 182 enum sip_attach_stage { 183 SIP_ATTACH_FIN = 0 184 , SIP_ATTACH_CREATE_RXMAP 185 , SIP_ATTACH_CREATE_TXMAP 186 , SIP_ATTACH_LOAD_MAP 187 , SIP_ATTACH_CREATE_MAP 188 , SIP_ATTACH_MAP_MEM 189 , SIP_ATTACH_ALLOC_MEM 190 , SIP_ATTACH_INTR 191 , SIP_ATTACH_MAP 192 }; 193 194 /* 195 * Software state per device. 196 */ 197 struct sip_softc { 198 device_t sc_dev; /* generic device information */ 199 device_suspensor_t sc_suspensor; 200 pmf_qual_t sc_qual; 201 202 bus_space_tag_t sc_st; /* bus space tag */ 203 bus_space_handle_t sc_sh; /* bus space handle */ 204 bus_size_t sc_sz; /* bus space size */ 205 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 206 pci_chipset_tag_t sc_pc; 207 bus_dma_segment_t sc_seg; 208 struct ethercom sc_ethercom; /* ethernet common data */ 209 210 const struct sip_product *sc_model; /* which model are we? */ 211 int sc_gigabit; /* 1: 83820, 0: other */ 212 int sc_rev; /* chip revision */ 213 214 void *sc_ih; /* interrupt cookie */ 215 216 struct mii_data sc_mii; /* MII/media information */ 217 218 callout_t sc_tick_ch; /* tick callout */ 219 220 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 221 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 222 223 /* 224 * Software state for transmit and receive descriptors. 225 */ 226 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 227 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 228 229 /* 230 * Control data structures. 231 */ 232 struct sip_control_data *sc_control_data; 233 #define sc_txdescs sc_control_data->scd_txdescs 234 #define sc_rxdescs sc_control_data->scd_rxdescs 235 236 #ifdef SIP_EVENT_COUNTERS 237 /* 238 * Event counters. 239 */ 240 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 241 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 242 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 243 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 244 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 245 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 246 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 247 struct evcnt sc_ev_rxpause; /* PAUSE received */ 248 /* DP83820 only */ 249 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 250 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 251 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 252 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 253 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 254 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 255 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 256 #endif /* SIP_EVENT_COUNTERS */ 257 258 uint32_t sc_txcfg; /* prototype TXCFG register */ 259 uint32_t sc_rxcfg; /* prototype RXCFG register */ 260 uint32_t sc_imr; /* prototype IMR register */ 261 uint32_t sc_rfcr; /* prototype RFCR register */ 262 263 uint32_t sc_cfg; /* prototype CFG register */ 264 265 uint32_t sc_gpior; /* prototype GPIOR register */ 266 267 uint32_t sc_tx_fill_thresh; /* transmit fill threshold */ 268 uint32_t sc_tx_drain_thresh; /* transmit drain threshold */ 269 270 uint32_t sc_rx_drain_thresh; /* receive drain threshold */ 271 272 int sc_flowflags; /* 802.3x flow control flags */ 273 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 274 int sc_paused; /* paused indication */ 275 276 int sc_txfree; /* number of free Tx descriptors */ 277 int sc_txnext; /* next ready Tx descriptor */ 278 int sc_txwin; /* Tx descriptors since last intr */ 279 280 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 281 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 282 283 /* values of interface state at last init */ 284 struct { 285 /* if_capenable */ 286 uint64_t if_capenable; 287 /* ec_capenable */ 288 int ec_capenable; 289 /* VLAN_ATTACHED */ 290 int is_vlan; 291 } sc_prev; 292 293 u_short sc_if_flags; 294 295 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 296 int sc_rxdiscard; 297 int sc_rxlen; 298 struct mbuf *sc_rxhead; 299 struct mbuf *sc_rxtail; 300 struct mbuf **sc_rxtailp; 301 302 int sc_ntxdesc; 303 int sc_ntxdesc_mask; 304 305 int sc_nrxdesc_mask; 306 307 const struct sip_parm { 308 const struct sip_regs { 309 int r_rxcfg; 310 int r_txcfg; 311 } p_regs; 312 313 const struct sip_bits { 314 uint32_t b_txcfg_mxdma_8; 315 uint32_t b_txcfg_mxdma_16; 316 uint32_t b_txcfg_mxdma_32; 317 uint32_t b_txcfg_mxdma_64; 318 uint32_t b_txcfg_mxdma_128; 319 uint32_t b_txcfg_mxdma_256; 320 uint32_t b_txcfg_mxdma_512; 321 uint32_t b_txcfg_flth_mask; 322 uint32_t b_txcfg_drth_mask; 323 324 uint32_t b_rxcfg_mxdma_8; 325 uint32_t b_rxcfg_mxdma_16; 326 uint32_t b_rxcfg_mxdma_32; 327 uint32_t b_rxcfg_mxdma_64; 328 uint32_t b_rxcfg_mxdma_128; 329 uint32_t b_rxcfg_mxdma_256; 330 uint32_t b_rxcfg_mxdma_512; 331 332 uint32_t b_isr_txrcmp; 333 uint32_t b_isr_rxrcmp; 334 uint32_t b_isr_dperr; 335 uint32_t b_isr_sserr; 336 uint32_t b_isr_rmabt; 337 uint32_t b_isr_rtabt; 338 339 uint32_t b_cmdsts_size_mask; 340 } p_bits; 341 int p_filtmem; 342 int p_rxbuf_len; 343 bus_size_t p_tx_dmamap_size; 344 int p_ntxsegs; 345 int p_ntxsegs_alloc; 346 int p_nrxdesc; 347 } *sc_parm; 348 349 void (*sc_rxintr)(struct sip_softc *); 350 351 krndsource_t rnd_source; /* random source */ 352 }; 353 354 #define sc_bits sc_parm->p_bits 355 #define sc_regs sc_parm->p_regs 356 357 static const struct sip_parm sip_parm = { 358 .p_filtmem = OTHER_RFCR_NS_RFADDR_FILTMEM 359 , .p_rxbuf_len = MCLBYTES - 1 /* field width */ 360 , .p_tx_dmamap_size = MCLBYTES 361 , .p_ntxsegs = 16 362 , .p_ntxsegs_alloc = SIP_NTXSEGS_ALLOC 363 , .p_nrxdesc = SIP_NRXDESC 364 , .p_bits = { 365 .b_txcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 366 , .b_txcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 367 , .b_txcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 368 , .b_txcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 369 , .b_txcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 370 , .b_txcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 371 , .b_txcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 372 , .b_txcfg_flth_mask = 0x00003f00 /* Tx fill threshold */ 373 , .b_txcfg_drth_mask = 0x0000003f /* Tx drain threshold */ 374 375 , .b_rxcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 376 , .b_rxcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 377 , .b_rxcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 378 , .b_rxcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 379 , .b_rxcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 380 , .b_rxcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 381 , .b_rxcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 382 383 , .b_isr_txrcmp = 0x02000000 /* transmit reset complete */ 384 , .b_isr_rxrcmp = 0x01000000 /* receive reset complete */ 385 , .b_isr_dperr = 0x00800000 /* detected parity error */ 386 , .b_isr_sserr = 0x00400000 /* signalled system error */ 387 , .b_isr_rmabt = 0x00200000 /* received master abort */ 388 , .b_isr_rtabt = 0x00100000 /* received target abort */ 389 , .b_cmdsts_size_mask = OTHER_CMDSTS_SIZE_MASK 390 } 391 , .p_regs = { 392 .r_rxcfg = OTHER_SIP_RXCFG, 393 .r_txcfg = OTHER_SIP_TXCFG 394 } 395 }, gsip_parm = { 396 .p_filtmem = DP83820_RFCR_NS_RFADDR_FILTMEM 397 , .p_rxbuf_len = MCLBYTES - 8 398 , .p_tx_dmamap_size = ETHER_MAX_LEN_JUMBO 399 , .p_ntxsegs = 64 400 , .p_ntxsegs_alloc = GSIP_NTXSEGS_ALLOC 401 , .p_nrxdesc = GSIP_NRXDESC 402 , .p_bits = { 403 .b_txcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 404 , .b_txcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 405 , .b_txcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 406 , .b_txcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 407 , .b_txcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 408 , .b_txcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 409 , .b_txcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 410 , .b_txcfg_flth_mask = 0x0000ff00 /* Fx fill threshold */ 411 , .b_txcfg_drth_mask = 0x000000ff /* Tx drain threshold */ 412 413 , .b_rxcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 414 , .b_rxcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 415 , .b_rxcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 416 , .b_rxcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 417 , .b_rxcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 418 , .b_rxcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 419 , .b_rxcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 420 421 , .b_isr_txrcmp = 0x00400000 /* transmit reset complete */ 422 , .b_isr_rxrcmp = 0x00200000 /* receive reset complete */ 423 , .b_isr_dperr = 0x00100000 /* detected parity error */ 424 , .b_isr_sserr = 0x00080000 /* signalled system error */ 425 , .b_isr_rmabt = 0x00040000 /* received master abort */ 426 , .b_isr_rtabt = 0x00020000 /* received target abort */ 427 , .b_cmdsts_size_mask = DP83820_CMDSTS_SIZE_MASK 428 } 429 , .p_regs = { 430 .r_rxcfg = DP83820_SIP_RXCFG, 431 .r_txcfg = DP83820_SIP_TXCFG 432 } 433 }; 434 435 static inline int 436 sip_nexttx(const struct sip_softc *sc, int x) 437 { 438 return (x + 1) & sc->sc_ntxdesc_mask; 439 } 440 441 static inline int 442 sip_nextrx(const struct sip_softc *sc, int x) 443 { 444 return (x + 1) & sc->sc_nrxdesc_mask; 445 } 446 447 /* 83820 only */ 448 static inline void 449 sip_rxchain_reset(struct sip_softc *sc) 450 { 451 sc->sc_rxtailp = &sc->sc_rxhead; 452 *sc->sc_rxtailp = NULL; 453 sc->sc_rxlen = 0; 454 } 455 456 /* 83820 only */ 457 static inline void 458 sip_rxchain_link(struct sip_softc *sc, struct mbuf *m) 459 { 460 *sc->sc_rxtailp = sc->sc_rxtail = m; 461 sc->sc_rxtailp = &m->m_next; 462 } 463 464 #ifdef SIP_EVENT_COUNTERS 465 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 466 #else 467 #define SIP_EVCNT_INCR(ev) /* nothing */ 468 #endif 469 470 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 471 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 472 473 static inline void 474 sip_cdtxsync(struct sip_softc *sc, const int x0, const int n0, const int ops) 475 { 476 int x, n; 477 478 x = x0; 479 n = n0; 480 481 /* If it will wrap around, sync to the end of the ring. */ 482 if (x + n > sc->sc_ntxdesc) { 483 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 484 SIP_CDTXOFF(x), sizeof(struct sip_desc) * 485 (sc->sc_ntxdesc - x), ops); 486 n -= (sc->sc_ntxdesc - x); 487 x = 0; 488 } 489 490 /* Now sync whatever is left. */ 491 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 492 SIP_CDTXOFF(x), sizeof(struct sip_desc) * n, ops); 493 } 494 495 static inline void 496 sip_cdrxsync(struct sip_softc *sc, int x, int ops) 497 { 498 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 499 SIP_CDRXOFF(x), sizeof(struct sip_desc), ops); 500 } 501 502 #if 0 503 #ifdef DP83820 504 uint32_t sipd_bufptr; /* pointer to DMA segment */ 505 uint32_t sipd_cmdsts; /* command/status word */ 506 #else 507 uint32_t sipd_cmdsts; /* command/status word */ 508 uint32_t sipd_bufptr; /* pointer to DMA segment */ 509 #endif /* DP83820 */ 510 #endif /* 0 */ 511 512 static inline volatile uint32_t * 513 sipd_cmdsts(struct sip_softc *sc, struct sip_desc *sipd) 514 { 515 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 1 : 0]; 516 } 517 518 static inline volatile uint32_t * 519 sipd_bufptr(struct sip_softc *sc, struct sip_desc *sipd) 520 { 521 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 0 : 1]; 522 } 523 524 static inline void 525 sip_init_rxdesc(struct sip_softc *sc, int x) 526 { 527 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 528 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 529 530 sipd->sipd_link = htole32(SIP_CDRXADDR(sc, sip_nextrx(sc, x))); 531 *sipd_bufptr(sc, sipd) = htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 532 *sipd_cmdsts(sc, sipd) = htole32(CMDSTS_INTR | 533 (sc->sc_parm->p_rxbuf_len & sc->sc_bits.b_cmdsts_size_mask)); 534 sipd->sipd_extsts = 0; 535 sip_cdrxsync(sc, x, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 536 } 537 538 #define SIP_CHIP_VERS(sc, v, p, r) \ 539 ((sc)->sc_model->sip_vendor == (v) && \ 540 (sc)->sc_model->sip_product == (p) && \ 541 (sc)->sc_rev == (r)) 542 543 #define SIP_CHIP_MODEL(sc, v, p) \ 544 ((sc)->sc_model->sip_vendor == (v) && \ 545 (sc)->sc_model->sip_product == (p)) 546 547 #define SIP_SIS900_REV(sc, rev) \ 548 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 549 550 #define SIP_TIMEOUT 1000 551 552 static int sip_ifflags_cb(struct ethercom *); 553 static void sipcom_start(struct ifnet *); 554 static void sipcom_watchdog(struct ifnet *); 555 static int sipcom_ioctl(struct ifnet *, u_long, void *); 556 static int sipcom_init(struct ifnet *); 557 static void sipcom_stop(struct ifnet *, int); 558 559 static bool sipcom_reset(struct sip_softc *); 560 static void sipcom_rxdrain(struct sip_softc *); 561 static int sipcom_add_rxbuf(struct sip_softc *, int); 562 static void sipcom_read_eeprom(struct sip_softc *, int, int, 563 uint16_t *); 564 static void sipcom_tick(void *); 565 566 static void sipcom_sis900_set_filter(struct sip_softc *); 567 static void sipcom_dp83815_set_filter(struct sip_softc *); 568 569 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 570 const struct pci_attach_args *, uint8_t *); 571 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 572 static void sipcom_sis900_read_macaddr(struct sip_softc *, 573 const struct pci_attach_args *, uint8_t *); 574 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 575 const struct pci_attach_args *, uint8_t *); 576 577 static int sipcom_intr(void *); 578 static void sipcom_txintr(struct sip_softc *); 579 static void sip_rxintr(struct sip_softc *); 580 static void gsip_rxintr(struct sip_softc *); 581 582 static int sipcom_dp83820_mii_readreg(device_t, int, int, uint16_t *); 583 static int sipcom_dp83820_mii_writereg(device_t, int, int, uint16_t); 584 static void sipcom_dp83820_mii_statchg(struct ifnet *); 585 586 static int sipcom_sis900_mii_readreg(device_t, int, int, uint16_t *); 587 static int sipcom_sis900_mii_writereg(device_t, int, int, uint16_t); 588 static void sipcom_sis900_mii_statchg(struct ifnet *); 589 590 static int sipcom_dp83815_mii_readreg(device_t, int, int, uint16_t *); 591 static int sipcom_dp83815_mii_writereg(device_t, int, int, uint16_t); 592 static void sipcom_dp83815_mii_statchg(struct ifnet *); 593 594 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 595 596 static int sipcom_match(device_t, cfdata_t, void *); 597 static void sipcom_attach(device_t, device_t, void *); 598 static void sipcom_do_detach(device_t, enum sip_attach_stage); 599 static int sipcom_detach(device_t, int); 600 static bool sipcom_resume(device_t, const pmf_qual_t *); 601 static bool sipcom_suspend(device_t, const pmf_qual_t *); 602 603 int gsip_copy_small = 0; 604 int sip_copy_small = 0; 605 606 CFATTACH_DECL3_NEW(gsip, sizeof(struct sip_softc), 607 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 608 DVF_DETACH_SHUTDOWN); 609 CFATTACH_DECL3_NEW(sip, sizeof(struct sip_softc), 610 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 611 DVF_DETACH_SHUTDOWN); 612 613 /* 614 * Descriptions of the variants of the SiS900. 615 */ 616 struct sip_variant { 617 int (*sipv_mii_readreg)(device_t, int, int, uint16_t *); 618 int (*sipv_mii_writereg)(device_t, int, int, uint16_t); 619 void (*sipv_mii_statchg)(struct ifnet *); 620 void (*sipv_set_filter)(struct sip_softc *); 621 void (*sipv_read_macaddr)(struct sip_softc *, 622 const struct pci_attach_args *, uint8_t *); 623 }; 624 625 static uint32_t sipcom_mii_bitbang_read(device_t); 626 static void sipcom_mii_bitbang_write(device_t, uint32_t); 627 628 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 629 sipcom_mii_bitbang_read, 630 sipcom_mii_bitbang_write, 631 { 632 EROMAR_MDIO, /* MII_BIT_MDO */ 633 EROMAR_MDIO, /* MII_BIT_MDI */ 634 EROMAR_MDC, /* MII_BIT_MDC */ 635 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 636 0, /* MII_BIT_DIR_PHY_HOST */ 637 } 638 }; 639 640 static const struct sip_variant sipcom_variant_dp83820 = { 641 sipcom_dp83820_mii_readreg, 642 sipcom_dp83820_mii_writereg, 643 sipcom_dp83820_mii_statchg, 644 sipcom_dp83815_set_filter, 645 sipcom_dp83820_read_macaddr, 646 }; 647 648 static const struct sip_variant sipcom_variant_sis900 = { 649 sipcom_sis900_mii_readreg, 650 sipcom_sis900_mii_writereg, 651 sipcom_sis900_mii_statchg, 652 sipcom_sis900_set_filter, 653 sipcom_sis900_read_macaddr, 654 }; 655 656 static const struct sip_variant sipcom_variant_dp83815 = { 657 sipcom_dp83815_mii_readreg, 658 sipcom_dp83815_mii_writereg, 659 sipcom_dp83815_mii_statchg, 660 sipcom_dp83815_set_filter, 661 sipcom_dp83815_read_macaddr, 662 }; 663 664 665 /* 666 * Devices supported by this driver. 667 */ 668 static const struct sip_product { 669 pci_vendor_id_t sip_vendor; 670 pci_product_id_t sip_product; 671 const char *sip_name; 672 const struct sip_variant *sip_variant; 673 int sip_gigabit; 674 } sipcom_products[] = { 675 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 676 "NatSemi DP83820 Gigabit Ethernet", 677 &sipcom_variant_dp83820, 1 }, 678 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 679 "SiS 900 10/100 Ethernet", 680 &sipcom_variant_sis900, 0 }, 681 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 682 "SiS 7016 10/100 Ethernet", 683 &sipcom_variant_sis900, 0 }, 684 685 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 686 "NatSemi DP83815 10/100 Ethernet", 687 &sipcom_variant_dp83815, 0 }, 688 689 { 0, 0, 690 NULL, 691 NULL, 0 }, 692 }; 693 694 static const struct sip_product * 695 sipcom_lookup(const struct pci_attach_args *pa, bool gigabit) 696 { 697 const struct sip_product *sip; 698 699 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 700 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 701 PCI_PRODUCT(pa->pa_id) == sip->sip_product && 702 sip->sip_gigabit == gigabit) 703 return sip; 704 } 705 return NULL; 706 } 707 708 /* 709 * I really hate stupid hardware vendors. There's a bit in the EEPROM 710 * which indicates if the card can do 64-bit data transfers. Unfortunately, 711 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 712 * which means we try to use 64-bit data transfers on those cards if we 713 * happen to be plugged into a 32-bit slot. 714 * 715 * What we do is use this table of cards known to be 64-bit cards. If 716 * you have a 64-bit card who's subsystem ID is not listed in this table, 717 * send the output of "pcictl dump ..." of the device to me so that your 718 * card will use the 64-bit data path when plugged into a 64-bit slot. 719 * 720 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 721 * June 30, 2002 722 */ 723 static int 724 sipcom_check_64bit(const struct pci_attach_args *pa) 725 { 726 static const struct { 727 pci_vendor_id_t c64_vendor; 728 pci_product_id_t c64_product; 729 } card64[] = { 730 /* Asante GigaNIX */ 731 { 0x128a, 0x0002 }, 732 733 /* Accton EN1407-T, Planex GN-1000TE */ 734 { 0x1113, 0x1407 }, 735 736 /* Netgear GA621 */ 737 { 0x1385, 0x621a }, 738 739 /* Netgear GA622 */ 740 { 0x1385, 0x622a }, 741 742 /* SMC EZ Card 1000 (9462TX) */ 743 { 0x10b8, 0x9462 }, 744 745 { 0, 0} 746 }; 747 pcireg_t subsys; 748 int i; 749 750 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 751 752 for (i = 0; card64[i].c64_vendor != 0; i++) { 753 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 754 PCI_PRODUCT(subsys) == card64[i].c64_product) 755 return 1; 756 } 757 758 return 0; 759 } 760 761 static int 762 sipcom_match(device_t parent, cfdata_t cf, void *aux) 763 { 764 struct pci_attach_args *pa = aux; 765 766 if (sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0) != NULL) 767 return 1; 768 769 return 0; 770 } 771 772 static void 773 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 774 { 775 uint32_t reg; 776 int i; 777 778 /* 779 * Cause the chip to load configuration data from the EEPROM. 780 */ 781 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 782 for (i = 0; i < 10000; i++) { 783 delay(10); 784 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 785 PTSCR_EELOAD_EN) == 0) 786 break; 787 } 788 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 789 PTSCR_EELOAD_EN) { 790 printf("%s: timeout loading configuration from EEPROM\n", 791 device_xname(sc->sc_dev)); 792 return; 793 } 794 795 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 796 797 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 798 if (reg & CFG_PCI64_DET) { 799 printf("%s: 64-bit PCI slot detected", device_xname(sc->sc_dev)); 800 /* 801 * Check to see if this card is 64-bit. If so, enable 64-bit 802 * data transfers. 803 * 804 * We can't use the DATA64_EN bit in the EEPROM, because 805 * vendors of 32-bit cards fail to clear that bit in many 806 * cases (yet the card still detects that it's in a 64-bit 807 * slot; go figure). 808 */ 809 if (sipcom_check_64bit(pa)) { 810 sc->sc_cfg |= CFG_DATA64_EN; 811 printf(", using 64-bit data transfers"); 812 } 813 printf("\n"); 814 } 815 816 /* 817 * XXX Need some PCI flags indicating support for 818 * XXX 64-bit addressing. 819 */ 820 #if 0 821 if (reg & CFG_M64ADDR) 822 sc->sc_cfg |= CFG_M64ADDR; 823 if (reg & CFG_T64ADDR) 824 sc->sc_cfg |= CFG_T64ADDR; 825 #endif 826 827 if (reg & (CFG_TBI_EN | CFG_EXT_125)) { 828 const char *sep = ""; 829 printf("%s: using ", device_xname(sc->sc_dev)); 830 if (reg & CFG_EXT_125) { 831 sc->sc_cfg |= CFG_EXT_125; 832 printf("%s125MHz clock", sep); 833 sep = ", "; 834 } 835 if (reg & CFG_TBI_EN) { 836 sc->sc_cfg |= CFG_TBI_EN; 837 printf("%sten-bit interface", sep); 838 sep = ", "; 839 } 840 printf("\n"); 841 } 842 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 843 (reg & CFG_MRM_DIS) != 0) 844 sc->sc_cfg |= CFG_MRM_DIS; 845 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 846 (reg & CFG_MWI_DIS) != 0) 847 sc->sc_cfg |= CFG_MWI_DIS; 848 849 /* 850 * Use the extended descriptor format on the DP83820. This 851 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 852 * checksumming. 853 */ 854 sc->sc_cfg |= CFG_EXTSTS_EN; 855 } 856 857 static int 858 sipcom_detach(device_t self, int flags) 859 { 860 int s; 861 862 s = splnet(); 863 sipcom_do_detach(self, SIP_ATTACH_FIN); 864 splx(s); 865 866 return 0; 867 } 868 869 static void 870 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 871 { 872 int i; 873 struct sip_softc *sc = device_private(self); 874 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 875 876 /* 877 * Free any resources we've allocated during attach. 878 * Do this in reverse order and fall through. 879 */ 880 switch (stage) { 881 case SIP_ATTACH_FIN: 882 sipcom_stop(ifp, 1); 883 pmf_device_deregister(self); 884 #ifdef SIP_EVENT_COUNTERS 885 /* 886 * Attach event counters. 887 */ 888 evcnt_detach(&sc->sc_ev_txforceintr); 889 evcnt_detach(&sc->sc_ev_txdstall); 890 evcnt_detach(&sc->sc_ev_txsstall); 891 evcnt_detach(&sc->sc_ev_hiberr); 892 evcnt_detach(&sc->sc_ev_rxintr); 893 evcnt_detach(&sc->sc_ev_txiintr); 894 evcnt_detach(&sc->sc_ev_txdintr); 895 if (!sc->sc_gigabit) { 896 evcnt_detach(&sc->sc_ev_rxpause); 897 } else { 898 evcnt_detach(&sc->sc_ev_txudpsum); 899 evcnt_detach(&sc->sc_ev_txtcpsum); 900 evcnt_detach(&sc->sc_ev_txipsum); 901 evcnt_detach(&sc->sc_ev_rxudpsum); 902 evcnt_detach(&sc->sc_ev_rxtcpsum); 903 evcnt_detach(&sc->sc_ev_rxipsum); 904 evcnt_detach(&sc->sc_ev_txpause); 905 evcnt_detach(&sc->sc_ev_rxpause); 906 } 907 #endif /* SIP_EVENT_COUNTERS */ 908 909 rnd_detach_source(&sc->rnd_source); 910 911 ether_ifdetach(ifp); 912 if_detach(ifp); 913 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 914 ifmedia_fini(&sc->sc_mii.mii_media); 915 916 /*FALLTHROUGH*/ 917 case SIP_ATTACH_CREATE_RXMAP: 918 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 919 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 920 bus_dmamap_destroy(sc->sc_dmat, 921 sc->sc_rxsoft[i].rxs_dmamap); 922 } 923 /*FALLTHROUGH*/ 924 case SIP_ATTACH_CREATE_TXMAP: 925 for (i = 0; i < SIP_TXQUEUELEN; i++) { 926 if (sc->sc_txsoft[i].txs_dmamap != NULL) 927 bus_dmamap_destroy(sc->sc_dmat, 928 sc->sc_txsoft[i].txs_dmamap); 929 } 930 /*FALLTHROUGH*/ 931 case SIP_ATTACH_LOAD_MAP: 932 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 933 /*FALLTHROUGH*/ 934 case SIP_ATTACH_CREATE_MAP: 935 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 936 /*FALLTHROUGH*/ 937 case SIP_ATTACH_MAP_MEM: 938 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 939 sizeof(struct sip_control_data)); 940 /*FALLTHROUGH*/ 941 case SIP_ATTACH_ALLOC_MEM: 942 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 943 /* FALLTHROUGH*/ 944 case SIP_ATTACH_INTR: 945 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 946 /* FALLTHROUGH*/ 947 case SIP_ATTACH_MAP: 948 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 949 break; 950 default: 951 break; 952 } 953 return; 954 } 955 956 static bool 957 sipcom_resume(device_t self, const pmf_qual_t *qual) 958 { 959 struct sip_softc *sc = device_private(self); 960 961 return sipcom_reset(sc); 962 } 963 964 static bool 965 sipcom_suspend(device_t self, const pmf_qual_t *qual) 966 { 967 struct sip_softc *sc = device_private(self); 968 969 sipcom_rxdrain(sc); 970 return true; 971 } 972 973 static void 974 sipcom_attach(device_t parent, device_t self, void *aux) 975 { 976 struct sip_softc *sc = device_private(self); 977 struct pci_attach_args *pa = aux; 978 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 979 struct mii_data * const mii = &sc->sc_mii; 980 pci_chipset_tag_t pc = pa->pa_pc; 981 pci_intr_handle_t ih; 982 const char *intrstr = NULL; 983 bus_space_tag_t iot, memt; 984 bus_space_handle_t ioh, memh; 985 bus_size_t iosz, memsz; 986 int ioh_valid, memh_valid; 987 int i, rseg, error; 988 const struct sip_product *sip; 989 uint8_t enaddr[ETHER_ADDR_LEN]; 990 pcireg_t csr; 991 pcireg_t memtype; 992 bus_size_t tx_dmamap_size; 993 int ntxsegs_alloc; 994 cfdata_t cf = device_cfdata(self); 995 char intrbuf[PCI_INTRSTR_LEN]; 996 997 callout_init(&sc->sc_tick_ch, 0); 998 999 sip = sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0); 1000 if (sip == NULL) { 1001 aprint_error("\n"); 1002 panic("%s: impossible", __func__); 1003 } 1004 sc->sc_dev = self; 1005 sc->sc_gigabit = sip->sip_gigabit; 1006 pmf_self_suspensor_init(self, &sc->sc_suspensor, &sc->sc_qual); 1007 sc->sc_pc = pc; 1008 1009 if (sc->sc_gigabit) { 1010 sc->sc_rxintr = gsip_rxintr; 1011 sc->sc_parm = &gsip_parm; 1012 } else { 1013 sc->sc_rxintr = sip_rxintr; 1014 sc->sc_parm = &sip_parm; 1015 } 1016 tx_dmamap_size = sc->sc_parm->p_tx_dmamap_size; 1017 ntxsegs_alloc = sc->sc_parm->p_ntxsegs_alloc; 1018 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 1019 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 1020 sc->sc_nrxdesc_mask = sc->sc_parm->p_nrxdesc - 1; 1021 1022 sc->sc_rev = PCI_REVISION(pa->pa_class); 1023 1024 aprint_naive("\n"); 1025 aprint_normal(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 1026 1027 sc->sc_model = sip; 1028 1029 /* 1030 * XXX Work-around broken PXE firmware on some boards. 1031 * 1032 * The DP83815 shares an address decoder with the MEM BAR 1033 * and the ROM BAR. Make sure the ROM BAR is disabled, 1034 * so that memory mapped access works. 1035 */ 1036 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1037 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1038 ~PCI_MAPREG_ROM_ENABLE); 1039 1040 /* 1041 * Map the device. 1042 */ 1043 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 1044 PCI_MAPREG_TYPE_IO, 0, 1045 &iot, &ioh, NULL, &iosz) == 0); 1046 if (sc->sc_gigabit) { 1047 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 1048 switch (memtype) { 1049 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1050 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1051 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1052 memtype, 0, &memt, &memh, NULL, &memsz) == 0); 1053 break; 1054 default: 1055 memh_valid = 0; 1056 } 1057 } else { 1058 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1059 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 1060 &memt, &memh, NULL, &memsz) == 0); 1061 } 1062 1063 if (memh_valid) { 1064 sc->sc_st = memt; 1065 sc->sc_sh = memh; 1066 sc->sc_sz = memsz; 1067 } else if (ioh_valid) { 1068 sc->sc_st = iot; 1069 sc->sc_sh = ioh; 1070 sc->sc_sz = iosz; 1071 } else { 1072 aprint_error_dev(self, "unable to map device registers\n"); 1073 return; 1074 } 1075 1076 sc->sc_dmat = pa->pa_dmat; 1077 1078 /* 1079 * Make sure bus mastering is enabled. Also make sure 1080 * Write/Invalidate is enabled if we're allowed to use it. 1081 */ 1082 csr = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1083 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 1084 csr |= PCI_COMMAND_INVALIDATE_ENABLE; 1085 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1086 csr | PCI_COMMAND_MASTER_ENABLE); 1087 1088 /* Power up chip */ 1089 error = pci_activate(pa->pa_pc, pa->pa_tag, self, pci_activate_null); 1090 if (error != 0 && error != EOPNOTSUPP) { 1091 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 1092 return; 1093 } 1094 1095 /* 1096 * Map and establish our interrupt. 1097 */ 1098 if (pci_intr_map(pa, &ih)) { 1099 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 1100 return; 1101 } 1102 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1103 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, sipcom_intr, sc, 1104 device_xname(self)); 1105 if (sc->sc_ih == NULL) { 1106 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 1107 if (intrstr != NULL) 1108 aprint_error(" at %s", intrstr); 1109 aprint_error("\n"); 1110 sipcom_do_detach(self, SIP_ATTACH_MAP); 1111 return; 1112 } 1113 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1114 1115 SIMPLEQ_INIT(&sc->sc_txfreeq); 1116 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1117 1118 /* 1119 * Allocate the control data structures, and create and load the 1120 * DMA map for it. 1121 */ 1122 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1123 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 1124 &rseg, 0)) != 0) { 1125 aprint_error_dev(sc->sc_dev, 1126 "unable to allocate control data, error = %d\n", error); 1127 sipcom_do_detach(self, SIP_ATTACH_INTR); 1128 return; 1129 } 1130 1131 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 1132 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 1133 BUS_DMA_COHERENT)) != 0) { 1134 aprint_error_dev(sc->sc_dev, 1135 "unable to map control data, error = %d\n", error); 1136 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 1137 } 1138 1139 if ((error = bus_dmamap_create(sc->sc_dmat, 1140 sizeof(struct sip_control_data), 1, 1141 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 1142 aprint_error_dev(self, "unable to create control data DMA map" 1143 ", error = %d\n", error); 1144 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 1145 } 1146 1147 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1148 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 1149 0)) != 0) { 1150 aprint_error_dev(self, "unable to load control data DMA map" 1151 ", error = %d\n", error); 1152 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 1153 } 1154 1155 /* 1156 * Create the transmit buffer DMA maps. 1157 */ 1158 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1159 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 1160 sc->sc_parm->p_ntxsegs, MCLBYTES, 0, 0, 1161 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1162 aprint_error_dev(self, "unable to create tx DMA map %d" 1163 ", error = %d\n", i, error); 1164 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 1165 } 1166 } 1167 1168 /* 1169 * Create the receive buffer DMA maps. 1170 */ 1171 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1172 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1173 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1174 aprint_error_dev(self, "unable to create rx DMA map %d" 1175 ", error = %d\n", i, error); 1176 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 1177 } 1178 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1179 } 1180 1181 /* 1182 * Reset the chip to a known state. 1183 */ 1184 sipcom_reset(sc); 1185 1186 /* 1187 * Read the Ethernet address from the EEPROM. This might 1188 * also fetch other stuff from the EEPROM and stash it 1189 * in the softc. 1190 */ 1191 sc->sc_cfg = 0; 1192 if (!sc->sc_gigabit) { 1193 if (SIP_SIS900_REV(sc, SIS_REV_635) || 1194 SIP_SIS900_REV(sc, SIS_REV_900B)) 1195 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1196 1197 if (SIP_SIS900_REV(sc, SIS_REV_635) || 1198 SIP_SIS900_REV(sc, SIS_REV_960) || 1199 SIP_SIS900_REV(sc, SIS_REV_900B)) 1200 sc->sc_cfg |= 1201 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1202 CFG_EDBMASTEN); 1203 } 1204 1205 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1206 1207 aprint_normal_dev(self, "Ethernet address %s\n",ether_sprintf(enaddr)); 1208 1209 /* 1210 * Initialize the configuration register: aggressive PCI 1211 * bus request algorithm, default backoff, default OW timer, 1212 * default parity error detection. 1213 * 1214 * NOTE: "Big endian mode" is useless on the SiS900 and 1215 * friends -- it affects packet data, not descriptors. 1216 */ 1217 if (sc->sc_gigabit) 1218 sipcom_dp83820_attach(sc, pa); 1219 1220 /* 1221 * Initialize our media structures and probe the MII. 1222 */ 1223 mii->mii_ifp = ifp; 1224 mii->mii_readreg = sip->sip_variant->sipv_mii_readreg; 1225 mii->mii_writereg = sip->sip_variant->sipv_mii_writereg; 1226 mii->mii_statchg = sip->sip_variant->sipv_mii_statchg; 1227 sc->sc_ethercom.ec_mii = mii; 1228 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 1229 sipcom_mediastatus); 1230 1231 /* 1232 * XXX We cannot handle flow control on the DP83815. 1233 */ 1234 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1235 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 1236 MII_OFFSET_ANY, 0); 1237 else 1238 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 1239 MII_OFFSET_ANY, MIIF_DOPAUSE); 1240 if (LIST_FIRST(&mii->mii_phys) == NULL) { 1241 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 1242 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 1243 } else 1244 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1245 1246 ifp = &sc->sc_ethercom.ec_if; 1247 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1248 ifp->if_softc = sc; 1249 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1250 sc->sc_if_flags = ifp->if_flags; 1251 ifp->if_ioctl = sipcom_ioctl; 1252 ifp->if_start = sipcom_start; 1253 ifp->if_watchdog = sipcom_watchdog; 1254 ifp->if_init = sipcom_init; 1255 ifp->if_stop = sipcom_stop; 1256 IFQ_SET_READY(&ifp->if_snd); 1257 1258 /* 1259 * We can support 802.1Q VLAN-sized frames. 1260 */ 1261 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1262 1263 if (sc->sc_gigabit) { 1264 /* 1265 * And the DP83820 can do VLAN tagging in hardware, and 1266 * support the jumbo Ethernet MTU. 1267 */ 1268 sc->sc_ethercom.ec_capabilities |= 1269 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1270 sc->sc_ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 1271 1272 /* 1273 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1274 * in hardware. 1275 */ 1276 ifp->if_capabilities |= 1277 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1278 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1279 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1280 } 1281 1282 /* 1283 * Attach the interface. 1284 */ 1285 if_attach(ifp); 1286 if_deferred_start_init(ifp, NULL); 1287 ether_ifattach(ifp, enaddr); 1288 ether_set_ifflags_cb(&sc->sc_ethercom, sip_ifflags_cb); 1289 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1290 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1291 sc->sc_prev.if_capenable = ifp->if_capenable; 1292 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 1293 RND_TYPE_NET, RND_FLAG_DEFAULT); 1294 1295 /* 1296 * The number of bytes that must be available in 1297 * the Tx FIFO before the bus master can DMA more 1298 * data into the FIFO. 1299 */ 1300 sc->sc_tx_fill_thresh = 64 / 32; 1301 1302 /* 1303 * Start at a drain threshold of 512 bytes. We will 1304 * increase it if a DMA underrun occurs. 1305 * 1306 * XXX The minimum value of this variable should be 1307 * tuned. We may be able to improve performance 1308 * by starting with a lower value. That, however, 1309 * may trash the first few outgoing packets if the 1310 * PCI bus is saturated. 1311 */ 1312 if (sc->sc_gigabit) 1313 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1314 else 1315 sc->sc_tx_drain_thresh = 1504 / 32; 1316 1317 /* 1318 * Initialize the Rx FIFO drain threshold. 1319 * 1320 * This is in units of 8 bytes. 1321 * 1322 * We should never set this value lower than 2; 14 bytes are 1323 * required to filter the packet. 1324 */ 1325 sc->sc_rx_drain_thresh = 128 / 8; 1326 1327 #ifdef SIP_EVENT_COUNTERS 1328 /* 1329 * Attach event counters. 1330 */ 1331 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1332 NULL, device_xname(sc->sc_dev), "txsstall"); 1333 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1334 NULL, device_xname(sc->sc_dev), "txdstall"); 1335 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1336 NULL, device_xname(sc->sc_dev), "txforceintr"); 1337 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1338 NULL, device_xname(sc->sc_dev), "txdintr"); 1339 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1340 NULL, device_xname(sc->sc_dev), "txiintr"); 1341 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1342 NULL, device_xname(sc->sc_dev), "rxintr"); 1343 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1344 NULL, device_xname(sc->sc_dev), "hiberr"); 1345 if (!sc->sc_gigabit) { 1346 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1347 NULL, device_xname(sc->sc_dev), "rxpause"); 1348 } else { 1349 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1350 NULL, device_xname(sc->sc_dev), "rxpause"); 1351 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1352 NULL, device_xname(sc->sc_dev), "txpause"); 1353 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1354 NULL, device_xname(sc->sc_dev), "rxipsum"); 1355 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1356 NULL, device_xname(sc->sc_dev), "rxtcpsum"); 1357 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1358 NULL, device_xname(sc->sc_dev), "rxudpsum"); 1359 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1360 NULL, device_xname(sc->sc_dev), "txipsum"); 1361 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1362 NULL, device_xname(sc->sc_dev), "txtcpsum"); 1363 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1364 NULL, device_xname(sc->sc_dev), "txudpsum"); 1365 } 1366 #endif /* SIP_EVENT_COUNTERS */ 1367 1368 if (pmf_device_register(self, sipcom_suspend, sipcom_resume)) 1369 pmf_class_network_register(self, ifp); 1370 else 1371 aprint_error_dev(self, "couldn't establish power handler\n"); 1372 } 1373 1374 static inline void 1375 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1376 uint64_t capenable) 1377 { 1378 uint32_t extsts; 1379 #ifdef DEBUG 1380 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1381 #endif 1382 /* 1383 * If VLANs are enabled and the packet has a VLAN tag, set 1384 * up the descriptor to encapsulate the packet for us. 1385 * 1386 * This apparently has to be on the last descriptor of 1387 * the packet. 1388 */ 1389 1390 /* 1391 * Byte swapping is tricky. We need to provide the tag 1392 * in a network byte order. On a big-endian machine, 1393 * the byteorder is correct, but we need to swap it 1394 * anyway, because this will be undone by the outside 1395 * htole32(). That's why there must be an 1396 * unconditional swap instead of htons() inside. 1397 */ 1398 if (vlan_has_tag(m0)) { 1399 sc->sc_txdescs[lasttx].sipd_extsts |= 1400 htole32(EXTSTS_VPKT | 1401 (bswap16(vlan_get_tag(m0)) & 1402 EXTSTS_VTCI)); 1403 } 1404 1405 /* 1406 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1407 * checksumming, set up the descriptor to do this work 1408 * for us. 1409 * 1410 * This apparently has to be on the first descriptor of 1411 * the packet. 1412 * 1413 * Byte-swap constants so the compiler can optimize. 1414 */ 1415 extsts = 0; 1416 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1417 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1418 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1419 extsts |= htole32(EXTSTS_IPPKT); 1420 } 1421 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1422 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1423 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1424 extsts |= htole32(EXTSTS_TCPPKT); 1425 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1426 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1427 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1428 extsts |= htole32(EXTSTS_UDPPKT); 1429 } 1430 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1431 } 1432 1433 /* 1434 * sip_start: [ifnet interface function] 1435 * 1436 * Start packet transmission on the interface. 1437 */ 1438 static void 1439 sipcom_start(struct ifnet *ifp) 1440 { 1441 struct sip_softc *sc = ifp->if_softc; 1442 struct mbuf *m0; 1443 struct mbuf *m; 1444 struct sip_txsoft *txs; 1445 bus_dmamap_t dmamap; 1446 int error, nexttx, lasttx, seg; 1447 int ofree = sc->sc_txfree; 1448 #if 0 1449 int firsttx = sc->sc_txnext; 1450 #endif 1451 1452 /* 1453 * If we've been told to pause, don't transmit any more packets. 1454 */ 1455 if (!sc->sc_gigabit && sc->sc_paused) 1456 ifp->if_flags |= IFF_OACTIVE; 1457 1458 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1459 return; 1460 1461 /* 1462 * Loop through the send queue, setting up transmit descriptors 1463 * until we drain the queue, or use up all available transmit 1464 * descriptors. 1465 */ 1466 for (;;) { 1467 /* Get a work queue entry. */ 1468 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1469 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1470 break; 1471 } 1472 1473 /* 1474 * Grab a packet off the queue. 1475 */ 1476 IFQ_POLL(&ifp->if_snd, m0); 1477 if (m0 == NULL) 1478 break; 1479 m = NULL; 1480 1481 dmamap = txs->txs_dmamap; 1482 1483 /* 1484 * Load the DMA map. If this fails, the packet either 1485 * didn't fit in the alloted number of segments, or we 1486 * were short on resources. 1487 */ 1488 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1489 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1490 /* In the non-gigabit case, we'll copy and try again. */ 1491 if (error != 0 && !sc->sc_gigabit) { 1492 MGETHDR(m, M_DONTWAIT, MT_DATA); 1493 if (m == NULL) { 1494 printf("%s: unable to allocate Tx mbuf\n", 1495 device_xname(sc->sc_dev)); 1496 break; 1497 } 1498 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1499 if (m0->m_pkthdr.len > MHLEN) { 1500 MCLGET(m, M_DONTWAIT); 1501 if ((m->m_flags & M_EXT) == 0) { 1502 printf("%s: unable to allocate Tx " 1503 "cluster\n", 1504 device_xname(sc->sc_dev)); 1505 m_freem(m); 1506 break; 1507 } 1508 } 1509 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1510 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1511 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1512 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1513 if (error) { 1514 printf("%s: unable to load Tx buffer, error = " 1515 "%d\n", device_xname(sc->sc_dev), error); 1516 break; 1517 } 1518 } else if (error == EFBIG) { 1519 /* 1520 * For the too-many-segments case, we simply 1521 * report an error and drop the packet, 1522 * since we can't sanely copy a jumbo packet 1523 * to a single buffer. 1524 */ 1525 printf("%s: Tx packet consumes too many DMA segments, " 1526 "dropping...\n", device_xname(sc->sc_dev)); 1527 IFQ_DEQUEUE(&ifp->if_snd, m0); 1528 m_freem(m0); 1529 continue; 1530 } else if (error != 0) { 1531 /* 1532 * Short on resources, just stop for now. 1533 */ 1534 break; 1535 } 1536 1537 /* 1538 * Ensure we have enough descriptors free to describe 1539 * the packet. Note, we always reserve one descriptor 1540 * at the end of the ring as a termination point, to 1541 * prevent wrap-around. 1542 */ 1543 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1544 /* 1545 * Not enough free descriptors to transmit this 1546 * packet. We haven't committed anything yet, 1547 * so just unload the DMA map, put the packet 1548 * back on the queue, and punt. Notify the upper 1549 * layer that there are not more slots left. 1550 * 1551 * XXX We could allocate an mbuf and copy, but 1552 * XXX is it worth it? 1553 */ 1554 ifp->if_flags |= IFF_OACTIVE; 1555 bus_dmamap_unload(sc->sc_dmat, dmamap); 1556 if (m != NULL) 1557 m_freem(m); 1558 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1559 break; 1560 } 1561 1562 IFQ_DEQUEUE(&ifp->if_snd, m0); 1563 if (m != NULL) { 1564 m_freem(m0); 1565 m0 = m; 1566 } 1567 1568 /* 1569 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1570 */ 1571 1572 /* Sync the DMA map. */ 1573 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1574 BUS_DMASYNC_PREWRITE); 1575 1576 /* 1577 * Initialize the transmit descriptors. 1578 */ 1579 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1580 seg < dmamap->dm_nsegs; 1581 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1582 /* 1583 * If this is the first descriptor we're 1584 * enqueueing, don't set the OWN bit just 1585 * yet. That could cause a race condition. 1586 * We'll do it below. 1587 */ 1588 *sipd_bufptr(sc, &sc->sc_txdescs[nexttx]) = 1589 htole32(dmamap->dm_segs[seg].ds_addr); 1590 *sipd_cmdsts(sc, &sc->sc_txdescs[nexttx]) = 1591 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) 1592 | CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1593 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1594 lasttx = nexttx; 1595 } 1596 1597 /* Clear the MORE bit on the last segment. */ 1598 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) &= 1599 htole32(~CMDSTS_MORE); 1600 1601 /* 1602 * If we're in the interrupt delay window, delay the 1603 * interrupt. 1604 */ 1605 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1606 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1607 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) |= 1608 htole32(CMDSTS_INTR); 1609 sc->sc_txwin = 0; 1610 } 1611 1612 if (sc->sc_gigabit) 1613 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1614 1615 /* Sync the descriptors we're using. */ 1616 sip_cdtxsync(sc, sc->sc_txnext, dmamap->dm_nsegs, 1617 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1618 1619 /* 1620 * The entire packet is set up. Give the first descrptor 1621 * to the chip now. 1622 */ 1623 *sipd_cmdsts(sc, &sc->sc_txdescs[sc->sc_txnext]) |= 1624 htole32(CMDSTS_OWN); 1625 sip_cdtxsync(sc, sc->sc_txnext, 1, 1626 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1627 1628 /* 1629 * Store a pointer to the packet so we can free it later, 1630 * and remember what txdirty will be once the packet is 1631 * done. 1632 */ 1633 txs->txs_mbuf = m0; 1634 txs->txs_firstdesc = sc->sc_txnext; 1635 txs->txs_lastdesc = lasttx; 1636 1637 /* Advance the tx pointer. */ 1638 sc->sc_txfree -= dmamap->dm_nsegs; 1639 sc->sc_txnext = nexttx; 1640 1641 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1642 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1643 1644 /* Pass the packet to any BPF listeners. */ 1645 bpf_mtap(ifp, m0, BPF_D_OUT); 1646 } 1647 1648 if (txs == NULL || sc->sc_txfree == 0) { 1649 /* No more slots left; notify upper layer. */ 1650 ifp->if_flags |= IFF_OACTIVE; 1651 } 1652 1653 if (sc->sc_txfree != ofree) { 1654 /* 1655 * Start the transmit process. Note, the manual says 1656 * that if there are no pending transmissions in the 1657 * chip's internal queue (indicated by TXE being clear), 1658 * then the driver software must set the TXDP to the 1659 * first descriptor to be transmitted. However, if we 1660 * do this, it causes serious performance degredation on 1661 * the DP83820 under load, not setting TXDP doesn't seem 1662 * to adversely affect the SiS 900 or DP83815. 1663 * 1664 * Well, I guess it wouldn't be the first time a manual 1665 * has lied -- and they could be speaking of the NULL- 1666 * terminated descriptor list case, rather than OWN- 1667 * terminated rings. 1668 */ 1669 #if 0 1670 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1671 CR_TXE) == 0) { 1672 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1673 SIP_CDTXADDR(sc, firsttx)); 1674 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1675 } 1676 #else 1677 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1678 #endif 1679 1680 /* Set a watchdog timer in case the chip flakes out. */ 1681 /* Gigabit autonegotiation takes 5 seconds. */ 1682 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1683 } 1684 } 1685 1686 /* 1687 * sip_watchdog: [ifnet interface function] 1688 * 1689 * Watchdog timer handler. 1690 */ 1691 static void 1692 sipcom_watchdog(struct ifnet *ifp) 1693 { 1694 struct sip_softc *sc = ifp->if_softc; 1695 1696 /* 1697 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1698 * If we get a timeout, try and sweep up transmit descriptors. 1699 * If we manage to sweep them all up, ignore the lack of 1700 * interrupt. 1701 */ 1702 sipcom_txintr(sc); 1703 1704 if (sc->sc_txfree != sc->sc_ntxdesc) { 1705 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1706 if_statinc(ifp, if_oerrors); 1707 1708 /* Reset the interface. */ 1709 (void) sipcom_init(ifp); 1710 } else if (ifp->if_flags & IFF_DEBUG) 1711 printf("%s: recovered from device timeout\n", 1712 device_xname(sc->sc_dev)); 1713 1714 /* Try to get more packets going. */ 1715 sipcom_start(ifp); 1716 } 1717 1718 /* If the interface is up and running, only modify the receive 1719 * filter when setting promiscuous or debug mode. Otherwise fall 1720 * through to ether_ioctl, which will reset the chip. 1721 */ 1722 static int 1723 sip_ifflags_cb(struct ethercom *ec) 1724 { 1725 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1726 == (sc)->sc_ethercom.ec_capenable) \ 1727 && ((sc)->sc_prev.is_vlan == \ 1728 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1729 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1730 struct ifnet *ifp = &ec->ec_if; 1731 struct sip_softc *sc = ifp->if_softc; 1732 u_short change = ifp->if_flags ^ sc->sc_if_flags; 1733 1734 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0 || !COMPARE_EC(sc) || 1735 !COMPARE_IC(sc, ifp)) 1736 return ENETRESET; 1737 /* Set up the receive filter. */ 1738 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1739 return 0; 1740 } 1741 1742 /* 1743 * sip_ioctl: [ifnet interface function] 1744 * 1745 * Handle control requests from the operator. 1746 */ 1747 static int 1748 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1749 { 1750 struct sip_softc *sc = ifp->if_softc; 1751 struct ifreq *ifr = (struct ifreq *)data; 1752 int s, error; 1753 1754 s = splnet(); 1755 1756 switch (cmd) { 1757 case SIOCSIFMEDIA: 1758 /* Flow control requires full-duplex mode. */ 1759 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1760 (ifr->ifr_media & IFM_FDX) == 0) 1761 ifr->ifr_media &= ~IFM_ETH_FMASK; 1762 1763 /* XXX */ 1764 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1765 ifr->ifr_media &= ~IFM_ETH_FMASK; 1766 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1767 if (sc->sc_gigabit && 1768 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1769 /* We can do both TXPAUSE and RXPAUSE. */ 1770 ifr->ifr_media |= 1771 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1772 } else if (ifr->ifr_media & IFM_FLOW) { 1773 /* 1774 * Both TXPAUSE and RXPAUSE must be set. 1775 * (SiS900 and DP83815 don't have PAUSE_ASYM 1776 * feature.) 1777 * 1778 * XXX Can SiS900 and DP83815 send PAUSE? 1779 */ 1780 ifr->ifr_media |= 1781 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1782 } 1783 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1784 } 1785 /*FALLTHROUGH*/ 1786 default: 1787 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1788 break; 1789 1790 error = 0; 1791 1792 if (cmd == SIOCSIFCAP) 1793 error = (*ifp->if_init)(ifp); 1794 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1795 ; 1796 else if (ifp->if_flags & IFF_RUNNING) { 1797 /* 1798 * Multicast list has changed; set the hardware filter 1799 * accordingly. 1800 */ 1801 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1802 } 1803 break; 1804 } 1805 1806 /* Try to get more packets going. */ 1807 sipcom_start(ifp); 1808 1809 sc->sc_if_flags = ifp->if_flags; 1810 splx(s); 1811 return error; 1812 } 1813 1814 /* 1815 * sip_intr: 1816 * 1817 * Interrupt service routine. 1818 */ 1819 static int 1820 sipcom_intr(void *arg) 1821 { 1822 struct sip_softc *sc = arg; 1823 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1824 uint32_t isr; 1825 int handled = 0; 1826 1827 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 1828 return 0; 1829 1830 /* Disable interrupts. */ 1831 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1832 1833 for (;;) { 1834 /* Reading clears interrupt. */ 1835 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1836 if ((isr & sc->sc_imr) == 0) 1837 break; 1838 1839 rnd_add_uint32(&sc->rnd_source, isr); 1840 1841 handled = 1; 1842 1843 if ((ifp->if_flags & IFF_RUNNING) == 0) 1844 break; 1845 1846 if (isr & (ISR_RXORN | ISR_RXIDLE | ISR_RXDESC)) { 1847 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1848 1849 /* Grab any new packets. */ 1850 (*sc->sc_rxintr)(sc); 1851 1852 if (isr & ISR_RXORN) { 1853 printf("%s: receive FIFO overrun\n", 1854 device_xname(sc->sc_dev)); 1855 1856 /* XXX adjust rx_drain_thresh? */ 1857 } 1858 1859 if (isr & ISR_RXIDLE) { 1860 printf("%s: receive ring overrun\n", 1861 device_xname(sc->sc_dev)); 1862 1863 /* Get the receive process going again. */ 1864 bus_space_write_4(sc->sc_st, sc->sc_sh, 1865 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1866 bus_space_write_4(sc->sc_st, sc->sc_sh, 1867 SIP_CR, CR_RXE); 1868 } 1869 } 1870 1871 if (isr & (ISR_TXURN | ISR_TXDESC | ISR_TXIDLE)) { 1872 #ifdef SIP_EVENT_COUNTERS 1873 if (isr & ISR_TXDESC) 1874 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1875 else if (isr & ISR_TXIDLE) 1876 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1877 #endif 1878 1879 /* Sweep up transmit descriptors. */ 1880 sipcom_txintr(sc); 1881 1882 if (isr & ISR_TXURN) { 1883 uint32_t thresh; 1884 int txfifo_size = (sc->sc_gigabit) 1885 ? DP83820_SIP_TXFIFO_SIZE 1886 : OTHER_SIP_TXFIFO_SIZE; 1887 1888 printf("%s: transmit FIFO underrun", 1889 device_xname(sc->sc_dev)); 1890 thresh = sc->sc_tx_drain_thresh + 1; 1891 if (thresh <= __SHIFTOUT_MASK(sc->sc_bits.b_txcfg_drth_mask) 1892 && (thresh * 32) <= (txfifo_size - 1893 (sc->sc_tx_fill_thresh * 32))) { 1894 printf("; increasing Tx drain " 1895 "threshold to %u bytes\n", 1896 thresh * 32); 1897 sc->sc_tx_drain_thresh = thresh; 1898 (void) sipcom_init(ifp); 1899 } else { 1900 (void) sipcom_init(ifp); 1901 printf("\n"); 1902 } 1903 } 1904 } 1905 1906 if (sc->sc_imr & (ISR_PAUSE_END | ISR_PAUSE_ST)) { 1907 if (isr & ISR_PAUSE_ST) { 1908 sc->sc_paused = 1; 1909 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1910 ifp->if_flags |= IFF_OACTIVE; 1911 } 1912 if (isr & ISR_PAUSE_END) { 1913 sc->sc_paused = 0; 1914 ifp->if_flags &= ~IFF_OACTIVE; 1915 } 1916 } 1917 1918 if (isr & ISR_HIBERR) { 1919 int want_init = 0; 1920 1921 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1922 1923 #define PRINTERR(bit, str) \ 1924 do { \ 1925 if ((isr & (bit)) != 0) { \ 1926 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1927 printf("%s: %s\n", \ 1928 device_xname(sc->sc_dev), str); \ 1929 want_init = 1; \ 1930 } \ 1931 } while (/*CONSTCOND*/0) 1932 1933 PRINTERR(sc->sc_bits.b_isr_dperr, "parity error"); 1934 PRINTERR(sc->sc_bits.b_isr_sserr, "system error"); 1935 PRINTERR(sc->sc_bits.b_isr_rmabt, "master abort"); 1936 PRINTERR(sc->sc_bits.b_isr_rtabt, "target abort"); 1937 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1938 /* 1939 * Ignore: 1940 * Tx reset complete 1941 * Rx reset complete 1942 */ 1943 if (want_init) 1944 (void) sipcom_init(ifp); 1945 #undef PRINTERR 1946 } 1947 } 1948 1949 /* Re-enable interrupts. */ 1950 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1951 1952 /* Try to get more packets going. */ 1953 if_schedule_deferred_start(ifp); 1954 1955 return handled; 1956 } 1957 1958 /* 1959 * sip_txintr: 1960 * 1961 * Helper; handle transmit interrupts. 1962 */ 1963 static void 1964 sipcom_txintr(struct sip_softc *sc) 1965 { 1966 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1967 struct sip_txsoft *txs; 1968 uint32_t cmdsts; 1969 1970 if (sc->sc_paused == 0) 1971 ifp->if_flags &= ~IFF_OACTIVE; 1972 1973 /* 1974 * Go through our Tx list and free mbufs for those 1975 * frames which have been transmitted. 1976 */ 1977 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1978 sip_cdtxsync(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1979 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1980 1981 cmdsts = le32toh(*sipd_cmdsts(sc, 1982 &sc->sc_txdescs[txs->txs_lastdesc])); 1983 if (cmdsts & CMDSTS_OWN) 1984 break; 1985 1986 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1987 1988 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1989 1990 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1991 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1992 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1993 m_freem(txs->txs_mbuf); 1994 txs->txs_mbuf = NULL; 1995 1996 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1997 1998 /* Check for errors and collisions. */ 1999 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 2000 if (cmdsts & (CMDSTS_Tx_TXA | CMDSTS_Tx_TFU | CMDSTS_Tx_ED | 2001 CMDSTS_Tx_EC)) { 2002 if_statinc_ref(nsr, if_oerrors); 2003 if (cmdsts & CMDSTS_Tx_EC) 2004 if_statadd_ref(nsr, if_collisions, 16); 2005 if (ifp->if_flags & IFF_DEBUG) { 2006 if (cmdsts & CMDSTS_Tx_ED) 2007 printf("%s: excessive deferral\n", 2008 device_xname(sc->sc_dev)); 2009 if (cmdsts & CMDSTS_Tx_EC) 2010 printf("%s: excessive collisions\n", 2011 device_xname(sc->sc_dev)); 2012 } 2013 } else { 2014 /* Packet was transmitted successfully. */ 2015 if_statinc_ref(nsr, if_opackets); 2016 if (CMDSTS_COLLISIONS(cmdsts)) 2017 if_statadd_ref(nsr, if_collisions, 2018 CMDSTS_COLLISIONS(cmdsts)); 2019 } 2020 IF_STAT_PUTREF(ifp); 2021 } 2022 2023 /* 2024 * If there are no more pending transmissions, cancel the watchdog 2025 * timer. 2026 */ 2027 if (txs == NULL) { 2028 ifp->if_timer = 0; 2029 sc->sc_txwin = 0; 2030 } 2031 } 2032 2033 /* 2034 * gsip_rxintr: 2035 * 2036 * Helper; handle receive interrupts on gigabit parts. 2037 */ 2038 static void 2039 gsip_rxintr(struct sip_softc *sc) 2040 { 2041 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2042 struct sip_rxsoft *rxs; 2043 struct mbuf *m; 2044 uint32_t cmdsts, extsts; 2045 int i, len; 2046 2047 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2048 rxs = &sc->sc_rxsoft[i]; 2049 2050 sip_cdrxsync(sc, i, 2051 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2052 2053 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2054 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 2055 len = CMDSTS_SIZE(sc, cmdsts); 2056 2057 /* 2058 * NOTE: OWN is set if owned by _consumer_. We're the 2059 * consumer of the receive ring, so if the bit is clear, 2060 * we have processed all of the packets. 2061 */ 2062 if ((cmdsts & CMDSTS_OWN) == 0) { 2063 /* 2064 * We have processed all of the receive buffers. 2065 */ 2066 break; 2067 } 2068 2069 if (__predict_false(sc->sc_rxdiscard)) { 2070 sip_init_rxdesc(sc, i); 2071 if ((cmdsts & CMDSTS_MORE) == 0) { 2072 /* Reset our state. */ 2073 sc->sc_rxdiscard = 0; 2074 } 2075 continue; 2076 } 2077 2078 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2079 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2080 2081 m = rxs->rxs_mbuf; 2082 2083 /* 2084 * Add a new receive buffer to the ring. 2085 */ 2086 if (sipcom_add_rxbuf(sc, i) != 0) { 2087 /* 2088 * Failed, throw away what we've done so 2089 * far, and discard the rest of the packet. 2090 */ 2091 if_statinc(ifp, if_ierrors); 2092 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2093 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2094 sip_init_rxdesc(sc, i); 2095 if (cmdsts & CMDSTS_MORE) 2096 sc->sc_rxdiscard = 1; 2097 if (sc->sc_rxhead != NULL) 2098 m_freem(sc->sc_rxhead); 2099 sip_rxchain_reset(sc); 2100 continue; 2101 } 2102 2103 sip_rxchain_link(sc, m); 2104 2105 m->m_len = len; 2106 2107 /* 2108 * If this is not the end of the packet, keep 2109 * looking. 2110 */ 2111 if (cmdsts & CMDSTS_MORE) { 2112 sc->sc_rxlen += len; 2113 continue; 2114 } 2115 2116 /* 2117 * Okay, we have the entire packet now. The chip includes 2118 * the FCS, so we need to trim it. 2119 */ 2120 m->m_len -= ETHER_CRC_LEN; 2121 2122 *sc->sc_rxtailp = NULL; 2123 len = m->m_len + sc->sc_rxlen; 2124 m = sc->sc_rxhead; 2125 2126 sip_rxchain_reset(sc); 2127 2128 /* If an error occurred, update stats and drop the packet. */ 2129 if (cmdsts & (CMDSTS_Rx_RXA | CMDSTS_Rx_RUNT | 2130 CMDSTS_Rx_ISE | CMDSTS_Rx_CRCE | CMDSTS_Rx_FAE)) { 2131 if_statinc(ifp, if_ierrors); 2132 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2133 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2134 /* Receive overrun handled elsewhere. */ 2135 printf("%s: receive descriptor error\n", 2136 device_xname(sc->sc_dev)); 2137 } 2138 #define PRINTERR(bit, str) \ 2139 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2140 (cmdsts & (bit)) != 0) \ 2141 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2142 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2143 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2144 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2145 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2146 #undef PRINTERR 2147 m_freem(m); 2148 continue; 2149 } 2150 2151 /* 2152 * If the packet is small enough to fit in a 2153 * single header mbuf, allocate one and copy 2154 * the data into it. This greatly reduces 2155 * memory consumption when we receive lots 2156 * of small packets. 2157 */ 2158 if (gsip_copy_small != 0 && len <= (MHLEN - 2)) { 2159 struct mbuf *nm; 2160 MGETHDR(nm, M_DONTWAIT, MT_DATA); 2161 if (nm == NULL) { 2162 if_statinc(ifp, if_ierrors); 2163 m_freem(m); 2164 continue; 2165 } 2166 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2167 nm->m_data += 2; 2168 nm->m_pkthdr.len = nm->m_len = len; 2169 m_copydata(m, 0, len, mtod(nm, void *)); 2170 m_freem(m); 2171 m = nm; 2172 } 2173 #ifndef __NO_STRICT_ALIGNMENT 2174 else { 2175 /* 2176 * The DP83820's receive buffers must be 4-byte 2177 * aligned. But this means that the data after 2178 * the Ethernet header is misaligned. To compensate, 2179 * we have artificially shortened the buffer size 2180 * in the descriptor, and we do an overlapping copy 2181 * of the data two bytes further in (in the first 2182 * buffer of the chain only). 2183 */ 2184 memmove(mtod(m, char *) + 2, mtod(m, void *), 2185 m->m_len); 2186 m->m_data += 2; 2187 } 2188 #endif /* ! __NO_STRICT_ALIGNMENT */ 2189 2190 /* 2191 * If VLANs are enabled, VLAN packets have been unwrapped 2192 * for us. Associate the tag with the packet. 2193 */ 2194 2195 /* 2196 * Again, byte swapping is tricky. Hardware provided 2197 * the tag in the network byte order, but extsts was 2198 * passed through le32toh() in the meantime. On a 2199 * big-endian machine, we need to swap it again. On a 2200 * little-endian machine, we need to convert from the 2201 * network to host byte order. This means that we must 2202 * swap it in any case, so unconditional swap instead 2203 * of htons() is used. 2204 */ 2205 if ((extsts & EXTSTS_VPKT) != 0) { 2206 vlan_set_tag(m, bswap16(extsts & EXTSTS_VTCI)); 2207 } 2208 2209 /* 2210 * Set the incoming checksum information for the 2211 * packet. 2212 */ 2213 if ((extsts & EXTSTS_IPPKT) != 0) { 2214 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2215 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2216 if (extsts & EXTSTS_Rx_IPERR) 2217 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2218 if (extsts & EXTSTS_TCPPKT) { 2219 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2220 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2221 if (extsts & EXTSTS_Rx_TCPERR) 2222 m->m_pkthdr.csum_flags |= 2223 M_CSUM_TCP_UDP_BAD; 2224 } else if (extsts & EXTSTS_UDPPKT) { 2225 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2226 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2227 if (extsts & EXTSTS_Rx_UDPERR) 2228 m->m_pkthdr.csum_flags |= 2229 M_CSUM_TCP_UDP_BAD; 2230 } 2231 } 2232 2233 m_set_rcvif(m, ifp); 2234 m->m_pkthdr.len = len; 2235 2236 /* Pass it on. */ 2237 if_percpuq_enqueue(ifp->if_percpuq, m); 2238 } 2239 2240 /* Update the receive pointer. */ 2241 sc->sc_rxptr = i; 2242 } 2243 2244 /* 2245 * sip_rxintr: 2246 * 2247 * Helper; handle receive interrupts on 10/100 parts. 2248 */ 2249 static void 2250 sip_rxintr(struct sip_softc *sc) 2251 { 2252 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2253 struct sip_rxsoft *rxs; 2254 struct mbuf *m; 2255 uint32_t cmdsts; 2256 int i, len; 2257 2258 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2259 rxs = &sc->sc_rxsoft[i]; 2260 2261 sip_cdrxsync(sc, i, 2262 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2263 2264 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2265 2266 /* 2267 * NOTE: OWN is set if owned by _consumer_. We're the 2268 * consumer of the receive ring, so if the bit is clear, 2269 * we have processed all of the packets. 2270 */ 2271 if ((cmdsts & CMDSTS_OWN) == 0) { 2272 /* 2273 * We have processed all of the receive buffers. 2274 */ 2275 break; 2276 } 2277 2278 /* If any collisions were seen on the wire, count one. */ 2279 if (cmdsts & CMDSTS_Rx_COL) 2280 if_statinc(ifp, if_collisions); 2281 2282 /* 2283 * If an error occurred, update stats, clear the status 2284 * word, and leave the packet buffer in place. It will 2285 * simply be reused the next time the ring comes around. 2286 */ 2287 if (cmdsts & (CMDSTS_Rx_RXA | CMDSTS_Rx_RUNT | 2288 CMDSTS_Rx_ISE | CMDSTS_Rx_CRCE | CMDSTS_Rx_FAE)) { 2289 if_statinc(ifp, if_ierrors); 2290 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2291 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2292 /* Receive overrun handled elsewhere. */ 2293 printf("%s: receive descriptor error\n", 2294 device_xname(sc->sc_dev)); 2295 } 2296 #define PRINTERR(bit, str) \ 2297 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2298 (cmdsts & (bit)) != 0) \ 2299 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2300 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2301 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2302 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2303 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2304 #undef PRINTERR 2305 sip_init_rxdesc(sc, i); 2306 continue; 2307 } 2308 2309 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2310 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2311 2312 /* 2313 * No errors; receive the packet. Note, the SiS 900 2314 * includes the CRC with every packet. 2315 */ 2316 len = CMDSTS_SIZE(sc, cmdsts) - ETHER_CRC_LEN; 2317 2318 #ifdef __NO_STRICT_ALIGNMENT 2319 /* 2320 * If the packet is small enough to fit in a 2321 * single header mbuf, allocate one and copy 2322 * the data into it. This greatly reduces 2323 * memory consumption when we receive lots 2324 * of small packets. 2325 * 2326 * Otherwise, we add a new buffer to the receive 2327 * chain. If this fails, we drop the packet and 2328 * recycle the old buffer. 2329 */ 2330 if (sip_copy_small != 0 && len <= MHLEN) { 2331 MGETHDR(m, M_DONTWAIT, MT_DATA); 2332 if (m == NULL) 2333 goto dropit; 2334 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2335 memcpy(mtod(m, void *), 2336 mtod(rxs->rxs_mbuf, void *), len); 2337 sip_init_rxdesc(sc, i); 2338 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2339 rxs->rxs_dmamap->dm_mapsize, 2340 BUS_DMASYNC_PREREAD); 2341 } else { 2342 m = rxs->rxs_mbuf; 2343 if (sipcom_add_rxbuf(sc, i) != 0) { 2344 dropit: 2345 if_statinc(ifp, if_ierrors); 2346 sip_init_rxdesc(sc, i); 2347 bus_dmamap_sync(sc->sc_dmat, 2348 rxs->rxs_dmamap, 0, 2349 rxs->rxs_dmamap->dm_mapsize, 2350 BUS_DMASYNC_PREREAD); 2351 continue; 2352 } 2353 } 2354 #else 2355 /* 2356 * The SiS 900's receive buffers must be 4-byte aligned. 2357 * But this means that the data after the Ethernet header 2358 * is misaligned. We must allocate a new buffer and 2359 * copy the data, shifted forward 2 bytes. 2360 */ 2361 MGETHDR(m, M_DONTWAIT, MT_DATA); 2362 if (m == NULL) { 2363 dropit: 2364 if_statinc(ifp, if_ierrors); 2365 sip_init_rxdesc(sc, i); 2366 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2367 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2368 continue; 2369 } 2370 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2371 if (len > (MHLEN - 2)) { 2372 MCLGET(m, M_DONTWAIT); 2373 if ((m->m_flags & M_EXT) == 0) { 2374 m_freem(m); 2375 goto dropit; 2376 } 2377 } 2378 m->m_data += 2; 2379 2380 /* 2381 * Note that we use clusters for incoming frames, so the 2382 * buffer is virtually contiguous. 2383 */ 2384 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2385 2386 /* Allow the receive descriptor to continue using its mbuf. */ 2387 sip_init_rxdesc(sc, i); 2388 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2389 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2390 #endif /* __NO_STRICT_ALIGNMENT */ 2391 2392 m_set_rcvif(m, ifp); 2393 m->m_pkthdr.len = m->m_len = len; 2394 2395 /* Pass it on. */ 2396 if_percpuq_enqueue(ifp->if_percpuq, m); 2397 } 2398 2399 /* Update the receive pointer. */ 2400 sc->sc_rxptr = i; 2401 } 2402 2403 /* 2404 * sip_tick: 2405 * 2406 * One second timer, used to tick the MII. 2407 */ 2408 static void 2409 sipcom_tick(void *arg) 2410 { 2411 struct sip_softc *sc = arg; 2412 int s; 2413 2414 s = splnet(); 2415 #ifdef SIP_EVENT_COUNTERS 2416 if (sc->sc_gigabit) { 2417 /* Read PAUSE related counts from MIB registers. */ 2418 sc->sc_ev_rxpause.ev_count += 2419 bus_space_read_4(sc->sc_st, sc->sc_sh, 2420 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2421 sc->sc_ev_txpause.ev_count += 2422 bus_space_read_4(sc->sc_st, sc->sc_sh, 2423 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2424 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2425 } 2426 #endif /* SIP_EVENT_COUNTERS */ 2427 mii_tick(&sc->sc_mii); 2428 splx(s); 2429 2430 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2431 } 2432 2433 /* 2434 * sip_reset: 2435 * 2436 * Perform a soft reset on the SiS 900. 2437 */ 2438 static bool 2439 sipcom_reset(struct sip_softc *sc) 2440 { 2441 bus_space_tag_t st = sc->sc_st; 2442 bus_space_handle_t sh = sc->sc_sh; 2443 int i; 2444 2445 bus_space_write_4(st, sh, SIP_IER, 0); 2446 bus_space_write_4(st, sh, SIP_IMR, 0); 2447 bus_space_write_4(st, sh, SIP_RFCR, 0); 2448 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2449 2450 for (i = 0; i < SIP_TIMEOUT; i++) { 2451 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2452 break; 2453 delay(2); 2454 } 2455 2456 if (i == SIP_TIMEOUT) { 2457 printf("%s: reset failed to complete\n", 2458 device_xname(sc->sc_dev)); 2459 return false; 2460 } 2461 2462 delay(1000); 2463 2464 if (sc->sc_gigabit) { 2465 /* 2466 * Set the general purpose I/O bits. Do it here in case we 2467 * need to have GPIO set up to talk to the media interface. 2468 */ 2469 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2470 delay(1000); 2471 } 2472 return true; 2473 } 2474 2475 static void 2476 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2477 { 2478 uint32_t reg; 2479 bus_space_tag_t st = sc->sc_st; 2480 bus_space_handle_t sh = sc->sc_sh; 2481 /* 2482 * Initialize the VLAN/IP receive control register. 2483 * We enable checksum computation on all incoming 2484 * packets, and do not reject packets w/ bad checksums. 2485 */ 2486 reg = 0; 2487 if (capenable & 2488 (IFCAP_CSUM_IPv4_Rx | IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 2489 reg |= VRCR_IPEN; 2490 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2491 reg |= VRCR_VTDEN | VRCR_VTREN; 2492 bus_space_write_4(st, sh, SIP_VRCR, reg); 2493 2494 /* 2495 * Initialize the VLAN/IP transmit control register. 2496 * We enable outgoing checksum computation on a 2497 * per-packet basis. 2498 */ 2499 reg = 0; 2500 if (capenable & 2501 (IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx)) 2502 reg |= VTCR_PPCHK; 2503 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2504 reg |= VTCR_VPPTI; 2505 bus_space_write_4(st, sh, SIP_VTCR, reg); 2506 2507 /* 2508 * If we're using VLANs, initialize the VLAN data register. 2509 * To understand why we bswap the VLAN Ethertype, see section 2510 * 4.2.36 of the DP83820 manual. 2511 */ 2512 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2513 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2514 } 2515 2516 /* 2517 * sip_init: [ ifnet interface function ] 2518 * 2519 * Initialize the interface. Must be called at splnet(). 2520 */ 2521 static int 2522 sipcom_init(struct ifnet *ifp) 2523 { 2524 struct sip_softc *sc = ifp->if_softc; 2525 bus_space_tag_t st = sc->sc_st; 2526 bus_space_handle_t sh = sc->sc_sh; 2527 struct sip_txsoft *txs; 2528 struct sip_rxsoft *rxs; 2529 struct sip_desc *sipd; 2530 int i, error = 0; 2531 2532 if (device_is_active(sc->sc_dev)) { 2533 /* 2534 * Cancel any pending I/O. 2535 */ 2536 sipcom_stop(ifp, 0); 2537 } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 2538 !device_is_active(sc->sc_dev)) 2539 return 0; 2540 2541 /* 2542 * Reset the chip to a known state. 2543 */ 2544 if (!sipcom_reset(sc)) 2545 return EBUSY; 2546 2547 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2548 /* 2549 * DP83815 manual, page 78: 2550 * 4.4 Recommended Registers Configuration 2551 * For optimum performance of the DP83815, version noted 2552 * as DP83815CVNG (SRR = 203h), the listed register 2553 * modifications must be followed in sequence... 2554 * 2555 * It's not clear if this should be 302h or 203h because that 2556 * chip name is listed as SRR 302h in the description of the 2557 * SRR register. However, my revision 302h DP83815 on the 2558 * Netgear FA311 purchased in 02/2001 needs these settings 2559 * to avoid tons of errors in AcceptPerfectMatch (non- 2560 * IFF_PROMISC) mode. I do not know if other revisions need 2561 * this set or not. [briggs -- 09 March 2001] 2562 * 2563 * Note that only the low-order 12 bits of 0xe4 are documented 2564 * and that this sets reserved bits in that register. 2565 */ 2566 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2567 2568 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2569 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2570 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2571 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2572 2573 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2574 } 2575 2576 /* 2577 * Initialize the transmit descriptor ring. 2578 */ 2579 for (i = 0; i < sc->sc_ntxdesc; i++) { 2580 sipd = &sc->sc_txdescs[i]; 2581 memset(sipd, 0, sizeof(struct sip_desc)); 2582 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, sip_nexttx(sc, i))); 2583 } 2584 sip_cdtxsync(sc, 0, sc->sc_ntxdesc, 2585 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2586 sc->sc_txfree = sc->sc_ntxdesc; 2587 sc->sc_txnext = 0; 2588 sc->sc_txwin = 0; 2589 2590 /* 2591 * Initialize the transmit job descriptors. 2592 */ 2593 SIMPLEQ_INIT(&sc->sc_txfreeq); 2594 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2595 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2596 txs = &sc->sc_txsoft[i]; 2597 txs->txs_mbuf = NULL; 2598 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2599 } 2600 2601 /* 2602 * Initialize the receive descriptor and receive job 2603 * descriptor rings. 2604 */ 2605 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2606 rxs = &sc->sc_rxsoft[i]; 2607 if (rxs->rxs_mbuf == NULL) { 2608 if ((error = sipcom_add_rxbuf(sc, i)) != 0) { 2609 printf("%s: unable to allocate or map rx " 2610 "buffer %d, error = %d\n", 2611 device_xname(sc->sc_dev), i, error); 2612 /* 2613 * XXX Should attempt to run with fewer receive 2614 * XXX buffers instead of just failing. 2615 */ 2616 sipcom_rxdrain(sc); 2617 goto out; 2618 } 2619 } else 2620 sip_init_rxdesc(sc, i); 2621 } 2622 sc->sc_rxptr = 0; 2623 sc->sc_rxdiscard = 0; 2624 sip_rxchain_reset(sc); 2625 2626 /* 2627 * Set the configuration register; it's already initialized 2628 * in sip_attach(). 2629 */ 2630 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2631 2632 /* 2633 * Initialize the prototype TXCFG register. 2634 */ 2635 if (sc->sc_gigabit) { 2636 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2637 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2638 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2639 SIP_SIS900_REV(sc, SIS_REV_960) || 2640 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2641 (sc->sc_cfg & CFG_EDBMASTEN)) { 2642 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_64; 2643 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_64; 2644 } else { 2645 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2646 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2647 } 2648 2649 sc->sc_txcfg |= TXCFG_ATP | 2650 __SHIFTIN(sc->sc_tx_fill_thresh, sc->sc_bits.b_txcfg_flth_mask) | 2651 sc->sc_tx_drain_thresh; 2652 bus_space_write_4(st, sh, sc->sc_regs.r_txcfg, sc->sc_txcfg); 2653 2654 /* 2655 * Initialize the receive drain threshold if we have never 2656 * done so. 2657 */ 2658 if (sc->sc_rx_drain_thresh == 0) { 2659 /* 2660 * XXX This value should be tuned. This is set to the 2661 * maximum of 248 bytes, and we may be able to improve 2662 * performance by decreasing it (although we should never 2663 * set this value lower than 2; 14 bytes are required to 2664 * filter the packet). 2665 */ 2666 sc->sc_rx_drain_thresh = __SHIFTOUT_MASK(RXCFG_DRTH_MASK); 2667 } 2668 2669 /* 2670 * Initialize the prototype RXCFG register. 2671 */ 2672 sc->sc_rxcfg |= __SHIFTIN(sc->sc_rx_drain_thresh, RXCFG_DRTH_MASK); 2673 /* 2674 * Accept long packets (including FCS) so we can handle 2675 * 802.1q-tagged frames and jumbo frames properly. 2676 */ 2677 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2678 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2679 sc->sc_rxcfg |= RXCFG_ALP; 2680 2681 /* 2682 * Checksum offloading is disabled if the user selects an MTU 2683 * larger than 8109. (FreeBSD says 8152, but there is emperical 2684 * evidence that >8109 does not work on some boards, such as the 2685 * Planex GN-1000TE). 2686 */ 2687 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2688 (ifp->if_capenable & 2689 (IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2690 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2691 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx))) { 2692 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2693 "disabled.\n", device_xname(sc->sc_dev)); 2694 ifp->if_capenable &= 2695 ~(IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2696 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2697 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx); 2698 ifp->if_csum_flags_tx = 0; 2699 ifp->if_csum_flags_rx = 0; 2700 } 2701 2702 bus_space_write_4(st, sh, sc->sc_regs.r_rxcfg, sc->sc_rxcfg); 2703 2704 if (sc->sc_gigabit) 2705 sipcom_dp83820_init(sc, ifp->if_capenable); 2706 2707 /* 2708 * Give the transmit and receive rings to the chip. 2709 */ 2710 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2711 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2712 2713 /* 2714 * Initialize the interrupt mask. 2715 */ 2716 sc->sc_imr = sc->sc_bits.b_isr_dperr | 2717 sc->sc_bits.b_isr_sserr | 2718 sc->sc_bits.b_isr_rmabt | 2719 sc->sc_bits.b_isr_rtabt | 2720 ISR_RXSOVR | ISR_TXURN | ISR_TXDESC | ISR_TXIDLE | ISR_RXORN | 2721 ISR_RXIDLE | ISR_RXDESC; 2722 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2723 2724 /* Set up the receive filter. */ 2725 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2726 2727 /* 2728 * Tune sc_rx_flow_thresh. 2729 * XXX "More than 8KB" is too short for jumbo frames. 2730 * XXX TODO: Threshold value should be user-settable. 2731 */ 2732 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2733 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2734 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2735 2736 /* 2737 * Set the current media. Do this after initializing the prototype 2738 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2739 * control. 2740 */ 2741 if ((error = ether_mediachange(ifp)) != 0) 2742 goto out; 2743 2744 /* 2745 * Set the interrupt hold-off timer to 100us. 2746 */ 2747 if (sc->sc_gigabit) 2748 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2749 2750 /* 2751 * Enable interrupts. 2752 */ 2753 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2754 2755 /* 2756 * Start the transmit and receive processes. 2757 */ 2758 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2759 2760 /* 2761 * Start the one second MII clock. 2762 */ 2763 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2764 2765 /* 2766 * ...all done! 2767 */ 2768 ifp->if_flags |= IFF_RUNNING; 2769 ifp->if_flags &= ~IFF_OACTIVE; 2770 sc->sc_if_flags = ifp->if_flags; 2771 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2772 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2773 sc->sc_prev.if_capenable = ifp->if_capenable; 2774 2775 out: 2776 if (error) 2777 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 2778 return error; 2779 } 2780 2781 /* 2782 * sip_drain: 2783 * 2784 * Drain the receive queue. 2785 */ 2786 static void 2787 sipcom_rxdrain(struct sip_softc *sc) 2788 { 2789 struct sip_rxsoft *rxs; 2790 int i; 2791 2792 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2793 rxs = &sc->sc_rxsoft[i]; 2794 if (rxs->rxs_mbuf != NULL) { 2795 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2796 m_freem(rxs->rxs_mbuf); 2797 rxs->rxs_mbuf = NULL; 2798 } 2799 } 2800 } 2801 2802 /* 2803 * sip_stop: [ ifnet interface function ] 2804 * 2805 * Stop transmission on the interface. 2806 */ 2807 static void 2808 sipcom_stop(struct ifnet *ifp, int disable) 2809 { 2810 struct sip_softc *sc = ifp->if_softc; 2811 bus_space_tag_t st = sc->sc_st; 2812 bus_space_handle_t sh = sc->sc_sh; 2813 struct sip_txsoft *txs; 2814 uint32_t cmdsts = 0; /* DEBUG */ 2815 2816 /* 2817 * Stop the one second clock. 2818 */ 2819 callout_stop(&sc->sc_tick_ch); 2820 2821 /* Down the MII. */ 2822 mii_down(&sc->sc_mii); 2823 2824 if (device_is_active(sc->sc_dev)) { 2825 /* 2826 * Disable interrupts. 2827 */ 2828 bus_space_write_4(st, sh, SIP_IER, 0); 2829 2830 /* 2831 * Stop receiver and transmitter. 2832 */ 2833 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2834 } 2835 2836 /* 2837 * Release any queued transmit buffers. 2838 */ 2839 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2840 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2841 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2842 (le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])) & 2843 CMDSTS_INTR) == 0) 2844 printf("%s: sip_stop: last descriptor does not " 2845 "have INTR bit set\n", device_xname(sc->sc_dev)); 2846 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2847 #ifdef DIAGNOSTIC 2848 if (txs->txs_mbuf == NULL) { 2849 printf("%s: dirty txsoft with no mbuf chain\n", 2850 device_xname(sc->sc_dev)); 2851 panic("sip_stop"); 2852 } 2853 #endif 2854 cmdsts |= /* DEBUG */ 2855 le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 2856 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2857 m_freem(txs->txs_mbuf); 2858 txs->txs_mbuf = NULL; 2859 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2860 } 2861 2862 /* 2863 * Mark the interface down and cancel the watchdog timer. 2864 */ 2865 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2866 ifp->if_timer = 0; 2867 2868 if (disable) 2869 pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); 2870 2871 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2872 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2873 printf("%s: sip_stop: no INTR bits set in dirty tx " 2874 "descriptors\n", device_xname(sc->sc_dev)); 2875 } 2876 2877 /* 2878 * sip_read_eeprom: 2879 * 2880 * Read data from the serial EEPROM. 2881 */ 2882 static void 2883 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2884 uint16_t *data) 2885 { 2886 bus_space_tag_t st = sc->sc_st; 2887 bus_space_handle_t sh = sc->sc_sh; 2888 uint16_t reg; 2889 int i, x; 2890 2891 for (i = 0; i < wordcnt; i++) { 2892 /* Send CHIP SELECT. */ 2893 reg = EROMAR_EECS; 2894 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2895 2896 /* Shift in the READ opcode. */ 2897 for (x = 3; x > 0; x--) { 2898 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2899 reg |= EROMAR_EEDI; 2900 else 2901 reg &= ~EROMAR_EEDI; 2902 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2903 bus_space_write_4(st, sh, SIP_EROMAR, 2904 reg | EROMAR_EESK); 2905 delay(4); 2906 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2907 delay(4); 2908 } 2909 2910 /* Shift in address. */ 2911 for (x = 6; x > 0; x--) { 2912 if ((word + i) & (1 << (x - 1))) 2913 reg |= EROMAR_EEDI; 2914 else 2915 reg &= ~EROMAR_EEDI; 2916 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2917 bus_space_write_4(st, sh, SIP_EROMAR, 2918 reg | EROMAR_EESK); 2919 delay(4); 2920 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2921 delay(4); 2922 } 2923 2924 /* Shift out data. */ 2925 reg = EROMAR_EECS; 2926 data[i] = 0; 2927 for (x = 16; x > 0; x--) { 2928 bus_space_write_4(st, sh, SIP_EROMAR, 2929 reg | EROMAR_EESK); 2930 delay(4); 2931 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2932 data[i] |= (1 << (x - 1)); 2933 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2934 delay(4); 2935 } 2936 2937 /* Clear CHIP SELECT. */ 2938 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2939 delay(4); 2940 } 2941 } 2942 2943 /* 2944 * sipcom_add_rxbuf: 2945 * 2946 * Add a receive buffer to the indicated descriptor. 2947 */ 2948 static int 2949 sipcom_add_rxbuf(struct sip_softc *sc, int idx) 2950 { 2951 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2952 struct mbuf *m; 2953 int error; 2954 2955 MGETHDR(m, M_DONTWAIT, MT_DATA); 2956 if (m == NULL) 2957 return ENOBUFS; 2958 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2959 2960 MCLGET(m, M_DONTWAIT); 2961 if ((m->m_flags & M_EXT) == 0) { 2962 m_freem(m); 2963 return ENOBUFS; 2964 } 2965 2966 /* XXX I don't believe this is necessary. --dyoung */ 2967 if (sc->sc_gigabit) 2968 m->m_len = sc->sc_parm->p_rxbuf_len; 2969 2970 if (rxs->rxs_mbuf != NULL) 2971 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2972 2973 rxs->rxs_mbuf = m; 2974 2975 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2976 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2977 BUS_DMA_READ | BUS_DMA_NOWAIT); 2978 if (error) { 2979 printf("%s: can't load rx DMA map %d, error = %d\n", 2980 device_xname(sc->sc_dev), idx, error); 2981 panic("%s", __func__); /* XXX */ 2982 } 2983 2984 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2985 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2986 2987 sip_init_rxdesc(sc, idx); 2988 2989 return 0; 2990 } 2991 2992 /* 2993 * sip_sis900_set_filter: 2994 * 2995 * Set up the receive filter. 2996 */ 2997 static void 2998 sipcom_sis900_set_filter(struct sip_softc *sc) 2999 { 3000 bus_space_tag_t st = sc->sc_st; 3001 bus_space_handle_t sh = sc->sc_sh; 3002 struct ethercom *ec = &sc->sc_ethercom; 3003 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3004 struct ether_multi *enm; 3005 const uint8_t *cp; 3006 struct ether_multistep step; 3007 uint32_t crc, mchash[16]; 3008 3009 /* 3010 * Initialize the prototype RFCR. 3011 */ 3012 sc->sc_rfcr = RFCR_RFEN; 3013 if (ifp->if_flags & IFF_BROADCAST) 3014 sc->sc_rfcr |= RFCR_AAB; 3015 if (ifp->if_flags & IFF_PROMISC) { 3016 sc->sc_rfcr |= RFCR_AAP; 3017 goto allmulti; 3018 } 3019 3020 /* 3021 * Set up the multicast address filter by passing all multicast 3022 * addresses through a CRC generator, and then using the high-order 3023 * 6 bits as an index into the 128 bit multicast hash table (only 3024 * the lower 16 bits of each 32 bit multicast hash register are 3025 * valid). The high order bits select the register, while the 3026 * rest of the bits select the bit within the register. 3027 */ 3028 3029 memset(mchash, 0, sizeof(mchash)); 3030 3031 /* 3032 * SiS900 (at least SiS963) requires us to register the address of 3033 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 3034 */ 3035 crc = 0x0ed423f9; 3036 3037 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3038 SIP_SIS900_REV(sc, SIS_REV_960) || 3039 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3040 /* Just want the 8 most significant bits. */ 3041 crc >>= 24; 3042 } else { 3043 /* Just want the 7 most significant bits. */ 3044 crc >>= 25; 3045 } 3046 3047 /* Set the corresponding bit in the hash table. */ 3048 mchash[crc >> 4] |= 1 << (crc & 0xf); 3049 3050 ETHER_LOCK(ec); 3051 ETHER_FIRST_MULTI(step, ec, enm); 3052 while (enm != NULL) { 3053 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3054 /* 3055 * We must listen to a range of multicast addresses. 3056 * For now, just accept all multicasts, rather than 3057 * trying to set only those filter bits needed to match 3058 * the range. (At this time, the only use of address 3059 * ranges is for IP multicast routing, for which the 3060 * range is big enough to require all bits set.) 3061 */ 3062 ETHER_UNLOCK(ec); 3063 goto allmulti; 3064 } 3065 3066 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3067 3068 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3069 SIP_SIS900_REV(sc, SIS_REV_960) || 3070 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3071 /* Just want the 8 most significant bits. */ 3072 crc >>= 24; 3073 } else { 3074 /* Just want the 7 most significant bits. */ 3075 crc >>= 25; 3076 } 3077 3078 /* Set the corresponding bit in the hash table. */ 3079 mchash[crc >> 4] |= 1 << (crc & 0xf); 3080 3081 ETHER_NEXT_MULTI(step, enm); 3082 } 3083 ETHER_UNLOCK(ec); 3084 3085 ifp->if_flags &= ~IFF_ALLMULTI; 3086 goto setit; 3087 3088 allmulti: 3089 ifp->if_flags |= IFF_ALLMULTI; 3090 sc->sc_rfcr |= RFCR_AAM; 3091 3092 setit: 3093 #define FILTER_EMIT(addr, data) \ 3094 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3095 delay(1); \ 3096 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3097 delay(1) 3098 3099 /* 3100 * Disable receive filter, and program the node address. 3101 */ 3102 cp = CLLADDR(ifp->if_sadl); 3103 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 3104 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 3105 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 3106 3107 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3108 /* 3109 * Program the multicast hash table. 3110 */ 3111 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 3112 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 3113 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 3114 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 3115 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 3116 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 3117 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 3118 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 3119 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3120 SIP_SIS900_REV(sc, SIS_REV_960) || 3121 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3122 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 3123 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 3124 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 3125 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 3126 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 3127 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 3128 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 3129 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 3130 } 3131 } 3132 #undef FILTER_EMIT 3133 3134 /* 3135 * Re-enable the receiver filter. 3136 */ 3137 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3138 } 3139 3140 /* 3141 * sip_dp83815_set_filter: 3142 * 3143 * Set up the receive filter. 3144 */ 3145 static void 3146 sipcom_dp83815_set_filter(struct sip_softc *sc) 3147 { 3148 bus_space_tag_t st = sc->sc_st; 3149 bus_space_handle_t sh = sc->sc_sh; 3150 struct ethercom *ec = &sc->sc_ethercom; 3151 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3152 struct ether_multi *enm; 3153 const uint8_t *cp; 3154 struct ether_multistep step; 3155 uint32_t crc, hash, slot, bit; 3156 #define MCHASH_NWORDS_83820 128 3157 #define MCHASH_NWORDS_83815 32 3158 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3159 uint16_t mchash[MCHASH_NWORDS]; 3160 int i; 3161 3162 /* 3163 * Initialize the prototype RFCR. 3164 * Enable the receive filter, and accept on 3165 * Perfect (destination address) Match 3166 * If IFF_BROADCAST, also accept all broadcast packets. 3167 * If IFF_PROMISC, accept all unicast packets (and later, set 3168 * IFF_ALLMULTI and accept all multicast, too). 3169 */ 3170 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3171 if (ifp->if_flags & IFF_BROADCAST) 3172 sc->sc_rfcr |= RFCR_AAB; 3173 if (ifp->if_flags & IFF_PROMISC) { 3174 sc->sc_rfcr |= RFCR_AAP; 3175 goto allmulti; 3176 } 3177 3178 /* 3179 * Set up the DP83820/DP83815 multicast address filter by 3180 * passing all multicast addresses through a CRC generator, 3181 * and then using the high-order 11/9 bits as an index into 3182 * the 2048/512 bit multicast hash table. The high-order 3183 * 7/5 bits select the slot, while the low-order 4 bits 3184 * select the bit within the slot. Note that only the low 3185 * 16-bits of each filter word are used, and there are 3186 * 128/32 filter words. 3187 */ 3188 3189 memset(mchash, 0, sizeof(mchash)); 3190 3191 ifp->if_flags &= ~IFF_ALLMULTI; 3192 ETHER_FIRST_MULTI(step, ec, enm); 3193 if (enm == NULL) 3194 goto setit; 3195 while (enm != NULL) { 3196 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3197 /* 3198 * We must listen to a range of multicast addresses. 3199 * For now, just accept all multicasts, rather than 3200 * trying to set only those filter bits needed to match 3201 * the range. (At this time, the only use of address 3202 * ranges is for IP multicast routing, for which the 3203 * range is big enough to require all bits set.) 3204 */ 3205 goto allmulti; 3206 } 3207 3208 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3209 3210 if (sc->sc_gigabit) { 3211 /* Just want the 11 most significant bits. */ 3212 hash = crc >> 21; 3213 } else { 3214 /* Just want the 9 most significant bits. */ 3215 hash = crc >> 23; 3216 } 3217 3218 slot = hash >> 4; 3219 bit = hash & 0xf; 3220 3221 /* Set the corresponding bit in the hash table. */ 3222 mchash[slot] |= 1 << bit; 3223 3224 ETHER_NEXT_MULTI(step, enm); 3225 } 3226 sc->sc_rfcr |= RFCR_MHEN; 3227 goto setit; 3228 3229 allmulti: 3230 ifp->if_flags |= IFF_ALLMULTI; 3231 sc->sc_rfcr |= RFCR_AAM; 3232 3233 setit: 3234 #define FILTER_EMIT(addr, data) \ 3235 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3236 delay(1); \ 3237 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3238 delay(1) 3239 3240 /* 3241 * Disable receive filter, and program the node address. 3242 */ 3243 cp = CLLADDR(ifp->if_sadl); 3244 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3245 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3246 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3247 3248 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3249 int nwords = 3250 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3251 /* 3252 * Program the multicast hash table. 3253 */ 3254 for (i = 0; i < nwords; i++) { 3255 FILTER_EMIT(sc->sc_parm->p_filtmem + (i * 2), mchash[i]); 3256 } 3257 } 3258 #undef FILTER_EMIT 3259 #undef MCHASH_NWORDS 3260 #undef MCHASH_NWORDS_83815 3261 #undef MCHASH_NWORDS_83820 3262 3263 /* 3264 * Re-enable the receiver filter. 3265 */ 3266 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3267 } 3268 3269 /* 3270 * sip_dp83820_mii_readreg: [mii interface function] 3271 * 3272 * Read a PHY register on the MII of the DP83820. 3273 */ 3274 static int 3275 sipcom_dp83820_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3276 { 3277 struct sip_softc *sc = device_private(self); 3278 3279 if (sc->sc_cfg & CFG_TBI_EN) { 3280 bus_addr_t tbireg; 3281 3282 if (phy != 0) 3283 return -1; 3284 3285 switch (reg) { 3286 case MII_BMCR: tbireg = SIP_TBICR; break; 3287 case MII_BMSR: tbireg = SIP_TBISR; break; 3288 case MII_ANAR: tbireg = SIP_TANAR; break; 3289 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3290 case MII_ANER: tbireg = SIP_TANER; break; 3291 case MII_EXTSR: 3292 /* 3293 * Don't even bother reading the TESR register. 3294 * The manual documents that the device has 3295 * 1000baseX full/half capability, but the 3296 * register itself seems read back 0 on some 3297 * boards. Just hard-code the result. 3298 */ 3299 *val = (EXTSR_1000XFDX | EXTSR_1000XHDX); 3300 return 0; 3301 3302 default: 3303 return 0; 3304 } 3305 3306 *val = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3307 if (tbireg == SIP_TBISR) { 3308 /* LINK and ACOMP are switched! */ 3309 int sr = *val; 3310 3311 *val = 0; 3312 if (sr & TBISR_MR_LINK_STATUS) 3313 *val |= BMSR_LINK; 3314 if (sr & TBISR_MR_AN_COMPLETE) 3315 *val |= BMSR_ACOMP; 3316 3317 /* 3318 * The manual claims this register reads back 0 3319 * on hard and soft reset. But we want to let 3320 * the gentbi driver know that we support auto- 3321 * negotiation, so hard-code this bit in the 3322 * result. 3323 */ 3324 *val |= BMSR_ANEG | BMSR_EXTSTAT; 3325 } 3326 3327 return 0; 3328 } 3329 3330 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg, 3331 val); 3332 } 3333 3334 /* 3335 * sip_dp83820_mii_writereg: [mii interface function] 3336 * 3337 * Write a PHY register on the MII of the DP83820. 3338 */ 3339 static int 3340 sipcom_dp83820_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3341 { 3342 struct sip_softc *sc = device_private(self); 3343 3344 if (sc->sc_cfg & CFG_TBI_EN) { 3345 bus_addr_t tbireg; 3346 3347 if (phy != 0) 3348 return -1; 3349 3350 switch (reg) { 3351 case MII_BMCR: tbireg = SIP_TBICR; break; 3352 case MII_ANAR: tbireg = SIP_TANAR; break; 3353 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3354 default: 3355 return 0; 3356 } 3357 3358 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3359 return 0; 3360 } 3361 3362 return mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, 3363 val); 3364 } 3365 3366 /* 3367 * sip_dp83820_mii_statchg: [mii interface function] 3368 * 3369 * Callback from MII layer when media changes. 3370 */ 3371 static void 3372 sipcom_dp83820_mii_statchg(struct ifnet *ifp) 3373 { 3374 struct sip_softc *sc = ifp->if_softc; 3375 struct mii_data *mii = &sc->sc_mii; 3376 uint32_t cfg, pcr; 3377 3378 /* 3379 * Get flow control negotiation result. 3380 */ 3381 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3382 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3383 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3384 mii->mii_media_active &= ~IFM_ETH_FMASK; 3385 } 3386 3387 /* 3388 * Update TXCFG for full-duplex operation. 3389 */ 3390 if ((mii->mii_media_active & IFM_FDX) != 0) 3391 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3392 else 3393 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3394 3395 /* 3396 * Update RXCFG for full-duplex or loopback. 3397 */ 3398 if ((mii->mii_media_active & IFM_FDX) != 0 || 3399 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3400 sc->sc_rxcfg |= RXCFG_ATX; 3401 else 3402 sc->sc_rxcfg &= ~RXCFG_ATX; 3403 3404 /* 3405 * Update CFG for MII/GMII. 3406 */ 3407 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3408 cfg = sc->sc_cfg | CFG_MODE_1000; 3409 else 3410 cfg = sc->sc_cfg; 3411 3412 /* 3413 * 802.3x flow control. 3414 */ 3415 pcr = 0; 3416 if (sc->sc_flowflags & IFM_FLOW) { 3417 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3418 pcr |= sc->sc_rx_flow_thresh; 3419 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3420 pcr |= PCR_PSEN | PCR_PS_MCAST; 3421 } 3422 3423 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3424 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3425 sc->sc_txcfg); 3426 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3427 sc->sc_rxcfg); 3428 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3429 } 3430 3431 /* 3432 * sip_mii_bitbang_read: [mii bit-bang interface function] 3433 * 3434 * Read the MII serial port for the MII bit-bang module. 3435 */ 3436 static uint32_t 3437 sipcom_mii_bitbang_read(device_t self) 3438 { 3439 struct sip_softc *sc = device_private(self); 3440 3441 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3442 } 3443 3444 /* 3445 * sip_mii_bitbang_write: [mii big-bang interface function] 3446 * 3447 * Write the MII serial port for the MII bit-bang module. 3448 */ 3449 static void 3450 sipcom_mii_bitbang_write(device_t self, uint32_t val) 3451 { 3452 struct sip_softc *sc = device_private(self); 3453 3454 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3455 } 3456 3457 /* 3458 * sip_sis900_mii_readreg: [mii interface function] 3459 * 3460 * Read a PHY register on the MII. 3461 */ 3462 static int 3463 sipcom_sis900_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3464 { 3465 struct sip_softc *sc = device_private(self); 3466 uint32_t enphy; 3467 3468 /* 3469 * The PHY of recent SiS chipsets is accessed through bitbang 3470 * operations. 3471 */ 3472 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3473 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3474 phy, reg, val); 3475 3476 #ifndef SIS900_MII_RESTRICT 3477 /* 3478 * The SiS 900 has only an internal PHY on the MII. Only allow 3479 * MII address 0. 3480 */ 3481 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3482 return -1; 3483 #endif 3484 3485 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3486 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3487 ENPHY_RWCMD | ENPHY_ACCESS); 3488 do { 3489 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3490 } while (enphy & ENPHY_ACCESS); 3491 3492 *val = (enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT; 3493 return 0; 3494 } 3495 3496 /* 3497 * sip_sis900_mii_writereg: [mii interface function] 3498 * 3499 * Write a PHY register on the MII. 3500 */ 3501 static int 3502 sipcom_sis900_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3503 { 3504 struct sip_softc *sc = device_private(self); 3505 uint32_t enphy; 3506 3507 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3508 return mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3509 phy, reg, val); 3510 } 3511 3512 #ifndef SIS900_MII_RESTRICT 3513 /* 3514 * The SiS 900 has only an internal PHY on the MII. Only allow 3515 * MII address 0. 3516 */ 3517 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3518 return -1; 3519 #endif 3520 3521 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3522 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3523 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3524 do { 3525 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3526 } while (enphy & ENPHY_ACCESS); 3527 3528 return 0; 3529 } 3530 3531 /* 3532 * sip_sis900_mii_statchg: [mii interface function] 3533 * 3534 * Callback from MII layer when media changes. 3535 */ 3536 static void 3537 sipcom_sis900_mii_statchg(struct ifnet *ifp) 3538 { 3539 struct sip_softc *sc = ifp->if_softc; 3540 struct mii_data *mii = &sc->sc_mii; 3541 uint32_t flowctl; 3542 3543 /* 3544 * Get flow control negotiation result. 3545 */ 3546 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3547 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3548 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3549 mii->mii_media_active &= ~IFM_ETH_FMASK; 3550 } 3551 3552 /* 3553 * Update TXCFG for full-duplex operation. 3554 */ 3555 if ((mii->mii_media_active & IFM_FDX) != 0) 3556 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3557 else 3558 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3559 3560 /* 3561 * Update RXCFG for full-duplex or loopback. 3562 */ 3563 if ((mii->mii_media_active & IFM_FDX) != 0 || 3564 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3565 sc->sc_rxcfg |= RXCFG_ATX; 3566 else 3567 sc->sc_rxcfg &= ~RXCFG_ATX; 3568 3569 /* 3570 * Update IMR for use of 802.3x flow control. 3571 */ 3572 if (sc->sc_flowflags & IFM_FLOW) { 3573 sc->sc_imr |= (ISR_PAUSE_END | ISR_PAUSE_ST); 3574 flowctl = FLOWCTL_FLOWEN; 3575 } else { 3576 sc->sc_imr &= ~(ISR_PAUSE_END | ISR_PAUSE_ST); 3577 flowctl = 0; 3578 } 3579 3580 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3581 sc->sc_txcfg); 3582 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3583 sc->sc_rxcfg); 3584 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3585 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3586 } 3587 3588 /* 3589 * sip_dp83815_mii_readreg: [mii interface function] 3590 * 3591 * Read a PHY register on the MII. 3592 */ 3593 static int 3594 sipcom_dp83815_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3595 { 3596 struct sip_softc *sc = device_private(self); 3597 uint32_t data; 3598 3599 /* 3600 * The DP83815 only has an internal PHY. Only allow 3601 * MII address 0. 3602 */ 3603 if (phy != 0) 3604 return -1; 3605 3606 /* 3607 * Apparently, after a reset, the DP83815 can take a while 3608 * to respond. During this recovery period, the BMSR returns 3609 * a value of 0. Catch this -- it's not supposed to happen 3610 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3611 * PHY to come back to life. 3612 * 3613 * This works out because the BMSR is the first register 3614 * read during the PHY probe process. 3615 */ 3616 do { 3617 data = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3618 } while (reg == MII_BMSR && data == 0); 3619 3620 *val = data & 0xffff; 3621 return 0; 3622 } 3623 3624 /* 3625 * sip_dp83815_mii_writereg: [mii interface function] 3626 * 3627 * Write a PHY register to the MII. 3628 */ 3629 static int 3630 sipcom_dp83815_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3631 { 3632 struct sip_softc *sc = device_private(self); 3633 3634 /* 3635 * The DP83815 only has an internal PHY. Only allow 3636 * MII address 0. 3637 */ 3638 if (phy != 0) 3639 return -1; 3640 3641 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3642 3643 return 0; 3644 } 3645 3646 /* 3647 * sip_dp83815_mii_statchg: [mii interface function] 3648 * 3649 * Callback from MII layer when media changes. 3650 */ 3651 static void 3652 sipcom_dp83815_mii_statchg(struct ifnet *ifp) 3653 { 3654 struct sip_softc *sc = ifp->if_softc; 3655 3656 /* 3657 * Update TXCFG for full-duplex operation. 3658 */ 3659 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3660 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3661 else 3662 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3663 3664 /* 3665 * Update RXCFG for full-duplex or loopback. 3666 */ 3667 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3668 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3669 sc->sc_rxcfg |= RXCFG_ATX; 3670 else 3671 sc->sc_rxcfg &= ~RXCFG_ATX; 3672 3673 /* 3674 * XXX 802.3x flow control. 3675 */ 3676 3677 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3678 sc->sc_txcfg); 3679 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3680 sc->sc_rxcfg); 3681 3682 /* 3683 * Some DP83815s experience problems when used with short 3684 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3685 * sequence adjusts the DSP's signal attenuation to fix the 3686 * problem. 3687 */ 3688 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3689 uint32_t reg; 3690 3691 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3692 3693 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3694 reg &= 0x0fff; 3695 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3696 delay(100); 3697 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3698 reg &= 0x00ff; 3699 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3700 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3701 0x00e8); 3702 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3703 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3704 reg | 0x20); 3705 } 3706 3707 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3708 } 3709 } 3710 3711 static void 3712 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3713 const struct pci_attach_args *pa, uint8_t *enaddr) 3714 { 3715 uint16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3716 uint8_t cksum, *e, match; 3717 int i; 3718 3719 /* 3720 * EEPROM data format for the DP83820 can be found in 3721 * the DP83820 manual, section 4.2.4. 3722 */ 3723 3724 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3725 3726 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3727 match = ~(match - 1); 3728 3729 cksum = 0x55; 3730 e = (uint8_t *)eeprom_data; 3731 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3732 cksum += *e++; 3733 3734 if (cksum != match) 3735 printf("%s: Checksum (%x) mismatch (%x)", 3736 device_xname(sc->sc_dev), cksum, match); 3737 3738 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3739 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3740 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3741 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3742 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3743 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3744 } 3745 3746 static void 3747 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3748 { 3749 int i; 3750 3751 /* 3752 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3753 * a reason, but I don't know it. 3754 */ 3755 for (i = 0; i < 10; i++) 3756 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3757 } 3758 3759 static void 3760 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3761 const struct pci_attach_args *pa, uint8_t *enaddr) 3762 { 3763 uint16_t myea[ETHER_ADDR_LEN / 2]; 3764 3765 switch (sc->sc_rev) { 3766 case SIS_REV_630S: 3767 case SIS_REV_630E: 3768 case SIS_REV_630EA1: 3769 case SIS_REV_630ET: 3770 case SIS_REV_635: 3771 /* 3772 * The MAC address for the on-board Ethernet of 3773 * the SiS 630 chipset is in the NVRAM. Kick 3774 * the chip into re-loading it from NVRAM, and 3775 * read the MAC address out of the filter registers. 3776 */ 3777 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3778 3779 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3780 RFCR_RFADDR_NODE0); 3781 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3782 0xffff; 3783 3784 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3785 RFCR_RFADDR_NODE2); 3786 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3787 0xffff; 3788 3789 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3790 RFCR_RFADDR_NODE4); 3791 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3792 0xffff; 3793 break; 3794 3795 case SIS_REV_960: 3796 { 3797 #define SIS_SET_EROMAR(x, y) \ 3798 bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3799 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3800 3801 #define SIS_CLR_EROMAR(x, y) \ 3802 bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3803 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3804 3805 int waittime, i; 3806 3807 /* Allow to read EEPROM from LAN. It is shared 3808 * between a 1394 controller and the NIC and each 3809 * time we access it, we need to set SIS_EECMD_REQ. 3810 */ 3811 SIS_SET_EROMAR(sc, EROMAR_REQ); 3812 3813 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3814 /* Force EEPROM to idle state. */ 3815 3816 /* 3817 * XXX-cube This is ugly. 3818 * I'll look for docs about it. 3819 */ 3820 SIS_SET_EROMAR(sc, EROMAR_EECS); 3821 sipcom_sis900_eeprom_delay(sc); 3822 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3823 SIS_SET_EROMAR(sc, EROMAR_EESK); 3824 sipcom_sis900_eeprom_delay(sc); 3825 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3826 sipcom_sis900_eeprom_delay(sc); 3827 } 3828 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3829 sipcom_sis900_eeprom_delay(sc); 3830 bus_space_write_4(sc->sc_st, sc->sc_sh, 3831 SIP_EROMAR, 0); 3832 3833 if (bus_space_read_4(sc->sc_st, sc->sc_sh, 3834 SIP_EROMAR) & EROMAR_GNT) { 3835 sipcom_read_eeprom(sc, 3836 SIP_EEPROM_ETHERNET_ID0 >> 1, 3837 sizeof(myea) / sizeof(myea[0]), 3838 myea); 3839 break; 3840 } 3841 DELAY(1); 3842 } 3843 3844 /* 3845 * Set SIS_EECTL_CLK to high, so a other master 3846 * can operate on the i2c bus. 3847 */ 3848 SIS_SET_EROMAR(sc, EROMAR_EESK); 3849 3850 /* Refuse EEPROM access by LAN */ 3851 SIS_SET_EROMAR(sc, EROMAR_DONE); 3852 } break; 3853 3854 default: 3855 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3856 sizeof(myea) / sizeof(myea[0]), myea); 3857 } 3858 3859 enaddr[0] = myea[0] & 0xff; 3860 enaddr[1] = myea[0] >> 8; 3861 enaddr[2] = myea[1] & 0xff; 3862 enaddr[3] = myea[1] >> 8; 3863 enaddr[4] = myea[2] & 0xff; 3864 enaddr[5] = myea[2] >> 8; 3865 } 3866 3867 /* Table and macro to bit-reverse an octet. */ 3868 static const uint8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3869 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3870 3871 static void 3872 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3873 const struct pci_attach_args *pa, uint8_t *enaddr) 3874 { 3875 uint16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3876 uint8_t cksum, *e, match; 3877 int i; 3878 3879 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3880 sizeof(eeprom_data[0]), eeprom_data); 3881 3882 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3883 match = ~(match - 1); 3884 3885 cksum = 0x55; 3886 e = (uint8_t *)eeprom_data; 3887 for (i = 0; i < SIP_DP83815_EEPROM_CHECKSUM; i++) 3888 cksum += *e++; 3889 3890 if (cksum != match) 3891 printf("%s: Checksum (%x) mismatch (%x)", 3892 device_xname(sc->sc_dev), cksum, match); 3893 3894 /* 3895 * Unrolled because it makes slightly more sense this way. 3896 * The DP83815 stores the MAC address in bit 0 of word 6 3897 * through bit 15 of word 8. 3898 */ 3899 ea = &eeprom_data[6]; 3900 enaddr[0] = ((*ea & 0x1) << 7); 3901 ea++; 3902 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3903 enaddr[1] = ((*ea & 0x1FE) >> 1); 3904 enaddr[2] = ((*ea & 0x1) << 7); 3905 ea++; 3906 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3907 enaddr[3] = ((*ea & 0x1FE) >> 1); 3908 enaddr[4] = ((*ea & 0x1) << 7); 3909 ea++; 3910 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3911 enaddr[5] = ((*ea & 0x1FE) >> 1); 3912 3913 /* 3914 * In case that's not weird enough, we also need to reverse 3915 * the bits in each byte. This all actually makes more sense 3916 * if you think about the EEPROM storage as an array of bits 3917 * being shifted into bytes, but that's not how we're looking 3918 * at it here... 3919 */ 3920 for (i = 0; i < 6 ;i++) 3921 enaddr[i] = bbr(enaddr[i]); 3922 } 3923 3924 /* 3925 * sip_mediastatus: [ifmedia interface function] 3926 * 3927 * Get the current interface media status. 3928 */ 3929 static void 3930 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3931 { 3932 struct sip_softc *sc = ifp->if_softc; 3933 3934 if (!device_is_active(sc->sc_dev)) { 3935 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 3936 ifmr->ifm_status = 0; 3937 return; 3938 } 3939 ether_mediastatus(ifp, ifmr); 3940 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) | 3941 sc->sc_flowflags; 3942 } 3943
Indexes created Tue Sep 30 11:09:46 GMT 2025