if_sip.c revision 1.178
1 /* $NetBSD: if_sip.c,v 1.178 2020/02/07 00:04:28 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999 Network Computer, Inc. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of Network Computer, Inc. nor the names of its 45 * contributors may be used to endorse or promote products derived 46 * from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * Device driver for the Silicon Integrated Systems SiS 900, 63 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 64 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 65 * controllers. 66 * 67 * Originally written to support the SiS 900 by Jason R. Thorpe for 68 * Network Computer, Inc. 69 * 70 * TODO: 71 * 72 * - Reduce the Rx interrupt load. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.178 2020/02/07 00:04:28 thorpej Exp $"); 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/callout.h> 81 #include <sys/mbuf.h> 82 #include <sys/malloc.h> 83 #include <sys/kernel.h> 84 #include <sys/socket.h> 85 #include <sys/ioctl.h> 86 #include <sys/errno.h> 87 #include <sys/device.h> 88 #include <sys/queue.h> 89 #include <sys/rndsource.h> 90 91 #include <net/if.h> 92 #include <net/if_dl.h> 93 #include <net/if_media.h> 94 #include <net/if_ether.h> 95 #include <net/bpf.h> 96 97 #include <sys/bus.h> 98 #include <sys/intr.h> 99 #include <machine/endian.h> 100 101 #include <dev/mii/mii.h> 102 #include <dev/mii/miivar.h> 103 #include <dev/mii/mii_bitbang.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 109 #include <dev/pci/if_sipreg.h> 110 111 /* 112 * Transmit descriptor list size. This is arbitrary, but allocate 113 * enough descriptors for 128 pending transmissions, and 8 segments 114 * per packet (64 for DP83820 for jumbo frames). 115 * 116 * This MUST work out to a power of 2. 117 */ 118 #define GSIP_NTXSEGS_ALLOC 16 119 #define SIP_NTXSEGS_ALLOC 8 120 121 #define SIP_TXQUEUELEN 256 122 #define MAX_SIP_NTXDESC \ 123 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 124 125 /* 126 * Receive descriptor list size. We have one Rx buffer per incoming 127 * packet, so this logic is a little simpler. 128 * 129 * Actually, on the DP83820, we allow the packet to consume more than 130 * one buffer, in order to support jumbo Ethernet frames. In that 131 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 132 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 133 * so we'd better be quick about handling receive interrupts. 134 */ 135 #define GSIP_NRXDESC 256 136 #define SIP_NRXDESC 128 137 138 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 139 140 /* 141 * Control structures are DMA'd to the SiS900 chip. We allocate them in 142 * a single clump that maps to a single DMA segment to make several things 143 * easier. 144 */ 145 struct sip_control_data { 146 /* 147 * The transmit descriptors. 148 */ 149 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 150 151 /* 152 * The receive descriptors. 153 */ 154 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 155 }; 156 157 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 158 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 159 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 160 161 /* 162 * Software state for transmit jobs. 163 */ 164 struct sip_txsoft { 165 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 166 bus_dmamap_t txs_dmamap; /* our DMA map */ 167 int txs_firstdesc; /* first descriptor in packet */ 168 int txs_lastdesc; /* last descriptor in packet */ 169 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 170 }; 171 172 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 173 174 /* 175 * Software state for receive jobs. 176 */ 177 struct sip_rxsoft { 178 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 179 bus_dmamap_t rxs_dmamap; /* our DMA map */ 180 }; 181 182 enum sip_attach_stage { 183 SIP_ATTACH_FIN = 0 184 , SIP_ATTACH_CREATE_RXMAP 185 , SIP_ATTACH_CREATE_TXMAP 186 , SIP_ATTACH_LOAD_MAP 187 , SIP_ATTACH_CREATE_MAP 188 , SIP_ATTACH_MAP_MEM 189 , SIP_ATTACH_ALLOC_MEM 190 , SIP_ATTACH_INTR 191 , SIP_ATTACH_MAP 192 }; 193 194 /* 195 * Software state per device. 196 */ 197 struct sip_softc { 198 device_t sc_dev; /* generic device information */ 199 device_suspensor_t sc_suspensor; 200 pmf_qual_t sc_qual; 201 202 bus_space_tag_t sc_st; /* bus space tag */ 203 bus_space_handle_t sc_sh; /* bus space handle */ 204 bus_size_t sc_sz; /* bus space size */ 205 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 206 pci_chipset_tag_t sc_pc; 207 bus_dma_segment_t sc_seg; 208 struct ethercom sc_ethercom; /* ethernet common data */ 209 210 const struct sip_product *sc_model; /* which model are we? */ 211 int sc_gigabit; /* 1: 83820, 0: other */ 212 int sc_rev; /* chip revision */ 213 214 void *sc_ih; /* interrupt cookie */ 215 216 struct mii_data sc_mii; /* MII/media information */ 217 218 callout_t sc_tick_ch; /* tick callout */ 219 220 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 221 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 222 223 /* 224 * Software state for transmit and receive descriptors. 225 */ 226 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 227 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 228 229 /* 230 * Control data structures. 231 */ 232 struct sip_control_data *sc_control_data; 233 #define sc_txdescs sc_control_data->scd_txdescs 234 #define sc_rxdescs sc_control_data->scd_rxdescs 235 236 #ifdef SIP_EVENT_COUNTERS 237 /* 238 * Event counters. 239 */ 240 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 241 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 242 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 243 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 244 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 245 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 246 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 247 struct evcnt sc_ev_rxpause; /* PAUSE received */ 248 /* DP83820 only */ 249 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 250 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 251 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 252 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 253 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 254 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 255 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 256 #endif /* SIP_EVENT_COUNTERS */ 257 258 uint32_t sc_txcfg; /* prototype TXCFG register */ 259 uint32_t sc_rxcfg; /* prototype RXCFG register */ 260 uint32_t sc_imr; /* prototype IMR register */ 261 uint32_t sc_rfcr; /* prototype RFCR register */ 262 263 uint32_t sc_cfg; /* prototype CFG register */ 264 265 uint32_t sc_gpior; /* prototype GPIOR register */ 266 267 uint32_t sc_tx_fill_thresh; /* transmit fill threshold */ 268 uint32_t sc_tx_drain_thresh; /* transmit drain threshold */ 269 270 uint32_t sc_rx_drain_thresh; /* receive drain threshold */ 271 272 int sc_flowflags; /* 802.3x flow control flags */ 273 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 274 int sc_paused; /* paused indication */ 275 276 int sc_txfree; /* number of free Tx descriptors */ 277 int sc_txnext; /* next ready Tx descriptor */ 278 int sc_txwin; /* Tx descriptors since last intr */ 279 280 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 281 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 282 283 /* values of interface state at last init */ 284 struct { 285 /* if_capenable */ 286 uint64_t if_capenable; 287 /* ec_capenable */ 288 int ec_capenable; 289 /* VLAN_ATTACHED */ 290 int is_vlan; 291 } sc_prev; 292 293 u_short sc_if_flags; 294 295 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 296 int sc_rxdiscard; 297 int sc_rxlen; 298 struct mbuf *sc_rxhead; 299 struct mbuf *sc_rxtail; 300 struct mbuf **sc_rxtailp; 301 302 int sc_ntxdesc; 303 int sc_ntxdesc_mask; 304 305 int sc_nrxdesc_mask; 306 307 const struct sip_parm { 308 const struct sip_regs { 309 int r_rxcfg; 310 int r_txcfg; 311 } p_regs; 312 313 const struct sip_bits { 314 uint32_t b_txcfg_mxdma_8; 315 uint32_t b_txcfg_mxdma_16; 316 uint32_t b_txcfg_mxdma_32; 317 uint32_t b_txcfg_mxdma_64; 318 uint32_t b_txcfg_mxdma_128; 319 uint32_t b_txcfg_mxdma_256; 320 uint32_t b_txcfg_mxdma_512; 321 uint32_t b_txcfg_flth_mask; 322 uint32_t b_txcfg_drth_mask; 323 324 uint32_t b_rxcfg_mxdma_8; 325 uint32_t b_rxcfg_mxdma_16; 326 uint32_t b_rxcfg_mxdma_32; 327 uint32_t b_rxcfg_mxdma_64; 328 uint32_t b_rxcfg_mxdma_128; 329 uint32_t b_rxcfg_mxdma_256; 330 uint32_t b_rxcfg_mxdma_512; 331 332 uint32_t b_isr_txrcmp; 333 uint32_t b_isr_rxrcmp; 334 uint32_t b_isr_dperr; 335 uint32_t b_isr_sserr; 336 uint32_t b_isr_rmabt; 337 uint32_t b_isr_rtabt; 338 339 uint32_t b_cmdsts_size_mask; 340 } p_bits; 341 int p_filtmem; 342 int p_rxbuf_len; 343 bus_size_t p_tx_dmamap_size; 344 int p_ntxsegs; 345 int p_ntxsegs_alloc; 346 int p_nrxdesc; 347 } *sc_parm; 348 349 void (*sc_rxintr)(struct sip_softc *); 350 351 krndsource_t rnd_source; /* random source */ 352 }; 353 354 #define sc_bits sc_parm->p_bits 355 #define sc_regs sc_parm->p_regs 356 357 static const struct sip_parm sip_parm = { 358 .p_filtmem = OTHER_RFCR_NS_RFADDR_FILTMEM 359 , .p_rxbuf_len = MCLBYTES - 1 /* field width */ 360 , .p_tx_dmamap_size = MCLBYTES 361 , .p_ntxsegs = 16 362 , .p_ntxsegs_alloc = SIP_NTXSEGS_ALLOC 363 , .p_nrxdesc = SIP_NRXDESC 364 , .p_bits = { 365 .b_txcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 366 , .b_txcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 367 , .b_txcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 368 , .b_txcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 369 , .b_txcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 370 , .b_txcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 371 , .b_txcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 372 , .b_txcfg_flth_mask = 0x00003f00 /* Tx fill threshold */ 373 , .b_txcfg_drth_mask = 0x0000003f /* Tx drain threshold */ 374 375 , .b_rxcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 376 , .b_rxcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 377 , .b_rxcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 378 , .b_rxcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 379 , .b_rxcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 380 , .b_rxcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 381 , .b_rxcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 382 383 , .b_isr_txrcmp = 0x02000000 /* transmit reset complete */ 384 , .b_isr_rxrcmp = 0x01000000 /* receive reset complete */ 385 , .b_isr_dperr = 0x00800000 /* detected parity error */ 386 , .b_isr_sserr = 0x00400000 /* signalled system error */ 387 , .b_isr_rmabt = 0x00200000 /* received master abort */ 388 , .b_isr_rtabt = 0x00100000 /* received target abort */ 389 , .b_cmdsts_size_mask = OTHER_CMDSTS_SIZE_MASK 390 } 391 , .p_regs = { 392 .r_rxcfg = OTHER_SIP_RXCFG, 393 .r_txcfg = OTHER_SIP_TXCFG 394 } 395 }, gsip_parm = { 396 .p_filtmem = DP83820_RFCR_NS_RFADDR_FILTMEM 397 , .p_rxbuf_len = MCLBYTES - 8 398 , .p_tx_dmamap_size = ETHER_MAX_LEN_JUMBO 399 , .p_ntxsegs = 64 400 , .p_ntxsegs_alloc = GSIP_NTXSEGS_ALLOC 401 , .p_nrxdesc = GSIP_NRXDESC 402 , .p_bits = { 403 .b_txcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 404 , .b_txcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 405 , .b_txcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 406 , .b_txcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 407 , .b_txcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 408 , .b_txcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 409 , .b_txcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 410 , .b_txcfg_flth_mask = 0x0000ff00 /* Fx fill threshold */ 411 , .b_txcfg_drth_mask = 0x000000ff /* Tx drain threshold */ 412 413 , .b_rxcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 414 , .b_rxcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 415 , .b_rxcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 416 , .b_rxcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 417 , .b_rxcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 418 , .b_rxcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 419 , .b_rxcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 420 421 , .b_isr_txrcmp = 0x00400000 /* transmit reset complete */ 422 , .b_isr_rxrcmp = 0x00200000 /* receive reset complete */ 423 , .b_isr_dperr = 0x00100000 /* detected parity error */ 424 , .b_isr_sserr = 0x00080000 /* signalled system error */ 425 , .b_isr_rmabt = 0x00040000 /* received master abort */ 426 , .b_isr_rtabt = 0x00020000 /* received target abort */ 427 , .b_cmdsts_size_mask = DP83820_CMDSTS_SIZE_MASK 428 } 429 , .p_regs = { 430 .r_rxcfg = DP83820_SIP_RXCFG, 431 .r_txcfg = DP83820_SIP_TXCFG 432 } 433 }; 434 435 static inline int 436 sip_nexttx(const struct sip_softc *sc, int x) 437 { 438 return (x + 1) & sc->sc_ntxdesc_mask; 439 } 440 441 static inline int 442 sip_nextrx(const struct sip_softc *sc, int x) 443 { 444 return (x + 1) & sc->sc_nrxdesc_mask; 445 } 446 447 /* 83820 only */ 448 static inline void 449 sip_rxchain_reset(struct sip_softc *sc) 450 { 451 sc->sc_rxtailp = &sc->sc_rxhead; 452 *sc->sc_rxtailp = NULL; 453 sc->sc_rxlen = 0; 454 } 455 456 /* 83820 only */ 457 static inline void 458 sip_rxchain_link(struct sip_softc *sc, struct mbuf *m) 459 { 460 *sc->sc_rxtailp = sc->sc_rxtail = m; 461 sc->sc_rxtailp = &m->m_next; 462 } 463 464 #ifdef SIP_EVENT_COUNTERS 465 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 466 #else 467 #define SIP_EVCNT_INCR(ev) /* nothing */ 468 #endif 469 470 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 471 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 472 473 static inline void 474 sip_cdtxsync(struct sip_softc *sc, const int x0, const int n0, const int ops) 475 { 476 int x, n; 477 478 x = x0; 479 n = n0; 480 481 /* If it will wrap around, sync to the end of the ring. */ 482 if (x + n > sc->sc_ntxdesc) { 483 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 484 SIP_CDTXOFF(x), sizeof(struct sip_desc) * 485 (sc->sc_ntxdesc - x), ops); 486 n -= (sc->sc_ntxdesc - x); 487 x = 0; 488 } 489 490 /* Now sync whatever is left. */ 491 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 492 SIP_CDTXOFF(x), sizeof(struct sip_desc) * n, ops); 493 } 494 495 static inline void 496 sip_cdrxsync(struct sip_softc *sc, int x, int ops) 497 { 498 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 499 SIP_CDRXOFF(x), sizeof(struct sip_desc), ops); 500 } 501 502 #if 0 503 #ifdef DP83820 504 uint32_t sipd_bufptr; /* pointer to DMA segment */ 505 uint32_t sipd_cmdsts; /* command/status word */ 506 #else 507 uint32_t sipd_cmdsts; /* command/status word */ 508 uint32_t sipd_bufptr; /* pointer to DMA segment */ 509 #endif /* DP83820 */ 510 #endif /* 0 */ 511 512 static inline volatile uint32_t * 513 sipd_cmdsts(struct sip_softc *sc, struct sip_desc *sipd) 514 { 515 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 1 : 0]; 516 } 517 518 static inline volatile uint32_t * 519 sipd_bufptr(struct sip_softc *sc, struct sip_desc *sipd) 520 { 521 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 0 : 1]; 522 } 523 524 static inline void 525 sip_init_rxdesc(struct sip_softc *sc, int x) 526 { 527 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 528 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 529 530 sipd->sipd_link = htole32(SIP_CDRXADDR(sc, sip_nextrx(sc, x))); 531 *sipd_bufptr(sc, sipd) = htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 532 *sipd_cmdsts(sc, sipd) = htole32(CMDSTS_INTR | 533 (sc->sc_parm->p_rxbuf_len & sc->sc_bits.b_cmdsts_size_mask)); 534 sipd->sipd_extsts = 0; 535 sip_cdrxsync(sc, x, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 536 } 537 538 #define SIP_CHIP_VERS(sc, v, p, r) \ 539 ((sc)->sc_model->sip_vendor == (v) && \ 540 (sc)->sc_model->sip_product == (p) && \ 541 (sc)->sc_rev == (r)) 542 543 #define SIP_CHIP_MODEL(sc, v, p) \ 544 ((sc)->sc_model->sip_vendor == (v) && \ 545 (sc)->sc_model->sip_product == (p)) 546 547 #define SIP_SIS900_REV(sc, rev) \ 548 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 549 550 #define SIP_TIMEOUT 1000 551 552 static int sip_ifflags_cb(struct ethercom *); 553 static void sipcom_start(struct ifnet *); 554 static void sipcom_watchdog(struct ifnet *); 555 static int sipcom_ioctl(struct ifnet *, u_long, void *); 556 static int sipcom_init(struct ifnet *); 557 static void sipcom_stop(struct ifnet *, int); 558 559 static bool sipcom_reset(struct sip_softc *); 560 static void sipcom_rxdrain(struct sip_softc *); 561 static int sipcom_add_rxbuf(struct sip_softc *, int); 562 static void sipcom_read_eeprom(struct sip_softc *, int, int, 563 uint16_t *); 564 static void sipcom_tick(void *); 565 566 static void sipcom_sis900_set_filter(struct sip_softc *); 567 static void sipcom_dp83815_set_filter(struct sip_softc *); 568 569 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 570 const struct pci_attach_args *, uint8_t *); 571 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 572 static void sipcom_sis900_read_macaddr(struct sip_softc *, 573 const struct pci_attach_args *, uint8_t *); 574 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 575 const struct pci_attach_args *, uint8_t *); 576 577 static int sipcom_intr(void *); 578 static void sipcom_txintr(struct sip_softc *); 579 static void sip_rxintr(struct sip_softc *); 580 static void gsip_rxintr(struct sip_softc *); 581 582 static int sipcom_dp83820_mii_readreg(device_t, int, int, uint16_t *); 583 static int sipcom_dp83820_mii_writereg(device_t, int, int, uint16_t); 584 static void sipcom_dp83820_mii_statchg(struct ifnet *); 585 586 static int sipcom_sis900_mii_readreg(device_t, int, int, uint16_t *); 587 static int sipcom_sis900_mii_writereg(device_t, int, int, uint16_t); 588 static void sipcom_sis900_mii_statchg(struct ifnet *); 589 590 static int sipcom_dp83815_mii_readreg(device_t, int, int, uint16_t *); 591 static int sipcom_dp83815_mii_writereg(device_t, int, int, uint16_t); 592 static void sipcom_dp83815_mii_statchg(struct ifnet *); 593 594 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 595 596 static int sipcom_match(device_t, cfdata_t, void *); 597 static void sipcom_attach(device_t, device_t, void *); 598 static void sipcom_do_detach(device_t, enum sip_attach_stage); 599 static int sipcom_detach(device_t, int); 600 static bool sipcom_resume(device_t, const pmf_qual_t *); 601 static bool sipcom_suspend(device_t, const pmf_qual_t *); 602 603 int gsip_copy_small = 0; 604 int sip_copy_small = 0; 605 606 CFATTACH_DECL3_NEW(gsip, sizeof(struct sip_softc), 607 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 608 DVF_DETACH_SHUTDOWN); 609 CFATTACH_DECL3_NEW(sip, sizeof(struct sip_softc), 610 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 611 DVF_DETACH_SHUTDOWN); 612 613 /* 614 * Descriptions of the variants of the SiS900. 615 */ 616 struct sip_variant { 617 int (*sipv_mii_readreg)(device_t, int, int, uint16_t *); 618 int (*sipv_mii_writereg)(device_t, int, int, uint16_t); 619 void (*sipv_mii_statchg)(struct ifnet *); 620 void (*sipv_set_filter)(struct sip_softc *); 621 void (*sipv_read_macaddr)(struct sip_softc *, 622 const struct pci_attach_args *, uint8_t *); 623 }; 624 625 static uint32_t sipcom_mii_bitbang_read(device_t); 626 static void sipcom_mii_bitbang_write(device_t, uint32_t); 627 628 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 629 sipcom_mii_bitbang_read, 630 sipcom_mii_bitbang_write, 631 { 632 EROMAR_MDIO, /* MII_BIT_MDO */ 633 EROMAR_MDIO, /* MII_BIT_MDI */ 634 EROMAR_MDC, /* MII_BIT_MDC */ 635 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 636 0, /* MII_BIT_DIR_PHY_HOST */ 637 } 638 }; 639 640 static const struct sip_variant sipcom_variant_dp83820 = { 641 sipcom_dp83820_mii_readreg, 642 sipcom_dp83820_mii_writereg, 643 sipcom_dp83820_mii_statchg, 644 sipcom_dp83815_set_filter, 645 sipcom_dp83820_read_macaddr, 646 }; 647 648 static const struct sip_variant sipcom_variant_sis900 = { 649 sipcom_sis900_mii_readreg, 650 sipcom_sis900_mii_writereg, 651 sipcom_sis900_mii_statchg, 652 sipcom_sis900_set_filter, 653 sipcom_sis900_read_macaddr, 654 }; 655 656 static const struct sip_variant sipcom_variant_dp83815 = { 657 sipcom_dp83815_mii_readreg, 658 sipcom_dp83815_mii_writereg, 659 sipcom_dp83815_mii_statchg, 660 sipcom_dp83815_set_filter, 661 sipcom_dp83815_read_macaddr, 662 }; 663 664 665 /* 666 * Devices supported by this driver. 667 */ 668 static const struct sip_product { 669 pci_vendor_id_t sip_vendor; 670 pci_product_id_t sip_product; 671 const char *sip_name; 672 const struct sip_variant *sip_variant; 673 int sip_gigabit; 674 } sipcom_products[] = { 675 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 676 "NatSemi DP83820 Gigabit Ethernet", 677 &sipcom_variant_dp83820, 1 }, 678 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 679 "SiS 900 10/100 Ethernet", 680 &sipcom_variant_sis900, 0 }, 681 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 682 "SiS 7016 10/100 Ethernet", 683 &sipcom_variant_sis900, 0 }, 684 685 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 686 "NatSemi DP83815 10/100 Ethernet", 687 &sipcom_variant_dp83815, 0 }, 688 689 { 0, 0, 690 NULL, 691 NULL, 0 }, 692 }; 693 694 static const struct sip_product * 695 sipcom_lookup(const struct pci_attach_args *pa, bool gigabit) 696 { 697 const struct sip_product *sip; 698 699 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 700 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 701 PCI_PRODUCT(pa->pa_id) == sip->sip_product && 702 sip->sip_gigabit == gigabit) 703 return sip; 704 } 705 return NULL; 706 } 707 708 /* 709 * I really hate stupid hardware vendors. There's a bit in the EEPROM 710 * which indicates if the card can do 64-bit data transfers. Unfortunately, 711 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 712 * which means we try to use 64-bit data transfers on those cards if we 713 * happen to be plugged into a 32-bit slot. 714 * 715 * What we do is use this table of cards known to be 64-bit cards. If 716 * you have a 64-bit card who's subsystem ID is not listed in this table, 717 * send the output of "pcictl dump ..." of the device to me so that your 718 * card will use the 64-bit data path when plugged into a 64-bit slot. 719 * 720 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 721 * June 30, 2002 722 */ 723 static int 724 sipcom_check_64bit(const struct pci_attach_args *pa) 725 { 726 static const struct { 727 pci_vendor_id_t c64_vendor; 728 pci_product_id_t c64_product; 729 } card64[] = { 730 /* Asante GigaNIX */ 731 { 0x128a, 0x0002 }, 732 733 /* Accton EN1407-T, Planex GN-1000TE */ 734 { 0x1113, 0x1407 }, 735 736 /* Netgear GA621 */ 737 { 0x1385, 0x621a }, 738 739 /* Netgear GA622 */ 740 { 0x1385, 0x622a }, 741 742 /* SMC EZ Card 1000 (9462TX) */ 743 { 0x10b8, 0x9462 }, 744 745 { 0, 0} 746 }; 747 pcireg_t subsys; 748 int i; 749 750 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 751 752 for (i = 0; card64[i].c64_vendor != 0; i++) { 753 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 754 PCI_PRODUCT(subsys) == card64[i].c64_product) 755 return 1; 756 } 757 758 return 0; 759 } 760 761 static int 762 sipcom_match(device_t parent, cfdata_t cf, void *aux) 763 { 764 struct pci_attach_args *pa = aux; 765 766 if (sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0) != NULL) 767 return 1; 768 769 return 0; 770 } 771 772 static void 773 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 774 { 775 uint32_t reg; 776 int i; 777 778 /* 779 * Cause the chip to load configuration data from the EEPROM. 780 */ 781 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 782 for (i = 0; i < 10000; i++) { 783 delay(10); 784 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 785 PTSCR_EELOAD_EN) == 0) 786 break; 787 } 788 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 789 PTSCR_EELOAD_EN) { 790 printf("%s: timeout loading configuration from EEPROM\n", 791 device_xname(sc->sc_dev)); 792 return; 793 } 794 795 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 796 797 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 798 if (reg & CFG_PCI64_DET) { 799 printf("%s: 64-bit PCI slot detected", device_xname(sc->sc_dev)); 800 /* 801 * Check to see if this card is 64-bit. If so, enable 64-bit 802 * data transfers. 803 * 804 * We can't use the DATA64_EN bit in the EEPROM, because 805 * vendors of 32-bit cards fail to clear that bit in many 806 * cases (yet the card still detects that it's in a 64-bit 807 * slot; go figure). 808 */ 809 if (sipcom_check_64bit(pa)) { 810 sc->sc_cfg |= CFG_DATA64_EN; 811 printf(", using 64-bit data transfers"); 812 } 813 printf("\n"); 814 } 815 816 /* 817 * XXX Need some PCI flags indicating support for 818 * XXX 64-bit addressing. 819 */ 820 #if 0 821 if (reg & CFG_M64ADDR) 822 sc->sc_cfg |= CFG_M64ADDR; 823 if (reg & CFG_T64ADDR) 824 sc->sc_cfg |= CFG_T64ADDR; 825 #endif 826 827 if (reg & (CFG_TBI_EN | CFG_EXT_125)) { 828 const char *sep = ""; 829 printf("%s: using ", device_xname(sc->sc_dev)); 830 if (reg & CFG_EXT_125) { 831 sc->sc_cfg |= CFG_EXT_125; 832 printf("%s125MHz clock", sep); 833 sep = ", "; 834 } 835 if (reg & CFG_TBI_EN) { 836 sc->sc_cfg |= CFG_TBI_EN; 837 printf("%sten-bit interface", sep); 838 sep = ", "; 839 } 840 printf("\n"); 841 } 842 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 843 (reg & CFG_MRM_DIS) != 0) 844 sc->sc_cfg |= CFG_MRM_DIS; 845 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 846 (reg & CFG_MWI_DIS) != 0) 847 sc->sc_cfg |= CFG_MWI_DIS; 848 849 /* 850 * Use the extended descriptor format on the DP83820. This 851 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 852 * checksumming. 853 */ 854 sc->sc_cfg |= CFG_EXTSTS_EN; 855 } 856 857 static int 858 sipcom_detach(device_t self, int flags) 859 { 860 int s; 861 862 s = splnet(); 863 sipcom_do_detach(self, SIP_ATTACH_FIN); 864 splx(s); 865 866 return 0; 867 } 868 869 static void 870 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 871 { 872 int i; 873 struct sip_softc *sc = device_private(self); 874 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 875 876 /* 877 * Free any resources we've allocated during attach. 878 * Do this in reverse order and fall through. 879 */ 880 switch (stage) { 881 case SIP_ATTACH_FIN: 882 sipcom_stop(ifp, 1); 883 pmf_device_deregister(self); 884 #ifdef SIP_EVENT_COUNTERS 885 /* 886 * Attach event counters. 887 */ 888 evcnt_detach(&sc->sc_ev_txforceintr); 889 evcnt_detach(&sc->sc_ev_txdstall); 890 evcnt_detach(&sc->sc_ev_txsstall); 891 evcnt_detach(&sc->sc_ev_hiberr); 892 evcnt_detach(&sc->sc_ev_rxintr); 893 evcnt_detach(&sc->sc_ev_txiintr); 894 evcnt_detach(&sc->sc_ev_txdintr); 895 if (!sc->sc_gigabit) { 896 evcnt_detach(&sc->sc_ev_rxpause); 897 } else { 898 evcnt_detach(&sc->sc_ev_txudpsum); 899 evcnt_detach(&sc->sc_ev_txtcpsum); 900 evcnt_detach(&sc->sc_ev_txipsum); 901 evcnt_detach(&sc->sc_ev_rxudpsum); 902 evcnt_detach(&sc->sc_ev_rxtcpsum); 903 evcnt_detach(&sc->sc_ev_rxipsum); 904 evcnt_detach(&sc->sc_ev_txpause); 905 evcnt_detach(&sc->sc_ev_rxpause); 906 } 907 #endif /* SIP_EVENT_COUNTERS */ 908 909 rnd_detach_source(&sc->rnd_source); 910 911 ether_ifdetach(ifp); 912 if_detach(ifp); 913 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 914 ifmedia_fini(&sc->sc_mii.mii_media); 915 916 /*FALLTHROUGH*/ 917 case SIP_ATTACH_CREATE_RXMAP: 918 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 919 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 920 bus_dmamap_destroy(sc->sc_dmat, 921 sc->sc_rxsoft[i].rxs_dmamap); 922 } 923 /*FALLTHROUGH*/ 924 case SIP_ATTACH_CREATE_TXMAP: 925 for (i = 0; i < SIP_TXQUEUELEN; i++) { 926 if (sc->sc_txsoft[i].txs_dmamap != NULL) 927 bus_dmamap_destroy(sc->sc_dmat, 928 sc->sc_txsoft[i].txs_dmamap); 929 } 930 /*FALLTHROUGH*/ 931 case SIP_ATTACH_LOAD_MAP: 932 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 933 /*FALLTHROUGH*/ 934 case SIP_ATTACH_CREATE_MAP: 935 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 936 /*FALLTHROUGH*/ 937 case SIP_ATTACH_MAP_MEM: 938 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 939 sizeof(struct sip_control_data)); 940 /*FALLTHROUGH*/ 941 case SIP_ATTACH_ALLOC_MEM: 942 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 943 /* FALLTHROUGH*/ 944 case SIP_ATTACH_INTR: 945 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 946 /* FALLTHROUGH*/ 947 case SIP_ATTACH_MAP: 948 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 949 break; 950 default: 951 break; 952 } 953 return; 954 } 955 956 static bool 957 sipcom_resume(device_t self, const pmf_qual_t *qual) 958 { 959 struct sip_softc *sc = device_private(self); 960 961 return sipcom_reset(sc); 962 } 963 964 static bool 965 sipcom_suspend(device_t self, const pmf_qual_t *qual) 966 { 967 struct sip_softc *sc = device_private(self); 968 969 sipcom_rxdrain(sc); 970 return true; 971 } 972 973 static void 974 sipcom_attach(device_t parent, device_t self, void *aux) 975 { 976 struct sip_softc *sc = device_private(self); 977 struct pci_attach_args *pa = aux; 978 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 979 struct mii_data * const mii = &sc->sc_mii; 980 pci_chipset_tag_t pc = pa->pa_pc; 981 pci_intr_handle_t ih; 982 const char *intrstr = NULL; 983 bus_space_tag_t iot, memt; 984 bus_space_handle_t ioh, memh; 985 bus_size_t iosz, memsz; 986 int ioh_valid, memh_valid; 987 int i, rseg, error; 988 const struct sip_product *sip; 989 uint8_t enaddr[ETHER_ADDR_LEN]; 990 pcireg_t csr; 991 pcireg_t memtype; 992 bus_size_t tx_dmamap_size; 993 int ntxsegs_alloc; 994 cfdata_t cf = device_cfdata(self); 995 char intrbuf[PCI_INTRSTR_LEN]; 996 997 callout_init(&sc->sc_tick_ch, 0); 998 callout_setfunc(&sc->sc_tick_ch, sipcom_tick, sc); 999 1000 sip = sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0); 1001 if (sip == NULL) { 1002 aprint_error("\n"); 1003 panic("%s: impossible", __func__); 1004 } 1005 sc->sc_dev = self; 1006 sc->sc_gigabit = sip->sip_gigabit; 1007 pmf_self_suspensor_init(self, &sc->sc_suspensor, &sc->sc_qual); 1008 sc->sc_pc = pc; 1009 1010 if (sc->sc_gigabit) { 1011 sc->sc_rxintr = gsip_rxintr; 1012 sc->sc_parm = &gsip_parm; 1013 } else { 1014 sc->sc_rxintr = sip_rxintr; 1015 sc->sc_parm = &sip_parm; 1016 } 1017 tx_dmamap_size = sc->sc_parm->p_tx_dmamap_size; 1018 ntxsegs_alloc = sc->sc_parm->p_ntxsegs_alloc; 1019 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 1020 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 1021 sc->sc_nrxdesc_mask = sc->sc_parm->p_nrxdesc - 1; 1022 1023 sc->sc_rev = PCI_REVISION(pa->pa_class); 1024 1025 aprint_naive("\n"); 1026 aprint_normal(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 1027 1028 sc->sc_model = sip; 1029 1030 /* 1031 * XXX Work-around broken PXE firmware on some boards. 1032 * 1033 * The DP83815 shares an address decoder with the MEM BAR 1034 * and the ROM BAR. Make sure the ROM BAR is disabled, 1035 * so that memory mapped access works. 1036 */ 1037 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1038 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1039 ~PCI_MAPREG_ROM_ENABLE); 1040 1041 /* 1042 * Map the device. 1043 */ 1044 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 1045 PCI_MAPREG_TYPE_IO, 0, 1046 &iot, &ioh, NULL, &iosz) == 0); 1047 if (sc->sc_gigabit) { 1048 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 1049 switch (memtype) { 1050 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1051 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1052 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1053 memtype, 0, &memt, &memh, NULL, &memsz) == 0); 1054 break; 1055 default: 1056 memh_valid = 0; 1057 } 1058 } else { 1059 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1060 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 1061 &memt, &memh, NULL, &memsz) == 0); 1062 } 1063 1064 if (memh_valid) { 1065 sc->sc_st = memt; 1066 sc->sc_sh = memh; 1067 sc->sc_sz = memsz; 1068 } else if (ioh_valid) { 1069 sc->sc_st = iot; 1070 sc->sc_sh = ioh; 1071 sc->sc_sz = iosz; 1072 } else { 1073 aprint_error_dev(self, "unable to map device registers\n"); 1074 return; 1075 } 1076 1077 sc->sc_dmat = pa->pa_dmat; 1078 1079 /* 1080 * Make sure bus mastering is enabled. Also make sure 1081 * Write/Invalidate is enabled if we're allowed to use it. 1082 */ 1083 csr = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1084 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 1085 csr |= PCI_COMMAND_INVALIDATE_ENABLE; 1086 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1087 csr | PCI_COMMAND_MASTER_ENABLE); 1088 1089 /* Power up chip */ 1090 error = pci_activate(pa->pa_pc, pa->pa_tag, self, pci_activate_null); 1091 if (error != 0 && error != EOPNOTSUPP) { 1092 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 1093 return; 1094 } 1095 1096 /* 1097 * Map and establish our interrupt. 1098 */ 1099 if (pci_intr_map(pa, &ih)) { 1100 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 1101 return; 1102 } 1103 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1104 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, sipcom_intr, sc, 1105 device_xname(self)); 1106 if (sc->sc_ih == NULL) { 1107 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 1108 if (intrstr != NULL) 1109 aprint_error(" at %s", intrstr); 1110 aprint_error("\n"); 1111 sipcom_do_detach(self, SIP_ATTACH_MAP); 1112 return; 1113 } 1114 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1115 1116 SIMPLEQ_INIT(&sc->sc_txfreeq); 1117 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1118 1119 /* 1120 * Allocate the control data structures, and create and load the 1121 * DMA map for it. 1122 */ 1123 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1124 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 1125 &rseg, 0)) != 0) { 1126 aprint_error_dev(sc->sc_dev, 1127 "unable to allocate control data, error = %d\n", error); 1128 sipcom_do_detach(self, SIP_ATTACH_INTR); 1129 return; 1130 } 1131 1132 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 1133 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 1134 BUS_DMA_COHERENT)) != 0) { 1135 aprint_error_dev(sc->sc_dev, 1136 "unable to map control data, error = %d\n", error); 1137 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 1138 } 1139 1140 if ((error = bus_dmamap_create(sc->sc_dmat, 1141 sizeof(struct sip_control_data), 1, 1142 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 1143 aprint_error_dev(self, "unable to create control data DMA map" 1144 ", error = %d\n", error); 1145 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 1146 } 1147 1148 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1149 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 1150 0)) != 0) { 1151 aprint_error_dev(self, "unable to load control data DMA map" 1152 ", error = %d\n", error); 1153 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 1154 } 1155 1156 /* 1157 * Create the transmit buffer DMA maps. 1158 */ 1159 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1160 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 1161 sc->sc_parm->p_ntxsegs, MCLBYTES, 0, 0, 1162 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1163 aprint_error_dev(self, "unable to create tx DMA map %d" 1164 ", error = %d\n", i, error); 1165 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 1166 } 1167 } 1168 1169 /* 1170 * Create the receive buffer DMA maps. 1171 */ 1172 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1173 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1174 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1175 aprint_error_dev(self, "unable to create rx DMA map %d" 1176 ", error = %d\n", i, error); 1177 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 1178 } 1179 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1180 } 1181 1182 /* 1183 * Reset the chip to a known state. 1184 */ 1185 sipcom_reset(sc); 1186 1187 /* 1188 * Read the Ethernet address from the EEPROM. This might 1189 * also fetch other stuff from the EEPROM and stash it 1190 * in the softc. 1191 */ 1192 sc->sc_cfg = 0; 1193 if (!sc->sc_gigabit) { 1194 if (SIP_SIS900_REV(sc, SIS_REV_635) || 1195 SIP_SIS900_REV(sc, SIS_REV_900B)) 1196 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1197 1198 if (SIP_SIS900_REV(sc, SIS_REV_635) || 1199 SIP_SIS900_REV(sc, SIS_REV_960) || 1200 SIP_SIS900_REV(sc, SIS_REV_900B)) 1201 sc->sc_cfg |= 1202 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1203 CFG_EDBMASTEN); 1204 } 1205 1206 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1207 1208 aprint_normal_dev(self, "Ethernet address %s\n",ether_sprintf(enaddr)); 1209 1210 /* 1211 * Initialize the configuration register: aggressive PCI 1212 * bus request algorithm, default backoff, default OW timer, 1213 * default parity error detection. 1214 * 1215 * NOTE: "Big endian mode" is useless on the SiS900 and 1216 * friends -- it affects packet data, not descriptors. 1217 */ 1218 if (sc->sc_gigabit) 1219 sipcom_dp83820_attach(sc, pa); 1220 1221 /* 1222 * Initialize our media structures and probe the MII. 1223 */ 1224 mii->mii_ifp = ifp; 1225 mii->mii_readreg = sip->sip_variant->sipv_mii_readreg; 1226 mii->mii_writereg = sip->sip_variant->sipv_mii_writereg; 1227 mii->mii_statchg = sip->sip_variant->sipv_mii_statchg; 1228 sc->sc_ethercom.ec_mii = mii; 1229 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 1230 sipcom_mediastatus); 1231 1232 /* 1233 * XXX We cannot handle flow control on the DP83815. 1234 */ 1235 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1236 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 1237 MII_OFFSET_ANY, 0); 1238 else 1239 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 1240 MII_OFFSET_ANY, MIIF_DOPAUSE); 1241 if (LIST_FIRST(&mii->mii_phys) == NULL) { 1242 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 1243 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 1244 } else 1245 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1246 1247 ifp = &sc->sc_ethercom.ec_if; 1248 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1249 ifp->if_softc = sc; 1250 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1251 sc->sc_if_flags = ifp->if_flags; 1252 ifp->if_ioctl = sipcom_ioctl; 1253 ifp->if_start = sipcom_start; 1254 ifp->if_watchdog = sipcom_watchdog; 1255 ifp->if_init = sipcom_init; 1256 ifp->if_stop = sipcom_stop; 1257 IFQ_SET_READY(&ifp->if_snd); 1258 1259 /* 1260 * We can support 802.1Q VLAN-sized frames. 1261 */ 1262 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1263 1264 if (sc->sc_gigabit) { 1265 /* 1266 * And the DP83820 can do VLAN tagging in hardware, and 1267 * support the jumbo Ethernet MTU. 1268 */ 1269 sc->sc_ethercom.ec_capabilities |= 1270 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1271 sc->sc_ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 1272 1273 /* 1274 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1275 * in hardware. 1276 */ 1277 ifp->if_capabilities |= 1278 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1279 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1280 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1281 } 1282 1283 /* 1284 * Attach the interface. 1285 */ 1286 if_attach(ifp); 1287 if_deferred_start_init(ifp, NULL); 1288 ether_ifattach(ifp, enaddr); 1289 ether_set_ifflags_cb(&sc->sc_ethercom, sip_ifflags_cb); 1290 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1291 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1292 sc->sc_prev.if_capenable = ifp->if_capenable; 1293 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 1294 RND_TYPE_NET, RND_FLAG_DEFAULT); 1295 1296 /* 1297 * The number of bytes that must be available in 1298 * the Tx FIFO before the bus master can DMA more 1299 * data into the FIFO. 1300 */ 1301 sc->sc_tx_fill_thresh = 64 / 32; 1302 1303 /* 1304 * Start at a drain threshold of 512 bytes. We will 1305 * increase it if a DMA underrun occurs. 1306 * 1307 * XXX The minimum value of this variable should be 1308 * tuned. We may be able to improve performance 1309 * by starting with a lower value. That, however, 1310 * may trash the first few outgoing packets if the 1311 * PCI bus is saturated. 1312 */ 1313 if (sc->sc_gigabit) 1314 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1315 else 1316 sc->sc_tx_drain_thresh = 1504 / 32; 1317 1318 /* 1319 * Initialize the Rx FIFO drain threshold. 1320 * 1321 * This is in units of 8 bytes. 1322 * 1323 * We should never set this value lower than 2; 14 bytes are 1324 * required to filter the packet. 1325 */ 1326 sc->sc_rx_drain_thresh = 128 / 8; 1327 1328 #ifdef SIP_EVENT_COUNTERS 1329 /* 1330 * Attach event counters. 1331 */ 1332 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1333 NULL, device_xname(sc->sc_dev), "txsstall"); 1334 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1335 NULL, device_xname(sc->sc_dev), "txdstall"); 1336 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1337 NULL, device_xname(sc->sc_dev), "txforceintr"); 1338 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1339 NULL, device_xname(sc->sc_dev), "txdintr"); 1340 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1341 NULL, device_xname(sc->sc_dev), "txiintr"); 1342 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1343 NULL, device_xname(sc->sc_dev), "rxintr"); 1344 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1345 NULL, device_xname(sc->sc_dev), "hiberr"); 1346 if (!sc->sc_gigabit) { 1347 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1348 NULL, device_xname(sc->sc_dev), "rxpause"); 1349 } else { 1350 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1351 NULL, device_xname(sc->sc_dev), "rxpause"); 1352 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1353 NULL, device_xname(sc->sc_dev), "txpause"); 1354 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1355 NULL, device_xname(sc->sc_dev), "rxipsum"); 1356 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1357 NULL, device_xname(sc->sc_dev), "rxtcpsum"); 1358 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1359 NULL, device_xname(sc->sc_dev), "rxudpsum"); 1360 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1361 NULL, device_xname(sc->sc_dev), "txipsum"); 1362 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1363 NULL, device_xname(sc->sc_dev), "txtcpsum"); 1364 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1365 NULL, device_xname(sc->sc_dev), "txudpsum"); 1366 } 1367 #endif /* SIP_EVENT_COUNTERS */ 1368 1369 if (pmf_device_register(self, sipcom_suspend, sipcom_resume)) 1370 pmf_class_network_register(self, ifp); 1371 else 1372 aprint_error_dev(self, "couldn't establish power handler\n"); 1373 } 1374 1375 static inline void 1376 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1377 uint64_t capenable) 1378 { 1379 uint32_t extsts; 1380 #ifdef DEBUG 1381 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1382 #endif 1383 /* 1384 * If VLANs are enabled and the packet has a VLAN tag, set 1385 * up the descriptor to encapsulate the packet for us. 1386 * 1387 * This apparently has to be on the last descriptor of 1388 * the packet. 1389 */ 1390 1391 /* 1392 * Byte swapping is tricky. We need to provide the tag 1393 * in a network byte order. On a big-endian machine, 1394 * the byteorder is correct, but we need to swap it 1395 * anyway, because this will be undone by the outside 1396 * htole32(). That's why there must be an 1397 * unconditional swap instead of htons() inside. 1398 */ 1399 if (vlan_has_tag(m0)) { 1400 sc->sc_txdescs[lasttx].sipd_extsts |= 1401 htole32(EXTSTS_VPKT | 1402 (bswap16(vlan_get_tag(m0)) & 1403 EXTSTS_VTCI)); 1404 } 1405 1406 /* 1407 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1408 * checksumming, set up the descriptor to do this work 1409 * for us. 1410 * 1411 * This apparently has to be on the first descriptor of 1412 * the packet. 1413 * 1414 * Byte-swap constants so the compiler can optimize. 1415 */ 1416 extsts = 0; 1417 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1418 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1419 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1420 extsts |= htole32(EXTSTS_IPPKT); 1421 } 1422 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1423 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1424 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1425 extsts |= htole32(EXTSTS_TCPPKT); 1426 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1427 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1428 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1429 extsts |= htole32(EXTSTS_UDPPKT); 1430 } 1431 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1432 } 1433 1434 /* 1435 * sip_start: [ifnet interface function] 1436 * 1437 * Start packet transmission on the interface. 1438 */ 1439 static void 1440 sipcom_start(struct ifnet *ifp) 1441 { 1442 struct sip_softc *sc = ifp->if_softc; 1443 struct mbuf *m0; 1444 struct mbuf *m; 1445 struct sip_txsoft *txs; 1446 bus_dmamap_t dmamap; 1447 int error, nexttx, lasttx, seg; 1448 int ofree = sc->sc_txfree; 1449 #if 0 1450 int firsttx = sc->sc_txnext; 1451 #endif 1452 1453 /* 1454 * If we've been told to pause, don't transmit any more packets. 1455 */ 1456 if (!sc->sc_gigabit && sc->sc_paused) 1457 ifp->if_flags |= IFF_OACTIVE; 1458 1459 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1460 return; 1461 1462 /* 1463 * Loop through the send queue, setting up transmit descriptors 1464 * until we drain the queue, or use up all available transmit 1465 * descriptors. 1466 */ 1467 for (;;) { 1468 /* Get a work queue entry. */ 1469 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1470 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1471 break; 1472 } 1473 1474 /* 1475 * Grab a packet off the queue. 1476 */ 1477 IFQ_POLL(&ifp->if_snd, m0); 1478 if (m0 == NULL) 1479 break; 1480 m = NULL; 1481 1482 dmamap = txs->txs_dmamap; 1483 1484 /* 1485 * Load the DMA map. If this fails, the packet either 1486 * didn't fit in the alloted number of segments, or we 1487 * were short on resources. 1488 */ 1489 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1490 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1491 /* In the non-gigabit case, we'll copy and try again. */ 1492 if (error != 0 && !sc->sc_gigabit) { 1493 MGETHDR(m, M_DONTWAIT, MT_DATA); 1494 if (m == NULL) { 1495 printf("%s: unable to allocate Tx mbuf\n", 1496 device_xname(sc->sc_dev)); 1497 break; 1498 } 1499 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1500 if (m0->m_pkthdr.len > MHLEN) { 1501 MCLGET(m, M_DONTWAIT); 1502 if ((m->m_flags & M_EXT) == 0) { 1503 printf("%s: unable to allocate Tx " 1504 "cluster\n", 1505 device_xname(sc->sc_dev)); 1506 m_freem(m); 1507 break; 1508 } 1509 } 1510 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1511 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1512 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1513 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1514 if (error) { 1515 printf("%s: unable to load Tx buffer, error = " 1516 "%d\n", device_xname(sc->sc_dev), error); 1517 break; 1518 } 1519 } else if (error == EFBIG) { 1520 /* 1521 * For the too-many-segments case, we simply 1522 * report an error and drop the packet, 1523 * since we can't sanely copy a jumbo packet 1524 * to a single buffer. 1525 */ 1526 printf("%s: Tx packet consumes too many DMA segments, " 1527 "dropping...\n", device_xname(sc->sc_dev)); 1528 IFQ_DEQUEUE(&ifp->if_snd, m0); 1529 m_freem(m0); 1530 continue; 1531 } else if (error != 0) { 1532 /* 1533 * Short on resources, just stop for now. 1534 */ 1535 break; 1536 } 1537 1538 /* 1539 * Ensure we have enough descriptors free to describe 1540 * the packet. Note, we always reserve one descriptor 1541 * at the end of the ring as a termination point, to 1542 * prevent wrap-around. 1543 */ 1544 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1545 /* 1546 * Not enough free descriptors to transmit this 1547 * packet. We haven't committed anything yet, 1548 * so just unload the DMA map, put the packet 1549 * back on the queue, and punt. Notify the upper 1550 * layer that there are not more slots left. 1551 * 1552 * XXX We could allocate an mbuf and copy, but 1553 * XXX is it worth it? 1554 */ 1555 ifp->if_flags |= IFF_OACTIVE; 1556 bus_dmamap_unload(sc->sc_dmat, dmamap); 1557 if (m != NULL) 1558 m_freem(m); 1559 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1560 break; 1561 } 1562 1563 IFQ_DEQUEUE(&ifp->if_snd, m0); 1564 if (m != NULL) { 1565 m_freem(m0); 1566 m0 = m; 1567 } 1568 1569 /* 1570 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1571 */ 1572 1573 /* Sync the DMA map. */ 1574 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1575 BUS_DMASYNC_PREWRITE); 1576 1577 /* 1578 * Initialize the transmit descriptors. 1579 */ 1580 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1581 seg < dmamap->dm_nsegs; 1582 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1583 /* 1584 * If this is the first descriptor we're 1585 * enqueueing, don't set the OWN bit just 1586 * yet. That could cause a race condition. 1587 * We'll do it below. 1588 */ 1589 *sipd_bufptr(sc, &sc->sc_txdescs[nexttx]) = 1590 htole32(dmamap->dm_segs[seg].ds_addr); 1591 *sipd_cmdsts(sc, &sc->sc_txdescs[nexttx]) = 1592 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) 1593 | CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1594 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1595 lasttx = nexttx; 1596 } 1597 1598 /* Clear the MORE bit on the last segment. */ 1599 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) &= 1600 htole32(~CMDSTS_MORE); 1601 1602 /* 1603 * If we're in the interrupt delay window, delay the 1604 * interrupt. 1605 */ 1606 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1607 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1608 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) |= 1609 htole32(CMDSTS_INTR); 1610 sc->sc_txwin = 0; 1611 } 1612 1613 if (sc->sc_gigabit) 1614 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1615 1616 /* Sync the descriptors we're using. */ 1617 sip_cdtxsync(sc, sc->sc_txnext, dmamap->dm_nsegs, 1618 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1619 1620 /* 1621 * The entire packet is set up. Give the first descrptor 1622 * to the chip now. 1623 */ 1624 *sipd_cmdsts(sc, &sc->sc_txdescs[sc->sc_txnext]) |= 1625 htole32(CMDSTS_OWN); 1626 sip_cdtxsync(sc, sc->sc_txnext, 1, 1627 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1628 1629 /* 1630 * Store a pointer to the packet so we can free it later, 1631 * and remember what txdirty will be once the packet is 1632 * done. 1633 */ 1634 txs->txs_mbuf = m0; 1635 txs->txs_firstdesc = sc->sc_txnext; 1636 txs->txs_lastdesc = lasttx; 1637 1638 /* Advance the tx pointer. */ 1639 sc->sc_txfree -= dmamap->dm_nsegs; 1640 sc->sc_txnext = nexttx; 1641 1642 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1643 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1644 1645 /* Pass the packet to any BPF listeners. */ 1646 bpf_mtap(ifp, m0, BPF_D_OUT); 1647 } 1648 1649 if (txs == NULL || sc->sc_txfree == 0) { 1650 /* No more slots left; notify upper layer. */ 1651 ifp->if_flags |= IFF_OACTIVE; 1652 } 1653 1654 if (sc->sc_txfree != ofree) { 1655 /* 1656 * Start the transmit process. Note, the manual says 1657 * that if there are no pending transmissions in the 1658 * chip's internal queue (indicated by TXE being clear), 1659 * then the driver software must set the TXDP to the 1660 * first descriptor to be transmitted. However, if we 1661 * do this, it causes serious performance degredation on 1662 * the DP83820 under load, not setting TXDP doesn't seem 1663 * to adversely affect the SiS 900 or DP83815. 1664 * 1665 * Well, I guess it wouldn't be the first time a manual 1666 * has lied -- and they could be speaking of the NULL- 1667 * terminated descriptor list case, rather than OWN- 1668 * terminated rings. 1669 */ 1670 #if 0 1671 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1672 CR_TXE) == 0) { 1673 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1674 SIP_CDTXADDR(sc, firsttx)); 1675 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1676 } 1677 #else 1678 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1679 #endif 1680 1681 /* Set a watchdog timer in case the chip flakes out. */ 1682 /* Gigabit autonegotiation takes 5 seconds. */ 1683 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1684 } 1685 } 1686 1687 /* 1688 * sip_watchdog: [ifnet interface function] 1689 * 1690 * Watchdog timer handler. 1691 */ 1692 static void 1693 sipcom_watchdog(struct ifnet *ifp) 1694 { 1695 struct sip_softc *sc = ifp->if_softc; 1696 1697 /* 1698 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1699 * If we get a timeout, try and sweep up transmit descriptors. 1700 * If we manage to sweep them all up, ignore the lack of 1701 * interrupt. 1702 */ 1703 sipcom_txintr(sc); 1704 1705 if (sc->sc_txfree != sc->sc_ntxdesc) { 1706 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1707 if_statinc(ifp, if_oerrors); 1708 1709 /* Reset the interface. */ 1710 (void) sipcom_init(ifp); 1711 } else if (ifp->if_flags & IFF_DEBUG) 1712 printf("%s: recovered from device timeout\n", 1713 device_xname(sc->sc_dev)); 1714 1715 /* Try to get more packets going. */ 1716 sipcom_start(ifp); 1717 } 1718 1719 /* If the interface is up and running, only modify the receive 1720 * filter when setting promiscuous or debug mode. Otherwise fall 1721 * through to ether_ioctl, which will reset the chip. 1722 */ 1723 static int 1724 sip_ifflags_cb(struct ethercom *ec) 1725 { 1726 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1727 == (sc)->sc_ethercom.ec_capenable) \ 1728 && ((sc)->sc_prev.is_vlan == \ 1729 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1730 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1731 struct ifnet *ifp = &ec->ec_if; 1732 struct sip_softc *sc = ifp->if_softc; 1733 u_short change = ifp->if_flags ^ sc->sc_if_flags; 1734 1735 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0 || !COMPARE_EC(sc) || 1736 !COMPARE_IC(sc, ifp)) 1737 return ENETRESET; 1738 /* Set up the receive filter. */ 1739 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1740 return 0; 1741 } 1742 1743 /* 1744 * sip_ioctl: [ifnet interface function] 1745 * 1746 * Handle control requests from the operator. 1747 */ 1748 static int 1749 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1750 { 1751 struct sip_softc *sc = ifp->if_softc; 1752 struct ifreq *ifr = (struct ifreq *)data; 1753 int s, error; 1754 1755 s = splnet(); 1756 1757 switch (cmd) { 1758 case SIOCSIFMEDIA: 1759 /* Flow control requires full-duplex mode. */ 1760 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1761 (ifr->ifr_media & IFM_FDX) == 0) 1762 ifr->ifr_media &= ~IFM_ETH_FMASK; 1763 1764 /* XXX */ 1765 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1766 ifr->ifr_media &= ~IFM_ETH_FMASK; 1767 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1768 if (sc->sc_gigabit && 1769 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1770 /* We can do both TXPAUSE and RXPAUSE. */ 1771 ifr->ifr_media |= 1772 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1773 } else if (ifr->ifr_media & IFM_FLOW) { 1774 /* 1775 * Both TXPAUSE and RXPAUSE must be set. 1776 * (SiS900 and DP83815 don't have PAUSE_ASYM 1777 * feature.) 1778 * 1779 * XXX Can SiS900 and DP83815 send PAUSE? 1780 */ 1781 ifr->ifr_media |= 1782 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1783 } 1784 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1785 } 1786 /*FALLTHROUGH*/ 1787 default: 1788 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1789 break; 1790 1791 error = 0; 1792 1793 if (cmd == SIOCSIFCAP) 1794 error = (*ifp->if_init)(ifp); 1795 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1796 ; 1797 else if (ifp->if_flags & IFF_RUNNING) { 1798 /* 1799 * Multicast list has changed; set the hardware filter 1800 * accordingly. 1801 */ 1802 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1803 } 1804 break; 1805 } 1806 1807 /* Try to get more packets going. */ 1808 sipcom_start(ifp); 1809 1810 sc->sc_if_flags = ifp->if_flags; 1811 splx(s); 1812 return error; 1813 } 1814 1815 /* 1816 * sip_intr: 1817 * 1818 * Interrupt service routine. 1819 */ 1820 static int 1821 sipcom_intr(void *arg) 1822 { 1823 struct sip_softc *sc = arg; 1824 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1825 uint32_t isr; 1826 int handled = 0; 1827 1828 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 1829 return 0; 1830 1831 /* Disable interrupts. */ 1832 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1833 1834 for (;;) { 1835 /* Reading clears interrupt. */ 1836 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1837 if ((isr & sc->sc_imr) == 0) 1838 break; 1839 1840 rnd_add_uint32(&sc->rnd_source, isr); 1841 1842 handled = 1; 1843 1844 if ((ifp->if_flags & IFF_RUNNING) == 0) 1845 break; 1846 1847 if (isr & (ISR_RXORN | ISR_RXIDLE | ISR_RXDESC)) { 1848 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1849 1850 /* Grab any new packets. */ 1851 (*sc->sc_rxintr)(sc); 1852 1853 if (isr & ISR_RXORN) { 1854 printf("%s: receive FIFO overrun\n", 1855 device_xname(sc->sc_dev)); 1856 1857 /* XXX adjust rx_drain_thresh? */ 1858 } 1859 1860 if (isr & ISR_RXIDLE) { 1861 printf("%s: receive ring overrun\n", 1862 device_xname(sc->sc_dev)); 1863 1864 /* Get the receive process going again. */ 1865 bus_space_write_4(sc->sc_st, sc->sc_sh, 1866 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1867 bus_space_write_4(sc->sc_st, sc->sc_sh, 1868 SIP_CR, CR_RXE); 1869 } 1870 } 1871 1872 if (isr & (ISR_TXURN | ISR_TXDESC | ISR_TXIDLE)) { 1873 #ifdef SIP_EVENT_COUNTERS 1874 if (isr & ISR_TXDESC) 1875 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1876 else if (isr & ISR_TXIDLE) 1877 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1878 #endif 1879 1880 /* Sweep up transmit descriptors. */ 1881 sipcom_txintr(sc); 1882 1883 if (isr & ISR_TXURN) { 1884 uint32_t thresh; 1885 int txfifo_size = (sc->sc_gigabit) 1886 ? DP83820_SIP_TXFIFO_SIZE 1887 : OTHER_SIP_TXFIFO_SIZE; 1888 1889 printf("%s: transmit FIFO underrun", 1890 device_xname(sc->sc_dev)); 1891 thresh = sc->sc_tx_drain_thresh + 1; 1892 if (thresh <= __SHIFTOUT_MASK(sc->sc_bits.b_txcfg_drth_mask) 1893 && (thresh * 32) <= (txfifo_size - 1894 (sc->sc_tx_fill_thresh * 32))) { 1895 printf("; increasing Tx drain " 1896 "threshold to %u bytes\n", 1897 thresh * 32); 1898 sc->sc_tx_drain_thresh = thresh; 1899 (void) sipcom_init(ifp); 1900 } else { 1901 (void) sipcom_init(ifp); 1902 printf("\n"); 1903 } 1904 } 1905 } 1906 1907 if (sc->sc_imr & (ISR_PAUSE_END | ISR_PAUSE_ST)) { 1908 if (isr & ISR_PAUSE_ST) { 1909 sc->sc_paused = 1; 1910 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1911 ifp->if_flags |= IFF_OACTIVE; 1912 } 1913 if (isr & ISR_PAUSE_END) { 1914 sc->sc_paused = 0; 1915 ifp->if_flags &= ~IFF_OACTIVE; 1916 } 1917 } 1918 1919 if (isr & ISR_HIBERR) { 1920 int want_init = 0; 1921 1922 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1923 1924 #define PRINTERR(bit, str) \ 1925 do { \ 1926 if ((isr & (bit)) != 0) { \ 1927 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1928 printf("%s: %s\n", \ 1929 device_xname(sc->sc_dev), str); \ 1930 want_init = 1; \ 1931 } \ 1932 } while (/*CONSTCOND*/0) 1933 1934 PRINTERR(sc->sc_bits.b_isr_dperr, "parity error"); 1935 PRINTERR(sc->sc_bits.b_isr_sserr, "system error"); 1936 PRINTERR(sc->sc_bits.b_isr_rmabt, "master abort"); 1937 PRINTERR(sc->sc_bits.b_isr_rtabt, "target abort"); 1938 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1939 /* 1940 * Ignore: 1941 * Tx reset complete 1942 * Rx reset complete 1943 */ 1944 if (want_init) 1945 (void) sipcom_init(ifp); 1946 #undef PRINTERR 1947 } 1948 } 1949 1950 /* Re-enable interrupts. */ 1951 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1952 1953 /* Try to get more packets going. */ 1954 if_schedule_deferred_start(ifp); 1955 1956 return handled; 1957 } 1958 1959 /* 1960 * sip_txintr: 1961 * 1962 * Helper; handle transmit interrupts. 1963 */ 1964 static void 1965 sipcom_txintr(struct sip_softc *sc) 1966 { 1967 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1968 struct sip_txsoft *txs; 1969 uint32_t cmdsts; 1970 1971 if (sc->sc_paused == 0) 1972 ifp->if_flags &= ~IFF_OACTIVE; 1973 1974 /* 1975 * Go through our Tx list and free mbufs for those 1976 * frames which have been transmitted. 1977 */ 1978 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1979 sip_cdtxsync(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1980 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1981 1982 cmdsts = le32toh(*sipd_cmdsts(sc, 1983 &sc->sc_txdescs[txs->txs_lastdesc])); 1984 if (cmdsts & CMDSTS_OWN) 1985 break; 1986 1987 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1988 1989 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1990 1991 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1992 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1993 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1994 m_freem(txs->txs_mbuf); 1995 txs->txs_mbuf = NULL; 1996 1997 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1998 1999 /* Check for errors and collisions. */ 2000 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 2001 if (cmdsts & (CMDSTS_Tx_TXA | CMDSTS_Tx_TFU | CMDSTS_Tx_ED | 2002 CMDSTS_Tx_EC)) { 2003 if_statinc_ref(nsr, if_oerrors); 2004 if (cmdsts & CMDSTS_Tx_EC) 2005 if_statadd_ref(nsr, if_collisions, 16); 2006 if (ifp->if_flags & IFF_DEBUG) { 2007 if (cmdsts & CMDSTS_Tx_ED) 2008 printf("%s: excessive deferral\n", 2009 device_xname(sc->sc_dev)); 2010 if (cmdsts & CMDSTS_Tx_EC) 2011 printf("%s: excessive collisions\n", 2012 device_xname(sc->sc_dev)); 2013 } 2014 } else { 2015 /* Packet was transmitted successfully. */ 2016 if_statinc_ref(nsr, if_opackets); 2017 if (CMDSTS_COLLISIONS(cmdsts)) 2018 if_statadd_ref(nsr, if_collisions, 2019 CMDSTS_COLLISIONS(cmdsts)); 2020 } 2021 IF_STAT_PUTREF(ifp); 2022 } 2023 2024 /* 2025 * If there are no more pending transmissions, cancel the watchdog 2026 * timer. 2027 */ 2028 if (txs == NULL) { 2029 ifp->if_timer = 0; 2030 sc->sc_txwin = 0; 2031 } 2032 } 2033 2034 /* 2035 * gsip_rxintr: 2036 * 2037 * Helper; handle receive interrupts on gigabit parts. 2038 */ 2039 static void 2040 gsip_rxintr(struct sip_softc *sc) 2041 { 2042 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2043 struct sip_rxsoft *rxs; 2044 struct mbuf *m; 2045 uint32_t cmdsts, extsts; 2046 int i, len; 2047 2048 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2049 rxs = &sc->sc_rxsoft[i]; 2050 2051 sip_cdrxsync(sc, i, 2052 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2053 2054 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2055 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 2056 len = CMDSTS_SIZE(sc, cmdsts); 2057 2058 /* 2059 * NOTE: OWN is set if owned by _consumer_. We're the 2060 * consumer of the receive ring, so if the bit is clear, 2061 * we have processed all of the packets. 2062 */ 2063 if ((cmdsts & CMDSTS_OWN) == 0) { 2064 /* 2065 * We have processed all of the receive buffers. 2066 */ 2067 break; 2068 } 2069 2070 if (__predict_false(sc->sc_rxdiscard)) { 2071 sip_init_rxdesc(sc, i); 2072 if ((cmdsts & CMDSTS_MORE) == 0) { 2073 /* Reset our state. */ 2074 sc->sc_rxdiscard = 0; 2075 } 2076 continue; 2077 } 2078 2079 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2080 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2081 2082 m = rxs->rxs_mbuf; 2083 2084 /* 2085 * Add a new receive buffer to the ring. 2086 */ 2087 if (sipcom_add_rxbuf(sc, i) != 0) { 2088 /* 2089 * Failed, throw away what we've done so 2090 * far, and discard the rest of the packet. 2091 */ 2092 if_statinc(ifp, if_ierrors); 2093 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2094 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2095 sip_init_rxdesc(sc, i); 2096 if (cmdsts & CMDSTS_MORE) 2097 sc->sc_rxdiscard = 1; 2098 if (sc->sc_rxhead != NULL) 2099 m_freem(sc->sc_rxhead); 2100 sip_rxchain_reset(sc); 2101 continue; 2102 } 2103 2104 sip_rxchain_link(sc, m); 2105 2106 m->m_len = len; 2107 2108 /* 2109 * If this is not the end of the packet, keep 2110 * looking. 2111 */ 2112 if (cmdsts & CMDSTS_MORE) { 2113 sc->sc_rxlen += len; 2114 continue; 2115 } 2116 2117 /* 2118 * Okay, we have the entire packet now. The chip includes 2119 * the FCS, so we need to trim it. 2120 */ 2121 m->m_len -= ETHER_CRC_LEN; 2122 2123 *sc->sc_rxtailp = NULL; 2124 len = m->m_len + sc->sc_rxlen; 2125 m = sc->sc_rxhead; 2126 2127 sip_rxchain_reset(sc); 2128 2129 /* If an error occurred, update stats and drop the packet. */ 2130 if (cmdsts & (CMDSTS_Rx_RXA | CMDSTS_Rx_RUNT | 2131 CMDSTS_Rx_ISE | CMDSTS_Rx_CRCE | CMDSTS_Rx_FAE)) { 2132 if_statinc(ifp, if_ierrors); 2133 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2134 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2135 /* Receive overrun handled elsewhere. */ 2136 printf("%s: receive descriptor error\n", 2137 device_xname(sc->sc_dev)); 2138 } 2139 #define PRINTERR(bit, str) \ 2140 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2141 (cmdsts & (bit)) != 0) \ 2142 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2143 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2144 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2145 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2146 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2147 #undef PRINTERR 2148 m_freem(m); 2149 continue; 2150 } 2151 2152 /* 2153 * If the packet is small enough to fit in a 2154 * single header mbuf, allocate one and copy 2155 * the data into it. This greatly reduces 2156 * memory consumption when we receive lots 2157 * of small packets. 2158 */ 2159 if (gsip_copy_small != 0 && len <= (MHLEN - 2)) { 2160 struct mbuf *nm; 2161 MGETHDR(nm, M_DONTWAIT, MT_DATA); 2162 if (nm == NULL) { 2163 if_statinc(ifp, if_ierrors); 2164 m_freem(m); 2165 continue; 2166 } 2167 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2168 nm->m_data += 2; 2169 nm->m_pkthdr.len = nm->m_len = len; 2170 m_copydata(m, 0, len, mtod(nm, void *)); 2171 m_freem(m); 2172 m = nm; 2173 } 2174 #ifndef __NO_STRICT_ALIGNMENT 2175 else { 2176 /* 2177 * The DP83820's receive buffers must be 4-byte 2178 * aligned. But this means that the data after 2179 * the Ethernet header is misaligned. To compensate, 2180 * we have artificially shortened the buffer size 2181 * in the descriptor, and we do an overlapping copy 2182 * of the data two bytes further in (in the first 2183 * buffer of the chain only). 2184 */ 2185 memmove(mtod(m, char *) + 2, mtod(m, void *), 2186 m->m_len); 2187 m->m_data += 2; 2188 } 2189 #endif /* ! __NO_STRICT_ALIGNMENT */ 2190 2191 /* 2192 * If VLANs are enabled, VLAN packets have been unwrapped 2193 * for us. Associate the tag with the packet. 2194 */ 2195 2196 /* 2197 * Again, byte swapping is tricky. Hardware provided 2198 * the tag in the network byte order, but extsts was 2199 * passed through le32toh() in the meantime. On a 2200 * big-endian machine, we need to swap it again. On a 2201 * little-endian machine, we need to convert from the 2202 * network to host byte order. This means that we must 2203 * swap it in any case, so unconditional swap instead 2204 * of htons() is used. 2205 */ 2206 if ((extsts & EXTSTS_VPKT) != 0) { 2207 vlan_set_tag(m, bswap16(extsts & EXTSTS_VTCI)); 2208 } 2209 2210 /* 2211 * Set the incoming checksum information for the 2212 * packet. 2213 */ 2214 if ((extsts & EXTSTS_IPPKT) != 0) { 2215 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2216 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2217 if (extsts & EXTSTS_Rx_IPERR) 2218 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2219 if (extsts & EXTSTS_TCPPKT) { 2220 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2221 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2222 if (extsts & EXTSTS_Rx_TCPERR) 2223 m->m_pkthdr.csum_flags |= 2224 M_CSUM_TCP_UDP_BAD; 2225 } else if (extsts & EXTSTS_UDPPKT) { 2226 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2227 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2228 if (extsts & EXTSTS_Rx_UDPERR) 2229 m->m_pkthdr.csum_flags |= 2230 M_CSUM_TCP_UDP_BAD; 2231 } 2232 } 2233 2234 m_set_rcvif(m, ifp); 2235 m->m_pkthdr.len = len; 2236 2237 /* Pass it on. */ 2238 if_percpuq_enqueue(ifp->if_percpuq, m); 2239 } 2240 2241 /* Update the receive pointer. */ 2242 sc->sc_rxptr = i; 2243 } 2244 2245 /* 2246 * sip_rxintr: 2247 * 2248 * Helper; handle receive interrupts on 10/100 parts. 2249 */ 2250 static void 2251 sip_rxintr(struct sip_softc *sc) 2252 { 2253 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2254 struct sip_rxsoft *rxs; 2255 struct mbuf *m; 2256 uint32_t cmdsts; 2257 int i, len; 2258 2259 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2260 rxs = &sc->sc_rxsoft[i]; 2261 2262 sip_cdrxsync(sc, i, 2263 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2264 2265 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2266 2267 /* 2268 * NOTE: OWN is set if owned by _consumer_. We're the 2269 * consumer of the receive ring, so if the bit is clear, 2270 * we have processed all of the packets. 2271 */ 2272 if ((cmdsts & CMDSTS_OWN) == 0) { 2273 /* 2274 * We have processed all of the receive buffers. 2275 */ 2276 break; 2277 } 2278 2279 /* If any collisions were seen on the wire, count one. */ 2280 if (cmdsts & CMDSTS_Rx_COL) 2281 if_statinc(ifp, if_collisions); 2282 2283 /* 2284 * If an error occurred, update stats, clear the status 2285 * word, and leave the packet buffer in place. It will 2286 * simply be reused the next time the ring comes around. 2287 */ 2288 if (cmdsts & (CMDSTS_Rx_RXA | CMDSTS_Rx_RUNT | 2289 CMDSTS_Rx_ISE | CMDSTS_Rx_CRCE | CMDSTS_Rx_FAE)) { 2290 if_statinc(ifp, if_ierrors); 2291 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2292 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2293 /* Receive overrun handled elsewhere. */ 2294 printf("%s: receive descriptor error\n", 2295 device_xname(sc->sc_dev)); 2296 } 2297 #define PRINTERR(bit, str) \ 2298 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2299 (cmdsts & (bit)) != 0) \ 2300 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2301 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2302 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2303 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2304 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2305 #undef PRINTERR 2306 sip_init_rxdesc(sc, i); 2307 continue; 2308 } 2309 2310 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2311 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2312 2313 /* 2314 * No errors; receive the packet. Note, the SiS 900 2315 * includes the CRC with every packet. 2316 */ 2317 len = CMDSTS_SIZE(sc, cmdsts) - ETHER_CRC_LEN; 2318 2319 #ifdef __NO_STRICT_ALIGNMENT 2320 /* 2321 * If the packet is small enough to fit in a 2322 * single header mbuf, allocate one and copy 2323 * the data into it. This greatly reduces 2324 * memory consumption when we receive lots 2325 * of small packets. 2326 * 2327 * Otherwise, we add a new buffer to the receive 2328 * chain. If this fails, we drop the packet and 2329 * recycle the old buffer. 2330 */ 2331 if (sip_copy_small != 0 && len <= MHLEN) { 2332 MGETHDR(m, M_DONTWAIT, MT_DATA); 2333 if (m == NULL) 2334 goto dropit; 2335 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2336 memcpy(mtod(m, void *), 2337 mtod(rxs->rxs_mbuf, void *), len); 2338 sip_init_rxdesc(sc, i); 2339 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2340 rxs->rxs_dmamap->dm_mapsize, 2341 BUS_DMASYNC_PREREAD); 2342 } else { 2343 m = rxs->rxs_mbuf; 2344 if (sipcom_add_rxbuf(sc, i) != 0) { 2345 dropit: 2346 if_statinc(ifp, if_ierrors); 2347 sip_init_rxdesc(sc, i); 2348 bus_dmamap_sync(sc->sc_dmat, 2349 rxs->rxs_dmamap, 0, 2350 rxs->rxs_dmamap->dm_mapsize, 2351 BUS_DMASYNC_PREREAD); 2352 continue; 2353 } 2354 } 2355 #else 2356 /* 2357 * The SiS 900's receive buffers must be 4-byte aligned. 2358 * But this means that the data after the Ethernet header 2359 * is misaligned. We must allocate a new buffer and 2360 * copy the data, shifted forward 2 bytes. 2361 */ 2362 MGETHDR(m, M_DONTWAIT, MT_DATA); 2363 if (m == NULL) { 2364 dropit: 2365 if_statinc(ifp, if_ierrors); 2366 sip_init_rxdesc(sc, i); 2367 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2368 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2369 continue; 2370 } 2371 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2372 if (len > (MHLEN - 2)) { 2373 MCLGET(m, M_DONTWAIT); 2374 if ((m->m_flags & M_EXT) == 0) { 2375 m_freem(m); 2376 goto dropit; 2377 } 2378 } 2379 m->m_data += 2; 2380 2381 /* 2382 * Note that we use clusters for incoming frames, so the 2383 * buffer is virtually contiguous. 2384 */ 2385 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2386 2387 /* Allow the receive descriptor to continue using its mbuf. */ 2388 sip_init_rxdesc(sc, i); 2389 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2390 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2391 #endif /* __NO_STRICT_ALIGNMENT */ 2392 2393 m_set_rcvif(m, ifp); 2394 m->m_pkthdr.len = m->m_len = len; 2395 2396 /* Pass it on. */ 2397 if_percpuq_enqueue(ifp->if_percpuq, m); 2398 } 2399 2400 /* Update the receive pointer. */ 2401 sc->sc_rxptr = i; 2402 } 2403 2404 /* 2405 * sip_tick: 2406 * 2407 * One second timer, used to tick the MII. 2408 */ 2409 static void 2410 sipcom_tick(void *arg) 2411 { 2412 struct sip_softc *sc = arg; 2413 int s; 2414 2415 s = splnet(); 2416 #ifdef SIP_EVENT_COUNTERS 2417 if (sc->sc_gigabit) { 2418 /* Read PAUSE related counts from MIB registers. */ 2419 sc->sc_ev_rxpause.ev_count += 2420 bus_space_read_4(sc->sc_st, sc->sc_sh, 2421 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2422 sc->sc_ev_txpause.ev_count += 2423 bus_space_read_4(sc->sc_st, sc->sc_sh, 2424 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2425 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2426 } 2427 #endif /* SIP_EVENT_COUNTERS */ 2428 mii_tick(&sc->sc_mii); 2429 splx(s); 2430 2431 callout_schedule(&sc->sc_tick_ch, hz); 2432 } 2433 2434 /* 2435 * sip_reset: 2436 * 2437 * Perform a soft reset on the SiS 900. 2438 */ 2439 static bool 2440 sipcom_reset(struct sip_softc *sc) 2441 { 2442 bus_space_tag_t st = sc->sc_st; 2443 bus_space_handle_t sh = sc->sc_sh; 2444 int i; 2445 2446 bus_space_write_4(st, sh, SIP_IER, 0); 2447 bus_space_write_4(st, sh, SIP_IMR, 0); 2448 bus_space_write_4(st, sh, SIP_RFCR, 0); 2449 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2450 2451 for (i = 0; i < SIP_TIMEOUT; i++) { 2452 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2453 break; 2454 delay(2); 2455 } 2456 2457 if (i == SIP_TIMEOUT) { 2458 printf("%s: reset failed to complete\n", 2459 device_xname(sc->sc_dev)); 2460 return false; 2461 } 2462 2463 delay(1000); 2464 2465 if (sc->sc_gigabit) { 2466 /* 2467 * Set the general purpose I/O bits. Do it here in case we 2468 * need to have GPIO set up to talk to the media interface. 2469 */ 2470 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2471 delay(1000); 2472 } 2473 return true; 2474 } 2475 2476 static void 2477 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2478 { 2479 uint32_t reg; 2480 bus_space_tag_t st = sc->sc_st; 2481 bus_space_handle_t sh = sc->sc_sh; 2482 /* 2483 * Initialize the VLAN/IP receive control register. 2484 * We enable checksum computation on all incoming 2485 * packets, and do not reject packets w/ bad checksums. 2486 */ 2487 reg = 0; 2488 if (capenable & 2489 (IFCAP_CSUM_IPv4_Rx | IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 2490 reg |= VRCR_IPEN; 2491 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2492 reg |= VRCR_VTDEN | VRCR_VTREN; 2493 bus_space_write_4(st, sh, SIP_VRCR, reg); 2494 2495 /* 2496 * Initialize the VLAN/IP transmit control register. 2497 * We enable outgoing checksum computation on a 2498 * per-packet basis. 2499 */ 2500 reg = 0; 2501 if (capenable & 2502 (IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx)) 2503 reg |= VTCR_PPCHK; 2504 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2505 reg |= VTCR_VPPTI; 2506 bus_space_write_4(st, sh, SIP_VTCR, reg); 2507 2508 /* 2509 * If we're using VLANs, initialize the VLAN data register. 2510 * To understand why we bswap the VLAN Ethertype, see section 2511 * 4.2.36 of the DP83820 manual. 2512 */ 2513 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2514 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2515 } 2516 2517 /* 2518 * sip_init: [ ifnet interface function ] 2519 * 2520 * Initialize the interface. Must be called at splnet(). 2521 */ 2522 static int 2523 sipcom_init(struct ifnet *ifp) 2524 { 2525 struct sip_softc *sc = ifp->if_softc; 2526 bus_space_tag_t st = sc->sc_st; 2527 bus_space_handle_t sh = sc->sc_sh; 2528 struct sip_txsoft *txs; 2529 struct sip_rxsoft *rxs; 2530 struct sip_desc *sipd; 2531 int i, error = 0; 2532 2533 if (device_is_active(sc->sc_dev)) { 2534 /* 2535 * Cancel any pending I/O. 2536 */ 2537 sipcom_stop(ifp, 0); 2538 } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 2539 !device_is_active(sc->sc_dev)) 2540 return 0; 2541 2542 /* 2543 * Reset the chip to a known state. 2544 */ 2545 if (!sipcom_reset(sc)) 2546 return EBUSY; 2547 2548 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2549 /* 2550 * DP83815 manual, page 78: 2551 * 4.4 Recommended Registers Configuration 2552 * For optimum performance of the DP83815, version noted 2553 * as DP83815CVNG (SRR = 203h), the listed register 2554 * modifications must be followed in sequence... 2555 * 2556 * It's not clear if this should be 302h or 203h because that 2557 * chip name is listed as SRR 302h in the description of the 2558 * SRR register. However, my revision 302h DP83815 on the 2559 * Netgear FA311 purchased in 02/2001 needs these settings 2560 * to avoid tons of errors in AcceptPerfectMatch (non- 2561 * IFF_PROMISC) mode. I do not know if other revisions need 2562 * this set or not. [briggs -- 09 March 2001] 2563 * 2564 * Note that only the low-order 12 bits of 0xe4 are documented 2565 * and that this sets reserved bits in that register. 2566 */ 2567 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2568 2569 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2570 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2571 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2572 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2573 2574 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2575 } 2576 2577 /* 2578 * Initialize the transmit descriptor ring. 2579 */ 2580 for (i = 0; i < sc->sc_ntxdesc; i++) { 2581 sipd = &sc->sc_txdescs[i]; 2582 memset(sipd, 0, sizeof(struct sip_desc)); 2583 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, sip_nexttx(sc, i))); 2584 } 2585 sip_cdtxsync(sc, 0, sc->sc_ntxdesc, 2586 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2587 sc->sc_txfree = sc->sc_ntxdesc; 2588 sc->sc_txnext = 0; 2589 sc->sc_txwin = 0; 2590 2591 /* 2592 * Initialize the transmit job descriptors. 2593 */ 2594 SIMPLEQ_INIT(&sc->sc_txfreeq); 2595 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2596 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2597 txs = &sc->sc_txsoft[i]; 2598 txs->txs_mbuf = NULL; 2599 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2600 } 2601 2602 /* 2603 * Initialize the receive descriptor and receive job 2604 * descriptor rings. 2605 */ 2606 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2607 rxs = &sc->sc_rxsoft[i]; 2608 if (rxs->rxs_mbuf == NULL) { 2609 if ((error = sipcom_add_rxbuf(sc, i)) != 0) { 2610 printf("%s: unable to allocate or map rx " 2611 "buffer %d, error = %d\n", 2612 device_xname(sc->sc_dev), i, error); 2613 /* 2614 * XXX Should attempt to run with fewer receive 2615 * XXX buffers instead of just failing. 2616 */ 2617 sipcom_rxdrain(sc); 2618 goto out; 2619 } 2620 } else 2621 sip_init_rxdesc(sc, i); 2622 } 2623 sc->sc_rxptr = 0; 2624 sc->sc_rxdiscard = 0; 2625 sip_rxchain_reset(sc); 2626 2627 /* 2628 * Set the configuration register; it's already initialized 2629 * in sip_attach(). 2630 */ 2631 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2632 2633 /* 2634 * Initialize the prototype TXCFG register. 2635 */ 2636 if (sc->sc_gigabit) { 2637 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2638 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2639 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2640 SIP_SIS900_REV(sc, SIS_REV_960) || 2641 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2642 (sc->sc_cfg & CFG_EDBMASTEN)) { 2643 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_64; 2644 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_64; 2645 } else { 2646 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2647 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2648 } 2649 2650 sc->sc_txcfg |= TXCFG_ATP | 2651 __SHIFTIN(sc->sc_tx_fill_thresh, sc->sc_bits.b_txcfg_flth_mask) | 2652 sc->sc_tx_drain_thresh; 2653 bus_space_write_4(st, sh, sc->sc_regs.r_txcfg, sc->sc_txcfg); 2654 2655 /* 2656 * Initialize the receive drain threshold if we have never 2657 * done so. 2658 */ 2659 if (sc->sc_rx_drain_thresh == 0) { 2660 /* 2661 * XXX This value should be tuned. This is set to the 2662 * maximum of 248 bytes, and we may be able to improve 2663 * performance by decreasing it (although we should never 2664 * set this value lower than 2; 14 bytes are required to 2665 * filter the packet). 2666 */ 2667 sc->sc_rx_drain_thresh = __SHIFTOUT_MASK(RXCFG_DRTH_MASK); 2668 } 2669 2670 /* 2671 * Initialize the prototype RXCFG register. 2672 */ 2673 sc->sc_rxcfg |= __SHIFTIN(sc->sc_rx_drain_thresh, RXCFG_DRTH_MASK); 2674 /* 2675 * Accept long packets (including FCS) so we can handle 2676 * 802.1q-tagged frames and jumbo frames properly. 2677 */ 2678 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2679 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2680 sc->sc_rxcfg |= RXCFG_ALP; 2681 2682 /* 2683 * Checksum offloading is disabled if the user selects an MTU 2684 * larger than 8109. (FreeBSD says 8152, but there is emperical 2685 * evidence that >8109 does not work on some boards, such as the 2686 * Planex GN-1000TE). 2687 */ 2688 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2689 (ifp->if_capenable & 2690 (IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2691 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2692 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx))) { 2693 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2694 "disabled.\n", device_xname(sc->sc_dev)); 2695 ifp->if_capenable &= 2696 ~(IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2697 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2698 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx); 2699 ifp->if_csum_flags_tx = 0; 2700 ifp->if_csum_flags_rx = 0; 2701 } 2702 2703 bus_space_write_4(st, sh, sc->sc_regs.r_rxcfg, sc->sc_rxcfg); 2704 2705 if (sc->sc_gigabit) 2706 sipcom_dp83820_init(sc, ifp->if_capenable); 2707 2708 /* 2709 * Give the transmit and receive rings to the chip. 2710 */ 2711 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2712 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2713 2714 /* 2715 * Initialize the interrupt mask. 2716 */ 2717 sc->sc_imr = sc->sc_bits.b_isr_dperr | 2718 sc->sc_bits.b_isr_sserr | 2719 sc->sc_bits.b_isr_rmabt | 2720 sc->sc_bits.b_isr_rtabt | 2721 ISR_RXSOVR | ISR_TXURN | ISR_TXDESC | ISR_TXIDLE | ISR_RXORN | 2722 ISR_RXIDLE | ISR_RXDESC; 2723 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2724 2725 /* Set up the receive filter. */ 2726 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2727 2728 /* 2729 * Tune sc_rx_flow_thresh. 2730 * XXX "More than 8KB" is too short for jumbo frames. 2731 * XXX TODO: Threshold value should be user-settable. 2732 */ 2733 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2734 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2735 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2736 2737 /* 2738 * Set the current media. Do this after initializing the prototype 2739 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2740 * control. 2741 */ 2742 if ((error = ether_mediachange(ifp)) != 0) 2743 goto out; 2744 2745 /* 2746 * Set the interrupt hold-off timer to 100us. 2747 */ 2748 if (sc->sc_gigabit) 2749 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2750 2751 /* 2752 * Enable interrupts. 2753 */ 2754 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2755 2756 /* 2757 * Start the transmit and receive processes. 2758 */ 2759 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2760 2761 /* 2762 * Start the one second MII clock. 2763 */ 2764 callout_schedule(&sc->sc_tick_ch, hz); 2765 2766 /* 2767 * ...all done! 2768 */ 2769 ifp->if_flags |= IFF_RUNNING; 2770 ifp->if_flags &= ~IFF_OACTIVE; 2771 sc->sc_if_flags = ifp->if_flags; 2772 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2773 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2774 sc->sc_prev.if_capenable = ifp->if_capenable; 2775 2776 out: 2777 if (error) 2778 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 2779 return error; 2780 } 2781 2782 /* 2783 * sip_drain: 2784 * 2785 * Drain the receive queue. 2786 */ 2787 static void 2788 sipcom_rxdrain(struct sip_softc *sc) 2789 { 2790 struct sip_rxsoft *rxs; 2791 int i; 2792 2793 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2794 rxs = &sc->sc_rxsoft[i]; 2795 if (rxs->rxs_mbuf != NULL) { 2796 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2797 m_freem(rxs->rxs_mbuf); 2798 rxs->rxs_mbuf = NULL; 2799 } 2800 } 2801 } 2802 2803 /* 2804 * sip_stop: [ ifnet interface function ] 2805 * 2806 * Stop transmission on the interface. 2807 */ 2808 static void 2809 sipcom_stop(struct ifnet *ifp, int disable) 2810 { 2811 struct sip_softc *sc = ifp->if_softc; 2812 bus_space_tag_t st = sc->sc_st; 2813 bus_space_handle_t sh = sc->sc_sh; 2814 struct sip_txsoft *txs; 2815 uint32_t cmdsts = 0; /* DEBUG */ 2816 2817 /* 2818 * Stop the one second clock. 2819 */ 2820 callout_stop(&sc->sc_tick_ch); 2821 2822 /* Down the MII. */ 2823 mii_down(&sc->sc_mii); 2824 2825 if (device_is_active(sc->sc_dev)) { 2826 /* 2827 * Disable interrupts. 2828 */ 2829 bus_space_write_4(st, sh, SIP_IER, 0); 2830 2831 /* 2832 * Stop receiver and transmitter. 2833 */ 2834 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2835 } 2836 2837 /* 2838 * Release any queued transmit buffers. 2839 */ 2840 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2841 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2842 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2843 (le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])) & 2844 CMDSTS_INTR) == 0) 2845 printf("%s: sip_stop: last descriptor does not " 2846 "have INTR bit set\n", device_xname(sc->sc_dev)); 2847 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2848 #ifdef DIAGNOSTIC 2849 if (txs->txs_mbuf == NULL) { 2850 printf("%s: dirty txsoft with no mbuf chain\n", 2851 device_xname(sc->sc_dev)); 2852 panic("sip_stop"); 2853 } 2854 #endif 2855 cmdsts |= /* DEBUG */ 2856 le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 2857 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2858 m_freem(txs->txs_mbuf); 2859 txs->txs_mbuf = NULL; 2860 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2861 } 2862 2863 /* 2864 * Mark the interface down and cancel the watchdog timer. 2865 */ 2866 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2867 ifp->if_timer = 0; 2868 2869 if (disable) 2870 pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); 2871 2872 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2873 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2874 printf("%s: sip_stop: no INTR bits set in dirty tx " 2875 "descriptors\n", device_xname(sc->sc_dev)); 2876 } 2877 2878 /* 2879 * sip_read_eeprom: 2880 * 2881 * Read data from the serial EEPROM. 2882 */ 2883 static void 2884 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2885 uint16_t *data) 2886 { 2887 bus_space_tag_t st = sc->sc_st; 2888 bus_space_handle_t sh = sc->sc_sh; 2889 uint16_t reg; 2890 int i, x; 2891 2892 for (i = 0; i < wordcnt; i++) { 2893 /* Send CHIP SELECT. */ 2894 reg = EROMAR_EECS; 2895 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2896 2897 /* Shift in the READ opcode. */ 2898 for (x = 3; x > 0; x--) { 2899 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2900 reg |= EROMAR_EEDI; 2901 else 2902 reg &= ~EROMAR_EEDI; 2903 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2904 bus_space_write_4(st, sh, SIP_EROMAR, 2905 reg | EROMAR_EESK); 2906 delay(4); 2907 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2908 delay(4); 2909 } 2910 2911 /* Shift in address. */ 2912 for (x = 6; x > 0; x--) { 2913 if ((word + i) & (1 << (x - 1))) 2914 reg |= EROMAR_EEDI; 2915 else 2916 reg &= ~EROMAR_EEDI; 2917 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2918 bus_space_write_4(st, sh, SIP_EROMAR, 2919 reg | EROMAR_EESK); 2920 delay(4); 2921 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2922 delay(4); 2923 } 2924 2925 /* Shift out data. */ 2926 reg = EROMAR_EECS; 2927 data[i] = 0; 2928 for (x = 16; x > 0; x--) { 2929 bus_space_write_4(st, sh, SIP_EROMAR, 2930 reg | EROMAR_EESK); 2931 delay(4); 2932 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2933 data[i] |= (1 << (x - 1)); 2934 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2935 delay(4); 2936 } 2937 2938 /* Clear CHIP SELECT. */ 2939 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2940 delay(4); 2941 } 2942 } 2943 2944 /* 2945 * sipcom_add_rxbuf: 2946 * 2947 * Add a receive buffer to the indicated descriptor. 2948 */ 2949 static int 2950 sipcom_add_rxbuf(struct sip_softc *sc, int idx) 2951 { 2952 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2953 struct mbuf *m; 2954 int error; 2955 2956 MGETHDR(m, M_DONTWAIT, MT_DATA); 2957 if (m == NULL) 2958 return ENOBUFS; 2959 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2960 2961 MCLGET(m, M_DONTWAIT); 2962 if ((m->m_flags & M_EXT) == 0) { 2963 m_freem(m); 2964 return ENOBUFS; 2965 } 2966 2967 /* XXX I don't believe this is necessary. --dyoung */ 2968 if (sc->sc_gigabit) 2969 m->m_len = sc->sc_parm->p_rxbuf_len; 2970 2971 if (rxs->rxs_mbuf != NULL) 2972 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2973 2974 rxs->rxs_mbuf = m; 2975 2976 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2977 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2978 BUS_DMA_READ | BUS_DMA_NOWAIT); 2979 if (error) { 2980 printf("%s: can't load rx DMA map %d, error = %d\n", 2981 device_xname(sc->sc_dev), idx, error); 2982 panic("%s", __func__); /* XXX */ 2983 } 2984 2985 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2986 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2987 2988 sip_init_rxdesc(sc, idx); 2989 2990 return 0; 2991 } 2992 2993 /* 2994 * sip_sis900_set_filter: 2995 * 2996 * Set up the receive filter. 2997 */ 2998 static void 2999 sipcom_sis900_set_filter(struct sip_softc *sc) 3000 { 3001 bus_space_tag_t st = sc->sc_st; 3002 bus_space_handle_t sh = sc->sc_sh; 3003 struct ethercom *ec = &sc->sc_ethercom; 3004 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3005 struct ether_multi *enm; 3006 const uint8_t *cp; 3007 struct ether_multistep step; 3008 uint32_t crc, mchash[16]; 3009 3010 /* 3011 * Initialize the prototype RFCR. 3012 */ 3013 sc->sc_rfcr = RFCR_RFEN; 3014 if (ifp->if_flags & IFF_BROADCAST) 3015 sc->sc_rfcr |= RFCR_AAB; 3016 if (ifp->if_flags & IFF_PROMISC) { 3017 sc->sc_rfcr |= RFCR_AAP; 3018 goto allmulti; 3019 } 3020 3021 /* 3022 * Set up the multicast address filter by passing all multicast 3023 * addresses through a CRC generator, and then using the high-order 3024 * 6 bits as an index into the 128 bit multicast hash table (only 3025 * the lower 16 bits of each 32 bit multicast hash register are 3026 * valid). The high order bits select the register, while the 3027 * rest of the bits select the bit within the register. 3028 */ 3029 3030 memset(mchash, 0, sizeof(mchash)); 3031 3032 /* 3033 * SiS900 (at least SiS963) requires us to register the address of 3034 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 3035 */ 3036 crc = 0x0ed423f9; 3037 3038 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3039 SIP_SIS900_REV(sc, SIS_REV_960) || 3040 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3041 /* Just want the 8 most significant bits. */ 3042 crc >>= 24; 3043 } else { 3044 /* Just want the 7 most significant bits. */ 3045 crc >>= 25; 3046 } 3047 3048 /* Set the corresponding bit in the hash table. */ 3049 mchash[crc >> 4] |= 1 << (crc & 0xf); 3050 3051 ETHER_LOCK(ec); 3052 ETHER_FIRST_MULTI(step, ec, enm); 3053 while (enm != NULL) { 3054 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3055 /* 3056 * We must listen to a range of multicast addresses. 3057 * For now, just accept all multicasts, rather than 3058 * trying to set only those filter bits needed to match 3059 * the range. (At this time, the only use of address 3060 * ranges is for IP multicast routing, for which the 3061 * range is big enough to require all bits set.) 3062 */ 3063 ETHER_UNLOCK(ec); 3064 goto allmulti; 3065 } 3066 3067 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3068 3069 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3070 SIP_SIS900_REV(sc, SIS_REV_960) || 3071 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3072 /* Just want the 8 most significant bits. */ 3073 crc >>= 24; 3074 } else { 3075 /* Just want the 7 most significant bits. */ 3076 crc >>= 25; 3077 } 3078 3079 /* Set the corresponding bit in the hash table. */ 3080 mchash[crc >> 4] |= 1 << (crc & 0xf); 3081 3082 ETHER_NEXT_MULTI(step, enm); 3083 } 3084 ETHER_UNLOCK(ec); 3085 3086 ifp->if_flags &= ~IFF_ALLMULTI; 3087 goto setit; 3088 3089 allmulti: 3090 ifp->if_flags |= IFF_ALLMULTI; 3091 sc->sc_rfcr |= RFCR_AAM; 3092 3093 setit: 3094 #define FILTER_EMIT(addr, data) \ 3095 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3096 delay(1); \ 3097 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3098 delay(1) 3099 3100 /* 3101 * Disable receive filter, and program the node address. 3102 */ 3103 cp = CLLADDR(ifp->if_sadl); 3104 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 3105 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 3106 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 3107 3108 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3109 /* 3110 * Program the multicast hash table. 3111 */ 3112 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 3113 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 3114 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 3115 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 3116 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 3117 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 3118 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 3119 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 3120 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3121 SIP_SIS900_REV(sc, SIS_REV_960) || 3122 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3123 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 3124 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 3125 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 3126 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 3127 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 3128 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 3129 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 3130 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 3131 } 3132 } 3133 #undef FILTER_EMIT 3134 3135 /* 3136 * Re-enable the receiver filter. 3137 */ 3138 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3139 } 3140 3141 /* 3142 * sip_dp83815_set_filter: 3143 * 3144 * Set up the receive filter. 3145 */ 3146 static void 3147 sipcom_dp83815_set_filter(struct sip_softc *sc) 3148 { 3149 bus_space_tag_t st = sc->sc_st; 3150 bus_space_handle_t sh = sc->sc_sh; 3151 struct ethercom *ec = &sc->sc_ethercom; 3152 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3153 struct ether_multi *enm; 3154 const uint8_t *cp; 3155 struct ether_multistep step; 3156 uint32_t crc, hash, slot, bit; 3157 #define MCHASH_NWORDS_83820 128 3158 #define MCHASH_NWORDS_83815 32 3159 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3160 uint16_t mchash[MCHASH_NWORDS]; 3161 int i; 3162 3163 /* 3164 * Initialize the prototype RFCR. 3165 * Enable the receive filter, and accept on 3166 * Perfect (destination address) Match 3167 * If IFF_BROADCAST, also accept all broadcast packets. 3168 * If IFF_PROMISC, accept all unicast packets (and later, set 3169 * IFF_ALLMULTI and accept all multicast, too). 3170 */ 3171 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3172 if (ifp->if_flags & IFF_BROADCAST) 3173 sc->sc_rfcr |= RFCR_AAB; 3174 if (ifp->if_flags & IFF_PROMISC) { 3175 sc->sc_rfcr |= RFCR_AAP; 3176 goto allmulti; 3177 } 3178 3179 /* 3180 * Set up the DP83820/DP83815 multicast address filter by 3181 * passing all multicast addresses through a CRC generator, 3182 * and then using the high-order 11/9 bits as an index into 3183 * the 2048/512 bit multicast hash table. The high-order 3184 * 7/5 bits select the slot, while the low-order 4 bits 3185 * select the bit within the slot. Note that only the low 3186 * 16-bits of each filter word are used, and there are 3187 * 128/32 filter words. 3188 */ 3189 3190 memset(mchash, 0, sizeof(mchash)); 3191 3192 ifp->if_flags &= ~IFF_ALLMULTI; 3193 ETHER_FIRST_MULTI(step, ec, enm); 3194 if (enm == NULL) 3195 goto setit; 3196 while (enm != NULL) { 3197 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3198 /* 3199 * We must listen to a range of multicast addresses. 3200 * For now, just accept all multicasts, rather than 3201 * trying to set only those filter bits needed to match 3202 * the range. (At this time, the only use of address 3203 * ranges is for IP multicast routing, for which the 3204 * range is big enough to require all bits set.) 3205 */ 3206 goto allmulti; 3207 } 3208 3209 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3210 3211 if (sc->sc_gigabit) { 3212 /* Just want the 11 most significant bits. */ 3213 hash = crc >> 21; 3214 } else { 3215 /* Just want the 9 most significant bits. */ 3216 hash = crc >> 23; 3217 } 3218 3219 slot = hash >> 4; 3220 bit = hash & 0xf; 3221 3222 /* Set the corresponding bit in the hash table. */ 3223 mchash[slot] |= 1 << bit; 3224 3225 ETHER_NEXT_MULTI(step, enm); 3226 } 3227 sc->sc_rfcr |= RFCR_MHEN; 3228 goto setit; 3229 3230 allmulti: 3231 ifp->if_flags |= IFF_ALLMULTI; 3232 sc->sc_rfcr |= RFCR_AAM; 3233 3234 setit: 3235 #define FILTER_EMIT(addr, data) \ 3236 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3237 delay(1); \ 3238 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3239 delay(1) 3240 3241 /* 3242 * Disable receive filter, and program the node address. 3243 */ 3244 cp = CLLADDR(ifp->if_sadl); 3245 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3246 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3247 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3248 3249 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3250 int nwords = 3251 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3252 /* 3253 * Program the multicast hash table. 3254 */ 3255 for (i = 0; i < nwords; i++) { 3256 FILTER_EMIT(sc->sc_parm->p_filtmem + (i * 2), mchash[i]); 3257 } 3258 } 3259 #undef FILTER_EMIT 3260 #undef MCHASH_NWORDS 3261 #undef MCHASH_NWORDS_83815 3262 #undef MCHASH_NWORDS_83820 3263 3264 /* 3265 * Re-enable the receiver filter. 3266 */ 3267 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3268 } 3269 3270 /* 3271 * sip_dp83820_mii_readreg: [mii interface function] 3272 * 3273 * Read a PHY register on the MII of the DP83820. 3274 */ 3275 static int 3276 sipcom_dp83820_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3277 { 3278 struct sip_softc *sc = device_private(self); 3279 3280 if (sc->sc_cfg & CFG_TBI_EN) { 3281 bus_addr_t tbireg; 3282 3283 if (phy != 0) 3284 return -1; 3285 3286 switch (reg) { 3287 case MII_BMCR: tbireg = SIP_TBICR; break; 3288 case MII_BMSR: tbireg = SIP_TBISR; break; 3289 case MII_ANAR: tbireg = SIP_TANAR; break; 3290 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3291 case MII_ANER: tbireg = SIP_TANER; break; 3292 case MII_EXTSR: 3293 /* 3294 * Don't even bother reading the TESR register. 3295 * The manual documents that the device has 3296 * 1000baseX full/half capability, but the 3297 * register itself seems read back 0 on some 3298 * boards. Just hard-code the result. 3299 */ 3300 *val = (EXTSR_1000XFDX | EXTSR_1000XHDX); 3301 return 0; 3302 3303 default: 3304 return 0; 3305 } 3306 3307 *val = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3308 if (tbireg == SIP_TBISR) { 3309 /* LINK and ACOMP are switched! */ 3310 int sr = *val; 3311 3312 *val = 0; 3313 if (sr & TBISR_MR_LINK_STATUS) 3314 *val |= BMSR_LINK; 3315 if (sr & TBISR_MR_AN_COMPLETE) 3316 *val |= BMSR_ACOMP; 3317 3318 /* 3319 * The manual claims this register reads back 0 3320 * on hard and soft reset. But we want to let 3321 * the gentbi driver know that we support auto- 3322 * negotiation, so hard-code this bit in the 3323 * result. 3324 */ 3325 *val |= BMSR_ANEG | BMSR_EXTSTAT; 3326 } 3327 3328 return 0; 3329 } 3330 3331 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg, 3332 val); 3333 } 3334 3335 /* 3336 * sip_dp83820_mii_writereg: [mii interface function] 3337 * 3338 * Write a PHY register on the MII of the DP83820. 3339 */ 3340 static int 3341 sipcom_dp83820_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3342 { 3343 struct sip_softc *sc = device_private(self); 3344 3345 if (sc->sc_cfg & CFG_TBI_EN) { 3346 bus_addr_t tbireg; 3347 3348 if (phy != 0) 3349 return -1; 3350 3351 switch (reg) { 3352 case MII_BMCR: tbireg = SIP_TBICR; break; 3353 case MII_ANAR: tbireg = SIP_TANAR; break; 3354 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3355 default: 3356 return 0; 3357 } 3358 3359 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3360 return 0; 3361 } 3362 3363 return mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, 3364 val); 3365 } 3366 3367 /* 3368 * sip_dp83820_mii_statchg: [mii interface function] 3369 * 3370 * Callback from MII layer when media changes. 3371 */ 3372 static void 3373 sipcom_dp83820_mii_statchg(struct ifnet *ifp) 3374 { 3375 struct sip_softc *sc = ifp->if_softc; 3376 struct mii_data *mii = &sc->sc_mii; 3377 uint32_t cfg, pcr; 3378 3379 /* 3380 * Get flow control negotiation result. 3381 */ 3382 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3383 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3384 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3385 mii->mii_media_active &= ~IFM_ETH_FMASK; 3386 } 3387 3388 /* 3389 * Update TXCFG for full-duplex operation. 3390 */ 3391 if ((mii->mii_media_active & IFM_FDX) != 0) 3392 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3393 else 3394 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3395 3396 /* 3397 * Update RXCFG for full-duplex or loopback. 3398 */ 3399 if ((mii->mii_media_active & IFM_FDX) != 0 || 3400 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3401 sc->sc_rxcfg |= RXCFG_ATX; 3402 else 3403 sc->sc_rxcfg &= ~RXCFG_ATX; 3404 3405 /* 3406 * Update CFG for MII/GMII. 3407 */ 3408 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3409 cfg = sc->sc_cfg | CFG_MODE_1000; 3410 else 3411 cfg = sc->sc_cfg; 3412 3413 /* 3414 * 802.3x flow control. 3415 */ 3416 pcr = 0; 3417 if (sc->sc_flowflags & IFM_FLOW) { 3418 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3419 pcr |= sc->sc_rx_flow_thresh; 3420 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3421 pcr |= PCR_PSEN | PCR_PS_MCAST; 3422 } 3423 3424 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3425 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3426 sc->sc_txcfg); 3427 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3428 sc->sc_rxcfg); 3429 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3430 } 3431 3432 /* 3433 * sip_mii_bitbang_read: [mii bit-bang interface function] 3434 * 3435 * Read the MII serial port for the MII bit-bang module. 3436 */ 3437 static uint32_t 3438 sipcom_mii_bitbang_read(device_t self) 3439 { 3440 struct sip_softc *sc = device_private(self); 3441 3442 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3443 } 3444 3445 /* 3446 * sip_mii_bitbang_write: [mii big-bang interface function] 3447 * 3448 * Write the MII serial port for the MII bit-bang module. 3449 */ 3450 static void 3451 sipcom_mii_bitbang_write(device_t self, uint32_t val) 3452 { 3453 struct sip_softc *sc = device_private(self); 3454 3455 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3456 } 3457 3458 /* 3459 * sip_sis900_mii_readreg: [mii interface function] 3460 * 3461 * Read a PHY register on the MII. 3462 */ 3463 static int 3464 sipcom_sis900_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3465 { 3466 struct sip_softc *sc = device_private(self); 3467 uint32_t enphy; 3468 3469 /* 3470 * The PHY of recent SiS chipsets is accessed through bitbang 3471 * operations. 3472 */ 3473 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3474 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3475 phy, reg, val); 3476 3477 #ifndef SIS900_MII_RESTRICT 3478 /* 3479 * The SiS 900 has only an internal PHY on the MII. Only allow 3480 * MII address 0. 3481 */ 3482 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3483 return -1; 3484 #endif 3485 3486 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3487 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3488 ENPHY_RWCMD | ENPHY_ACCESS); 3489 do { 3490 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3491 } while (enphy & ENPHY_ACCESS); 3492 3493 *val = (enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT; 3494 return 0; 3495 } 3496 3497 /* 3498 * sip_sis900_mii_writereg: [mii interface function] 3499 * 3500 * Write a PHY register on the MII. 3501 */ 3502 static int 3503 sipcom_sis900_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3504 { 3505 struct sip_softc *sc = device_private(self); 3506 uint32_t enphy; 3507 3508 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3509 return mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3510 phy, reg, val); 3511 } 3512 3513 #ifndef SIS900_MII_RESTRICT 3514 /* 3515 * The SiS 900 has only an internal PHY on the MII. Only allow 3516 * MII address 0. 3517 */ 3518 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3519 return -1; 3520 #endif 3521 3522 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3523 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3524 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3525 do { 3526 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3527 } while (enphy & ENPHY_ACCESS); 3528 3529 return 0; 3530 } 3531 3532 /* 3533 * sip_sis900_mii_statchg: [mii interface function] 3534 * 3535 * Callback from MII layer when media changes. 3536 */ 3537 static void 3538 sipcom_sis900_mii_statchg(struct ifnet *ifp) 3539 { 3540 struct sip_softc *sc = ifp->if_softc; 3541 struct mii_data *mii = &sc->sc_mii; 3542 uint32_t flowctl; 3543 3544 /* 3545 * Get flow control negotiation result. 3546 */ 3547 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3548 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3549 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3550 mii->mii_media_active &= ~IFM_ETH_FMASK; 3551 } 3552 3553 /* 3554 * Update TXCFG for full-duplex operation. 3555 */ 3556 if ((mii->mii_media_active & IFM_FDX) != 0) 3557 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3558 else 3559 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3560 3561 /* 3562 * Update RXCFG for full-duplex or loopback. 3563 */ 3564 if ((mii->mii_media_active & IFM_FDX) != 0 || 3565 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3566 sc->sc_rxcfg |= RXCFG_ATX; 3567 else 3568 sc->sc_rxcfg &= ~RXCFG_ATX; 3569 3570 /* 3571 * Update IMR for use of 802.3x flow control. 3572 */ 3573 if (sc->sc_flowflags & IFM_FLOW) { 3574 sc->sc_imr |= (ISR_PAUSE_END | ISR_PAUSE_ST); 3575 flowctl = FLOWCTL_FLOWEN; 3576 } else { 3577 sc->sc_imr &= ~(ISR_PAUSE_END | ISR_PAUSE_ST); 3578 flowctl = 0; 3579 } 3580 3581 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3582 sc->sc_txcfg); 3583 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3584 sc->sc_rxcfg); 3585 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3586 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3587 } 3588 3589 /* 3590 * sip_dp83815_mii_readreg: [mii interface function] 3591 * 3592 * Read a PHY register on the MII. 3593 */ 3594 static int 3595 sipcom_dp83815_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3596 { 3597 struct sip_softc *sc = device_private(self); 3598 uint32_t data; 3599 3600 /* 3601 * The DP83815 only has an internal PHY. Only allow 3602 * MII address 0. 3603 */ 3604 if (phy != 0) 3605 return -1; 3606 3607 /* 3608 * Apparently, after a reset, the DP83815 can take a while 3609 * to respond. During this recovery period, the BMSR returns 3610 * a value of 0. Catch this -- it's not supposed to happen 3611 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3612 * PHY to come back to life. 3613 * 3614 * This works out because the BMSR is the first register 3615 * read during the PHY probe process. 3616 */ 3617 do { 3618 data = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3619 } while (reg == MII_BMSR && data == 0); 3620 3621 *val = data & 0xffff; 3622 return 0; 3623 } 3624 3625 /* 3626 * sip_dp83815_mii_writereg: [mii interface function] 3627 * 3628 * Write a PHY register to the MII. 3629 */ 3630 static int 3631 sipcom_dp83815_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3632 { 3633 struct sip_softc *sc = device_private(self); 3634 3635 /* 3636 * The DP83815 only has an internal PHY. Only allow 3637 * MII address 0. 3638 */ 3639 if (phy != 0) 3640 return -1; 3641 3642 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3643 3644 return 0; 3645 } 3646 3647 /* 3648 * sip_dp83815_mii_statchg: [mii interface function] 3649 * 3650 * Callback from MII layer when media changes. 3651 */ 3652 static void 3653 sipcom_dp83815_mii_statchg(struct ifnet *ifp) 3654 { 3655 struct sip_softc *sc = ifp->if_softc; 3656 3657 /* 3658 * Update TXCFG for full-duplex operation. 3659 */ 3660 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3661 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3662 else 3663 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3664 3665 /* 3666 * Update RXCFG for full-duplex or loopback. 3667 */ 3668 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3669 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3670 sc->sc_rxcfg |= RXCFG_ATX; 3671 else 3672 sc->sc_rxcfg &= ~RXCFG_ATX; 3673 3674 /* 3675 * XXX 802.3x flow control. 3676 */ 3677 3678 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3679 sc->sc_txcfg); 3680 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3681 sc->sc_rxcfg); 3682 3683 /* 3684 * Some DP83815s experience problems when used with short 3685 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3686 * sequence adjusts the DSP's signal attenuation to fix the 3687 * problem. 3688 */ 3689 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3690 uint32_t reg; 3691 3692 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3693 3694 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3695 reg &= 0x0fff; 3696 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3697 delay(100); 3698 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3699 reg &= 0x00ff; 3700 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3701 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3702 0x00e8); 3703 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3704 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3705 reg | 0x20); 3706 } 3707 3708 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3709 } 3710 } 3711 3712 static void 3713 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3714 const struct pci_attach_args *pa, uint8_t *enaddr) 3715 { 3716 uint16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3717 uint8_t cksum, *e, match; 3718 int i; 3719 3720 /* 3721 * EEPROM data format for the DP83820 can be found in 3722 * the DP83820 manual, section 4.2.4. 3723 */ 3724 3725 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3726 3727 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3728 match = ~(match - 1); 3729 3730 cksum = 0x55; 3731 e = (uint8_t *)eeprom_data; 3732 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3733 cksum += *e++; 3734 3735 if (cksum != match) 3736 printf("%s: Checksum (%x) mismatch (%x)", 3737 device_xname(sc->sc_dev), cksum, match); 3738 3739 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3740 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3741 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3742 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3743 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3744 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3745 } 3746 3747 static void 3748 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3749 { 3750 int i; 3751 3752 /* 3753 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3754 * a reason, but I don't know it. 3755 */ 3756 for (i = 0; i < 10; i++) 3757 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3758 } 3759 3760 static void 3761 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3762 const struct pci_attach_args *pa, uint8_t *enaddr) 3763 { 3764 uint16_t myea[ETHER_ADDR_LEN / 2]; 3765 3766 switch (sc->sc_rev) { 3767 case SIS_REV_630S: 3768 case SIS_REV_630E: 3769 case SIS_REV_630EA1: 3770 case SIS_REV_630ET: 3771 case SIS_REV_635: 3772 /* 3773 * The MAC address for the on-board Ethernet of 3774 * the SiS 630 chipset is in the NVRAM. Kick 3775 * the chip into re-loading it from NVRAM, and 3776 * read the MAC address out of the filter registers. 3777 */ 3778 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3779 3780 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3781 RFCR_RFADDR_NODE0); 3782 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3783 0xffff; 3784 3785 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3786 RFCR_RFADDR_NODE2); 3787 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3788 0xffff; 3789 3790 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3791 RFCR_RFADDR_NODE4); 3792 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3793 0xffff; 3794 break; 3795 3796 case SIS_REV_960: 3797 { 3798 #define SIS_SET_EROMAR(x, y) \ 3799 bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3800 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3801 3802 #define SIS_CLR_EROMAR(x, y) \ 3803 bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3804 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3805 3806 int waittime, i; 3807 3808 /* Allow to read EEPROM from LAN. It is shared 3809 * between a 1394 controller and the NIC and each 3810 * time we access it, we need to set SIS_EECMD_REQ. 3811 */ 3812 SIS_SET_EROMAR(sc, EROMAR_REQ); 3813 3814 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3815 /* Force EEPROM to idle state. */ 3816 3817 /* 3818 * XXX-cube This is ugly. 3819 * I'll look for docs about it. 3820 */ 3821 SIS_SET_EROMAR(sc, EROMAR_EECS); 3822 sipcom_sis900_eeprom_delay(sc); 3823 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3824 SIS_SET_EROMAR(sc, EROMAR_EESK); 3825 sipcom_sis900_eeprom_delay(sc); 3826 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3827 sipcom_sis900_eeprom_delay(sc); 3828 } 3829 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3830 sipcom_sis900_eeprom_delay(sc); 3831 bus_space_write_4(sc->sc_st, sc->sc_sh, 3832 SIP_EROMAR, 0); 3833 3834 if (bus_space_read_4(sc->sc_st, sc->sc_sh, 3835 SIP_EROMAR) & EROMAR_GNT) { 3836 sipcom_read_eeprom(sc, 3837 SIP_EEPROM_ETHERNET_ID0 >> 1, 3838 sizeof(myea) / sizeof(myea[0]), 3839 myea); 3840 break; 3841 } 3842 DELAY(1); 3843 } 3844 3845 /* 3846 * Set SIS_EECTL_CLK to high, so a other master 3847 * can operate on the i2c bus. 3848 */ 3849 SIS_SET_EROMAR(sc, EROMAR_EESK); 3850 3851 /* Refuse EEPROM access by LAN */ 3852 SIS_SET_EROMAR(sc, EROMAR_DONE); 3853 } break; 3854 3855 default: 3856 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3857 sizeof(myea) / sizeof(myea[0]), myea); 3858 } 3859 3860 enaddr[0] = myea[0] & 0xff; 3861 enaddr[1] = myea[0] >> 8; 3862 enaddr[2] = myea[1] & 0xff; 3863 enaddr[3] = myea[1] >> 8; 3864 enaddr[4] = myea[2] & 0xff; 3865 enaddr[5] = myea[2] >> 8; 3866 } 3867 3868 /* Table and macro to bit-reverse an octet. */ 3869 static const uint8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3870 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3871 3872 static void 3873 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3874 const struct pci_attach_args *pa, uint8_t *enaddr) 3875 { 3876 uint16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3877 uint8_t cksum, *e, match; 3878 int i; 3879 3880 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3881 sizeof(eeprom_data[0]), eeprom_data); 3882 3883 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3884 match = ~(match - 1); 3885 3886 cksum = 0x55; 3887 e = (uint8_t *)eeprom_data; 3888 for (i = 0; i < SIP_DP83815_EEPROM_CHECKSUM; i++) 3889 cksum += *e++; 3890 3891 if (cksum != match) 3892 printf("%s: Checksum (%x) mismatch (%x)", 3893 device_xname(sc->sc_dev), cksum, match); 3894 3895 /* 3896 * Unrolled because it makes slightly more sense this way. 3897 * The DP83815 stores the MAC address in bit 0 of word 6 3898 * through bit 15 of word 8. 3899 */ 3900 ea = &eeprom_data[6]; 3901 enaddr[0] = ((*ea & 0x1) << 7); 3902 ea++; 3903 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3904 enaddr[1] = ((*ea & 0x1FE) >> 1); 3905 enaddr[2] = ((*ea & 0x1) << 7); 3906 ea++; 3907 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3908 enaddr[3] = ((*ea & 0x1FE) >> 1); 3909 enaddr[4] = ((*ea & 0x1) << 7); 3910 ea++; 3911 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3912 enaddr[5] = ((*ea & 0x1FE) >> 1); 3913 3914 /* 3915 * In case that's not weird enough, we also need to reverse 3916 * the bits in each byte. This all actually makes more sense 3917 * if you think about the EEPROM storage as an array of bits 3918 * being shifted into bytes, but that's not how we're looking 3919 * at it here... 3920 */ 3921 for (i = 0; i < 6 ;i++) 3922 enaddr[i] = bbr(enaddr[i]); 3923 } 3924 3925 /* 3926 * sip_mediastatus: [ifmedia interface function] 3927 * 3928 * Get the current interface media status. 3929 */ 3930 static void 3931 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3932 { 3933 struct sip_softc *sc = ifp->if_softc; 3934 3935 if (!device_is_active(sc->sc_dev)) { 3936 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 3937 ifmr->ifm_status = 0; 3938 return; 3939 } 3940 ether_mediastatus(ifp, ifmr); 3941 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) | 3942 sc->sc_flowflags; 3943 } 3944
Indexes created Sun Sep 21 20:09:37 GMT 2025