if_sip.c revision 1.181
1 /* $NetBSD: if_sip.c,v 1.181 2020/03/15 22:20:31 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999 Network Computer, Inc. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of Network Computer, Inc. nor the names of its 45 * contributors may be used to endorse or promote products derived 46 * from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * Device driver for the Silicon Integrated Systems SiS 900, 63 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 64 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 65 * controllers. 66 * 67 * Originally written to support the SiS 900 by Jason R. Thorpe for 68 * Network Computer, Inc. 69 * 70 * TODO: 71 * 72 * - Reduce the Rx interrupt load. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.181 2020/03/15 22:20:31 thorpej Exp $"); 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/callout.h> 81 #include <sys/mbuf.h> 82 #include <sys/malloc.h> 83 #include <sys/kernel.h> 84 #include <sys/socket.h> 85 #include <sys/ioctl.h> 86 #include <sys/errno.h> 87 #include <sys/device.h> 88 #include <sys/queue.h> 89 #include <sys/rndsource.h> 90 91 #include <net/if.h> 92 #include <net/if_dl.h> 93 #include <net/if_media.h> 94 #include <net/if_ether.h> 95 #include <net/bpf.h> 96 97 #include <sys/bus.h> 98 #include <sys/intr.h> 99 #include <machine/endian.h> 100 101 #include <dev/mii/mii.h> 102 #include <dev/mii/miivar.h> 103 #include <dev/mii/mii_bitbang.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 109 #include <dev/pci/if_sipreg.h> 110 111 /* 112 * Transmit descriptor list size. This is arbitrary, but allocate 113 * enough descriptors for 128 pending transmissions, and 8 segments 114 * per packet (64 for DP83820 for jumbo frames). 115 * 116 * This MUST work out to a power of 2. 117 */ 118 #define GSIP_NTXSEGS_ALLOC 16 119 #define SIP_NTXSEGS_ALLOC 8 120 121 #define SIP_TXQUEUELEN 256 122 #define MAX_SIP_NTXDESC \ 123 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 124 125 /* 126 * Receive descriptor list size. We have one Rx buffer per incoming 127 * packet, so this logic is a little simpler. 128 * 129 * Actually, on the DP83820, we allow the packet to consume more than 130 * one buffer, in order to support jumbo Ethernet frames. In that 131 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 132 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 133 * so we'd better be quick about handling receive interrupts. 134 */ 135 #define GSIP_NRXDESC 256 136 #define SIP_NRXDESC 128 137 138 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 139 140 /* 141 * Set this to 1 to force-disable using the 64-bit data path 142 * on DP83820. 143 */ 144 static int gsip_disable_data64 = 0; 145 146 /* 147 * Control structures are DMA'd to the SiS900 chip. We allocate them in 148 * a single clump that maps to a single DMA segment to make several things 149 * easier. 150 */ 151 struct sip_control_data { 152 /* 153 * The transmit descriptors. 154 */ 155 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 156 157 /* 158 * The receive descriptors. 159 */ 160 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 161 }; 162 163 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 164 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 165 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 166 167 /* 168 * Software state for transmit jobs. 169 */ 170 struct sip_txsoft { 171 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 172 bus_dmamap_t txs_dmamap; /* our DMA map */ 173 int txs_firstdesc; /* first descriptor in packet */ 174 int txs_lastdesc; /* last descriptor in packet */ 175 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 176 }; 177 178 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 179 180 /* 181 * Software state for receive jobs. 182 */ 183 struct sip_rxsoft { 184 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 185 bus_dmamap_t rxs_dmamap; /* our DMA map */ 186 }; 187 188 enum sip_attach_stage { 189 SIP_ATTACH_FIN = 0 190 , SIP_ATTACH_CREATE_RXMAP 191 , SIP_ATTACH_CREATE_TXMAP 192 , SIP_ATTACH_LOAD_MAP 193 , SIP_ATTACH_CREATE_MAP 194 , SIP_ATTACH_MAP_MEM 195 , SIP_ATTACH_ALLOC_MEM 196 , SIP_ATTACH_INTR 197 , SIP_ATTACH_MAP 198 }; 199 200 /* 201 * Software state per device. 202 */ 203 struct sip_softc { 204 device_t sc_dev; /* generic device information */ 205 device_suspensor_t sc_suspensor; 206 pmf_qual_t sc_qual; 207 208 bus_space_tag_t sc_st; /* bus space tag */ 209 bus_space_handle_t sc_sh; /* bus space handle */ 210 bus_size_t sc_sz; /* bus space size */ 211 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 212 pci_chipset_tag_t sc_pc; 213 bus_dma_segment_t sc_seg; 214 struct ethercom sc_ethercom; /* ethernet common data */ 215 216 const struct sip_product *sc_model; /* which model are we? */ 217 bool sc_gigabit; /* 1: 83820, 0: other */ 218 bool sc_dma64; /* using 64-bit DMA addresses */ 219 int sc_rev; /* chip revision */ 220 221 unsigned int sc_bufptr_idx; 222 unsigned int sc_cmdsts_idx; 223 unsigned int sc_extsts_idx; /* DP83820 only */ 224 225 void *sc_ih; /* interrupt cookie */ 226 227 struct mii_data sc_mii; /* MII/media information */ 228 229 callout_t sc_tick_ch; /* tick callout */ 230 231 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 232 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 233 234 /* 235 * Software state for transmit and receive descriptors. 236 */ 237 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 238 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 239 240 /* 241 * Control data structures. 242 */ 243 struct sip_control_data *sc_control_data; 244 #define sc_txdescs sc_control_data->scd_txdescs 245 #define sc_rxdescs sc_control_data->scd_rxdescs 246 247 #ifdef SIP_EVENT_COUNTERS 248 /* 249 * Event counters. 250 */ 251 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 252 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 253 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 254 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 255 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 256 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 257 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 258 struct evcnt sc_ev_rxpause; /* PAUSE received */ 259 /* DP83820 only */ 260 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 261 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 262 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 263 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 264 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 265 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 266 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 267 #endif /* SIP_EVENT_COUNTERS */ 268 269 uint32_t sc_txcfg; /* prototype TXCFG register */ 270 uint32_t sc_rxcfg; /* prototype RXCFG register */ 271 uint32_t sc_imr; /* prototype IMR register */ 272 uint32_t sc_rfcr; /* prototype RFCR register */ 273 274 uint32_t sc_cfg; /* prototype CFG register */ 275 276 uint32_t sc_gpior; /* prototype GPIOR register */ 277 278 uint32_t sc_tx_fill_thresh; /* transmit fill threshold */ 279 uint32_t sc_tx_drain_thresh; /* transmit drain threshold */ 280 281 uint32_t sc_rx_drain_thresh; /* receive drain threshold */ 282 283 int sc_flowflags; /* 802.3x flow control flags */ 284 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 285 int sc_paused; /* paused indication */ 286 287 int sc_txfree; /* number of free Tx descriptors */ 288 int sc_txnext; /* next ready Tx descriptor */ 289 int sc_txwin; /* Tx descriptors since last intr */ 290 291 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 292 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 293 294 /* values of interface state at last init */ 295 struct { 296 /* if_capenable */ 297 uint64_t if_capenable; 298 /* ec_capenable */ 299 int ec_capenable; 300 /* VLAN_ATTACHED */ 301 int is_vlan; 302 } sc_prev; 303 304 u_short sc_if_flags; 305 306 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 307 int sc_rxdiscard; 308 int sc_rxlen; 309 struct mbuf *sc_rxhead; 310 struct mbuf *sc_rxtail; 311 struct mbuf **sc_rxtailp; 312 313 int sc_ntxdesc; 314 int sc_ntxdesc_mask; 315 316 int sc_nrxdesc_mask; 317 318 const struct sip_parm { 319 const struct sip_regs { 320 int r_rxcfg; 321 int r_txcfg; 322 } p_regs; 323 324 const struct sip_bits { 325 uint32_t b_txcfg_mxdma_8; 326 uint32_t b_txcfg_mxdma_16; 327 uint32_t b_txcfg_mxdma_32; 328 uint32_t b_txcfg_mxdma_64; 329 uint32_t b_txcfg_mxdma_128; 330 uint32_t b_txcfg_mxdma_256; 331 uint32_t b_txcfg_mxdma_512; 332 uint32_t b_txcfg_flth_mask; 333 uint32_t b_txcfg_drth_mask; 334 335 uint32_t b_rxcfg_mxdma_8; 336 uint32_t b_rxcfg_mxdma_16; 337 uint32_t b_rxcfg_mxdma_32; 338 uint32_t b_rxcfg_mxdma_64; 339 uint32_t b_rxcfg_mxdma_128; 340 uint32_t b_rxcfg_mxdma_256; 341 uint32_t b_rxcfg_mxdma_512; 342 343 uint32_t b_isr_txrcmp; 344 uint32_t b_isr_rxrcmp; 345 uint32_t b_isr_dperr; 346 uint32_t b_isr_sserr; 347 uint32_t b_isr_rmabt; 348 uint32_t b_isr_rtabt; 349 350 uint32_t b_cmdsts_size_mask; 351 } p_bits; 352 int p_filtmem; 353 int p_rxbuf_len; 354 bus_size_t p_tx_dmamap_size; 355 int p_ntxsegs; 356 int p_ntxsegs_alloc; 357 int p_nrxdesc; 358 } *sc_parm; 359 360 void (*sc_rxintr)(struct sip_softc *); 361 362 krndsource_t rnd_source; /* random source */ 363 }; 364 365 #define sc_bits sc_parm->p_bits 366 #define sc_regs sc_parm->p_regs 367 368 static const struct sip_parm sip_parm = { 369 .p_filtmem = OTHER_RFCR_NS_RFADDR_FILTMEM 370 , .p_rxbuf_len = MCLBYTES - 1 /* field width */ 371 , .p_tx_dmamap_size = MCLBYTES 372 , .p_ntxsegs = 16 373 , .p_ntxsegs_alloc = SIP_NTXSEGS_ALLOC 374 , .p_nrxdesc = SIP_NRXDESC 375 , .p_bits = { 376 .b_txcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 377 , .b_txcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 378 , .b_txcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 379 , .b_txcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 380 , .b_txcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 381 , .b_txcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 382 , .b_txcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 383 , .b_txcfg_flth_mask = 0x00003f00 /* Tx fill threshold */ 384 , .b_txcfg_drth_mask = 0x0000003f /* Tx drain threshold */ 385 386 , .b_rxcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 387 , .b_rxcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 388 , .b_rxcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 389 , .b_rxcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 390 , .b_rxcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 391 , .b_rxcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 392 , .b_rxcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 393 394 , .b_isr_txrcmp = 0x02000000 /* transmit reset complete */ 395 , .b_isr_rxrcmp = 0x01000000 /* receive reset complete */ 396 , .b_isr_dperr = 0x00800000 /* detected parity error */ 397 , .b_isr_sserr = 0x00400000 /* signalled system error */ 398 , .b_isr_rmabt = 0x00200000 /* received master abort */ 399 , .b_isr_rtabt = 0x00100000 /* received target abort */ 400 , .b_cmdsts_size_mask = OTHER_CMDSTS_SIZE_MASK 401 } 402 , .p_regs = { 403 .r_rxcfg = OTHER_SIP_RXCFG, 404 .r_txcfg = OTHER_SIP_TXCFG 405 } 406 }, gsip_parm = { 407 .p_filtmem = DP83820_RFCR_NS_RFADDR_FILTMEM 408 , .p_rxbuf_len = MCLBYTES - 8 409 , .p_tx_dmamap_size = ETHER_MAX_LEN_JUMBO 410 , .p_ntxsegs = 64 411 , .p_ntxsegs_alloc = GSIP_NTXSEGS_ALLOC 412 , .p_nrxdesc = GSIP_NRXDESC 413 , .p_bits = { 414 .b_txcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 415 , .b_txcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 416 , .b_txcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 417 , .b_txcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 418 , .b_txcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 419 , .b_txcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 420 , .b_txcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 421 , .b_txcfg_flth_mask = 0x0000ff00 /* Fx fill threshold */ 422 , .b_txcfg_drth_mask = 0x000000ff /* Tx drain threshold */ 423 424 , .b_rxcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 425 , .b_rxcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 426 , .b_rxcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 427 , .b_rxcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 428 , .b_rxcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 429 , .b_rxcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 430 , .b_rxcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 431 432 , .b_isr_txrcmp = 0x00400000 /* transmit reset complete */ 433 , .b_isr_rxrcmp = 0x00200000 /* receive reset complete */ 434 , .b_isr_dperr = 0x00100000 /* detected parity error */ 435 , .b_isr_sserr = 0x00080000 /* signalled system error */ 436 , .b_isr_rmabt = 0x00040000 /* received master abort */ 437 , .b_isr_rtabt = 0x00020000 /* received target abort */ 438 , .b_cmdsts_size_mask = DP83820_CMDSTS_SIZE_MASK 439 } 440 , .p_regs = { 441 .r_rxcfg = DP83820_SIP_RXCFG, 442 .r_txcfg = DP83820_SIP_TXCFG 443 } 444 }; 445 446 static inline int 447 sip_nexttx(const struct sip_softc *sc, int x) 448 { 449 return (x + 1) & sc->sc_ntxdesc_mask; 450 } 451 452 static inline int 453 sip_nextrx(const struct sip_softc *sc, int x) 454 { 455 return (x + 1) & sc->sc_nrxdesc_mask; 456 } 457 458 /* 83820 only */ 459 static inline void 460 sip_rxchain_reset(struct sip_softc *sc) 461 { 462 sc->sc_rxtailp = &sc->sc_rxhead; 463 *sc->sc_rxtailp = NULL; 464 sc->sc_rxlen = 0; 465 } 466 467 /* 83820 only */ 468 static inline void 469 sip_rxchain_link(struct sip_softc *sc, struct mbuf *m) 470 { 471 *sc->sc_rxtailp = sc->sc_rxtail = m; 472 sc->sc_rxtailp = &m->m_next; 473 } 474 475 #ifdef SIP_EVENT_COUNTERS 476 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 477 #else 478 #define SIP_EVCNT_INCR(ev) /* nothing */ 479 #endif 480 481 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 482 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 483 484 static inline void 485 sip_set_rxdp(struct sip_softc *sc, bus_addr_t addr) 486 { 487 if (sc->sc_gigabit) 488 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXDP_HI, 489 BUS_ADDR_HI32(addr)); 490 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXDP, BUS_ADDR_LO32(addr)); 491 } 492 493 static inline void 494 sip_set_txdp(struct sip_softc *sc, bus_addr_t addr) 495 { 496 if (sc->sc_gigabit) 497 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP_HI, 498 BUS_ADDR_HI32(addr)); 499 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, BUS_ADDR_LO32(addr)); 500 } 501 502 static inline void 503 sip_cdtxsync(struct sip_softc *sc, const int x0, const int n0, const int ops) 504 { 505 int x, n; 506 507 x = x0; 508 n = n0; 509 510 /* If it will wrap around, sync to the end of the ring. */ 511 if (x + n > sc->sc_ntxdesc) { 512 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 513 SIP_CDTXOFF(x), sizeof(struct sip_desc) * 514 (sc->sc_ntxdesc - x), ops); 515 n -= (sc->sc_ntxdesc - x); 516 x = 0; 517 } 518 519 /* Now sync whatever is left. */ 520 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 521 SIP_CDTXOFF(x), sizeof(struct sip_desc) * n, ops); 522 } 523 524 static inline void 525 sip_cdrxsync(struct sip_softc *sc, int x, int ops) 526 { 527 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 528 SIP_CDRXOFF(x), sizeof(struct sip_desc), ops); 529 } 530 531 static void 532 sip_init_txring(struct sip_softc *sc) 533 { 534 struct sip_desc *sipd; 535 bus_addr_t next_desc; 536 int i; 537 538 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 539 for (i = 0; i < sc->sc_ntxdesc; i++) { 540 sipd = &sc->sc_txdescs[i]; 541 next_desc = SIP_CDTXADDR(sc, sip_nexttx(sc, i)); 542 if (sc->sc_dma64) { 543 sipd->sipd_words[GSIP64_DESC_LINK_LO] = 544 htole32(BUS_ADDR_LO32(next_desc)); 545 sipd->sipd_words[GSIP64_DESC_LINK_HI] = 546 htole32(BUS_ADDR_HI32(next_desc)); 547 } else { 548 /* SIP_DESC_LINK == GSIP_DESC_LINK */ 549 sipd->sipd_words[SIP_DESC_LINK] = htole32(next_desc); 550 } 551 } 552 sip_cdtxsync(sc, 0, sc->sc_ntxdesc, 553 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 554 sc->sc_txfree = sc->sc_ntxdesc; 555 sc->sc_txnext = 0; 556 sc->sc_txwin = 0; 557 } 558 559 static inline void 560 sip_init_txdesc(struct sip_softc *sc, int x, bus_addr_t bufptr, uint32_t cmdsts) 561 { 562 struct sip_desc *sipd = &sc->sc_txdescs[x]; 563 564 if (sc->sc_dma64) { 565 sipd->sipd_words[GSIP64_DESC_BUFPTR_LO] = 566 htole32(BUS_ADDR_LO32(bufptr)); 567 sipd->sipd_words[GSIP64_DESC_BUFPTR_HI] = 568 htole32(BUS_ADDR_HI32(bufptr)); 569 } else { 570 sipd->sipd_words[sc->sc_bufptr_idx] = htole32(bufptr); 571 } 572 sipd->sipd_words[sc->sc_extsts_idx] = 0; 573 membar_producer(); 574 sipd->sipd_words[sc->sc_cmdsts_idx] = htole32(cmdsts); 575 /* sip_cdtxsync() will be done later. */ 576 } 577 578 static inline void 579 sip_init_rxdesc(struct sip_softc *sc, int x) 580 { 581 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 582 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 583 const bus_addr_t next_desc = SIP_CDRXADDR(sc, sip_nextrx(sc, x)); 584 585 if (sc->sc_dma64) { 586 sipd->sipd_words[GSIP64_DESC_LINK_LO] = 587 htole32(BUS_ADDR_LO32(next_desc)); 588 sipd->sipd_words[GSIP64_DESC_LINK_HI] = 589 htole32(BUS_ADDR_HI32(next_desc)); 590 sipd->sipd_words[GSIP64_DESC_BUFPTR_LO] = 591 htole32(BUS_ADDR_LO32(rxs->rxs_dmamap->dm_segs[0].ds_addr)); 592 sipd->sipd_words[GSIP64_DESC_BUFPTR_HI] = 593 htole32(BUS_ADDR_HI32(rxs->rxs_dmamap->dm_segs[0].ds_addr)); 594 } else { 595 sipd->sipd_words[SIP_DESC_LINK] = htole32(next_desc); 596 sipd->sipd_words[sc->sc_bufptr_idx] = 597 htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 598 } 599 sipd->sipd_words[sc->sc_extsts_idx] = 0; 600 membar_producer(); 601 sipd->sipd_words[sc->sc_cmdsts_idx] = 602 htole32(CMDSTS_INTR | (sc->sc_parm->p_rxbuf_len & 603 sc->sc_bits.b_cmdsts_size_mask)); 604 sip_cdrxsync(sc, x, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 605 } 606 607 #define SIP_CHIP_VERS(sc, v, p, r) \ 608 ((sc)->sc_model->sip_vendor == (v) && \ 609 (sc)->sc_model->sip_product == (p) && \ 610 (sc)->sc_rev == (r)) 611 612 #define SIP_CHIP_MODEL(sc, v, p) \ 613 ((sc)->sc_model->sip_vendor == (v) && \ 614 (sc)->sc_model->sip_product == (p)) 615 616 #define SIP_SIS900_REV(sc, rev) \ 617 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 618 619 #define SIP_TIMEOUT 1000 620 621 static int sip_ifflags_cb(struct ethercom *); 622 static void sipcom_start(struct ifnet *); 623 static void sipcom_watchdog(struct ifnet *); 624 static int sipcom_ioctl(struct ifnet *, u_long, void *); 625 static int sipcom_init(struct ifnet *); 626 static void sipcom_stop(struct ifnet *, int); 627 628 static bool sipcom_reset(struct sip_softc *); 629 static void sipcom_rxdrain(struct sip_softc *); 630 static int sipcom_add_rxbuf(struct sip_softc *, int); 631 static void sipcom_read_eeprom(struct sip_softc *, int, int, 632 uint16_t *); 633 static void sipcom_tick(void *); 634 635 static void sipcom_sis900_set_filter(struct sip_softc *); 636 static void sipcom_dp83815_set_filter(struct sip_softc *); 637 638 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 639 const struct pci_attach_args *, uint8_t *); 640 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 641 static void sipcom_sis900_read_macaddr(struct sip_softc *, 642 const struct pci_attach_args *, uint8_t *); 643 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 644 const struct pci_attach_args *, uint8_t *); 645 646 static int sipcom_intr(void *); 647 static void sipcom_txintr(struct sip_softc *); 648 static void sip_rxintr(struct sip_softc *); 649 static void gsip_rxintr(struct sip_softc *); 650 651 static int sipcom_dp83820_mii_readreg(device_t, int, int, uint16_t *); 652 static int sipcom_dp83820_mii_writereg(device_t, int, int, uint16_t); 653 static void sipcom_dp83820_mii_statchg(struct ifnet *); 654 655 static int sipcom_sis900_mii_readreg(device_t, int, int, uint16_t *); 656 static int sipcom_sis900_mii_writereg(device_t, int, int, uint16_t); 657 static void sipcom_sis900_mii_statchg(struct ifnet *); 658 659 static int sipcom_dp83815_mii_readreg(device_t, int, int, uint16_t *); 660 static int sipcom_dp83815_mii_writereg(device_t, int, int, uint16_t); 661 static void sipcom_dp83815_mii_statchg(struct ifnet *); 662 663 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 664 665 static int sipcom_match(device_t, cfdata_t, void *); 666 static void sipcom_attach(device_t, device_t, void *); 667 static void sipcom_do_detach(device_t, enum sip_attach_stage); 668 static int sipcom_detach(device_t, int); 669 static bool sipcom_resume(device_t, const pmf_qual_t *); 670 static bool sipcom_suspend(device_t, const pmf_qual_t *); 671 672 int gsip_copy_small = 0; 673 int sip_copy_small = 0; 674 675 CFATTACH_DECL3_NEW(gsip, sizeof(struct sip_softc), 676 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 677 DVF_DETACH_SHUTDOWN); 678 CFATTACH_DECL3_NEW(sip, sizeof(struct sip_softc), 679 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 680 DVF_DETACH_SHUTDOWN); 681 682 /* 683 * Descriptions of the variants of the SiS900. 684 */ 685 struct sip_variant { 686 int (*sipv_mii_readreg)(device_t, int, int, uint16_t *); 687 int (*sipv_mii_writereg)(device_t, int, int, uint16_t); 688 void (*sipv_mii_statchg)(struct ifnet *); 689 void (*sipv_set_filter)(struct sip_softc *); 690 void (*sipv_read_macaddr)(struct sip_softc *, 691 const struct pci_attach_args *, uint8_t *); 692 }; 693 694 static uint32_t sipcom_mii_bitbang_read(device_t); 695 static void sipcom_mii_bitbang_write(device_t, uint32_t); 696 697 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 698 sipcom_mii_bitbang_read, 699 sipcom_mii_bitbang_write, 700 { 701 EROMAR_MDIO, /* MII_BIT_MDO */ 702 EROMAR_MDIO, /* MII_BIT_MDI */ 703 EROMAR_MDC, /* MII_BIT_MDC */ 704 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 705 0, /* MII_BIT_DIR_PHY_HOST */ 706 } 707 }; 708 709 static const struct sip_variant sipcom_variant_dp83820 = { 710 sipcom_dp83820_mii_readreg, 711 sipcom_dp83820_mii_writereg, 712 sipcom_dp83820_mii_statchg, 713 sipcom_dp83815_set_filter, 714 sipcom_dp83820_read_macaddr, 715 }; 716 717 static const struct sip_variant sipcom_variant_sis900 = { 718 sipcom_sis900_mii_readreg, 719 sipcom_sis900_mii_writereg, 720 sipcom_sis900_mii_statchg, 721 sipcom_sis900_set_filter, 722 sipcom_sis900_read_macaddr, 723 }; 724 725 static const struct sip_variant sipcom_variant_dp83815 = { 726 sipcom_dp83815_mii_readreg, 727 sipcom_dp83815_mii_writereg, 728 sipcom_dp83815_mii_statchg, 729 sipcom_dp83815_set_filter, 730 sipcom_dp83815_read_macaddr, 731 }; 732 733 734 /* 735 * Devices supported by this driver. 736 */ 737 static const struct sip_product { 738 pci_vendor_id_t sip_vendor; 739 pci_product_id_t sip_product; 740 const char *sip_name; 741 const struct sip_variant *sip_variant; 742 bool sip_gigabit; 743 } sipcom_products[] = { 744 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 745 "NatSemi DP83820 Gigabit Ethernet", 746 &sipcom_variant_dp83820, true }, 747 748 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 749 "SiS 900 10/100 Ethernet", 750 &sipcom_variant_sis900, false }, 751 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 752 "SiS 7016 10/100 Ethernet", 753 &sipcom_variant_sis900, false }, 754 755 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 756 "NatSemi DP83815 10/100 Ethernet", 757 &sipcom_variant_dp83815, false }, 758 759 { 0, 0, 760 NULL, 761 NULL, false }, 762 }; 763 764 static const struct sip_product * 765 sipcom_lookup(const struct pci_attach_args *pa, bool gigabit) 766 { 767 const struct sip_product *sip; 768 769 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 770 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 771 PCI_PRODUCT(pa->pa_id) == sip->sip_product && 772 sip->sip_gigabit == gigabit) 773 return sip; 774 } 775 return NULL; 776 } 777 778 /* 779 * I really hate stupid hardware vendors. There's a bit in the EEPROM 780 * which indicates if the card can do 64-bit data transfers. Unfortunately, 781 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 782 * which means we try to use 64-bit data transfers on those cards if we 783 * happen to be plugged into a 32-bit slot. 784 * 785 * What we do is use this table of cards known to be 64-bit cards. If 786 * you have a 64-bit card who's subsystem ID is not listed in this table, 787 * send the output of "pcictl dump ..." of the device to me so that your 788 * card will use the 64-bit data path when plugged into a 64-bit slot. 789 * 790 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 791 * June 30, 2002 792 */ 793 static int 794 sipcom_check_64bit(const struct pci_attach_args *pa) 795 { 796 static const struct { 797 pci_vendor_id_t c64_vendor; 798 pci_product_id_t c64_product; 799 } card64[] = { 800 /* Asante GigaNIX */ 801 { 0x128a, 0x0002 }, 802 803 /* Accton EN1407-T, Planex GN-1000TE */ 804 { 0x1113, 0x1407 }, 805 806 /* Netgear GA621 */ 807 { 0x1385, 0x621a }, 808 809 /* Netgear GA622 */ 810 { 0x1385, 0x622a }, 811 812 /* SMC EZ Card 1000 (9462TX) */ 813 { 0x10b8, 0x9462 }, 814 815 { 0, 0} 816 }; 817 pcireg_t subsys; 818 int i; 819 820 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 821 822 for (i = 0; card64[i].c64_vendor != 0; i++) { 823 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 824 PCI_PRODUCT(subsys) == card64[i].c64_product) 825 return 1; 826 } 827 828 return 0; 829 } 830 831 static int 832 sipcom_match(device_t parent, cfdata_t cf, void *aux) 833 { 834 struct pci_attach_args *pa = aux; 835 836 if (sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0) != NULL) 837 return 1; 838 839 return 0; 840 } 841 842 static void 843 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 844 { 845 uint32_t reg; 846 int i; 847 848 /* 849 * Cause the chip to load configuration data from the EEPROM. 850 */ 851 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 852 for (i = 0; i < 10000; i++) { 853 delay(10); 854 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 855 PTSCR_EELOAD_EN) == 0) 856 break; 857 } 858 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 859 PTSCR_EELOAD_EN) { 860 printf("%s: timeout loading configuration from EEPROM\n", 861 device_xname(sc->sc_dev)); 862 return; 863 } 864 865 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 866 867 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 868 if (reg & CFG_PCI64_DET) { 869 const char *using64 = NULL; 870 871 if (reg & CFG_DATA64_EN) { 872 /* 873 * Check to see if this card is 64-bit. If so, 874 * enable 64-bit data transfers. 875 * 876 * We can't trust the DATA64_EN bit in the EEPROM, 877 * because vendors of 32-bit cards fail to clear 878 * that bit in many cases (yet the card still detects 879 * that it's in a 64-bit slot because I guess they 880 * wired up ACK64# and REQ64#). 881 */ 882 if (gsip_disable_data64) 883 using64 = "force-disabled"; 884 else if (sipcom_check_64bit(pa)) { 885 sc->sc_cfg |= CFG_DATA64_EN; 886 using64 = "enabled"; 887 } else 888 using64 = "disabled (32-bit card)"; 889 } else { 890 using64 = "disabled in EEPROM"; 891 } 892 printf("%s: 64-bit slot detected, 64-bit tranfers %s\n", 893 device_xname(sc->sc_dev), using64); 894 } 895 896 /* 897 * The T64ADDR bit is loaded by the chip from the EEPROM and 898 * is read-only. 899 */ 900 if (reg & CFG_T64ADDR) 901 sc->sc_cfg |= CFG_T64ADDR; 902 903 /* 904 * We can use 64-bit DMA addressing regardless of what 905 * sort of slot we're in. 906 */ 907 if (pci_dma64_available(pa)) { 908 sc->sc_dmat = pa->pa_dmat64; 909 sc->sc_cfg |= CFG_M64ADDR; 910 sc->sc_dma64 = true; 911 } 912 913 if (reg & (CFG_TBI_EN | CFG_EXT_125)) { 914 const char *sep = ""; 915 printf("%s: using ", device_xname(sc->sc_dev)); 916 if (reg & CFG_EXT_125) { 917 sc->sc_cfg |= CFG_EXT_125; 918 printf("%sexternal 125MHz clock", sep); 919 sep = ", "; 920 } 921 if (reg & CFG_TBI_EN) { 922 sc->sc_cfg |= CFG_TBI_EN; 923 printf("%sten-bit interface", sep); 924 sep = ", "; 925 } 926 printf("\n"); 927 } 928 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 929 (reg & CFG_MRM_DIS) != 0) 930 sc->sc_cfg |= CFG_MRM_DIS; 931 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 932 (reg & CFG_MWI_DIS) != 0) 933 sc->sc_cfg |= CFG_MWI_DIS; 934 935 /* 936 * Use the extended descriptor format on the DP83820. This 937 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 938 * checksumming. 939 */ 940 sc->sc_cfg |= CFG_EXTSTS_EN; 941 } 942 943 static int 944 sipcom_detach(device_t self, int flags) 945 { 946 int s; 947 948 s = splnet(); 949 sipcom_do_detach(self, SIP_ATTACH_FIN); 950 splx(s); 951 952 return 0; 953 } 954 955 static void 956 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 957 { 958 int i; 959 struct sip_softc *sc = device_private(self); 960 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 961 962 /* 963 * Free any resources we've allocated during attach. 964 * Do this in reverse order and fall through. 965 */ 966 switch (stage) { 967 case SIP_ATTACH_FIN: 968 sipcom_stop(ifp, 1); 969 pmf_device_deregister(self); 970 #ifdef SIP_EVENT_COUNTERS 971 /* 972 * Attach event counters. 973 */ 974 evcnt_detach(&sc->sc_ev_txforceintr); 975 evcnt_detach(&sc->sc_ev_txdstall); 976 evcnt_detach(&sc->sc_ev_txsstall); 977 evcnt_detach(&sc->sc_ev_hiberr); 978 evcnt_detach(&sc->sc_ev_rxintr); 979 evcnt_detach(&sc->sc_ev_txiintr); 980 evcnt_detach(&sc->sc_ev_txdintr); 981 if (!sc->sc_gigabit) { 982 evcnt_detach(&sc->sc_ev_rxpause); 983 } else { 984 evcnt_detach(&sc->sc_ev_txudpsum); 985 evcnt_detach(&sc->sc_ev_txtcpsum); 986 evcnt_detach(&sc->sc_ev_txipsum); 987 evcnt_detach(&sc->sc_ev_rxudpsum); 988 evcnt_detach(&sc->sc_ev_rxtcpsum); 989 evcnt_detach(&sc->sc_ev_rxipsum); 990 evcnt_detach(&sc->sc_ev_txpause); 991 evcnt_detach(&sc->sc_ev_rxpause); 992 } 993 #endif /* SIP_EVENT_COUNTERS */ 994 995 rnd_detach_source(&sc->rnd_source); 996 997 ether_ifdetach(ifp); 998 if_detach(ifp); 999 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1000 ifmedia_fini(&sc->sc_mii.mii_media); 1001 1002 /*FALLTHROUGH*/ 1003 case SIP_ATTACH_CREATE_RXMAP: 1004 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1005 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1006 bus_dmamap_destroy(sc->sc_dmat, 1007 sc->sc_rxsoft[i].rxs_dmamap); 1008 } 1009 /*FALLTHROUGH*/ 1010 case SIP_ATTACH_CREATE_TXMAP: 1011 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1012 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1013 bus_dmamap_destroy(sc->sc_dmat, 1014 sc->sc_txsoft[i].txs_dmamap); 1015 } 1016 /*FALLTHROUGH*/ 1017 case SIP_ATTACH_LOAD_MAP: 1018 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1019 /*FALLTHROUGH*/ 1020 case SIP_ATTACH_CREATE_MAP: 1021 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1022 /*FALLTHROUGH*/ 1023 case SIP_ATTACH_MAP_MEM: 1024 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 1025 sizeof(struct sip_control_data)); 1026 /*FALLTHROUGH*/ 1027 case SIP_ATTACH_ALLOC_MEM: 1028 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 1029 /* FALLTHROUGH*/ 1030 case SIP_ATTACH_INTR: 1031 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 1032 /* FALLTHROUGH*/ 1033 case SIP_ATTACH_MAP: 1034 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 1035 break; 1036 default: 1037 break; 1038 } 1039 return; 1040 } 1041 1042 static bool 1043 sipcom_resume(device_t self, const pmf_qual_t *qual) 1044 { 1045 struct sip_softc *sc = device_private(self); 1046 1047 return sipcom_reset(sc); 1048 } 1049 1050 static bool 1051 sipcom_suspend(device_t self, const pmf_qual_t *qual) 1052 { 1053 struct sip_softc *sc = device_private(self); 1054 1055 sipcom_rxdrain(sc); 1056 return true; 1057 } 1058 1059 static void 1060 sipcom_attach(device_t parent, device_t self, void *aux) 1061 { 1062 struct sip_softc *sc = device_private(self); 1063 struct pci_attach_args *pa = aux; 1064 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1065 struct mii_data * const mii = &sc->sc_mii; 1066 pci_chipset_tag_t pc = pa->pa_pc; 1067 pci_intr_handle_t ih; 1068 const char *intrstr = NULL; 1069 bus_space_tag_t iot, memt; 1070 bus_space_handle_t ioh, memh; 1071 bus_size_t iosz, memsz; 1072 int ioh_valid, memh_valid; 1073 int i, rseg, error; 1074 const struct sip_product *sip; 1075 uint8_t enaddr[ETHER_ADDR_LEN]; 1076 pcireg_t csr; 1077 pcireg_t memtype; 1078 bus_size_t tx_dmamap_size; 1079 int ntxsegs_alloc; 1080 cfdata_t cf = device_cfdata(self); 1081 char intrbuf[PCI_INTRSTR_LEN]; 1082 1083 callout_init(&sc->sc_tick_ch, 0); 1084 callout_setfunc(&sc->sc_tick_ch, sipcom_tick, sc); 1085 1086 sip = sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0); 1087 if (sip == NULL) { 1088 aprint_error("\n"); 1089 panic("%s: impossible", __func__); 1090 } 1091 sc->sc_dev = self; 1092 sc->sc_gigabit = sip->sip_gigabit; 1093 sc->sc_dma64 = false; 1094 pmf_self_suspensor_init(self, &sc->sc_suspensor, &sc->sc_qual); 1095 sc->sc_pc = pc; 1096 1097 if (sc->sc_gigabit) { 1098 if (sc->sc_dma64) { 1099 sc->sc_bufptr_idx = GSIP64_DESC_BUFPTR_LO; 1100 sc->sc_cmdsts_idx = GSIP64_DESC_CMDSTS; 1101 sc->sc_extsts_idx = GSIP64_DESC_EXTSTS; 1102 } else { 1103 sc->sc_bufptr_idx = GSIP_DESC_BUFPTR; 1104 sc->sc_cmdsts_idx = GSIP_DESC_CMDSTS; 1105 sc->sc_extsts_idx = GSIP_DESC_EXTSTS; 1106 } 1107 sc->sc_rxintr = gsip_rxintr; 1108 sc->sc_parm = &gsip_parm; 1109 } else { 1110 sc->sc_rxintr = sip_rxintr; 1111 sc->sc_parm = &sip_parm; 1112 sc->sc_bufptr_idx = SIP_DESC_BUFPTR; 1113 sc->sc_cmdsts_idx = SIP_DESC_CMDSTS; 1114 /* 1115 * EXTSTS doesn't really exist on non-GigE parts, 1116 * but we initialize the index for simplicity later. 1117 */ 1118 sc->sc_extsts_idx = GSIP_DESC_EXTSTS; 1119 } 1120 tx_dmamap_size = sc->sc_parm->p_tx_dmamap_size; 1121 ntxsegs_alloc = sc->sc_parm->p_ntxsegs_alloc; 1122 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 1123 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 1124 sc->sc_nrxdesc_mask = sc->sc_parm->p_nrxdesc - 1; 1125 1126 sc->sc_rev = PCI_REVISION(pa->pa_class); 1127 1128 aprint_naive("\n"); 1129 aprint_normal(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 1130 1131 sc->sc_model = sip; 1132 1133 /* 1134 * XXX Work-around broken PXE firmware on some boards. 1135 * 1136 * The DP83815 shares an address decoder with the MEM BAR 1137 * and the ROM BAR. Make sure the ROM BAR is disabled, 1138 * so that memory mapped access works. 1139 */ 1140 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1141 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1142 ~PCI_MAPREG_ROM_ENABLE); 1143 1144 /* 1145 * Map the device. 1146 */ 1147 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 1148 PCI_MAPREG_TYPE_IO, 0, 1149 &iot, &ioh, NULL, &iosz) == 0); 1150 if (sc->sc_gigabit) { 1151 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 1152 switch (memtype) { 1153 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1154 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1155 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1156 memtype, 0, &memt, &memh, NULL, &memsz) == 0); 1157 break; 1158 default: 1159 memh_valid = 0; 1160 } 1161 } else { 1162 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1163 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 1164 &memt, &memh, NULL, &memsz) == 0); 1165 } 1166 1167 if (memh_valid) { 1168 sc->sc_st = memt; 1169 sc->sc_sh = memh; 1170 sc->sc_sz = memsz; 1171 } else if (ioh_valid) { 1172 sc->sc_st = iot; 1173 sc->sc_sh = ioh; 1174 sc->sc_sz = iosz; 1175 } else { 1176 aprint_error_dev(self, "unable to map device registers\n"); 1177 return; 1178 } 1179 1180 sc->sc_dmat = pa->pa_dmat; 1181 1182 /* 1183 * Make sure bus mastering is enabled. Also make sure 1184 * Write/Invalidate is enabled if we're allowed to use it. 1185 */ 1186 csr = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1187 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 1188 csr |= PCI_COMMAND_INVALIDATE_ENABLE; 1189 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1190 csr | PCI_COMMAND_MASTER_ENABLE); 1191 1192 /* Power up chip */ 1193 error = pci_activate(pa->pa_pc, pa->pa_tag, self, pci_activate_null); 1194 if (error != 0 && error != EOPNOTSUPP) { 1195 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 1196 return; 1197 } 1198 1199 /* 1200 * Map and establish our interrupt. 1201 */ 1202 if (pci_intr_map(pa, &ih)) { 1203 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 1204 return; 1205 } 1206 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1207 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, sipcom_intr, sc, 1208 device_xname(self)); 1209 if (sc->sc_ih == NULL) { 1210 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 1211 if (intrstr != NULL) 1212 aprint_error(" at %s", intrstr); 1213 aprint_error("\n"); 1214 sipcom_do_detach(self, SIP_ATTACH_MAP); 1215 return; 1216 } 1217 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1218 1219 SIMPLEQ_INIT(&sc->sc_txfreeq); 1220 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1221 1222 /* 1223 * Allocate the control data structures, and create and load the 1224 * DMA map for it. 1225 */ 1226 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1227 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 1228 &rseg, 0)) != 0) { 1229 aprint_error_dev(sc->sc_dev, 1230 "unable to allocate control data, error = %d\n", error); 1231 sipcom_do_detach(self, SIP_ATTACH_INTR); 1232 return; 1233 } 1234 1235 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 1236 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 1237 BUS_DMA_COHERENT)) != 0) { 1238 aprint_error_dev(sc->sc_dev, 1239 "unable to map control data, error = %d\n", error); 1240 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 1241 } 1242 1243 if ((error = bus_dmamap_create(sc->sc_dmat, 1244 sizeof(struct sip_control_data), 1, 1245 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 1246 aprint_error_dev(self, "unable to create control data DMA map" 1247 ", error = %d\n", error); 1248 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 1249 } 1250 1251 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1252 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 1253 0)) != 0) { 1254 aprint_error_dev(self, "unable to load control data DMA map" 1255 ", error = %d\n", error); 1256 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 1257 } 1258 1259 /* 1260 * Create the transmit buffer DMA maps. 1261 */ 1262 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1263 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 1264 sc->sc_parm->p_ntxsegs, MCLBYTES, 0, 0, 1265 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1266 aprint_error_dev(self, "unable to create tx DMA map %d" 1267 ", error = %d\n", i, error); 1268 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 1269 } 1270 } 1271 1272 /* 1273 * Create the receive buffer DMA maps. 1274 */ 1275 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1276 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1277 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1278 aprint_error_dev(self, "unable to create rx DMA map %d" 1279 ", error = %d\n", i, error); 1280 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 1281 } 1282 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1283 } 1284 1285 /* 1286 * Reset the chip to a known state. 1287 */ 1288 sipcom_reset(sc); 1289 1290 /* 1291 * Read the Ethernet address from the EEPROM. This might 1292 * also fetch other stuff from the EEPROM and stash it 1293 * in the softc. 1294 */ 1295 sc->sc_cfg = 0; 1296 if (!sc->sc_gigabit) { 1297 if (SIP_SIS900_REV(sc, SIS_REV_635) || 1298 SIP_SIS900_REV(sc, SIS_REV_900B)) 1299 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1300 1301 if (SIP_SIS900_REV(sc, SIS_REV_635) || 1302 SIP_SIS900_REV(sc, SIS_REV_960) || 1303 SIP_SIS900_REV(sc, SIS_REV_900B)) 1304 sc->sc_cfg |= 1305 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1306 CFG_EDBMASTEN); 1307 } 1308 1309 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1310 1311 aprint_normal_dev(self, "Ethernet address %s\n",ether_sprintf(enaddr)); 1312 1313 /* 1314 * Initialize the configuration register: aggressive PCI 1315 * bus request algorithm, default backoff, default OW timer, 1316 * default parity error detection. 1317 * 1318 * NOTE: "Big endian mode" is useless on the SiS900 and 1319 * friends -- it affects packet data, not descriptors. 1320 */ 1321 if (sc->sc_gigabit) 1322 sipcom_dp83820_attach(sc, pa); 1323 1324 /* 1325 * Initialize our media structures and probe the MII. 1326 */ 1327 mii->mii_ifp = ifp; 1328 mii->mii_readreg = sip->sip_variant->sipv_mii_readreg; 1329 mii->mii_writereg = sip->sip_variant->sipv_mii_writereg; 1330 mii->mii_statchg = sip->sip_variant->sipv_mii_statchg; 1331 sc->sc_ethercom.ec_mii = mii; 1332 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 1333 sipcom_mediastatus); 1334 1335 /* 1336 * XXX We cannot handle flow control on the DP83815. 1337 */ 1338 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1339 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 1340 MII_OFFSET_ANY, 0); 1341 else 1342 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 1343 MII_OFFSET_ANY, MIIF_DOPAUSE); 1344 if (LIST_FIRST(&mii->mii_phys) == NULL) { 1345 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 1346 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 1347 } else 1348 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1349 1350 ifp = &sc->sc_ethercom.ec_if; 1351 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1352 ifp->if_softc = sc; 1353 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1354 sc->sc_if_flags = ifp->if_flags; 1355 ifp->if_ioctl = sipcom_ioctl; 1356 ifp->if_start = sipcom_start; 1357 ifp->if_watchdog = sipcom_watchdog; 1358 ifp->if_init = sipcom_init; 1359 ifp->if_stop = sipcom_stop; 1360 IFQ_SET_READY(&ifp->if_snd); 1361 1362 /* 1363 * We can support 802.1Q VLAN-sized frames. 1364 */ 1365 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1366 1367 if (sc->sc_gigabit) { 1368 /* 1369 * And the DP83820 can do VLAN tagging in hardware, and 1370 * support the jumbo Ethernet MTU. 1371 */ 1372 sc->sc_ethercom.ec_capabilities |= 1373 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1374 sc->sc_ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 1375 1376 /* 1377 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1378 * in hardware. 1379 */ 1380 ifp->if_capabilities |= 1381 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1382 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1383 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1384 } 1385 1386 /* 1387 * Attach the interface. 1388 */ 1389 if_attach(ifp); 1390 if_deferred_start_init(ifp, NULL); 1391 ether_ifattach(ifp, enaddr); 1392 ether_set_ifflags_cb(&sc->sc_ethercom, sip_ifflags_cb); 1393 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1394 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1395 sc->sc_prev.if_capenable = ifp->if_capenable; 1396 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 1397 RND_TYPE_NET, RND_FLAG_DEFAULT); 1398 1399 /* 1400 * The number of bytes that must be available in 1401 * the Tx FIFO before the bus master can DMA more 1402 * data into the FIFO. 1403 */ 1404 sc->sc_tx_fill_thresh = 64 / 32; 1405 1406 /* 1407 * Start at a drain threshold of 512 bytes. We will 1408 * increase it if a DMA underrun occurs. 1409 * 1410 * XXX The minimum value of this variable should be 1411 * tuned. We may be able to improve performance 1412 * by starting with a lower value. That, however, 1413 * may trash the first few outgoing packets if the 1414 * PCI bus is saturated. 1415 */ 1416 if (sc->sc_gigabit) 1417 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1418 else 1419 sc->sc_tx_drain_thresh = 1504 / 32; 1420 1421 /* 1422 * Initialize the Rx FIFO drain threshold. 1423 * 1424 * This is in units of 8 bytes. 1425 * 1426 * We should never set this value lower than 2; 14 bytes are 1427 * required to filter the packet. 1428 */ 1429 sc->sc_rx_drain_thresh = 128 / 8; 1430 1431 #ifdef SIP_EVENT_COUNTERS 1432 /* 1433 * Attach event counters. 1434 */ 1435 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1436 NULL, device_xname(sc->sc_dev), "txsstall"); 1437 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1438 NULL, device_xname(sc->sc_dev), "txdstall"); 1439 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1440 NULL, device_xname(sc->sc_dev), "txforceintr"); 1441 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1442 NULL, device_xname(sc->sc_dev), "txdintr"); 1443 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1444 NULL, device_xname(sc->sc_dev), "txiintr"); 1445 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1446 NULL, device_xname(sc->sc_dev), "rxintr"); 1447 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1448 NULL, device_xname(sc->sc_dev), "hiberr"); 1449 if (!sc->sc_gigabit) { 1450 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1451 NULL, device_xname(sc->sc_dev), "rxpause"); 1452 } else { 1453 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1454 NULL, device_xname(sc->sc_dev), "rxpause"); 1455 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1456 NULL, device_xname(sc->sc_dev), "txpause"); 1457 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1458 NULL, device_xname(sc->sc_dev), "rxipsum"); 1459 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1460 NULL, device_xname(sc->sc_dev), "rxtcpsum"); 1461 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1462 NULL, device_xname(sc->sc_dev), "rxudpsum"); 1463 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1464 NULL, device_xname(sc->sc_dev), "txipsum"); 1465 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1466 NULL, device_xname(sc->sc_dev), "txtcpsum"); 1467 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1468 NULL, device_xname(sc->sc_dev), "txudpsum"); 1469 } 1470 #endif /* SIP_EVENT_COUNTERS */ 1471 1472 if (pmf_device_register(self, sipcom_suspend, sipcom_resume)) 1473 pmf_class_network_register(self, ifp); 1474 else 1475 aprint_error_dev(self, "couldn't establish power handler\n"); 1476 } 1477 1478 static inline void 1479 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1480 uint64_t capenable) 1481 { 1482 uint32_t extsts = 0; 1483 #ifdef DEBUG 1484 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1485 #endif 1486 /* 1487 * If VLANs are enabled and the packet has a VLAN tag, set 1488 * up the descriptor to encapsulate the packet for us. 1489 * 1490 * This apparently has to be on the last descriptor of 1491 * the packet. 1492 */ 1493 1494 /* 1495 * Byte swapping is tricky. We need to provide the tag 1496 * in a network byte order. On a big-endian machine, 1497 * the byteorder is correct, but we need to swap it 1498 * anyway, because this will be undone by the outside 1499 * htole32(). That's why there must be an 1500 * unconditional swap instead of htons() inside. 1501 */ 1502 if (vlan_has_tag(m0)) { 1503 sc->sc_txdescs[lasttx].sipd_words[sc->sc_extsts_idx] |= 1504 htole32(EXTSTS_VPKT | 1505 (bswap16(vlan_get_tag(m0)) & 1506 EXTSTS_VTCI)); 1507 } 1508 1509 /* 1510 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1511 * checksumming, set up the descriptor to do this work 1512 * for us. 1513 * 1514 * This apparently has to be on the first descriptor of 1515 * the packet. 1516 * 1517 * Byte-swap constants so the compiler can optimize. 1518 */ 1519 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1520 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1521 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1522 extsts |= htole32(EXTSTS_IPPKT); 1523 } 1524 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1525 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1526 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1527 extsts |= htole32(EXTSTS_TCPPKT); 1528 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1529 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1530 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1531 extsts |= htole32(EXTSTS_UDPPKT); 1532 } 1533 sc->sc_txdescs[sc->sc_txnext].sipd_words[sc->sc_extsts_idx] |= extsts; 1534 } 1535 1536 /* 1537 * sip_start: [ifnet interface function] 1538 * 1539 * Start packet transmission on the interface. 1540 */ 1541 static void 1542 sipcom_start(struct ifnet *ifp) 1543 { 1544 struct sip_softc *sc = ifp->if_softc; 1545 struct mbuf *m0; 1546 struct mbuf *m; 1547 struct sip_txsoft *txs; 1548 bus_dmamap_t dmamap; 1549 int error, nexttx, lasttx, seg; 1550 int ofree = sc->sc_txfree; 1551 uint32_t cmdsts; 1552 #if 0 1553 int firsttx = sc->sc_txnext; 1554 #endif 1555 1556 /* 1557 * If we've been told to pause, don't transmit any more packets. 1558 */ 1559 if (!sc->sc_gigabit && sc->sc_paused) 1560 return; 1561 1562 if ((ifp->if_flags & IFF_RUNNING) != IFF_RUNNING) 1563 return; 1564 1565 /* 1566 * Loop through the send queue, setting up transmit descriptors 1567 * until we drain the queue, or use up all available transmit 1568 * descriptors. 1569 */ 1570 for (;;) { 1571 /* Get a work queue entry. */ 1572 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1573 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1574 break; 1575 } 1576 1577 /* 1578 * Grab a packet off the queue. 1579 */ 1580 IFQ_POLL(&ifp->if_snd, m0); 1581 if (m0 == NULL) 1582 break; 1583 m = NULL; 1584 1585 dmamap = txs->txs_dmamap; 1586 1587 /* 1588 * Load the DMA map. If this fails, the packet either 1589 * didn't fit in the alloted number of segments, or we 1590 * were short on resources. 1591 */ 1592 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1593 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1594 /* In the non-gigabit case, we'll copy and try again. */ 1595 if (error != 0 && !sc->sc_gigabit) { 1596 MGETHDR(m, M_DONTWAIT, MT_DATA); 1597 if (m == NULL) { 1598 printf("%s: unable to allocate Tx mbuf\n", 1599 device_xname(sc->sc_dev)); 1600 break; 1601 } 1602 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1603 if (m0->m_pkthdr.len > MHLEN) { 1604 MCLGET(m, M_DONTWAIT); 1605 if ((m->m_flags & M_EXT) == 0) { 1606 printf("%s: unable to allocate Tx " 1607 "cluster\n", 1608 device_xname(sc->sc_dev)); 1609 m_freem(m); 1610 break; 1611 } 1612 } 1613 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1614 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1615 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1616 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1617 if (error) { 1618 printf("%s: unable to load Tx buffer, error = " 1619 "%d\n", device_xname(sc->sc_dev), error); 1620 break; 1621 } 1622 } else if (error == EFBIG) { 1623 /* 1624 * For the too-many-segments case, we simply 1625 * report an error and drop the packet, 1626 * since we can't sanely copy a jumbo packet 1627 * to a single buffer. 1628 */ 1629 printf("%s: Tx packet consumes too many DMA segments, " 1630 "dropping...\n", device_xname(sc->sc_dev)); 1631 IFQ_DEQUEUE(&ifp->if_snd, m0); 1632 m_freem(m0); 1633 continue; 1634 } else if (error != 0) { 1635 /* 1636 * Short on resources, just stop for now. 1637 */ 1638 break; 1639 } 1640 1641 /* 1642 * Ensure we have enough descriptors free to describe 1643 * the packet. Note, we always reserve one descriptor 1644 * at the end of the ring as a termination point, to 1645 * prevent wrap-around. 1646 */ 1647 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1648 /* 1649 * Not enough free descriptors to transmit this 1650 * packet. 1651 */ 1652 bus_dmamap_unload(sc->sc_dmat, dmamap); 1653 if (m != NULL) 1654 m_freem(m); 1655 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1656 break; 1657 } 1658 1659 IFQ_DEQUEUE(&ifp->if_snd, m0); 1660 if (m != NULL) { 1661 m_freem(m0); 1662 m0 = m; 1663 } 1664 1665 /* 1666 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1667 */ 1668 1669 /* Sync the DMA map. */ 1670 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1671 BUS_DMASYNC_PREWRITE); 1672 1673 /* 1674 * Initialize the transmit descriptors. 1675 */ 1676 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1677 seg < dmamap->dm_nsegs; 1678 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1679 /* 1680 * If this is the first descriptor we're 1681 * enqueueing, don't set the OWN bit just 1682 * yet. That could cause a race condition. 1683 * We'll do it below. 1684 */ 1685 1686 cmdsts = dmamap->dm_segs[seg].ds_len; 1687 if (nexttx != sc->sc_txnext) 1688 cmdsts |= CMDSTS_OWN; 1689 if (seg < dmamap->dm_nsegs - 1) 1690 cmdsts |= CMDSTS_MORE; 1691 sip_init_txdesc(sc, nexttx, 1692 dmamap->dm_segs[seg].ds_addr, cmdsts); 1693 lasttx = nexttx; 1694 } 1695 1696 /* 1697 * If we're in the interrupt delay window, delay the 1698 * interrupt. 1699 */ 1700 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1701 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1702 sc->sc_txdescs[lasttx].sipd_words[sc->sc_cmdsts_idx] |= 1703 htole32(CMDSTS_INTR); 1704 sc->sc_txwin = 0; 1705 } 1706 1707 if (sc->sc_gigabit) 1708 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1709 1710 /* Sync the descriptors we're using. */ 1711 sip_cdtxsync(sc, sc->sc_txnext, dmamap->dm_nsegs, 1712 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1713 1714 /* 1715 * The entire packet is set up. Give the first descrptor 1716 * to the chip now. 1717 */ 1718 sc->sc_txdescs[sc->sc_txnext].sipd_words[sc->sc_cmdsts_idx] |= 1719 htole32(CMDSTS_OWN); 1720 sip_cdtxsync(sc, sc->sc_txnext, 1, 1721 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1722 1723 /* 1724 * Store a pointer to the packet so we can free it later, 1725 * and remember what txdirty will be once the packet is 1726 * done. 1727 */ 1728 txs->txs_mbuf = m0; 1729 txs->txs_firstdesc = sc->sc_txnext; 1730 txs->txs_lastdesc = lasttx; 1731 1732 /* Advance the tx pointer. */ 1733 sc->sc_txfree -= dmamap->dm_nsegs; 1734 sc->sc_txnext = nexttx; 1735 1736 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1737 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1738 1739 /* Pass the packet to any BPF listeners. */ 1740 bpf_mtap(ifp, m0, BPF_D_OUT); 1741 } 1742 1743 if (sc->sc_txfree != ofree) { 1744 /* 1745 * Start the transmit process. Note, the manual says 1746 * that if there are no pending transmissions in the 1747 * chip's internal queue (indicated by TXE being clear), 1748 * then the driver software must set the TXDP to the 1749 * first descriptor to be transmitted. However, if we 1750 * do this, it causes serious performance degredation on 1751 * the DP83820 under load, not setting TXDP doesn't seem 1752 * to adversely affect the SiS 900 or DP83815. 1753 * 1754 * Well, I guess it wouldn't be the first time a manual 1755 * has lied -- and they could be speaking of the NULL- 1756 * terminated descriptor list case, rather than OWN- 1757 * terminated rings. 1758 */ 1759 #if 0 1760 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1761 CR_TXE) == 0) { 1762 sip_set_txdp(sc, SIP_CDTXADDR(sc, firsttx)); 1763 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1764 } 1765 #else 1766 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1767 #endif 1768 1769 /* Set a watchdog timer in case the chip flakes out. */ 1770 /* Gigabit autonegotiation takes 5 seconds. */ 1771 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1772 } 1773 } 1774 1775 /* 1776 * sip_watchdog: [ifnet interface function] 1777 * 1778 * Watchdog timer handler. 1779 */ 1780 static void 1781 sipcom_watchdog(struct ifnet *ifp) 1782 { 1783 struct sip_softc *sc = ifp->if_softc; 1784 1785 /* 1786 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1787 * If we get a timeout, try and sweep up transmit descriptors. 1788 * If we manage to sweep them all up, ignore the lack of 1789 * interrupt. 1790 */ 1791 sipcom_txintr(sc); 1792 1793 if (sc->sc_txfree != sc->sc_ntxdesc) { 1794 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1795 if_statinc(ifp, if_oerrors); 1796 1797 /* Reset the interface. */ 1798 (void) sipcom_init(ifp); 1799 } else if (ifp->if_flags & IFF_DEBUG) 1800 printf("%s: recovered from device timeout\n", 1801 device_xname(sc->sc_dev)); 1802 1803 /* Try to get more packets going. */ 1804 sipcom_start(ifp); 1805 } 1806 1807 /* If the interface is up and running, only modify the receive 1808 * filter when setting promiscuous or debug mode. Otherwise fall 1809 * through to ether_ioctl, which will reset the chip. 1810 */ 1811 static int 1812 sip_ifflags_cb(struct ethercom *ec) 1813 { 1814 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1815 == (sc)->sc_ethercom.ec_capenable) \ 1816 && ((sc)->sc_prev.is_vlan == \ 1817 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1818 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1819 struct ifnet *ifp = &ec->ec_if; 1820 struct sip_softc *sc = ifp->if_softc; 1821 u_short change = ifp->if_flags ^ sc->sc_if_flags; 1822 1823 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0 || !COMPARE_EC(sc) || 1824 !COMPARE_IC(sc, ifp)) 1825 return ENETRESET; 1826 /* Set up the receive filter. */ 1827 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1828 return 0; 1829 } 1830 1831 /* 1832 * sip_ioctl: [ifnet interface function] 1833 * 1834 * Handle control requests from the operator. 1835 */ 1836 static int 1837 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1838 { 1839 struct sip_softc *sc = ifp->if_softc; 1840 struct ifreq *ifr = (struct ifreq *)data; 1841 int s, error; 1842 1843 s = splnet(); 1844 1845 switch (cmd) { 1846 case SIOCSIFMEDIA: 1847 /* Flow control requires full-duplex mode. */ 1848 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1849 (ifr->ifr_media & IFM_FDX) == 0) 1850 ifr->ifr_media &= ~IFM_ETH_FMASK; 1851 1852 /* XXX */ 1853 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1854 ifr->ifr_media &= ~IFM_ETH_FMASK; 1855 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1856 if (sc->sc_gigabit && 1857 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1858 /* We can do both TXPAUSE and RXPAUSE. */ 1859 ifr->ifr_media |= 1860 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1861 } else if (ifr->ifr_media & IFM_FLOW) { 1862 /* 1863 * Both TXPAUSE and RXPAUSE must be set. 1864 * (SiS900 and DP83815 don't have PAUSE_ASYM 1865 * feature.) 1866 * 1867 * XXX Can SiS900 and DP83815 send PAUSE? 1868 */ 1869 ifr->ifr_media |= 1870 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1871 } 1872 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1873 } 1874 /*FALLTHROUGH*/ 1875 default: 1876 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1877 break; 1878 1879 error = 0; 1880 1881 if (cmd == SIOCSIFCAP) 1882 error = (*ifp->if_init)(ifp); 1883 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1884 ; 1885 else if (ifp->if_flags & IFF_RUNNING) { 1886 /* 1887 * Multicast list has changed; set the hardware filter 1888 * accordingly. 1889 */ 1890 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1891 } 1892 break; 1893 } 1894 1895 /* Try to get more packets going. */ 1896 sipcom_start(ifp); 1897 1898 sc->sc_if_flags = ifp->if_flags; 1899 splx(s); 1900 return error; 1901 } 1902 1903 /* 1904 * sip_intr: 1905 * 1906 * Interrupt service routine. 1907 */ 1908 static int 1909 sipcom_intr(void *arg) 1910 { 1911 struct sip_softc *sc = arg; 1912 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1913 uint32_t isr; 1914 int handled = 0; 1915 1916 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 1917 return 0; 1918 1919 /* Disable interrupts. */ 1920 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1921 1922 for (;;) { 1923 /* Reading clears interrupt. */ 1924 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1925 if ((isr & sc->sc_imr) == 0) 1926 break; 1927 1928 rnd_add_uint32(&sc->rnd_source, isr); 1929 1930 handled = 1; 1931 1932 if ((ifp->if_flags & IFF_RUNNING) == 0) 1933 break; 1934 1935 if (isr & (ISR_RXORN | ISR_RXIDLE | ISR_RXDESC)) { 1936 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1937 1938 /* Grab any new packets. */ 1939 (*sc->sc_rxintr)(sc); 1940 1941 if (isr & ISR_RXORN) { 1942 printf("%s: receive FIFO overrun\n", 1943 device_xname(sc->sc_dev)); 1944 1945 /* XXX adjust rx_drain_thresh? */ 1946 } 1947 1948 if (isr & ISR_RXIDLE) { 1949 printf("%s: receive ring overrun\n", 1950 device_xname(sc->sc_dev)); 1951 1952 /* Get the receive process going again. */ 1953 sip_set_rxdp(sc, 1954 SIP_CDRXADDR(sc, sc->sc_rxptr)); 1955 bus_space_write_4(sc->sc_st, sc->sc_sh, 1956 SIP_CR, CR_RXE); 1957 } 1958 } 1959 1960 if (isr & (ISR_TXURN | ISR_TXDESC | ISR_TXIDLE)) { 1961 #ifdef SIP_EVENT_COUNTERS 1962 if (isr & ISR_TXDESC) 1963 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1964 else if (isr & ISR_TXIDLE) 1965 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1966 #endif 1967 1968 /* Sweep up transmit descriptors. */ 1969 sipcom_txintr(sc); 1970 1971 if (isr & ISR_TXURN) { 1972 uint32_t thresh; 1973 int txfifo_size = (sc->sc_gigabit) 1974 ? DP83820_SIP_TXFIFO_SIZE 1975 : OTHER_SIP_TXFIFO_SIZE; 1976 1977 printf("%s: transmit FIFO underrun", 1978 device_xname(sc->sc_dev)); 1979 thresh = sc->sc_tx_drain_thresh + 1; 1980 if (thresh <= __SHIFTOUT_MASK(sc->sc_bits.b_txcfg_drth_mask) 1981 && (thresh * 32) <= (txfifo_size - 1982 (sc->sc_tx_fill_thresh * 32))) { 1983 printf("; increasing Tx drain " 1984 "threshold to %u bytes\n", 1985 thresh * 32); 1986 sc->sc_tx_drain_thresh = thresh; 1987 (void) sipcom_init(ifp); 1988 } else { 1989 (void) sipcom_init(ifp); 1990 printf("\n"); 1991 } 1992 } 1993 } 1994 1995 if (sc->sc_imr & (ISR_PAUSE_END | ISR_PAUSE_ST)) { 1996 if (isr & ISR_PAUSE_ST) { 1997 sc->sc_paused = 1; 1998 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1999 } 2000 if (isr & ISR_PAUSE_END) { 2001 sc->sc_paused = 0; 2002 } 2003 } 2004 2005 if (isr & ISR_HIBERR) { 2006 int want_init = 0; 2007 2008 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 2009 2010 #define PRINTERR(bit, str) \ 2011 do { \ 2012 if ((isr & (bit)) != 0) { \ 2013 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 2014 printf("%s: %s\n", \ 2015 device_xname(sc->sc_dev), str); \ 2016 want_init = 1; \ 2017 } \ 2018 } while (/*CONSTCOND*/0) 2019 2020 PRINTERR(sc->sc_bits.b_isr_dperr, "parity error"); 2021 PRINTERR(sc->sc_bits.b_isr_sserr, "system error"); 2022 PRINTERR(sc->sc_bits.b_isr_rmabt, "master abort"); 2023 PRINTERR(sc->sc_bits.b_isr_rtabt, "target abort"); 2024 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 2025 /* 2026 * Ignore: 2027 * Tx reset complete 2028 * Rx reset complete 2029 */ 2030 if (want_init) 2031 (void) sipcom_init(ifp); 2032 #undef PRINTERR 2033 } 2034 } 2035 2036 /* Re-enable interrupts. */ 2037 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 2038 2039 /* Try to get more packets going. */ 2040 if_schedule_deferred_start(ifp); 2041 2042 return handled; 2043 } 2044 2045 /* 2046 * sip_txintr: 2047 * 2048 * Helper; handle transmit interrupts. 2049 */ 2050 static void 2051 sipcom_txintr(struct sip_softc *sc) 2052 { 2053 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2054 struct sip_txsoft *txs; 2055 uint32_t cmdsts; 2056 2057 /* 2058 * Go through our Tx list and free mbufs for those 2059 * frames which have been transmitted. 2060 */ 2061 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2062 sip_cdtxsync(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 2063 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2064 2065 cmdsts = le32toh(sc->sc_txdescs[ 2066 txs->txs_lastdesc].sipd_words[sc->sc_cmdsts_idx]); 2067 if (cmdsts & CMDSTS_OWN) 2068 break; 2069 2070 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2071 2072 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 2073 2074 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2075 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2076 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2077 m_freem(txs->txs_mbuf); 2078 txs->txs_mbuf = NULL; 2079 2080 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2081 2082 /* Check for errors and collisions. */ 2083 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 2084 if (cmdsts & (CMDSTS_Tx_TXA | CMDSTS_Tx_TFU | CMDSTS_Tx_ED | 2085 CMDSTS_Tx_EC)) { 2086 if_statinc_ref(nsr, if_oerrors); 2087 if (cmdsts & CMDSTS_Tx_EC) 2088 if_statadd_ref(nsr, if_collisions, 16); 2089 if (ifp->if_flags & IFF_DEBUG) { 2090 if (cmdsts & CMDSTS_Tx_ED) 2091 printf("%s: excessive deferral\n", 2092 device_xname(sc->sc_dev)); 2093 if (cmdsts & CMDSTS_Tx_EC) 2094 printf("%s: excessive collisions\n", 2095 device_xname(sc->sc_dev)); 2096 } 2097 } else { 2098 /* Packet was transmitted successfully. */ 2099 if_statinc_ref(nsr, if_opackets); 2100 if (CMDSTS_COLLISIONS(cmdsts)) 2101 if_statadd_ref(nsr, if_collisions, 2102 CMDSTS_COLLISIONS(cmdsts)); 2103 } 2104 IF_STAT_PUTREF(ifp); 2105 } 2106 2107 /* 2108 * If there are no more pending transmissions, cancel the watchdog 2109 * timer. 2110 */ 2111 if (txs == NULL) { 2112 ifp->if_timer = 0; 2113 sc->sc_txwin = 0; 2114 } 2115 } 2116 2117 /* 2118 * gsip_rxintr: 2119 * 2120 * Helper; handle receive interrupts on gigabit parts. 2121 */ 2122 static void 2123 gsip_rxintr(struct sip_softc *sc) 2124 { 2125 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2126 struct sip_rxsoft *rxs; 2127 struct mbuf *m; 2128 uint32_t cmdsts, extsts; 2129 int i, len; 2130 2131 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2132 rxs = &sc->sc_rxsoft[i]; 2133 2134 sip_cdrxsync(sc, i, 2135 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2136 2137 cmdsts = 2138 le32toh(sc->sc_rxdescs[i].sipd_words[sc->sc_cmdsts_idx]); 2139 extsts = 2140 le32toh(sc->sc_rxdescs[i].sipd_words[sc->sc_extsts_idx]); 2141 len = CMDSTS_SIZE(sc, cmdsts); 2142 2143 /* 2144 * NOTE: OWN is set if owned by _consumer_. We're the 2145 * consumer of the receive ring, so if the bit is clear, 2146 * we have processed all of the packets. 2147 */ 2148 if ((cmdsts & CMDSTS_OWN) == 0) { 2149 /* 2150 * We have processed all of the receive buffers. 2151 */ 2152 break; 2153 } 2154 2155 if (__predict_false(sc->sc_rxdiscard)) { 2156 sip_init_rxdesc(sc, i); 2157 if ((cmdsts & CMDSTS_MORE) == 0) { 2158 /* Reset our state. */ 2159 sc->sc_rxdiscard = 0; 2160 } 2161 continue; 2162 } 2163 2164 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2165 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2166 2167 m = rxs->rxs_mbuf; 2168 2169 /* 2170 * Add a new receive buffer to the ring. 2171 */ 2172 if (sipcom_add_rxbuf(sc, i) != 0) { 2173 /* 2174 * Failed, throw away what we've done so 2175 * far, and discard the rest of the packet. 2176 */ 2177 if_statinc(ifp, if_ierrors); 2178 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2179 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2180 sip_init_rxdesc(sc, i); 2181 if (cmdsts & CMDSTS_MORE) 2182 sc->sc_rxdiscard = 1; 2183 if (sc->sc_rxhead != NULL) 2184 m_freem(sc->sc_rxhead); 2185 sip_rxchain_reset(sc); 2186 continue; 2187 } 2188 2189 sip_rxchain_link(sc, m); 2190 2191 m->m_len = len; 2192 2193 /* 2194 * If this is not the end of the packet, keep 2195 * looking. 2196 */ 2197 if (cmdsts & CMDSTS_MORE) { 2198 sc->sc_rxlen += len; 2199 continue; 2200 } 2201 2202 /* 2203 * Okay, we have the entire packet now. The chip includes 2204 * the FCS, so we need to trim it. 2205 */ 2206 m->m_len -= ETHER_CRC_LEN; 2207 2208 *sc->sc_rxtailp = NULL; 2209 len = m->m_len + sc->sc_rxlen; 2210 m = sc->sc_rxhead; 2211 2212 sip_rxchain_reset(sc); 2213 2214 /* If an error occurred, update stats and drop the packet. */ 2215 if (cmdsts & (CMDSTS_Rx_RXA | CMDSTS_Rx_RUNT | 2216 CMDSTS_Rx_ISE | CMDSTS_Rx_CRCE | CMDSTS_Rx_FAE)) { 2217 if_statinc(ifp, if_ierrors); 2218 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2219 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2220 /* Receive overrun handled elsewhere. */ 2221 printf("%s: receive descriptor error\n", 2222 device_xname(sc->sc_dev)); 2223 } 2224 #define PRINTERR(bit, str) \ 2225 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2226 (cmdsts & (bit)) != 0) \ 2227 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2228 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2229 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2230 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2231 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2232 #undef PRINTERR 2233 m_freem(m); 2234 continue; 2235 } 2236 2237 /* 2238 * If the packet is small enough to fit in a 2239 * single header mbuf, allocate one and copy 2240 * the data into it. This greatly reduces 2241 * memory consumption when we receive lots 2242 * of small packets. 2243 */ 2244 if (gsip_copy_small != 0 && len <= (MHLEN - 2)) { 2245 struct mbuf *nm; 2246 MGETHDR(nm, M_DONTWAIT, MT_DATA); 2247 if (nm == NULL) { 2248 if_statinc(ifp, if_ierrors); 2249 m_freem(m); 2250 continue; 2251 } 2252 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2253 nm->m_data += 2; 2254 nm->m_pkthdr.len = nm->m_len = len; 2255 m_copydata(m, 0, len, mtod(nm, void *)); 2256 m_freem(m); 2257 m = nm; 2258 } 2259 #ifndef __NO_STRICT_ALIGNMENT 2260 else { 2261 /* 2262 * The DP83820's receive buffers must be 4-byte 2263 * aligned. But this means that the data after 2264 * the Ethernet header is misaligned. To compensate, 2265 * we have artificially shortened the buffer size 2266 * in the descriptor, and we do an overlapping copy 2267 * of the data two bytes further in (in the first 2268 * buffer of the chain only). 2269 */ 2270 memmove(mtod(m, char *) + 2, mtod(m, void *), 2271 m->m_len); 2272 m->m_data += 2; 2273 } 2274 #endif /* ! __NO_STRICT_ALIGNMENT */ 2275 2276 /* 2277 * If VLANs are enabled, VLAN packets have been unwrapped 2278 * for us. Associate the tag with the packet. 2279 */ 2280 2281 /* 2282 * Again, byte swapping is tricky. Hardware provided 2283 * the tag in the network byte order, but extsts was 2284 * passed through le32toh() in the meantime. On a 2285 * big-endian machine, we need to swap it again. On a 2286 * little-endian machine, we need to convert from the 2287 * network to host byte order. This means that we must 2288 * swap it in any case, so unconditional swap instead 2289 * of htons() is used. 2290 */ 2291 if ((extsts & EXTSTS_VPKT) != 0) { 2292 vlan_set_tag(m, bswap16(extsts & EXTSTS_VTCI)); 2293 } 2294 2295 /* 2296 * Set the incoming checksum information for the 2297 * packet. 2298 */ 2299 if ((extsts & EXTSTS_IPPKT) != 0) { 2300 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2301 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2302 if (extsts & EXTSTS_Rx_IPERR) 2303 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2304 if (extsts & EXTSTS_TCPPKT) { 2305 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2306 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2307 if (extsts & EXTSTS_Rx_TCPERR) 2308 m->m_pkthdr.csum_flags |= 2309 M_CSUM_TCP_UDP_BAD; 2310 } else if (extsts & EXTSTS_UDPPKT) { 2311 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2312 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2313 if (extsts & EXTSTS_Rx_UDPERR) 2314 m->m_pkthdr.csum_flags |= 2315 M_CSUM_TCP_UDP_BAD; 2316 } 2317 } 2318 2319 m_set_rcvif(m, ifp); 2320 m->m_pkthdr.len = len; 2321 2322 /* Pass it on. */ 2323 if_percpuq_enqueue(ifp->if_percpuq, m); 2324 } 2325 2326 /* Update the receive pointer. */ 2327 sc->sc_rxptr = i; 2328 } 2329 2330 /* 2331 * sip_rxintr: 2332 * 2333 * Helper; handle receive interrupts on 10/100 parts. 2334 */ 2335 static void 2336 sip_rxintr(struct sip_softc *sc) 2337 { 2338 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2339 struct sip_rxsoft *rxs; 2340 struct mbuf *m; 2341 uint32_t cmdsts; 2342 int i, len; 2343 2344 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2345 rxs = &sc->sc_rxsoft[i]; 2346 2347 sip_cdrxsync(sc, i, 2348 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2349 2350 cmdsts = 2351 le32toh(sc->sc_rxdescs[i].sipd_words[sc->sc_cmdsts_idx]); 2352 2353 /* 2354 * NOTE: OWN is set if owned by _consumer_. We're the 2355 * consumer of the receive ring, so if the bit is clear, 2356 * we have processed all of the packets. 2357 */ 2358 if ((cmdsts & CMDSTS_OWN) == 0) { 2359 /* 2360 * We have processed all of the receive buffers. 2361 */ 2362 break; 2363 } 2364 2365 /* If any collisions were seen on the wire, count one. */ 2366 if (cmdsts & CMDSTS_Rx_COL) 2367 if_statinc(ifp, if_collisions); 2368 2369 /* 2370 * If an error occurred, update stats, clear the status 2371 * word, and leave the packet buffer in place. It will 2372 * simply be reused the next time the ring comes around. 2373 */ 2374 if (cmdsts & (CMDSTS_Rx_RXA | CMDSTS_Rx_RUNT | 2375 CMDSTS_Rx_ISE | CMDSTS_Rx_CRCE | CMDSTS_Rx_FAE)) { 2376 if_statinc(ifp, if_ierrors); 2377 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2378 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2379 /* Receive overrun handled elsewhere. */ 2380 printf("%s: receive descriptor error\n", 2381 device_xname(sc->sc_dev)); 2382 } 2383 #define PRINTERR(bit, str) \ 2384 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2385 (cmdsts & (bit)) != 0) \ 2386 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2387 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2388 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2389 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2390 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2391 #undef PRINTERR 2392 sip_init_rxdesc(sc, i); 2393 continue; 2394 } 2395 2396 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2397 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2398 2399 /* 2400 * No errors; receive the packet. Note, the SiS 900 2401 * includes the CRC with every packet. 2402 */ 2403 len = CMDSTS_SIZE(sc, cmdsts) - ETHER_CRC_LEN; 2404 2405 #ifdef __NO_STRICT_ALIGNMENT 2406 /* 2407 * If the packet is small enough to fit in a 2408 * single header mbuf, allocate one and copy 2409 * the data into it. This greatly reduces 2410 * memory consumption when we receive lots 2411 * of small packets. 2412 * 2413 * Otherwise, we add a new buffer to the receive 2414 * chain. If this fails, we drop the packet and 2415 * recycle the old buffer. 2416 */ 2417 if (sip_copy_small != 0 && len <= MHLEN) { 2418 MGETHDR(m, M_DONTWAIT, MT_DATA); 2419 if (m == NULL) 2420 goto dropit; 2421 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2422 memcpy(mtod(m, void *), 2423 mtod(rxs->rxs_mbuf, void *), len); 2424 sip_init_rxdesc(sc, i); 2425 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2426 rxs->rxs_dmamap->dm_mapsize, 2427 BUS_DMASYNC_PREREAD); 2428 } else { 2429 m = rxs->rxs_mbuf; 2430 if (sipcom_add_rxbuf(sc, i) != 0) { 2431 dropit: 2432 if_statinc(ifp, if_ierrors); 2433 sip_init_rxdesc(sc, i); 2434 bus_dmamap_sync(sc->sc_dmat, 2435 rxs->rxs_dmamap, 0, 2436 rxs->rxs_dmamap->dm_mapsize, 2437 BUS_DMASYNC_PREREAD); 2438 continue; 2439 } 2440 } 2441 #else 2442 /* 2443 * The SiS 900's receive buffers must be 4-byte aligned. 2444 * But this means that the data after the Ethernet header 2445 * is misaligned. We must allocate a new buffer and 2446 * copy the data, shifted forward 2 bytes. 2447 */ 2448 MGETHDR(m, M_DONTWAIT, MT_DATA); 2449 if (m == NULL) { 2450 dropit: 2451 if_statinc(ifp, if_ierrors); 2452 sip_init_rxdesc(sc, i); 2453 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2454 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2455 continue; 2456 } 2457 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2458 if (len > (MHLEN - 2)) { 2459 MCLGET(m, M_DONTWAIT); 2460 if ((m->m_flags & M_EXT) == 0) { 2461 m_freem(m); 2462 goto dropit; 2463 } 2464 } 2465 m->m_data += 2; 2466 2467 /* 2468 * Note that we use clusters for incoming frames, so the 2469 * buffer is virtually contiguous. 2470 */ 2471 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2472 2473 /* Allow the receive descriptor to continue using its mbuf. */ 2474 sip_init_rxdesc(sc, i); 2475 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2476 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2477 #endif /* __NO_STRICT_ALIGNMENT */ 2478 2479 m_set_rcvif(m, ifp); 2480 m->m_pkthdr.len = m->m_len = len; 2481 2482 /* Pass it on. */ 2483 if_percpuq_enqueue(ifp->if_percpuq, m); 2484 } 2485 2486 /* Update the receive pointer. */ 2487 sc->sc_rxptr = i; 2488 } 2489 2490 /* 2491 * sip_tick: 2492 * 2493 * One second timer, used to tick the MII. 2494 */ 2495 static void 2496 sipcom_tick(void *arg) 2497 { 2498 struct sip_softc *sc = arg; 2499 int s; 2500 2501 s = splnet(); 2502 #ifdef SIP_EVENT_COUNTERS 2503 if (sc->sc_gigabit) { 2504 /* Read PAUSE related counts from MIB registers. */ 2505 sc->sc_ev_rxpause.ev_count += 2506 bus_space_read_4(sc->sc_st, sc->sc_sh, 2507 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2508 sc->sc_ev_txpause.ev_count += 2509 bus_space_read_4(sc->sc_st, sc->sc_sh, 2510 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2511 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2512 } 2513 #endif /* SIP_EVENT_COUNTERS */ 2514 mii_tick(&sc->sc_mii); 2515 splx(s); 2516 2517 callout_schedule(&sc->sc_tick_ch, hz); 2518 } 2519 2520 /* 2521 * sip_reset: 2522 * 2523 * Perform a soft reset on the SiS 900. 2524 */ 2525 static bool 2526 sipcom_reset(struct sip_softc *sc) 2527 { 2528 bus_space_tag_t st = sc->sc_st; 2529 bus_space_handle_t sh = sc->sc_sh; 2530 int i; 2531 2532 bus_space_write_4(st, sh, SIP_IER, 0); 2533 bus_space_write_4(st, sh, SIP_IMR, 0); 2534 bus_space_write_4(st, sh, SIP_RFCR, 0); 2535 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2536 2537 for (i = 0; i < SIP_TIMEOUT; i++) { 2538 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2539 break; 2540 delay(2); 2541 } 2542 2543 if (i == SIP_TIMEOUT) { 2544 printf("%s: reset failed to complete\n", 2545 device_xname(sc->sc_dev)); 2546 return false; 2547 } 2548 2549 delay(1000); 2550 2551 if (sc->sc_gigabit) { 2552 /* 2553 * Set the general purpose I/O bits. Do it here in case we 2554 * need to have GPIO set up to talk to the media interface. 2555 */ 2556 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2557 delay(1000); 2558 } 2559 return true; 2560 } 2561 2562 static void 2563 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2564 { 2565 uint32_t reg; 2566 bus_space_tag_t st = sc->sc_st; 2567 bus_space_handle_t sh = sc->sc_sh; 2568 /* 2569 * Initialize the VLAN/IP receive control register. 2570 * We enable checksum computation on all incoming 2571 * packets, and do not reject packets w/ bad checksums. 2572 */ 2573 reg = 0; 2574 if (capenable & 2575 (IFCAP_CSUM_IPv4_Rx | IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 2576 reg |= VRCR_IPEN; 2577 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2578 reg |= VRCR_VTDEN | VRCR_VTREN; 2579 bus_space_write_4(st, sh, SIP_VRCR, reg); 2580 2581 /* 2582 * Initialize the VLAN/IP transmit control register. 2583 * We enable outgoing checksum computation on a 2584 * per-packet basis. 2585 */ 2586 reg = 0; 2587 if (capenable & 2588 (IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx)) 2589 reg |= VTCR_PPCHK; 2590 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2591 reg |= VTCR_VPPTI; 2592 bus_space_write_4(st, sh, SIP_VTCR, reg); 2593 2594 /* 2595 * If we're using VLANs, initialize the VLAN data register. 2596 * To understand why we bswap the VLAN Ethertype, see section 2597 * 4.2.36 of the DP83820 manual. 2598 */ 2599 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2600 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2601 } 2602 2603 /* 2604 * sip_init: [ ifnet interface function ] 2605 * 2606 * Initialize the interface. Must be called at splnet(). 2607 */ 2608 static int 2609 sipcom_init(struct ifnet *ifp) 2610 { 2611 struct sip_softc *sc = ifp->if_softc; 2612 bus_space_tag_t st = sc->sc_st; 2613 bus_space_handle_t sh = sc->sc_sh; 2614 struct sip_txsoft *txs; 2615 struct sip_rxsoft *rxs; 2616 int i, error = 0; 2617 2618 if (device_is_active(sc->sc_dev)) { 2619 /* 2620 * Cancel any pending I/O. 2621 */ 2622 sipcom_stop(ifp, 0); 2623 } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 2624 !device_is_active(sc->sc_dev)) 2625 return 0; 2626 2627 /* 2628 * Reset the chip to a known state. 2629 */ 2630 if (!sipcom_reset(sc)) 2631 return EBUSY; 2632 2633 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2634 /* 2635 * DP83815 manual, page 78: 2636 * 4.4 Recommended Registers Configuration 2637 * For optimum performance of the DP83815, version noted 2638 * as DP83815CVNG (SRR = 203h), the listed register 2639 * modifications must be followed in sequence... 2640 * 2641 * It's not clear if this should be 302h or 203h because that 2642 * chip name is listed as SRR 302h in the description of the 2643 * SRR register. However, my revision 302h DP83815 on the 2644 * Netgear FA311 purchased in 02/2001 needs these settings 2645 * to avoid tons of errors in AcceptPerfectMatch (non- 2646 * IFF_PROMISC) mode. I do not know if other revisions need 2647 * this set or not. [briggs -- 09 March 2001] 2648 * 2649 * Note that only the low-order 12 bits of 0xe4 are documented 2650 * and that this sets reserved bits in that register. 2651 */ 2652 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2653 2654 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2655 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2656 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2657 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2658 2659 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2660 } 2661 2662 /* Initialize the transmit descriptor ring. */ 2663 sip_init_txring(sc); 2664 2665 /* 2666 * Initialize the transmit job descriptors. 2667 */ 2668 SIMPLEQ_INIT(&sc->sc_txfreeq); 2669 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2670 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2671 txs = &sc->sc_txsoft[i]; 2672 txs->txs_mbuf = NULL; 2673 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2674 } 2675 2676 /* 2677 * Initialize the receive descriptor and receive job 2678 * descriptor rings. 2679 */ 2680 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2681 rxs = &sc->sc_rxsoft[i]; 2682 if (rxs->rxs_mbuf == NULL) { 2683 if ((error = sipcom_add_rxbuf(sc, i)) != 0) { 2684 printf("%s: unable to allocate or map rx " 2685 "buffer %d, error = %d\n", 2686 device_xname(sc->sc_dev), i, error); 2687 /* 2688 * XXX Should attempt to run with fewer receive 2689 * XXX buffers instead of just failing. 2690 */ 2691 sipcom_rxdrain(sc); 2692 goto out; 2693 } 2694 } else 2695 sip_init_rxdesc(sc, i); 2696 } 2697 sc->sc_rxptr = 0; 2698 sc->sc_rxdiscard = 0; 2699 sip_rxchain_reset(sc); 2700 2701 /* 2702 * Set the configuration register; it's already initialized 2703 * in sip_attach(). 2704 */ 2705 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2706 2707 /* 2708 * Initialize the prototype TXCFG register. 2709 */ 2710 if (sc->sc_gigabit) { 2711 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2712 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2713 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2714 SIP_SIS900_REV(sc, SIS_REV_960) || 2715 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2716 (sc->sc_cfg & CFG_EDBMASTEN)) { 2717 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_64; 2718 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_64; 2719 } else { 2720 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2721 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2722 } 2723 2724 sc->sc_txcfg |= TXCFG_ATP | 2725 __SHIFTIN(sc->sc_tx_fill_thresh, sc->sc_bits.b_txcfg_flth_mask) | 2726 sc->sc_tx_drain_thresh; 2727 bus_space_write_4(st, sh, sc->sc_regs.r_txcfg, sc->sc_txcfg); 2728 2729 /* 2730 * Initialize the receive drain threshold if we have never 2731 * done so. 2732 */ 2733 if (sc->sc_rx_drain_thresh == 0) { 2734 /* 2735 * XXX This value should be tuned. This is set to the 2736 * maximum of 248 bytes, and we may be able to improve 2737 * performance by decreasing it (although we should never 2738 * set this value lower than 2; 14 bytes are required to 2739 * filter the packet). 2740 */ 2741 sc->sc_rx_drain_thresh = __SHIFTOUT_MASK(RXCFG_DRTH_MASK); 2742 } 2743 2744 /* 2745 * Initialize the prototype RXCFG register. 2746 */ 2747 sc->sc_rxcfg |= __SHIFTIN(sc->sc_rx_drain_thresh, RXCFG_DRTH_MASK); 2748 /* 2749 * Accept long packets (including FCS) so we can handle 2750 * 802.1q-tagged frames and jumbo frames properly. 2751 */ 2752 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2753 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2754 sc->sc_rxcfg |= RXCFG_ALP; 2755 2756 /* 2757 * Checksum offloading is disabled if the user selects an MTU 2758 * larger than 8109. (FreeBSD says 8152, but there is emperical 2759 * evidence that >8109 does not work on some boards, such as the 2760 * Planex GN-1000TE). 2761 */ 2762 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2763 (ifp->if_capenable & 2764 (IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2765 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2766 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx))) { 2767 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2768 "disabled.\n", device_xname(sc->sc_dev)); 2769 ifp->if_capenable &= 2770 ~(IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2771 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2772 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx); 2773 ifp->if_csum_flags_tx = 0; 2774 ifp->if_csum_flags_rx = 0; 2775 } 2776 2777 bus_space_write_4(st, sh, sc->sc_regs.r_rxcfg, sc->sc_rxcfg); 2778 2779 if (sc->sc_gigabit) 2780 sipcom_dp83820_init(sc, ifp->if_capenable); 2781 2782 /* 2783 * Give the transmit and receive rings to the chip. 2784 */ 2785 sip_set_txdp(sc, SIP_CDTXADDR(sc, sc->sc_txnext)); 2786 sip_set_rxdp(sc, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2787 2788 /* 2789 * Initialize the interrupt mask. 2790 */ 2791 sc->sc_imr = sc->sc_bits.b_isr_dperr | 2792 sc->sc_bits.b_isr_sserr | 2793 sc->sc_bits.b_isr_rmabt | 2794 sc->sc_bits.b_isr_rtabt | 2795 ISR_RXSOVR | ISR_TXURN | ISR_TXDESC | ISR_TXIDLE | ISR_RXORN | 2796 ISR_RXIDLE | ISR_RXDESC; 2797 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2798 2799 /* Set up the receive filter. */ 2800 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2801 2802 /* 2803 * Tune sc_rx_flow_thresh. 2804 * XXX "More than 8KB" is too short for jumbo frames. 2805 * XXX TODO: Threshold value should be user-settable. 2806 */ 2807 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2808 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2809 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2810 2811 /* 2812 * Set the current media. Do this after initializing the prototype 2813 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2814 * control. 2815 */ 2816 if ((error = ether_mediachange(ifp)) != 0) 2817 goto out; 2818 2819 /* 2820 * Set the interrupt hold-off timer to 100us. 2821 */ 2822 if (sc->sc_gigabit) 2823 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2824 2825 /* 2826 * Enable interrupts. 2827 */ 2828 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2829 2830 /* 2831 * Start the transmit and receive processes. 2832 */ 2833 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2834 2835 /* 2836 * Start the one second MII clock. 2837 */ 2838 callout_schedule(&sc->sc_tick_ch, hz); 2839 2840 /* 2841 * ...all done! 2842 */ 2843 ifp->if_flags |= IFF_RUNNING; 2844 sc->sc_if_flags = ifp->if_flags; 2845 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2846 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2847 sc->sc_prev.if_capenable = ifp->if_capenable; 2848 2849 out: 2850 if (error) 2851 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 2852 return error; 2853 } 2854 2855 /* 2856 * sip_drain: 2857 * 2858 * Drain the receive queue. 2859 */ 2860 static void 2861 sipcom_rxdrain(struct sip_softc *sc) 2862 { 2863 struct sip_rxsoft *rxs; 2864 int i; 2865 2866 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2867 rxs = &sc->sc_rxsoft[i]; 2868 if (rxs->rxs_mbuf != NULL) { 2869 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2870 m_freem(rxs->rxs_mbuf); 2871 rxs->rxs_mbuf = NULL; 2872 } 2873 } 2874 } 2875 2876 /* 2877 * sip_stop: [ ifnet interface function ] 2878 * 2879 * Stop transmission on the interface. 2880 */ 2881 static void 2882 sipcom_stop(struct ifnet *ifp, int disable) 2883 { 2884 struct sip_softc *sc = ifp->if_softc; 2885 bus_space_tag_t st = sc->sc_st; 2886 bus_space_handle_t sh = sc->sc_sh; 2887 struct sip_txsoft *txs; 2888 uint32_t cmdsts = 0; /* DEBUG */ 2889 2890 /* 2891 * Stop the one second clock. 2892 */ 2893 callout_stop(&sc->sc_tick_ch); 2894 2895 /* Down the MII. */ 2896 mii_down(&sc->sc_mii); 2897 2898 if (device_is_active(sc->sc_dev)) { 2899 /* 2900 * Disable interrupts. 2901 */ 2902 bus_space_write_4(st, sh, SIP_IER, 0); 2903 2904 /* 2905 * Stop receiver and transmitter. 2906 */ 2907 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2908 } 2909 2910 /* 2911 * Release any queued transmit buffers. 2912 */ 2913 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2914 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2915 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2916 (sc->sc_txdescs[ 2917 txs->txs_lastdesc].sipd_words[ 2918 sc->sc_cmdsts_idx] & htole32(CMDSTS_INTR)) == 0) 2919 printf("%s: sip_stop: last descriptor does not " 2920 "have INTR bit set\n", device_xname(sc->sc_dev)); 2921 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2922 #ifdef DIAGNOSTIC 2923 if (txs->txs_mbuf == NULL) { 2924 printf("%s: dirty txsoft with no mbuf chain\n", 2925 device_xname(sc->sc_dev)); 2926 panic("sip_stop"); 2927 } 2928 #endif 2929 cmdsts |= /* DEBUG */ 2930 le32toh(sc->sc_txdescs[ 2931 txs->txs_lastdesc].sipd_words[sc->sc_cmdsts_idx]); 2932 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2933 m_freem(txs->txs_mbuf); 2934 txs->txs_mbuf = NULL; 2935 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2936 } 2937 2938 /* 2939 * Mark the interface down and cancel the watchdog timer. 2940 */ 2941 ifp->if_flags &= ~IFF_RUNNING; 2942 ifp->if_timer = 0; 2943 2944 if (disable) 2945 pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); 2946 2947 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2948 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2949 printf("%s: sip_stop: no INTR bits set in dirty tx " 2950 "descriptors\n", device_xname(sc->sc_dev)); 2951 } 2952 2953 /* 2954 * sip_read_eeprom: 2955 * 2956 * Read data from the serial EEPROM. 2957 */ 2958 static void 2959 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2960 uint16_t *data) 2961 { 2962 bus_space_tag_t st = sc->sc_st; 2963 bus_space_handle_t sh = sc->sc_sh; 2964 uint16_t reg; 2965 int i, x; 2966 2967 for (i = 0; i < wordcnt; i++) { 2968 /* Send CHIP SELECT. */ 2969 reg = EROMAR_EECS; 2970 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2971 2972 /* Shift in the READ opcode. */ 2973 for (x = 3; x > 0; x--) { 2974 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2975 reg |= EROMAR_EEDI; 2976 else 2977 reg &= ~EROMAR_EEDI; 2978 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2979 bus_space_write_4(st, sh, SIP_EROMAR, 2980 reg | EROMAR_EESK); 2981 delay(4); 2982 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2983 delay(4); 2984 } 2985 2986 /* Shift in address. */ 2987 for (x = 6; x > 0; x--) { 2988 if ((word + i) & (1 << (x - 1))) 2989 reg |= EROMAR_EEDI; 2990 else 2991 reg &= ~EROMAR_EEDI; 2992 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2993 bus_space_write_4(st, sh, SIP_EROMAR, 2994 reg | EROMAR_EESK); 2995 delay(4); 2996 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2997 delay(4); 2998 } 2999 3000 /* Shift out data. */ 3001 reg = EROMAR_EECS; 3002 data[i] = 0; 3003 for (x = 16; x > 0; x--) { 3004 bus_space_write_4(st, sh, SIP_EROMAR, 3005 reg | EROMAR_EESK); 3006 delay(4); 3007 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 3008 data[i] |= (1 << (x - 1)); 3009 bus_space_write_4(st, sh, SIP_EROMAR, reg); 3010 delay(4); 3011 } 3012 3013 /* Clear CHIP SELECT. */ 3014 bus_space_write_4(st, sh, SIP_EROMAR, 0); 3015 delay(4); 3016 } 3017 } 3018 3019 /* 3020 * sipcom_add_rxbuf: 3021 * 3022 * Add a receive buffer to the indicated descriptor. 3023 */ 3024 static int 3025 sipcom_add_rxbuf(struct sip_softc *sc, int idx) 3026 { 3027 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 3028 struct mbuf *m; 3029 int error; 3030 3031 MGETHDR(m, M_DONTWAIT, MT_DATA); 3032 if (m == NULL) 3033 return ENOBUFS; 3034 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 3035 3036 MCLGET(m, M_DONTWAIT); 3037 if ((m->m_flags & M_EXT) == 0) { 3038 m_freem(m); 3039 return ENOBUFS; 3040 } 3041 3042 /* XXX I don't believe this is necessary. --dyoung */ 3043 if (sc->sc_gigabit) 3044 m->m_len = sc->sc_parm->p_rxbuf_len; 3045 3046 if (rxs->rxs_mbuf != NULL) 3047 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3048 3049 rxs->rxs_mbuf = m; 3050 3051 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 3052 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 3053 BUS_DMA_READ | BUS_DMA_NOWAIT); 3054 if (error) { 3055 printf("%s: can't load rx DMA map %d, error = %d\n", 3056 device_xname(sc->sc_dev), idx, error); 3057 panic("%s", __func__); /* XXX */ 3058 } 3059 3060 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3061 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3062 3063 sip_init_rxdesc(sc, idx); 3064 3065 return 0; 3066 } 3067 3068 /* 3069 * sip_sis900_set_filter: 3070 * 3071 * Set up the receive filter. 3072 */ 3073 static void 3074 sipcom_sis900_set_filter(struct sip_softc *sc) 3075 { 3076 bus_space_tag_t st = sc->sc_st; 3077 bus_space_handle_t sh = sc->sc_sh; 3078 struct ethercom *ec = &sc->sc_ethercom; 3079 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3080 struct ether_multi *enm; 3081 const uint8_t *cp; 3082 struct ether_multistep step; 3083 uint32_t crc, mchash[16]; 3084 3085 /* 3086 * Initialize the prototype RFCR. 3087 */ 3088 sc->sc_rfcr = RFCR_RFEN; 3089 if (ifp->if_flags & IFF_BROADCAST) 3090 sc->sc_rfcr |= RFCR_AAB; 3091 if (ifp->if_flags & IFF_PROMISC) { 3092 sc->sc_rfcr |= RFCR_AAP; 3093 goto allmulti; 3094 } 3095 3096 /* 3097 * Set up the multicast address filter by passing all multicast 3098 * addresses through a CRC generator, and then using the high-order 3099 * 6 bits as an index into the 128 bit multicast hash table (only 3100 * the lower 16 bits of each 32 bit multicast hash register are 3101 * valid). The high order bits select the register, while the 3102 * rest of the bits select the bit within the register. 3103 */ 3104 3105 memset(mchash, 0, sizeof(mchash)); 3106 3107 /* 3108 * SiS900 (at least SiS963) requires us to register the address of 3109 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 3110 */ 3111 crc = 0x0ed423f9; 3112 3113 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3114 SIP_SIS900_REV(sc, SIS_REV_960) || 3115 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3116 /* Just want the 8 most significant bits. */ 3117 crc >>= 24; 3118 } else { 3119 /* Just want the 7 most significant bits. */ 3120 crc >>= 25; 3121 } 3122 3123 /* Set the corresponding bit in the hash table. */ 3124 mchash[crc >> 4] |= 1 << (crc & 0xf); 3125 3126 ETHER_LOCK(ec); 3127 ETHER_FIRST_MULTI(step, ec, enm); 3128 while (enm != NULL) { 3129 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3130 /* 3131 * We must listen to a range of multicast addresses. 3132 * For now, just accept all multicasts, rather than 3133 * trying to set only those filter bits needed to match 3134 * the range. (At this time, the only use of address 3135 * ranges is for IP multicast routing, for which the 3136 * range is big enough to require all bits set.) 3137 */ 3138 ETHER_UNLOCK(ec); 3139 goto allmulti; 3140 } 3141 3142 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3143 3144 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3145 SIP_SIS900_REV(sc, SIS_REV_960) || 3146 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3147 /* Just want the 8 most significant bits. */ 3148 crc >>= 24; 3149 } else { 3150 /* Just want the 7 most significant bits. */ 3151 crc >>= 25; 3152 } 3153 3154 /* Set the corresponding bit in the hash table. */ 3155 mchash[crc >> 4] |= 1 << (crc & 0xf); 3156 3157 ETHER_NEXT_MULTI(step, enm); 3158 } 3159 ETHER_UNLOCK(ec); 3160 3161 ifp->if_flags &= ~IFF_ALLMULTI; 3162 goto setit; 3163 3164 allmulti: 3165 ifp->if_flags |= IFF_ALLMULTI; 3166 sc->sc_rfcr |= RFCR_AAM; 3167 3168 setit: 3169 #define FILTER_EMIT(addr, data) \ 3170 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3171 delay(1); \ 3172 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3173 delay(1) 3174 3175 /* 3176 * Disable receive filter, and program the node address. 3177 */ 3178 cp = CLLADDR(ifp->if_sadl); 3179 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 3180 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 3181 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 3182 3183 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3184 /* 3185 * Program the multicast hash table. 3186 */ 3187 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 3188 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 3189 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 3190 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 3191 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 3192 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 3193 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 3194 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 3195 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3196 SIP_SIS900_REV(sc, SIS_REV_960) || 3197 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3198 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 3199 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 3200 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 3201 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 3202 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 3203 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 3204 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 3205 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 3206 } 3207 } 3208 #undef FILTER_EMIT 3209 3210 /* 3211 * Re-enable the receiver filter. 3212 */ 3213 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3214 } 3215 3216 /* 3217 * sip_dp83815_set_filter: 3218 * 3219 * Set up the receive filter. 3220 */ 3221 static void 3222 sipcom_dp83815_set_filter(struct sip_softc *sc) 3223 { 3224 bus_space_tag_t st = sc->sc_st; 3225 bus_space_handle_t sh = sc->sc_sh; 3226 struct ethercom *ec = &sc->sc_ethercom; 3227 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3228 struct ether_multi *enm; 3229 const uint8_t *cp; 3230 struct ether_multistep step; 3231 uint32_t crc, hash, slot, bit; 3232 #define MCHASH_NWORDS_83820 128 3233 #define MCHASH_NWORDS_83815 32 3234 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3235 uint16_t mchash[MCHASH_NWORDS]; 3236 int i; 3237 3238 /* 3239 * Initialize the prototype RFCR. 3240 * Enable the receive filter, and accept on 3241 * Perfect (destination address) Match 3242 * If IFF_BROADCAST, also accept all broadcast packets. 3243 * If IFF_PROMISC, accept all unicast packets (and later, set 3244 * IFF_ALLMULTI and accept all multicast, too). 3245 */ 3246 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3247 if (ifp->if_flags & IFF_BROADCAST) 3248 sc->sc_rfcr |= RFCR_AAB; 3249 if (ifp->if_flags & IFF_PROMISC) { 3250 sc->sc_rfcr |= RFCR_AAP; 3251 goto allmulti; 3252 } 3253 3254 /* 3255 * Set up the DP83820/DP83815 multicast address filter by 3256 * passing all multicast addresses through a CRC generator, 3257 * and then using the high-order 11/9 bits as an index into 3258 * the 2048/512 bit multicast hash table. The high-order 3259 * 7/5 bits select the slot, while the low-order 4 bits 3260 * select the bit within the slot. Note that only the low 3261 * 16-bits of each filter word are used, and there are 3262 * 128/32 filter words. 3263 */ 3264 3265 memset(mchash, 0, sizeof(mchash)); 3266 3267 ifp->if_flags &= ~IFF_ALLMULTI; 3268 ETHER_FIRST_MULTI(step, ec, enm); 3269 if (enm == NULL) 3270 goto setit; 3271 while (enm != NULL) { 3272 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3273 /* 3274 * We must listen to a range of multicast addresses. 3275 * For now, just accept all multicasts, rather than 3276 * trying to set only those filter bits needed to match 3277 * the range. (At this time, the only use of address 3278 * ranges is for IP multicast routing, for which the 3279 * range is big enough to require all bits set.) 3280 */ 3281 goto allmulti; 3282 } 3283 3284 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3285 3286 if (sc->sc_gigabit) { 3287 /* Just want the 11 most significant bits. */ 3288 hash = crc >> 21; 3289 } else { 3290 /* Just want the 9 most significant bits. */ 3291 hash = crc >> 23; 3292 } 3293 3294 slot = hash >> 4; 3295 bit = hash & 0xf; 3296 3297 /* Set the corresponding bit in the hash table. */ 3298 mchash[slot] |= 1 << bit; 3299 3300 ETHER_NEXT_MULTI(step, enm); 3301 } 3302 sc->sc_rfcr |= RFCR_MHEN; 3303 goto setit; 3304 3305 allmulti: 3306 ifp->if_flags |= IFF_ALLMULTI; 3307 sc->sc_rfcr |= RFCR_AAM; 3308 3309 setit: 3310 #define FILTER_EMIT(addr, data) \ 3311 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3312 delay(1); \ 3313 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3314 delay(1) 3315 3316 /* 3317 * Disable receive filter, and program the node address. 3318 */ 3319 cp = CLLADDR(ifp->if_sadl); 3320 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3321 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3322 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3323 3324 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3325 int nwords = 3326 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3327 /* 3328 * Program the multicast hash table. 3329 */ 3330 for (i = 0; i < nwords; i++) { 3331 FILTER_EMIT(sc->sc_parm->p_filtmem + (i * 2), mchash[i]); 3332 } 3333 } 3334 #undef FILTER_EMIT 3335 #undef MCHASH_NWORDS 3336 #undef MCHASH_NWORDS_83815 3337 #undef MCHASH_NWORDS_83820 3338 3339 /* 3340 * Re-enable the receiver filter. 3341 */ 3342 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3343 } 3344 3345 /* 3346 * sip_dp83820_mii_readreg: [mii interface function] 3347 * 3348 * Read a PHY register on the MII of the DP83820. 3349 */ 3350 static int 3351 sipcom_dp83820_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3352 { 3353 struct sip_softc *sc = device_private(self); 3354 3355 if (sc->sc_cfg & CFG_TBI_EN) { 3356 bus_addr_t tbireg; 3357 3358 if (phy != 0) 3359 return -1; 3360 3361 switch (reg) { 3362 case MII_BMCR: tbireg = SIP_TBICR; break; 3363 case MII_BMSR: tbireg = SIP_TBISR; break; 3364 case MII_ANAR: tbireg = SIP_TANAR; break; 3365 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3366 case MII_ANER: tbireg = SIP_TANER; break; 3367 case MII_EXTSR: 3368 /* 3369 * Don't even bother reading the TESR register. 3370 * The manual documents that the device has 3371 * 1000baseX full/half capability, but the 3372 * register itself seems read back 0 on some 3373 * boards. Just hard-code the result. 3374 */ 3375 *val = (EXTSR_1000XFDX | EXTSR_1000XHDX); 3376 return 0; 3377 3378 default: 3379 return 0; 3380 } 3381 3382 *val = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3383 if (tbireg == SIP_TBISR) { 3384 /* LINK and ACOMP are switched! */ 3385 int sr = *val; 3386 3387 *val = 0; 3388 if (sr & TBISR_MR_LINK_STATUS) 3389 *val |= BMSR_LINK; 3390 if (sr & TBISR_MR_AN_COMPLETE) 3391 *val |= BMSR_ACOMP; 3392 3393 /* 3394 * The manual claims this register reads back 0 3395 * on hard and soft reset. But we want to let 3396 * the gentbi driver know that we support auto- 3397 * negotiation, so hard-code this bit in the 3398 * result. 3399 */ 3400 *val |= BMSR_ANEG | BMSR_EXTSTAT; 3401 } 3402 3403 return 0; 3404 } 3405 3406 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg, 3407 val); 3408 } 3409 3410 /* 3411 * sip_dp83820_mii_writereg: [mii interface function] 3412 * 3413 * Write a PHY register on the MII of the DP83820. 3414 */ 3415 static int 3416 sipcom_dp83820_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3417 { 3418 struct sip_softc *sc = device_private(self); 3419 3420 if (sc->sc_cfg & CFG_TBI_EN) { 3421 bus_addr_t tbireg; 3422 3423 if (phy != 0) 3424 return -1; 3425 3426 switch (reg) { 3427 case MII_BMCR: tbireg = SIP_TBICR; break; 3428 case MII_ANAR: tbireg = SIP_TANAR; break; 3429 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3430 default: 3431 return 0; 3432 } 3433 3434 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3435 return 0; 3436 } 3437 3438 return mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, 3439 val); 3440 } 3441 3442 /* 3443 * sip_dp83820_mii_statchg: [mii interface function] 3444 * 3445 * Callback from MII layer when media changes. 3446 */ 3447 static void 3448 sipcom_dp83820_mii_statchg(struct ifnet *ifp) 3449 { 3450 struct sip_softc *sc = ifp->if_softc; 3451 struct mii_data *mii = &sc->sc_mii; 3452 uint32_t cfg, pcr; 3453 3454 /* 3455 * Get flow control negotiation result. 3456 */ 3457 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3458 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3459 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3460 mii->mii_media_active &= ~IFM_ETH_FMASK; 3461 } 3462 3463 /* 3464 * Update TXCFG for full-duplex operation. 3465 */ 3466 if ((mii->mii_media_active & IFM_FDX) != 0) 3467 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3468 else 3469 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3470 3471 /* 3472 * Update RXCFG for full-duplex or loopback. 3473 */ 3474 if ((mii->mii_media_active & IFM_FDX) != 0 || 3475 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3476 sc->sc_rxcfg |= RXCFG_ATX; 3477 else 3478 sc->sc_rxcfg &= ~RXCFG_ATX; 3479 3480 /* 3481 * Update CFG for MII/GMII. 3482 */ 3483 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3484 cfg = sc->sc_cfg | CFG_MODE_1000; 3485 else 3486 cfg = sc->sc_cfg; 3487 3488 /* 3489 * 802.3x flow control. 3490 */ 3491 pcr = 0; 3492 if (sc->sc_flowflags & IFM_FLOW) { 3493 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3494 pcr |= sc->sc_rx_flow_thresh; 3495 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3496 pcr |= PCR_PSEN | PCR_PS_MCAST; 3497 } 3498 3499 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3500 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3501 sc->sc_txcfg); 3502 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3503 sc->sc_rxcfg); 3504 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3505 } 3506 3507 /* 3508 * sip_mii_bitbang_read: [mii bit-bang interface function] 3509 * 3510 * Read the MII serial port for the MII bit-bang module. 3511 */ 3512 static uint32_t 3513 sipcom_mii_bitbang_read(device_t self) 3514 { 3515 struct sip_softc *sc = device_private(self); 3516 3517 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3518 } 3519 3520 /* 3521 * sip_mii_bitbang_write: [mii big-bang interface function] 3522 * 3523 * Write the MII serial port for the MII bit-bang module. 3524 */ 3525 static void 3526 sipcom_mii_bitbang_write(device_t self, uint32_t val) 3527 { 3528 struct sip_softc *sc = device_private(self); 3529 3530 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3531 } 3532 3533 /* 3534 * sip_sis900_mii_readreg: [mii interface function] 3535 * 3536 * Read a PHY register on the MII. 3537 */ 3538 static int 3539 sipcom_sis900_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3540 { 3541 struct sip_softc *sc = device_private(self); 3542 uint32_t enphy; 3543 3544 /* 3545 * The PHY of recent SiS chipsets is accessed through bitbang 3546 * operations. 3547 */ 3548 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3549 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3550 phy, reg, val); 3551 3552 #ifndef SIS900_MII_RESTRICT 3553 /* 3554 * The SiS 900 has only an internal PHY on the MII. Only allow 3555 * MII address 0. 3556 */ 3557 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3558 return -1; 3559 #endif 3560 3561 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3562 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3563 ENPHY_RWCMD | ENPHY_ACCESS); 3564 do { 3565 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3566 } while (enphy & ENPHY_ACCESS); 3567 3568 *val = (enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT; 3569 return 0; 3570 } 3571 3572 /* 3573 * sip_sis900_mii_writereg: [mii interface function] 3574 * 3575 * Write a PHY register on the MII. 3576 */ 3577 static int 3578 sipcom_sis900_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3579 { 3580 struct sip_softc *sc = device_private(self); 3581 uint32_t enphy; 3582 3583 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3584 return mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3585 phy, reg, val); 3586 } 3587 3588 #ifndef SIS900_MII_RESTRICT 3589 /* 3590 * The SiS 900 has only an internal PHY on the MII. Only allow 3591 * MII address 0. 3592 */ 3593 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3594 return -1; 3595 #endif 3596 3597 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3598 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3599 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3600 do { 3601 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3602 } while (enphy & ENPHY_ACCESS); 3603 3604 return 0; 3605 } 3606 3607 /* 3608 * sip_sis900_mii_statchg: [mii interface function] 3609 * 3610 * Callback from MII layer when media changes. 3611 */ 3612 static void 3613 sipcom_sis900_mii_statchg(struct ifnet *ifp) 3614 { 3615 struct sip_softc *sc = ifp->if_softc; 3616 struct mii_data *mii = &sc->sc_mii; 3617 uint32_t flowctl; 3618 3619 /* 3620 * Get flow control negotiation result. 3621 */ 3622 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3623 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3624 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3625 mii->mii_media_active &= ~IFM_ETH_FMASK; 3626 } 3627 3628 /* 3629 * Update TXCFG for full-duplex operation. 3630 */ 3631 if ((mii->mii_media_active & IFM_FDX) != 0) 3632 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3633 else 3634 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3635 3636 /* 3637 * Update RXCFG for full-duplex or loopback. 3638 */ 3639 if ((mii->mii_media_active & IFM_FDX) != 0 || 3640 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3641 sc->sc_rxcfg |= RXCFG_ATX; 3642 else 3643 sc->sc_rxcfg &= ~RXCFG_ATX; 3644 3645 /* 3646 * Update IMR for use of 802.3x flow control. 3647 */ 3648 if (sc->sc_flowflags & IFM_FLOW) { 3649 sc->sc_imr |= (ISR_PAUSE_END | ISR_PAUSE_ST); 3650 flowctl = FLOWCTL_FLOWEN; 3651 } else { 3652 sc->sc_imr &= ~(ISR_PAUSE_END | ISR_PAUSE_ST); 3653 flowctl = 0; 3654 } 3655 3656 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3657 sc->sc_txcfg); 3658 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3659 sc->sc_rxcfg); 3660 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3661 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3662 } 3663 3664 /* 3665 * sip_dp83815_mii_readreg: [mii interface function] 3666 * 3667 * Read a PHY register on the MII. 3668 */ 3669 static int 3670 sipcom_dp83815_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3671 { 3672 struct sip_softc *sc = device_private(self); 3673 uint32_t data; 3674 3675 /* 3676 * The DP83815 only has an internal PHY. Only allow 3677 * MII address 0. 3678 */ 3679 if (phy != 0) 3680 return -1; 3681 3682 /* 3683 * Apparently, after a reset, the DP83815 can take a while 3684 * to respond. During this recovery period, the BMSR returns 3685 * a value of 0. Catch this -- it's not supposed to happen 3686 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3687 * PHY to come back to life. 3688 * 3689 * This works out because the BMSR is the first register 3690 * read during the PHY probe process. 3691 */ 3692 do { 3693 data = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3694 } while (reg == MII_BMSR && data == 0); 3695 3696 *val = data & 0xffff; 3697 return 0; 3698 } 3699 3700 /* 3701 * sip_dp83815_mii_writereg: [mii interface function] 3702 * 3703 * Write a PHY register to the MII. 3704 */ 3705 static int 3706 sipcom_dp83815_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3707 { 3708 struct sip_softc *sc = device_private(self); 3709 3710 /* 3711 * The DP83815 only has an internal PHY. Only allow 3712 * MII address 0. 3713 */ 3714 if (phy != 0) 3715 return -1; 3716 3717 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3718 3719 return 0; 3720 } 3721 3722 /* 3723 * sip_dp83815_mii_statchg: [mii interface function] 3724 * 3725 * Callback from MII layer when media changes. 3726 */ 3727 static void 3728 sipcom_dp83815_mii_statchg(struct ifnet *ifp) 3729 { 3730 struct sip_softc *sc = ifp->if_softc; 3731 3732 /* 3733 * Update TXCFG for full-duplex operation. 3734 */ 3735 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3736 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3737 else 3738 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3739 3740 /* 3741 * Update RXCFG for full-duplex or loopback. 3742 */ 3743 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3744 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3745 sc->sc_rxcfg |= RXCFG_ATX; 3746 else 3747 sc->sc_rxcfg &= ~RXCFG_ATX; 3748 3749 /* 3750 * XXX 802.3x flow control. 3751 */ 3752 3753 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3754 sc->sc_txcfg); 3755 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3756 sc->sc_rxcfg); 3757 3758 /* 3759 * Some DP83815s experience problems when used with short 3760 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3761 * sequence adjusts the DSP's signal attenuation to fix the 3762 * problem. 3763 */ 3764 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3765 uint32_t reg; 3766 3767 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3768 3769 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3770 reg &= 0x0fff; 3771 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3772 delay(100); 3773 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3774 reg &= 0x00ff; 3775 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3776 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3777 0x00e8); 3778 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3779 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3780 reg | 0x20); 3781 } 3782 3783 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3784 } 3785 } 3786 3787 static void 3788 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3789 const struct pci_attach_args *pa, uint8_t *enaddr) 3790 { 3791 uint16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3792 uint8_t cksum, *e, match; 3793 int i; 3794 3795 /* 3796 * EEPROM data format for the DP83820 can be found in 3797 * the DP83820 manual, section 4.2.4. 3798 */ 3799 3800 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3801 3802 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3803 match = ~(match - 1); 3804 3805 cksum = 0x55; 3806 e = (uint8_t *)eeprom_data; 3807 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3808 cksum += *e++; 3809 3810 if (cksum != match) 3811 printf("%s: Checksum (%x) mismatch (%x)", 3812 device_xname(sc->sc_dev), cksum, match); 3813 3814 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3815 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3816 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3817 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3818 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3819 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3820 } 3821 3822 static void 3823 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3824 { 3825 int i; 3826 3827 /* 3828 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3829 * a reason, but I don't know it. 3830 */ 3831 for (i = 0; i < 10; i++) 3832 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3833 } 3834 3835 static void 3836 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3837 const struct pci_attach_args *pa, uint8_t *enaddr) 3838 { 3839 uint16_t myea[ETHER_ADDR_LEN / 2]; 3840 3841 switch (sc->sc_rev) { 3842 case SIS_REV_630S: 3843 case SIS_REV_630E: 3844 case SIS_REV_630EA1: 3845 case SIS_REV_630ET: 3846 case SIS_REV_635: 3847 /* 3848 * The MAC address for the on-board Ethernet of 3849 * the SiS 630 chipset is in the NVRAM. Kick 3850 * the chip into re-loading it from NVRAM, and 3851 * read the MAC address out of the filter registers. 3852 */ 3853 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3854 3855 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3856 RFCR_RFADDR_NODE0); 3857 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3858 0xffff; 3859 3860 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3861 RFCR_RFADDR_NODE2); 3862 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3863 0xffff; 3864 3865 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3866 RFCR_RFADDR_NODE4); 3867 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3868 0xffff; 3869 break; 3870 3871 case SIS_REV_960: 3872 { 3873 #define SIS_SET_EROMAR(x, y) \ 3874 bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3875 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3876 3877 #define SIS_CLR_EROMAR(x, y) \ 3878 bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3879 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3880 3881 int waittime, i; 3882 3883 /* Allow to read EEPROM from LAN. It is shared 3884 * between a 1394 controller and the NIC and each 3885 * time we access it, we need to set SIS_EECMD_REQ. 3886 */ 3887 SIS_SET_EROMAR(sc, EROMAR_REQ); 3888 3889 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3890 /* Force EEPROM to idle state. */ 3891 3892 /* 3893 * XXX-cube This is ugly. 3894 * I'll look for docs about it. 3895 */ 3896 SIS_SET_EROMAR(sc, EROMAR_EECS); 3897 sipcom_sis900_eeprom_delay(sc); 3898 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3899 SIS_SET_EROMAR(sc, EROMAR_EESK); 3900 sipcom_sis900_eeprom_delay(sc); 3901 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3902 sipcom_sis900_eeprom_delay(sc); 3903 } 3904 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3905 sipcom_sis900_eeprom_delay(sc); 3906 bus_space_write_4(sc->sc_st, sc->sc_sh, 3907 SIP_EROMAR, 0); 3908 3909 if (bus_space_read_4(sc->sc_st, sc->sc_sh, 3910 SIP_EROMAR) & EROMAR_GNT) { 3911 sipcom_read_eeprom(sc, 3912 SIP_EEPROM_ETHERNET_ID0 >> 1, 3913 sizeof(myea) / sizeof(myea[0]), 3914 myea); 3915 break; 3916 } 3917 DELAY(1); 3918 } 3919 3920 /* 3921 * Set SIS_EECTL_CLK to high, so a other master 3922 * can operate on the i2c bus. 3923 */ 3924 SIS_SET_EROMAR(sc, EROMAR_EESK); 3925 3926 /* Refuse EEPROM access by LAN */ 3927 SIS_SET_EROMAR(sc, EROMAR_DONE); 3928 } break; 3929 3930 default: 3931 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3932 sizeof(myea) / sizeof(myea[0]), myea); 3933 } 3934 3935 enaddr[0] = myea[0] & 0xff; 3936 enaddr[1] = myea[0] >> 8; 3937 enaddr[2] = myea[1] & 0xff; 3938 enaddr[3] = myea[1] >> 8; 3939 enaddr[4] = myea[2] & 0xff; 3940 enaddr[5] = myea[2] >> 8; 3941 } 3942 3943 /* Table and macro to bit-reverse an octet. */ 3944 static const uint8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3945 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3946 3947 static void 3948 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3949 const struct pci_attach_args *pa, uint8_t *enaddr) 3950 { 3951 uint16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3952 uint8_t cksum, *e, match; 3953 int i; 3954 3955 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3956 sizeof(eeprom_data[0]), eeprom_data); 3957 3958 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3959 match = ~(match - 1); 3960 3961 cksum = 0x55; 3962 e = (uint8_t *)eeprom_data; 3963 for (i = 0; i < SIP_DP83815_EEPROM_CHECKSUM; i++) 3964 cksum += *e++; 3965 3966 if (cksum != match) 3967 printf("%s: Checksum (%x) mismatch (%x)", 3968 device_xname(sc->sc_dev), cksum, match); 3969 3970 /* 3971 * Unrolled because it makes slightly more sense this way. 3972 * The DP83815 stores the MAC address in bit 0 of word 6 3973 * through bit 15 of word 8. 3974 */ 3975 ea = &eeprom_data[6]; 3976 enaddr[0] = ((*ea & 0x1) << 7); 3977 ea++; 3978 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3979 enaddr[1] = ((*ea & 0x1FE) >> 1); 3980 enaddr[2] = ((*ea & 0x1) << 7); 3981 ea++; 3982 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3983 enaddr[3] = ((*ea & 0x1FE) >> 1); 3984 enaddr[4] = ((*ea & 0x1) << 7); 3985 ea++; 3986 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3987 enaddr[5] = ((*ea & 0x1FE) >> 1); 3988 3989 /* 3990 * In case that's not weird enough, we also need to reverse 3991 * the bits in each byte. This all actually makes more sense 3992 * if you think about the EEPROM storage as an array of bits 3993 * being shifted into bytes, but that's not how we're looking 3994 * at it here... 3995 */ 3996 for (i = 0; i < 6 ;i++) 3997 enaddr[i] = bbr(enaddr[i]); 3998 } 3999 4000 /* 4001 * sip_mediastatus: [ifmedia interface function] 4002 * 4003 * Get the current interface media status. 4004 */ 4005 static void 4006 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 4007 { 4008 struct sip_softc *sc = ifp->if_softc; 4009 4010 if (!device_is_active(sc->sc_dev)) { 4011 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 4012 ifmr->ifm_status = 0; 4013 return; 4014 } 4015 ether_mediastatus(ifp, ifmr); 4016 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) | 4017 sc->sc_flowflags; 4018 } 4019
Indexes created Tue Sep 30 11:09:46 GMT 2025