if_sip.c revision 1.182
1 /* $NetBSD: if_sip.c,v 1.182 2020/03/16 01:54:23 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999 Network Computer, Inc. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of Network Computer, Inc. nor the names of its 45 * contributors may be used to endorse or promote products derived 46 * from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * Device driver for the Silicon Integrated Systems SiS 900, 63 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 64 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 65 * controllers. 66 * 67 * Originally written to support the SiS 900 by Jason R. Thorpe for 68 * Network Computer, Inc. 69 * 70 * TODO: 71 * 72 * - Reduce the Rx interrupt load. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.182 2020/03/16 01:54:23 thorpej Exp $"); 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/callout.h> 81 #include <sys/mbuf.h> 82 #include <sys/malloc.h> 83 #include <sys/kernel.h> 84 #include <sys/socket.h> 85 #include <sys/ioctl.h> 86 #include <sys/errno.h> 87 #include <sys/device.h> 88 #include <sys/queue.h> 89 #include <sys/rndsource.h> 90 91 #include <net/if.h> 92 #include <net/if_dl.h> 93 #include <net/if_media.h> 94 #include <net/if_ether.h> 95 #include <net/bpf.h> 96 97 #include <sys/bus.h> 98 #include <sys/intr.h> 99 #include <machine/endian.h> 100 101 #include <dev/mii/mii.h> 102 #include <dev/mii/miivar.h> 103 #include <dev/mii/mii_bitbang.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 109 #include <dev/pci/if_sipreg.h> 110 111 /* 112 * Transmit descriptor list size. This is arbitrary, but allocate 113 * enough descriptors for 128 pending transmissions, and 8 segments 114 * per packet (64 for DP83820 for jumbo frames). 115 * 116 * This MUST work out to a power of 2. 117 */ 118 #define GSIP_NTXSEGS_ALLOC 16 119 #define SIP_NTXSEGS_ALLOC 8 120 121 #define SIP_TXQUEUELEN 256 122 #define MAX_SIP_NTXDESC \ 123 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 124 125 /* 126 * Receive descriptor list size. We have one Rx buffer per incoming 127 * packet, so this logic is a little simpler. 128 * 129 * Actually, on the DP83820, we allow the packet to consume more than 130 * one buffer, in order to support jumbo Ethernet frames. In that 131 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 132 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 133 * so we'd better be quick about handling receive interrupts. 134 */ 135 #define GSIP_NRXDESC 256 136 #define SIP_NRXDESC 128 137 138 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 139 140 /* 141 * Set this to 1 to force-disable using the 64-bit data path 142 * on DP83820. 143 */ 144 static int gsip_disable_data64 = 0; 145 146 /* 147 * Control structures are DMA'd to the SiS900 chip. We allocate them in 148 * a single clump that maps to a single DMA segment to make several things 149 * easier. 150 */ 151 struct sip_control_data { 152 /* 153 * The transmit descriptors. 154 */ 155 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 156 157 /* 158 * The receive descriptors. 159 */ 160 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 161 }; 162 163 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 164 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 165 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 166 167 /* 168 * Software state for transmit jobs. 169 */ 170 struct sip_txsoft { 171 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 172 bus_dmamap_t txs_dmamap; /* our DMA map */ 173 int txs_firstdesc; /* first descriptor in packet */ 174 int txs_lastdesc; /* last descriptor in packet */ 175 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 176 }; 177 178 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 179 180 /* 181 * Software state for receive jobs. 182 */ 183 struct sip_rxsoft { 184 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 185 bus_dmamap_t rxs_dmamap; /* our DMA map */ 186 }; 187 188 enum sip_attach_stage { 189 SIP_ATTACH_FIN = 0 190 , SIP_ATTACH_CREATE_RXMAP 191 , SIP_ATTACH_CREATE_TXMAP 192 , SIP_ATTACH_LOAD_MAP 193 , SIP_ATTACH_CREATE_MAP 194 , SIP_ATTACH_MAP_MEM 195 , SIP_ATTACH_ALLOC_MEM 196 , SIP_ATTACH_INTR 197 , SIP_ATTACH_MAP 198 }; 199 200 /* 201 * Software state per device. 202 */ 203 struct sip_softc { 204 device_t sc_dev; /* generic device information */ 205 device_suspensor_t sc_suspensor; 206 pmf_qual_t sc_qual; 207 208 bus_space_tag_t sc_st; /* bus space tag */ 209 bus_space_handle_t sc_sh; /* bus space handle */ 210 bus_size_t sc_sz; /* bus space size */ 211 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 212 pci_chipset_tag_t sc_pc; 213 bus_dma_segment_t sc_seg; 214 struct ethercom sc_ethercom; /* ethernet common data */ 215 216 const struct sip_product *sc_model; /* which model are we? */ 217 bool sc_gigabit; /* 1: 83820, 0: other */ 218 bool sc_dma64; /* using 64-bit DMA addresses */ 219 int sc_rev; /* chip revision */ 220 221 unsigned int sc_bufptr_idx; 222 unsigned int sc_cmdsts_idx; 223 unsigned int sc_extsts_idx; /* DP83820 only */ 224 225 void *sc_ih; /* interrupt cookie */ 226 227 struct mii_data sc_mii; /* MII/media information */ 228 229 callout_t sc_tick_ch; /* tick callout */ 230 231 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 232 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 233 234 /* 235 * Software state for transmit and receive descriptors. 236 */ 237 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 238 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 239 240 /* 241 * Control data structures. 242 */ 243 struct sip_control_data *sc_control_data; 244 #define sc_txdescs sc_control_data->scd_txdescs 245 #define sc_rxdescs sc_control_data->scd_rxdescs 246 247 #ifdef SIP_EVENT_COUNTERS 248 /* 249 * Event counters. 250 */ 251 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 252 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 253 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 254 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 255 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 256 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 257 struct evcnt sc_ev_rxpause; /* PAUSE received */ 258 /* DP83820 only */ 259 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 260 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 261 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 262 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 263 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 264 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 265 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 266 #endif /* SIP_EVENT_COUNTERS */ 267 268 uint32_t sc_txcfg; /* prototype TXCFG register */ 269 uint32_t sc_rxcfg; /* prototype RXCFG register */ 270 uint32_t sc_imr; /* prototype IMR register */ 271 uint32_t sc_rfcr; /* prototype RFCR register */ 272 273 uint32_t sc_cfg; /* prototype CFG register */ 274 275 uint32_t sc_gpior; /* prototype GPIOR register */ 276 277 uint32_t sc_tx_fill_thresh; /* transmit fill threshold */ 278 uint32_t sc_tx_drain_thresh; /* transmit drain threshold */ 279 280 uint32_t sc_rx_drain_thresh; /* receive drain threshold */ 281 282 int sc_flowflags; /* 802.3x flow control flags */ 283 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 284 int sc_paused; /* paused indication */ 285 286 int sc_txfree; /* number of free Tx descriptors */ 287 int sc_txnext; /* next ready Tx descriptor */ 288 int sc_txwin; /* Tx descriptors since last intr */ 289 290 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 291 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 292 293 /* values of interface state at last init */ 294 struct { 295 /* if_capenable */ 296 uint64_t if_capenable; 297 /* ec_capenable */ 298 int ec_capenable; 299 /* VLAN_ATTACHED */ 300 int is_vlan; 301 } sc_prev; 302 303 u_short sc_if_flags; 304 305 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 306 int sc_rxdiscard; 307 int sc_rxlen; 308 struct mbuf *sc_rxhead; 309 struct mbuf *sc_rxtail; 310 struct mbuf **sc_rxtailp; 311 312 int sc_ntxdesc; 313 int sc_ntxdesc_mask; 314 315 int sc_nrxdesc_mask; 316 317 const struct sip_parm { 318 const struct sip_regs { 319 int r_rxcfg; 320 int r_txcfg; 321 } p_regs; 322 323 const struct sip_bits { 324 uint32_t b_txcfg_mxdma_8; 325 uint32_t b_txcfg_mxdma_16; 326 uint32_t b_txcfg_mxdma_32; 327 uint32_t b_txcfg_mxdma_64; 328 uint32_t b_txcfg_mxdma_128; 329 uint32_t b_txcfg_mxdma_256; 330 uint32_t b_txcfg_mxdma_512; 331 uint32_t b_txcfg_flth_mask; 332 uint32_t b_txcfg_drth_mask; 333 334 uint32_t b_rxcfg_mxdma_8; 335 uint32_t b_rxcfg_mxdma_16; 336 uint32_t b_rxcfg_mxdma_32; 337 uint32_t b_rxcfg_mxdma_64; 338 uint32_t b_rxcfg_mxdma_128; 339 uint32_t b_rxcfg_mxdma_256; 340 uint32_t b_rxcfg_mxdma_512; 341 342 uint32_t b_isr_txrcmp; 343 uint32_t b_isr_rxrcmp; 344 uint32_t b_isr_dperr; 345 uint32_t b_isr_sserr; 346 uint32_t b_isr_rmabt; 347 uint32_t b_isr_rtabt; 348 349 uint32_t b_cmdsts_size_mask; 350 } p_bits; 351 int p_filtmem; 352 int p_rxbuf_len; 353 bus_size_t p_tx_dmamap_size; 354 int p_ntxsegs; 355 int p_ntxsegs_alloc; 356 int p_nrxdesc; 357 } *sc_parm; 358 359 void (*sc_rxintr)(struct sip_softc *); 360 361 krndsource_t rnd_source; /* random source */ 362 }; 363 364 #define sc_bits sc_parm->p_bits 365 #define sc_regs sc_parm->p_regs 366 367 static const struct sip_parm sip_parm = { 368 .p_filtmem = OTHER_RFCR_NS_RFADDR_FILTMEM 369 , .p_rxbuf_len = MCLBYTES - 1 /* field width */ 370 , .p_tx_dmamap_size = MCLBYTES 371 , .p_ntxsegs = 16 372 , .p_ntxsegs_alloc = SIP_NTXSEGS_ALLOC 373 , .p_nrxdesc = SIP_NRXDESC 374 , .p_bits = { 375 .b_txcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 376 , .b_txcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 377 , .b_txcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 378 , .b_txcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 379 , .b_txcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 380 , .b_txcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 381 , .b_txcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 382 , .b_txcfg_flth_mask = 0x00003f00 /* Tx fill threshold */ 383 , .b_txcfg_drth_mask = 0x0000003f /* Tx drain threshold */ 384 385 , .b_rxcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 386 , .b_rxcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 387 , .b_rxcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 388 , .b_rxcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 389 , .b_rxcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 390 , .b_rxcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 391 , .b_rxcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 392 393 , .b_isr_txrcmp = 0x02000000 /* transmit reset complete */ 394 , .b_isr_rxrcmp = 0x01000000 /* receive reset complete */ 395 , .b_isr_dperr = 0x00800000 /* detected parity error */ 396 , .b_isr_sserr = 0x00400000 /* signalled system error */ 397 , .b_isr_rmabt = 0x00200000 /* received master abort */ 398 , .b_isr_rtabt = 0x00100000 /* received target abort */ 399 , .b_cmdsts_size_mask = OTHER_CMDSTS_SIZE_MASK 400 } 401 , .p_regs = { 402 .r_rxcfg = OTHER_SIP_RXCFG, 403 .r_txcfg = OTHER_SIP_TXCFG 404 } 405 }, gsip_parm = { 406 .p_filtmem = DP83820_RFCR_NS_RFADDR_FILTMEM 407 , .p_rxbuf_len = MCLBYTES - 8 408 , .p_tx_dmamap_size = ETHER_MAX_LEN_JUMBO 409 , .p_ntxsegs = 64 410 , .p_ntxsegs_alloc = GSIP_NTXSEGS_ALLOC 411 , .p_nrxdesc = GSIP_NRXDESC 412 , .p_bits = { 413 .b_txcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 414 , .b_txcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 415 , .b_txcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 416 , .b_txcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 417 , .b_txcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 418 , .b_txcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 419 , .b_txcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 420 , .b_txcfg_flth_mask = 0x0000ff00 /* Fx fill threshold */ 421 , .b_txcfg_drth_mask = 0x000000ff /* Tx drain threshold */ 422 423 , .b_rxcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 424 , .b_rxcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 425 , .b_rxcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 426 , .b_rxcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 427 , .b_rxcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 428 , .b_rxcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 429 , .b_rxcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 430 431 , .b_isr_txrcmp = 0x00400000 /* transmit reset complete */ 432 , .b_isr_rxrcmp = 0x00200000 /* receive reset complete */ 433 , .b_isr_dperr = 0x00100000 /* detected parity error */ 434 , .b_isr_sserr = 0x00080000 /* signalled system error */ 435 , .b_isr_rmabt = 0x00040000 /* received master abort */ 436 , .b_isr_rtabt = 0x00020000 /* received target abort */ 437 , .b_cmdsts_size_mask = DP83820_CMDSTS_SIZE_MASK 438 } 439 , .p_regs = { 440 .r_rxcfg = DP83820_SIP_RXCFG, 441 .r_txcfg = DP83820_SIP_TXCFG 442 } 443 }; 444 445 static inline int 446 sip_nexttx(const struct sip_softc *sc, int x) 447 { 448 return (x + 1) & sc->sc_ntxdesc_mask; 449 } 450 451 static inline int 452 sip_nextrx(const struct sip_softc *sc, int x) 453 { 454 return (x + 1) & sc->sc_nrxdesc_mask; 455 } 456 457 /* 83820 only */ 458 static inline void 459 sip_rxchain_reset(struct sip_softc *sc) 460 { 461 sc->sc_rxtailp = &sc->sc_rxhead; 462 *sc->sc_rxtailp = NULL; 463 sc->sc_rxlen = 0; 464 } 465 466 /* 83820 only */ 467 static inline void 468 sip_rxchain_link(struct sip_softc *sc, struct mbuf *m) 469 { 470 *sc->sc_rxtailp = sc->sc_rxtail = m; 471 sc->sc_rxtailp = &m->m_next; 472 } 473 474 #ifdef SIP_EVENT_COUNTERS 475 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 476 #else 477 #define SIP_EVCNT_INCR(ev) /* nothing */ 478 #endif 479 480 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 481 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 482 483 static inline void 484 sip_set_rxdp(struct sip_softc *sc, bus_addr_t addr) 485 { 486 if (sc->sc_gigabit) 487 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXDP_HI, 488 BUS_ADDR_HI32(addr)); 489 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXDP, BUS_ADDR_LO32(addr)); 490 } 491 492 static inline void 493 sip_set_txdp(struct sip_softc *sc, bus_addr_t addr) 494 { 495 if (sc->sc_gigabit) 496 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP_HI, 497 BUS_ADDR_HI32(addr)); 498 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, BUS_ADDR_LO32(addr)); 499 } 500 501 static inline void 502 sip_cdtxsync(struct sip_softc *sc, const int x0, const int n0, const int ops) 503 { 504 int x, n; 505 506 x = x0; 507 n = n0; 508 509 /* If it will wrap around, sync to the end of the ring. */ 510 if (x + n > sc->sc_ntxdesc) { 511 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 512 SIP_CDTXOFF(x), sizeof(struct sip_desc) * 513 (sc->sc_ntxdesc - x), ops); 514 n -= (sc->sc_ntxdesc - x); 515 x = 0; 516 } 517 518 /* Now sync whatever is left. */ 519 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 520 SIP_CDTXOFF(x), sizeof(struct sip_desc) * n, ops); 521 } 522 523 static inline void 524 sip_cdrxsync(struct sip_softc *sc, int x, int ops) 525 { 526 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 527 SIP_CDRXOFF(x), sizeof(struct sip_desc), ops); 528 } 529 530 static void 531 sip_init_txring(struct sip_softc *sc) 532 { 533 struct sip_desc *sipd; 534 bus_addr_t next_desc; 535 int i; 536 537 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 538 for (i = 0; i < sc->sc_ntxdesc; i++) { 539 sipd = &sc->sc_txdescs[i]; 540 next_desc = SIP_CDTXADDR(sc, sip_nexttx(sc, i)); 541 if (sc->sc_dma64) { 542 sipd->sipd_words[GSIP64_DESC_LINK_LO] = 543 htole32(BUS_ADDR_LO32(next_desc)); 544 sipd->sipd_words[GSIP64_DESC_LINK_HI] = 545 htole32(BUS_ADDR_HI32(next_desc)); 546 } else { 547 /* SIP_DESC_LINK == GSIP_DESC_LINK */ 548 sipd->sipd_words[SIP_DESC_LINK] = htole32(next_desc); 549 } 550 } 551 sip_cdtxsync(sc, 0, sc->sc_ntxdesc, 552 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 553 sc->sc_txfree = sc->sc_ntxdesc; 554 sc->sc_txnext = 0; 555 sc->sc_txwin = 0; 556 } 557 558 static inline void 559 sip_init_txdesc(struct sip_softc *sc, int x, bus_addr_t bufptr, uint32_t cmdsts) 560 { 561 struct sip_desc *sipd = &sc->sc_txdescs[x]; 562 563 if (sc->sc_dma64) { 564 sipd->sipd_words[GSIP64_DESC_BUFPTR_LO] = 565 htole32(BUS_ADDR_LO32(bufptr)); 566 sipd->sipd_words[GSIP64_DESC_BUFPTR_HI] = 567 htole32(BUS_ADDR_HI32(bufptr)); 568 } else { 569 sipd->sipd_words[sc->sc_bufptr_idx] = htole32(bufptr); 570 } 571 sipd->sipd_words[sc->sc_extsts_idx] = 0; 572 membar_producer(); 573 sipd->sipd_words[sc->sc_cmdsts_idx] = htole32(cmdsts); 574 /* sip_cdtxsync() will be done later. */ 575 } 576 577 static inline void 578 sip_init_rxdesc(struct sip_softc *sc, int x) 579 { 580 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 581 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 582 const bus_addr_t next_desc = SIP_CDRXADDR(sc, sip_nextrx(sc, x)); 583 584 if (sc->sc_dma64) { 585 sipd->sipd_words[GSIP64_DESC_LINK_LO] = 586 htole32(BUS_ADDR_LO32(next_desc)); 587 sipd->sipd_words[GSIP64_DESC_LINK_HI] = 588 htole32(BUS_ADDR_HI32(next_desc)); 589 sipd->sipd_words[GSIP64_DESC_BUFPTR_LO] = 590 htole32(BUS_ADDR_LO32(rxs->rxs_dmamap->dm_segs[0].ds_addr)); 591 sipd->sipd_words[GSIP64_DESC_BUFPTR_HI] = 592 htole32(BUS_ADDR_HI32(rxs->rxs_dmamap->dm_segs[0].ds_addr)); 593 } else { 594 sipd->sipd_words[SIP_DESC_LINK] = htole32(next_desc); 595 sipd->sipd_words[sc->sc_bufptr_idx] = 596 htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 597 } 598 sipd->sipd_words[sc->sc_extsts_idx] = 0; 599 membar_producer(); 600 sipd->sipd_words[sc->sc_cmdsts_idx] = 601 htole32(CMDSTS_INTR | (sc->sc_parm->p_rxbuf_len & 602 sc->sc_bits.b_cmdsts_size_mask)); 603 sip_cdrxsync(sc, x, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 604 } 605 606 #define SIP_CHIP_VERS(sc, v, p, r) \ 607 ((sc)->sc_model->sip_vendor == (v) && \ 608 (sc)->sc_model->sip_product == (p) && \ 609 (sc)->sc_rev == (r)) 610 611 #define SIP_CHIP_MODEL(sc, v, p) \ 612 ((sc)->sc_model->sip_vendor == (v) && \ 613 (sc)->sc_model->sip_product == (p)) 614 615 #define SIP_SIS900_REV(sc, rev) \ 616 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 617 618 #define SIP_TIMEOUT 1000 619 620 static int sip_ifflags_cb(struct ethercom *); 621 static void sipcom_start(struct ifnet *); 622 static void sipcom_watchdog(struct ifnet *); 623 static int sipcom_ioctl(struct ifnet *, u_long, void *); 624 static int sipcom_init(struct ifnet *); 625 static void sipcom_stop(struct ifnet *, int); 626 627 static bool sipcom_reset(struct sip_softc *); 628 static void sipcom_rxdrain(struct sip_softc *); 629 static int sipcom_add_rxbuf(struct sip_softc *, int); 630 static void sipcom_read_eeprom(struct sip_softc *, int, int, 631 uint16_t *); 632 static void sipcom_tick(void *); 633 634 static void sipcom_sis900_set_filter(struct sip_softc *); 635 static void sipcom_dp83815_set_filter(struct sip_softc *); 636 637 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 638 const struct pci_attach_args *, uint8_t *); 639 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 640 static void sipcom_sis900_read_macaddr(struct sip_softc *, 641 const struct pci_attach_args *, uint8_t *); 642 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 643 const struct pci_attach_args *, uint8_t *); 644 645 static int sipcom_intr(void *); 646 static void sipcom_txintr(struct sip_softc *); 647 static void sip_rxintr(struct sip_softc *); 648 static void gsip_rxintr(struct sip_softc *); 649 650 static int sipcom_dp83820_mii_readreg(device_t, int, int, uint16_t *); 651 static int sipcom_dp83820_mii_writereg(device_t, int, int, uint16_t); 652 static void sipcom_dp83820_mii_statchg(struct ifnet *); 653 654 static int sipcom_sis900_mii_readreg(device_t, int, int, uint16_t *); 655 static int sipcom_sis900_mii_writereg(device_t, int, int, uint16_t); 656 static void sipcom_sis900_mii_statchg(struct ifnet *); 657 658 static int sipcom_dp83815_mii_readreg(device_t, int, int, uint16_t *); 659 static int sipcom_dp83815_mii_writereg(device_t, int, int, uint16_t); 660 static void sipcom_dp83815_mii_statchg(struct ifnet *); 661 662 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 663 664 static int sipcom_match(device_t, cfdata_t, void *); 665 static void sipcom_attach(device_t, device_t, void *); 666 static void sipcom_do_detach(device_t, enum sip_attach_stage); 667 static int sipcom_detach(device_t, int); 668 static bool sipcom_resume(device_t, const pmf_qual_t *); 669 static bool sipcom_suspend(device_t, const pmf_qual_t *); 670 671 int gsip_copy_small = 0; 672 int sip_copy_small = 0; 673 674 CFATTACH_DECL3_NEW(gsip, sizeof(struct sip_softc), 675 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 676 DVF_DETACH_SHUTDOWN); 677 CFATTACH_DECL3_NEW(sip, sizeof(struct sip_softc), 678 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 679 DVF_DETACH_SHUTDOWN); 680 681 /* 682 * Descriptions of the variants of the SiS900. 683 */ 684 struct sip_variant { 685 int (*sipv_mii_readreg)(device_t, int, int, uint16_t *); 686 int (*sipv_mii_writereg)(device_t, int, int, uint16_t); 687 void (*sipv_mii_statchg)(struct ifnet *); 688 void (*sipv_set_filter)(struct sip_softc *); 689 void (*sipv_read_macaddr)(struct sip_softc *, 690 const struct pci_attach_args *, uint8_t *); 691 }; 692 693 static uint32_t sipcom_mii_bitbang_read(device_t); 694 static void sipcom_mii_bitbang_write(device_t, uint32_t); 695 696 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 697 sipcom_mii_bitbang_read, 698 sipcom_mii_bitbang_write, 699 { 700 EROMAR_MDIO, /* MII_BIT_MDO */ 701 EROMAR_MDIO, /* MII_BIT_MDI */ 702 EROMAR_MDC, /* MII_BIT_MDC */ 703 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 704 0, /* MII_BIT_DIR_PHY_HOST */ 705 } 706 }; 707 708 static const struct sip_variant sipcom_variant_dp83820 = { 709 sipcom_dp83820_mii_readreg, 710 sipcom_dp83820_mii_writereg, 711 sipcom_dp83820_mii_statchg, 712 sipcom_dp83815_set_filter, 713 sipcom_dp83820_read_macaddr, 714 }; 715 716 static const struct sip_variant sipcom_variant_sis900 = { 717 sipcom_sis900_mii_readreg, 718 sipcom_sis900_mii_writereg, 719 sipcom_sis900_mii_statchg, 720 sipcom_sis900_set_filter, 721 sipcom_sis900_read_macaddr, 722 }; 723 724 static const struct sip_variant sipcom_variant_dp83815 = { 725 sipcom_dp83815_mii_readreg, 726 sipcom_dp83815_mii_writereg, 727 sipcom_dp83815_mii_statchg, 728 sipcom_dp83815_set_filter, 729 sipcom_dp83815_read_macaddr, 730 }; 731 732 733 /* 734 * Devices supported by this driver. 735 */ 736 static const struct sip_product { 737 pci_vendor_id_t sip_vendor; 738 pci_product_id_t sip_product; 739 const char *sip_name; 740 const struct sip_variant *sip_variant; 741 bool sip_gigabit; 742 } sipcom_products[] = { 743 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 744 "NatSemi DP83820 Gigabit Ethernet", 745 &sipcom_variant_dp83820, true }, 746 747 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 748 "SiS 900 10/100 Ethernet", 749 &sipcom_variant_sis900, false }, 750 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 751 "SiS 7016 10/100 Ethernet", 752 &sipcom_variant_sis900, false }, 753 754 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 755 "NatSemi DP83815 10/100 Ethernet", 756 &sipcom_variant_dp83815, false }, 757 758 { 0, 0, 759 NULL, 760 NULL, false }, 761 }; 762 763 static const struct sip_product * 764 sipcom_lookup(const struct pci_attach_args *pa, bool gigabit) 765 { 766 const struct sip_product *sip; 767 768 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 769 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 770 PCI_PRODUCT(pa->pa_id) == sip->sip_product && 771 sip->sip_gigabit == gigabit) 772 return sip; 773 } 774 return NULL; 775 } 776 777 /* 778 * I really hate stupid hardware vendors. There's a bit in the EEPROM 779 * which indicates if the card can do 64-bit data transfers. Unfortunately, 780 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 781 * which means we try to use 64-bit data transfers on those cards if we 782 * happen to be plugged into a 32-bit slot. 783 * 784 * What we do is use this table of cards known to be 64-bit cards. If 785 * you have a 64-bit card who's subsystem ID is not listed in this table, 786 * send the output of "pcictl dump ..." of the device to me so that your 787 * card will use the 64-bit data path when plugged into a 64-bit slot. 788 * 789 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 790 * June 30, 2002 791 */ 792 static int 793 sipcom_check_64bit(const struct pci_attach_args *pa) 794 { 795 static const struct { 796 pci_vendor_id_t c64_vendor; 797 pci_product_id_t c64_product; 798 } card64[] = { 799 /* Asante GigaNIX */ 800 { 0x128a, 0x0002 }, 801 802 /* Accton EN1407-T, Planex GN-1000TE */ 803 { 0x1113, 0x1407 }, 804 805 /* Netgear GA621 */ 806 { 0x1385, 0x621a }, 807 808 /* Netgear GA622 */ 809 { 0x1385, 0x622a }, 810 811 /* SMC EZ Card 1000 (9462TX) */ 812 { 0x10b8, 0x9462 }, 813 814 { 0, 0} 815 }; 816 pcireg_t subsys; 817 int i; 818 819 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 820 821 for (i = 0; card64[i].c64_vendor != 0; i++) { 822 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 823 PCI_PRODUCT(subsys) == card64[i].c64_product) 824 return 1; 825 } 826 827 return 0; 828 } 829 830 static int 831 sipcom_match(device_t parent, cfdata_t cf, void *aux) 832 { 833 struct pci_attach_args *pa = aux; 834 835 if (sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0) != NULL) 836 return 1; 837 838 return 0; 839 } 840 841 static void 842 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 843 { 844 uint32_t reg; 845 int i; 846 847 /* 848 * Cause the chip to load configuration data from the EEPROM. 849 */ 850 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 851 for (i = 0; i < 10000; i++) { 852 delay(10); 853 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 854 PTSCR_EELOAD_EN) == 0) 855 break; 856 } 857 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 858 PTSCR_EELOAD_EN) { 859 printf("%s: timeout loading configuration from EEPROM\n", 860 device_xname(sc->sc_dev)); 861 return; 862 } 863 864 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 865 866 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 867 if (reg & CFG_PCI64_DET) { 868 const char *using64 = NULL; 869 870 if (reg & CFG_DATA64_EN) { 871 /* 872 * Check to see if this card is 64-bit. If so, 873 * enable 64-bit data transfers. 874 * 875 * We can't trust the DATA64_EN bit in the EEPROM, 876 * because vendors of 32-bit cards fail to clear 877 * that bit in many cases (yet the card still detects 878 * that it's in a 64-bit slot because I guess they 879 * wired up ACK64# and REQ64#). 880 */ 881 if (gsip_disable_data64) 882 using64 = "force-disabled"; 883 else if (sipcom_check_64bit(pa)) { 884 sc->sc_cfg |= CFG_DATA64_EN; 885 using64 = "enabled"; 886 } else 887 using64 = "disabled (32-bit card)"; 888 } else { 889 using64 = "disabled in EEPROM"; 890 } 891 printf("%s: 64-bit slot detected, 64-bit tranfers %s\n", 892 device_xname(sc->sc_dev), using64); 893 } 894 895 /* 896 * The T64ADDR bit is loaded by the chip from the EEPROM and 897 * is read-only. 898 */ 899 if (reg & CFG_T64ADDR) 900 sc->sc_cfg |= CFG_T64ADDR; 901 902 /* 903 * We can use 64-bit DMA addressing regardless of what 904 * sort of slot we're in. 905 */ 906 if (pci_dma64_available(pa)) { 907 sc->sc_dmat = pa->pa_dmat64; 908 sc->sc_cfg |= CFG_M64ADDR; 909 sc->sc_dma64 = true; 910 } 911 912 if (reg & (CFG_TBI_EN | CFG_EXT_125)) { 913 const char *sep = ""; 914 printf("%s: using ", device_xname(sc->sc_dev)); 915 if (reg & CFG_EXT_125) { 916 sc->sc_cfg |= CFG_EXT_125; 917 printf("%sexternal 125MHz clock", sep); 918 sep = ", "; 919 } 920 if (reg & CFG_TBI_EN) { 921 sc->sc_cfg |= CFG_TBI_EN; 922 printf("%sten-bit interface", sep); 923 sep = ", "; 924 } 925 printf("\n"); 926 } 927 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 928 (reg & CFG_MRM_DIS) != 0) 929 sc->sc_cfg |= CFG_MRM_DIS; 930 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 931 (reg & CFG_MWI_DIS) != 0) 932 sc->sc_cfg |= CFG_MWI_DIS; 933 934 /* 935 * Use the extended descriptor format on the DP83820. This 936 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 937 * checksumming. 938 */ 939 sc->sc_cfg |= CFG_EXTSTS_EN; 940 } 941 942 static int 943 sipcom_detach(device_t self, int flags) 944 { 945 int s; 946 947 s = splnet(); 948 sipcom_do_detach(self, SIP_ATTACH_FIN); 949 splx(s); 950 951 return 0; 952 } 953 954 static void 955 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 956 { 957 int i; 958 struct sip_softc *sc = device_private(self); 959 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 960 961 /* 962 * Free any resources we've allocated during attach. 963 * Do this in reverse order and fall through. 964 */ 965 switch (stage) { 966 case SIP_ATTACH_FIN: 967 sipcom_stop(ifp, 1); 968 pmf_device_deregister(self); 969 #ifdef SIP_EVENT_COUNTERS 970 /* 971 * Attach event counters. 972 */ 973 evcnt_detach(&sc->sc_ev_txforceintr); 974 evcnt_detach(&sc->sc_ev_txdstall); 975 evcnt_detach(&sc->sc_ev_hiberr); 976 evcnt_detach(&sc->sc_ev_rxintr); 977 evcnt_detach(&sc->sc_ev_txiintr); 978 evcnt_detach(&sc->sc_ev_txdintr); 979 if (!sc->sc_gigabit) { 980 evcnt_detach(&sc->sc_ev_rxpause); 981 } else { 982 evcnt_detach(&sc->sc_ev_txudpsum); 983 evcnt_detach(&sc->sc_ev_txtcpsum); 984 evcnt_detach(&sc->sc_ev_txipsum); 985 evcnt_detach(&sc->sc_ev_rxudpsum); 986 evcnt_detach(&sc->sc_ev_rxtcpsum); 987 evcnt_detach(&sc->sc_ev_rxipsum); 988 evcnt_detach(&sc->sc_ev_txpause); 989 evcnt_detach(&sc->sc_ev_rxpause); 990 } 991 #endif /* SIP_EVENT_COUNTERS */ 992 993 rnd_detach_source(&sc->rnd_source); 994 995 ether_ifdetach(ifp); 996 if_detach(ifp); 997 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 998 ifmedia_fini(&sc->sc_mii.mii_media); 999 1000 /*FALLTHROUGH*/ 1001 case SIP_ATTACH_CREATE_RXMAP: 1002 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1003 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1004 bus_dmamap_destroy(sc->sc_dmat, 1005 sc->sc_rxsoft[i].rxs_dmamap); 1006 } 1007 /*FALLTHROUGH*/ 1008 case SIP_ATTACH_CREATE_TXMAP: 1009 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1010 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1011 bus_dmamap_destroy(sc->sc_dmat, 1012 sc->sc_txsoft[i].txs_dmamap); 1013 } 1014 /*FALLTHROUGH*/ 1015 case SIP_ATTACH_LOAD_MAP: 1016 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1017 /*FALLTHROUGH*/ 1018 case SIP_ATTACH_CREATE_MAP: 1019 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1020 /*FALLTHROUGH*/ 1021 case SIP_ATTACH_MAP_MEM: 1022 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 1023 sizeof(struct sip_control_data)); 1024 /*FALLTHROUGH*/ 1025 case SIP_ATTACH_ALLOC_MEM: 1026 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 1027 /* FALLTHROUGH*/ 1028 case SIP_ATTACH_INTR: 1029 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 1030 /* FALLTHROUGH*/ 1031 case SIP_ATTACH_MAP: 1032 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 1033 break; 1034 default: 1035 break; 1036 } 1037 return; 1038 } 1039 1040 static bool 1041 sipcom_resume(device_t self, const pmf_qual_t *qual) 1042 { 1043 struct sip_softc *sc = device_private(self); 1044 1045 return sipcom_reset(sc); 1046 } 1047 1048 static bool 1049 sipcom_suspend(device_t self, const pmf_qual_t *qual) 1050 { 1051 struct sip_softc *sc = device_private(self); 1052 1053 sipcom_rxdrain(sc); 1054 return true; 1055 } 1056 1057 static void 1058 sipcom_attach(device_t parent, device_t self, void *aux) 1059 { 1060 struct sip_softc *sc = device_private(self); 1061 struct pci_attach_args *pa = aux; 1062 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1063 struct mii_data * const mii = &sc->sc_mii; 1064 pci_chipset_tag_t pc = pa->pa_pc; 1065 pci_intr_handle_t ih; 1066 const char *intrstr = NULL; 1067 bus_space_tag_t iot, memt; 1068 bus_space_handle_t ioh, memh; 1069 bus_size_t iosz, memsz; 1070 int ioh_valid, memh_valid; 1071 int i, rseg, error; 1072 const struct sip_product *sip; 1073 uint8_t enaddr[ETHER_ADDR_LEN]; 1074 pcireg_t csr; 1075 pcireg_t memtype; 1076 bus_size_t tx_dmamap_size; 1077 int ntxsegs_alloc; 1078 cfdata_t cf = device_cfdata(self); 1079 char intrbuf[PCI_INTRSTR_LEN]; 1080 1081 callout_init(&sc->sc_tick_ch, 0); 1082 callout_setfunc(&sc->sc_tick_ch, sipcom_tick, sc); 1083 1084 sip = sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0); 1085 if (sip == NULL) { 1086 aprint_error("\n"); 1087 panic("%s: impossible", __func__); 1088 } 1089 sc->sc_dev = self; 1090 sc->sc_gigabit = sip->sip_gigabit; 1091 sc->sc_dma64 = false; 1092 pmf_self_suspensor_init(self, &sc->sc_suspensor, &sc->sc_qual); 1093 sc->sc_pc = pc; 1094 1095 if (sc->sc_gigabit) { 1096 if (sc->sc_dma64) { 1097 sc->sc_bufptr_idx = GSIP64_DESC_BUFPTR_LO; 1098 sc->sc_cmdsts_idx = GSIP64_DESC_CMDSTS; 1099 sc->sc_extsts_idx = GSIP64_DESC_EXTSTS; 1100 } else { 1101 sc->sc_bufptr_idx = GSIP_DESC_BUFPTR; 1102 sc->sc_cmdsts_idx = GSIP_DESC_CMDSTS; 1103 sc->sc_extsts_idx = GSIP_DESC_EXTSTS; 1104 } 1105 sc->sc_rxintr = gsip_rxintr; 1106 sc->sc_parm = &gsip_parm; 1107 } else { 1108 sc->sc_rxintr = sip_rxintr; 1109 sc->sc_parm = &sip_parm; 1110 sc->sc_bufptr_idx = SIP_DESC_BUFPTR; 1111 sc->sc_cmdsts_idx = SIP_DESC_CMDSTS; 1112 /* 1113 * EXTSTS doesn't really exist on non-GigE parts, 1114 * but we initialize the index for simplicity later. 1115 */ 1116 sc->sc_extsts_idx = GSIP_DESC_EXTSTS; 1117 } 1118 tx_dmamap_size = sc->sc_parm->p_tx_dmamap_size; 1119 ntxsegs_alloc = sc->sc_parm->p_ntxsegs_alloc; 1120 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 1121 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 1122 sc->sc_nrxdesc_mask = sc->sc_parm->p_nrxdesc - 1; 1123 1124 sc->sc_rev = PCI_REVISION(pa->pa_class); 1125 1126 aprint_naive("\n"); 1127 aprint_normal(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 1128 1129 sc->sc_model = sip; 1130 1131 /* 1132 * XXX Work-around broken PXE firmware on some boards. 1133 * 1134 * The DP83815 shares an address decoder with the MEM BAR 1135 * and the ROM BAR. Make sure the ROM BAR is disabled, 1136 * so that memory mapped access works. 1137 */ 1138 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1139 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1140 ~PCI_MAPREG_ROM_ENABLE); 1141 1142 /* 1143 * Map the device. 1144 */ 1145 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 1146 PCI_MAPREG_TYPE_IO, 0, 1147 &iot, &ioh, NULL, &iosz) == 0); 1148 if (sc->sc_gigabit) { 1149 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 1150 switch (memtype) { 1151 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1152 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1153 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1154 memtype, 0, &memt, &memh, NULL, &memsz) == 0); 1155 break; 1156 default: 1157 memh_valid = 0; 1158 } 1159 } else { 1160 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1161 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 1162 &memt, &memh, NULL, &memsz) == 0); 1163 } 1164 1165 if (memh_valid) { 1166 sc->sc_st = memt; 1167 sc->sc_sh = memh; 1168 sc->sc_sz = memsz; 1169 } else if (ioh_valid) { 1170 sc->sc_st = iot; 1171 sc->sc_sh = ioh; 1172 sc->sc_sz = iosz; 1173 } else { 1174 aprint_error_dev(self, "unable to map device registers\n"); 1175 return; 1176 } 1177 1178 sc->sc_dmat = pa->pa_dmat; 1179 1180 /* 1181 * Make sure bus mastering is enabled. Also make sure 1182 * Write/Invalidate is enabled if we're allowed to use it. 1183 */ 1184 csr = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1185 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 1186 csr |= PCI_COMMAND_INVALIDATE_ENABLE; 1187 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1188 csr | PCI_COMMAND_MASTER_ENABLE); 1189 1190 /* Power up chip */ 1191 error = pci_activate(pa->pa_pc, pa->pa_tag, self, pci_activate_null); 1192 if (error != 0 && error != EOPNOTSUPP) { 1193 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 1194 return; 1195 } 1196 1197 /* 1198 * Map and establish our interrupt. 1199 */ 1200 if (pci_intr_map(pa, &ih)) { 1201 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 1202 return; 1203 } 1204 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1205 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, sipcom_intr, sc, 1206 device_xname(self)); 1207 if (sc->sc_ih == NULL) { 1208 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 1209 if (intrstr != NULL) 1210 aprint_error(" at %s", intrstr); 1211 aprint_error("\n"); 1212 sipcom_do_detach(self, SIP_ATTACH_MAP); 1213 return; 1214 } 1215 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1216 1217 SIMPLEQ_INIT(&sc->sc_txfreeq); 1218 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1219 1220 /* 1221 * Allocate the control data structures, and create and load the 1222 * DMA map for it. 1223 */ 1224 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1225 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 1226 &rseg, 0)) != 0) { 1227 aprint_error_dev(sc->sc_dev, 1228 "unable to allocate control data, error = %d\n", error); 1229 sipcom_do_detach(self, SIP_ATTACH_INTR); 1230 return; 1231 } 1232 1233 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 1234 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 1235 BUS_DMA_COHERENT)) != 0) { 1236 aprint_error_dev(sc->sc_dev, 1237 "unable to map control data, error = %d\n", error); 1238 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 1239 } 1240 1241 if ((error = bus_dmamap_create(sc->sc_dmat, 1242 sizeof(struct sip_control_data), 1, 1243 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 1244 aprint_error_dev(self, "unable to create control data DMA map" 1245 ", error = %d\n", error); 1246 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 1247 } 1248 1249 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1250 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 1251 0)) != 0) { 1252 aprint_error_dev(self, "unable to load control data DMA map" 1253 ", error = %d\n", error); 1254 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 1255 } 1256 1257 /* 1258 * Create the transmit buffer DMA maps. 1259 */ 1260 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1261 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 1262 sc->sc_parm->p_ntxsegs, MCLBYTES, 0, 0, 1263 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1264 aprint_error_dev(self, "unable to create tx DMA map %d" 1265 ", error = %d\n", i, error); 1266 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 1267 } 1268 } 1269 1270 /* 1271 * Create the receive buffer DMA maps. 1272 */ 1273 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1274 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1275 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1276 aprint_error_dev(self, "unable to create rx DMA map %d" 1277 ", error = %d\n", i, error); 1278 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 1279 } 1280 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1281 } 1282 1283 /* 1284 * Reset the chip to a known state. 1285 */ 1286 sipcom_reset(sc); 1287 1288 /* 1289 * Read the Ethernet address from the EEPROM. This might 1290 * also fetch other stuff from the EEPROM and stash it 1291 * in the softc. 1292 */ 1293 sc->sc_cfg = 0; 1294 if (!sc->sc_gigabit) { 1295 if (SIP_SIS900_REV(sc, SIS_REV_635) || 1296 SIP_SIS900_REV(sc, SIS_REV_900B)) 1297 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1298 1299 if (SIP_SIS900_REV(sc, SIS_REV_635) || 1300 SIP_SIS900_REV(sc, SIS_REV_960) || 1301 SIP_SIS900_REV(sc, SIS_REV_900B)) 1302 sc->sc_cfg |= 1303 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1304 CFG_EDBMASTEN); 1305 } 1306 1307 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1308 1309 aprint_normal_dev(self, "Ethernet address %s\n",ether_sprintf(enaddr)); 1310 1311 /* 1312 * Initialize the configuration register: aggressive PCI 1313 * bus request algorithm, default backoff, default OW timer, 1314 * default parity error detection. 1315 * 1316 * NOTE: "Big endian mode" is useless on the SiS900 and 1317 * friends -- it affects packet data, not descriptors. 1318 */ 1319 if (sc->sc_gigabit) 1320 sipcom_dp83820_attach(sc, pa); 1321 1322 /* 1323 * Initialize our media structures and probe the MII. 1324 */ 1325 mii->mii_ifp = ifp; 1326 mii->mii_readreg = sip->sip_variant->sipv_mii_readreg; 1327 mii->mii_writereg = sip->sip_variant->sipv_mii_writereg; 1328 mii->mii_statchg = sip->sip_variant->sipv_mii_statchg; 1329 sc->sc_ethercom.ec_mii = mii; 1330 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 1331 sipcom_mediastatus); 1332 1333 /* 1334 * XXX We cannot handle flow control on the DP83815. 1335 */ 1336 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1337 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 1338 MII_OFFSET_ANY, 0); 1339 else 1340 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 1341 MII_OFFSET_ANY, MIIF_DOPAUSE); 1342 if (LIST_FIRST(&mii->mii_phys) == NULL) { 1343 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 1344 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 1345 } else 1346 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1347 1348 ifp = &sc->sc_ethercom.ec_if; 1349 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1350 ifp->if_softc = sc; 1351 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1352 sc->sc_if_flags = ifp->if_flags; 1353 ifp->if_ioctl = sipcom_ioctl; 1354 ifp->if_start = sipcom_start; 1355 ifp->if_watchdog = sipcom_watchdog; 1356 ifp->if_init = sipcom_init; 1357 ifp->if_stop = sipcom_stop; 1358 IFQ_SET_READY(&ifp->if_snd); 1359 1360 /* 1361 * We can support 802.1Q VLAN-sized frames. 1362 */ 1363 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1364 1365 if (sc->sc_gigabit) { 1366 /* 1367 * And the DP83820 can do VLAN tagging in hardware, and 1368 * support the jumbo Ethernet MTU. 1369 */ 1370 sc->sc_ethercom.ec_capabilities |= 1371 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1372 sc->sc_ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 1373 1374 /* 1375 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1376 * in hardware. 1377 */ 1378 ifp->if_capabilities |= 1379 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1380 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1381 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1382 } 1383 1384 /* 1385 * Attach the interface. 1386 */ 1387 if_attach(ifp); 1388 if_deferred_start_init(ifp, NULL); 1389 ether_ifattach(ifp, enaddr); 1390 ether_set_ifflags_cb(&sc->sc_ethercom, sip_ifflags_cb); 1391 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1392 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1393 sc->sc_prev.if_capenable = ifp->if_capenable; 1394 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 1395 RND_TYPE_NET, RND_FLAG_DEFAULT); 1396 1397 /* 1398 * The number of bytes that must be available in 1399 * the Tx FIFO before the bus master can DMA more 1400 * data into the FIFO. 1401 */ 1402 sc->sc_tx_fill_thresh = 64 / 32; 1403 1404 /* 1405 * Start at a drain threshold of 512 bytes. We will 1406 * increase it if a DMA underrun occurs. 1407 * 1408 * XXX The minimum value of this variable should be 1409 * tuned. We may be able to improve performance 1410 * by starting with a lower value. That, however, 1411 * may trash the first few outgoing packets if the 1412 * PCI bus is saturated. 1413 */ 1414 if (sc->sc_gigabit) 1415 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1416 else 1417 sc->sc_tx_drain_thresh = 1504 / 32; 1418 1419 /* 1420 * Initialize the Rx FIFO drain threshold. 1421 * 1422 * This is in units of 8 bytes. 1423 * 1424 * We should never set this value lower than 2; 14 bytes are 1425 * required to filter the packet. 1426 */ 1427 sc->sc_rx_drain_thresh = 128 / 8; 1428 1429 #ifdef SIP_EVENT_COUNTERS 1430 /* 1431 * Attach event counters. 1432 */ 1433 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1434 NULL, device_xname(sc->sc_dev), "txdstall"); 1435 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1436 NULL, device_xname(sc->sc_dev), "txforceintr"); 1437 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1438 NULL, device_xname(sc->sc_dev), "txdintr"); 1439 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1440 NULL, device_xname(sc->sc_dev), "txiintr"); 1441 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1442 NULL, device_xname(sc->sc_dev), "rxintr"); 1443 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1444 NULL, device_xname(sc->sc_dev), "hiberr"); 1445 if (!sc->sc_gigabit) { 1446 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1447 NULL, device_xname(sc->sc_dev), "rxpause"); 1448 } else { 1449 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1450 NULL, device_xname(sc->sc_dev), "rxpause"); 1451 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1452 NULL, device_xname(sc->sc_dev), "txpause"); 1453 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1454 NULL, device_xname(sc->sc_dev), "rxipsum"); 1455 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1456 NULL, device_xname(sc->sc_dev), "rxtcpsum"); 1457 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1458 NULL, device_xname(sc->sc_dev), "rxudpsum"); 1459 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1460 NULL, device_xname(sc->sc_dev), "txipsum"); 1461 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1462 NULL, device_xname(sc->sc_dev), "txtcpsum"); 1463 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1464 NULL, device_xname(sc->sc_dev), "txudpsum"); 1465 } 1466 #endif /* SIP_EVENT_COUNTERS */ 1467 1468 if (pmf_device_register(self, sipcom_suspend, sipcom_resume)) 1469 pmf_class_network_register(self, ifp); 1470 else 1471 aprint_error_dev(self, "couldn't establish power handler\n"); 1472 } 1473 1474 static inline void 1475 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1476 uint64_t capenable) 1477 { 1478 uint32_t extsts = 0; 1479 #ifdef DEBUG 1480 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1481 #endif 1482 /* 1483 * If VLANs are enabled and the packet has a VLAN tag, set 1484 * up the descriptor to encapsulate the packet for us. 1485 * 1486 * This apparently has to be on the last descriptor of 1487 * the packet. 1488 */ 1489 1490 /* 1491 * Byte swapping is tricky. We need to provide the tag 1492 * in a network byte order. On a big-endian machine, 1493 * the byteorder is correct, but we need to swap it 1494 * anyway, because this will be undone by the outside 1495 * htole32(). That's why there must be an 1496 * unconditional swap instead of htons() inside. 1497 */ 1498 if (vlan_has_tag(m0)) { 1499 sc->sc_txdescs[lasttx].sipd_words[sc->sc_extsts_idx] |= 1500 htole32(EXTSTS_VPKT | 1501 (bswap16(vlan_get_tag(m0)) & 1502 EXTSTS_VTCI)); 1503 } 1504 1505 /* 1506 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1507 * checksumming, set up the descriptor to do this work 1508 * for us. 1509 * 1510 * This apparently has to be on the first descriptor of 1511 * the packet. 1512 * 1513 * Byte-swap constants so the compiler can optimize. 1514 */ 1515 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1516 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1517 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1518 extsts |= htole32(EXTSTS_IPPKT); 1519 } 1520 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1521 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1522 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1523 extsts |= htole32(EXTSTS_TCPPKT); 1524 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1525 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1526 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1527 extsts |= htole32(EXTSTS_UDPPKT); 1528 } 1529 sc->sc_txdescs[sc->sc_txnext].sipd_words[sc->sc_extsts_idx] |= extsts; 1530 } 1531 1532 /* 1533 * sip_start: [ifnet interface function] 1534 * 1535 * Start packet transmission on the interface. 1536 */ 1537 static void 1538 sipcom_start(struct ifnet *ifp) 1539 { 1540 struct sip_softc *sc = ifp->if_softc; 1541 struct mbuf *m0; 1542 struct mbuf *m; 1543 struct sip_txsoft *txs; 1544 bus_dmamap_t dmamap; 1545 int error, nexttx, lasttx, seg; 1546 int ofree = sc->sc_txfree; 1547 uint32_t cmdsts; 1548 #if 0 1549 int firsttx = sc->sc_txnext; 1550 #endif 1551 1552 /* 1553 * If we've been told to pause, don't transmit any more packets. 1554 */ 1555 if (!sc->sc_gigabit && sc->sc_paused) 1556 return; 1557 1558 if ((ifp->if_flags & IFF_RUNNING) != IFF_RUNNING) 1559 return; 1560 1561 /* 1562 * Loop through the send queue, setting up transmit descriptors 1563 * until we drain the queue, or use up all available transmit 1564 * descriptors. 1565 */ 1566 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL) { 1567 /* 1568 * Grab a packet off the queue. 1569 */ 1570 IFQ_POLL(&ifp->if_snd, m0); 1571 if (m0 == NULL) 1572 break; 1573 m = NULL; 1574 1575 dmamap = txs->txs_dmamap; 1576 1577 /* 1578 * Load the DMA map. If this fails, the packet either 1579 * didn't fit in the alloted number of segments, or we 1580 * were short on resources. 1581 */ 1582 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1583 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1584 /* In the non-gigabit case, we'll copy and try again. */ 1585 if (error != 0 && !sc->sc_gigabit) { 1586 MGETHDR(m, M_DONTWAIT, MT_DATA); 1587 if (m == NULL) { 1588 printf("%s: unable to allocate Tx mbuf\n", 1589 device_xname(sc->sc_dev)); 1590 break; 1591 } 1592 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1593 if (m0->m_pkthdr.len > MHLEN) { 1594 MCLGET(m, M_DONTWAIT); 1595 if ((m->m_flags & M_EXT) == 0) { 1596 printf("%s: unable to allocate Tx " 1597 "cluster\n", 1598 device_xname(sc->sc_dev)); 1599 m_freem(m); 1600 break; 1601 } 1602 } 1603 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1604 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1605 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1606 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1607 if (error) { 1608 printf("%s: unable to load Tx buffer, error = " 1609 "%d\n", device_xname(sc->sc_dev), error); 1610 break; 1611 } 1612 } else if (error == EFBIG) { 1613 /* 1614 * For the too-many-segments case, we simply 1615 * report an error and drop the packet, 1616 * since we can't sanely copy a jumbo packet 1617 * to a single buffer. 1618 */ 1619 printf("%s: Tx packet consumes too many DMA segments, " 1620 "dropping...\n", device_xname(sc->sc_dev)); 1621 IFQ_DEQUEUE(&ifp->if_snd, m0); 1622 m_freem(m0); 1623 continue; 1624 } else if (error != 0) { 1625 /* 1626 * Short on resources, just stop for now. 1627 */ 1628 break; 1629 } 1630 1631 /* 1632 * Ensure we have enough descriptors free to describe 1633 * the packet. Note, we always reserve one descriptor 1634 * at the end of the ring as a termination point, to 1635 * prevent wrap-around. 1636 */ 1637 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1638 /* 1639 * Not enough free descriptors to transmit this 1640 * packet. 1641 */ 1642 bus_dmamap_unload(sc->sc_dmat, dmamap); 1643 if (m != NULL) 1644 m_freem(m); 1645 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1646 break; 1647 } 1648 1649 IFQ_DEQUEUE(&ifp->if_snd, m0); 1650 if (m != NULL) { 1651 m_freem(m0); 1652 m0 = m; 1653 } 1654 1655 /* 1656 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1657 */ 1658 1659 /* Sync the DMA map. */ 1660 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1661 BUS_DMASYNC_PREWRITE); 1662 1663 /* 1664 * Initialize the transmit descriptors. 1665 */ 1666 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1667 seg < dmamap->dm_nsegs; 1668 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1669 /* 1670 * If this is the first descriptor we're 1671 * enqueueing, don't set the OWN bit just 1672 * yet. That could cause a race condition. 1673 * We'll do it below. 1674 */ 1675 1676 cmdsts = dmamap->dm_segs[seg].ds_len; 1677 if (nexttx != sc->sc_txnext) 1678 cmdsts |= CMDSTS_OWN; 1679 if (seg < dmamap->dm_nsegs - 1) 1680 cmdsts |= CMDSTS_MORE; 1681 sip_init_txdesc(sc, nexttx, 1682 dmamap->dm_segs[seg].ds_addr, cmdsts); 1683 lasttx = nexttx; 1684 } 1685 1686 /* 1687 * If we're in the interrupt delay window, delay the 1688 * interrupt. 1689 */ 1690 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1691 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1692 sc->sc_txdescs[lasttx].sipd_words[sc->sc_cmdsts_idx] |= 1693 htole32(CMDSTS_INTR); 1694 sc->sc_txwin = 0; 1695 } 1696 1697 if (sc->sc_gigabit) 1698 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1699 1700 /* Sync the descriptors we're using. */ 1701 sip_cdtxsync(sc, sc->sc_txnext, dmamap->dm_nsegs, 1702 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1703 1704 /* 1705 * The entire packet is set up. Give the first descrptor 1706 * to the chip now. 1707 */ 1708 sc->sc_txdescs[sc->sc_txnext].sipd_words[sc->sc_cmdsts_idx] |= 1709 htole32(CMDSTS_OWN); 1710 sip_cdtxsync(sc, sc->sc_txnext, 1, 1711 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1712 1713 /* 1714 * Store a pointer to the packet so we can free it later, 1715 * and remember what txdirty will be once the packet is 1716 * done. 1717 */ 1718 txs->txs_mbuf = m0; 1719 txs->txs_firstdesc = sc->sc_txnext; 1720 txs->txs_lastdesc = lasttx; 1721 1722 /* Advance the tx pointer. */ 1723 sc->sc_txfree -= dmamap->dm_nsegs; 1724 sc->sc_txnext = nexttx; 1725 1726 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1727 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1728 1729 /* Pass the packet to any BPF listeners. */ 1730 bpf_mtap(ifp, m0, BPF_D_OUT); 1731 } 1732 1733 if (sc->sc_txfree != ofree) { 1734 /* 1735 * Start the transmit process. Note, the manual says 1736 * that if there are no pending transmissions in the 1737 * chip's internal queue (indicated by TXE being clear), 1738 * then the driver software must set the TXDP to the 1739 * first descriptor to be transmitted. However, if we 1740 * do this, it causes serious performance degredation on 1741 * the DP83820 under load, not setting TXDP doesn't seem 1742 * to adversely affect the SiS 900 or DP83815. 1743 * 1744 * Well, I guess it wouldn't be the first time a manual 1745 * has lied -- and they could be speaking of the NULL- 1746 * terminated descriptor list case, rather than OWN- 1747 * terminated rings. 1748 */ 1749 #if 0 1750 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1751 CR_TXE) == 0) { 1752 sip_set_txdp(sc, SIP_CDTXADDR(sc, firsttx)); 1753 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1754 } 1755 #else 1756 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1757 #endif 1758 1759 /* Set a watchdog timer in case the chip flakes out. */ 1760 /* Gigabit autonegotiation takes 5 seconds. */ 1761 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1762 } 1763 } 1764 1765 /* 1766 * sip_watchdog: [ifnet interface function] 1767 * 1768 * Watchdog timer handler. 1769 */ 1770 static void 1771 sipcom_watchdog(struct ifnet *ifp) 1772 { 1773 struct sip_softc *sc = ifp->if_softc; 1774 1775 /* 1776 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1777 * If we get a timeout, try and sweep up transmit descriptors. 1778 * If we manage to sweep them all up, ignore the lack of 1779 * interrupt. 1780 */ 1781 sipcom_txintr(sc); 1782 1783 if (sc->sc_txfree != sc->sc_ntxdesc) { 1784 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1785 if_statinc(ifp, if_oerrors); 1786 1787 /* Reset the interface. */ 1788 (void) sipcom_init(ifp); 1789 } else if (ifp->if_flags & IFF_DEBUG) 1790 printf("%s: recovered from device timeout\n", 1791 device_xname(sc->sc_dev)); 1792 1793 /* Try to get more packets going. */ 1794 sipcom_start(ifp); 1795 } 1796 1797 /* If the interface is up and running, only modify the receive 1798 * filter when setting promiscuous or debug mode. Otherwise fall 1799 * through to ether_ioctl, which will reset the chip. 1800 */ 1801 static int 1802 sip_ifflags_cb(struct ethercom *ec) 1803 { 1804 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1805 == (sc)->sc_ethercom.ec_capenable) \ 1806 && ((sc)->sc_prev.is_vlan == \ 1807 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1808 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1809 struct ifnet *ifp = &ec->ec_if; 1810 struct sip_softc *sc = ifp->if_softc; 1811 u_short change = ifp->if_flags ^ sc->sc_if_flags; 1812 1813 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0 || !COMPARE_EC(sc) || 1814 !COMPARE_IC(sc, ifp)) 1815 return ENETRESET; 1816 /* Set up the receive filter. */ 1817 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1818 return 0; 1819 } 1820 1821 /* 1822 * sip_ioctl: [ifnet interface function] 1823 * 1824 * Handle control requests from the operator. 1825 */ 1826 static int 1827 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1828 { 1829 struct sip_softc *sc = ifp->if_softc; 1830 struct ifreq *ifr = (struct ifreq *)data; 1831 int s, error; 1832 1833 s = splnet(); 1834 1835 switch (cmd) { 1836 case SIOCSIFMEDIA: 1837 /* Flow control requires full-duplex mode. */ 1838 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1839 (ifr->ifr_media & IFM_FDX) == 0) 1840 ifr->ifr_media &= ~IFM_ETH_FMASK; 1841 1842 /* XXX */ 1843 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1844 ifr->ifr_media &= ~IFM_ETH_FMASK; 1845 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1846 if (sc->sc_gigabit && 1847 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1848 /* We can do both TXPAUSE and RXPAUSE. */ 1849 ifr->ifr_media |= 1850 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1851 } else if (ifr->ifr_media & IFM_FLOW) { 1852 /* 1853 * Both TXPAUSE and RXPAUSE must be set. 1854 * (SiS900 and DP83815 don't have PAUSE_ASYM 1855 * feature.) 1856 * 1857 * XXX Can SiS900 and DP83815 send PAUSE? 1858 */ 1859 ifr->ifr_media |= 1860 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1861 } 1862 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1863 } 1864 /*FALLTHROUGH*/ 1865 default: 1866 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1867 break; 1868 1869 error = 0; 1870 1871 if (cmd == SIOCSIFCAP) 1872 error = (*ifp->if_init)(ifp); 1873 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1874 ; 1875 else if (ifp->if_flags & IFF_RUNNING) { 1876 /* 1877 * Multicast list has changed; set the hardware filter 1878 * accordingly. 1879 */ 1880 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1881 } 1882 break; 1883 } 1884 1885 /* Try to get more packets going. */ 1886 sipcom_start(ifp); 1887 1888 sc->sc_if_flags = ifp->if_flags; 1889 splx(s); 1890 return error; 1891 } 1892 1893 /* 1894 * sip_intr: 1895 * 1896 * Interrupt service routine. 1897 */ 1898 static int 1899 sipcom_intr(void *arg) 1900 { 1901 struct sip_softc *sc = arg; 1902 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1903 uint32_t isr; 1904 int handled = 0; 1905 1906 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 1907 return 0; 1908 1909 /* Disable interrupts. */ 1910 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1911 1912 for (;;) { 1913 /* Reading clears interrupt. */ 1914 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1915 if ((isr & sc->sc_imr) == 0) 1916 break; 1917 1918 rnd_add_uint32(&sc->rnd_source, isr); 1919 1920 handled = 1; 1921 1922 if ((ifp->if_flags & IFF_RUNNING) == 0) 1923 break; 1924 1925 if (isr & (ISR_RXORN | ISR_RXIDLE | ISR_RXDESC)) { 1926 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1927 1928 /* Grab any new packets. */ 1929 (*sc->sc_rxintr)(sc); 1930 1931 if (isr & ISR_RXORN) { 1932 printf("%s: receive FIFO overrun\n", 1933 device_xname(sc->sc_dev)); 1934 1935 /* XXX adjust rx_drain_thresh? */ 1936 } 1937 1938 if (isr & ISR_RXIDLE) { 1939 printf("%s: receive ring overrun\n", 1940 device_xname(sc->sc_dev)); 1941 1942 /* Get the receive process going again. */ 1943 sip_set_rxdp(sc, 1944 SIP_CDRXADDR(sc, sc->sc_rxptr)); 1945 bus_space_write_4(sc->sc_st, sc->sc_sh, 1946 SIP_CR, CR_RXE); 1947 } 1948 } 1949 1950 if (isr & (ISR_TXURN | ISR_TXDESC | ISR_TXIDLE)) { 1951 #ifdef SIP_EVENT_COUNTERS 1952 if (isr & ISR_TXDESC) 1953 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1954 else if (isr & ISR_TXIDLE) 1955 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1956 #endif 1957 1958 /* Sweep up transmit descriptors. */ 1959 sipcom_txintr(sc); 1960 1961 if (isr & ISR_TXURN) { 1962 uint32_t thresh; 1963 int txfifo_size = (sc->sc_gigabit) 1964 ? DP83820_SIP_TXFIFO_SIZE 1965 : OTHER_SIP_TXFIFO_SIZE; 1966 1967 printf("%s: transmit FIFO underrun", 1968 device_xname(sc->sc_dev)); 1969 thresh = sc->sc_tx_drain_thresh + 1; 1970 if (thresh <= __SHIFTOUT_MASK(sc->sc_bits.b_txcfg_drth_mask) 1971 && (thresh * 32) <= (txfifo_size - 1972 (sc->sc_tx_fill_thresh * 32))) { 1973 printf("; increasing Tx drain " 1974 "threshold to %u bytes\n", 1975 thresh * 32); 1976 sc->sc_tx_drain_thresh = thresh; 1977 (void) sipcom_init(ifp); 1978 } else { 1979 (void) sipcom_init(ifp); 1980 printf("\n"); 1981 } 1982 } 1983 } 1984 1985 if (sc->sc_imr & (ISR_PAUSE_END | ISR_PAUSE_ST)) { 1986 if (isr & ISR_PAUSE_ST) { 1987 sc->sc_paused = 1; 1988 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1989 } 1990 if (isr & ISR_PAUSE_END) { 1991 sc->sc_paused = 0; 1992 } 1993 } 1994 1995 if (isr & ISR_HIBERR) { 1996 int want_init = 0; 1997 1998 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1999 2000 #define PRINTERR(bit, str) \ 2001 do { \ 2002 if ((isr & (bit)) != 0) { \ 2003 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 2004 printf("%s: %s\n", \ 2005 device_xname(sc->sc_dev), str); \ 2006 want_init = 1; \ 2007 } \ 2008 } while (/*CONSTCOND*/0) 2009 2010 PRINTERR(sc->sc_bits.b_isr_dperr, "parity error"); 2011 PRINTERR(sc->sc_bits.b_isr_sserr, "system error"); 2012 PRINTERR(sc->sc_bits.b_isr_rmabt, "master abort"); 2013 PRINTERR(sc->sc_bits.b_isr_rtabt, "target abort"); 2014 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 2015 /* 2016 * Ignore: 2017 * Tx reset complete 2018 * Rx reset complete 2019 */ 2020 if (want_init) 2021 (void) sipcom_init(ifp); 2022 #undef PRINTERR 2023 } 2024 } 2025 2026 /* Re-enable interrupts. */ 2027 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 2028 2029 /* Try to get more packets going. */ 2030 if_schedule_deferred_start(ifp); 2031 2032 return handled; 2033 } 2034 2035 /* 2036 * sip_txintr: 2037 * 2038 * Helper; handle transmit interrupts. 2039 */ 2040 static void 2041 sipcom_txintr(struct sip_softc *sc) 2042 { 2043 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2044 struct sip_txsoft *txs; 2045 uint32_t cmdsts; 2046 2047 /* 2048 * Go through our Tx list and free mbufs for those 2049 * frames which have been transmitted. 2050 */ 2051 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2052 sip_cdtxsync(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 2053 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2054 2055 cmdsts = le32toh(sc->sc_txdescs[ 2056 txs->txs_lastdesc].sipd_words[sc->sc_cmdsts_idx]); 2057 if (cmdsts & CMDSTS_OWN) 2058 break; 2059 2060 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2061 2062 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 2063 2064 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2065 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2066 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2067 m_freem(txs->txs_mbuf); 2068 txs->txs_mbuf = NULL; 2069 2070 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2071 2072 /* Check for errors and collisions. */ 2073 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 2074 if (cmdsts & (CMDSTS_Tx_TXA | CMDSTS_Tx_TFU | CMDSTS_Tx_ED | 2075 CMDSTS_Tx_EC)) { 2076 if_statinc_ref(nsr, if_oerrors); 2077 if (cmdsts & CMDSTS_Tx_EC) 2078 if_statadd_ref(nsr, if_collisions, 16); 2079 if (ifp->if_flags & IFF_DEBUG) { 2080 if (cmdsts & CMDSTS_Tx_ED) 2081 printf("%s: excessive deferral\n", 2082 device_xname(sc->sc_dev)); 2083 if (cmdsts & CMDSTS_Tx_EC) 2084 printf("%s: excessive collisions\n", 2085 device_xname(sc->sc_dev)); 2086 } 2087 } else { 2088 /* Packet was transmitted successfully. */ 2089 if_statinc_ref(nsr, if_opackets); 2090 if (CMDSTS_COLLISIONS(cmdsts)) 2091 if_statadd_ref(nsr, if_collisions, 2092 CMDSTS_COLLISIONS(cmdsts)); 2093 } 2094 IF_STAT_PUTREF(ifp); 2095 } 2096 2097 /* 2098 * If there are no more pending transmissions, cancel the watchdog 2099 * timer. 2100 */ 2101 if (txs == NULL) { 2102 ifp->if_timer = 0; 2103 sc->sc_txwin = 0; 2104 } 2105 } 2106 2107 /* 2108 * gsip_rxintr: 2109 * 2110 * Helper; handle receive interrupts on gigabit parts. 2111 */ 2112 static void 2113 gsip_rxintr(struct sip_softc *sc) 2114 { 2115 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2116 struct sip_rxsoft *rxs; 2117 struct mbuf *m; 2118 uint32_t cmdsts, extsts; 2119 int i, len; 2120 2121 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2122 rxs = &sc->sc_rxsoft[i]; 2123 2124 sip_cdrxsync(sc, i, 2125 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2126 2127 cmdsts = 2128 le32toh(sc->sc_rxdescs[i].sipd_words[sc->sc_cmdsts_idx]); 2129 extsts = 2130 le32toh(sc->sc_rxdescs[i].sipd_words[sc->sc_extsts_idx]); 2131 len = CMDSTS_SIZE(sc, cmdsts); 2132 2133 /* 2134 * NOTE: OWN is set if owned by _consumer_. We're the 2135 * consumer of the receive ring, so if the bit is clear, 2136 * we have processed all of the packets. 2137 */ 2138 if ((cmdsts & CMDSTS_OWN) == 0) { 2139 /* 2140 * We have processed all of the receive buffers. 2141 */ 2142 break; 2143 } 2144 2145 if (__predict_false(sc->sc_rxdiscard)) { 2146 sip_init_rxdesc(sc, i); 2147 if ((cmdsts & CMDSTS_MORE) == 0) { 2148 /* Reset our state. */ 2149 sc->sc_rxdiscard = 0; 2150 } 2151 continue; 2152 } 2153 2154 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2155 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2156 2157 m = rxs->rxs_mbuf; 2158 2159 /* 2160 * Add a new receive buffer to the ring. 2161 */ 2162 if (sipcom_add_rxbuf(sc, i) != 0) { 2163 /* 2164 * Failed, throw away what we've done so 2165 * far, and discard the rest of the packet. 2166 */ 2167 if_statinc(ifp, if_ierrors); 2168 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2169 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2170 sip_init_rxdesc(sc, i); 2171 if (cmdsts & CMDSTS_MORE) 2172 sc->sc_rxdiscard = 1; 2173 if (sc->sc_rxhead != NULL) 2174 m_freem(sc->sc_rxhead); 2175 sip_rxchain_reset(sc); 2176 continue; 2177 } 2178 2179 sip_rxchain_link(sc, m); 2180 2181 m->m_len = len; 2182 2183 /* 2184 * If this is not the end of the packet, keep 2185 * looking. 2186 */ 2187 if (cmdsts & CMDSTS_MORE) { 2188 sc->sc_rxlen += len; 2189 continue; 2190 } 2191 2192 /* 2193 * Okay, we have the entire packet now. The chip includes 2194 * the FCS, so we need to trim it. 2195 */ 2196 m->m_len -= ETHER_CRC_LEN; 2197 2198 *sc->sc_rxtailp = NULL; 2199 len = m->m_len + sc->sc_rxlen; 2200 m = sc->sc_rxhead; 2201 2202 sip_rxchain_reset(sc); 2203 2204 /* If an error occurred, update stats and drop the packet. */ 2205 if (cmdsts & (CMDSTS_Rx_RXA | CMDSTS_Rx_RUNT | 2206 CMDSTS_Rx_ISE | CMDSTS_Rx_CRCE | CMDSTS_Rx_FAE)) { 2207 if_statinc(ifp, if_ierrors); 2208 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2209 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2210 /* Receive overrun handled elsewhere. */ 2211 printf("%s: receive descriptor error\n", 2212 device_xname(sc->sc_dev)); 2213 } 2214 #define PRINTERR(bit, str) \ 2215 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2216 (cmdsts & (bit)) != 0) \ 2217 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2218 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2219 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2220 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2221 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2222 #undef PRINTERR 2223 m_freem(m); 2224 continue; 2225 } 2226 2227 /* 2228 * If the packet is small enough to fit in a 2229 * single header mbuf, allocate one and copy 2230 * the data into it. This greatly reduces 2231 * memory consumption when we receive lots 2232 * of small packets. 2233 */ 2234 if (gsip_copy_small != 0 && len <= (MHLEN - 2)) { 2235 struct mbuf *nm; 2236 MGETHDR(nm, M_DONTWAIT, MT_DATA); 2237 if (nm == NULL) { 2238 if_statinc(ifp, if_ierrors); 2239 m_freem(m); 2240 continue; 2241 } 2242 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2243 nm->m_data += 2; 2244 nm->m_pkthdr.len = nm->m_len = len; 2245 m_copydata(m, 0, len, mtod(nm, void *)); 2246 m_freem(m); 2247 m = nm; 2248 } 2249 #ifndef __NO_STRICT_ALIGNMENT 2250 else { 2251 /* 2252 * The DP83820's receive buffers must be 4-byte 2253 * aligned. But this means that the data after 2254 * the Ethernet header is misaligned. To compensate, 2255 * we have artificially shortened the buffer size 2256 * in the descriptor, and we do an overlapping copy 2257 * of the data two bytes further in (in the first 2258 * buffer of the chain only). 2259 */ 2260 memmove(mtod(m, char *) + 2, mtod(m, void *), 2261 m->m_len); 2262 m->m_data += 2; 2263 } 2264 #endif /* ! __NO_STRICT_ALIGNMENT */ 2265 2266 /* 2267 * If VLANs are enabled, VLAN packets have been unwrapped 2268 * for us. Associate the tag with the packet. 2269 */ 2270 2271 /* 2272 * Again, byte swapping is tricky. Hardware provided 2273 * the tag in the network byte order, but extsts was 2274 * passed through le32toh() in the meantime. On a 2275 * big-endian machine, we need to swap it again. On a 2276 * little-endian machine, we need to convert from the 2277 * network to host byte order. This means that we must 2278 * swap it in any case, so unconditional swap instead 2279 * of htons() is used. 2280 */ 2281 if ((extsts & EXTSTS_VPKT) != 0) { 2282 vlan_set_tag(m, bswap16(extsts & EXTSTS_VTCI)); 2283 } 2284 2285 /* 2286 * Set the incoming checksum information for the 2287 * packet. 2288 */ 2289 if ((extsts & EXTSTS_IPPKT) != 0) { 2290 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2291 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2292 if (extsts & EXTSTS_Rx_IPERR) 2293 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2294 if (extsts & EXTSTS_TCPPKT) { 2295 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2296 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2297 if (extsts & EXTSTS_Rx_TCPERR) 2298 m->m_pkthdr.csum_flags |= 2299 M_CSUM_TCP_UDP_BAD; 2300 } else if (extsts & EXTSTS_UDPPKT) { 2301 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2302 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2303 if (extsts & EXTSTS_Rx_UDPERR) 2304 m->m_pkthdr.csum_flags |= 2305 M_CSUM_TCP_UDP_BAD; 2306 } 2307 } 2308 2309 m_set_rcvif(m, ifp); 2310 m->m_pkthdr.len = len; 2311 2312 /* Pass it on. */ 2313 if_percpuq_enqueue(ifp->if_percpuq, m); 2314 } 2315 2316 /* Update the receive pointer. */ 2317 sc->sc_rxptr = i; 2318 } 2319 2320 /* 2321 * sip_rxintr: 2322 * 2323 * Helper; handle receive interrupts on 10/100 parts. 2324 */ 2325 static void 2326 sip_rxintr(struct sip_softc *sc) 2327 { 2328 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2329 struct sip_rxsoft *rxs; 2330 struct mbuf *m; 2331 uint32_t cmdsts; 2332 int i, len; 2333 2334 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2335 rxs = &sc->sc_rxsoft[i]; 2336 2337 sip_cdrxsync(sc, i, 2338 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2339 2340 cmdsts = 2341 le32toh(sc->sc_rxdescs[i].sipd_words[sc->sc_cmdsts_idx]); 2342 2343 /* 2344 * NOTE: OWN is set if owned by _consumer_. We're the 2345 * consumer of the receive ring, so if the bit is clear, 2346 * we have processed all of the packets. 2347 */ 2348 if ((cmdsts & CMDSTS_OWN) == 0) { 2349 /* 2350 * We have processed all of the receive buffers. 2351 */ 2352 break; 2353 } 2354 2355 /* If any collisions were seen on the wire, count one. */ 2356 if (cmdsts & CMDSTS_Rx_COL) 2357 if_statinc(ifp, if_collisions); 2358 2359 /* 2360 * If an error occurred, update stats, clear the status 2361 * word, and leave the packet buffer in place. It will 2362 * simply be reused the next time the ring comes around. 2363 */ 2364 if (cmdsts & (CMDSTS_Rx_RXA | CMDSTS_Rx_RUNT | 2365 CMDSTS_Rx_ISE | CMDSTS_Rx_CRCE | CMDSTS_Rx_FAE)) { 2366 if_statinc(ifp, if_ierrors); 2367 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2368 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2369 /* Receive overrun handled elsewhere. */ 2370 printf("%s: receive descriptor error\n", 2371 device_xname(sc->sc_dev)); 2372 } 2373 #define PRINTERR(bit, str) \ 2374 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2375 (cmdsts & (bit)) != 0) \ 2376 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2377 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2378 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2379 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2380 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2381 #undef PRINTERR 2382 sip_init_rxdesc(sc, i); 2383 continue; 2384 } 2385 2386 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2387 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2388 2389 /* 2390 * No errors; receive the packet. Note, the SiS 900 2391 * includes the CRC with every packet. 2392 */ 2393 len = CMDSTS_SIZE(sc, cmdsts) - ETHER_CRC_LEN; 2394 2395 #ifdef __NO_STRICT_ALIGNMENT 2396 /* 2397 * If the packet is small enough to fit in a 2398 * single header mbuf, allocate one and copy 2399 * the data into it. This greatly reduces 2400 * memory consumption when we receive lots 2401 * of small packets. 2402 * 2403 * Otherwise, we add a new buffer to the receive 2404 * chain. If this fails, we drop the packet and 2405 * recycle the old buffer. 2406 */ 2407 if (sip_copy_small != 0 && len <= MHLEN) { 2408 MGETHDR(m, M_DONTWAIT, MT_DATA); 2409 if (m == NULL) 2410 goto dropit; 2411 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2412 memcpy(mtod(m, void *), 2413 mtod(rxs->rxs_mbuf, void *), len); 2414 sip_init_rxdesc(sc, i); 2415 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2416 rxs->rxs_dmamap->dm_mapsize, 2417 BUS_DMASYNC_PREREAD); 2418 } else { 2419 m = rxs->rxs_mbuf; 2420 if (sipcom_add_rxbuf(sc, i) != 0) { 2421 dropit: 2422 if_statinc(ifp, if_ierrors); 2423 sip_init_rxdesc(sc, i); 2424 bus_dmamap_sync(sc->sc_dmat, 2425 rxs->rxs_dmamap, 0, 2426 rxs->rxs_dmamap->dm_mapsize, 2427 BUS_DMASYNC_PREREAD); 2428 continue; 2429 } 2430 } 2431 #else 2432 /* 2433 * The SiS 900's receive buffers must be 4-byte aligned. 2434 * But this means that the data after the Ethernet header 2435 * is misaligned. We must allocate a new buffer and 2436 * copy the data, shifted forward 2 bytes. 2437 */ 2438 MGETHDR(m, M_DONTWAIT, MT_DATA); 2439 if (m == NULL) { 2440 dropit: 2441 if_statinc(ifp, if_ierrors); 2442 sip_init_rxdesc(sc, i); 2443 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2444 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2445 continue; 2446 } 2447 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2448 if (len > (MHLEN - 2)) { 2449 MCLGET(m, M_DONTWAIT); 2450 if ((m->m_flags & M_EXT) == 0) { 2451 m_freem(m); 2452 goto dropit; 2453 } 2454 } 2455 m->m_data += 2; 2456 2457 /* 2458 * Note that we use clusters for incoming frames, so the 2459 * buffer is virtually contiguous. 2460 */ 2461 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2462 2463 /* Allow the receive descriptor to continue using its mbuf. */ 2464 sip_init_rxdesc(sc, i); 2465 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2466 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2467 #endif /* __NO_STRICT_ALIGNMENT */ 2468 2469 m_set_rcvif(m, ifp); 2470 m->m_pkthdr.len = m->m_len = len; 2471 2472 /* Pass it on. */ 2473 if_percpuq_enqueue(ifp->if_percpuq, m); 2474 } 2475 2476 /* Update the receive pointer. */ 2477 sc->sc_rxptr = i; 2478 } 2479 2480 /* 2481 * sip_tick: 2482 * 2483 * One second timer, used to tick the MII. 2484 */ 2485 static void 2486 sipcom_tick(void *arg) 2487 { 2488 struct sip_softc *sc = arg; 2489 int s; 2490 2491 s = splnet(); 2492 #ifdef SIP_EVENT_COUNTERS 2493 if (sc->sc_gigabit) { 2494 /* Read PAUSE related counts from MIB registers. */ 2495 sc->sc_ev_rxpause.ev_count += 2496 bus_space_read_4(sc->sc_st, sc->sc_sh, 2497 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2498 sc->sc_ev_txpause.ev_count += 2499 bus_space_read_4(sc->sc_st, sc->sc_sh, 2500 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2501 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2502 } 2503 #endif /* SIP_EVENT_COUNTERS */ 2504 mii_tick(&sc->sc_mii); 2505 splx(s); 2506 2507 callout_schedule(&sc->sc_tick_ch, hz); 2508 } 2509 2510 /* 2511 * sip_reset: 2512 * 2513 * Perform a soft reset on the SiS 900. 2514 */ 2515 static bool 2516 sipcom_reset(struct sip_softc *sc) 2517 { 2518 bus_space_tag_t st = sc->sc_st; 2519 bus_space_handle_t sh = sc->sc_sh; 2520 int i; 2521 2522 bus_space_write_4(st, sh, SIP_IER, 0); 2523 bus_space_write_4(st, sh, SIP_IMR, 0); 2524 bus_space_write_4(st, sh, SIP_RFCR, 0); 2525 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2526 2527 for (i = 0; i < SIP_TIMEOUT; i++) { 2528 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2529 break; 2530 delay(2); 2531 } 2532 2533 if (i == SIP_TIMEOUT) { 2534 printf("%s: reset failed to complete\n", 2535 device_xname(sc->sc_dev)); 2536 return false; 2537 } 2538 2539 delay(1000); 2540 2541 if (sc->sc_gigabit) { 2542 /* 2543 * Set the general purpose I/O bits. Do it here in case we 2544 * need to have GPIO set up to talk to the media interface. 2545 */ 2546 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2547 delay(1000); 2548 } 2549 return true; 2550 } 2551 2552 static void 2553 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2554 { 2555 uint32_t reg; 2556 bus_space_tag_t st = sc->sc_st; 2557 bus_space_handle_t sh = sc->sc_sh; 2558 /* 2559 * Initialize the VLAN/IP receive control register. 2560 * We enable checksum computation on all incoming 2561 * packets, and do not reject packets w/ bad checksums. 2562 */ 2563 reg = 0; 2564 if (capenable & 2565 (IFCAP_CSUM_IPv4_Rx | IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 2566 reg |= VRCR_IPEN; 2567 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2568 reg |= VRCR_VTDEN | VRCR_VTREN; 2569 bus_space_write_4(st, sh, SIP_VRCR, reg); 2570 2571 /* 2572 * Initialize the VLAN/IP transmit control register. 2573 * We enable outgoing checksum computation on a 2574 * per-packet basis. 2575 */ 2576 reg = 0; 2577 if (capenable & 2578 (IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx)) 2579 reg |= VTCR_PPCHK; 2580 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2581 reg |= VTCR_VPPTI; 2582 bus_space_write_4(st, sh, SIP_VTCR, reg); 2583 2584 /* 2585 * If we're using VLANs, initialize the VLAN data register. 2586 * To understand why we bswap the VLAN Ethertype, see section 2587 * 4.2.36 of the DP83820 manual. 2588 */ 2589 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2590 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2591 } 2592 2593 /* 2594 * sip_init: [ ifnet interface function ] 2595 * 2596 * Initialize the interface. Must be called at splnet(). 2597 */ 2598 static int 2599 sipcom_init(struct ifnet *ifp) 2600 { 2601 struct sip_softc *sc = ifp->if_softc; 2602 bus_space_tag_t st = sc->sc_st; 2603 bus_space_handle_t sh = sc->sc_sh; 2604 struct sip_txsoft *txs; 2605 struct sip_rxsoft *rxs; 2606 int i, error = 0; 2607 2608 if (device_is_active(sc->sc_dev)) { 2609 /* 2610 * Cancel any pending I/O. 2611 */ 2612 sipcom_stop(ifp, 0); 2613 } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 2614 !device_is_active(sc->sc_dev)) 2615 return 0; 2616 2617 /* 2618 * Reset the chip to a known state. 2619 */ 2620 if (!sipcom_reset(sc)) 2621 return EBUSY; 2622 2623 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2624 /* 2625 * DP83815 manual, page 78: 2626 * 4.4 Recommended Registers Configuration 2627 * For optimum performance of the DP83815, version noted 2628 * as DP83815CVNG (SRR = 203h), the listed register 2629 * modifications must be followed in sequence... 2630 * 2631 * It's not clear if this should be 302h or 203h because that 2632 * chip name is listed as SRR 302h in the description of the 2633 * SRR register. However, my revision 302h DP83815 on the 2634 * Netgear FA311 purchased in 02/2001 needs these settings 2635 * to avoid tons of errors in AcceptPerfectMatch (non- 2636 * IFF_PROMISC) mode. I do not know if other revisions need 2637 * this set or not. [briggs -- 09 March 2001] 2638 * 2639 * Note that only the low-order 12 bits of 0xe4 are documented 2640 * and that this sets reserved bits in that register. 2641 */ 2642 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2643 2644 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2645 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2646 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2647 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2648 2649 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2650 } 2651 2652 /* Initialize the transmit descriptor ring. */ 2653 sip_init_txring(sc); 2654 2655 /* 2656 * Initialize the transmit job descriptors. 2657 */ 2658 SIMPLEQ_INIT(&sc->sc_txfreeq); 2659 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2660 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2661 txs = &sc->sc_txsoft[i]; 2662 txs->txs_mbuf = NULL; 2663 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2664 } 2665 2666 /* 2667 * Initialize the receive descriptor and receive job 2668 * descriptor rings. 2669 */ 2670 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2671 rxs = &sc->sc_rxsoft[i]; 2672 if (rxs->rxs_mbuf == NULL) { 2673 if ((error = sipcom_add_rxbuf(sc, i)) != 0) { 2674 printf("%s: unable to allocate or map rx " 2675 "buffer %d, error = %d\n", 2676 device_xname(sc->sc_dev), i, error); 2677 /* 2678 * XXX Should attempt to run with fewer receive 2679 * XXX buffers instead of just failing. 2680 */ 2681 sipcom_rxdrain(sc); 2682 goto out; 2683 } 2684 } else 2685 sip_init_rxdesc(sc, i); 2686 } 2687 sc->sc_rxptr = 0; 2688 sc->sc_rxdiscard = 0; 2689 sip_rxchain_reset(sc); 2690 2691 /* 2692 * Set the configuration register; it's already initialized 2693 * in sip_attach(). 2694 */ 2695 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2696 2697 /* 2698 * Initialize the prototype TXCFG register. 2699 */ 2700 if (sc->sc_gigabit) { 2701 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2702 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2703 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2704 SIP_SIS900_REV(sc, SIS_REV_960) || 2705 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2706 (sc->sc_cfg & CFG_EDBMASTEN)) { 2707 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_64; 2708 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_64; 2709 } else { 2710 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2711 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2712 } 2713 2714 sc->sc_txcfg |= TXCFG_ATP | 2715 __SHIFTIN(sc->sc_tx_fill_thresh, sc->sc_bits.b_txcfg_flth_mask) | 2716 sc->sc_tx_drain_thresh; 2717 bus_space_write_4(st, sh, sc->sc_regs.r_txcfg, sc->sc_txcfg); 2718 2719 /* 2720 * Initialize the receive drain threshold if we have never 2721 * done so. 2722 */ 2723 if (sc->sc_rx_drain_thresh == 0) { 2724 /* 2725 * XXX This value should be tuned. This is set to the 2726 * maximum of 248 bytes, and we may be able to improve 2727 * performance by decreasing it (although we should never 2728 * set this value lower than 2; 14 bytes are required to 2729 * filter the packet). 2730 */ 2731 sc->sc_rx_drain_thresh = __SHIFTOUT_MASK(RXCFG_DRTH_MASK); 2732 } 2733 2734 /* 2735 * Initialize the prototype RXCFG register. 2736 */ 2737 sc->sc_rxcfg |= __SHIFTIN(sc->sc_rx_drain_thresh, RXCFG_DRTH_MASK); 2738 /* 2739 * Accept long packets (including FCS) so we can handle 2740 * 802.1q-tagged frames and jumbo frames properly. 2741 */ 2742 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2743 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2744 sc->sc_rxcfg |= RXCFG_ALP; 2745 2746 /* 2747 * Checksum offloading is disabled if the user selects an MTU 2748 * larger than 8109. (FreeBSD says 8152, but there is emperical 2749 * evidence that >8109 does not work on some boards, such as the 2750 * Planex GN-1000TE). 2751 */ 2752 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2753 (ifp->if_capenable & 2754 (IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2755 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2756 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx))) { 2757 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2758 "disabled.\n", device_xname(sc->sc_dev)); 2759 ifp->if_capenable &= 2760 ~(IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2761 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2762 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx); 2763 ifp->if_csum_flags_tx = 0; 2764 ifp->if_csum_flags_rx = 0; 2765 } 2766 2767 bus_space_write_4(st, sh, sc->sc_regs.r_rxcfg, sc->sc_rxcfg); 2768 2769 if (sc->sc_gigabit) 2770 sipcom_dp83820_init(sc, ifp->if_capenable); 2771 2772 /* 2773 * Give the transmit and receive rings to the chip. 2774 */ 2775 sip_set_txdp(sc, SIP_CDTXADDR(sc, sc->sc_txnext)); 2776 sip_set_rxdp(sc, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2777 2778 /* 2779 * Initialize the interrupt mask. 2780 */ 2781 sc->sc_imr = sc->sc_bits.b_isr_dperr | 2782 sc->sc_bits.b_isr_sserr | 2783 sc->sc_bits.b_isr_rmabt | 2784 sc->sc_bits.b_isr_rtabt | 2785 ISR_RXSOVR | ISR_TXURN | ISR_TXDESC | ISR_TXIDLE | ISR_RXORN | 2786 ISR_RXIDLE | ISR_RXDESC; 2787 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2788 2789 /* Set up the receive filter. */ 2790 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2791 2792 /* 2793 * Tune sc_rx_flow_thresh. 2794 * XXX "More than 8KB" is too short for jumbo frames. 2795 * XXX TODO: Threshold value should be user-settable. 2796 */ 2797 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2798 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2799 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2800 2801 /* 2802 * Set the current media. Do this after initializing the prototype 2803 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2804 * control. 2805 */ 2806 if ((error = ether_mediachange(ifp)) != 0) 2807 goto out; 2808 2809 /* 2810 * Set the interrupt hold-off timer to 100us. 2811 */ 2812 if (sc->sc_gigabit) 2813 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2814 2815 /* 2816 * Enable interrupts. 2817 */ 2818 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2819 2820 /* 2821 * Start the transmit and receive processes. 2822 */ 2823 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2824 2825 /* 2826 * Start the one second MII clock. 2827 */ 2828 callout_schedule(&sc->sc_tick_ch, hz); 2829 2830 /* 2831 * ...all done! 2832 */ 2833 ifp->if_flags |= IFF_RUNNING; 2834 sc->sc_if_flags = ifp->if_flags; 2835 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2836 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2837 sc->sc_prev.if_capenable = ifp->if_capenable; 2838 2839 out: 2840 if (error) 2841 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 2842 return error; 2843 } 2844 2845 /* 2846 * sip_drain: 2847 * 2848 * Drain the receive queue. 2849 */ 2850 static void 2851 sipcom_rxdrain(struct sip_softc *sc) 2852 { 2853 struct sip_rxsoft *rxs; 2854 int i; 2855 2856 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2857 rxs = &sc->sc_rxsoft[i]; 2858 if (rxs->rxs_mbuf != NULL) { 2859 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2860 m_freem(rxs->rxs_mbuf); 2861 rxs->rxs_mbuf = NULL; 2862 } 2863 } 2864 } 2865 2866 /* 2867 * sip_stop: [ ifnet interface function ] 2868 * 2869 * Stop transmission on the interface. 2870 */ 2871 static void 2872 sipcom_stop(struct ifnet *ifp, int disable) 2873 { 2874 struct sip_softc *sc = ifp->if_softc; 2875 bus_space_tag_t st = sc->sc_st; 2876 bus_space_handle_t sh = sc->sc_sh; 2877 struct sip_txsoft *txs; 2878 uint32_t cmdsts = 0; /* DEBUG */ 2879 2880 /* 2881 * Stop the one second clock. 2882 */ 2883 callout_stop(&sc->sc_tick_ch); 2884 2885 /* Down the MII. */ 2886 mii_down(&sc->sc_mii); 2887 2888 if (device_is_active(sc->sc_dev)) { 2889 /* 2890 * Disable interrupts. 2891 */ 2892 bus_space_write_4(st, sh, SIP_IER, 0); 2893 2894 /* 2895 * Stop receiver and transmitter. 2896 */ 2897 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2898 } 2899 2900 /* 2901 * Release any queued transmit buffers. 2902 */ 2903 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2904 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2905 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2906 (sc->sc_txdescs[ 2907 txs->txs_lastdesc].sipd_words[ 2908 sc->sc_cmdsts_idx] & htole32(CMDSTS_INTR)) == 0) 2909 printf("%s: sip_stop: last descriptor does not " 2910 "have INTR bit set\n", device_xname(sc->sc_dev)); 2911 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2912 #ifdef DIAGNOSTIC 2913 if (txs->txs_mbuf == NULL) { 2914 printf("%s: dirty txsoft with no mbuf chain\n", 2915 device_xname(sc->sc_dev)); 2916 panic("sip_stop"); 2917 } 2918 #endif 2919 cmdsts |= /* DEBUG */ 2920 le32toh(sc->sc_txdescs[ 2921 txs->txs_lastdesc].sipd_words[sc->sc_cmdsts_idx]); 2922 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2923 m_freem(txs->txs_mbuf); 2924 txs->txs_mbuf = NULL; 2925 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2926 } 2927 2928 /* 2929 * Mark the interface down and cancel the watchdog timer. 2930 */ 2931 ifp->if_flags &= ~IFF_RUNNING; 2932 ifp->if_timer = 0; 2933 2934 if (disable) 2935 pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); 2936 2937 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2938 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2939 printf("%s: sip_stop: no INTR bits set in dirty tx " 2940 "descriptors\n", device_xname(sc->sc_dev)); 2941 } 2942 2943 /* 2944 * sip_read_eeprom: 2945 * 2946 * Read data from the serial EEPROM. 2947 */ 2948 static void 2949 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2950 uint16_t *data) 2951 { 2952 bus_space_tag_t st = sc->sc_st; 2953 bus_space_handle_t sh = sc->sc_sh; 2954 uint16_t reg; 2955 int i, x; 2956 2957 for (i = 0; i < wordcnt; i++) { 2958 /* Send CHIP SELECT. */ 2959 reg = EROMAR_EECS; 2960 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2961 2962 /* Shift in the READ opcode. */ 2963 for (x = 3; x > 0; x--) { 2964 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2965 reg |= EROMAR_EEDI; 2966 else 2967 reg &= ~EROMAR_EEDI; 2968 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2969 bus_space_write_4(st, sh, SIP_EROMAR, 2970 reg | EROMAR_EESK); 2971 delay(4); 2972 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2973 delay(4); 2974 } 2975 2976 /* Shift in address. */ 2977 for (x = 6; x > 0; x--) { 2978 if ((word + i) & (1 << (x - 1))) 2979 reg |= EROMAR_EEDI; 2980 else 2981 reg &= ~EROMAR_EEDI; 2982 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2983 bus_space_write_4(st, sh, SIP_EROMAR, 2984 reg | EROMAR_EESK); 2985 delay(4); 2986 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2987 delay(4); 2988 } 2989 2990 /* Shift out data. */ 2991 reg = EROMAR_EECS; 2992 data[i] = 0; 2993 for (x = 16; x > 0; x--) { 2994 bus_space_write_4(st, sh, SIP_EROMAR, 2995 reg | EROMAR_EESK); 2996 delay(4); 2997 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2998 data[i] |= (1 << (x - 1)); 2999 bus_space_write_4(st, sh, SIP_EROMAR, reg); 3000 delay(4); 3001 } 3002 3003 /* Clear CHIP SELECT. */ 3004 bus_space_write_4(st, sh, SIP_EROMAR, 0); 3005 delay(4); 3006 } 3007 } 3008 3009 /* 3010 * sipcom_add_rxbuf: 3011 * 3012 * Add a receive buffer to the indicated descriptor. 3013 */ 3014 static int 3015 sipcom_add_rxbuf(struct sip_softc *sc, int idx) 3016 { 3017 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 3018 struct mbuf *m; 3019 int error; 3020 3021 MGETHDR(m, M_DONTWAIT, MT_DATA); 3022 if (m == NULL) 3023 return ENOBUFS; 3024 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 3025 3026 MCLGET(m, M_DONTWAIT); 3027 if ((m->m_flags & M_EXT) == 0) { 3028 m_freem(m); 3029 return ENOBUFS; 3030 } 3031 3032 /* XXX I don't believe this is necessary. --dyoung */ 3033 if (sc->sc_gigabit) 3034 m->m_len = sc->sc_parm->p_rxbuf_len; 3035 3036 if (rxs->rxs_mbuf != NULL) 3037 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3038 3039 rxs->rxs_mbuf = m; 3040 3041 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 3042 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 3043 BUS_DMA_READ | BUS_DMA_NOWAIT); 3044 if (error) { 3045 printf("%s: can't load rx DMA map %d, error = %d\n", 3046 device_xname(sc->sc_dev), idx, error); 3047 panic("%s", __func__); /* XXX */ 3048 } 3049 3050 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3051 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3052 3053 sip_init_rxdesc(sc, idx); 3054 3055 return 0; 3056 } 3057 3058 /* 3059 * sip_sis900_set_filter: 3060 * 3061 * Set up the receive filter. 3062 */ 3063 static void 3064 sipcom_sis900_set_filter(struct sip_softc *sc) 3065 { 3066 bus_space_tag_t st = sc->sc_st; 3067 bus_space_handle_t sh = sc->sc_sh; 3068 struct ethercom *ec = &sc->sc_ethercom; 3069 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3070 struct ether_multi *enm; 3071 const uint8_t *cp; 3072 struct ether_multistep step; 3073 uint32_t crc, mchash[16]; 3074 3075 /* 3076 * Initialize the prototype RFCR. 3077 */ 3078 sc->sc_rfcr = RFCR_RFEN; 3079 if (ifp->if_flags & IFF_BROADCAST) 3080 sc->sc_rfcr |= RFCR_AAB; 3081 if (ifp->if_flags & IFF_PROMISC) { 3082 sc->sc_rfcr |= RFCR_AAP; 3083 goto allmulti; 3084 } 3085 3086 /* 3087 * Set up the multicast address filter by passing all multicast 3088 * addresses through a CRC generator, and then using the high-order 3089 * 6 bits as an index into the 128 bit multicast hash table (only 3090 * the lower 16 bits of each 32 bit multicast hash register are 3091 * valid). The high order bits select the register, while the 3092 * rest of the bits select the bit within the register. 3093 */ 3094 3095 memset(mchash, 0, sizeof(mchash)); 3096 3097 /* 3098 * SiS900 (at least SiS963) requires us to register the address of 3099 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 3100 */ 3101 crc = 0x0ed423f9; 3102 3103 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3104 SIP_SIS900_REV(sc, SIS_REV_960) || 3105 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3106 /* Just want the 8 most significant bits. */ 3107 crc >>= 24; 3108 } else { 3109 /* Just want the 7 most significant bits. */ 3110 crc >>= 25; 3111 } 3112 3113 /* Set the corresponding bit in the hash table. */ 3114 mchash[crc >> 4] |= 1 << (crc & 0xf); 3115 3116 ETHER_LOCK(ec); 3117 ETHER_FIRST_MULTI(step, ec, enm); 3118 while (enm != NULL) { 3119 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3120 /* 3121 * We must listen to a range of multicast addresses. 3122 * For now, just accept all multicasts, rather than 3123 * trying to set only those filter bits needed to match 3124 * the range. (At this time, the only use of address 3125 * ranges is for IP multicast routing, for which the 3126 * range is big enough to require all bits set.) 3127 */ 3128 ETHER_UNLOCK(ec); 3129 goto allmulti; 3130 } 3131 3132 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3133 3134 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3135 SIP_SIS900_REV(sc, SIS_REV_960) || 3136 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3137 /* Just want the 8 most significant bits. */ 3138 crc >>= 24; 3139 } else { 3140 /* Just want the 7 most significant bits. */ 3141 crc >>= 25; 3142 } 3143 3144 /* Set the corresponding bit in the hash table. */ 3145 mchash[crc >> 4] |= 1 << (crc & 0xf); 3146 3147 ETHER_NEXT_MULTI(step, enm); 3148 } 3149 ETHER_UNLOCK(ec); 3150 3151 ifp->if_flags &= ~IFF_ALLMULTI; 3152 goto setit; 3153 3154 allmulti: 3155 ifp->if_flags |= IFF_ALLMULTI; 3156 sc->sc_rfcr |= RFCR_AAM; 3157 3158 setit: 3159 #define FILTER_EMIT(addr, data) \ 3160 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3161 delay(1); \ 3162 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3163 delay(1) 3164 3165 /* 3166 * Disable receive filter, and program the node address. 3167 */ 3168 cp = CLLADDR(ifp->if_sadl); 3169 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 3170 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 3171 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 3172 3173 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3174 /* 3175 * Program the multicast hash table. 3176 */ 3177 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 3178 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 3179 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 3180 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 3181 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 3182 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 3183 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 3184 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 3185 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3186 SIP_SIS900_REV(sc, SIS_REV_960) || 3187 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3188 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 3189 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 3190 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 3191 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 3192 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 3193 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 3194 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 3195 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 3196 } 3197 } 3198 #undef FILTER_EMIT 3199 3200 /* 3201 * Re-enable the receiver filter. 3202 */ 3203 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3204 } 3205 3206 /* 3207 * sip_dp83815_set_filter: 3208 * 3209 * Set up the receive filter. 3210 */ 3211 static void 3212 sipcom_dp83815_set_filter(struct sip_softc *sc) 3213 { 3214 bus_space_tag_t st = sc->sc_st; 3215 bus_space_handle_t sh = sc->sc_sh; 3216 struct ethercom *ec = &sc->sc_ethercom; 3217 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3218 struct ether_multi *enm; 3219 const uint8_t *cp; 3220 struct ether_multistep step; 3221 uint32_t crc, hash, slot, bit; 3222 #define MCHASH_NWORDS_83820 128 3223 #define MCHASH_NWORDS_83815 32 3224 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3225 uint16_t mchash[MCHASH_NWORDS]; 3226 int i; 3227 3228 /* 3229 * Initialize the prototype RFCR. 3230 * Enable the receive filter, and accept on 3231 * Perfect (destination address) Match 3232 * If IFF_BROADCAST, also accept all broadcast packets. 3233 * If IFF_PROMISC, accept all unicast packets (and later, set 3234 * IFF_ALLMULTI and accept all multicast, too). 3235 */ 3236 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3237 if (ifp->if_flags & IFF_BROADCAST) 3238 sc->sc_rfcr |= RFCR_AAB; 3239 if (ifp->if_flags & IFF_PROMISC) { 3240 sc->sc_rfcr |= RFCR_AAP; 3241 goto allmulti; 3242 } 3243 3244 /* 3245 * Set up the DP83820/DP83815 multicast address filter by 3246 * passing all multicast addresses through a CRC generator, 3247 * and then using the high-order 11/9 bits as an index into 3248 * the 2048/512 bit multicast hash table. The high-order 3249 * 7/5 bits select the slot, while the low-order 4 bits 3250 * select the bit within the slot. Note that only the low 3251 * 16-bits of each filter word are used, and there are 3252 * 128/32 filter words. 3253 */ 3254 3255 memset(mchash, 0, sizeof(mchash)); 3256 3257 ifp->if_flags &= ~IFF_ALLMULTI; 3258 ETHER_FIRST_MULTI(step, ec, enm); 3259 if (enm == NULL) 3260 goto setit; 3261 while (enm != NULL) { 3262 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3263 /* 3264 * We must listen to a range of multicast addresses. 3265 * For now, just accept all multicasts, rather than 3266 * trying to set only those filter bits needed to match 3267 * the range. (At this time, the only use of address 3268 * ranges is for IP multicast routing, for which the 3269 * range is big enough to require all bits set.) 3270 */ 3271 goto allmulti; 3272 } 3273 3274 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3275 3276 if (sc->sc_gigabit) { 3277 /* Just want the 11 most significant bits. */ 3278 hash = crc >> 21; 3279 } else { 3280 /* Just want the 9 most significant bits. */ 3281 hash = crc >> 23; 3282 } 3283 3284 slot = hash >> 4; 3285 bit = hash & 0xf; 3286 3287 /* Set the corresponding bit in the hash table. */ 3288 mchash[slot] |= 1 << bit; 3289 3290 ETHER_NEXT_MULTI(step, enm); 3291 } 3292 sc->sc_rfcr |= RFCR_MHEN; 3293 goto setit; 3294 3295 allmulti: 3296 ifp->if_flags |= IFF_ALLMULTI; 3297 sc->sc_rfcr |= RFCR_AAM; 3298 3299 setit: 3300 #define FILTER_EMIT(addr, data) \ 3301 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3302 delay(1); \ 3303 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3304 delay(1) 3305 3306 /* 3307 * Disable receive filter, and program the node address. 3308 */ 3309 cp = CLLADDR(ifp->if_sadl); 3310 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3311 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3312 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3313 3314 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3315 int nwords = 3316 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3317 /* 3318 * Program the multicast hash table. 3319 */ 3320 for (i = 0; i < nwords; i++) { 3321 FILTER_EMIT(sc->sc_parm->p_filtmem + (i * 2), mchash[i]); 3322 } 3323 } 3324 #undef FILTER_EMIT 3325 #undef MCHASH_NWORDS 3326 #undef MCHASH_NWORDS_83815 3327 #undef MCHASH_NWORDS_83820 3328 3329 /* 3330 * Re-enable the receiver filter. 3331 */ 3332 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3333 } 3334 3335 /* 3336 * sip_dp83820_mii_readreg: [mii interface function] 3337 * 3338 * Read a PHY register on the MII of the DP83820. 3339 */ 3340 static int 3341 sipcom_dp83820_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3342 { 3343 struct sip_softc *sc = device_private(self); 3344 3345 if (sc->sc_cfg & CFG_TBI_EN) { 3346 bus_addr_t tbireg; 3347 3348 if (phy != 0) 3349 return -1; 3350 3351 switch (reg) { 3352 case MII_BMCR: tbireg = SIP_TBICR; break; 3353 case MII_BMSR: tbireg = SIP_TBISR; break; 3354 case MII_ANAR: tbireg = SIP_TANAR; break; 3355 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3356 case MII_ANER: tbireg = SIP_TANER; break; 3357 case MII_EXTSR: 3358 /* 3359 * Don't even bother reading the TESR register. 3360 * The manual documents that the device has 3361 * 1000baseX full/half capability, but the 3362 * register itself seems read back 0 on some 3363 * boards. Just hard-code the result. 3364 */ 3365 *val = (EXTSR_1000XFDX | EXTSR_1000XHDX); 3366 return 0; 3367 3368 default: 3369 return 0; 3370 } 3371 3372 *val = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3373 if (tbireg == SIP_TBISR) { 3374 /* LINK and ACOMP are switched! */ 3375 int sr = *val; 3376 3377 *val = 0; 3378 if (sr & TBISR_MR_LINK_STATUS) 3379 *val |= BMSR_LINK; 3380 if (sr & TBISR_MR_AN_COMPLETE) 3381 *val |= BMSR_ACOMP; 3382 3383 /* 3384 * The manual claims this register reads back 0 3385 * on hard and soft reset. But we want to let 3386 * the gentbi driver know that we support auto- 3387 * negotiation, so hard-code this bit in the 3388 * result. 3389 */ 3390 *val |= BMSR_ANEG | BMSR_EXTSTAT; 3391 } 3392 3393 return 0; 3394 } 3395 3396 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg, 3397 val); 3398 } 3399 3400 /* 3401 * sip_dp83820_mii_writereg: [mii interface function] 3402 * 3403 * Write a PHY register on the MII of the DP83820. 3404 */ 3405 static int 3406 sipcom_dp83820_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3407 { 3408 struct sip_softc *sc = device_private(self); 3409 3410 if (sc->sc_cfg & CFG_TBI_EN) { 3411 bus_addr_t tbireg; 3412 3413 if (phy != 0) 3414 return -1; 3415 3416 switch (reg) { 3417 case MII_BMCR: tbireg = SIP_TBICR; break; 3418 case MII_ANAR: tbireg = SIP_TANAR; break; 3419 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3420 default: 3421 return 0; 3422 } 3423 3424 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3425 return 0; 3426 } 3427 3428 return mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, 3429 val); 3430 } 3431 3432 /* 3433 * sip_dp83820_mii_statchg: [mii interface function] 3434 * 3435 * Callback from MII layer when media changes. 3436 */ 3437 static void 3438 sipcom_dp83820_mii_statchg(struct ifnet *ifp) 3439 { 3440 struct sip_softc *sc = ifp->if_softc; 3441 struct mii_data *mii = &sc->sc_mii; 3442 uint32_t cfg, pcr; 3443 3444 /* 3445 * Get flow control negotiation result. 3446 */ 3447 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3448 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3449 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3450 mii->mii_media_active &= ~IFM_ETH_FMASK; 3451 } 3452 3453 /* 3454 * Update TXCFG for full-duplex operation. 3455 */ 3456 if ((mii->mii_media_active & IFM_FDX) != 0) 3457 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3458 else 3459 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3460 3461 /* 3462 * Update RXCFG for full-duplex or loopback. 3463 */ 3464 if ((mii->mii_media_active & IFM_FDX) != 0 || 3465 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3466 sc->sc_rxcfg |= RXCFG_ATX; 3467 else 3468 sc->sc_rxcfg &= ~RXCFG_ATX; 3469 3470 /* 3471 * Update CFG for MII/GMII. 3472 */ 3473 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3474 cfg = sc->sc_cfg | CFG_MODE_1000; 3475 else 3476 cfg = sc->sc_cfg; 3477 3478 /* 3479 * 802.3x flow control. 3480 */ 3481 pcr = 0; 3482 if (sc->sc_flowflags & IFM_FLOW) { 3483 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3484 pcr |= sc->sc_rx_flow_thresh; 3485 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3486 pcr |= PCR_PSEN | PCR_PS_MCAST; 3487 } 3488 3489 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3490 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3491 sc->sc_txcfg); 3492 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3493 sc->sc_rxcfg); 3494 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3495 } 3496 3497 /* 3498 * sip_mii_bitbang_read: [mii bit-bang interface function] 3499 * 3500 * Read the MII serial port for the MII bit-bang module. 3501 */ 3502 static uint32_t 3503 sipcom_mii_bitbang_read(device_t self) 3504 { 3505 struct sip_softc *sc = device_private(self); 3506 3507 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3508 } 3509 3510 /* 3511 * sip_mii_bitbang_write: [mii big-bang interface function] 3512 * 3513 * Write the MII serial port for the MII bit-bang module. 3514 */ 3515 static void 3516 sipcom_mii_bitbang_write(device_t self, uint32_t val) 3517 { 3518 struct sip_softc *sc = device_private(self); 3519 3520 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3521 } 3522 3523 /* 3524 * sip_sis900_mii_readreg: [mii interface function] 3525 * 3526 * Read a PHY register on the MII. 3527 */ 3528 static int 3529 sipcom_sis900_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3530 { 3531 struct sip_softc *sc = device_private(self); 3532 uint32_t enphy; 3533 3534 /* 3535 * The PHY of recent SiS chipsets is accessed through bitbang 3536 * operations. 3537 */ 3538 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3539 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3540 phy, reg, val); 3541 3542 #ifndef SIS900_MII_RESTRICT 3543 /* 3544 * The SiS 900 has only an internal PHY on the MII. Only allow 3545 * MII address 0. 3546 */ 3547 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3548 return -1; 3549 #endif 3550 3551 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3552 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3553 ENPHY_RWCMD | ENPHY_ACCESS); 3554 do { 3555 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3556 } while (enphy & ENPHY_ACCESS); 3557 3558 *val = (enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT; 3559 return 0; 3560 } 3561 3562 /* 3563 * sip_sis900_mii_writereg: [mii interface function] 3564 * 3565 * Write a PHY register on the MII. 3566 */ 3567 static int 3568 sipcom_sis900_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3569 { 3570 struct sip_softc *sc = device_private(self); 3571 uint32_t enphy; 3572 3573 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3574 return mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3575 phy, reg, val); 3576 } 3577 3578 #ifndef SIS900_MII_RESTRICT 3579 /* 3580 * The SiS 900 has only an internal PHY on the MII. Only allow 3581 * MII address 0. 3582 */ 3583 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3584 return -1; 3585 #endif 3586 3587 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3588 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3589 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3590 do { 3591 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3592 } while (enphy & ENPHY_ACCESS); 3593 3594 return 0; 3595 } 3596 3597 /* 3598 * sip_sis900_mii_statchg: [mii interface function] 3599 * 3600 * Callback from MII layer when media changes. 3601 */ 3602 static void 3603 sipcom_sis900_mii_statchg(struct ifnet *ifp) 3604 { 3605 struct sip_softc *sc = ifp->if_softc; 3606 struct mii_data *mii = &sc->sc_mii; 3607 uint32_t flowctl; 3608 3609 /* 3610 * Get flow control negotiation result. 3611 */ 3612 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3613 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3614 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3615 mii->mii_media_active &= ~IFM_ETH_FMASK; 3616 } 3617 3618 /* 3619 * Update TXCFG for full-duplex operation. 3620 */ 3621 if ((mii->mii_media_active & IFM_FDX) != 0) 3622 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3623 else 3624 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3625 3626 /* 3627 * Update RXCFG for full-duplex or loopback. 3628 */ 3629 if ((mii->mii_media_active & IFM_FDX) != 0 || 3630 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3631 sc->sc_rxcfg |= RXCFG_ATX; 3632 else 3633 sc->sc_rxcfg &= ~RXCFG_ATX; 3634 3635 /* 3636 * Update IMR for use of 802.3x flow control. 3637 */ 3638 if (sc->sc_flowflags & IFM_FLOW) { 3639 sc->sc_imr |= (ISR_PAUSE_END | ISR_PAUSE_ST); 3640 flowctl = FLOWCTL_FLOWEN; 3641 } else { 3642 sc->sc_imr &= ~(ISR_PAUSE_END | ISR_PAUSE_ST); 3643 flowctl = 0; 3644 } 3645 3646 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3647 sc->sc_txcfg); 3648 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3649 sc->sc_rxcfg); 3650 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3651 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3652 } 3653 3654 /* 3655 * sip_dp83815_mii_readreg: [mii interface function] 3656 * 3657 * Read a PHY register on the MII. 3658 */ 3659 static int 3660 sipcom_dp83815_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3661 { 3662 struct sip_softc *sc = device_private(self); 3663 uint32_t data; 3664 3665 /* 3666 * The DP83815 only has an internal PHY. Only allow 3667 * MII address 0. 3668 */ 3669 if (phy != 0) 3670 return -1; 3671 3672 /* 3673 * Apparently, after a reset, the DP83815 can take a while 3674 * to respond. During this recovery period, the BMSR returns 3675 * a value of 0. Catch this -- it's not supposed to happen 3676 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3677 * PHY to come back to life. 3678 * 3679 * This works out because the BMSR is the first register 3680 * read during the PHY probe process. 3681 */ 3682 do { 3683 data = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3684 } while (reg == MII_BMSR && data == 0); 3685 3686 *val = data & 0xffff; 3687 return 0; 3688 } 3689 3690 /* 3691 * sip_dp83815_mii_writereg: [mii interface function] 3692 * 3693 * Write a PHY register to the MII. 3694 */ 3695 static int 3696 sipcom_dp83815_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3697 { 3698 struct sip_softc *sc = device_private(self); 3699 3700 /* 3701 * The DP83815 only has an internal PHY. Only allow 3702 * MII address 0. 3703 */ 3704 if (phy != 0) 3705 return -1; 3706 3707 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3708 3709 return 0; 3710 } 3711 3712 /* 3713 * sip_dp83815_mii_statchg: [mii interface function] 3714 * 3715 * Callback from MII layer when media changes. 3716 */ 3717 static void 3718 sipcom_dp83815_mii_statchg(struct ifnet *ifp) 3719 { 3720 struct sip_softc *sc = ifp->if_softc; 3721 3722 /* 3723 * Update TXCFG for full-duplex operation. 3724 */ 3725 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3726 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3727 else 3728 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3729 3730 /* 3731 * Update RXCFG for full-duplex or loopback. 3732 */ 3733 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3734 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3735 sc->sc_rxcfg |= RXCFG_ATX; 3736 else 3737 sc->sc_rxcfg &= ~RXCFG_ATX; 3738 3739 /* 3740 * XXX 802.3x flow control. 3741 */ 3742 3743 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3744 sc->sc_txcfg); 3745 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3746 sc->sc_rxcfg); 3747 3748 /* 3749 * Some DP83815s experience problems when used with short 3750 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3751 * sequence adjusts the DSP's signal attenuation to fix the 3752 * problem. 3753 */ 3754 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3755 uint32_t reg; 3756 3757 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3758 3759 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3760 reg &= 0x0fff; 3761 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3762 delay(100); 3763 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3764 reg &= 0x00ff; 3765 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3766 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3767 0x00e8); 3768 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3769 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3770 reg | 0x20); 3771 } 3772 3773 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3774 } 3775 } 3776 3777 static void 3778 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3779 const struct pci_attach_args *pa, uint8_t *enaddr) 3780 { 3781 uint16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3782 uint8_t cksum, *e, match; 3783 int i; 3784 3785 /* 3786 * EEPROM data format for the DP83820 can be found in 3787 * the DP83820 manual, section 4.2.4. 3788 */ 3789 3790 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3791 3792 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3793 match = ~(match - 1); 3794 3795 cksum = 0x55; 3796 e = (uint8_t *)eeprom_data; 3797 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3798 cksum += *e++; 3799 3800 if (cksum != match) 3801 printf("%s: Checksum (%x) mismatch (%x)", 3802 device_xname(sc->sc_dev), cksum, match); 3803 3804 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3805 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3806 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3807 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3808 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3809 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3810 } 3811 3812 static void 3813 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3814 { 3815 int i; 3816 3817 /* 3818 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3819 * a reason, but I don't know it. 3820 */ 3821 for (i = 0; i < 10; i++) 3822 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3823 } 3824 3825 static void 3826 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3827 const struct pci_attach_args *pa, uint8_t *enaddr) 3828 { 3829 uint16_t myea[ETHER_ADDR_LEN / 2]; 3830 3831 switch (sc->sc_rev) { 3832 case SIS_REV_630S: 3833 case SIS_REV_630E: 3834 case SIS_REV_630EA1: 3835 case SIS_REV_630ET: 3836 case SIS_REV_635: 3837 /* 3838 * The MAC address for the on-board Ethernet of 3839 * the SiS 630 chipset is in the NVRAM. Kick 3840 * the chip into re-loading it from NVRAM, and 3841 * read the MAC address out of the filter registers. 3842 */ 3843 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3844 3845 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3846 RFCR_RFADDR_NODE0); 3847 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3848 0xffff; 3849 3850 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3851 RFCR_RFADDR_NODE2); 3852 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3853 0xffff; 3854 3855 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3856 RFCR_RFADDR_NODE4); 3857 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3858 0xffff; 3859 break; 3860 3861 case SIS_REV_960: 3862 { 3863 #define SIS_SET_EROMAR(x, y) \ 3864 bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3865 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3866 3867 #define SIS_CLR_EROMAR(x, y) \ 3868 bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3869 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3870 3871 int waittime, i; 3872 3873 /* Allow to read EEPROM from LAN. It is shared 3874 * between a 1394 controller and the NIC and each 3875 * time we access it, we need to set SIS_EECMD_REQ. 3876 */ 3877 SIS_SET_EROMAR(sc, EROMAR_REQ); 3878 3879 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3880 /* Force EEPROM to idle state. */ 3881 3882 /* 3883 * XXX-cube This is ugly. 3884 * I'll look for docs about it. 3885 */ 3886 SIS_SET_EROMAR(sc, EROMAR_EECS); 3887 sipcom_sis900_eeprom_delay(sc); 3888 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3889 SIS_SET_EROMAR(sc, EROMAR_EESK); 3890 sipcom_sis900_eeprom_delay(sc); 3891 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3892 sipcom_sis900_eeprom_delay(sc); 3893 } 3894 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3895 sipcom_sis900_eeprom_delay(sc); 3896 bus_space_write_4(sc->sc_st, sc->sc_sh, 3897 SIP_EROMAR, 0); 3898 3899 if (bus_space_read_4(sc->sc_st, sc->sc_sh, 3900 SIP_EROMAR) & EROMAR_GNT) { 3901 sipcom_read_eeprom(sc, 3902 SIP_EEPROM_ETHERNET_ID0 >> 1, 3903 sizeof(myea) / sizeof(myea[0]), 3904 myea); 3905 break; 3906 } 3907 DELAY(1); 3908 } 3909 3910 /* 3911 * Set SIS_EECTL_CLK to high, so a other master 3912 * can operate on the i2c bus. 3913 */ 3914 SIS_SET_EROMAR(sc, EROMAR_EESK); 3915 3916 /* Refuse EEPROM access by LAN */ 3917 SIS_SET_EROMAR(sc, EROMAR_DONE); 3918 } break; 3919 3920 default: 3921 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3922 sizeof(myea) / sizeof(myea[0]), myea); 3923 } 3924 3925 enaddr[0] = myea[0] & 0xff; 3926 enaddr[1] = myea[0] >> 8; 3927 enaddr[2] = myea[1] & 0xff; 3928 enaddr[3] = myea[1] >> 8; 3929 enaddr[4] = myea[2] & 0xff; 3930 enaddr[5] = myea[2] >> 8; 3931 } 3932 3933 /* Table and macro to bit-reverse an octet. */ 3934 static const uint8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3935 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3936 3937 static void 3938 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3939 const struct pci_attach_args *pa, uint8_t *enaddr) 3940 { 3941 uint16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3942 uint8_t cksum, *e, match; 3943 int i; 3944 3945 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3946 sizeof(eeprom_data[0]), eeprom_data); 3947 3948 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3949 match = ~(match - 1); 3950 3951 cksum = 0x55; 3952 e = (uint8_t *)eeprom_data; 3953 for (i = 0; i < SIP_DP83815_EEPROM_CHECKSUM; i++) 3954 cksum += *e++; 3955 3956 if (cksum != match) 3957 printf("%s: Checksum (%x) mismatch (%x)", 3958 device_xname(sc->sc_dev), cksum, match); 3959 3960 /* 3961 * Unrolled because it makes slightly more sense this way. 3962 * The DP83815 stores the MAC address in bit 0 of word 6 3963 * through bit 15 of word 8. 3964 */ 3965 ea = &eeprom_data[6]; 3966 enaddr[0] = ((*ea & 0x1) << 7); 3967 ea++; 3968 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3969 enaddr[1] = ((*ea & 0x1FE) >> 1); 3970 enaddr[2] = ((*ea & 0x1) << 7); 3971 ea++; 3972 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3973 enaddr[3] = ((*ea & 0x1FE) >> 1); 3974 enaddr[4] = ((*ea & 0x1) << 7); 3975 ea++; 3976 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3977 enaddr[5] = ((*ea & 0x1FE) >> 1); 3978 3979 /* 3980 * In case that's not weird enough, we also need to reverse 3981 * the bits in each byte. This all actually makes more sense 3982 * if you think about the EEPROM storage as an array of bits 3983 * being shifted into bytes, but that's not how we're looking 3984 * at it here... 3985 */ 3986 for (i = 0; i < 6 ;i++) 3987 enaddr[i] = bbr(enaddr[i]); 3988 } 3989 3990 /* 3991 * sip_mediastatus: [ifmedia interface function] 3992 * 3993 * Get the current interface media status. 3994 */ 3995 static void 3996 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3997 { 3998 struct sip_softc *sc = ifp->if_softc; 3999 4000 if (!device_is_active(sc->sc_dev)) { 4001 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 4002 ifmr->ifm_status = 0; 4003 return; 4004 } 4005 ether_mediastatus(ifp, ifmr); 4006 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) | 4007 sc->sc_flowflags; 4008 } 4009
Indexes created Tue Sep 30 17:09:57 GMT 2025