if_sip.c revision 1.24.2.10
1 /* $NetBSD: if_sip.c,v 1.24.2.10 2002/08/13 02:19:38 nathanw Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.24.2.10 2002/08/13 02:19:38 nathanw Exp $"); 84 85 #include "bpfilter.h" 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/callout.h> 90 #include <sys/mbuf.h> 91 #include <sys/malloc.h> 92 #include <sys/kernel.h> 93 #include <sys/socket.h> 94 #include <sys/ioctl.h> 95 #include <sys/errno.h> 96 #include <sys/device.h> 97 #include <sys/queue.h> 98 99 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 100 101 #include <net/if.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 #include <net/if_ether.h> 105 106 #if NBPFILTER > 0 107 #include <net/bpf.h> 108 #endif 109 110 #include <machine/bus.h> 111 #include <machine/intr.h> 112 #include <machine/endian.h> 113 114 #include <dev/mii/mii.h> 115 #include <dev/mii/miivar.h> 116 #ifdef DP83820 117 #include <dev/mii/mii_bitbang.h> 118 #endif /* DP83820 */ 119 120 #include <dev/pci/pcireg.h> 121 #include <dev/pci/pcivar.h> 122 #include <dev/pci/pcidevs.h> 123 124 #include <dev/pci/if_sipreg.h> 125 126 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 127 #define SIP_DECL(x) __CONCAT(gsip_,x) 128 #else /* SiS900 and DP83815 */ 129 #define SIP_DECL(x) __CONCAT(sip_,x) 130 #endif 131 132 #define SIP_STR(x) __STRING(SIP_DECL(x)) 133 134 /* 135 * Transmit descriptor list size. This is arbitrary, but allocate 136 * enough descriptors for 128 pending transmissions, and 8 segments 137 * per packet. This MUST work out to a power of 2. 138 */ 139 #define SIP_NTXSEGS 16 140 #define SIP_NTXSEGS_ALLOC 8 141 142 #define SIP_TXQUEUELEN 256 143 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 144 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 145 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 146 147 #if defined(DP83020) 148 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 149 #else 150 #define TX_DMAMAP_SIZE MCLBYTES 151 #endif 152 153 /* 154 * Receive descriptor list size. We have one Rx buffer per incoming 155 * packet, so this logic is a little simpler. 156 * 157 * Actually, on the DP83820, we allow the packet to consume more than 158 * one buffer, in order to support jumbo Ethernet frames. In that 159 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 160 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 161 * so we'd better be quick about handling receive interrupts. 162 */ 163 #if defined(DP83820) 164 #define SIP_NRXDESC 256 165 #else 166 #define SIP_NRXDESC 128 167 #endif /* DP83820 */ 168 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 169 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 170 171 /* 172 * Control structures are DMA'd to the SiS900 chip. We allocate them in 173 * a single clump that maps to a single DMA segment to make several things 174 * easier. 175 */ 176 struct sip_control_data { 177 /* 178 * The transmit descriptors. 179 */ 180 struct sip_desc scd_txdescs[SIP_NTXDESC]; 181 182 /* 183 * The receive descriptors. 184 */ 185 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 186 }; 187 188 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 189 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 190 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 191 192 /* 193 * Software state for transmit jobs. 194 */ 195 struct sip_txsoft { 196 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 197 bus_dmamap_t txs_dmamap; /* our DMA map */ 198 int txs_firstdesc; /* first descriptor in packet */ 199 int txs_lastdesc; /* last descriptor in packet */ 200 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 201 }; 202 203 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 204 205 /* 206 * Software state for receive jobs. 207 */ 208 struct sip_rxsoft { 209 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 210 bus_dmamap_t rxs_dmamap; /* our DMA map */ 211 }; 212 213 /* 214 * Software state per device. 215 */ 216 struct sip_softc { 217 struct device sc_dev; /* generic device information */ 218 bus_space_tag_t sc_st; /* bus space tag */ 219 bus_space_handle_t sc_sh; /* bus space handle */ 220 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 221 struct ethercom sc_ethercom; /* ethernet common data */ 222 void *sc_sdhook; /* shutdown hook */ 223 224 const struct sip_product *sc_model; /* which model are we? */ 225 int sc_rev; /* chip revision */ 226 227 void *sc_ih; /* interrupt cookie */ 228 229 struct mii_data sc_mii; /* MII/media information */ 230 231 struct callout sc_tick_ch; /* tick callout */ 232 233 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 234 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 235 236 /* 237 * Software state for transmit and receive descriptors. 238 */ 239 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 240 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 241 242 /* 243 * Control data structures. 244 */ 245 struct sip_control_data *sc_control_data; 246 #define sc_txdescs sc_control_data->scd_txdescs 247 #define sc_rxdescs sc_control_data->scd_rxdescs 248 249 #ifdef SIP_EVENT_COUNTERS 250 /* 251 * Event counters. 252 */ 253 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 254 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 255 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 256 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 257 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 258 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 259 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 260 #ifdef DP83820 261 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 262 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 263 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 264 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 265 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 266 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 267 #endif /* DP83820 */ 268 #endif /* SIP_EVENT_COUNTERS */ 269 270 u_int32_t sc_txcfg; /* prototype TXCFG register */ 271 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 272 u_int32_t sc_imr; /* prototype IMR register */ 273 u_int32_t sc_rfcr; /* prototype RFCR register */ 274 275 u_int32_t sc_cfg; /* prototype CFG register */ 276 277 #ifdef DP83820 278 u_int32_t sc_gpior; /* prototype GPIOR register */ 279 #endif /* DP83820 */ 280 281 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 282 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 283 284 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 285 286 int sc_flags; /* misc. flags; see below */ 287 288 int sc_txfree; /* number of free Tx descriptors */ 289 int sc_txnext; /* next ready Tx descriptor */ 290 int sc_txwin; /* Tx descriptors since last intr */ 291 292 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 293 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 294 295 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 296 #if defined(DP83820) 297 int sc_rxdiscard; 298 int sc_rxlen; 299 struct mbuf *sc_rxhead; 300 struct mbuf *sc_rxtail; 301 struct mbuf **sc_rxtailp; 302 #endif /* DP83820 */ 303 }; 304 305 /* sc_flags */ 306 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 307 308 #ifdef DP83820 309 #define SIP_RXCHAIN_RESET(sc) \ 310 do { \ 311 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 312 *(sc)->sc_rxtailp = NULL; \ 313 (sc)->sc_rxlen = 0; \ 314 } while (/*CONSTCOND*/0) 315 316 #define SIP_RXCHAIN_LINK(sc, m) \ 317 do { \ 318 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 319 (sc)->sc_rxtailp = &(m)->m_next; \ 320 } while (/*CONSTCOND*/0) 321 #endif /* DP83820 */ 322 323 #ifdef SIP_EVENT_COUNTERS 324 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 325 #else 326 #define SIP_EVCNT_INCR(ev) /* nothing */ 327 #endif 328 329 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 330 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 331 332 #define SIP_CDTXSYNC(sc, x, n, ops) \ 333 do { \ 334 int __x, __n; \ 335 \ 336 __x = (x); \ 337 __n = (n); \ 338 \ 339 /* If it will wrap around, sync to the end of the ring. */ \ 340 if ((__x + __n) > SIP_NTXDESC) { \ 341 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 342 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 343 (SIP_NTXDESC - __x), (ops)); \ 344 __n -= (SIP_NTXDESC - __x); \ 345 __x = 0; \ 346 } \ 347 \ 348 /* Now sync whatever is left. */ \ 349 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 350 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 351 } while (0) 352 353 #define SIP_CDRXSYNC(sc, x, ops) \ 354 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 355 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 356 357 #ifdef DP83820 358 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 359 #define SIP_RXBUF_LEN (MCLBYTES - 4) 360 #else 361 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 362 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 363 #endif 364 #define SIP_INIT_RXDESC(sc, x) \ 365 do { \ 366 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 367 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 368 \ 369 __sipd->sipd_link = \ 370 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 371 __sipd->sipd_bufptr = \ 372 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 373 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 374 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 375 SIP_INIT_RXDESC_EXTSTS \ 376 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 377 } while (0) 378 379 #define SIP_CHIP_VERS(sc, v, p, r) \ 380 ((sc)->sc_model->sip_vendor == (v) && \ 381 (sc)->sc_model->sip_product == (p) && \ 382 (sc)->sc_rev == (r)) 383 384 #define SIP_CHIP_MODEL(sc, v, p) \ 385 ((sc)->sc_model->sip_vendor == (v) && \ 386 (sc)->sc_model->sip_product == (p)) 387 388 #if !defined(DP83820) 389 #define SIP_SIS900_REV(sc, rev) \ 390 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 391 #endif 392 393 #define SIP_TIMEOUT 1000 394 395 void SIP_DECL(start)(struct ifnet *); 396 void SIP_DECL(watchdog)(struct ifnet *); 397 int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 398 int SIP_DECL(init)(struct ifnet *); 399 void SIP_DECL(stop)(struct ifnet *, int); 400 401 void SIP_DECL(shutdown)(void *); 402 403 void SIP_DECL(reset)(struct sip_softc *); 404 void SIP_DECL(rxdrain)(struct sip_softc *); 405 int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 406 void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, u_int16_t *); 407 void SIP_DECL(tick)(void *); 408 409 #if !defined(DP83820) 410 void SIP_DECL(sis900_set_filter)(struct sip_softc *); 411 #endif /* ! DP83820 */ 412 void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 413 414 #if defined(DP83820) 415 void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 416 const struct pci_attach_args *, u_int8_t *); 417 #else 418 void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 419 const struct pci_attach_args *, u_int8_t *); 420 void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 421 const struct pci_attach_args *, u_int8_t *); 422 #endif /* DP83820 */ 423 424 int SIP_DECL(intr)(void *); 425 void SIP_DECL(txintr)(struct sip_softc *); 426 void SIP_DECL(rxintr)(struct sip_softc *); 427 428 #if defined(DP83820) 429 int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 430 void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 431 void SIP_DECL(dp83820_mii_statchg)(struct device *); 432 #else 433 int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 434 void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 435 void SIP_DECL(sis900_mii_statchg)(struct device *); 436 437 int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 438 void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 439 void SIP_DECL(dp83815_mii_statchg)(struct device *); 440 #endif /* DP83820 */ 441 442 int SIP_DECL(mediachange)(struct ifnet *); 443 void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 444 445 int SIP_DECL(match)(struct device *, struct cfdata *, void *); 446 void SIP_DECL(attach)(struct device *, struct device *, void *); 447 448 int SIP_DECL(copy_small) = 0; 449 450 struct cfattach SIP_DECL(ca) = { 451 sizeof(struct sip_softc), SIP_DECL(match), SIP_DECL(attach), 452 }; 453 454 /* 455 * Descriptions of the variants of the SiS900. 456 */ 457 struct sip_variant { 458 int (*sipv_mii_readreg)(struct device *, int, int); 459 void (*sipv_mii_writereg)(struct device *, int, int, int); 460 void (*sipv_mii_statchg)(struct device *); 461 void (*sipv_set_filter)(struct sip_softc *); 462 void (*sipv_read_macaddr)(struct sip_softc *, 463 const struct pci_attach_args *, u_int8_t *); 464 }; 465 466 #if defined(DP83820) 467 u_int32_t SIP_DECL(dp83820_mii_bitbang_read)(struct device *); 468 void SIP_DECL(dp83820_mii_bitbang_write)(struct device *, u_int32_t); 469 470 const struct mii_bitbang_ops SIP_DECL(dp83820_mii_bitbang_ops) = { 471 SIP_DECL(dp83820_mii_bitbang_read), 472 SIP_DECL(dp83820_mii_bitbang_write), 473 { 474 EROMAR_MDIO, /* MII_BIT_MDO */ 475 EROMAR_MDIO, /* MII_BIT_MDI */ 476 EROMAR_MDC, /* MII_BIT_MDC */ 477 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 478 0, /* MII_BIT_DIR_PHY_HOST */ 479 } 480 }; 481 #endif /* DP83820 */ 482 483 #if defined(DP83820) 484 const struct sip_variant SIP_DECL(variant_dp83820) = { 485 SIP_DECL(dp83820_mii_readreg), 486 SIP_DECL(dp83820_mii_writereg), 487 SIP_DECL(dp83820_mii_statchg), 488 SIP_DECL(dp83815_set_filter), 489 SIP_DECL(dp83820_read_macaddr), 490 }; 491 #else 492 const struct sip_variant SIP_DECL(variant_sis900) = { 493 SIP_DECL(sis900_mii_readreg), 494 SIP_DECL(sis900_mii_writereg), 495 SIP_DECL(sis900_mii_statchg), 496 SIP_DECL(sis900_set_filter), 497 SIP_DECL(sis900_read_macaddr), 498 }; 499 500 const struct sip_variant SIP_DECL(variant_dp83815) = { 501 SIP_DECL(dp83815_mii_readreg), 502 SIP_DECL(dp83815_mii_writereg), 503 SIP_DECL(dp83815_mii_statchg), 504 SIP_DECL(dp83815_set_filter), 505 SIP_DECL(dp83815_read_macaddr), 506 }; 507 #endif /* DP83820 */ 508 509 /* 510 * Devices supported by this driver. 511 */ 512 const struct sip_product { 513 pci_vendor_id_t sip_vendor; 514 pci_product_id_t sip_product; 515 const char *sip_name; 516 const struct sip_variant *sip_variant; 517 } SIP_DECL(products)[] = { 518 #if defined(DP83820) 519 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 520 "NatSemi DP83820 Gigabit Ethernet", 521 &SIP_DECL(variant_dp83820) }, 522 #else 523 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 524 "SiS 900 10/100 Ethernet", 525 &SIP_DECL(variant_sis900) }, 526 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 527 "SiS 7016 10/100 Ethernet", 528 &SIP_DECL(variant_sis900) }, 529 530 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 531 "NatSemi DP83815 10/100 Ethernet", 532 &SIP_DECL(variant_dp83815) }, 533 #endif /* DP83820 */ 534 535 { 0, 0, 536 NULL, 537 NULL }, 538 }; 539 540 static const struct sip_product * 541 SIP_DECL(lookup)(const struct pci_attach_args *pa) 542 { 543 const struct sip_product *sip; 544 545 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 546 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 547 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 548 return (sip); 549 } 550 return (NULL); 551 } 552 553 #ifdef DP83820 554 /* 555 * I really hate stupid hardware vendors. There's a bit in the EEPROM 556 * which indicates if the card can do 64-bit data transfers. Unfortunately, 557 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 558 * which means we try to use 64-bit data transfers on those cards if we 559 * happen to be plugged into a 32-bit slot. 560 * 561 * What we do is use this table of cards known to be 64-bit cards. If 562 * you have a 64-bit card who's subsystem ID is not listed in this table, 563 * send the output of "pcictl dump ..." of the device to me so that your 564 * card will use the 64-bit data path when plugged into a 64-bit slot. 565 * 566 * -- Jason R. Thorpe <thorpej (at) netbsd.org> 567 * June 30, 2002 568 */ 569 static int 570 SIP_DECL(check_64bit)(const struct pci_attach_args *pa) 571 { 572 static const struct { 573 pci_vendor_id_t c64_vendor; 574 pci_product_id_t c64_product; 575 } card64[] = { 576 /* Asante GigaNIX */ 577 { 0x128a, 0x0002 }, 578 579 /* Accton EN1407-T, Planex GN-1000TE */ 580 { 0x1113, 0x1407 }, 581 582 { 0, 0} 583 }; 584 pcireg_t subsys; 585 int i; 586 587 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 588 589 for (i = 0; card64[i].c64_vendor != 0; i++) { 590 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 591 PCI_PRODUCT(subsys) == card64[i].c64_product) 592 return (1); 593 } 594 595 return (0); 596 } 597 #endif /* DP83820 */ 598 599 int 600 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 601 { 602 struct pci_attach_args *pa = aux; 603 604 if (SIP_DECL(lookup)(pa) != NULL) 605 return (1); 606 607 return (0); 608 } 609 610 void 611 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 612 { 613 struct sip_softc *sc = (struct sip_softc *) self; 614 struct pci_attach_args *pa = aux; 615 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 616 pci_chipset_tag_t pc = pa->pa_pc; 617 pci_intr_handle_t ih; 618 const char *intrstr = NULL; 619 bus_space_tag_t iot, memt; 620 bus_space_handle_t ioh, memh; 621 bus_dma_segment_t seg; 622 int ioh_valid, memh_valid; 623 int i, rseg, error; 624 const struct sip_product *sip; 625 pcireg_t pmode; 626 u_int8_t enaddr[ETHER_ADDR_LEN]; 627 int pmreg; 628 #ifdef DP83820 629 pcireg_t memtype; 630 u_int32_t reg; 631 #endif /* DP83820 */ 632 633 callout_init(&sc->sc_tick_ch); 634 635 sip = SIP_DECL(lookup)(pa); 636 if (sip == NULL) { 637 printf("\n"); 638 panic(SIP_STR(attach) ": impossible"); 639 } 640 sc->sc_rev = PCI_REVISION(pa->pa_class); 641 642 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 643 644 sc->sc_model = sip; 645 646 /* 647 * XXX Work-around broken PXE firmware on some boards. 648 * 649 * The DP83815 shares an address decoder with the MEM BAR 650 * and the ROM BAR. Make sure the ROM BAR is disabled, 651 * so that memory mapped access works. 652 */ 653 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 654 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 655 ~PCI_MAPREG_ROM_ENABLE); 656 657 /* 658 * Map the device. 659 */ 660 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 661 PCI_MAPREG_TYPE_IO, 0, 662 &iot, &ioh, NULL, NULL) == 0); 663 #ifdef DP83820 664 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 665 switch (memtype) { 666 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 667 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 668 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 669 memtype, 0, &memt, &memh, NULL, NULL) == 0); 670 break; 671 default: 672 memh_valid = 0; 673 } 674 #else 675 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 676 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 677 &memt, &memh, NULL, NULL) == 0); 678 #endif /* DP83820 */ 679 680 if (memh_valid) { 681 sc->sc_st = memt; 682 sc->sc_sh = memh; 683 } else if (ioh_valid) { 684 sc->sc_st = iot; 685 sc->sc_sh = ioh; 686 } else { 687 printf("%s: unable to map device registers\n", 688 sc->sc_dev.dv_xname); 689 return; 690 } 691 692 sc->sc_dmat = pa->pa_dmat; 693 694 /* 695 * Make sure bus mastering is enabled. Also make sure 696 * Write/Invalidate is enabled if we're allowed to use it. 697 */ 698 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 699 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 700 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 701 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 702 pmreg | PCI_COMMAND_MASTER_ENABLE); 703 704 /* Get it out of power save mode if needed. */ 705 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 706 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 707 if (pmode == 3) { 708 /* 709 * The card has lost all configuration data in 710 * this state, so punt. 711 */ 712 printf("%s: unable to wake up from power state D3\n", 713 sc->sc_dev.dv_xname); 714 return; 715 } 716 if (pmode != 0) { 717 printf("%s: waking up from power state D%d\n", 718 sc->sc_dev.dv_xname, pmode); 719 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 720 } 721 } 722 723 /* 724 * Map and establish our interrupt. 725 */ 726 if (pci_intr_map(pa, &ih)) { 727 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 728 return; 729 } 730 intrstr = pci_intr_string(pc, ih); 731 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 732 if (sc->sc_ih == NULL) { 733 printf("%s: unable to establish interrupt", 734 sc->sc_dev.dv_xname); 735 if (intrstr != NULL) 736 printf(" at %s", intrstr); 737 printf("\n"); 738 return; 739 } 740 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 741 742 SIMPLEQ_INIT(&sc->sc_txfreeq); 743 SIMPLEQ_INIT(&sc->sc_txdirtyq); 744 745 /* 746 * Allocate the control data structures, and create and load the 747 * DMA map for it. 748 */ 749 if ((error = bus_dmamem_alloc(sc->sc_dmat, 750 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 751 0)) != 0) { 752 printf("%s: unable to allocate control data, error = %d\n", 753 sc->sc_dev.dv_xname, error); 754 goto fail_0; 755 } 756 757 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 758 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 759 BUS_DMA_COHERENT)) != 0) { 760 printf("%s: unable to map control data, error = %d\n", 761 sc->sc_dev.dv_xname, error); 762 goto fail_1; 763 } 764 765 if ((error = bus_dmamap_create(sc->sc_dmat, 766 sizeof(struct sip_control_data), 1, 767 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 768 printf("%s: unable to create control data DMA map, " 769 "error = %d\n", sc->sc_dev.dv_xname, error); 770 goto fail_2; 771 } 772 773 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 774 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 775 0)) != 0) { 776 printf("%s: unable to load control data DMA map, error = %d\n", 777 sc->sc_dev.dv_xname, error); 778 goto fail_3; 779 } 780 781 /* 782 * Create the transmit buffer DMA maps. 783 */ 784 for (i = 0; i < SIP_TXQUEUELEN; i++) { 785 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 786 SIP_NTXSEGS, MCLBYTES, 0, 0, 787 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 788 printf("%s: unable to create tx DMA map %d, " 789 "error = %d\n", sc->sc_dev.dv_xname, i, error); 790 goto fail_4; 791 } 792 } 793 794 /* 795 * Create the receive buffer DMA maps. 796 */ 797 for (i = 0; i < SIP_NRXDESC; i++) { 798 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 799 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 800 printf("%s: unable to create rx DMA map %d, " 801 "error = %d\n", sc->sc_dev.dv_xname, i, error); 802 goto fail_5; 803 } 804 sc->sc_rxsoft[i].rxs_mbuf = NULL; 805 } 806 807 /* 808 * Reset the chip to a known state. 809 */ 810 SIP_DECL(reset)(sc); 811 812 /* 813 * Read the Ethernet address from the EEPROM. This might 814 * also fetch other stuff from the EEPROM and stash it 815 * in the softc. 816 */ 817 sc->sc_cfg = 0; 818 #if !defined(DP83820) 819 if (SIP_SIS900_REV(sc,SIS_REV_635) || 820 SIP_SIS900_REV(sc,SIS_REV_900B)) 821 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 822 #endif 823 824 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 825 826 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 827 ether_sprintf(enaddr)); 828 829 /* 830 * Initialize the configuration register: aggressive PCI 831 * bus request algorithm, default backoff, default OW timer, 832 * default parity error detection. 833 * 834 * NOTE: "Big endian mode" is useless on the SiS900 and 835 * friends -- it affects packet data, not descriptors. 836 */ 837 #ifdef DP83820 838 /* 839 * Cause the chip to load configuration data from the EEPROM. 840 */ 841 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 842 for (i = 0; i < 10000; i++) { 843 delay(10); 844 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 845 PTSCR_EELOAD_EN) == 0) 846 break; 847 } 848 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 849 PTSCR_EELOAD_EN) { 850 printf("%s: timeout loading configuration from EEPROM\n", 851 sc->sc_dev.dv_xname); 852 return; 853 } 854 855 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 856 if (reg & CFG_PCI64_DET) { 857 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 858 /* 859 * Check to see if this card is 64-bit. If so, enable 64-bit 860 * data transfers. 861 * 862 * We can't use the DATA64_EN bit in the EEPROM, because 863 * vendors of 32-bit cards fail to clear that bit in many 864 * cases (yet the card still detects that it's in a 64-bit 865 * slot; go figure). 866 */ 867 if (SIP_DECL(check_64bit)(pa)) { 868 sc->sc_cfg |= CFG_DATA64_EN; 869 printf(", using 64-bit data transfers"); 870 } 871 printf("\n"); 872 } 873 874 /* 875 * XXX Need some PCI flags indicating support for 876 * XXX 64-bit addressing. 877 */ 878 #if 0 879 if (reg & CFG_M64ADDR) 880 sc->sc_cfg |= CFG_M64ADDR; 881 if (reg & CFG_T64ADDR) 882 sc->sc_cfg |= CFG_T64ADDR; 883 #endif 884 885 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 886 const char *sep = ""; 887 printf("%s: using ", sc->sc_dev.dv_xname); 888 if (reg & CFG_EXT_125) { 889 sc->sc_cfg |= CFG_EXT_125; 890 printf("%s125MHz clock", sep); 891 sep = ", "; 892 } 893 if (reg & CFG_TBI_EN) { 894 sc->sc_cfg |= CFG_TBI_EN; 895 printf("%sten-bit interface", sep); 896 sep = ", "; 897 } 898 printf("\n"); 899 } 900 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 901 (reg & CFG_MRM_DIS) != 0) 902 sc->sc_cfg |= CFG_MRM_DIS; 903 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 904 (reg & CFG_MWI_DIS) != 0) 905 sc->sc_cfg |= CFG_MWI_DIS; 906 907 /* 908 * Use the extended descriptor format on the DP83820. This 909 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 910 * checksumming. 911 */ 912 sc->sc_cfg |= CFG_EXTSTS_EN; 913 #endif /* DP83820 */ 914 915 /* 916 * Initialize our media structures and probe the MII. 917 */ 918 sc->sc_mii.mii_ifp = ifp; 919 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 920 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 921 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 922 ifmedia_init(&sc->sc_mii.mii_media, 0, SIP_DECL(mediachange), 923 SIP_DECL(mediastatus)); 924 925 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 926 MII_OFFSET_ANY, 0); 927 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 928 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 929 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 930 } else 931 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 932 933 ifp = &sc->sc_ethercom.ec_if; 934 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 935 ifp->if_softc = sc; 936 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 937 ifp->if_ioctl = SIP_DECL(ioctl); 938 ifp->if_start = SIP_DECL(start); 939 ifp->if_watchdog = SIP_DECL(watchdog); 940 ifp->if_init = SIP_DECL(init); 941 ifp->if_stop = SIP_DECL(stop); 942 IFQ_SET_READY(&ifp->if_snd); 943 944 /* 945 * We can support 802.1Q VLAN-sized frames. 946 */ 947 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 948 949 #ifdef DP83820 950 /* 951 * And the DP83820 can do VLAN tagging in hardware, and 952 * support the jumbo Ethernet MTU. 953 */ 954 sc->sc_ethercom.ec_capabilities |= 955 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 956 957 /* 958 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 959 * in hardware. 960 */ 961 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 962 IFCAP_CSUM_UDPv4; 963 #endif /* DP83820 */ 964 965 /* 966 * Attach the interface. 967 */ 968 if_attach(ifp); 969 ether_ifattach(ifp, enaddr); 970 971 /* 972 * The number of bytes that must be available in 973 * the Tx FIFO before the bus master can DMA more 974 * data into the FIFO. 975 */ 976 sc->sc_tx_fill_thresh = 64 / 32; 977 978 /* 979 * Start at a drain threshold of 512 bytes. We will 980 * increase it if a DMA underrun occurs. 981 * 982 * XXX The minimum value of this variable should be 983 * tuned. We may be able to improve performance 984 * by starting with a lower value. That, however, 985 * may trash the first few outgoing packets if the 986 * PCI bus is saturated. 987 */ 988 sc->sc_tx_drain_thresh = 1504 / 32; 989 990 /* 991 * Initialize the Rx FIFO drain threshold. 992 * 993 * This is in units of 8 bytes. 994 * 995 * We should never set this value lower than 2; 14 bytes are 996 * required to filter the packet. 997 */ 998 sc->sc_rx_drain_thresh = 128 / 8; 999 1000 #ifdef SIP_EVENT_COUNTERS 1001 /* 1002 * Attach event counters. 1003 */ 1004 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1005 NULL, sc->sc_dev.dv_xname, "txsstall"); 1006 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1007 NULL, sc->sc_dev.dv_xname, "txdstall"); 1008 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1009 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1010 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1011 NULL, sc->sc_dev.dv_xname, "txdintr"); 1012 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1013 NULL, sc->sc_dev.dv_xname, "txiintr"); 1014 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1015 NULL, sc->sc_dev.dv_xname, "rxintr"); 1016 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1017 NULL, sc->sc_dev.dv_xname, "hiberr"); 1018 #ifdef DP83820 1019 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1020 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1021 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1022 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1023 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1024 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1025 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1026 NULL, sc->sc_dev.dv_xname, "txipsum"); 1027 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1028 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1029 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1030 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1031 #endif /* DP83820 */ 1032 #endif /* SIP_EVENT_COUNTERS */ 1033 1034 /* 1035 * Make sure the interface is shutdown during reboot. 1036 */ 1037 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 1038 if (sc->sc_sdhook == NULL) 1039 printf("%s: WARNING: unable to establish shutdown hook\n", 1040 sc->sc_dev.dv_xname); 1041 return; 1042 1043 /* 1044 * Free any resources we've allocated during the failed attach 1045 * attempt. Do this in reverse order and fall through. 1046 */ 1047 fail_5: 1048 for (i = 0; i < SIP_NRXDESC; i++) { 1049 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1050 bus_dmamap_destroy(sc->sc_dmat, 1051 sc->sc_rxsoft[i].rxs_dmamap); 1052 } 1053 fail_4: 1054 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1055 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1056 bus_dmamap_destroy(sc->sc_dmat, 1057 sc->sc_txsoft[i].txs_dmamap); 1058 } 1059 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1060 fail_3: 1061 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1062 fail_2: 1063 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1064 sizeof(struct sip_control_data)); 1065 fail_1: 1066 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1067 fail_0: 1068 return; 1069 } 1070 1071 /* 1072 * sip_shutdown: 1073 * 1074 * Make sure the interface is stopped at reboot time. 1075 */ 1076 void 1077 SIP_DECL(shutdown)(void *arg) 1078 { 1079 struct sip_softc *sc = arg; 1080 1081 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1082 } 1083 1084 /* 1085 * sip_start: [ifnet interface function] 1086 * 1087 * Start packet transmission on the interface. 1088 */ 1089 void 1090 SIP_DECL(start)(struct ifnet *ifp) 1091 { 1092 struct sip_softc *sc = ifp->if_softc; 1093 struct mbuf *m0, *m; 1094 struct sip_txsoft *txs; 1095 bus_dmamap_t dmamap; 1096 int error, nexttx, lasttx, seg; 1097 int ofree = sc->sc_txfree; 1098 #if 0 1099 int firsttx = sc->sc_txnext; 1100 #endif 1101 #ifdef DP83820 1102 u_int32_t extsts; 1103 #endif 1104 1105 /* 1106 * If we've been told to pause, don't transmit any more packets. 1107 */ 1108 if (sc->sc_flags & SIPF_PAUSED) 1109 ifp->if_flags |= IFF_OACTIVE; 1110 1111 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1112 return; 1113 1114 /* 1115 * Loop through the send queue, setting up transmit descriptors 1116 * until we drain the queue, or use up all available transmit 1117 * descriptors. 1118 */ 1119 for (;;) { 1120 /* Get a work queue entry. */ 1121 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1122 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1123 break; 1124 } 1125 1126 /* 1127 * Grab a packet off the queue. 1128 */ 1129 IFQ_POLL(&ifp->if_snd, m0); 1130 if (m0 == NULL) 1131 break; 1132 #ifndef DP83820 1133 m = NULL; 1134 #endif 1135 1136 dmamap = txs->txs_dmamap; 1137 1138 #ifdef DP83820 1139 /* 1140 * Load the DMA map. If this fails, the packet either 1141 * didn't fit in the allotted number of segments, or we 1142 * were short on resources. For the too-many-segments 1143 * case, we simply report an error and drop the packet, 1144 * since we can't sanely copy a jumbo packet to a single 1145 * buffer. 1146 */ 1147 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1148 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1149 if (error) { 1150 if (error == EFBIG) { 1151 printf("%s: Tx packet consumes too many " 1152 "DMA segments, dropping...\n", 1153 sc->sc_dev.dv_xname); 1154 IFQ_DEQUEUE(&ifp->if_snd, m0); 1155 m_freem(m0); 1156 continue; 1157 } 1158 /* 1159 * Short on resources, just stop for now. 1160 */ 1161 break; 1162 } 1163 #else /* DP83820 */ 1164 /* 1165 * Load the DMA map. If this fails, the packet either 1166 * didn't fit in the alloted number of segments, or we 1167 * were short on resources. In this case, we'll copy 1168 * and try again. 1169 */ 1170 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1171 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1172 MGETHDR(m, M_DONTWAIT, MT_DATA); 1173 if (m == NULL) { 1174 printf("%s: unable to allocate Tx mbuf\n", 1175 sc->sc_dev.dv_xname); 1176 break; 1177 } 1178 if (m0->m_pkthdr.len > MHLEN) { 1179 MCLGET(m, M_DONTWAIT); 1180 if ((m->m_flags & M_EXT) == 0) { 1181 printf("%s: unable to allocate Tx " 1182 "cluster\n", sc->sc_dev.dv_xname); 1183 m_freem(m); 1184 break; 1185 } 1186 } 1187 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1188 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1189 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1190 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1191 if (error) { 1192 printf("%s: unable to load Tx buffer, " 1193 "error = %d\n", sc->sc_dev.dv_xname, error); 1194 break; 1195 } 1196 } 1197 #endif /* DP83820 */ 1198 1199 /* 1200 * Ensure we have enough descriptors free to describe 1201 * the packet. Note, we always reserve one descriptor 1202 * at the end of the ring as a termination point, to 1203 * prevent wrap-around. 1204 */ 1205 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1206 /* 1207 * Not enough free descriptors to transmit this 1208 * packet. We haven't committed anything yet, 1209 * so just unload the DMA map, put the packet 1210 * back on the queue, and punt. Notify the upper 1211 * layer that there are not more slots left. 1212 * 1213 * XXX We could allocate an mbuf and copy, but 1214 * XXX is it worth it? 1215 */ 1216 ifp->if_flags |= IFF_OACTIVE; 1217 bus_dmamap_unload(sc->sc_dmat, dmamap); 1218 #ifndef DP83820 1219 if (m != NULL) 1220 m_freem(m); 1221 #endif 1222 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1223 break; 1224 } 1225 1226 IFQ_DEQUEUE(&ifp->if_snd, m0); 1227 #ifndef DP83820 1228 if (m != NULL) { 1229 m_freem(m0); 1230 m0 = m; 1231 } 1232 #endif 1233 1234 /* 1235 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1236 */ 1237 1238 /* Sync the DMA map. */ 1239 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1240 BUS_DMASYNC_PREWRITE); 1241 1242 /* 1243 * Initialize the transmit descriptors. 1244 */ 1245 for (nexttx = sc->sc_txnext, seg = 0; 1246 seg < dmamap->dm_nsegs; 1247 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1248 /* 1249 * If this is the first descriptor we're 1250 * enqueueing, don't set the OWN bit just 1251 * yet. That could cause a race condition. 1252 * We'll do it below. 1253 */ 1254 sc->sc_txdescs[nexttx].sipd_bufptr = 1255 htole32(dmamap->dm_segs[seg].ds_addr); 1256 sc->sc_txdescs[nexttx].sipd_cmdsts = 1257 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1258 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1259 #ifdef DP83820 1260 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1261 #endif /* DP83820 */ 1262 lasttx = nexttx; 1263 } 1264 1265 /* Clear the MORE bit on the last segment. */ 1266 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1267 1268 /* 1269 * If we're in the interrupt delay window, delay the 1270 * interrupt. 1271 */ 1272 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1273 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1274 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1275 htole32(CMDSTS_INTR); 1276 sc->sc_txwin = 0; 1277 } 1278 1279 #ifdef DP83820 1280 /* 1281 * If VLANs are enabled and the packet has a VLAN tag, set 1282 * up the descriptor to encapsulate the packet for us. 1283 * 1284 * This apparently has to be on the last descriptor of 1285 * the packet. 1286 */ 1287 if (sc->sc_ethercom.ec_nvlans != 0 && 1288 (m = m_aux_find(m0, AF_LINK, ETHERTYPE_VLAN)) != NULL) { 1289 sc->sc_txdescs[lasttx].sipd_extsts |= 1290 htole32(EXTSTS_VPKT | 1291 htons(*mtod(m, int *) & EXTSTS_VTCI)); 1292 } 1293 1294 /* 1295 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1296 * checksumming, set up the descriptor to do this work 1297 * for us. 1298 * 1299 * This apparently has to be on the first descriptor of 1300 * the packet. 1301 * 1302 * Byte-swap constants so the compiler can optimize. 1303 */ 1304 extsts = 0; 1305 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1306 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1307 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1308 extsts |= htole32(EXTSTS_IPPKT); 1309 } 1310 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1311 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1312 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1313 extsts |= htole32(EXTSTS_TCPPKT); 1314 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1315 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1316 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1317 extsts |= htole32(EXTSTS_UDPPKT); 1318 } 1319 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1320 #endif /* DP83820 */ 1321 1322 /* Sync the descriptors we're using. */ 1323 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1324 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1325 1326 /* 1327 * The entire packet is set up. Give the first descrptor 1328 * to the chip now. 1329 */ 1330 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1331 htole32(CMDSTS_OWN); 1332 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1333 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1334 1335 /* 1336 * Store a pointer to the packet so we can free it later, 1337 * and remember what txdirty will be once the packet is 1338 * done. 1339 */ 1340 txs->txs_mbuf = m0; 1341 txs->txs_firstdesc = sc->sc_txnext; 1342 txs->txs_lastdesc = lasttx; 1343 1344 /* Advance the tx pointer. */ 1345 sc->sc_txfree -= dmamap->dm_nsegs; 1346 sc->sc_txnext = nexttx; 1347 1348 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1349 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1350 1351 #if NBPFILTER > 0 1352 /* 1353 * Pass the packet to any BPF listeners. 1354 */ 1355 if (ifp->if_bpf) 1356 bpf_mtap(ifp->if_bpf, m0); 1357 #endif /* NBPFILTER > 0 */ 1358 } 1359 1360 if (txs == NULL || sc->sc_txfree == 0) { 1361 /* No more slots left; notify upper layer. */ 1362 ifp->if_flags |= IFF_OACTIVE; 1363 } 1364 1365 if (sc->sc_txfree != ofree) { 1366 /* 1367 * Start the transmit process. Note, the manual says 1368 * that if there are no pending transmissions in the 1369 * chip's internal queue (indicated by TXE being clear), 1370 * then the driver software must set the TXDP to the 1371 * first descriptor to be transmitted. However, if we 1372 * do this, it causes serious performance degredation on 1373 * the DP83820 under load, not setting TXDP doesn't seem 1374 * to adversely affect the SiS 900 or DP83815. 1375 * 1376 * Well, I guess it wouldn't be the first time a manual 1377 * has lied -- and they could be speaking of the NULL- 1378 * terminated descriptor list case, rather than OWN- 1379 * terminated rings. 1380 */ 1381 #if 0 1382 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1383 CR_TXE) == 0) { 1384 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1385 SIP_CDTXADDR(sc, firsttx)); 1386 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1387 } 1388 #else 1389 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1390 #endif 1391 1392 /* Set a watchdog timer in case the chip flakes out. */ 1393 ifp->if_timer = 5; 1394 } 1395 } 1396 1397 /* 1398 * sip_watchdog: [ifnet interface function] 1399 * 1400 * Watchdog timer handler. 1401 */ 1402 void 1403 SIP_DECL(watchdog)(struct ifnet *ifp) 1404 { 1405 struct sip_softc *sc = ifp->if_softc; 1406 1407 /* 1408 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1409 * If we get a timeout, try and sweep up transmit descriptors. 1410 * If we manage to sweep them all up, ignore the lack of 1411 * interrupt. 1412 */ 1413 SIP_DECL(txintr)(sc); 1414 1415 if (sc->sc_txfree != SIP_NTXDESC) { 1416 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1417 ifp->if_oerrors++; 1418 1419 /* Reset the interface. */ 1420 (void) SIP_DECL(init)(ifp); 1421 } else if (ifp->if_flags & IFF_DEBUG) 1422 printf("%s: recovered from device timeout\n", 1423 sc->sc_dev.dv_xname); 1424 1425 /* Try to get more packets going. */ 1426 SIP_DECL(start)(ifp); 1427 } 1428 1429 /* 1430 * sip_ioctl: [ifnet interface function] 1431 * 1432 * Handle control requests from the operator. 1433 */ 1434 int 1435 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1436 { 1437 struct sip_softc *sc = ifp->if_softc; 1438 struct ifreq *ifr = (struct ifreq *)data; 1439 int s, error; 1440 1441 s = splnet(); 1442 1443 switch (cmd) { 1444 case SIOCSIFMEDIA: 1445 case SIOCGIFMEDIA: 1446 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1447 break; 1448 1449 default: 1450 error = ether_ioctl(ifp, cmd, data); 1451 if (error == ENETRESET) { 1452 /* 1453 * Multicast list has changed; set the hardware filter 1454 * accordingly. 1455 */ 1456 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1457 error = 0; 1458 } 1459 break; 1460 } 1461 1462 /* Try to get more packets going. */ 1463 SIP_DECL(start)(ifp); 1464 1465 splx(s); 1466 return (error); 1467 } 1468 1469 /* 1470 * sip_intr: 1471 * 1472 * Interrupt service routine. 1473 */ 1474 int 1475 SIP_DECL(intr)(void *arg) 1476 { 1477 struct sip_softc *sc = arg; 1478 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1479 u_int32_t isr; 1480 int handled = 0; 1481 1482 for (;;) { 1483 /* Reading clears interrupt. */ 1484 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1485 if ((isr & sc->sc_imr) == 0) 1486 break; 1487 1488 handled = 1; 1489 1490 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1491 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1492 1493 /* Grab any new packets. */ 1494 SIP_DECL(rxintr)(sc); 1495 1496 if (isr & ISR_RXORN) { 1497 printf("%s: receive FIFO overrun\n", 1498 sc->sc_dev.dv_xname); 1499 1500 /* XXX adjust rx_drain_thresh? */ 1501 } 1502 1503 if (isr & ISR_RXIDLE) { 1504 printf("%s: receive ring overrun\n", 1505 sc->sc_dev.dv_xname); 1506 1507 /* Get the receive process going again. */ 1508 bus_space_write_4(sc->sc_st, sc->sc_sh, 1509 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1510 bus_space_write_4(sc->sc_st, sc->sc_sh, 1511 SIP_CR, CR_RXE); 1512 } 1513 } 1514 1515 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1516 #ifdef SIP_EVENT_COUNTERS 1517 if (isr & ISR_TXDESC) 1518 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1519 else if (isr & ISR_TXIDLE) 1520 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1521 #endif 1522 1523 /* Sweep up transmit descriptors. */ 1524 SIP_DECL(txintr)(sc); 1525 1526 if (isr & ISR_TXURN) { 1527 u_int32_t thresh; 1528 1529 printf("%s: transmit FIFO underrun", 1530 sc->sc_dev.dv_xname); 1531 1532 thresh = sc->sc_tx_drain_thresh + 1; 1533 if (thresh <= TXCFG_DRTH && 1534 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1535 (sc->sc_tx_fill_thresh * 32))) { 1536 printf("; increasing Tx drain " 1537 "threshold to %u bytes\n", 1538 thresh * 32); 1539 sc->sc_tx_drain_thresh = thresh; 1540 (void) SIP_DECL(init)(ifp); 1541 } else { 1542 (void) SIP_DECL(init)(ifp); 1543 printf("\n"); 1544 } 1545 } 1546 } 1547 1548 #if !defined(DP83820) 1549 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1550 if (isr & ISR_PAUSE_ST) { 1551 sc->sc_flags |= SIPF_PAUSED; 1552 ifp->if_flags |= IFF_OACTIVE; 1553 } 1554 if (isr & ISR_PAUSE_END) { 1555 sc->sc_flags &= ~SIPF_PAUSED; 1556 ifp->if_flags &= ~IFF_OACTIVE; 1557 } 1558 } 1559 #endif /* ! DP83820 */ 1560 1561 if (isr & ISR_HIBERR) { 1562 int want_init = 0; 1563 1564 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1565 1566 #define PRINTERR(bit, str) \ 1567 do { \ 1568 if (isr & (bit)) { \ 1569 printf("%s: %s\n", \ 1570 sc->sc_dev.dv_xname, str); \ 1571 want_init = 1; \ 1572 } \ 1573 } while (/*CONSTCOND*/0) 1574 1575 PRINTERR(ISR_DPERR, "parity error"); 1576 PRINTERR(ISR_SSERR, "system error"); 1577 PRINTERR(ISR_RMABT, "master abort"); 1578 PRINTERR(ISR_RTABT, "target abort"); 1579 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1580 /* 1581 * Ignore: 1582 * Tx reset complete 1583 * Rx reset complete 1584 */ 1585 if (want_init) 1586 (void) SIP_DECL(init)(ifp); 1587 #undef PRINTERR 1588 } 1589 } 1590 1591 /* Try to get more packets going. */ 1592 SIP_DECL(start)(ifp); 1593 1594 return (handled); 1595 } 1596 1597 /* 1598 * sip_txintr: 1599 * 1600 * Helper; handle transmit interrupts. 1601 */ 1602 void 1603 SIP_DECL(txintr)(struct sip_softc *sc) 1604 { 1605 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1606 struct sip_txsoft *txs; 1607 u_int32_t cmdsts; 1608 1609 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1610 ifp->if_flags &= ~IFF_OACTIVE; 1611 1612 /* 1613 * Go through our Tx list and free mbufs for those 1614 * frames which have been transmitted. 1615 */ 1616 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1617 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1618 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1619 1620 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1621 if (cmdsts & CMDSTS_OWN) 1622 break; 1623 1624 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1625 1626 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1627 1628 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1629 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1630 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1631 m_freem(txs->txs_mbuf); 1632 txs->txs_mbuf = NULL; 1633 1634 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1635 1636 /* 1637 * Check for errors and collisions. 1638 */ 1639 if (cmdsts & 1640 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1641 ifp->if_oerrors++; 1642 if (cmdsts & CMDSTS_Tx_EC) 1643 ifp->if_collisions += 16; 1644 if (ifp->if_flags & IFF_DEBUG) { 1645 if (cmdsts & CMDSTS_Tx_ED) 1646 printf("%s: excessive deferral\n", 1647 sc->sc_dev.dv_xname); 1648 if (cmdsts & CMDSTS_Tx_EC) 1649 printf("%s: excessive collisions\n", 1650 sc->sc_dev.dv_xname); 1651 } 1652 } else { 1653 /* Packet was transmitted successfully. */ 1654 ifp->if_opackets++; 1655 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1656 } 1657 } 1658 1659 /* 1660 * If there are no more pending transmissions, cancel the watchdog 1661 * timer. 1662 */ 1663 if (txs == NULL) { 1664 ifp->if_timer = 0; 1665 sc->sc_txwin = 0; 1666 } 1667 } 1668 1669 #if defined(DP83820) 1670 /* 1671 * sip_rxintr: 1672 * 1673 * Helper; handle receive interrupts. 1674 */ 1675 void 1676 SIP_DECL(rxintr)(struct sip_softc *sc) 1677 { 1678 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1679 struct sip_rxsoft *rxs; 1680 struct mbuf *m, *tailm; 1681 u_int32_t cmdsts, extsts; 1682 int i, len; 1683 1684 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1685 rxs = &sc->sc_rxsoft[i]; 1686 1687 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1688 1689 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1690 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1691 1692 /* 1693 * NOTE: OWN is set if owned by _consumer_. We're the 1694 * consumer of the receive ring, so if the bit is clear, 1695 * we have processed all of the packets. 1696 */ 1697 if ((cmdsts & CMDSTS_OWN) == 0) { 1698 /* 1699 * We have processed all of the receive buffers. 1700 */ 1701 break; 1702 } 1703 1704 if (__predict_false(sc->sc_rxdiscard)) { 1705 SIP_INIT_RXDESC(sc, i); 1706 if ((cmdsts & CMDSTS_MORE) == 0) { 1707 /* Reset our state. */ 1708 sc->sc_rxdiscard = 0; 1709 } 1710 continue; 1711 } 1712 1713 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1714 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1715 1716 m = rxs->rxs_mbuf; 1717 1718 /* 1719 * Add a new receive buffer to the ring. 1720 */ 1721 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1722 /* 1723 * Failed, throw away what we've done so 1724 * far, and discard the rest of the packet. 1725 */ 1726 ifp->if_ierrors++; 1727 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1728 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1729 SIP_INIT_RXDESC(sc, i); 1730 if (cmdsts & CMDSTS_MORE) 1731 sc->sc_rxdiscard = 1; 1732 if (sc->sc_rxhead != NULL) 1733 m_freem(sc->sc_rxhead); 1734 SIP_RXCHAIN_RESET(sc); 1735 continue; 1736 } 1737 1738 SIP_RXCHAIN_LINK(sc, m); 1739 1740 /* 1741 * If this is not the end of the packet, keep 1742 * looking. 1743 */ 1744 if (cmdsts & CMDSTS_MORE) { 1745 sc->sc_rxlen += m->m_len; 1746 continue; 1747 } 1748 1749 /* 1750 * Okay, we have the entire packet now... 1751 */ 1752 *sc->sc_rxtailp = NULL; 1753 m = sc->sc_rxhead; 1754 tailm = sc->sc_rxtail; 1755 1756 SIP_RXCHAIN_RESET(sc); 1757 1758 /* 1759 * If an error occurred, update stats and drop the packet. 1760 */ 1761 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1762 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1763 ifp->if_ierrors++; 1764 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1765 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1766 /* Receive overrun handled elsewhere. */ 1767 printf("%s: receive descriptor error\n", 1768 sc->sc_dev.dv_xname); 1769 } 1770 #define PRINTERR(bit, str) \ 1771 if (cmdsts & (bit)) \ 1772 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1773 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1774 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1775 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1776 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1777 #undef PRINTERR 1778 m_freem(m); 1779 continue; 1780 } 1781 1782 /* 1783 * No errors. 1784 * 1785 * Note, the DP83820 includes the CRC with 1786 * every packet. 1787 */ 1788 len = CMDSTS_SIZE(cmdsts); 1789 tailm->m_len = len - sc->sc_rxlen; 1790 1791 /* 1792 * If the packet is small enough to fit in a 1793 * single header mbuf, allocate one and copy 1794 * the data into it. This greatly reduces 1795 * memory consumption when we receive lots 1796 * of small packets. 1797 */ 1798 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1799 struct mbuf *nm; 1800 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1801 if (nm == NULL) { 1802 ifp->if_ierrors++; 1803 m_freem(m); 1804 continue; 1805 } 1806 nm->m_data += 2; 1807 nm->m_pkthdr.len = nm->m_len = len; 1808 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1809 m_freem(m); 1810 m = nm; 1811 } 1812 #ifndef __NO_STRICT_ALIGNMENT 1813 else { 1814 /* 1815 * The DP83820's receive buffers must be 4-byte 1816 * aligned. But this means that the data after 1817 * the Ethernet header is misaligned. To compensate, 1818 * we have artificially shortened the buffer size 1819 * in the descriptor, and we do an overlapping copy 1820 * of the data two bytes further in (in the first 1821 * buffer of the chain only). 1822 */ 1823 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1824 m->m_len); 1825 m->m_data += 2; 1826 } 1827 #endif /* ! __NO_STRICT_ALIGNMENT */ 1828 1829 /* 1830 * If VLANs are enabled, VLAN packets have been unwrapped 1831 * for us. Associate the tag with the packet. 1832 */ 1833 if (sc->sc_ethercom.ec_nvlans != 0 && 1834 (extsts & EXTSTS_VPKT) != 0) { 1835 struct mbuf *vtag; 1836 1837 vtag = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 1838 if (vtag == NULL) { 1839 ifp->if_ierrors++; 1840 printf("%s: unable to allocate VLAN tag\n", 1841 sc->sc_dev.dv_xname); 1842 m_freem(m); 1843 continue; 1844 } 1845 1846 *mtod(vtag, int *) = ntohs(extsts & EXTSTS_VTCI); 1847 vtag->m_len = sizeof(int); 1848 } 1849 1850 /* 1851 * Set the incoming checksum information for the 1852 * packet. 1853 */ 1854 if ((extsts & EXTSTS_IPPKT) != 0) { 1855 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1856 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1857 if (extsts & EXTSTS_Rx_IPERR) 1858 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1859 if (extsts & EXTSTS_TCPPKT) { 1860 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1861 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1862 if (extsts & EXTSTS_Rx_TCPERR) 1863 m->m_pkthdr.csum_flags |= 1864 M_CSUM_TCP_UDP_BAD; 1865 } else if (extsts & EXTSTS_UDPPKT) { 1866 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1867 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1868 if (extsts & EXTSTS_Rx_UDPERR) 1869 m->m_pkthdr.csum_flags |= 1870 M_CSUM_TCP_UDP_BAD; 1871 } 1872 } 1873 1874 ifp->if_ipackets++; 1875 m->m_flags |= M_HASFCS; 1876 m->m_pkthdr.rcvif = ifp; 1877 m->m_pkthdr.len = len; 1878 1879 #if NBPFILTER > 0 1880 /* 1881 * Pass this up to any BPF listeners, but only 1882 * pass if up the stack if it's for us. 1883 */ 1884 if (ifp->if_bpf) 1885 bpf_mtap(ifp->if_bpf, m); 1886 #endif /* NBPFILTER > 0 */ 1887 1888 /* Pass it on. */ 1889 (*ifp->if_input)(ifp, m); 1890 } 1891 1892 /* Update the receive pointer. */ 1893 sc->sc_rxptr = i; 1894 } 1895 #else /* ! DP83820 */ 1896 /* 1897 * sip_rxintr: 1898 * 1899 * Helper; handle receive interrupts. 1900 */ 1901 void 1902 SIP_DECL(rxintr)(struct sip_softc *sc) 1903 { 1904 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1905 struct sip_rxsoft *rxs; 1906 struct mbuf *m; 1907 u_int32_t cmdsts; 1908 int i, len; 1909 1910 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1911 rxs = &sc->sc_rxsoft[i]; 1912 1913 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1914 1915 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1916 1917 /* 1918 * NOTE: OWN is set if owned by _consumer_. We're the 1919 * consumer of the receive ring, so if the bit is clear, 1920 * we have processed all of the packets. 1921 */ 1922 if ((cmdsts & CMDSTS_OWN) == 0) { 1923 /* 1924 * We have processed all of the receive buffers. 1925 */ 1926 break; 1927 } 1928 1929 /* 1930 * If any collisions were seen on the wire, count one. 1931 */ 1932 if (cmdsts & CMDSTS_Rx_COL) 1933 ifp->if_collisions++; 1934 1935 /* 1936 * If an error occurred, update stats, clear the status 1937 * word, and leave the packet buffer in place. It will 1938 * simply be reused the next time the ring comes around. 1939 */ 1940 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1941 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1942 ifp->if_ierrors++; 1943 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1944 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1945 /* Receive overrun handled elsewhere. */ 1946 printf("%s: receive descriptor error\n", 1947 sc->sc_dev.dv_xname); 1948 } 1949 #define PRINTERR(bit, str) \ 1950 if (cmdsts & (bit)) \ 1951 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1952 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1953 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1954 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1955 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1956 #undef PRINTERR 1957 SIP_INIT_RXDESC(sc, i); 1958 continue; 1959 } 1960 1961 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1962 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1963 1964 /* 1965 * No errors; receive the packet. Note, the SiS 900 1966 * includes the CRC with every packet. 1967 */ 1968 len = CMDSTS_SIZE(cmdsts); 1969 1970 #ifdef __NO_STRICT_ALIGNMENT 1971 /* 1972 * If the packet is small enough to fit in a 1973 * single header mbuf, allocate one and copy 1974 * the data into it. This greatly reduces 1975 * memory consumption when we receive lots 1976 * of small packets. 1977 * 1978 * Otherwise, we add a new buffer to the receive 1979 * chain. If this fails, we drop the packet and 1980 * recycle the old buffer. 1981 */ 1982 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 1983 MGETHDR(m, M_DONTWAIT, MT_DATA); 1984 if (m == NULL) 1985 goto dropit; 1986 memcpy(mtod(m, caddr_t), 1987 mtod(rxs->rxs_mbuf, caddr_t), len); 1988 SIP_INIT_RXDESC(sc, i); 1989 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1990 rxs->rxs_dmamap->dm_mapsize, 1991 BUS_DMASYNC_PREREAD); 1992 } else { 1993 m = rxs->rxs_mbuf; 1994 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1995 dropit: 1996 ifp->if_ierrors++; 1997 SIP_INIT_RXDESC(sc, i); 1998 bus_dmamap_sync(sc->sc_dmat, 1999 rxs->rxs_dmamap, 0, 2000 rxs->rxs_dmamap->dm_mapsize, 2001 BUS_DMASYNC_PREREAD); 2002 continue; 2003 } 2004 } 2005 #else 2006 /* 2007 * The SiS 900's receive buffers must be 4-byte aligned. 2008 * But this means that the data after the Ethernet header 2009 * is misaligned. We must allocate a new buffer and 2010 * copy the data, shifted forward 2 bytes. 2011 */ 2012 MGETHDR(m, M_DONTWAIT, MT_DATA); 2013 if (m == NULL) { 2014 dropit: 2015 ifp->if_ierrors++; 2016 SIP_INIT_RXDESC(sc, i); 2017 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2018 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2019 continue; 2020 } 2021 if (len > (MHLEN - 2)) { 2022 MCLGET(m, M_DONTWAIT); 2023 if ((m->m_flags & M_EXT) == 0) { 2024 m_freem(m); 2025 goto dropit; 2026 } 2027 } 2028 m->m_data += 2; 2029 2030 /* 2031 * Note that we use clusters for incoming frames, so the 2032 * buffer is virtually contiguous. 2033 */ 2034 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 2035 2036 /* Allow the receive descriptor to continue using its mbuf. */ 2037 SIP_INIT_RXDESC(sc, i); 2038 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2039 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2040 #endif /* __NO_STRICT_ALIGNMENT */ 2041 2042 ifp->if_ipackets++; 2043 m->m_flags |= M_HASFCS; 2044 m->m_pkthdr.rcvif = ifp; 2045 m->m_pkthdr.len = m->m_len = len; 2046 2047 #if NBPFILTER > 0 2048 /* 2049 * Pass this up to any BPF listeners, but only 2050 * pass if up the stack if it's for us. 2051 */ 2052 if (ifp->if_bpf) 2053 bpf_mtap(ifp->if_bpf, m); 2054 #endif /* NBPFILTER > 0 */ 2055 2056 /* Pass it on. */ 2057 (*ifp->if_input)(ifp, m); 2058 } 2059 2060 /* Update the receive pointer. */ 2061 sc->sc_rxptr = i; 2062 } 2063 #endif /* DP83820 */ 2064 2065 /* 2066 * sip_tick: 2067 * 2068 * One second timer, used to tick the MII. 2069 */ 2070 void 2071 SIP_DECL(tick)(void *arg) 2072 { 2073 struct sip_softc *sc = arg; 2074 int s; 2075 2076 s = splnet(); 2077 mii_tick(&sc->sc_mii); 2078 splx(s); 2079 2080 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2081 } 2082 2083 /* 2084 * sip_reset: 2085 * 2086 * Perform a soft reset on the SiS 900. 2087 */ 2088 void 2089 SIP_DECL(reset)(struct sip_softc *sc) 2090 { 2091 bus_space_tag_t st = sc->sc_st; 2092 bus_space_handle_t sh = sc->sc_sh; 2093 int i; 2094 2095 bus_space_write_4(st, sh, SIP_IER, 0); 2096 bus_space_write_4(st, sh, SIP_IMR, 0); 2097 bus_space_write_4(st, sh, SIP_RFCR, 0); 2098 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2099 2100 for (i = 0; i < SIP_TIMEOUT; i++) { 2101 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2102 break; 2103 delay(2); 2104 } 2105 2106 if (i == SIP_TIMEOUT) 2107 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2108 2109 delay(1000); 2110 2111 #ifdef DP83820 2112 /* 2113 * Set the general purpose I/O bits. Do it here in case we 2114 * need to have GPIO set up to talk to the media interface. 2115 */ 2116 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2117 delay(1000); 2118 #endif /* DP83820 */ 2119 } 2120 2121 /* 2122 * sip_init: [ ifnet interface function ] 2123 * 2124 * Initialize the interface. Must be called at splnet(). 2125 */ 2126 int 2127 SIP_DECL(init)(struct ifnet *ifp) 2128 { 2129 struct sip_softc *sc = ifp->if_softc; 2130 bus_space_tag_t st = sc->sc_st; 2131 bus_space_handle_t sh = sc->sc_sh; 2132 struct sip_txsoft *txs; 2133 struct sip_rxsoft *rxs; 2134 struct sip_desc *sipd; 2135 u_int32_t reg; 2136 int i, error = 0; 2137 2138 /* 2139 * Cancel any pending I/O. 2140 */ 2141 SIP_DECL(stop)(ifp, 0); 2142 2143 /* 2144 * Reset the chip to a known state. 2145 */ 2146 SIP_DECL(reset)(sc); 2147 2148 #if !defined(DP83820) 2149 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2150 /* 2151 * DP83815 manual, page 78: 2152 * 4.4 Recommended Registers Configuration 2153 * For optimum performance of the DP83815, version noted 2154 * as DP83815CVNG (SRR = 203h), the listed register 2155 * modifications must be followed in sequence... 2156 * 2157 * It's not clear if this should be 302h or 203h because that 2158 * chip name is listed as SRR 302h in the description of the 2159 * SRR register. However, my revision 302h DP83815 on the 2160 * Netgear FA311 purchased in 02/2001 needs these settings 2161 * to avoid tons of errors in AcceptPerfectMatch (non- 2162 * IFF_PROMISC) mode. I do not know if other revisions need 2163 * this set or not. [briggs -- 09 March 2001] 2164 * 2165 * Note that only the low-order 12 bits of 0xe4 are documented 2166 * and that this sets reserved bits in that register. 2167 */ 2168 reg = bus_space_read_4(st, sh, SIP_NS_SRR); 2169 if (reg == 0x302) { 2170 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2171 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2172 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2173 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2174 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2175 } 2176 } 2177 #endif /* ! DP83820 */ 2178 2179 /* 2180 * Initialize the transmit descriptor ring. 2181 */ 2182 for (i = 0; i < SIP_NTXDESC; i++) { 2183 sipd = &sc->sc_txdescs[i]; 2184 memset(sipd, 0, sizeof(struct sip_desc)); 2185 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2186 } 2187 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2188 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2189 sc->sc_txfree = SIP_NTXDESC; 2190 sc->sc_txnext = 0; 2191 sc->sc_txwin = 0; 2192 2193 /* 2194 * Initialize the transmit job descriptors. 2195 */ 2196 SIMPLEQ_INIT(&sc->sc_txfreeq); 2197 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2198 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2199 txs = &sc->sc_txsoft[i]; 2200 txs->txs_mbuf = NULL; 2201 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2202 } 2203 2204 /* 2205 * Initialize the receive descriptor and receive job 2206 * descriptor rings. 2207 */ 2208 for (i = 0; i < SIP_NRXDESC; i++) { 2209 rxs = &sc->sc_rxsoft[i]; 2210 if (rxs->rxs_mbuf == NULL) { 2211 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2212 printf("%s: unable to allocate or map rx " 2213 "buffer %d, error = %d\n", 2214 sc->sc_dev.dv_xname, i, error); 2215 /* 2216 * XXX Should attempt to run with fewer receive 2217 * XXX buffers instead of just failing. 2218 */ 2219 SIP_DECL(rxdrain)(sc); 2220 goto out; 2221 } 2222 } else 2223 SIP_INIT_RXDESC(sc, i); 2224 } 2225 sc->sc_rxptr = 0; 2226 #ifdef DP83820 2227 sc->sc_rxdiscard = 0; 2228 SIP_RXCHAIN_RESET(sc); 2229 #endif /* DP83820 */ 2230 2231 /* 2232 * Set the configuration register; it's already initialized 2233 * in sip_attach(). 2234 */ 2235 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2236 2237 /* 2238 * Initialize the prototype TXCFG register. 2239 */ 2240 #if defined(DP83820) 2241 sc->sc_txcfg = TXCFG_MXDMA_512; 2242 sc->sc_rxcfg = RXCFG_MXDMA_512; 2243 #else 2244 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2245 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2246 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & CFG_EDBMASTEN)) { 2247 sc->sc_txcfg = TXCFG_MXDMA_64; 2248 sc->sc_rxcfg = RXCFG_MXDMA_64; 2249 } else { 2250 sc->sc_txcfg = TXCFG_MXDMA_512; 2251 sc->sc_rxcfg = RXCFG_MXDMA_512; 2252 } 2253 #endif /* DP83820 */ 2254 2255 sc->sc_txcfg |= TXCFG_ATP | 2256 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2257 sc->sc_tx_drain_thresh; 2258 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2259 2260 /* 2261 * Initialize the receive drain threshold if we have never 2262 * done so. 2263 */ 2264 if (sc->sc_rx_drain_thresh == 0) { 2265 /* 2266 * XXX This value should be tuned. This is set to the 2267 * maximum of 248 bytes, and we may be able to improve 2268 * performance by decreasing it (although we should never 2269 * set this value lower than 2; 14 bytes are required to 2270 * filter the packet). 2271 */ 2272 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2273 } 2274 2275 /* 2276 * Initialize the prototype RXCFG register. 2277 */ 2278 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2279 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2280 2281 #ifdef DP83820 2282 /* 2283 * Initialize the VLAN/IP receive control register. 2284 * We enable checksum computation on all incoming 2285 * packets, and do not reject packets w/ bad checksums. 2286 */ 2287 reg = 0; 2288 if (ifp->if_capenable & 2289 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2290 reg |= VRCR_IPEN; 2291 if (sc->sc_ethercom.ec_nvlans != 0) 2292 reg |= VRCR_VTDEN|VRCR_VTREN; 2293 bus_space_write_4(st, sh, SIP_VRCR, reg); 2294 2295 /* 2296 * Initialize the VLAN/IP transmit control register. 2297 * We enable outgoing checksum computation on a 2298 * per-packet basis. 2299 */ 2300 reg = 0; 2301 if (ifp->if_capenable & 2302 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2303 reg |= VTCR_PPCHK; 2304 if (sc->sc_ethercom.ec_nvlans != 0) 2305 reg |= VTCR_VPPTI; 2306 bus_space_write_4(st, sh, SIP_VTCR, reg); 2307 2308 /* 2309 * If we're using VLANs, initialize the VLAN data register. 2310 * To understand why we bswap the VLAN Ethertype, see section 2311 * 4.2.36 of the DP83820 manual. 2312 */ 2313 if (sc->sc_ethercom.ec_nvlans != 0) 2314 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2315 #endif /* DP83820 */ 2316 2317 /* 2318 * Give the transmit and receive rings to the chip. 2319 */ 2320 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2321 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2322 2323 /* 2324 * Initialize the interrupt mask. 2325 */ 2326 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2327 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2328 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2329 2330 /* Set up the receive filter. */ 2331 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2332 2333 /* 2334 * Set the current media. Do this after initializing the prototype 2335 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2336 * control. 2337 */ 2338 mii_mediachg(&sc->sc_mii); 2339 2340 /* 2341 * Enable interrupts. 2342 */ 2343 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2344 2345 /* 2346 * Start the transmit and receive processes. 2347 */ 2348 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2349 2350 /* 2351 * Start the one second MII clock. 2352 */ 2353 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2354 2355 /* 2356 * ...all done! 2357 */ 2358 ifp->if_flags |= IFF_RUNNING; 2359 ifp->if_flags &= ~IFF_OACTIVE; 2360 2361 out: 2362 if (error) 2363 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2364 return (error); 2365 } 2366 2367 /* 2368 * sip_drain: 2369 * 2370 * Drain the receive queue. 2371 */ 2372 void 2373 SIP_DECL(rxdrain)(struct sip_softc *sc) 2374 { 2375 struct sip_rxsoft *rxs; 2376 int i; 2377 2378 for (i = 0; i < SIP_NRXDESC; i++) { 2379 rxs = &sc->sc_rxsoft[i]; 2380 if (rxs->rxs_mbuf != NULL) { 2381 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2382 m_freem(rxs->rxs_mbuf); 2383 rxs->rxs_mbuf = NULL; 2384 } 2385 } 2386 } 2387 2388 /* 2389 * sip_stop: [ ifnet interface function ] 2390 * 2391 * Stop transmission on the interface. 2392 */ 2393 void 2394 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2395 { 2396 struct sip_softc *sc = ifp->if_softc; 2397 bus_space_tag_t st = sc->sc_st; 2398 bus_space_handle_t sh = sc->sc_sh; 2399 struct sip_txsoft *txs; 2400 u_int32_t cmdsts = 0; /* DEBUG */ 2401 2402 /* 2403 * Stop the one second clock. 2404 */ 2405 callout_stop(&sc->sc_tick_ch); 2406 2407 /* Down the MII. */ 2408 mii_down(&sc->sc_mii); 2409 2410 /* 2411 * Disable interrupts. 2412 */ 2413 bus_space_write_4(st, sh, SIP_IER, 0); 2414 2415 /* 2416 * Stop receiver and transmitter. 2417 */ 2418 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2419 2420 /* 2421 * Release any queued transmit buffers. 2422 */ 2423 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2424 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2425 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2426 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2427 CMDSTS_INTR) == 0) 2428 printf("%s: sip_stop: last descriptor does not " 2429 "have INTR bit set\n", sc->sc_dev.dv_xname); 2430 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2431 #ifdef DIAGNOSTIC 2432 if (txs->txs_mbuf == NULL) { 2433 printf("%s: dirty txsoft with no mbuf chain\n", 2434 sc->sc_dev.dv_xname); 2435 panic("sip_stop"); 2436 } 2437 #endif 2438 cmdsts |= /* DEBUG */ 2439 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2440 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2441 m_freem(txs->txs_mbuf); 2442 txs->txs_mbuf = NULL; 2443 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2444 } 2445 2446 if (disable) 2447 SIP_DECL(rxdrain)(sc); 2448 2449 /* 2450 * Mark the interface down and cancel the watchdog timer. 2451 */ 2452 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2453 ifp->if_timer = 0; 2454 2455 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2456 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2457 printf("%s: sip_stop: no INTR bits set in dirty tx " 2458 "descriptors\n", sc->sc_dev.dv_xname); 2459 } 2460 2461 /* 2462 * sip_read_eeprom: 2463 * 2464 * Read data from the serial EEPROM. 2465 */ 2466 void 2467 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2468 u_int16_t *data) 2469 { 2470 bus_space_tag_t st = sc->sc_st; 2471 bus_space_handle_t sh = sc->sc_sh; 2472 u_int16_t reg; 2473 int i, x; 2474 2475 for (i = 0; i < wordcnt; i++) { 2476 /* Send CHIP SELECT. */ 2477 reg = EROMAR_EECS; 2478 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2479 2480 /* Shift in the READ opcode. */ 2481 for (x = 3; x > 0; x--) { 2482 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2483 reg |= EROMAR_EEDI; 2484 else 2485 reg &= ~EROMAR_EEDI; 2486 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2487 bus_space_write_4(st, sh, SIP_EROMAR, 2488 reg | EROMAR_EESK); 2489 delay(4); 2490 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2491 delay(4); 2492 } 2493 2494 /* Shift in address. */ 2495 for (x = 6; x > 0; x--) { 2496 if ((word + i) & (1 << (x - 1))) 2497 reg |= EROMAR_EEDI; 2498 else 2499 reg &= ~EROMAR_EEDI; 2500 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2501 bus_space_write_4(st, sh, SIP_EROMAR, 2502 reg | EROMAR_EESK); 2503 delay(4); 2504 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2505 delay(4); 2506 } 2507 2508 /* Shift out data. */ 2509 reg = EROMAR_EECS; 2510 data[i] = 0; 2511 for (x = 16; x > 0; x--) { 2512 bus_space_write_4(st, sh, SIP_EROMAR, 2513 reg | EROMAR_EESK); 2514 delay(4); 2515 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2516 data[i] |= (1 << (x - 1)); 2517 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2518 delay(4); 2519 } 2520 2521 /* Clear CHIP SELECT. */ 2522 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2523 delay(4); 2524 } 2525 } 2526 2527 /* 2528 * sip_add_rxbuf: 2529 * 2530 * Add a receive buffer to the indicated descriptor. 2531 */ 2532 int 2533 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2534 { 2535 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2536 struct mbuf *m; 2537 int error; 2538 2539 MGETHDR(m, M_DONTWAIT, MT_DATA); 2540 if (m == NULL) 2541 return (ENOBUFS); 2542 2543 MCLGET(m, M_DONTWAIT); 2544 if ((m->m_flags & M_EXT) == 0) { 2545 m_freem(m); 2546 return (ENOBUFS); 2547 } 2548 2549 #if defined(DP83820) 2550 m->m_len = SIP_RXBUF_LEN; 2551 #endif /* DP83820 */ 2552 2553 if (rxs->rxs_mbuf != NULL) 2554 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2555 2556 rxs->rxs_mbuf = m; 2557 2558 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2559 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2560 BUS_DMA_READ|BUS_DMA_NOWAIT); 2561 if (error) { 2562 printf("%s: can't load rx DMA map %d, error = %d\n", 2563 sc->sc_dev.dv_xname, idx, error); 2564 panic("sip_add_rxbuf"); /* XXX */ 2565 } 2566 2567 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2568 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2569 2570 SIP_INIT_RXDESC(sc, idx); 2571 2572 return (0); 2573 } 2574 2575 #if !defined(DP83820) 2576 /* 2577 * sip_sis900_set_filter: 2578 * 2579 * Set up the receive filter. 2580 */ 2581 void 2582 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2583 { 2584 bus_space_tag_t st = sc->sc_st; 2585 bus_space_handle_t sh = sc->sc_sh; 2586 struct ethercom *ec = &sc->sc_ethercom; 2587 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2588 struct ether_multi *enm; 2589 u_int8_t *cp; 2590 struct ether_multistep step; 2591 u_int32_t crc, mchash[16]; 2592 2593 /* 2594 * Initialize the prototype RFCR. 2595 */ 2596 sc->sc_rfcr = RFCR_RFEN; 2597 if (ifp->if_flags & IFF_BROADCAST) 2598 sc->sc_rfcr |= RFCR_AAB; 2599 if (ifp->if_flags & IFF_PROMISC) { 2600 sc->sc_rfcr |= RFCR_AAP; 2601 goto allmulti; 2602 } 2603 2604 /* 2605 * Set up the multicast address filter by passing all multicast 2606 * addresses through a CRC generator, and then using the high-order 2607 * 6 bits as an index into the 128 bit multicast hash table (only 2608 * the lower 16 bits of each 32 bit multicast hash register are 2609 * valid). The high order bits select the register, while the 2610 * rest of the bits select the bit within the register. 2611 */ 2612 2613 memset(mchash, 0, sizeof(mchash)); 2614 2615 ETHER_FIRST_MULTI(step, ec, enm); 2616 while (enm != NULL) { 2617 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2618 /* 2619 * We must listen to a range of multicast addresses. 2620 * For now, just accept all multicasts, rather than 2621 * trying to set only those filter bits needed to match 2622 * the range. (At this time, the only use of address 2623 * ranges is for IP multicast routing, for which the 2624 * range is big enough to require all bits set.) 2625 */ 2626 goto allmulti; 2627 } 2628 2629 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2630 2631 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2632 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2633 /* Just want the 8 most significant bits. */ 2634 crc >>= 24; 2635 } else { 2636 /* Just want the 7 most significant bits. */ 2637 crc >>= 25; 2638 } 2639 2640 /* Set the corresponding bit in the hash table. */ 2641 mchash[crc >> 4] |= 1 << (crc & 0xf); 2642 2643 ETHER_NEXT_MULTI(step, enm); 2644 } 2645 2646 ifp->if_flags &= ~IFF_ALLMULTI; 2647 goto setit; 2648 2649 allmulti: 2650 ifp->if_flags |= IFF_ALLMULTI; 2651 sc->sc_rfcr |= RFCR_AAM; 2652 2653 setit: 2654 #define FILTER_EMIT(addr, data) \ 2655 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2656 delay(1); \ 2657 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2658 delay(1) 2659 2660 /* 2661 * Disable receive filter, and program the node address. 2662 */ 2663 cp = LLADDR(ifp->if_sadl); 2664 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2665 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2666 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2667 2668 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2669 /* 2670 * Program the multicast hash table. 2671 */ 2672 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2673 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2674 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2675 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2676 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2677 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2678 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2679 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2680 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2681 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2682 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2683 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2684 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2685 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2686 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2687 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2688 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2689 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2690 } 2691 } 2692 #undef FILTER_EMIT 2693 2694 /* 2695 * Re-enable the receiver filter. 2696 */ 2697 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2698 } 2699 #endif /* ! DP83820 */ 2700 2701 /* 2702 * sip_dp83815_set_filter: 2703 * 2704 * Set up the receive filter. 2705 */ 2706 void 2707 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2708 { 2709 bus_space_tag_t st = sc->sc_st; 2710 bus_space_handle_t sh = sc->sc_sh; 2711 struct ethercom *ec = &sc->sc_ethercom; 2712 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2713 struct ether_multi *enm; 2714 u_int8_t *cp; 2715 struct ether_multistep step; 2716 u_int32_t crc, hash, slot, bit; 2717 #ifdef DP83820 2718 #define MCHASH_NWORDS 128 2719 #else 2720 #define MCHASH_NWORDS 32 2721 #endif /* DP83820 */ 2722 u_int16_t mchash[MCHASH_NWORDS]; 2723 int i; 2724 2725 /* 2726 * Initialize the prototype RFCR. 2727 * Enable the receive filter, and accept on 2728 * Perfect (destination address) Match 2729 * If IFF_BROADCAST, also accept all broadcast packets. 2730 * If IFF_PROMISC, accept all unicast packets (and later, set 2731 * IFF_ALLMULTI and accept all multicast, too). 2732 */ 2733 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2734 if (ifp->if_flags & IFF_BROADCAST) 2735 sc->sc_rfcr |= RFCR_AAB; 2736 if (ifp->if_flags & IFF_PROMISC) { 2737 sc->sc_rfcr |= RFCR_AAP; 2738 goto allmulti; 2739 } 2740 2741 #ifdef DP83820 2742 /* 2743 * Set up the DP83820 multicast address filter by passing all multicast 2744 * addresses through a CRC generator, and then using the high-order 2745 * 11 bits as an index into the 2048 bit multicast hash table. The 2746 * high-order 7 bits select the slot, while the low-order 4 bits 2747 * select the bit within the slot. Note that only the low 16-bits 2748 * of each filter word are used, and there are 128 filter words. 2749 */ 2750 #else 2751 /* 2752 * Set up the DP83815 multicast address filter by passing all multicast 2753 * addresses through a CRC generator, and then using the high-order 2754 * 9 bits as an index into the 512 bit multicast hash table. The 2755 * high-order 5 bits select the slot, while the low-order 4 bits 2756 * select the bit within the slot. Note that only the low 16-bits 2757 * of each filter word are used, and there are 32 filter words. 2758 */ 2759 #endif /* DP83820 */ 2760 2761 memset(mchash, 0, sizeof(mchash)); 2762 2763 ifp->if_flags &= ~IFF_ALLMULTI; 2764 ETHER_FIRST_MULTI(step, ec, enm); 2765 if (enm == NULL) 2766 goto setit; 2767 while (enm != NULL) { 2768 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2769 /* 2770 * We must listen to a range of multicast addresses. 2771 * For now, just accept all multicasts, rather than 2772 * trying to set only those filter bits needed to match 2773 * the range. (At this time, the only use of address 2774 * ranges is for IP multicast routing, for which the 2775 * range is big enough to require all bits set.) 2776 */ 2777 goto allmulti; 2778 } 2779 2780 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2781 2782 #ifdef DP83820 2783 /* Just want the 11 most significant bits. */ 2784 hash = crc >> 21; 2785 #else 2786 /* Just want the 9 most significant bits. */ 2787 hash = crc >> 23; 2788 #endif /* DP83820 */ 2789 2790 slot = hash >> 4; 2791 bit = hash & 0xf; 2792 2793 /* Set the corresponding bit in the hash table. */ 2794 mchash[slot] |= 1 << bit; 2795 2796 ETHER_NEXT_MULTI(step, enm); 2797 } 2798 sc->sc_rfcr |= RFCR_MHEN; 2799 goto setit; 2800 2801 allmulti: 2802 ifp->if_flags |= IFF_ALLMULTI; 2803 sc->sc_rfcr |= RFCR_AAM; 2804 2805 setit: 2806 #define FILTER_EMIT(addr, data) \ 2807 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2808 delay(1); \ 2809 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2810 delay(1) 2811 2812 /* 2813 * Disable receive filter, and program the node address. 2814 */ 2815 cp = LLADDR(ifp->if_sadl); 2816 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 2817 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 2818 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 2819 2820 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2821 /* 2822 * Program the multicast hash table. 2823 */ 2824 for (i = 0; i < MCHASH_NWORDS; i++) { 2825 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 2826 mchash[i]); 2827 } 2828 } 2829 #undef FILTER_EMIT 2830 #undef MCHASH_NWORDS 2831 2832 /* 2833 * Re-enable the receiver filter. 2834 */ 2835 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2836 } 2837 2838 #if defined(DP83820) 2839 /* 2840 * sip_dp83820_mii_readreg: [mii interface function] 2841 * 2842 * Read a PHY register on the MII of the DP83820. 2843 */ 2844 int 2845 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 2846 { 2847 struct sip_softc *sc = (void *) self; 2848 2849 if (sc->sc_cfg & CFG_TBI_EN) { 2850 bus_addr_t tbireg; 2851 int rv; 2852 2853 if (phy != 0) 2854 return (0); 2855 2856 switch (reg) { 2857 case MII_BMCR: tbireg = SIP_TBICR; break; 2858 case MII_BMSR: tbireg = SIP_TBISR; break; 2859 case MII_ANAR: tbireg = SIP_TANAR; break; 2860 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 2861 case MII_ANER: tbireg = SIP_TANER; break; 2862 case MII_EXTSR: tbireg = SIP_TESR; break; 2863 default: 2864 return (0); 2865 } 2866 2867 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 2868 if (tbireg == SIP_TBISR) { 2869 /* LINK and ACOMP are switched! */ 2870 int val = rv; 2871 2872 rv = 0; 2873 if (val & TBISR_MR_LINK_STATUS) 2874 rv |= BMSR_LINK; 2875 if (val & TBISR_MR_AN_COMPLETE) 2876 rv |= BMSR_ACOMP; 2877 } 2878 2879 return (rv); 2880 } 2881 2882 return (mii_bitbang_readreg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2883 phy, reg)); 2884 } 2885 2886 /* 2887 * sip_dp83820_mii_writereg: [mii interface function] 2888 * 2889 * Write a PHY register on the MII of the DP83820. 2890 */ 2891 void 2892 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 2893 { 2894 struct sip_softc *sc = (void *) self; 2895 2896 if (sc->sc_cfg & CFG_TBI_EN) { 2897 bus_addr_t tbireg; 2898 2899 if (phy != 0) 2900 return; 2901 2902 switch (reg) { 2903 case MII_BMCR: tbireg = SIP_TBICR; break; 2904 case MII_ANAR: tbireg = SIP_TANAR; break; 2905 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 2906 default: 2907 return; 2908 } 2909 2910 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 2911 return; 2912 } 2913 2914 mii_bitbang_writereg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2915 phy, reg, val); 2916 } 2917 2918 /* 2919 * sip_dp83815_mii_statchg: [mii interface function] 2920 * 2921 * Callback from MII layer when media changes. 2922 */ 2923 void 2924 SIP_DECL(dp83820_mii_statchg)(struct device *self) 2925 { 2926 struct sip_softc *sc = (struct sip_softc *) self; 2927 u_int32_t cfg; 2928 2929 /* 2930 * Update TXCFG for full-duplex operation. 2931 */ 2932 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2933 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2934 else 2935 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2936 2937 /* 2938 * Update RXCFG for full-duplex or loopback. 2939 */ 2940 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2941 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2942 sc->sc_rxcfg |= RXCFG_ATX; 2943 else 2944 sc->sc_rxcfg &= ~RXCFG_ATX; 2945 2946 /* 2947 * Update CFG for MII/GMII. 2948 */ 2949 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2950 cfg = sc->sc_cfg | CFG_MODE_1000; 2951 else 2952 cfg = sc->sc_cfg; 2953 2954 /* 2955 * XXX 802.3x flow control. 2956 */ 2957 2958 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 2959 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2960 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2961 } 2962 2963 /* 2964 * sip_dp83820_mii_bitbang_read: [mii bit-bang interface function] 2965 * 2966 * Read the MII serial port for the MII bit-bang module. 2967 */ 2968 u_int32_t 2969 SIP_DECL(dp83820_mii_bitbang_read)(struct device *self) 2970 { 2971 struct sip_softc *sc = (void *) self; 2972 2973 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 2974 } 2975 2976 /* 2977 * sip_dp83820_mii_bitbang_write: [mii big-bang interface function] 2978 * 2979 * Write the MII serial port for the MII bit-bang module. 2980 */ 2981 void 2982 SIP_DECL(dp83820_mii_bitbang_write)(struct device *self, u_int32_t val) 2983 { 2984 struct sip_softc *sc = (void *) self; 2985 2986 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 2987 } 2988 #else /* ! DP83820 */ 2989 /* 2990 * sip_sis900_mii_readreg: [mii interface function] 2991 * 2992 * Read a PHY register on the MII. 2993 */ 2994 int 2995 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 2996 { 2997 struct sip_softc *sc = (struct sip_softc *) self; 2998 u_int32_t enphy; 2999 3000 /* 3001 * The SiS 900 has only an internal PHY on the MII. Only allow 3002 * MII address 0. 3003 */ 3004 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 3005 sc->sc_rev < SIS_REV_635 && phy != 0) 3006 return (0); 3007 3008 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3009 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3010 ENPHY_RWCMD | ENPHY_ACCESS); 3011 do { 3012 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3013 } while (enphy & ENPHY_ACCESS); 3014 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3015 } 3016 3017 /* 3018 * sip_sis900_mii_writereg: [mii interface function] 3019 * 3020 * Write a PHY register on the MII. 3021 */ 3022 void 3023 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 3024 { 3025 struct sip_softc *sc = (struct sip_softc *) self; 3026 u_int32_t enphy; 3027 3028 /* 3029 * The SiS 900 has only an internal PHY on the MII. Only allow 3030 * MII address 0. 3031 */ 3032 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 3033 sc->sc_rev < SIS_REV_635 && phy != 0) 3034 return; 3035 3036 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3037 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3038 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3039 do { 3040 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3041 } while (enphy & ENPHY_ACCESS); 3042 } 3043 3044 /* 3045 * sip_sis900_mii_statchg: [mii interface function] 3046 * 3047 * Callback from MII layer when media changes. 3048 */ 3049 void 3050 SIP_DECL(sis900_mii_statchg)(struct device *self) 3051 { 3052 struct sip_softc *sc = (struct sip_softc *) self; 3053 u_int32_t flowctl; 3054 3055 /* 3056 * Update TXCFG for full-duplex operation. 3057 */ 3058 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3059 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3060 else 3061 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3062 3063 /* 3064 * Update RXCFG for full-duplex or loopback. 3065 */ 3066 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3067 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3068 sc->sc_rxcfg |= RXCFG_ATX; 3069 else 3070 sc->sc_rxcfg &= ~RXCFG_ATX; 3071 3072 /* 3073 * Update IMR for use of 802.3x flow control. 3074 */ 3075 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 3076 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3077 flowctl = FLOWCTL_FLOWEN; 3078 } else { 3079 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3080 flowctl = 0; 3081 } 3082 3083 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3084 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3085 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3086 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3087 } 3088 3089 /* 3090 * sip_dp83815_mii_readreg: [mii interface function] 3091 * 3092 * Read a PHY register on the MII. 3093 */ 3094 int 3095 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 3096 { 3097 struct sip_softc *sc = (struct sip_softc *) self; 3098 u_int32_t val; 3099 3100 /* 3101 * The DP83815 only has an internal PHY. Only allow 3102 * MII address 0. 3103 */ 3104 if (phy != 0) 3105 return (0); 3106 3107 /* 3108 * Apparently, after a reset, the DP83815 can take a while 3109 * to respond. During this recovery period, the BMSR returns 3110 * a value of 0. Catch this -- it's not supposed to happen 3111 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3112 * PHY to come back to life. 3113 * 3114 * This works out because the BMSR is the first register 3115 * read during the PHY probe process. 3116 */ 3117 do { 3118 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3119 } while (reg == MII_BMSR && val == 0); 3120 3121 return (val & 0xffff); 3122 } 3123 3124 /* 3125 * sip_dp83815_mii_writereg: [mii interface function] 3126 * 3127 * Write a PHY register to the MII. 3128 */ 3129 void 3130 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3131 { 3132 struct sip_softc *sc = (struct sip_softc *) self; 3133 3134 /* 3135 * The DP83815 only has an internal PHY. Only allow 3136 * MII address 0. 3137 */ 3138 if (phy != 0) 3139 return; 3140 3141 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3142 } 3143 3144 /* 3145 * sip_dp83815_mii_statchg: [mii interface function] 3146 * 3147 * Callback from MII layer when media changes. 3148 */ 3149 void 3150 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3151 { 3152 struct sip_softc *sc = (struct sip_softc *) self; 3153 3154 /* 3155 * Update TXCFG for full-duplex operation. 3156 */ 3157 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3158 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3159 else 3160 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3161 3162 /* 3163 * Update RXCFG for full-duplex or loopback. 3164 */ 3165 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3166 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3167 sc->sc_rxcfg |= RXCFG_ATX; 3168 else 3169 sc->sc_rxcfg &= ~RXCFG_ATX; 3170 3171 /* 3172 * XXX 802.3x flow control. 3173 */ 3174 3175 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3176 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3177 } 3178 #endif /* DP83820 */ 3179 3180 #if defined(DP83820) 3181 void 3182 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3183 const struct pci_attach_args *pa, u_int8_t *enaddr) 3184 { 3185 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3186 u_int8_t cksum, *e, match; 3187 int i; 3188 3189 /* 3190 * EEPROM data format for the DP83820 can be found in 3191 * the DP83820 manual, section 4.2.4. 3192 */ 3193 3194 SIP_DECL(read_eeprom)(sc, 0, 3195 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3196 3197 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3198 match = ~(match - 1); 3199 3200 cksum = 0x55; 3201 e = (u_int8_t *) eeprom_data; 3202 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3203 cksum += *e++; 3204 3205 if (cksum != match) 3206 printf("%s: Checksum (%x) mismatch (%x)", 3207 sc->sc_dev.dv_xname, cksum, match); 3208 3209 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3210 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3211 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3212 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3213 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3214 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3215 3216 /* Get the GPIOR bits. */ 3217 sc->sc_gpior = eeprom_data[0x04]; 3218 } 3219 #else /* ! DP83820 */ 3220 void 3221 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3222 const struct pci_attach_args *pa, u_int8_t *enaddr) 3223 { 3224 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3225 3226 switch (sc->sc_rev) { 3227 case SIS_REV_630S: 3228 case SIS_REV_630E: 3229 case SIS_REV_630EA1: 3230 case SIS_REV_630ET: 3231 case SIS_REV_635: 3232 /* 3233 * The MAC address for the on-board Ethernet of 3234 * the SiS 630 chipset is in the NVRAM. Kick 3235 * the chip into re-loading it from NVRAM, and 3236 * read the MAC address out of the filter registers. 3237 */ 3238 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3239 3240 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3241 RFCR_RFADDR_NODE0); 3242 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3243 0xffff; 3244 3245 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3246 RFCR_RFADDR_NODE2); 3247 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3248 0xffff; 3249 3250 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3251 RFCR_RFADDR_NODE4); 3252 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3253 0xffff; 3254 break; 3255 3256 default: 3257 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3258 sizeof(myea) / sizeof(myea[0]), myea); 3259 } 3260 3261 enaddr[0] = myea[0] & 0xff; 3262 enaddr[1] = myea[0] >> 8; 3263 enaddr[2] = myea[1] & 0xff; 3264 enaddr[3] = myea[1] >> 8; 3265 enaddr[4] = myea[2] & 0xff; 3266 enaddr[5] = myea[2] >> 8; 3267 } 3268 3269 /* Table and macro to bit-reverse an octet. */ 3270 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3271 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3272 3273 void 3274 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3275 const struct pci_attach_args *pa, u_int8_t *enaddr) 3276 { 3277 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3278 u_int8_t cksum, *e, match; 3279 int i; 3280 3281 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3282 sizeof(eeprom_data[0]), eeprom_data); 3283 3284 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3285 match = ~(match - 1); 3286 3287 cksum = 0x55; 3288 e = (u_int8_t *) eeprom_data; 3289 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3290 cksum += *e++; 3291 } 3292 if (cksum != match) { 3293 printf("%s: Checksum (%x) mismatch (%x)", 3294 sc->sc_dev.dv_xname, cksum, match); 3295 } 3296 3297 /* 3298 * Unrolled because it makes slightly more sense this way. 3299 * The DP83815 stores the MAC address in bit 0 of word 6 3300 * through bit 15 of word 8. 3301 */ 3302 ea = &eeprom_data[6]; 3303 enaddr[0] = ((*ea & 0x1) << 7); 3304 ea++; 3305 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3306 enaddr[1] = ((*ea & 0x1FE) >> 1); 3307 enaddr[2] = ((*ea & 0x1) << 7); 3308 ea++; 3309 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3310 enaddr[3] = ((*ea & 0x1FE) >> 1); 3311 enaddr[4] = ((*ea & 0x1) << 7); 3312 ea++; 3313 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3314 enaddr[5] = ((*ea & 0x1FE) >> 1); 3315 3316 /* 3317 * In case that's not weird enough, we also need to reverse 3318 * the bits in each byte. This all actually makes more sense 3319 * if you think about the EEPROM storage as an array of bits 3320 * being shifted into bytes, but that's not how we're looking 3321 * at it here... 3322 */ 3323 for (i = 0; i < 6 ;i++) 3324 enaddr[i] = bbr(enaddr[i]); 3325 } 3326 #endif /* DP83820 */ 3327 3328 /* 3329 * sip_mediastatus: [ifmedia interface function] 3330 * 3331 * Get the current interface media status. 3332 */ 3333 void 3334 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3335 { 3336 struct sip_softc *sc = ifp->if_softc; 3337 3338 mii_pollstat(&sc->sc_mii); 3339 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3340 ifmr->ifm_active = sc->sc_mii.mii_media_active; 3341 } 3342 3343 /* 3344 * sip_mediachange: [ifmedia interface function] 3345 * 3346 * Set hardware to newly-selected media. 3347 */ 3348 int 3349 SIP_DECL(mediachange)(struct ifnet *ifp) 3350 { 3351 struct sip_softc *sc = ifp->if_softc; 3352 3353 if (ifp->if_flags & IFF_UP) 3354 mii_mediachg(&sc->sc_mii); 3355 return (0); 3356 } 3357
Indexes created Tue Sep 30 11:09:46 GMT 2025