if_sip.c revision 1.24.2.11
1 /* $NetBSD: if_sip.c,v 1.24.2.11 2002/08/27 23:46:48 nathanw Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.24.2.11 2002/08/27 23:46:48 nathanw Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <machine/bus.h> 116 #include <machine/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #ifdef DP83820 122 #include <dev/mii/mii_bitbang.h> 123 #endif /* DP83820 */ 124 125 #include <dev/pci/pcireg.h> 126 #include <dev/pci/pcivar.h> 127 #include <dev/pci/pcidevs.h> 128 129 #include <dev/pci/if_sipreg.h> 130 131 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 132 #define SIP_DECL(x) __CONCAT(gsip_,x) 133 #else /* SiS900 and DP83815 */ 134 #define SIP_DECL(x) __CONCAT(sip_,x) 135 #endif 136 137 #define SIP_STR(x) __STRING(SIP_DECL(x)) 138 139 /* 140 * Transmit descriptor list size. This is arbitrary, but allocate 141 * enough descriptors for 128 pending transmissions, and 8 segments 142 * per packet. This MUST work out to a power of 2. 143 */ 144 #define SIP_NTXSEGS 16 145 #define SIP_NTXSEGS_ALLOC 8 146 147 #define SIP_TXQUEUELEN 256 148 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 149 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 150 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 151 152 #if defined(DP83020) 153 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 154 #else 155 #define TX_DMAMAP_SIZE MCLBYTES 156 #endif 157 158 /* 159 * Receive descriptor list size. We have one Rx buffer per incoming 160 * packet, so this logic is a little simpler. 161 * 162 * Actually, on the DP83820, we allow the packet to consume more than 163 * one buffer, in order to support jumbo Ethernet frames. In that 164 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 165 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 166 * so we'd better be quick about handling receive interrupts. 167 */ 168 #if defined(DP83820) 169 #define SIP_NRXDESC 256 170 #else 171 #define SIP_NRXDESC 128 172 #endif /* DP83820 */ 173 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 174 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 175 176 /* 177 * Control structures are DMA'd to the SiS900 chip. We allocate them in 178 * a single clump that maps to a single DMA segment to make several things 179 * easier. 180 */ 181 struct sip_control_data { 182 /* 183 * The transmit descriptors. 184 */ 185 struct sip_desc scd_txdescs[SIP_NTXDESC]; 186 187 /* 188 * The receive descriptors. 189 */ 190 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 191 }; 192 193 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 194 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 195 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 196 197 /* 198 * Software state for transmit jobs. 199 */ 200 struct sip_txsoft { 201 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 202 bus_dmamap_t txs_dmamap; /* our DMA map */ 203 int txs_firstdesc; /* first descriptor in packet */ 204 int txs_lastdesc; /* last descriptor in packet */ 205 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 206 }; 207 208 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 209 210 /* 211 * Software state for receive jobs. 212 */ 213 struct sip_rxsoft { 214 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 215 bus_dmamap_t rxs_dmamap; /* our DMA map */ 216 }; 217 218 /* 219 * Software state per device. 220 */ 221 struct sip_softc { 222 struct device sc_dev; /* generic device information */ 223 bus_space_tag_t sc_st; /* bus space tag */ 224 bus_space_handle_t sc_sh; /* bus space handle */ 225 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 226 struct ethercom sc_ethercom; /* ethernet common data */ 227 void *sc_sdhook; /* shutdown hook */ 228 229 const struct sip_product *sc_model; /* which model are we? */ 230 int sc_rev; /* chip revision */ 231 232 void *sc_ih; /* interrupt cookie */ 233 234 struct mii_data sc_mii; /* MII/media information */ 235 236 struct callout sc_tick_ch; /* tick callout */ 237 238 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 239 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 240 241 /* 242 * Software state for transmit and receive descriptors. 243 */ 244 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 245 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 246 247 /* 248 * Control data structures. 249 */ 250 struct sip_control_data *sc_control_data; 251 #define sc_txdescs sc_control_data->scd_txdescs 252 #define sc_rxdescs sc_control_data->scd_rxdescs 253 254 #ifdef SIP_EVENT_COUNTERS 255 /* 256 * Event counters. 257 */ 258 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 259 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 260 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 261 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 262 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 263 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 264 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 265 #ifdef DP83820 266 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 267 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 268 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 269 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 270 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 271 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 272 #endif /* DP83820 */ 273 #endif /* SIP_EVENT_COUNTERS */ 274 275 u_int32_t sc_txcfg; /* prototype TXCFG register */ 276 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 277 u_int32_t sc_imr; /* prototype IMR register */ 278 u_int32_t sc_rfcr; /* prototype RFCR register */ 279 280 u_int32_t sc_cfg; /* prototype CFG register */ 281 282 #ifdef DP83820 283 u_int32_t sc_gpior; /* prototype GPIOR register */ 284 #endif /* DP83820 */ 285 286 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 287 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 288 289 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 290 291 int sc_flags; /* misc. flags; see below */ 292 293 int sc_txfree; /* number of free Tx descriptors */ 294 int sc_txnext; /* next ready Tx descriptor */ 295 int sc_txwin; /* Tx descriptors since last intr */ 296 297 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 298 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 299 300 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 301 #if defined(DP83820) 302 int sc_rxdiscard; 303 int sc_rxlen; 304 struct mbuf *sc_rxhead; 305 struct mbuf *sc_rxtail; 306 struct mbuf **sc_rxtailp; 307 #endif /* DP83820 */ 308 309 #if NRND > 0 310 rndsource_element_t rnd_source; /* random source */ 311 #endif 312 }; 313 314 /* sc_flags */ 315 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 316 317 #ifdef DP83820 318 #define SIP_RXCHAIN_RESET(sc) \ 319 do { \ 320 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 321 *(sc)->sc_rxtailp = NULL; \ 322 (sc)->sc_rxlen = 0; \ 323 } while (/*CONSTCOND*/0) 324 325 #define SIP_RXCHAIN_LINK(sc, m) \ 326 do { \ 327 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 328 (sc)->sc_rxtailp = &(m)->m_next; \ 329 } while (/*CONSTCOND*/0) 330 #endif /* DP83820 */ 331 332 #ifdef SIP_EVENT_COUNTERS 333 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 334 #else 335 #define SIP_EVCNT_INCR(ev) /* nothing */ 336 #endif 337 338 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 339 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 340 341 #define SIP_CDTXSYNC(sc, x, n, ops) \ 342 do { \ 343 int __x, __n; \ 344 \ 345 __x = (x); \ 346 __n = (n); \ 347 \ 348 /* If it will wrap around, sync to the end of the ring. */ \ 349 if ((__x + __n) > SIP_NTXDESC) { \ 350 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 351 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 352 (SIP_NTXDESC - __x), (ops)); \ 353 __n -= (SIP_NTXDESC - __x); \ 354 __x = 0; \ 355 } \ 356 \ 357 /* Now sync whatever is left. */ \ 358 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 359 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 360 } while (0) 361 362 #define SIP_CDRXSYNC(sc, x, ops) \ 363 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 364 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 365 366 #ifdef DP83820 367 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 368 #define SIP_RXBUF_LEN (MCLBYTES - 4) 369 #else 370 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 371 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 372 #endif 373 #define SIP_INIT_RXDESC(sc, x) \ 374 do { \ 375 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 376 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 377 \ 378 __sipd->sipd_link = \ 379 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 380 __sipd->sipd_bufptr = \ 381 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 382 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 383 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 384 SIP_INIT_RXDESC_EXTSTS \ 385 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 386 } while (0) 387 388 #define SIP_CHIP_VERS(sc, v, p, r) \ 389 ((sc)->sc_model->sip_vendor == (v) && \ 390 (sc)->sc_model->sip_product == (p) && \ 391 (sc)->sc_rev == (r)) 392 393 #define SIP_CHIP_MODEL(sc, v, p) \ 394 ((sc)->sc_model->sip_vendor == (v) && \ 395 (sc)->sc_model->sip_product == (p)) 396 397 #if !defined(DP83820) 398 #define SIP_SIS900_REV(sc, rev) \ 399 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 400 #endif 401 402 #define SIP_TIMEOUT 1000 403 404 void SIP_DECL(start)(struct ifnet *); 405 void SIP_DECL(watchdog)(struct ifnet *); 406 int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 407 int SIP_DECL(init)(struct ifnet *); 408 void SIP_DECL(stop)(struct ifnet *, int); 409 410 void SIP_DECL(shutdown)(void *); 411 412 void SIP_DECL(reset)(struct sip_softc *); 413 void SIP_DECL(rxdrain)(struct sip_softc *); 414 int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 415 void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, u_int16_t *); 416 void SIP_DECL(tick)(void *); 417 418 #if !defined(DP83820) 419 void SIP_DECL(sis900_set_filter)(struct sip_softc *); 420 #endif /* ! DP83820 */ 421 void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 422 423 #if defined(DP83820) 424 void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 425 const struct pci_attach_args *, u_int8_t *); 426 #else 427 void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 428 const struct pci_attach_args *, u_int8_t *); 429 void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 430 const struct pci_attach_args *, u_int8_t *); 431 #endif /* DP83820 */ 432 433 int SIP_DECL(intr)(void *); 434 void SIP_DECL(txintr)(struct sip_softc *); 435 void SIP_DECL(rxintr)(struct sip_softc *); 436 437 #if defined(DP83820) 438 int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 439 void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 440 void SIP_DECL(dp83820_mii_statchg)(struct device *); 441 #else 442 int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 443 void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 444 void SIP_DECL(sis900_mii_statchg)(struct device *); 445 446 int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 447 void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 448 void SIP_DECL(dp83815_mii_statchg)(struct device *); 449 #endif /* DP83820 */ 450 451 int SIP_DECL(mediachange)(struct ifnet *); 452 void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 453 454 int SIP_DECL(match)(struct device *, struct cfdata *, void *); 455 void SIP_DECL(attach)(struct device *, struct device *, void *); 456 457 int SIP_DECL(copy_small) = 0; 458 459 struct cfattach SIP_DECL(ca) = { 460 sizeof(struct sip_softc), SIP_DECL(match), SIP_DECL(attach), 461 }; 462 463 /* 464 * Descriptions of the variants of the SiS900. 465 */ 466 struct sip_variant { 467 int (*sipv_mii_readreg)(struct device *, int, int); 468 void (*sipv_mii_writereg)(struct device *, int, int, int); 469 void (*sipv_mii_statchg)(struct device *); 470 void (*sipv_set_filter)(struct sip_softc *); 471 void (*sipv_read_macaddr)(struct sip_softc *, 472 const struct pci_attach_args *, u_int8_t *); 473 }; 474 475 #if defined(DP83820) 476 u_int32_t SIP_DECL(dp83820_mii_bitbang_read)(struct device *); 477 void SIP_DECL(dp83820_mii_bitbang_write)(struct device *, u_int32_t); 478 479 const struct mii_bitbang_ops SIP_DECL(dp83820_mii_bitbang_ops) = { 480 SIP_DECL(dp83820_mii_bitbang_read), 481 SIP_DECL(dp83820_mii_bitbang_write), 482 { 483 EROMAR_MDIO, /* MII_BIT_MDO */ 484 EROMAR_MDIO, /* MII_BIT_MDI */ 485 EROMAR_MDC, /* MII_BIT_MDC */ 486 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 487 0, /* MII_BIT_DIR_PHY_HOST */ 488 } 489 }; 490 #endif /* DP83820 */ 491 492 #if defined(DP83820) 493 const struct sip_variant SIP_DECL(variant_dp83820) = { 494 SIP_DECL(dp83820_mii_readreg), 495 SIP_DECL(dp83820_mii_writereg), 496 SIP_DECL(dp83820_mii_statchg), 497 SIP_DECL(dp83815_set_filter), 498 SIP_DECL(dp83820_read_macaddr), 499 }; 500 #else 501 const struct sip_variant SIP_DECL(variant_sis900) = { 502 SIP_DECL(sis900_mii_readreg), 503 SIP_DECL(sis900_mii_writereg), 504 SIP_DECL(sis900_mii_statchg), 505 SIP_DECL(sis900_set_filter), 506 SIP_DECL(sis900_read_macaddr), 507 }; 508 509 const struct sip_variant SIP_DECL(variant_dp83815) = { 510 SIP_DECL(dp83815_mii_readreg), 511 SIP_DECL(dp83815_mii_writereg), 512 SIP_DECL(dp83815_mii_statchg), 513 SIP_DECL(dp83815_set_filter), 514 SIP_DECL(dp83815_read_macaddr), 515 }; 516 #endif /* DP83820 */ 517 518 /* 519 * Devices supported by this driver. 520 */ 521 const struct sip_product { 522 pci_vendor_id_t sip_vendor; 523 pci_product_id_t sip_product; 524 const char *sip_name; 525 const struct sip_variant *sip_variant; 526 } SIP_DECL(products)[] = { 527 #if defined(DP83820) 528 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 529 "NatSemi DP83820 Gigabit Ethernet", 530 &SIP_DECL(variant_dp83820) }, 531 #else 532 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 533 "SiS 900 10/100 Ethernet", 534 &SIP_DECL(variant_sis900) }, 535 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 536 "SiS 7016 10/100 Ethernet", 537 &SIP_DECL(variant_sis900) }, 538 539 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 540 "NatSemi DP83815 10/100 Ethernet", 541 &SIP_DECL(variant_dp83815) }, 542 #endif /* DP83820 */ 543 544 { 0, 0, 545 NULL, 546 NULL }, 547 }; 548 549 static const struct sip_product * 550 SIP_DECL(lookup)(const struct pci_attach_args *pa) 551 { 552 const struct sip_product *sip; 553 554 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 555 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 556 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 557 return (sip); 558 } 559 return (NULL); 560 } 561 562 #ifdef DP83820 563 /* 564 * I really hate stupid hardware vendors. There's a bit in the EEPROM 565 * which indicates if the card can do 64-bit data transfers. Unfortunately, 566 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 567 * which means we try to use 64-bit data transfers on those cards if we 568 * happen to be plugged into a 32-bit slot. 569 * 570 * What we do is use this table of cards known to be 64-bit cards. If 571 * you have a 64-bit card who's subsystem ID is not listed in this table, 572 * send the output of "pcictl dump ..." of the device to me so that your 573 * card will use the 64-bit data path when plugged into a 64-bit slot. 574 * 575 * -- Jason R. Thorpe <thorpej (at) netbsd.org> 576 * June 30, 2002 577 */ 578 static int 579 SIP_DECL(check_64bit)(const struct pci_attach_args *pa) 580 { 581 static const struct { 582 pci_vendor_id_t c64_vendor; 583 pci_product_id_t c64_product; 584 } card64[] = { 585 /* Asante GigaNIX */ 586 { 0x128a, 0x0002 }, 587 588 /* Accton EN1407-T, Planex GN-1000TE */ 589 { 0x1113, 0x1407 }, 590 591 /* Netgear GA-621 */ 592 { 0x1385, 0x621a }, 593 594 { 0, 0} 595 }; 596 pcireg_t subsys; 597 int i; 598 599 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 600 601 for (i = 0; card64[i].c64_vendor != 0; i++) { 602 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 603 PCI_PRODUCT(subsys) == card64[i].c64_product) 604 return (1); 605 } 606 607 return (0); 608 } 609 #endif /* DP83820 */ 610 611 int 612 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 613 { 614 struct pci_attach_args *pa = aux; 615 616 if (SIP_DECL(lookup)(pa) != NULL) 617 return (1); 618 619 return (0); 620 } 621 622 void 623 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 624 { 625 struct sip_softc *sc = (struct sip_softc *) self; 626 struct pci_attach_args *pa = aux; 627 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 628 pci_chipset_tag_t pc = pa->pa_pc; 629 pci_intr_handle_t ih; 630 const char *intrstr = NULL; 631 bus_space_tag_t iot, memt; 632 bus_space_handle_t ioh, memh; 633 bus_dma_segment_t seg; 634 int ioh_valid, memh_valid; 635 int i, rseg, error; 636 const struct sip_product *sip; 637 pcireg_t pmode; 638 u_int8_t enaddr[ETHER_ADDR_LEN]; 639 int pmreg; 640 #ifdef DP83820 641 pcireg_t memtype; 642 u_int32_t reg; 643 #endif /* DP83820 */ 644 645 callout_init(&sc->sc_tick_ch); 646 647 sip = SIP_DECL(lookup)(pa); 648 if (sip == NULL) { 649 printf("\n"); 650 panic(SIP_STR(attach) ": impossible"); 651 } 652 sc->sc_rev = PCI_REVISION(pa->pa_class); 653 654 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 655 656 sc->sc_model = sip; 657 658 /* 659 * XXX Work-around broken PXE firmware on some boards. 660 * 661 * The DP83815 shares an address decoder with the MEM BAR 662 * and the ROM BAR. Make sure the ROM BAR is disabled, 663 * so that memory mapped access works. 664 */ 665 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 666 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 667 ~PCI_MAPREG_ROM_ENABLE); 668 669 /* 670 * Map the device. 671 */ 672 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 673 PCI_MAPREG_TYPE_IO, 0, 674 &iot, &ioh, NULL, NULL) == 0); 675 #ifdef DP83820 676 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 677 switch (memtype) { 678 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 679 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 680 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 681 memtype, 0, &memt, &memh, NULL, NULL) == 0); 682 break; 683 default: 684 memh_valid = 0; 685 } 686 #else 687 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 688 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 689 &memt, &memh, NULL, NULL) == 0); 690 #endif /* DP83820 */ 691 692 if (memh_valid) { 693 sc->sc_st = memt; 694 sc->sc_sh = memh; 695 } else if (ioh_valid) { 696 sc->sc_st = iot; 697 sc->sc_sh = ioh; 698 } else { 699 printf("%s: unable to map device registers\n", 700 sc->sc_dev.dv_xname); 701 return; 702 } 703 704 sc->sc_dmat = pa->pa_dmat; 705 706 /* 707 * Make sure bus mastering is enabled. Also make sure 708 * Write/Invalidate is enabled if we're allowed to use it. 709 */ 710 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 711 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 712 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 713 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 714 pmreg | PCI_COMMAND_MASTER_ENABLE); 715 716 /* Get it out of power save mode if needed. */ 717 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 718 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 719 if (pmode == 3) { 720 /* 721 * The card has lost all configuration data in 722 * this state, so punt. 723 */ 724 printf("%s: unable to wake up from power state D3\n", 725 sc->sc_dev.dv_xname); 726 return; 727 } 728 if (pmode != 0) { 729 printf("%s: waking up from power state D%d\n", 730 sc->sc_dev.dv_xname, pmode); 731 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 732 } 733 } 734 735 /* 736 * Map and establish our interrupt. 737 */ 738 if (pci_intr_map(pa, &ih)) { 739 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 740 return; 741 } 742 intrstr = pci_intr_string(pc, ih); 743 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 744 if (sc->sc_ih == NULL) { 745 printf("%s: unable to establish interrupt", 746 sc->sc_dev.dv_xname); 747 if (intrstr != NULL) 748 printf(" at %s", intrstr); 749 printf("\n"); 750 return; 751 } 752 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 753 754 SIMPLEQ_INIT(&sc->sc_txfreeq); 755 SIMPLEQ_INIT(&sc->sc_txdirtyq); 756 757 /* 758 * Allocate the control data structures, and create and load the 759 * DMA map for it. 760 */ 761 if ((error = bus_dmamem_alloc(sc->sc_dmat, 762 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 763 0)) != 0) { 764 printf("%s: unable to allocate control data, error = %d\n", 765 sc->sc_dev.dv_xname, error); 766 goto fail_0; 767 } 768 769 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 770 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 771 BUS_DMA_COHERENT)) != 0) { 772 printf("%s: unable to map control data, error = %d\n", 773 sc->sc_dev.dv_xname, error); 774 goto fail_1; 775 } 776 777 if ((error = bus_dmamap_create(sc->sc_dmat, 778 sizeof(struct sip_control_data), 1, 779 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 780 printf("%s: unable to create control data DMA map, " 781 "error = %d\n", sc->sc_dev.dv_xname, error); 782 goto fail_2; 783 } 784 785 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 786 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 787 0)) != 0) { 788 printf("%s: unable to load control data DMA map, error = %d\n", 789 sc->sc_dev.dv_xname, error); 790 goto fail_3; 791 } 792 793 /* 794 * Create the transmit buffer DMA maps. 795 */ 796 for (i = 0; i < SIP_TXQUEUELEN; i++) { 797 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 798 SIP_NTXSEGS, MCLBYTES, 0, 0, 799 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 800 printf("%s: unable to create tx DMA map %d, " 801 "error = %d\n", sc->sc_dev.dv_xname, i, error); 802 goto fail_4; 803 } 804 } 805 806 /* 807 * Create the receive buffer DMA maps. 808 */ 809 for (i = 0; i < SIP_NRXDESC; i++) { 810 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 811 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 812 printf("%s: unable to create rx DMA map %d, " 813 "error = %d\n", sc->sc_dev.dv_xname, i, error); 814 goto fail_5; 815 } 816 sc->sc_rxsoft[i].rxs_mbuf = NULL; 817 } 818 819 /* 820 * Reset the chip to a known state. 821 */ 822 SIP_DECL(reset)(sc); 823 824 /* 825 * Read the Ethernet address from the EEPROM. This might 826 * also fetch other stuff from the EEPROM and stash it 827 * in the softc. 828 */ 829 sc->sc_cfg = 0; 830 #if !defined(DP83820) 831 if (SIP_SIS900_REV(sc,SIS_REV_635) || 832 SIP_SIS900_REV(sc,SIS_REV_900B)) 833 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 834 #endif 835 836 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 837 838 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 839 ether_sprintf(enaddr)); 840 841 /* 842 * Initialize the configuration register: aggressive PCI 843 * bus request algorithm, default backoff, default OW timer, 844 * default parity error detection. 845 * 846 * NOTE: "Big endian mode" is useless on the SiS900 and 847 * friends -- it affects packet data, not descriptors. 848 */ 849 #ifdef DP83820 850 /* 851 * Cause the chip to load configuration data from the EEPROM. 852 */ 853 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 854 for (i = 0; i < 10000; i++) { 855 delay(10); 856 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 857 PTSCR_EELOAD_EN) == 0) 858 break; 859 } 860 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 861 PTSCR_EELOAD_EN) { 862 printf("%s: timeout loading configuration from EEPROM\n", 863 sc->sc_dev.dv_xname); 864 return; 865 } 866 867 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 868 869 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 870 if (reg & CFG_PCI64_DET) { 871 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 872 /* 873 * Check to see if this card is 64-bit. If so, enable 64-bit 874 * data transfers. 875 * 876 * We can't use the DATA64_EN bit in the EEPROM, because 877 * vendors of 32-bit cards fail to clear that bit in many 878 * cases (yet the card still detects that it's in a 64-bit 879 * slot; go figure). 880 */ 881 if (SIP_DECL(check_64bit)(pa)) { 882 sc->sc_cfg |= CFG_DATA64_EN; 883 printf(", using 64-bit data transfers"); 884 } 885 printf("\n"); 886 } 887 888 /* 889 * XXX Need some PCI flags indicating support for 890 * XXX 64-bit addressing. 891 */ 892 #if 0 893 if (reg & CFG_M64ADDR) 894 sc->sc_cfg |= CFG_M64ADDR; 895 if (reg & CFG_T64ADDR) 896 sc->sc_cfg |= CFG_T64ADDR; 897 #endif 898 899 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 900 const char *sep = ""; 901 printf("%s: using ", sc->sc_dev.dv_xname); 902 if (reg & CFG_EXT_125) { 903 sc->sc_cfg |= CFG_EXT_125; 904 printf("%s125MHz clock", sep); 905 sep = ", "; 906 } 907 if (reg & CFG_TBI_EN) { 908 sc->sc_cfg |= CFG_TBI_EN; 909 printf("%sten-bit interface", sep); 910 sep = ", "; 911 } 912 printf("\n"); 913 } 914 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 915 (reg & CFG_MRM_DIS) != 0) 916 sc->sc_cfg |= CFG_MRM_DIS; 917 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 918 (reg & CFG_MWI_DIS) != 0) 919 sc->sc_cfg |= CFG_MWI_DIS; 920 921 /* 922 * Use the extended descriptor format on the DP83820. This 923 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 924 * checksumming. 925 */ 926 sc->sc_cfg |= CFG_EXTSTS_EN; 927 #endif /* DP83820 */ 928 929 /* 930 * Initialize our media structures and probe the MII. 931 */ 932 sc->sc_mii.mii_ifp = ifp; 933 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 934 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 935 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 936 ifmedia_init(&sc->sc_mii.mii_media, 0, SIP_DECL(mediachange), 937 SIP_DECL(mediastatus)); 938 939 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 940 MII_OFFSET_ANY, 0); 941 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 942 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 943 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 944 } else 945 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 946 947 ifp = &sc->sc_ethercom.ec_if; 948 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 949 ifp->if_softc = sc; 950 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 951 ifp->if_ioctl = SIP_DECL(ioctl); 952 ifp->if_start = SIP_DECL(start); 953 ifp->if_watchdog = SIP_DECL(watchdog); 954 ifp->if_init = SIP_DECL(init); 955 ifp->if_stop = SIP_DECL(stop); 956 IFQ_SET_READY(&ifp->if_snd); 957 958 /* 959 * We can support 802.1Q VLAN-sized frames. 960 */ 961 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 962 963 #ifdef DP83820 964 /* 965 * And the DP83820 can do VLAN tagging in hardware, and 966 * support the jumbo Ethernet MTU. 967 */ 968 sc->sc_ethercom.ec_capabilities |= 969 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 970 971 /* 972 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 973 * in hardware. 974 */ 975 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 976 IFCAP_CSUM_UDPv4; 977 #endif /* DP83820 */ 978 979 /* 980 * Attach the interface. 981 */ 982 if_attach(ifp); 983 ether_ifattach(ifp, enaddr); 984 #if NRND > 0 985 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 986 RND_TYPE_NET, 0); 987 #endif 988 989 /* 990 * The number of bytes that must be available in 991 * the Tx FIFO before the bus master can DMA more 992 * data into the FIFO. 993 */ 994 sc->sc_tx_fill_thresh = 64 / 32; 995 996 /* 997 * Start at a drain threshold of 512 bytes. We will 998 * increase it if a DMA underrun occurs. 999 * 1000 * XXX The minimum value of this variable should be 1001 * tuned. We may be able to improve performance 1002 * by starting with a lower value. That, however, 1003 * may trash the first few outgoing packets if the 1004 * PCI bus is saturated. 1005 */ 1006 sc->sc_tx_drain_thresh = 1504 / 32; 1007 1008 /* 1009 * Initialize the Rx FIFO drain threshold. 1010 * 1011 * This is in units of 8 bytes. 1012 * 1013 * We should never set this value lower than 2; 14 bytes are 1014 * required to filter the packet. 1015 */ 1016 sc->sc_rx_drain_thresh = 128 / 8; 1017 1018 #ifdef SIP_EVENT_COUNTERS 1019 /* 1020 * Attach event counters. 1021 */ 1022 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1023 NULL, sc->sc_dev.dv_xname, "txsstall"); 1024 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1025 NULL, sc->sc_dev.dv_xname, "txdstall"); 1026 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1027 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1028 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1029 NULL, sc->sc_dev.dv_xname, "txdintr"); 1030 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1031 NULL, sc->sc_dev.dv_xname, "txiintr"); 1032 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1033 NULL, sc->sc_dev.dv_xname, "rxintr"); 1034 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1035 NULL, sc->sc_dev.dv_xname, "hiberr"); 1036 #ifdef DP83820 1037 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1038 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1039 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1040 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1041 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1042 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1043 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1044 NULL, sc->sc_dev.dv_xname, "txipsum"); 1045 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1046 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1047 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1048 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1049 #endif /* DP83820 */ 1050 #endif /* SIP_EVENT_COUNTERS */ 1051 1052 /* 1053 * Make sure the interface is shutdown during reboot. 1054 */ 1055 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 1056 if (sc->sc_sdhook == NULL) 1057 printf("%s: WARNING: unable to establish shutdown hook\n", 1058 sc->sc_dev.dv_xname); 1059 return; 1060 1061 /* 1062 * Free any resources we've allocated during the failed attach 1063 * attempt. Do this in reverse order and fall through. 1064 */ 1065 fail_5: 1066 for (i = 0; i < SIP_NRXDESC; i++) { 1067 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1068 bus_dmamap_destroy(sc->sc_dmat, 1069 sc->sc_rxsoft[i].rxs_dmamap); 1070 } 1071 fail_4: 1072 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1073 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1074 bus_dmamap_destroy(sc->sc_dmat, 1075 sc->sc_txsoft[i].txs_dmamap); 1076 } 1077 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1078 fail_3: 1079 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1080 fail_2: 1081 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1082 sizeof(struct sip_control_data)); 1083 fail_1: 1084 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1085 fail_0: 1086 return; 1087 } 1088 1089 /* 1090 * sip_shutdown: 1091 * 1092 * Make sure the interface is stopped at reboot time. 1093 */ 1094 void 1095 SIP_DECL(shutdown)(void *arg) 1096 { 1097 struct sip_softc *sc = arg; 1098 1099 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1100 } 1101 1102 /* 1103 * sip_start: [ifnet interface function] 1104 * 1105 * Start packet transmission on the interface. 1106 */ 1107 void 1108 SIP_DECL(start)(struct ifnet *ifp) 1109 { 1110 struct sip_softc *sc = ifp->if_softc; 1111 struct mbuf *m0, *m; 1112 struct sip_txsoft *txs; 1113 bus_dmamap_t dmamap; 1114 int error, nexttx, lasttx, seg; 1115 int ofree = sc->sc_txfree; 1116 #if 0 1117 int firsttx = sc->sc_txnext; 1118 #endif 1119 #ifdef DP83820 1120 u_int32_t extsts; 1121 #endif 1122 1123 /* 1124 * If we've been told to pause, don't transmit any more packets. 1125 */ 1126 if (sc->sc_flags & SIPF_PAUSED) 1127 ifp->if_flags |= IFF_OACTIVE; 1128 1129 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1130 return; 1131 1132 /* 1133 * Loop through the send queue, setting up transmit descriptors 1134 * until we drain the queue, or use up all available transmit 1135 * descriptors. 1136 */ 1137 for (;;) { 1138 /* Get a work queue entry. */ 1139 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1140 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1141 break; 1142 } 1143 1144 /* 1145 * Grab a packet off the queue. 1146 */ 1147 IFQ_POLL(&ifp->if_snd, m0); 1148 if (m0 == NULL) 1149 break; 1150 #ifndef DP83820 1151 m = NULL; 1152 #endif 1153 1154 dmamap = txs->txs_dmamap; 1155 1156 #ifdef DP83820 1157 /* 1158 * Load the DMA map. If this fails, the packet either 1159 * didn't fit in the allotted number of segments, or we 1160 * were short on resources. For the too-many-segments 1161 * case, we simply report an error and drop the packet, 1162 * since we can't sanely copy a jumbo packet to a single 1163 * buffer. 1164 */ 1165 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1166 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1167 if (error) { 1168 if (error == EFBIG) { 1169 printf("%s: Tx packet consumes too many " 1170 "DMA segments, dropping...\n", 1171 sc->sc_dev.dv_xname); 1172 IFQ_DEQUEUE(&ifp->if_snd, m0); 1173 m_freem(m0); 1174 continue; 1175 } 1176 /* 1177 * Short on resources, just stop for now. 1178 */ 1179 break; 1180 } 1181 #else /* DP83820 */ 1182 /* 1183 * Load the DMA map. If this fails, the packet either 1184 * didn't fit in the alloted number of segments, or we 1185 * were short on resources. In this case, we'll copy 1186 * and try again. 1187 */ 1188 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1189 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1190 MGETHDR(m, M_DONTWAIT, MT_DATA); 1191 if (m == NULL) { 1192 printf("%s: unable to allocate Tx mbuf\n", 1193 sc->sc_dev.dv_xname); 1194 break; 1195 } 1196 if (m0->m_pkthdr.len > MHLEN) { 1197 MCLGET(m, M_DONTWAIT); 1198 if ((m->m_flags & M_EXT) == 0) { 1199 printf("%s: unable to allocate Tx " 1200 "cluster\n", sc->sc_dev.dv_xname); 1201 m_freem(m); 1202 break; 1203 } 1204 } 1205 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1206 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1207 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1208 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1209 if (error) { 1210 printf("%s: unable to load Tx buffer, " 1211 "error = %d\n", sc->sc_dev.dv_xname, error); 1212 break; 1213 } 1214 } 1215 #endif /* DP83820 */ 1216 1217 /* 1218 * Ensure we have enough descriptors free to describe 1219 * the packet. Note, we always reserve one descriptor 1220 * at the end of the ring as a termination point, to 1221 * prevent wrap-around. 1222 */ 1223 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1224 /* 1225 * Not enough free descriptors to transmit this 1226 * packet. We haven't committed anything yet, 1227 * so just unload the DMA map, put the packet 1228 * back on the queue, and punt. Notify the upper 1229 * layer that there are not more slots left. 1230 * 1231 * XXX We could allocate an mbuf and copy, but 1232 * XXX is it worth it? 1233 */ 1234 ifp->if_flags |= IFF_OACTIVE; 1235 bus_dmamap_unload(sc->sc_dmat, dmamap); 1236 #ifndef DP83820 1237 if (m != NULL) 1238 m_freem(m); 1239 #endif 1240 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1241 break; 1242 } 1243 1244 IFQ_DEQUEUE(&ifp->if_snd, m0); 1245 #ifndef DP83820 1246 if (m != NULL) { 1247 m_freem(m0); 1248 m0 = m; 1249 } 1250 #endif 1251 1252 /* 1253 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1254 */ 1255 1256 /* Sync the DMA map. */ 1257 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1258 BUS_DMASYNC_PREWRITE); 1259 1260 /* 1261 * Initialize the transmit descriptors. 1262 */ 1263 for (nexttx = sc->sc_txnext, seg = 0; 1264 seg < dmamap->dm_nsegs; 1265 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1266 /* 1267 * If this is the first descriptor we're 1268 * enqueueing, don't set the OWN bit just 1269 * yet. That could cause a race condition. 1270 * We'll do it below. 1271 */ 1272 sc->sc_txdescs[nexttx].sipd_bufptr = 1273 htole32(dmamap->dm_segs[seg].ds_addr); 1274 sc->sc_txdescs[nexttx].sipd_cmdsts = 1275 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1276 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1277 #ifdef DP83820 1278 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1279 #endif /* DP83820 */ 1280 lasttx = nexttx; 1281 } 1282 1283 /* Clear the MORE bit on the last segment. */ 1284 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1285 1286 /* 1287 * If we're in the interrupt delay window, delay the 1288 * interrupt. 1289 */ 1290 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1291 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1292 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1293 htole32(CMDSTS_INTR); 1294 sc->sc_txwin = 0; 1295 } 1296 1297 #ifdef DP83820 1298 /* 1299 * If VLANs are enabled and the packet has a VLAN tag, set 1300 * up the descriptor to encapsulate the packet for us. 1301 * 1302 * This apparently has to be on the last descriptor of 1303 * the packet. 1304 */ 1305 if (sc->sc_ethercom.ec_nvlans != 0 && 1306 (m = m_aux_find(m0, AF_LINK, ETHERTYPE_VLAN)) != NULL) { 1307 sc->sc_txdescs[lasttx].sipd_extsts |= 1308 htole32(EXTSTS_VPKT | 1309 htons(*mtod(m, int *) & EXTSTS_VTCI)); 1310 } 1311 1312 /* 1313 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1314 * checksumming, set up the descriptor to do this work 1315 * for us. 1316 * 1317 * This apparently has to be on the first descriptor of 1318 * the packet. 1319 * 1320 * Byte-swap constants so the compiler can optimize. 1321 */ 1322 extsts = 0; 1323 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1324 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1325 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1326 extsts |= htole32(EXTSTS_IPPKT); 1327 } 1328 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1329 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1330 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1331 extsts |= htole32(EXTSTS_TCPPKT); 1332 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1333 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1334 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1335 extsts |= htole32(EXTSTS_UDPPKT); 1336 } 1337 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1338 #endif /* DP83820 */ 1339 1340 /* Sync the descriptors we're using. */ 1341 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1342 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1343 1344 /* 1345 * The entire packet is set up. Give the first descrptor 1346 * to the chip now. 1347 */ 1348 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1349 htole32(CMDSTS_OWN); 1350 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1351 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1352 1353 /* 1354 * Store a pointer to the packet so we can free it later, 1355 * and remember what txdirty will be once the packet is 1356 * done. 1357 */ 1358 txs->txs_mbuf = m0; 1359 txs->txs_firstdesc = sc->sc_txnext; 1360 txs->txs_lastdesc = lasttx; 1361 1362 /* Advance the tx pointer. */ 1363 sc->sc_txfree -= dmamap->dm_nsegs; 1364 sc->sc_txnext = nexttx; 1365 1366 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1367 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1368 1369 #if NBPFILTER > 0 1370 /* 1371 * Pass the packet to any BPF listeners. 1372 */ 1373 if (ifp->if_bpf) 1374 bpf_mtap(ifp->if_bpf, m0); 1375 #endif /* NBPFILTER > 0 */ 1376 } 1377 1378 if (txs == NULL || sc->sc_txfree == 0) { 1379 /* No more slots left; notify upper layer. */ 1380 ifp->if_flags |= IFF_OACTIVE; 1381 } 1382 1383 if (sc->sc_txfree != ofree) { 1384 /* 1385 * Start the transmit process. Note, the manual says 1386 * that if there are no pending transmissions in the 1387 * chip's internal queue (indicated by TXE being clear), 1388 * then the driver software must set the TXDP to the 1389 * first descriptor to be transmitted. However, if we 1390 * do this, it causes serious performance degredation on 1391 * the DP83820 under load, not setting TXDP doesn't seem 1392 * to adversely affect the SiS 900 or DP83815. 1393 * 1394 * Well, I guess it wouldn't be the first time a manual 1395 * has lied -- and they could be speaking of the NULL- 1396 * terminated descriptor list case, rather than OWN- 1397 * terminated rings. 1398 */ 1399 #if 0 1400 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1401 CR_TXE) == 0) { 1402 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1403 SIP_CDTXADDR(sc, firsttx)); 1404 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1405 } 1406 #else 1407 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1408 #endif 1409 1410 /* Set a watchdog timer in case the chip flakes out. */ 1411 ifp->if_timer = 5; 1412 } 1413 } 1414 1415 /* 1416 * sip_watchdog: [ifnet interface function] 1417 * 1418 * Watchdog timer handler. 1419 */ 1420 void 1421 SIP_DECL(watchdog)(struct ifnet *ifp) 1422 { 1423 struct sip_softc *sc = ifp->if_softc; 1424 1425 /* 1426 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1427 * If we get a timeout, try and sweep up transmit descriptors. 1428 * If we manage to sweep them all up, ignore the lack of 1429 * interrupt. 1430 */ 1431 SIP_DECL(txintr)(sc); 1432 1433 if (sc->sc_txfree != SIP_NTXDESC) { 1434 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1435 ifp->if_oerrors++; 1436 1437 /* Reset the interface. */ 1438 (void) SIP_DECL(init)(ifp); 1439 } else if (ifp->if_flags & IFF_DEBUG) 1440 printf("%s: recovered from device timeout\n", 1441 sc->sc_dev.dv_xname); 1442 1443 /* Try to get more packets going. */ 1444 SIP_DECL(start)(ifp); 1445 } 1446 1447 /* 1448 * sip_ioctl: [ifnet interface function] 1449 * 1450 * Handle control requests from the operator. 1451 */ 1452 int 1453 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1454 { 1455 struct sip_softc *sc = ifp->if_softc; 1456 struct ifreq *ifr = (struct ifreq *)data; 1457 int s, error; 1458 1459 s = splnet(); 1460 1461 switch (cmd) { 1462 case SIOCSIFMEDIA: 1463 case SIOCGIFMEDIA: 1464 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1465 break; 1466 1467 default: 1468 error = ether_ioctl(ifp, cmd, data); 1469 if (error == ENETRESET) { 1470 /* 1471 * Multicast list has changed; set the hardware filter 1472 * accordingly. 1473 */ 1474 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1475 error = 0; 1476 } 1477 break; 1478 } 1479 1480 /* Try to get more packets going. */ 1481 SIP_DECL(start)(ifp); 1482 1483 splx(s); 1484 return (error); 1485 } 1486 1487 /* 1488 * sip_intr: 1489 * 1490 * Interrupt service routine. 1491 */ 1492 int 1493 SIP_DECL(intr)(void *arg) 1494 { 1495 struct sip_softc *sc = arg; 1496 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1497 u_int32_t isr; 1498 int handled = 0; 1499 1500 for (;;) { 1501 /* Reading clears interrupt. */ 1502 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1503 if ((isr & sc->sc_imr) == 0) 1504 break; 1505 1506 #if NRND > 0 1507 if (RND_ENABLED(&sc->rnd_source)) 1508 rnd_add_uint32(&sc->rnd_source, isr); 1509 #endif 1510 1511 handled = 1; 1512 1513 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1514 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1515 1516 /* Grab any new packets. */ 1517 SIP_DECL(rxintr)(sc); 1518 1519 if (isr & ISR_RXORN) { 1520 printf("%s: receive FIFO overrun\n", 1521 sc->sc_dev.dv_xname); 1522 1523 /* XXX adjust rx_drain_thresh? */ 1524 } 1525 1526 if (isr & ISR_RXIDLE) { 1527 printf("%s: receive ring overrun\n", 1528 sc->sc_dev.dv_xname); 1529 1530 /* Get the receive process going again. */ 1531 bus_space_write_4(sc->sc_st, sc->sc_sh, 1532 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1533 bus_space_write_4(sc->sc_st, sc->sc_sh, 1534 SIP_CR, CR_RXE); 1535 } 1536 } 1537 1538 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1539 #ifdef SIP_EVENT_COUNTERS 1540 if (isr & ISR_TXDESC) 1541 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1542 else if (isr & ISR_TXIDLE) 1543 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1544 #endif 1545 1546 /* Sweep up transmit descriptors. */ 1547 SIP_DECL(txintr)(sc); 1548 1549 if (isr & ISR_TXURN) { 1550 u_int32_t thresh; 1551 1552 printf("%s: transmit FIFO underrun", 1553 sc->sc_dev.dv_xname); 1554 1555 thresh = sc->sc_tx_drain_thresh + 1; 1556 if (thresh <= TXCFG_DRTH && 1557 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1558 (sc->sc_tx_fill_thresh * 32))) { 1559 printf("; increasing Tx drain " 1560 "threshold to %u bytes\n", 1561 thresh * 32); 1562 sc->sc_tx_drain_thresh = thresh; 1563 (void) SIP_DECL(init)(ifp); 1564 } else { 1565 (void) SIP_DECL(init)(ifp); 1566 printf("\n"); 1567 } 1568 } 1569 } 1570 1571 #if !defined(DP83820) 1572 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1573 if (isr & ISR_PAUSE_ST) { 1574 sc->sc_flags |= SIPF_PAUSED; 1575 ifp->if_flags |= IFF_OACTIVE; 1576 } 1577 if (isr & ISR_PAUSE_END) { 1578 sc->sc_flags &= ~SIPF_PAUSED; 1579 ifp->if_flags &= ~IFF_OACTIVE; 1580 } 1581 } 1582 #endif /* ! DP83820 */ 1583 1584 if (isr & ISR_HIBERR) { 1585 int want_init = 0; 1586 1587 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1588 1589 #define PRINTERR(bit, str) \ 1590 do { \ 1591 if ((isr & (bit)) != 0) { \ 1592 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1593 printf("%s: %s\n", \ 1594 sc->sc_dev.dv_xname, str); \ 1595 want_init = 1; \ 1596 } \ 1597 } while (/*CONSTCOND*/0) 1598 1599 PRINTERR(ISR_DPERR, "parity error"); 1600 PRINTERR(ISR_SSERR, "system error"); 1601 PRINTERR(ISR_RMABT, "master abort"); 1602 PRINTERR(ISR_RTABT, "target abort"); 1603 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1604 /* 1605 * Ignore: 1606 * Tx reset complete 1607 * Rx reset complete 1608 */ 1609 if (want_init) 1610 (void) SIP_DECL(init)(ifp); 1611 #undef PRINTERR 1612 } 1613 } 1614 1615 /* Try to get more packets going. */ 1616 SIP_DECL(start)(ifp); 1617 1618 return (handled); 1619 } 1620 1621 /* 1622 * sip_txintr: 1623 * 1624 * Helper; handle transmit interrupts. 1625 */ 1626 void 1627 SIP_DECL(txintr)(struct sip_softc *sc) 1628 { 1629 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1630 struct sip_txsoft *txs; 1631 u_int32_t cmdsts; 1632 1633 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1634 ifp->if_flags &= ~IFF_OACTIVE; 1635 1636 /* 1637 * Go through our Tx list and free mbufs for those 1638 * frames which have been transmitted. 1639 */ 1640 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1641 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1642 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1643 1644 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1645 if (cmdsts & CMDSTS_OWN) 1646 break; 1647 1648 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1649 1650 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1651 1652 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1653 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1654 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1655 m_freem(txs->txs_mbuf); 1656 txs->txs_mbuf = NULL; 1657 1658 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1659 1660 /* 1661 * Check for errors and collisions. 1662 */ 1663 if (cmdsts & 1664 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1665 ifp->if_oerrors++; 1666 if (cmdsts & CMDSTS_Tx_EC) 1667 ifp->if_collisions += 16; 1668 if (ifp->if_flags & IFF_DEBUG) { 1669 if (cmdsts & CMDSTS_Tx_ED) 1670 printf("%s: excessive deferral\n", 1671 sc->sc_dev.dv_xname); 1672 if (cmdsts & CMDSTS_Tx_EC) 1673 printf("%s: excessive collisions\n", 1674 sc->sc_dev.dv_xname); 1675 } 1676 } else { 1677 /* Packet was transmitted successfully. */ 1678 ifp->if_opackets++; 1679 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1680 } 1681 } 1682 1683 /* 1684 * If there are no more pending transmissions, cancel the watchdog 1685 * timer. 1686 */ 1687 if (txs == NULL) { 1688 ifp->if_timer = 0; 1689 sc->sc_txwin = 0; 1690 } 1691 } 1692 1693 #if defined(DP83820) 1694 /* 1695 * sip_rxintr: 1696 * 1697 * Helper; handle receive interrupts. 1698 */ 1699 void 1700 SIP_DECL(rxintr)(struct sip_softc *sc) 1701 { 1702 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1703 struct sip_rxsoft *rxs; 1704 struct mbuf *m, *tailm; 1705 u_int32_t cmdsts, extsts; 1706 int i, len; 1707 1708 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1709 rxs = &sc->sc_rxsoft[i]; 1710 1711 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1712 1713 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1714 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1715 1716 /* 1717 * NOTE: OWN is set if owned by _consumer_. We're the 1718 * consumer of the receive ring, so if the bit is clear, 1719 * we have processed all of the packets. 1720 */ 1721 if ((cmdsts & CMDSTS_OWN) == 0) { 1722 /* 1723 * We have processed all of the receive buffers. 1724 */ 1725 break; 1726 } 1727 1728 if (__predict_false(sc->sc_rxdiscard)) { 1729 SIP_INIT_RXDESC(sc, i); 1730 if ((cmdsts & CMDSTS_MORE) == 0) { 1731 /* Reset our state. */ 1732 sc->sc_rxdiscard = 0; 1733 } 1734 continue; 1735 } 1736 1737 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1738 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1739 1740 m = rxs->rxs_mbuf; 1741 1742 /* 1743 * Add a new receive buffer to the ring. 1744 */ 1745 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1746 /* 1747 * Failed, throw away what we've done so 1748 * far, and discard the rest of the packet. 1749 */ 1750 ifp->if_ierrors++; 1751 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1752 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1753 SIP_INIT_RXDESC(sc, i); 1754 if (cmdsts & CMDSTS_MORE) 1755 sc->sc_rxdiscard = 1; 1756 if (sc->sc_rxhead != NULL) 1757 m_freem(sc->sc_rxhead); 1758 SIP_RXCHAIN_RESET(sc); 1759 continue; 1760 } 1761 1762 SIP_RXCHAIN_LINK(sc, m); 1763 1764 /* 1765 * If this is not the end of the packet, keep 1766 * looking. 1767 */ 1768 if (cmdsts & CMDSTS_MORE) { 1769 sc->sc_rxlen += m->m_len; 1770 continue; 1771 } 1772 1773 /* 1774 * Okay, we have the entire packet now... 1775 */ 1776 *sc->sc_rxtailp = NULL; 1777 m = sc->sc_rxhead; 1778 tailm = sc->sc_rxtail; 1779 1780 SIP_RXCHAIN_RESET(sc); 1781 1782 /* 1783 * If an error occurred, update stats and drop the packet. 1784 */ 1785 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1786 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1787 ifp->if_ierrors++; 1788 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1789 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1790 /* Receive overrun handled elsewhere. */ 1791 printf("%s: receive descriptor error\n", 1792 sc->sc_dev.dv_xname); 1793 } 1794 #define PRINTERR(bit, str) \ 1795 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1796 (cmdsts & (bit)) != 0) \ 1797 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1798 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1799 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1800 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1801 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1802 #undef PRINTERR 1803 m_freem(m); 1804 continue; 1805 } 1806 1807 /* 1808 * No errors. 1809 * 1810 * Note, the DP83820 includes the CRC with 1811 * every packet. 1812 */ 1813 len = CMDSTS_SIZE(cmdsts); 1814 tailm->m_len = len - sc->sc_rxlen; 1815 1816 /* 1817 * If the packet is small enough to fit in a 1818 * single header mbuf, allocate one and copy 1819 * the data into it. This greatly reduces 1820 * memory consumption when we receive lots 1821 * of small packets. 1822 */ 1823 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1824 struct mbuf *nm; 1825 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1826 if (nm == NULL) { 1827 ifp->if_ierrors++; 1828 m_freem(m); 1829 continue; 1830 } 1831 nm->m_data += 2; 1832 nm->m_pkthdr.len = nm->m_len = len; 1833 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1834 m_freem(m); 1835 m = nm; 1836 } 1837 #ifndef __NO_STRICT_ALIGNMENT 1838 else { 1839 /* 1840 * The DP83820's receive buffers must be 4-byte 1841 * aligned. But this means that the data after 1842 * the Ethernet header is misaligned. To compensate, 1843 * we have artificially shortened the buffer size 1844 * in the descriptor, and we do an overlapping copy 1845 * of the data two bytes further in (in the first 1846 * buffer of the chain only). 1847 */ 1848 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1849 m->m_len); 1850 m->m_data += 2; 1851 } 1852 #endif /* ! __NO_STRICT_ALIGNMENT */ 1853 1854 /* 1855 * If VLANs are enabled, VLAN packets have been unwrapped 1856 * for us. Associate the tag with the packet. 1857 */ 1858 if (sc->sc_ethercom.ec_nvlans != 0 && 1859 (extsts & EXTSTS_VPKT) != 0) { 1860 struct mbuf *vtag; 1861 1862 vtag = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 1863 if (vtag == NULL) { 1864 ifp->if_ierrors++; 1865 printf("%s: unable to allocate VLAN tag\n", 1866 sc->sc_dev.dv_xname); 1867 m_freem(m); 1868 continue; 1869 } 1870 1871 *mtod(vtag, int *) = ntohs(extsts & EXTSTS_VTCI); 1872 vtag->m_len = sizeof(int); 1873 } 1874 1875 /* 1876 * Set the incoming checksum information for the 1877 * packet. 1878 */ 1879 if ((extsts & EXTSTS_IPPKT) != 0) { 1880 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1881 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1882 if (extsts & EXTSTS_Rx_IPERR) 1883 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1884 if (extsts & EXTSTS_TCPPKT) { 1885 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1886 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1887 if (extsts & EXTSTS_Rx_TCPERR) 1888 m->m_pkthdr.csum_flags |= 1889 M_CSUM_TCP_UDP_BAD; 1890 } else if (extsts & EXTSTS_UDPPKT) { 1891 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1892 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1893 if (extsts & EXTSTS_Rx_UDPERR) 1894 m->m_pkthdr.csum_flags |= 1895 M_CSUM_TCP_UDP_BAD; 1896 } 1897 } 1898 1899 ifp->if_ipackets++; 1900 m->m_flags |= M_HASFCS; 1901 m->m_pkthdr.rcvif = ifp; 1902 m->m_pkthdr.len = len; 1903 1904 #if NBPFILTER > 0 1905 /* 1906 * Pass this up to any BPF listeners, but only 1907 * pass if up the stack if it's for us. 1908 */ 1909 if (ifp->if_bpf) 1910 bpf_mtap(ifp->if_bpf, m); 1911 #endif /* NBPFILTER > 0 */ 1912 1913 /* Pass it on. */ 1914 (*ifp->if_input)(ifp, m); 1915 } 1916 1917 /* Update the receive pointer. */ 1918 sc->sc_rxptr = i; 1919 } 1920 #else /* ! DP83820 */ 1921 /* 1922 * sip_rxintr: 1923 * 1924 * Helper; handle receive interrupts. 1925 */ 1926 void 1927 SIP_DECL(rxintr)(struct sip_softc *sc) 1928 { 1929 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1930 struct sip_rxsoft *rxs; 1931 struct mbuf *m; 1932 u_int32_t cmdsts; 1933 int i, len; 1934 1935 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1936 rxs = &sc->sc_rxsoft[i]; 1937 1938 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1939 1940 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1941 1942 /* 1943 * NOTE: OWN is set if owned by _consumer_. We're the 1944 * consumer of the receive ring, so if the bit is clear, 1945 * we have processed all of the packets. 1946 */ 1947 if ((cmdsts & CMDSTS_OWN) == 0) { 1948 /* 1949 * We have processed all of the receive buffers. 1950 */ 1951 break; 1952 } 1953 1954 /* 1955 * If any collisions were seen on the wire, count one. 1956 */ 1957 if (cmdsts & CMDSTS_Rx_COL) 1958 ifp->if_collisions++; 1959 1960 /* 1961 * If an error occurred, update stats, clear the status 1962 * word, and leave the packet buffer in place. It will 1963 * simply be reused the next time the ring comes around. 1964 */ 1965 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1966 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1967 ifp->if_ierrors++; 1968 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1969 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1970 /* Receive overrun handled elsewhere. */ 1971 printf("%s: receive descriptor error\n", 1972 sc->sc_dev.dv_xname); 1973 } 1974 #define PRINTERR(bit, str) \ 1975 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1976 (cmdsts & (bit)) != 0) \ 1977 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1978 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1979 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1980 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1981 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1982 #undef PRINTERR 1983 SIP_INIT_RXDESC(sc, i); 1984 continue; 1985 } 1986 1987 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1988 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1989 1990 /* 1991 * No errors; receive the packet. Note, the SiS 900 1992 * includes the CRC with every packet. 1993 */ 1994 len = CMDSTS_SIZE(cmdsts); 1995 1996 #ifdef __NO_STRICT_ALIGNMENT 1997 /* 1998 * If the packet is small enough to fit in a 1999 * single header mbuf, allocate one and copy 2000 * the data into it. This greatly reduces 2001 * memory consumption when we receive lots 2002 * of small packets. 2003 * 2004 * Otherwise, we add a new buffer to the receive 2005 * chain. If this fails, we drop the packet and 2006 * recycle the old buffer. 2007 */ 2008 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 2009 MGETHDR(m, M_DONTWAIT, MT_DATA); 2010 if (m == NULL) 2011 goto dropit; 2012 memcpy(mtod(m, caddr_t), 2013 mtod(rxs->rxs_mbuf, caddr_t), len); 2014 SIP_INIT_RXDESC(sc, i); 2015 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2016 rxs->rxs_dmamap->dm_mapsize, 2017 BUS_DMASYNC_PREREAD); 2018 } else { 2019 m = rxs->rxs_mbuf; 2020 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 2021 dropit: 2022 ifp->if_ierrors++; 2023 SIP_INIT_RXDESC(sc, i); 2024 bus_dmamap_sync(sc->sc_dmat, 2025 rxs->rxs_dmamap, 0, 2026 rxs->rxs_dmamap->dm_mapsize, 2027 BUS_DMASYNC_PREREAD); 2028 continue; 2029 } 2030 } 2031 #else 2032 /* 2033 * The SiS 900's receive buffers must be 4-byte aligned. 2034 * But this means that the data after the Ethernet header 2035 * is misaligned. We must allocate a new buffer and 2036 * copy the data, shifted forward 2 bytes. 2037 */ 2038 MGETHDR(m, M_DONTWAIT, MT_DATA); 2039 if (m == NULL) { 2040 dropit: 2041 ifp->if_ierrors++; 2042 SIP_INIT_RXDESC(sc, i); 2043 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2044 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2045 continue; 2046 } 2047 if (len > (MHLEN - 2)) { 2048 MCLGET(m, M_DONTWAIT); 2049 if ((m->m_flags & M_EXT) == 0) { 2050 m_freem(m); 2051 goto dropit; 2052 } 2053 } 2054 m->m_data += 2; 2055 2056 /* 2057 * Note that we use clusters for incoming frames, so the 2058 * buffer is virtually contiguous. 2059 */ 2060 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 2061 2062 /* Allow the receive descriptor to continue using its mbuf. */ 2063 SIP_INIT_RXDESC(sc, i); 2064 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2065 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2066 #endif /* __NO_STRICT_ALIGNMENT */ 2067 2068 ifp->if_ipackets++; 2069 m->m_flags |= M_HASFCS; 2070 m->m_pkthdr.rcvif = ifp; 2071 m->m_pkthdr.len = m->m_len = len; 2072 2073 #if NBPFILTER > 0 2074 /* 2075 * Pass this up to any BPF listeners, but only 2076 * pass if up the stack if it's for us. 2077 */ 2078 if (ifp->if_bpf) 2079 bpf_mtap(ifp->if_bpf, m); 2080 #endif /* NBPFILTER > 0 */ 2081 2082 /* Pass it on. */ 2083 (*ifp->if_input)(ifp, m); 2084 } 2085 2086 /* Update the receive pointer. */ 2087 sc->sc_rxptr = i; 2088 } 2089 #endif /* DP83820 */ 2090 2091 /* 2092 * sip_tick: 2093 * 2094 * One second timer, used to tick the MII. 2095 */ 2096 void 2097 SIP_DECL(tick)(void *arg) 2098 { 2099 struct sip_softc *sc = arg; 2100 int s; 2101 2102 s = splnet(); 2103 mii_tick(&sc->sc_mii); 2104 splx(s); 2105 2106 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2107 } 2108 2109 /* 2110 * sip_reset: 2111 * 2112 * Perform a soft reset on the SiS 900. 2113 */ 2114 void 2115 SIP_DECL(reset)(struct sip_softc *sc) 2116 { 2117 bus_space_tag_t st = sc->sc_st; 2118 bus_space_handle_t sh = sc->sc_sh; 2119 int i; 2120 2121 bus_space_write_4(st, sh, SIP_IER, 0); 2122 bus_space_write_4(st, sh, SIP_IMR, 0); 2123 bus_space_write_4(st, sh, SIP_RFCR, 0); 2124 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2125 2126 for (i = 0; i < SIP_TIMEOUT; i++) { 2127 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2128 break; 2129 delay(2); 2130 } 2131 2132 if (i == SIP_TIMEOUT) 2133 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2134 2135 delay(1000); 2136 2137 #ifdef DP83820 2138 /* 2139 * Set the general purpose I/O bits. Do it here in case we 2140 * need to have GPIO set up to talk to the media interface. 2141 */ 2142 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2143 delay(1000); 2144 #endif /* DP83820 */ 2145 } 2146 2147 /* 2148 * sip_init: [ ifnet interface function ] 2149 * 2150 * Initialize the interface. Must be called at splnet(). 2151 */ 2152 int 2153 SIP_DECL(init)(struct ifnet *ifp) 2154 { 2155 struct sip_softc *sc = ifp->if_softc; 2156 bus_space_tag_t st = sc->sc_st; 2157 bus_space_handle_t sh = sc->sc_sh; 2158 struct sip_txsoft *txs; 2159 struct sip_rxsoft *rxs; 2160 struct sip_desc *sipd; 2161 u_int32_t reg; 2162 int i, error = 0; 2163 2164 /* 2165 * Cancel any pending I/O. 2166 */ 2167 SIP_DECL(stop)(ifp, 0); 2168 2169 /* 2170 * Reset the chip to a known state. 2171 */ 2172 SIP_DECL(reset)(sc); 2173 2174 #if !defined(DP83820) 2175 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2176 /* 2177 * DP83815 manual, page 78: 2178 * 4.4 Recommended Registers Configuration 2179 * For optimum performance of the DP83815, version noted 2180 * as DP83815CVNG (SRR = 203h), the listed register 2181 * modifications must be followed in sequence... 2182 * 2183 * It's not clear if this should be 302h or 203h because that 2184 * chip name is listed as SRR 302h in the description of the 2185 * SRR register. However, my revision 302h DP83815 on the 2186 * Netgear FA311 purchased in 02/2001 needs these settings 2187 * to avoid tons of errors in AcceptPerfectMatch (non- 2188 * IFF_PROMISC) mode. I do not know if other revisions need 2189 * this set or not. [briggs -- 09 March 2001] 2190 * 2191 * Note that only the low-order 12 bits of 0xe4 are documented 2192 * and that this sets reserved bits in that register. 2193 */ 2194 reg = bus_space_read_4(st, sh, SIP_NS_SRR); 2195 if (reg == 0x302) { 2196 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2197 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2198 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2199 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2200 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2201 } 2202 } 2203 #endif /* ! DP83820 */ 2204 2205 /* 2206 * Initialize the transmit descriptor ring. 2207 */ 2208 for (i = 0; i < SIP_NTXDESC; i++) { 2209 sipd = &sc->sc_txdescs[i]; 2210 memset(sipd, 0, sizeof(struct sip_desc)); 2211 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2212 } 2213 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2214 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2215 sc->sc_txfree = SIP_NTXDESC; 2216 sc->sc_txnext = 0; 2217 sc->sc_txwin = 0; 2218 2219 /* 2220 * Initialize the transmit job descriptors. 2221 */ 2222 SIMPLEQ_INIT(&sc->sc_txfreeq); 2223 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2224 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2225 txs = &sc->sc_txsoft[i]; 2226 txs->txs_mbuf = NULL; 2227 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2228 } 2229 2230 /* 2231 * Initialize the receive descriptor and receive job 2232 * descriptor rings. 2233 */ 2234 for (i = 0; i < SIP_NRXDESC; i++) { 2235 rxs = &sc->sc_rxsoft[i]; 2236 if (rxs->rxs_mbuf == NULL) { 2237 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2238 printf("%s: unable to allocate or map rx " 2239 "buffer %d, error = %d\n", 2240 sc->sc_dev.dv_xname, i, error); 2241 /* 2242 * XXX Should attempt to run with fewer receive 2243 * XXX buffers instead of just failing. 2244 */ 2245 SIP_DECL(rxdrain)(sc); 2246 goto out; 2247 } 2248 } else 2249 SIP_INIT_RXDESC(sc, i); 2250 } 2251 sc->sc_rxptr = 0; 2252 #ifdef DP83820 2253 sc->sc_rxdiscard = 0; 2254 SIP_RXCHAIN_RESET(sc); 2255 #endif /* DP83820 */ 2256 2257 /* 2258 * Set the configuration register; it's already initialized 2259 * in sip_attach(). 2260 */ 2261 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2262 2263 /* 2264 * Initialize the prototype TXCFG register. 2265 */ 2266 #if defined(DP83820) 2267 sc->sc_txcfg = TXCFG_MXDMA_512; 2268 sc->sc_rxcfg = RXCFG_MXDMA_512; 2269 #else 2270 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2271 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2272 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & CFG_EDBMASTEN)) { 2273 sc->sc_txcfg = TXCFG_MXDMA_64; 2274 sc->sc_rxcfg = RXCFG_MXDMA_64; 2275 } else { 2276 sc->sc_txcfg = TXCFG_MXDMA_512; 2277 sc->sc_rxcfg = RXCFG_MXDMA_512; 2278 } 2279 #endif /* DP83820 */ 2280 2281 sc->sc_txcfg |= TXCFG_ATP | 2282 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2283 sc->sc_tx_drain_thresh; 2284 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2285 2286 /* 2287 * Initialize the receive drain threshold if we have never 2288 * done so. 2289 */ 2290 if (sc->sc_rx_drain_thresh == 0) { 2291 /* 2292 * XXX This value should be tuned. This is set to the 2293 * maximum of 248 bytes, and we may be able to improve 2294 * performance by decreasing it (although we should never 2295 * set this value lower than 2; 14 bytes are required to 2296 * filter the packet). 2297 */ 2298 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2299 } 2300 2301 /* 2302 * Initialize the prototype RXCFG register. 2303 */ 2304 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2305 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2306 2307 #ifdef DP83820 2308 /* 2309 * Initialize the VLAN/IP receive control register. 2310 * We enable checksum computation on all incoming 2311 * packets, and do not reject packets w/ bad checksums. 2312 */ 2313 reg = 0; 2314 if (ifp->if_capenable & 2315 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2316 reg |= VRCR_IPEN; 2317 if (sc->sc_ethercom.ec_nvlans != 0) 2318 reg |= VRCR_VTDEN|VRCR_VTREN; 2319 bus_space_write_4(st, sh, SIP_VRCR, reg); 2320 2321 /* 2322 * Initialize the VLAN/IP transmit control register. 2323 * We enable outgoing checksum computation on a 2324 * per-packet basis. 2325 */ 2326 reg = 0; 2327 if (ifp->if_capenable & 2328 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2329 reg |= VTCR_PPCHK; 2330 if (sc->sc_ethercom.ec_nvlans != 0) 2331 reg |= VTCR_VPPTI; 2332 bus_space_write_4(st, sh, SIP_VTCR, reg); 2333 2334 /* 2335 * If we're using VLANs, initialize the VLAN data register. 2336 * To understand why we bswap the VLAN Ethertype, see section 2337 * 4.2.36 of the DP83820 manual. 2338 */ 2339 if (sc->sc_ethercom.ec_nvlans != 0) 2340 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2341 #endif /* DP83820 */ 2342 2343 /* 2344 * Give the transmit and receive rings to the chip. 2345 */ 2346 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2347 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2348 2349 /* 2350 * Initialize the interrupt mask. 2351 */ 2352 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2353 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2354 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2355 2356 /* Set up the receive filter. */ 2357 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2358 2359 /* 2360 * Set the current media. Do this after initializing the prototype 2361 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2362 * control. 2363 */ 2364 mii_mediachg(&sc->sc_mii); 2365 2366 /* 2367 * Enable interrupts. 2368 */ 2369 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2370 2371 /* 2372 * Start the transmit and receive processes. 2373 */ 2374 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2375 2376 /* 2377 * Start the one second MII clock. 2378 */ 2379 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2380 2381 /* 2382 * ...all done! 2383 */ 2384 ifp->if_flags |= IFF_RUNNING; 2385 ifp->if_flags &= ~IFF_OACTIVE; 2386 2387 out: 2388 if (error) 2389 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2390 return (error); 2391 } 2392 2393 /* 2394 * sip_drain: 2395 * 2396 * Drain the receive queue. 2397 */ 2398 void 2399 SIP_DECL(rxdrain)(struct sip_softc *sc) 2400 { 2401 struct sip_rxsoft *rxs; 2402 int i; 2403 2404 for (i = 0; i < SIP_NRXDESC; i++) { 2405 rxs = &sc->sc_rxsoft[i]; 2406 if (rxs->rxs_mbuf != NULL) { 2407 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2408 m_freem(rxs->rxs_mbuf); 2409 rxs->rxs_mbuf = NULL; 2410 } 2411 } 2412 } 2413 2414 /* 2415 * sip_stop: [ ifnet interface function ] 2416 * 2417 * Stop transmission on the interface. 2418 */ 2419 void 2420 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2421 { 2422 struct sip_softc *sc = ifp->if_softc; 2423 bus_space_tag_t st = sc->sc_st; 2424 bus_space_handle_t sh = sc->sc_sh; 2425 struct sip_txsoft *txs; 2426 u_int32_t cmdsts = 0; /* DEBUG */ 2427 2428 /* 2429 * Stop the one second clock. 2430 */ 2431 callout_stop(&sc->sc_tick_ch); 2432 2433 /* Down the MII. */ 2434 mii_down(&sc->sc_mii); 2435 2436 /* 2437 * Disable interrupts. 2438 */ 2439 bus_space_write_4(st, sh, SIP_IER, 0); 2440 2441 /* 2442 * Stop receiver and transmitter. 2443 */ 2444 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2445 2446 /* 2447 * Release any queued transmit buffers. 2448 */ 2449 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2450 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2451 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2452 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2453 CMDSTS_INTR) == 0) 2454 printf("%s: sip_stop: last descriptor does not " 2455 "have INTR bit set\n", sc->sc_dev.dv_xname); 2456 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2457 #ifdef DIAGNOSTIC 2458 if (txs->txs_mbuf == NULL) { 2459 printf("%s: dirty txsoft with no mbuf chain\n", 2460 sc->sc_dev.dv_xname); 2461 panic("sip_stop"); 2462 } 2463 #endif 2464 cmdsts |= /* DEBUG */ 2465 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2466 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2467 m_freem(txs->txs_mbuf); 2468 txs->txs_mbuf = NULL; 2469 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2470 } 2471 2472 if (disable) 2473 SIP_DECL(rxdrain)(sc); 2474 2475 /* 2476 * Mark the interface down and cancel the watchdog timer. 2477 */ 2478 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2479 ifp->if_timer = 0; 2480 2481 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2482 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2483 printf("%s: sip_stop: no INTR bits set in dirty tx " 2484 "descriptors\n", sc->sc_dev.dv_xname); 2485 } 2486 2487 /* 2488 * sip_read_eeprom: 2489 * 2490 * Read data from the serial EEPROM. 2491 */ 2492 void 2493 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2494 u_int16_t *data) 2495 { 2496 bus_space_tag_t st = sc->sc_st; 2497 bus_space_handle_t sh = sc->sc_sh; 2498 u_int16_t reg; 2499 int i, x; 2500 2501 for (i = 0; i < wordcnt; i++) { 2502 /* Send CHIP SELECT. */ 2503 reg = EROMAR_EECS; 2504 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2505 2506 /* Shift in the READ opcode. */ 2507 for (x = 3; x > 0; x--) { 2508 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2509 reg |= EROMAR_EEDI; 2510 else 2511 reg &= ~EROMAR_EEDI; 2512 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2513 bus_space_write_4(st, sh, SIP_EROMAR, 2514 reg | EROMAR_EESK); 2515 delay(4); 2516 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2517 delay(4); 2518 } 2519 2520 /* Shift in address. */ 2521 for (x = 6; x > 0; x--) { 2522 if ((word + i) & (1 << (x - 1))) 2523 reg |= EROMAR_EEDI; 2524 else 2525 reg &= ~EROMAR_EEDI; 2526 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2527 bus_space_write_4(st, sh, SIP_EROMAR, 2528 reg | EROMAR_EESK); 2529 delay(4); 2530 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2531 delay(4); 2532 } 2533 2534 /* Shift out data. */ 2535 reg = EROMAR_EECS; 2536 data[i] = 0; 2537 for (x = 16; x > 0; x--) { 2538 bus_space_write_4(st, sh, SIP_EROMAR, 2539 reg | EROMAR_EESK); 2540 delay(4); 2541 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2542 data[i] |= (1 << (x - 1)); 2543 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2544 delay(4); 2545 } 2546 2547 /* Clear CHIP SELECT. */ 2548 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2549 delay(4); 2550 } 2551 } 2552 2553 /* 2554 * sip_add_rxbuf: 2555 * 2556 * Add a receive buffer to the indicated descriptor. 2557 */ 2558 int 2559 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2560 { 2561 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2562 struct mbuf *m; 2563 int error; 2564 2565 MGETHDR(m, M_DONTWAIT, MT_DATA); 2566 if (m == NULL) 2567 return (ENOBUFS); 2568 2569 MCLGET(m, M_DONTWAIT); 2570 if ((m->m_flags & M_EXT) == 0) { 2571 m_freem(m); 2572 return (ENOBUFS); 2573 } 2574 2575 #if defined(DP83820) 2576 m->m_len = SIP_RXBUF_LEN; 2577 #endif /* DP83820 */ 2578 2579 if (rxs->rxs_mbuf != NULL) 2580 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2581 2582 rxs->rxs_mbuf = m; 2583 2584 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2585 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2586 BUS_DMA_READ|BUS_DMA_NOWAIT); 2587 if (error) { 2588 printf("%s: can't load rx DMA map %d, error = %d\n", 2589 sc->sc_dev.dv_xname, idx, error); 2590 panic("sip_add_rxbuf"); /* XXX */ 2591 } 2592 2593 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2594 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2595 2596 SIP_INIT_RXDESC(sc, idx); 2597 2598 return (0); 2599 } 2600 2601 #if !defined(DP83820) 2602 /* 2603 * sip_sis900_set_filter: 2604 * 2605 * Set up the receive filter. 2606 */ 2607 void 2608 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2609 { 2610 bus_space_tag_t st = sc->sc_st; 2611 bus_space_handle_t sh = sc->sc_sh; 2612 struct ethercom *ec = &sc->sc_ethercom; 2613 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2614 struct ether_multi *enm; 2615 u_int8_t *cp; 2616 struct ether_multistep step; 2617 u_int32_t crc, mchash[16]; 2618 2619 /* 2620 * Initialize the prototype RFCR. 2621 */ 2622 sc->sc_rfcr = RFCR_RFEN; 2623 if (ifp->if_flags & IFF_BROADCAST) 2624 sc->sc_rfcr |= RFCR_AAB; 2625 if (ifp->if_flags & IFF_PROMISC) { 2626 sc->sc_rfcr |= RFCR_AAP; 2627 goto allmulti; 2628 } 2629 2630 /* 2631 * Set up the multicast address filter by passing all multicast 2632 * addresses through a CRC generator, and then using the high-order 2633 * 6 bits as an index into the 128 bit multicast hash table (only 2634 * the lower 16 bits of each 32 bit multicast hash register are 2635 * valid). The high order bits select the register, while the 2636 * rest of the bits select the bit within the register. 2637 */ 2638 2639 memset(mchash, 0, sizeof(mchash)); 2640 2641 ETHER_FIRST_MULTI(step, ec, enm); 2642 while (enm != NULL) { 2643 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2644 /* 2645 * We must listen to a range of multicast addresses. 2646 * For now, just accept all multicasts, rather than 2647 * trying to set only those filter bits needed to match 2648 * the range. (At this time, the only use of address 2649 * ranges is for IP multicast routing, for which the 2650 * range is big enough to require all bits set.) 2651 */ 2652 goto allmulti; 2653 } 2654 2655 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2656 2657 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2658 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2659 /* Just want the 8 most significant bits. */ 2660 crc >>= 24; 2661 } else { 2662 /* Just want the 7 most significant bits. */ 2663 crc >>= 25; 2664 } 2665 2666 /* Set the corresponding bit in the hash table. */ 2667 mchash[crc >> 4] |= 1 << (crc & 0xf); 2668 2669 ETHER_NEXT_MULTI(step, enm); 2670 } 2671 2672 ifp->if_flags &= ~IFF_ALLMULTI; 2673 goto setit; 2674 2675 allmulti: 2676 ifp->if_flags |= IFF_ALLMULTI; 2677 sc->sc_rfcr |= RFCR_AAM; 2678 2679 setit: 2680 #define FILTER_EMIT(addr, data) \ 2681 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2682 delay(1); \ 2683 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2684 delay(1) 2685 2686 /* 2687 * Disable receive filter, and program the node address. 2688 */ 2689 cp = LLADDR(ifp->if_sadl); 2690 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2691 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2692 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2693 2694 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2695 /* 2696 * Program the multicast hash table. 2697 */ 2698 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2699 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2700 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2701 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2702 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2703 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2704 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2705 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2706 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2707 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2708 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2709 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2710 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2711 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2712 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2713 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2714 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2715 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2716 } 2717 } 2718 #undef FILTER_EMIT 2719 2720 /* 2721 * Re-enable the receiver filter. 2722 */ 2723 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2724 } 2725 #endif /* ! DP83820 */ 2726 2727 /* 2728 * sip_dp83815_set_filter: 2729 * 2730 * Set up the receive filter. 2731 */ 2732 void 2733 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2734 { 2735 bus_space_tag_t st = sc->sc_st; 2736 bus_space_handle_t sh = sc->sc_sh; 2737 struct ethercom *ec = &sc->sc_ethercom; 2738 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2739 struct ether_multi *enm; 2740 u_int8_t *cp; 2741 struct ether_multistep step; 2742 u_int32_t crc, hash, slot, bit; 2743 #ifdef DP83820 2744 #define MCHASH_NWORDS 128 2745 #else 2746 #define MCHASH_NWORDS 32 2747 #endif /* DP83820 */ 2748 u_int16_t mchash[MCHASH_NWORDS]; 2749 int i; 2750 2751 /* 2752 * Initialize the prototype RFCR. 2753 * Enable the receive filter, and accept on 2754 * Perfect (destination address) Match 2755 * If IFF_BROADCAST, also accept all broadcast packets. 2756 * If IFF_PROMISC, accept all unicast packets (and later, set 2757 * IFF_ALLMULTI and accept all multicast, too). 2758 */ 2759 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2760 if (ifp->if_flags & IFF_BROADCAST) 2761 sc->sc_rfcr |= RFCR_AAB; 2762 if (ifp->if_flags & IFF_PROMISC) { 2763 sc->sc_rfcr |= RFCR_AAP; 2764 goto allmulti; 2765 } 2766 2767 #ifdef DP83820 2768 /* 2769 * Set up the DP83820 multicast address filter by passing all multicast 2770 * addresses through a CRC generator, and then using the high-order 2771 * 11 bits as an index into the 2048 bit multicast hash table. The 2772 * high-order 7 bits select the slot, while the low-order 4 bits 2773 * select the bit within the slot. Note that only the low 16-bits 2774 * of each filter word are used, and there are 128 filter words. 2775 */ 2776 #else 2777 /* 2778 * Set up the DP83815 multicast address filter by passing all multicast 2779 * addresses through a CRC generator, and then using the high-order 2780 * 9 bits as an index into the 512 bit multicast hash table. The 2781 * high-order 5 bits select the slot, while the low-order 4 bits 2782 * select the bit within the slot. Note that only the low 16-bits 2783 * of each filter word are used, and there are 32 filter words. 2784 */ 2785 #endif /* DP83820 */ 2786 2787 memset(mchash, 0, sizeof(mchash)); 2788 2789 ifp->if_flags &= ~IFF_ALLMULTI; 2790 ETHER_FIRST_MULTI(step, ec, enm); 2791 if (enm == NULL) 2792 goto setit; 2793 while (enm != NULL) { 2794 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2795 /* 2796 * We must listen to a range of multicast addresses. 2797 * For now, just accept all multicasts, rather than 2798 * trying to set only those filter bits needed to match 2799 * the range. (At this time, the only use of address 2800 * ranges is for IP multicast routing, for which the 2801 * range is big enough to require all bits set.) 2802 */ 2803 goto allmulti; 2804 } 2805 2806 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2807 2808 #ifdef DP83820 2809 /* Just want the 11 most significant bits. */ 2810 hash = crc >> 21; 2811 #else 2812 /* Just want the 9 most significant bits. */ 2813 hash = crc >> 23; 2814 #endif /* DP83820 */ 2815 2816 slot = hash >> 4; 2817 bit = hash & 0xf; 2818 2819 /* Set the corresponding bit in the hash table. */ 2820 mchash[slot] |= 1 << bit; 2821 2822 ETHER_NEXT_MULTI(step, enm); 2823 } 2824 sc->sc_rfcr |= RFCR_MHEN; 2825 goto setit; 2826 2827 allmulti: 2828 ifp->if_flags |= IFF_ALLMULTI; 2829 sc->sc_rfcr |= RFCR_AAM; 2830 2831 setit: 2832 #define FILTER_EMIT(addr, data) \ 2833 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2834 delay(1); \ 2835 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2836 delay(1) 2837 2838 /* 2839 * Disable receive filter, and program the node address. 2840 */ 2841 cp = LLADDR(ifp->if_sadl); 2842 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 2843 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 2844 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 2845 2846 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2847 /* 2848 * Program the multicast hash table. 2849 */ 2850 for (i = 0; i < MCHASH_NWORDS; i++) { 2851 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 2852 mchash[i]); 2853 } 2854 } 2855 #undef FILTER_EMIT 2856 #undef MCHASH_NWORDS 2857 2858 /* 2859 * Re-enable the receiver filter. 2860 */ 2861 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2862 } 2863 2864 #if defined(DP83820) 2865 /* 2866 * sip_dp83820_mii_readreg: [mii interface function] 2867 * 2868 * Read a PHY register on the MII of the DP83820. 2869 */ 2870 int 2871 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 2872 { 2873 struct sip_softc *sc = (void *) self; 2874 2875 if (sc->sc_cfg & CFG_TBI_EN) { 2876 bus_addr_t tbireg; 2877 int rv; 2878 2879 if (phy != 0) 2880 return (0); 2881 2882 switch (reg) { 2883 case MII_BMCR: tbireg = SIP_TBICR; break; 2884 case MII_BMSR: tbireg = SIP_TBISR; break; 2885 case MII_ANAR: tbireg = SIP_TANAR; break; 2886 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 2887 case MII_ANER: tbireg = SIP_TANER; break; 2888 case MII_EXTSR: 2889 /* 2890 * Don't even bother reading the TESR register. 2891 * The manual documents that the device has 2892 * 1000baseX full/half capability, but the 2893 * register itself seems read back 0 on some 2894 * boards. Just hard-code the result. 2895 */ 2896 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 2897 2898 default: 2899 return (0); 2900 } 2901 2902 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 2903 if (tbireg == SIP_TBISR) { 2904 /* LINK and ACOMP are switched! */ 2905 int val = rv; 2906 2907 rv = 0; 2908 if (val & TBISR_MR_LINK_STATUS) 2909 rv |= BMSR_LINK; 2910 if (val & TBISR_MR_AN_COMPLETE) 2911 rv |= BMSR_ACOMP; 2912 2913 /* 2914 * The manual claims this register reads back 0 2915 * on hard and soft reset. But we want to let 2916 * the gentbi driver know that we support auto- 2917 * negotiation, so hard-code this bit in the 2918 * result. 2919 */ 2920 rv |= BMSR_ANEG | BMSR_EXTSTAT; 2921 } 2922 2923 return (rv); 2924 } 2925 2926 return (mii_bitbang_readreg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2927 phy, reg)); 2928 } 2929 2930 /* 2931 * sip_dp83820_mii_writereg: [mii interface function] 2932 * 2933 * Write a PHY register on the MII of the DP83820. 2934 */ 2935 void 2936 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 2937 { 2938 struct sip_softc *sc = (void *) self; 2939 2940 if (sc->sc_cfg & CFG_TBI_EN) { 2941 bus_addr_t tbireg; 2942 2943 if (phy != 0) 2944 return; 2945 2946 switch (reg) { 2947 case MII_BMCR: tbireg = SIP_TBICR; break; 2948 case MII_ANAR: tbireg = SIP_TANAR; break; 2949 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 2950 default: 2951 return; 2952 } 2953 2954 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 2955 return; 2956 } 2957 2958 mii_bitbang_writereg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2959 phy, reg, val); 2960 } 2961 2962 /* 2963 * sip_dp83815_mii_statchg: [mii interface function] 2964 * 2965 * Callback from MII layer when media changes. 2966 */ 2967 void 2968 SIP_DECL(dp83820_mii_statchg)(struct device *self) 2969 { 2970 struct sip_softc *sc = (struct sip_softc *) self; 2971 u_int32_t cfg; 2972 2973 /* 2974 * Update TXCFG for full-duplex operation. 2975 */ 2976 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2977 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2978 else 2979 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2980 2981 /* 2982 * Update RXCFG for full-duplex or loopback. 2983 */ 2984 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2985 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2986 sc->sc_rxcfg |= RXCFG_ATX; 2987 else 2988 sc->sc_rxcfg &= ~RXCFG_ATX; 2989 2990 /* 2991 * Update CFG for MII/GMII. 2992 */ 2993 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2994 cfg = sc->sc_cfg | CFG_MODE_1000; 2995 else 2996 cfg = sc->sc_cfg; 2997 2998 /* 2999 * XXX 802.3x flow control. 3000 */ 3001 3002 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3003 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3004 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3005 } 3006 3007 /* 3008 * sip_dp83820_mii_bitbang_read: [mii bit-bang interface function] 3009 * 3010 * Read the MII serial port for the MII bit-bang module. 3011 */ 3012 u_int32_t 3013 SIP_DECL(dp83820_mii_bitbang_read)(struct device *self) 3014 { 3015 struct sip_softc *sc = (void *) self; 3016 3017 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3018 } 3019 3020 /* 3021 * sip_dp83820_mii_bitbang_write: [mii big-bang interface function] 3022 * 3023 * Write the MII serial port for the MII bit-bang module. 3024 */ 3025 void 3026 SIP_DECL(dp83820_mii_bitbang_write)(struct device *self, u_int32_t val) 3027 { 3028 struct sip_softc *sc = (void *) self; 3029 3030 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3031 } 3032 #else /* ! DP83820 */ 3033 /* 3034 * sip_sis900_mii_readreg: [mii interface function] 3035 * 3036 * Read a PHY register on the MII. 3037 */ 3038 int 3039 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 3040 { 3041 struct sip_softc *sc = (struct sip_softc *) self; 3042 u_int32_t enphy; 3043 3044 /* 3045 * The SiS 900 has only an internal PHY on the MII. Only allow 3046 * MII address 0. 3047 */ 3048 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 3049 sc->sc_rev < SIS_REV_635 && phy != 0) 3050 return (0); 3051 3052 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3053 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3054 ENPHY_RWCMD | ENPHY_ACCESS); 3055 do { 3056 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3057 } while (enphy & ENPHY_ACCESS); 3058 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3059 } 3060 3061 /* 3062 * sip_sis900_mii_writereg: [mii interface function] 3063 * 3064 * Write a PHY register on the MII. 3065 */ 3066 void 3067 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 3068 { 3069 struct sip_softc *sc = (struct sip_softc *) self; 3070 u_int32_t enphy; 3071 3072 /* 3073 * The SiS 900 has only an internal PHY on the MII. Only allow 3074 * MII address 0. 3075 */ 3076 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 3077 sc->sc_rev < SIS_REV_635 && phy != 0) 3078 return; 3079 3080 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3081 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3082 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3083 do { 3084 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3085 } while (enphy & ENPHY_ACCESS); 3086 } 3087 3088 /* 3089 * sip_sis900_mii_statchg: [mii interface function] 3090 * 3091 * Callback from MII layer when media changes. 3092 */ 3093 void 3094 SIP_DECL(sis900_mii_statchg)(struct device *self) 3095 { 3096 struct sip_softc *sc = (struct sip_softc *) self; 3097 u_int32_t flowctl; 3098 3099 /* 3100 * Update TXCFG for full-duplex operation. 3101 */ 3102 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3103 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3104 else 3105 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3106 3107 /* 3108 * Update RXCFG for full-duplex or loopback. 3109 */ 3110 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3111 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3112 sc->sc_rxcfg |= RXCFG_ATX; 3113 else 3114 sc->sc_rxcfg &= ~RXCFG_ATX; 3115 3116 /* 3117 * Update IMR for use of 802.3x flow control. 3118 */ 3119 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 3120 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3121 flowctl = FLOWCTL_FLOWEN; 3122 } else { 3123 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3124 flowctl = 0; 3125 } 3126 3127 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3128 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3129 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3130 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3131 } 3132 3133 /* 3134 * sip_dp83815_mii_readreg: [mii interface function] 3135 * 3136 * Read a PHY register on the MII. 3137 */ 3138 int 3139 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 3140 { 3141 struct sip_softc *sc = (struct sip_softc *) self; 3142 u_int32_t val; 3143 3144 /* 3145 * The DP83815 only has an internal PHY. Only allow 3146 * MII address 0. 3147 */ 3148 if (phy != 0) 3149 return (0); 3150 3151 /* 3152 * Apparently, after a reset, the DP83815 can take a while 3153 * to respond. During this recovery period, the BMSR returns 3154 * a value of 0. Catch this -- it's not supposed to happen 3155 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3156 * PHY to come back to life. 3157 * 3158 * This works out because the BMSR is the first register 3159 * read during the PHY probe process. 3160 */ 3161 do { 3162 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3163 } while (reg == MII_BMSR && val == 0); 3164 3165 return (val & 0xffff); 3166 } 3167 3168 /* 3169 * sip_dp83815_mii_writereg: [mii interface function] 3170 * 3171 * Write a PHY register to the MII. 3172 */ 3173 void 3174 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3175 { 3176 struct sip_softc *sc = (struct sip_softc *) self; 3177 3178 /* 3179 * The DP83815 only has an internal PHY. Only allow 3180 * MII address 0. 3181 */ 3182 if (phy != 0) 3183 return; 3184 3185 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3186 } 3187 3188 /* 3189 * sip_dp83815_mii_statchg: [mii interface function] 3190 * 3191 * Callback from MII layer when media changes. 3192 */ 3193 void 3194 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3195 { 3196 struct sip_softc *sc = (struct sip_softc *) self; 3197 3198 /* 3199 * Update TXCFG for full-duplex operation. 3200 */ 3201 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3202 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3203 else 3204 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3205 3206 /* 3207 * Update RXCFG for full-duplex or loopback. 3208 */ 3209 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3210 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3211 sc->sc_rxcfg |= RXCFG_ATX; 3212 else 3213 sc->sc_rxcfg &= ~RXCFG_ATX; 3214 3215 /* 3216 * XXX 802.3x flow control. 3217 */ 3218 3219 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3220 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3221 } 3222 #endif /* DP83820 */ 3223 3224 #if defined(DP83820) 3225 void 3226 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3227 const struct pci_attach_args *pa, u_int8_t *enaddr) 3228 { 3229 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3230 u_int8_t cksum, *e, match; 3231 int i; 3232 3233 /* 3234 * EEPROM data format for the DP83820 can be found in 3235 * the DP83820 manual, section 4.2.4. 3236 */ 3237 3238 SIP_DECL(read_eeprom)(sc, 0, 3239 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3240 3241 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3242 match = ~(match - 1); 3243 3244 cksum = 0x55; 3245 e = (u_int8_t *) eeprom_data; 3246 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3247 cksum += *e++; 3248 3249 if (cksum != match) 3250 printf("%s: Checksum (%x) mismatch (%x)", 3251 sc->sc_dev.dv_xname, cksum, match); 3252 3253 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3254 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3255 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3256 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3257 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3258 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3259 } 3260 #else /* ! DP83820 */ 3261 void 3262 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3263 const struct pci_attach_args *pa, u_int8_t *enaddr) 3264 { 3265 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3266 3267 switch (sc->sc_rev) { 3268 case SIS_REV_630S: 3269 case SIS_REV_630E: 3270 case SIS_REV_630EA1: 3271 case SIS_REV_630ET: 3272 case SIS_REV_635: 3273 /* 3274 * The MAC address for the on-board Ethernet of 3275 * the SiS 630 chipset is in the NVRAM. Kick 3276 * the chip into re-loading it from NVRAM, and 3277 * read the MAC address out of the filter registers. 3278 */ 3279 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3280 3281 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3282 RFCR_RFADDR_NODE0); 3283 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3284 0xffff; 3285 3286 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3287 RFCR_RFADDR_NODE2); 3288 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3289 0xffff; 3290 3291 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3292 RFCR_RFADDR_NODE4); 3293 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3294 0xffff; 3295 break; 3296 3297 default: 3298 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3299 sizeof(myea) / sizeof(myea[0]), myea); 3300 } 3301 3302 enaddr[0] = myea[0] & 0xff; 3303 enaddr[1] = myea[0] >> 8; 3304 enaddr[2] = myea[1] & 0xff; 3305 enaddr[3] = myea[1] >> 8; 3306 enaddr[4] = myea[2] & 0xff; 3307 enaddr[5] = myea[2] >> 8; 3308 } 3309 3310 /* Table and macro to bit-reverse an octet. */ 3311 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3312 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3313 3314 void 3315 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3316 const struct pci_attach_args *pa, u_int8_t *enaddr) 3317 { 3318 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3319 u_int8_t cksum, *e, match; 3320 int i; 3321 3322 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3323 sizeof(eeprom_data[0]), eeprom_data); 3324 3325 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3326 match = ~(match - 1); 3327 3328 cksum = 0x55; 3329 e = (u_int8_t *) eeprom_data; 3330 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3331 cksum += *e++; 3332 } 3333 if (cksum != match) { 3334 printf("%s: Checksum (%x) mismatch (%x)", 3335 sc->sc_dev.dv_xname, cksum, match); 3336 } 3337 3338 /* 3339 * Unrolled because it makes slightly more sense this way. 3340 * The DP83815 stores the MAC address in bit 0 of word 6 3341 * through bit 15 of word 8. 3342 */ 3343 ea = &eeprom_data[6]; 3344 enaddr[0] = ((*ea & 0x1) << 7); 3345 ea++; 3346 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3347 enaddr[1] = ((*ea & 0x1FE) >> 1); 3348 enaddr[2] = ((*ea & 0x1) << 7); 3349 ea++; 3350 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3351 enaddr[3] = ((*ea & 0x1FE) >> 1); 3352 enaddr[4] = ((*ea & 0x1) << 7); 3353 ea++; 3354 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3355 enaddr[5] = ((*ea & 0x1FE) >> 1); 3356 3357 /* 3358 * In case that's not weird enough, we also need to reverse 3359 * the bits in each byte. This all actually makes more sense 3360 * if you think about the EEPROM storage as an array of bits 3361 * being shifted into bytes, but that's not how we're looking 3362 * at it here... 3363 */ 3364 for (i = 0; i < 6 ;i++) 3365 enaddr[i] = bbr(enaddr[i]); 3366 } 3367 #endif /* DP83820 */ 3368 3369 /* 3370 * sip_mediastatus: [ifmedia interface function] 3371 * 3372 * Get the current interface media status. 3373 */ 3374 void 3375 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3376 { 3377 struct sip_softc *sc = ifp->if_softc; 3378 3379 mii_pollstat(&sc->sc_mii); 3380 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3381 ifmr->ifm_active = sc->sc_mii.mii_media_active; 3382 } 3383 3384 /* 3385 * sip_mediachange: [ifmedia interface function] 3386 * 3387 * Set hardware to newly-selected media. 3388 */ 3389 int 3390 SIP_DECL(mediachange)(struct ifnet *ifp) 3391 { 3392 struct sip_softc *sc = ifp->if_softc; 3393 3394 if (ifp->if_flags & IFF_UP) 3395 mii_mediachg(&sc->sc_mii); 3396 return (0); 3397 } 3398
Indexes created Tue Sep 30 11:09:46 GMT 2025