if_sip.c revision 1.24.2.6
1 /* $NetBSD: if_sip.c,v 1.24.2.6 2002/02/28 04:14:01 nathanw Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Support the 10-bit interface on the DP83820 (for fiber). 80 * 81 * - Reduce the interrupt load. 82 */ 83 84 #include <sys/cdefs.h> 85 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.24.2.6 2002/02/28 04:14:01 nathanw Exp $"); 86 87 #include "bpfilter.h" 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/callout.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/ioctl.h> 97 #include <sys/errno.h> 98 #include <sys/device.h> 99 #include <sys/queue.h> 100 101 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 102 103 #include <net/if.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 #include <net/if_ether.h> 107 108 #if NBPFILTER > 0 109 #include <net/bpf.h> 110 #endif 111 112 #include <machine/bus.h> 113 #include <machine/intr.h> 114 #include <machine/endian.h> 115 116 #include <dev/mii/mii.h> 117 #include <dev/mii/miivar.h> 118 #ifdef DP83820 119 #include <dev/mii/mii_bitbang.h> 120 #endif /* DP83820 */ 121 122 #include <dev/pci/pcireg.h> 123 #include <dev/pci/pcivar.h> 124 #include <dev/pci/pcidevs.h> 125 126 #include <dev/pci/if_sipreg.h> 127 128 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 129 #define SIP_DECL(x) __CONCAT(gsip_,x) 130 #else /* SiS900 and DP83815 */ 131 #define SIP_DECL(x) __CONCAT(sip_,x) 132 #endif 133 134 #define SIP_STR(x) __STRING(SIP_DECL(x)) 135 136 /* 137 * Transmit descriptor list size. This is arbitrary, but allocate 138 * enough descriptors for 128 pending transmissions, and 8 segments 139 * per packet. This MUST work out to a power of 2. 140 */ 141 #define SIP_NTXSEGS 8 142 143 #define SIP_TXQUEUELEN 256 144 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS) 145 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 146 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 147 148 /* 149 * Receive descriptor list size. We have one Rx buffer per incoming 150 * packet, so this logic is a little simpler. 151 * 152 * Actually, on the DP83820, we allow the packet to consume more than 153 * one buffer, in order to support jumbo Ethernet frames. In that 154 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 155 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 156 * so we'd better be quick about handling receive interrupts. 157 */ 158 #if defined(DP83820) 159 #define SIP_NRXDESC 256 160 #else 161 #define SIP_NRXDESC 128 162 #endif /* DP83820 */ 163 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 164 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 165 166 /* 167 * Control structures are DMA'd to the SiS900 chip. We allocate them in 168 * a single clump that maps to a single DMA segment to make several things 169 * easier. 170 */ 171 struct sip_control_data { 172 /* 173 * The transmit descriptors. 174 */ 175 struct sip_desc scd_txdescs[SIP_NTXDESC]; 176 177 /* 178 * The receive descriptors. 179 */ 180 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 181 }; 182 183 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 184 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 185 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 186 187 /* 188 * Software state for transmit jobs. 189 */ 190 struct sip_txsoft { 191 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 192 bus_dmamap_t txs_dmamap; /* our DMA map */ 193 int txs_firstdesc; /* first descriptor in packet */ 194 int txs_lastdesc; /* last descriptor in packet */ 195 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 196 }; 197 198 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 199 200 /* 201 * Software state for receive jobs. 202 */ 203 struct sip_rxsoft { 204 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 205 bus_dmamap_t rxs_dmamap; /* our DMA map */ 206 }; 207 208 /* 209 * Software state per device. 210 */ 211 struct sip_softc { 212 struct device sc_dev; /* generic device information */ 213 bus_space_tag_t sc_st; /* bus space tag */ 214 bus_space_handle_t sc_sh; /* bus space handle */ 215 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 216 struct ethercom sc_ethercom; /* ethernet common data */ 217 void *sc_sdhook; /* shutdown hook */ 218 219 const struct sip_product *sc_model; /* which model are we? */ 220 int sc_rev; /* chip revision */ 221 222 void *sc_ih; /* interrupt cookie */ 223 224 struct mii_data sc_mii; /* MII/media information */ 225 226 struct callout sc_tick_ch; /* tick callout */ 227 228 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 229 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 230 231 /* 232 * Software state for transmit and receive descriptors. 233 */ 234 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 235 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 236 237 /* 238 * Control data structures. 239 */ 240 struct sip_control_data *sc_control_data; 241 #define sc_txdescs sc_control_data->scd_txdescs 242 #define sc_rxdescs sc_control_data->scd_rxdescs 243 244 #ifdef SIP_EVENT_COUNTERS 245 /* 246 * Event counters. 247 */ 248 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 249 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 250 struct evcnt sc_ev_txintr; /* Tx interrupts */ 251 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 252 #ifdef DP83820 253 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 254 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 255 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 256 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 257 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 258 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 259 #endif /* DP83820 */ 260 #endif /* SIP_EVENT_COUNTERS */ 261 262 u_int32_t sc_txcfg; /* prototype TXCFG register */ 263 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 264 u_int32_t sc_imr; /* prototype IMR register */ 265 u_int32_t sc_rfcr; /* prototype RFCR register */ 266 267 u_int32_t sc_cfg; /* prototype CFG register */ 268 269 #ifdef DP83820 270 u_int32_t sc_gpior; /* prototype GPIOR register */ 271 #endif /* DP83820 */ 272 273 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 274 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 275 276 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 277 278 int sc_flags; /* misc. flags; see below */ 279 280 int sc_txfree; /* number of free Tx descriptors */ 281 int sc_txnext; /* next ready Tx descriptor */ 282 283 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 284 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 285 286 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 287 #if defined(DP83820) 288 int sc_rxdiscard; 289 int sc_rxlen; 290 struct mbuf *sc_rxhead; 291 struct mbuf *sc_rxtail; 292 struct mbuf **sc_rxtailp; 293 #endif /* DP83820 */ 294 }; 295 296 /* sc_flags */ 297 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 298 299 #ifdef DP83820 300 #define SIP_RXCHAIN_RESET(sc) \ 301 do { \ 302 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 303 *(sc)->sc_rxtailp = NULL; \ 304 (sc)->sc_rxlen = 0; \ 305 } while (/*CONSTCOND*/0) 306 307 #define SIP_RXCHAIN_LINK(sc, m) \ 308 do { \ 309 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 310 (sc)->sc_rxtailp = &(m)->m_next; \ 311 } while (/*CONSTCOND*/0) 312 #endif /* DP83820 */ 313 314 #ifdef SIP_EVENT_COUNTERS 315 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 316 #else 317 #define SIP_EVCNT_INCR(ev) /* nothing */ 318 #endif 319 320 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 321 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 322 323 #define SIP_CDTXSYNC(sc, x, n, ops) \ 324 do { \ 325 int __x, __n; \ 326 \ 327 __x = (x); \ 328 __n = (n); \ 329 \ 330 /* If it will wrap around, sync to the end of the ring. */ \ 331 if ((__x + __n) > SIP_NTXDESC) { \ 332 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 333 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 334 (SIP_NTXDESC - __x), (ops)); \ 335 __n -= (SIP_NTXDESC - __x); \ 336 __x = 0; \ 337 } \ 338 \ 339 /* Now sync whatever is left. */ \ 340 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 341 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 342 } while (0) 343 344 #define SIP_CDRXSYNC(sc, x, ops) \ 345 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 346 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 347 348 #ifdef DP83820 349 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 350 #define SIP_RXBUF_LEN (MCLBYTES - 4) 351 #else 352 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 353 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 354 #endif 355 #define SIP_INIT_RXDESC(sc, x) \ 356 do { \ 357 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 358 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 359 \ 360 __sipd->sipd_link = \ 361 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 362 __sipd->sipd_bufptr = \ 363 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 364 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 365 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 366 SIP_INIT_RXDESC_EXTSTS \ 367 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 368 } while (0) 369 370 #define SIP_CHIP_VERS(sc, v, p, r) \ 371 ((sc)->sc_model->sip_vendor == (v) && \ 372 (sc)->sc_model->sip_product == (p) && \ 373 (sc)->sc_rev == (r)) 374 375 #define SIP_CHIP_MODEL(sc, v, p) \ 376 ((sc)->sc_model->sip_vendor == (v) && \ 377 (sc)->sc_model->sip_product == (p)) 378 379 #if !defined(DP83820) 380 #define SIP_SIS900_REV(sc, rev) \ 381 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 382 #endif 383 384 #define SIP_TIMEOUT 1000 385 386 void SIP_DECL(start)(struct ifnet *); 387 void SIP_DECL(watchdog)(struct ifnet *); 388 int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 389 int SIP_DECL(init)(struct ifnet *); 390 void SIP_DECL(stop)(struct ifnet *, int); 391 392 void SIP_DECL(shutdown)(void *); 393 394 void SIP_DECL(reset)(struct sip_softc *); 395 void SIP_DECL(rxdrain)(struct sip_softc *); 396 int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 397 void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, u_int16_t *); 398 void SIP_DECL(tick)(void *); 399 400 #if !defined(DP83820) 401 void SIP_DECL(sis900_set_filter)(struct sip_softc *); 402 #endif /* ! DP83820 */ 403 void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 404 405 #if defined(DP83820) 406 void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 407 const struct pci_attach_args *, u_int8_t *); 408 #else 409 void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 410 const struct pci_attach_args *, u_int8_t *); 411 void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 412 const struct pci_attach_args *, u_int8_t *); 413 #endif /* DP83820 */ 414 415 int SIP_DECL(intr)(void *); 416 void SIP_DECL(txintr)(struct sip_softc *); 417 void SIP_DECL(rxintr)(struct sip_softc *); 418 419 #if defined(DP83820) 420 int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 421 void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 422 void SIP_DECL(dp83820_mii_statchg)(struct device *); 423 #else 424 int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 425 void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 426 void SIP_DECL(sis900_mii_statchg)(struct device *); 427 428 int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 429 void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 430 void SIP_DECL(dp83815_mii_statchg)(struct device *); 431 #endif /* DP83820 */ 432 433 int SIP_DECL(mediachange)(struct ifnet *); 434 void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 435 436 int SIP_DECL(match)(struct device *, struct cfdata *, void *); 437 void SIP_DECL(attach)(struct device *, struct device *, void *); 438 439 int SIP_DECL(copy_small) = 0; 440 441 struct cfattach SIP_DECL(ca) = { 442 sizeof(struct sip_softc), SIP_DECL(match), SIP_DECL(attach), 443 }; 444 445 /* 446 * Descriptions of the variants of the SiS900. 447 */ 448 struct sip_variant { 449 int (*sipv_mii_readreg)(struct device *, int, int); 450 void (*sipv_mii_writereg)(struct device *, int, int, int); 451 void (*sipv_mii_statchg)(struct device *); 452 void (*sipv_set_filter)(struct sip_softc *); 453 void (*sipv_read_macaddr)(struct sip_softc *, 454 const struct pci_attach_args *, u_int8_t *); 455 }; 456 457 #if defined(DP83820) 458 u_int32_t SIP_DECL(dp83820_mii_bitbang_read)(struct device *); 459 void SIP_DECL(dp83820_mii_bitbang_write)(struct device *, u_int32_t); 460 461 const struct mii_bitbang_ops SIP_DECL(dp83820_mii_bitbang_ops) = { 462 SIP_DECL(dp83820_mii_bitbang_read), 463 SIP_DECL(dp83820_mii_bitbang_write), 464 { 465 EROMAR_MDIO, /* MII_BIT_MDO */ 466 EROMAR_MDIO, /* MII_BIT_MDI */ 467 EROMAR_MDC, /* MII_BIT_MDC */ 468 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 469 0, /* MII_BIT_DIR_PHY_HOST */ 470 } 471 }; 472 #endif /* DP83820 */ 473 474 #if defined(DP83820) 475 const struct sip_variant SIP_DECL(variant_dp83820) = { 476 SIP_DECL(dp83820_mii_readreg), 477 SIP_DECL(dp83820_mii_writereg), 478 SIP_DECL(dp83820_mii_statchg), 479 SIP_DECL(dp83815_set_filter), 480 SIP_DECL(dp83820_read_macaddr), 481 }; 482 #else 483 const struct sip_variant SIP_DECL(variant_sis900) = { 484 SIP_DECL(sis900_mii_readreg), 485 SIP_DECL(sis900_mii_writereg), 486 SIP_DECL(sis900_mii_statchg), 487 SIP_DECL(sis900_set_filter), 488 SIP_DECL(sis900_read_macaddr), 489 }; 490 491 const struct sip_variant SIP_DECL(variant_dp83815) = { 492 SIP_DECL(dp83815_mii_readreg), 493 SIP_DECL(dp83815_mii_writereg), 494 SIP_DECL(dp83815_mii_statchg), 495 SIP_DECL(dp83815_set_filter), 496 SIP_DECL(dp83815_read_macaddr), 497 }; 498 #endif /* DP83820 */ 499 500 /* 501 * Devices supported by this driver. 502 */ 503 const struct sip_product { 504 pci_vendor_id_t sip_vendor; 505 pci_product_id_t sip_product; 506 const char *sip_name; 507 const struct sip_variant *sip_variant; 508 } SIP_DECL(products)[] = { 509 #if defined(DP83820) 510 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 511 "NatSemi DP83820 Gigabit Ethernet", 512 &SIP_DECL(variant_dp83820) }, 513 #else 514 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 515 "SiS 900 10/100 Ethernet", 516 &SIP_DECL(variant_sis900) }, 517 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 518 "SiS 7016 10/100 Ethernet", 519 &SIP_DECL(variant_sis900) }, 520 521 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 522 "NatSemi DP83815 10/100 Ethernet", 523 &SIP_DECL(variant_dp83815) }, 524 #endif /* DP83820 */ 525 526 { 0, 0, 527 NULL, 528 NULL }, 529 }; 530 531 static const struct sip_product * 532 SIP_DECL(lookup)(const struct pci_attach_args *pa) 533 { 534 const struct sip_product *sip; 535 536 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 537 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 538 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 539 return (sip); 540 } 541 return (NULL); 542 } 543 544 int 545 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 546 { 547 struct pci_attach_args *pa = aux; 548 549 if (SIP_DECL(lookup)(pa) != NULL) 550 return (1); 551 552 return (0); 553 } 554 555 void 556 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 557 { 558 struct sip_softc *sc = (struct sip_softc *) self; 559 struct pci_attach_args *pa = aux; 560 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 561 pci_chipset_tag_t pc = pa->pa_pc; 562 pci_intr_handle_t ih; 563 const char *intrstr = NULL; 564 bus_space_tag_t iot, memt; 565 bus_space_handle_t ioh, memh; 566 bus_dma_segment_t seg; 567 int ioh_valid, memh_valid; 568 int i, rseg, error; 569 const struct sip_product *sip; 570 pcireg_t pmode; 571 u_int8_t enaddr[ETHER_ADDR_LEN]; 572 int pmreg; 573 #ifdef DP83820 574 pcireg_t memtype; 575 u_int32_t reg; 576 #endif /* DP83820 */ 577 578 callout_init(&sc->sc_tick_ch); 579 580 sip = SIP_DECL(lookup)(pa); 581 if (sip == NULL) { 582 printf("\n"); 583 panic(SIP_STR(attach) ": impossible"); 584 } 585 sc->sc_rev = PCI_REVISION(pa->pa_class); 586 587 printf(": %s\n", sip->sip_name); 588 589 sc->sc_model = sip; 590 591 /* 592 * Map the device. 593 */ 594 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 595 PCI_MAPREG_TYPE_IO, 0, 596 &iot, &ioh, NULL, NULL) == 0); 597 #ifdef DP83820 598 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 599 switch (memtype) { 600 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 601 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 602 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 603 memtype, 0, &memt, &memh, NULL, NULL) == 0); 604 break; 605 default: 606 memh_valid = 0; 607 } 608 #else 609 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 610 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 611 &memt, &memh, NULL, NULL) == 0); 612 #endif /* DP83820 */ 613 614 if (memh_valid) { 615 sc->sc_st = memt; 616 sc->sc_sh = memh; 617 } else if (ioh_valid) { 618 sc->sc_st = iot; 619 sc->sc_sh = ioh; 620 } else { 621 printf("%s: unable to map device registers\n", 622 sc->sc_dev.dv_xname); 623 return; 624 } 625 626 sc->sc_dmat = pa->pa_dmat; 627 628 /* Enable bus mastering. */ 629 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 630 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 631 PCI_COMMAND_MASTER_ENABLE); 632 633 /* Get it out of power save mode if needed. */ 634 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 635 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 636 if (pmode == 3) { 637 /* 638 * The card has lost all configuration data in 639 * this state, so punt. 640 */ 641 printf("%s: unable to wake up from power state D3\n", 642 sc->sc_dev.dv_xname); 643 return; 644 } 645 if (pmode != 0) { 646 printf("%s: waking up from power state D%d\n", 647 sc->sc_dev.dv_xname, pmode); 648 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 649 } 650 } 651 652 /* 653 * Map and establish our interrupt. 654 */ 655 if (pci_intr_map(pa, &ih)) { 656 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 657 return; 658 } 659 intrstr = pci_intr_string(pc, ih); 660 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 661 if (sc->sc_ih == NULL) { 662 printf("%s: unable to establish interrupt", 663 sc->sc_dev.dv_xname); 664 if (intrstr != NULL) 665 printf(" at %s", intrstr); 666 printf("\n"); 667 return; 668 } 669 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 670 671 SIMPLEQ_INIT(&sc->sc_txfreeq); 672 SIMPLEQ_INIT(&sc->sc_txdirtyq); 673 674 /* 675 * Allocate the control data structures, and create and load the 676 * DMA map for it. 677 */ 678 if ((error = bus_dmamem_alloc(sc->sc_dmat, 679 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 680 0)) != 0) { 681 printf("%s: unable to allocate control data, error = %d\n", 682 sc->sc_dev.dv_xname, error); 683 goto fail_0; 684 } 685 686 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 687 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 688 BUS_DMA_COHERENT)) != 0) { 689 printf("%s: unable to map control data, error = %d\n", 690 sc->sc_dev.dv_xname, error); 691 goto fail_1; 692 } 693 694 if ((error = bus_dmamap_create(sc->sc_dmat, 695 sizeof(struct sip_control_data), 1, 696 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 697 printf("%s: unable to create control data DMA map, " 698 "error = %d\n", sc->sc_dev.dv_xname, error); 699 goto fail_2; 700 } 701 702 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 703 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 704 0)) != 0) { 705 printf("%s: unable to load control data DMA map, error = %d\n", 706 sc->sc_dev.dv_xname, error); 707 goto fail_3; 708 } 709 710 /* 711 * Create the transmit buffer DMA maps. 712 */ 713 for (i = 0; i < SIP_TXQUEUELEN; i++) { 714 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 715 SIP_NTXSEGS, MCLBYTES, 0, 0, 716 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 717 printf("%s: unable to create tx DMA map %d, " 718 "error = %d\n", sc->sc_dev.dv_xname, i, error); 719 goto fail_4; 720 } 721 } 722 723 /* 724 * Create the receive buffer DMA maps. 725 */ 726 for (i = 0; i < SIP_NRXDESC; i++) { 727 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 728 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 729 printf("%s: unable to create rx DMA map %d, " 730 "error = %d\n", sc->sc_dev.dv_xname, i, error); 731 goto fail_5; 732 } 733 sc->sc_rxsoft[i].rxs_mbuf = NULL; 734 } 735 736 /* 737 * Reset the chip to a known state. 738 */ 739 SIP_DECL(reset)(sc); 740 741 /* 742 * Read the Ethernet address from the EEPROM. This might 743 * also fetch other stuff from the EEPROM and stash it 744 * in the softc. 745 */ 746 sc->sc_cfg = 0; 747 #if !defined(DP83820) 748 if (SIP_SIS900_REV(sc,SIS_REV_635) || 749 SIP_SIS900_REV(sc,SIS_REV_900B)) 750 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 751 #endif 752 753 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 754 755 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 756 ether_sprintf(enaddr)); 757 758 /* 759 * Initialize the configuration register: aggressive PCI 760 * bus request algorithm, default backoff, default OW timer, 761 * default parity error detection. 762 * 763 * NOTE: "Big endian mode" is useless on the SiS900 and 764 * friends -- it affects packet data, not descriptors. 765 */ 766 #ifdef DP83820 767 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 768 if (reg & CFG_PCI64_DET) { 769 printf("%s: 64-bit PCI slot detected\n", sc->sc_dev.dv_xname); 770 /* 771 * XXX Need some PCI flags indicating support for 772 * XXX 64-bit addressing (SAC or DAC) and 64-bit 773 * XXX data path. 774 */ 775 } 776 if (sc->sc_cfg & (CFG_TBI_EN|CFG_EXT_125)) { 777 const char *sep = ""; 778 printf("%s: using ", sc->sc_dev.dv_xname); 779 if (sc->sc_cfg & CFG_EXT_125) { 780 printf("%s125MHz clock", sep); 781 sep = ", "; 782 } 783 if (sc->sc_cfg & CFG_TBI_EN) { 784 printf("%sten-bit interface", sep); 785 sep = ", "; 786 } 787 printf("\n"); 788 } 789 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0) 790 sc->sc_cfg |= CFG_MRM_DIS; 791 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 792 sc->sc_cfg |= CFG_MWI_DIS; 793 794 /* 795 * Use the extended descriptor format on the DP83820. This 796 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 797 * checksumming. 798 */ 799 sc->sc_cfg |= CFG_EXTSTS_EN; 800 #endif /* DP83820 */ 801 802 /* 803 * Initialize our media structures and probe the MII. 804 */ 805 sc->sc_mii.mii_ifp = ifp; 806 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 807 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 808 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 809 ifmedia_init(&sc->sc_mii.mii_media, 0, SIP_DECL(mediachange), 810 SIP_DECL(mediastatus)); 811 #ifdef DP83820 812 if (sc->sc_cfg & CFG_TBI_EN) { 813 /* Using ten-bit interface. */ 814 printf("%s: TBI -- FIXME\n", sc->sc_dev.dv_xname); 815 } else { 816 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 817 MII_OFFSET_ANY, 0); 818 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 819 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 820 0, NULL); 821 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 822 } else 823 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 824 } 825 #else 826 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 827 MII_OFFSET_ANY, 0); 828 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 829 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 830 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 831 } else 832 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 833 #endif /* DP83820 */ 834 835 ifp = &sc->sc_ethercom.ec_if; 836 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 837 ifp->if_softc = sc; 838 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 839 ifp->if_ioctl = SIP_DECL(ioctl); 840 ifp->if_start = SIP_DECL(start); 841 ifp->if_watchdog = SIP_DECL(watchdog); 842 ifp->if_init = SIP_DECL(init); 843 ifp->if_stop = SIP_DECL(stop); 844 IFQ_SET_READY(&ifp->if_snd); 845 846 /* 847 * We can support 802.1Q VLAN-sized frames. 848 */ 849 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 850 851 #ifdef DP83820 852 /* 853 * And the DP83820 can do VLAN tagging in hardware, and 854 * support the jumbo Ethernet MTU. 855 */ 856 sc->sc_ethercom.ec_capabilities |= 857 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 858 859 /* 860 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 861 * in hardware. 862 */ 863 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 864 IFCAP_CSUM_UDPv4; 865 #endif /* DP83820 */ 866 867 /* 868 * Attach the interface. 869 */ 870 if_attach(ifp); 871 ether_ifattach(ifp, enaddr); 872 873 #ifdef SIP_EVENT_COUNTERS 874 /* 875 * Attach event counters. 876 */ 877 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 878 NULL, sc->sc_dev.dv_xname, "txsstall"); 879 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 880 NULL, sc->sc_dev.dv_xname, "txdstall"); 881 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 882 NULL, sc->sc_dev.dv_xname, "txintr"); 883 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 884 NULL, sc->sc_dev.dv_xname, "rxintr"); 885 #ifdef DP83820 886 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 887 NULL, sc->sc_dev.dv_xname, "rxipsum"); 888 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 889 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 890 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 891 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 892 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 893 NULL, sc->sc_dev.dv_xname, "txipsum"); 894 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 895 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 896 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 897 NULL, sc->sc_dev.dv_xname, "txudpsum"); 898 #endif /* DP83820 */ 899 #endif /* SIP_EVENT_COUNTERS */ 900 901 /* 902 * Make sure the interface is shutdown during reboot. 903 */ 904 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 905 if (sc->sc_sdhook == NULL) 906 printf("%s: WARNING: unable to establish shutdown hook\n", 907 sc->sc_dev.dv_xname); 908 return; 909 910 /* 911 * Free any resources we've allocated during the failed attach 912 * attempt. Do this in reverse order and fall through. 913 */ 914 fail_5: 915 for (i = 0; i < SIP_NRXDESC; i++) { 916 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 917 bus_dmamap_destroy(sc->sc_dmat, 918 sc->sc_rxsoft[i].rxs_dmamap); 919 } 920 fail_4: 921 for (i = 0; i < SIP_TXQUEUELEN; i++) { 922 if (sc->sc_txsoft[i].txs_dmamap != NULL) 923 bus_dmamap_destroy(sc->sc_dmat, 924 sc->sc_txsoft[i].txs_dmamap); 925 } 926 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 927 fail_3: 928 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 929 fail_2: 930 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 931 sizeof(struct sip_control_data)); 932 fail_1: 933 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 934 fail_0: 935 return; 936 } 937 938 /* 939 * sip_shutdown: 940 * 941 * Make sure the interface is stopped at reboot time. 942 */ 943 void 944 SIP_DECL(shutdown)(void *arg) 945 { 946 struct sip_softc *sc = arg; 947 948 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 949 } 950 951 /* 952 * sip_start: [ifnet interface function] 953 * 954 * Start packet transmission on the interface. 955 */ 956 void 957 SIP_DECL(start)(struct ifnet *ifp) 958 { 959 struct sip_softc *sc = ifp->if_softc; 960 struct mbuf *m0, *m; 961 struct sip_txsoft *txs; 962 bus_dmamap_t dmamap; 963 int error, firsttx, nexttx, lasttx, ofree, seg; 964 #ifdef DP83820 965 u_int32_t extsts; 966 #endif 967 968 /* 969 * If we've been told to pause, don't transmit any more packets. 970 */ 971 if (sc->sc_flags & SIPF_PAUSED) 972 ifp->if_flags |= IFF_OACTIVE; 973 974 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 975 return; 976 977 /* 978 * Remember the previous number of free descriptors and 979 * the first descriptor we'll use. 980 */ 981 ofree = sc->sc_txfree; 982 firsttx = sc->sc_txnext; 983 984 /* 985 * Loop through the send queue, setting up transmit descriptors 986 * until we drain the queue, or use up all available transmit 987 * descriptors. 988 */ 989 for (;;) { 990 /* Get a work queue entry. */ 991 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 992 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 993 break; 994 } 995 996 /* 997 * Grab a packet off the queue. 998 */ 999 IFQ_POLL(&ifp->if_snd, m0); 1000 if (m0 == NULL) 1001 break; 1002 #ifndef DP83820 1003 m = NULL; 1004 #endif 1005 1006 dmamap = txs->txs_dmamap; 1007 1008 #ifdef DP83820 1009 /* 1010 * Load the DMA map. If this fails, the packet either 1011 * didn't fit in the allotted number of segments, or we 1012 * were short on resources. For the too-many-segments 1013 * case, we simply report an error and drop the packet, 1014 * since we can't sanely copy a jumbo packet to a single 1015 * buffer. 1016 */ 1017 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1018 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1019 if (error) { 1020 if (error == EFBIG) { 1021 printf("%s: Tx packet consumes too many " 1022 "DMA segments, dropping...\n", 1023 sc->sc_dev.dv_xname); 1024 IFQ_DEQUEUE(&ifp->if_snd, m0); 1025 m_freem(m0); 1026 continue; 1027 } 1028 /* 1029 * Short on resources, just stop for now. 1030 */ 1031 break; 1032 } 1033 #else /* DP83820 */ 1034 /* 1035 * Load the DMA map. If this fails, the packet either 1036 * didn't fit in the alloted number of segments, or we 1037 * were short on resources. In this case, we'll copy 1038 * and try again. 1039 */ 1040 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1041 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1042 MGETHDR(m, M_DONTWAIT, MT_DATA); 1043 if (m == NULL) { 1044 printf("%s: unable to allocate Tx mbuf\n", 1045 sc->sc_dev.dv_xname); 1046 break; 1047 } 1048 if (m0->m_pkthdr.len > MHLEN) { 1049 MCLGET(m, M_DONTWAIT); 1050 if ((m->m_flags & M_EXT) == 0) { 1051 printf("%s: unable to allocate Tx " 1052 "cluster\n", sc->sc_dev.dv_xname); 1053 m_freem(m); 1054 break; 1055 } 1056 } 1057 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1058 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1059 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1060 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1061 if (error) { 1062 printf("%s: unable to load Tx buffer, " 1063 "error = %d\n", sc->sc_dev.dv_xname, error); 1064 break; 1065 } 1066 } 1067 #endif /* DP83820 */ 1068 1069 /* 1070 * Ensure we have enough descriptors free to describe 1071 * the packet. Note, we always reserve one descriptor 1072 * at the end of the ring as a termination point, to 1073 * prevent wrap-around. 1074 */ 1075 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1076 /* 1077 * Not enough free descriptors to transmit this 1078 * packet. We haven't committed anything yet, 1079 * so just unload the DMA map, put the packet 1080 * back on the queue, and punt. Notify the upper 1081 * layer that there are not more slots left. 1082 * 1083 * XXX We could allocate an mbuf and copy, but 1084 * XXX is it worth it? 1085 */ 1086 ifp->if_flags |= IFF_OACTIVE; 1087 bus_dmamap_unload(sc->sc_dmat, dmamap); 1088 #ifndef DP83820 1089 if (m != NULL) 1090 m_freem(m); 1091 #endif 1092 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1093 break; 1094 } 1095 1096 IFQ_DEQUEUE(&ifp->if_snd, m0); 1097 #ifndef DP83820 1098 if (m != NULL) { 1099 m_freem(m0); 1100 m0 = m; 1101 } 1102 #endif 1103 1104 /* 1105 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1106 */ 1107 1108 /* Sync the DMA map. */ 1109 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1110 BUS_DMASYNC_PREWRITE); 1111 1112 /* 1113 * Initialize the transmit descriptors. 1114 */ 1115 for (nexttx = sc->sc_txnext, seg = 0; 1116 seg < dmamap->dm_nsegs; 1117 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1118 /* 1119 * If this is the first descriptor we're 1120 * enqueueing, don't set the OWN bit just 1121 * yet. That could cause a race condition. 1122 * We'll do it below. 1123 */ 1124 sc->sc_txdescs[nexttx].sipd_bufptr = 1125 htole32(dmamap->dm_segs[seg].ds_addr); 1126 sc->sc_txdescs[nexttx].sipd_cmdsts = 1127 htole32((nexttx == firsttx ? 0 : CMDSTS_OWN) | 1128 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1129 #ifdef DP83820 1130 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1131 #endif /* DP83820 */ 1132 lasttx = nexttx; 1133 } 1134 1135 /* Clear the MORE bit on the last segment. */ 1136 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1137 1138 #ifdef DP83820 1139 /* 1140 * If VLANs are enabled and the packet has a VLAN tag, set 1141 * up the descriptor to encapsulate the packet for us. 1142 * 1143 * This apparently has to be on the last descriptor of 1144 * the packet. 1145 */ 1146 if (sc->sc_ethercom.ec_nvlans != 0 && 1147 (m = m_aux_find(m0, AF_LINK, ETHERTYPE_VLAN)) != NULL) { 1148 sc->sc_txdescs[lasttx].sipd_extsts |= 1149 htole32(EXTSTS_VPKT | 1150 htons(*mtod(m, int *) & EXTSTS_VTCI)); 1151 } 1152 1153 /* 1154 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1155 * checksumming, set up the descriptor to do this work 1156 * for us. 1157 * 1158 * This apparently has to be on the first descriptor of 1159 * the packet. 1160 * 1161 * Byte-swap constants so the compiler can optimize. 1162 */ 1163 extsts = 0; 1164 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1165 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1166 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1167 extsts |= htole32(EXTSTS_IPPKT); 1168 } 1169 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1170 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1171 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1172 extsts |= htole32(EXTSTS_TCPPKT); 1173 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1174 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1175 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1176 extsts |= htole32(EXTSTS_UDPPKT); 1177 } 1178 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1179 #endif /* DP83820 */ 1180 1181 /* Sync the descriptors we're using. */ 1182 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1183 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1184 1185 /* 1186 * Store a pointer to the packet so we can free it later, 1187 * and remember what txdirty will be once the packet is 1188 * done. 1189 */ 1190 txs->txs_mbuf = m0; 1191 txs->txs_firstdesc = sc->sc_txnext; 1192 txs->txs_lastdesc = lasttx; 1193 1194 /* Advance the tx pointer. */ 1195 sc->sc_txfree -= dmamap->dm_nsegs; 1196 sc->sc_txnext = nexttx; 1197 1198 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs, txs_q); 1199 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1200 1201 #if NBPFILTER > 0 1202 /* 1203 * Pass the packet to any BPF listeners. 1204 */ 1205 if (ifp->if_bpf) 1206 bpf_mtap(ifp->if_bpf, m0); 1207 #endif /* NBPFILTER > 0 */ 1208 } 1209 1210 if (txs == NULL || sc->sc_txfree == 0) { 1211 /* No more slots left; notify upper layer. */ 1212 ifp->if_flags |= IFF_OACTIVE; 1213 } 1214 1215 if (sc->sc_txfree != ofree) { 1216 /* 1217 * Cause a descriptor interrupt to happen on the 1218 * last packet we enqueued. 1219 */ 1220 sc->sc_txdescs[lasttx].sipd_cmdsts |= htole32(CMDSTS_INTR); 1221 SIP_CDTXSYNC(sc, lasttx, 1, 1222 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1223 1224 /* 1225 * The entire packet chain is set up. Give the 1226 * first descrptor to the chip now. 1227 */ 1228 sc->sc_txdescs[firsttx].sipd_cmdsts |= htole32(CMDSTS_OWN); 1229 SIP_CDTXSYNC(sc, firsttx, 1, 1230 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1231 1232 /* 1233 * Start the transmit process. Note, the manual says 1234 * that if there are no pending transmissions in the 1235 * chip's internal queue (indicated by TXE being clear), 1236 * then the driver software must set the TXDP to the 1237 * first descriptor to be transmitted. However, if we 1238 * do this, it causes serious performance degredation on 1239 * the DP83820 under load, not setting TXDP doesn't seem 1240 * to adversely affect the SiS 900 or DP83815. 1241 * 1242 * Well, I guess it wouldn't be the first time a manual 1243 * has lied -- and they could be speaking of the NULL- 1244 * terminated descriptor list case, rather than OWN- 1245 * terminated rings. 1246 */ 1247 #if 0 1248 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1249 CR_TXE) == 0) { 1250 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1251 SIP_CDTXADDR(sc, firsttx)); 1252 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1253 } 1254 #else 1255 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1256 #endif 1257 1258 /* Set a watchdog timer in case the chip flakes out. */ 1259 ifp->if_timer = 5; 1260 } 1261 } 1262 1263 /* 1264 * sip_watchdog: [ifnet interface function] 1265 * 1266 * Watchdog timer handler. 1267 */ 1268 void 1269 SIP_DECL(watchdog)(struct ifnet *ifp) 1270 { 1271 struct sip_softc *sc = ifp->if_softc; 1272 1273 /* 1274 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1275 * If we get a timeout, try and sweep up transmit descriptors. 1276 * If we manage to sweep them all up, ignore the lack of 1277 * interrupt. 1278 */ 1279 SIP_DECL(txintr)(sc); 1280 1281 if (sc->sc_txfree != SIP_NTXDESC) { 1282 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1283 ifp->if_oerrors++; 1284 1285 /* Reset the interface. */ 1286 (void) SIP_DECL(init)(ifp); 1287 } else if (ifp->if_flags & IFF_DEBUG) 1288 printf("%s: recovered from device timeout\n", 1289 sc->sc_dev.dv_xname); 1290 1291 /* Try to get more packets going. */ 1292 SIP_DECL(start)(ifp); 1293 } 1294 1295 /* 1296 * sip_ioctl: [ifnet interface function] 1297 * 1298 * Handle control requests from the operator. 1299 */ 1300 int 1301 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1302 { 1303 struct sip_softc *sc = ifp->if_softc; 1304 struct ifreq *ifr = (struct ifreq *)data; 1305 int s, error; 1306 1307 s = splnet(); 1308 1309 switch (cmd) { 1310 case SIOCSIFMEDIA: 1311 case SIOCGIFMEDIA: 1312 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1313 break; 1314 1315 default: 1316 error = ether_ioctl(ifp, cmd, data); 1317 if (error == ENETRESET) { 1318 /* 1319 * Multicast list has changed; set the hardware filter 1320 * accordingly. 1321 */ 1322 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1323 error = 0; 1324 } 1325 break; 1326 } 1327 1328 /* Try to get more packets going. */ 1329 SIP_DECL(start)(ifp); 1330 1331 splx(s); 1332 return (error); 1333 } 1334 1335 /* 1336 * sip_intr: 1337 * 1338 * Interrupt service routine. 1339 */ 1340 int 1341 SIP_DECL(intr)(void *arg) 1342 { 1343 struct sip_softc *sc = arg; 1344 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1345 u_int32_t isr; 1346 int handled = 0; 1347 1348 for (;;) { 1349 /* Reading clears interrupt. */ 1350 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1351 if ((isr & sc->sc_imr) == 0) 1352 break; 1353 1354 handled = 1; 1355 1356 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1357 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1358 1359 /* Grab any new packets. */ 1360 SIP_DECL(rxintr)(sc); 1361 1362 if (isr & ISR_RXORN) { 1363 printf("%s: receive FIFO overrun\n", 1364 sc->sc_dev.dv_xname); 1365 1366 /* XXX adjust rx_drain_thresh? */ 1367 } 1368 1369 if (isr & ISR_RXIDLE) { 1370 printf("%s: receive ring overrun\n", 1371 sc->sc_dev.dv_xname); 1372 1373 /* Get the receive process going again. */ 1374 bus_space_write_4(sc->sc_st, sc->sc_sh, 1375 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1376 bus_space_write_4(sc->sc_st, sc->sc_sh, 1377 SIP_CR, CR_RXE); 1378 } 1379 } 1380 1381 if (isr & (ISR_TXURN|ISR_TXDESC)) { 1382 SIP_EVCNT_INCR(&sc->sc_ev_txintr); 1383 1384 /* Sweep up transmit descriptors. */ 1385 SIP_DECL(txintr)(sc); 1386 1387 if (isr & ISR_TXURN) { 1388 u_int32_t thresh; 1389 1390 printf("%s: transmit FIFO underrun", 1391 sc->sc_dev.dv_xname); 1392 1393 thresh = sc->sc_tx_drain_thresh + 1; 1394 if (thresh <= TXCFG_DRTH && 1395 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1396 (sc->sc_tx_fill_thresh * 32))) { 1397 printf("; increasing Tx drain " 1398 "threshold to %u bytes\n", 1399 thresh * 32); 1400 sc->sc_tx_drain_thresh = thresh; 1401 (void) SIP_DECL(init)(ifp); 1402 } else { 1403 (void) SIP_DECL(init)(ifp); 1404 printf("\n"); 1405 } 1406 } 1407 } 1408 1409 #if !defined(DP83820) 1410 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1411 if (isr & ISR_PAUSE_ST) { 1412 sc->sc_flags |= SIPF_PAUSED; 1413 ifp->if_flags |= IFF_OACTIVE; 1414 } 1415 if (isr & ISR_PAUSE_END) { 1416 sc->sc_flags &= ~SIPF_PAUSED; 1417 ifp->if_flags &= ~IFF_OACTIVE; 1418 } 1419 } 1420 #endif /* ! DP83820 */ 1421 1422 if (isr & ISR_HIBERR) { 1423 #define PRINTERR(bit, str) \ 1424 if (isr & (bit)) \ 1425 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1426 PRINTERR(ISR_DPERR, "parity error"); 1427 PRINTERR(ISR_SSERR, "system error"); 1428 PRINTERR(ISR_RMABT, "master abort"); 1429 PRINTERR(ISR_RTABT, "target abort"); 1430 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1431 (void) SIP_DECL(init)(ifp); 1432 #undef PRINTERR 1433 } 1434 } 1435 1436 /* Try to get more packets going. */ 1437 SIP_DECL(start)(ifp); 1438 1439 return (handled); 1440 } 1441 1442 /* 1443 * sip_txintr: 1444 * 1445 * Helper; handle transmit interrupts. 1446 */ 1447 void 1448 SIP_DECL(txintr)(struct sip_softc *sc) 1449 { 1450 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1451 struct sip_txsoft *txs; 1452 u_int32_t cmdsts; 1453 1454 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1455 ifp->if_flags &= ~IFF_OACTIVE; 1456 1457 /* 1458 * Go through our Tx list and free mbufs for those 1459 * frames which have been transmitted. 1460 */ 1461 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1462 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1463 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1464 1465 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1466 if (cmdsts & CMDSTS_OWN) 1467 break; 1468 1469 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1470 1471 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1472 1473 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1474 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1475 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1476 m_freem(txs->txs_mbuf); 1477 txs->txs_mbuf = NULL; 1478 1479 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1480 1481 /* 1482 * Check for errors and collisions. 1483 */ 1484 if (cmdsts & 1485 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1486 ifp->if_oerrors++; 1487 if (cmdsts & CMDSTS_Tx_EC) 1488 ifp->if_collisions += 16; 1489 if (ifp->if_flags & IFF_DEBUG) { 1490 if (cmdsts & CMDSTS_Tx_ED) 1491 printf("%s: excessive deferral\n", 1492 sc->sc_dev.dv_xname); 1493 if (cmdsts & CMDSTS_Tx_EC) 1494 printf("%s: excessive collisions\n", 1495 sc->sc_dev.dv_xname); 1496 } 1497 } else { 1498 /* Packet was transmitted successfully. */ 1499 ifp->if_opackets++; 1500 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1501 } 1502 } 1503 1504 /* 1505 * If there are no more pending transmissions, cancel the watchdog 1506 * timer. 1507 */ 1508 if (txs == NULL) 1509 ifp->if_timer = 0; 1510 } 1511 1512 #if defined(DP83820) 1513 /* 1514 * sip_rxintr: 1515 * 1516 * Helper; handle receive interrupts. 1517 */ 1518 void 1519 SIP_DECL(rxintr)(struct sip_softc *sc) 1520 { 1521 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1522 struct sip_rxsoft *rxs; 1523 struct mbuf *m, *tailm; 1524 u_int32_t cmdsts, extsts; 1525 int i, len; 1526 1527 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1528 rxs = &sc->sc_rxsoft[i]; 1529 1530 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1531 1532 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1533 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1534 1535 /* 1536 * NOTE: OWN is set if owned by _consumer_. We're the 1537 * consumer of the receive ring, so if the bit is clear, 1538 * we have processed all of the packets. 1539 */ 1540 if ((cmdsts & CMDSTS_OWN) == 0) { 1541 /* 1542 * We have processed all of the receive buffers. 1543 */ 1544 break; 1545 } 1546 1547 if (__predict_false(sc->sc_rxdiscard)) { 1548 SIP_INIT_RXDESC(sc, i); 1549 if ((cmdsts & CMDSTS_MORE) == 0) { 1550 /* Reset our state. */ 1551 sc->sc_rxdiscard = 0; 1552 } 1553 continue; 1554 } 1555 1556 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1557 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1558 1559 m = rxs->rxs_mbuf; 1560 1561 /* 1562 * Add a new receive buffer to the ring. 1563 */ 1564 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1565 /* 1566 * Failed, throw away what we've done so 1567 * far, and discard the rest of the packet. 1568 */ 1569 ifp->if_ierrors++; 1570 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1571 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1572 SIP_INIT_RXDESC(sc, i); 1573 if (cmdsts & CMDSTS_MORE) 1574 sc->sc_rxdiscard = 1; 1575 if (sc->sc_rxhead != NULL) 1576 m_freem(sc->sc_rxhead); 1577 SIP_RXCHAIN_RESET(sc); 1578 continue; 1579 } 1580 1581 SIP_RXCHAIN_LINK(sc, m); 1582 1583 /* 1584 * If this is not the end of the packet, keep 1585 * looking. 1586 */ 1587 if (cmdsts & CMDSTS_MORE) { 1588 sc->sc_rxlen += m->m_len; 1589 continue; 1590 } 1591 1592 /* 1593 * Okay, we have the entire packet now... 1594 */ 1595 *sc->sc_rxtailp = NULL; 1596 m = sc->sc_rxhead; 1597 tailm = sc->sc_rxtail; 1598 1599 SIP_RXCHAIN_RESET(sc); 1600 1601 /* 1602 * If an error occurred, update stats and drop the packet. 1603 */ 1604 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1605 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1606 ifp->if_ierrors++; 1607 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1608 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1609 /* Receive overrun handled elsewhere. */ 1610 printf("%s: receive descriptor error\n", 1611 sc->sc_dev.dv_xname); 1612 } 1613 #define PRINTERR(bit, str) \ 1614 if (cmdsts & (bit)) \ 1615 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1616 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1617 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1618 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1619 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1620 #undef PRINTERR 1621 m_freem(m); 1622 continue; 1623 } 1624 1625 /* 1626 * No errors. 1627 * 1628 * Note, the DP83820 includes the CRC with 1629 * every packet. 1630 */ 1631 len = CMDSTS_SIZE(cmdsts); 1632 tailm->m_len = len - sc->sc_rxlen; 1633 1634 /* 1635 * If the packet is small enough to fit in a 1636 * single header mbuf, allocate one and copy 1637 * the data into it. This greatly reduces 1638 * memory consumption when we receive lots 1639 * of small packets. 1640 */ 1641 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1642 struct mbuf *nm; 1643 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1644 if (nm == NULL) { 1645 ifp->if_ierrors++; 1646 m_freem(m); 1647 continue; 1648 } 1649 nm->m_data += 2; 1650 nm->m_pkthdr.len = nm->m_len = len; 1651 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1652 m_freem(m); 1653 m = nm; 1654 } 1655 #ifndef __NO_STRICT_ALIGNMENT 1656 else { 1657 /* 1658 * The DP83820's receive buffers must be 4-byte 1659 * aligned. But this means that the data after 1660 * the Ethernet header is misaligned. To compensate, 1661 * we have artificially shortened the buffer size 1662 * in the descriptor, and we do an overlapping copy 1663 * of the data two bytes further in (in the first 1664 * buffer of the chain only). 1665 */ 1666 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1667 m->m_len); 1668 m->m_data += 2; 1669 } 1670 #endif /* ! __NO_STRICT_ALIGNMENT */ 1671 1672 /* 1673 * If VLANs are enabled, VLAN packets have been unwrapped 1674 * for us. Associate the tag with the packet. 1675 */ 1676 if (sc->sc_ethercom.ec_nvlans != 0 && 1677 (extsts & EXTSTS_VPKT) != 0) { 1678 struct mbuf *vtag; 1679 1680 vtag = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 1681 if (vtag == NULL) { 1682 ifp->if_ierrors++; 1683 printf("%s: unable to allocate VLAN tag\n", 1684 sc->sc_dev.dv_xname); 1685 m_freem(m); 1686 continue; 1687 } 1688 1689 *mtod(vtag, int *) = ntohs(extsts & EXTSTS_VTCI); 1690 vtag->m_len = sizeof(int); 1691 } 1692 1693 /* 1694 * Set the incoming checksum information for the 1695 * packet. 1696 */ 1697 if ((extsts & EXTSTS_IPPKT) != 0) { 1698 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1699 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1700 if (extsts & EXTSTS_Rx_IPERR) 1701 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1702 if (extsts & EXTSTS_TCPPKT) { 1703 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1704 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1705 if (extsts & EXTSTS_Rx_TCPERR) 1706 m->m_pkthdr.csum_flags |= 1707 M_CSUM_TCP_UDP_BAD; 1708 } else if (extsts & EXTSTS_UDPPKT) { 1709 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1710 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1711 if (extsts & EXTSTS_Rx_UDPERR) 1712 m->m_pkthdr.csum_flags |= 1713 M_CSUM_TCP_UDP_BAD; 1714 } 1715 } 1716 1717 ifp->if_ipackets++; 1718 m->m_flags |= M_HASFCS; 1719 m->m_pkthdr.rcvif = ifp; 1720 m->m_pkthdr.len = len; 1721 1722 #if NBPFILTER > 0 1723 /* 1724 * Pass this up to any BPF listeners, but only 1725 * pass if up the stack if it's for us. 1726 */ 1727 if (ifp->if_bpf) 1728 bpf_mtap(ifp->if_bpf, m); 1729 #endif /* NBPFILTER > 0 */ 1730 1731 /* Pass it on. */ 1732 (*ifp->if_input)(ifp, m); 1733 } 1734 1735 /* Update the receive pointer. */ 1736 sc->sc_rxptr = i; 1737 } 1738 #else /* ! DP83820 */ 1739 /* 1740 * sip_rxintr: 1741 * 1742 * Helper; handle receive interrupts. 1743 */ 1744 void 1745 SIP_DECL(rxintr)(struct sip_softc *sc) 1746 { 1747 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1748 struct sip_rxsoft *rxs; 1749 struct mbuf *m; 1750 u_int32_t cmdsts; 1751 int i, len; 1752 1753 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1754 rxs = &sc->sc_rxsoft[i]; 1755 1756 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1757 1758 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1759 1760 /* 1761 * NOTE: OWN is set if owned by _consumer_. We're the 1762 * consumer of the receive ring, so if the bit is clear, 1763 * we have processed all of the packets. 1764 */ 1765 if ((cmdsts & CMDSTS_OWN) == 0) { 1766 /* 1767 * We have processed all of the receive buffers. 1768 */ 1769 break; 1770 } 1771 1772 /* 1773 * If any collisions were seen on the wire, count one. 1774 */ 1775 if (cmdsts & CMDSTS_Rx_COL) 1776 ifp->if_collisions++; 1777 1778 /* 1779 * If an error occurred, update stats, clear the status 1780 * word, and leave the packet buffer in place. It will 1781 * simply be reused the next time the ring comes around. 1782 */ 1783 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1784 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1785 ifp->if_ierrors++; 1786 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1787 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1788 /* Receive overrun handled elsewhere. */ 1789 printf("%s: receive descriptor error\n", 1790 sc->sc_dev.dv_xname); 1791 } 1792 #define PRINTERR(bit, str) \ 1793 if (cmdsts & (bit)) \ 1794 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1795 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1796 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1797 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1798 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1799 #undef PRINTERR 1800 SIP_INIT_RXDESC(sc, i); 1801 continue; 1802 } 1803 1804 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1805 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1806 1807 /* 1808 * No errors; receive the packet. Note, the SiS 900 1809 * includes the CRC with every packet. 1810 */ 1811 len = CMDSTS_SIZE(cmdsts); 1812 1813 #ifdef __NO_STRICT_ALIGNMENT 1814 /* 1815 * If the packet is small enough to fit in a 1816 * single header mbuf, allocate one and copy 1817 * the data into it. This greatly reduces 1818 * memory consumption when we receive lots 1819 * of small packets. 1820 * 1821 * Otherwise, we add a new buffer to the receive 1822 * chain. If this fails, we drop the packet and 1823 * recycle the old buffer. 1824 */ 1825 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 1826 MGETHDR(m, M_DONTWAIT, MT_DATA); 1827 if (m == NULL) 1828 goto dropit; 1829 memcpy(mtod(m, caddr_t), 1830 mtod(rxs->rxs_mbuf, caddr_t), len); 1831 SIP_INIT_RXDESC(sc, i); 1832 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1833 rxs->rxs_dmamap->dm_mapsize, 1834 BUS_DMASYNC_PREREAD); 1835 } else { 1836 m = rxs->rxs_mbuf; 1837 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1838 dropit: 1839 ifp->if_ierrors++; 1840 SIP_INIT_RXDESC(sc, i); 1841 bus_dmamap_sync(sc->sc_dmat, 1842 rxs->rxs_dmamap, 0, 1843 rxs->rxs_dmamap->dm_mapsize, 1844 BUS_DMASYNC_PREREAD); 1845 continue; 1846 } 1847 } 1848 #else 1849 /* 1850 * The SiS 900's receive buffers must be 4-byte aligned. 1851 * But this means that the data after the Ethernet header 1852 * is misaligned. We must allocate a new buffer and 1853 * copy the data, shifted forward 2 bytes. 1854 */ 1855 MGETHDR(m, M_DONTWAIT, MT_DATA); 1856 if (m == NULL) { 1857 dropit: 1858 ifp->if_ierrors++; 1859 SIP_INIT_RXDESC(sc, i); 1860 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1861 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1862 continue; 1863 } 1864 if (len > (MHLEN - 2)) { 1865 MCLGET(m, M_DONTWAIT); 1866 if ((m->m_flags & M_EXT) == 0) { 1867 m_freem(m); 1868 goto dropit; 1869 } 1870 } 1871 m->m_data += 2; 1872 1873 /* 1874 * Note that we use clusters for incoming frames, so the 1875 * buffer is virtually contiguous. 1876 */ 1877 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 1878 1879 /* Allow the receive descriptor to continue using its mbuf. */ 1880 SIP_INIT_RXDESC(sc, i); 1881 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1882 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1883 #endif /* __NO_STRICT_ALIGNMENT */ 1884 1885 ifp->if_ipackets++; 1886 m->m_flags |= M_HASFCS; 1887 m->m_pkthdr.rcvif = ifp; 1888 m->m_pkthdr.len = m->m_len = len; 1889 1890 #if NBPFILTER > 0 1891 /* 1892 * Pass this up to any BPF listeners, but only 1893 * pass if up the stack if it's for us. 1894 */ 1895 if (ifp->if_bpf) 1896 bpf_mtap(ifp->if_bpf, m); 1897 #endif /* NBPFILTER > 0 */ 1898 1899 /* Pass it on. */ 1900 (*ifp->if_input)(ifp, m); 1901 } 1902 1903 /* Update the receive pointer. */ 1904 sc->sc_rxptr = i; 1905 } 1906 #endif /* DP83820 */ 1907 1908 /* 1909 * sip_tick: 1910 * 1911 * One second timer, used to tick the MII. 1912 */ 1913 void 1914 SIP_DECL(tick)(void *arg) 1915 { 1916 struct sip_softc *sc = arg; 1917 int s; 1918 1919 s = splnet(); 1920 mii_tick(&sc->sc_mii); 1921 splx(s); 1922 1923 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 1924 } 1925 1926 /* 1927 * sip_reset: 1928 * 1929 * Perform a soft reset on the SiS 900. 1930 */ 1931 void 1932 SIP_DECL(reset)(struct sip_softc *sc) 1933 { 1934 bus_space_tag_t st = sc->sc_st; 1935 bus_space_handle_t sh = sc->sc_sh; 1936 int i; 1937 1938 bus_space_write_4(st, sh, SIP_IER, 0); 1939 bus_space_write_4(st, sh, SIP_IMR, 0); 1940 bus_space_write_4(st, sh, SIP_RFCR, 0); 1941 bus_space_write_4(st, sh, SIP_CR, CR_RST); 1942 1943 for (i = 0; i < SIP_TIMEOUT; i++) { 1944 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 1945 break; 1946 delay(2); 1947 } 1948 1949 if (i == SIP_TIMEOUT) 1950 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1951 1952 delay(1000); 1953 1954 #ifdef DP83820 1955 /* 1956 * Set the general purpose I/O bits. Do it here in case we 1957 * need to have GPIO set up to talk to the media interface. 1958 */ 1959 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 1960 delay(1000); 1961 #endif /* DP83820 */ 1962 } 1963 1964 /* 1965 * sip_init: [ ifnet interface function ] 1966 * 1967 * Initialize the interface. Must be called at splnet(). 1968 */ 1969 int 1970 SIP_DECL(init)(struct ifnet *ifp) 1971 { 1972 struct sip_softc *sc = ifp->if_softc; 1973 bus_space_tag_t st = sc->sc_st; 1974 bus_space_handle_t sh = sc->sc_sh; 1975 struct sip_txsoft *txs; 1976 struct sip_rxsoft *rxs; 1977 struct sip_desc *sipd; 1978 u_int32_t reg; 1979 int i, error = 0; 1980 1981 /* 1982 * Cancel any pending I/O. 1983 */ 1984 SIP_DECL(stop)(ifp, 0); 1985 1986 /* 1987 * Reset the chip to a known state. 1988 */ 1989 SIP_DECL(reset)(sc); 1990 1991 #if !defined(DP83820) 1992 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 1993 /* 1994 * DP83815 manual, page 78: 1995 * 4.4 Recommended Registers Configuration 1996 * For optimum performance of the DP83815, version noted 1997 * as DP83815CVNG (SRR = 203h), the listed register 1998 * modifications must be followed in sequence... 1999 * 2000 * It's not clear if this should be 302h or 203h because that 2001 * chip name is listed as SRR 302h in the description of the 2002 * SRR register. However, my revision 302h DP83815 on the 2003 * Netgear FA311 purchased in 02/2001 needs these settings 2004 * to avoid tons of errors in AcceptPerfectMatch (non- 2005 * IFF_PROMISC) mode. I do not know if other revisions need 2006 * this set or not. [briggs -- 09 March 2001] 2007 * 2008 * Note that only the low-order 12 bits of 0xe4 are documented 2009 * and that this sets reserved bits in that register. 2010 */ 2011 reg = bus_space_read_4(st, sh, SIP_NS_SRR); 2012 if (reg == 0x302) { 2013 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2014 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2015 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2016 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2017 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2018 } 2019 } 2020 #endif /* ! DP83820 */ 2021 2022 /* 2023 * Initialize the transmit descriptor ring. 2024 */ 2025 for (i = 0; i < SIP_NTXDESC; i++) { 2026 sipd = &sc->sc_txdescs[i]; 2027 memset(sipd, 0, sizeof(struct sip_desc)); 2028 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2029 } 2030 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2031 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2032 sc->sc_txfree = SIP_NTXDESC; 2033 sc->sc_txnext = 0; 2034 2035 /* 2036 * Initialize the transmit job descriptors. 2037 */ 2038 SIMPLEQ_INIT(&sc->sc_txfreeq); 2039 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2040 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2041 txs = &sc->sc_txsoft[i]; 2042 txs->txs_mbuf = NULL; 2043 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2044 } 2045 2046 /* 2047 * Initialize the receive descriptor and receive job 2048 * descriptor rings. 2049 */ 2050 for (i = 0; i < SIP_NRXDESC; i++) { 2051 rxs = &sc->sc_rxsoft[i]; 2052 if (rxs->rxs_mbuf == NULL) { 2053 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2054 printf("%s: unable to allocate or map rx " 2055 "buffer %d, error = %d\n", 2056 sc->sc_dev.dv_xname, i, error); 2057 /* 2058 * XXX Should attempt to run with fewer receive 2059 * XXX buffers instead of just failing. 2060 */ 2061 SIP_DECL(rxdrain)(sc); 2062 goto out; 2063 } 2064 } else 2065 SIP_INIT_RXDESC(sc, i); 2066 } 2067 sc->sc_rxptr = 0; 2068 #ifdef DP83820 2069 sc->sc_rxdiscard = 0; 2070 SIP_RXCHAIN_RESET(sc); 2071 #endif /* DP83820 */ 2072 2073 /* 2074 * Set the configuration register; it's already initialized 2075 * in sip_attach(). 2076 */ 2077 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2078 2079 /* 2080 * Initialize the transmit fill and drain thresholds if 2081 * we have never done so. 2082 */ 2083 if (sc->sc_tx_fill_thresh == 0) { 2084 /* 2085 * XXX This value should be tuned. We may be able to 2086 * improve performance by increasing it. 2087 */ 2088 sc->sc_tx_fill_thresh = 64/32; 2089 } 2090 if (sc->sc_tx_drain_thresh == 0) { 2091 /* 2092 * Start at a drain threshold of 512 bytes. We will 2093 * increase it if a DMA underrun occurs. 2094 * 2095 * XXX The minimum value of this variable should be 2096 * tuned. We may be able to improve performance 2097 * by starting with a lower value. That, however, 2098 * may trash the first few outgoing packets if the 2099 * PCI bus is saturated. 2100 */ 2101 sc->sc_tx_drain_thresh = 512 / 32; 2102 } 2103 2104 /* 2105 * Initialize the prototype TXCFG register. 2106 */ 2107 #if defined(DP83820) 2108 sc->sc_txcfg = TXCFG_MXDMA_512; 2109 sc->sc_rxcfg = RXCFG_MXDMA_512; 2110 #else 2111 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2112 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2113 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & CFG_EDBMASTEN)) { 2114 sc->sc_txcfg = TXCFG_MXDMA_64; 2115 sc->sc_rxcfg = RXCFG_MXDMA_64; 2116 } else { 2117 sc->sc_txcfg = TXCFG_MXDMA_512; 2118 sc->sc_rxcfg = RXCFG_MXDMA_512; 2119 } 2120 #endif /* DP83820 */ 2121 2122 sc->sc_txcfg |= TXCFG_ATP | 2123 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2124 sc->sc_tx_drain_thresh; 2125 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2126 2127 /* 2128 * Initialize the receive drain threshold if we have never 2129 * done so. 2130 */ 2131 if (sc->sc_rx_drain_thresh == 0) { 2132 /* 2133 * XXX This value should be tuned. This is set to the 2134 * maximum of 248 bytes, and we may be able to improve 2135 * performance by decreasing it (although we should never 2136 * set this value lower than 2; 14 bytes are required to 2137 * filter the packet). 2138 */ 2139 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2140 } 2141 2142 /* 2143 * Initialize the prototype RXCFG register. 2144 */ 2145 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2146 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2147 2148 #ifdef DP83820 2149 /* 2150 * Initialize the VLAN/IP receive control register. 2151 * We enable checksum computation on all incoming 2152 * packets, and do not reject packets w/ bad checksums. 2153 */ 2154 reg = 0; 2155 if (ifp->if_capenable & 2156 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2157 reg |= VRCR_IPEN; 2158 if (sc->sc_ethercom.ec_nvlans != 0) 2159 reg |= VRCR_VTDEN|VRCR_VTREN; 2160 bus_space_write_4(st, sh, SIP_VRCR, reg); 2161 2162 /* 2163 * Initialize the VLAN/IP transmit control register. 2164 * We enable outgoing checksum computation on a 2165 * per-packet basis. 2166 */ 2167 reg = 0; 2168 if (ifp->if_capenable & 2169 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2170 reg |= VTCR_PPCHK; 2171 if (sc->sc_ethercom.ec_nvlans != 0) 2172 reg |= VTCR_VPPTI; 2173 bus_space_write_4(st, sh, SIP_VTCR, reg); 2174 2175 /* 2176 * If we're using VLANs, initialize the VLAN data register. 2177 * To understand why we bswap the VLAN Ethertype, see section 2178 * 4.2.36 of the DP83820 manual. 2179 */ 2180 if (sc->sc_ethercom.ec_nvlans != 0) 2181 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2182 #endif /* DP83820 */ 2183 2184 /* 2185 * Give the transmit and receive rings to the chip. 2186 */ 2187 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2188 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2189 2190 /* 2191 * Initialize the interrupt mask. 2192 */ 2193 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2194 ISR_TXURN|ISR_TXDESC|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2195 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2196 2197 /* Set up the receive filter. */ 2198 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2199 2200 /* 2201 * Set the current media. Do this after initializing the prototype 2202 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2203 * control. 2204 */ 2205 mii_mediachg(&sc->sc_mii); 2206 2207 /* 2208 * Enable interrupts. 2209 */ 2210 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2211 2212 /* 2213 * Start the transmit and receive processes. 2214 */ 2215 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2216 2217 /* 2218 * Start the one second MII clock. 2219 */ 2220 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2221 2222 /* 2223 * ...all done! 2224 */ 2225 ifp->if_flags |= IFF_RUNNING; 2226 ifp->if_flags &= ~IFF_OACTIVE; 2227 2228 out: 2229 if (error) 2230 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2231 return (error); 2232 } 2233 2234 /* 2235 * sip_drain: 2236 * 2237 * Drain the receive queue. 2238 */ 2239 void 2240 SIP_DECL(rxdrain)(struct sip_softc *sc) 2241 { 2242 struct sip_rxsoft *rxs; 2243 int i; 2244 2245 for (i = 0; i < SIP_NRXDESC; i++) { 2246 rxs = &sc->sc_rxsoft[i]; 2247 if (rxs->rxs_mbuf != NULL) { 2248 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2249 m_freem(rxs->rxs_mbuf); 2250 rxs->rxs_mbuf = NULL; 2251 } 2252 } 2253 } 2254 2255 /* 2256 * sip_stop: [ ifnet interface function ] 2257 * 2258 * Stop transmission on the interface. 2259 */ 2260 void 2261 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2262 { 2263 struct sip_softc *sc = ifp->if_softc; 2264 bus_space_tag_t st = sc->sc_st; 2265 bus_space_handle_t sh = sc->sc_sh; 2266 struct sip_txsoft *txs; 2267 u_int32_t cmdsts = 0; /* DEBUG */ 2268 2269 /* 2270 * Stop the one second clock. 2271 */ 2272 callout_stop(&sc->sc_tick_ch); 2273 2274 /* Down the MII. */ 2275 mii_down(&sc->sc_mii); 2276 2277 /* 2278 * Disable interrupts. 2279 */ 2280 bus_space_write_4(st, sh, SIP_IER, 0); 2281 2282 /* 2283 * Stop receiver and transmitter. 2284 */ 2285 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2286 2287 /* 2288 * Release any queued transmit buffers. 2289 */ 2290 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2291 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2292 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2293 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2294 CMDSTS_INTR) == 0) 2295 printf("%s: sip_stop: last descriptor does not " 2296 "have INTR bit set\n", sc->sc_dev.dv_xname); 2297 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 2298 #ifdef DIAGNOSTIC 2299 if (txs->txs_mbuf == NULL) { 2300 printf("%s: dirty txsoft with no mbuf chain\n", 2301 sc->sc_dev.dv_xname); 2302 panic("sip_stop"); 2303 } 2304 #endif 2305 cmdsts |= /* DEBUG */ 2306 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2307 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2308 m_freem(txs->txs_mbuf); 2309 txs->txs_mbuf = NULL; 2310 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2311 } 2312 2313 if (disable) 2314 SIP_DECL(rxdrain)(sc); 2315 2316 /* 2317 * Mark the interface down and cancel the watchdog timer. 2318 */ 2319 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2320 ifp->if_timer = 0; 2321 2322 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2323 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2324 printf("%s: sip_stop: no INTR bits set in dirty tx " 2325 "descriptors\n", sc->sc_dev.dv_xname); 2326 } 2327 2328 /* 2329 * sip_read_eeprom: 2330 * 2331 * Read data from the serial EEPROM. 2332 */ 2333 void 2334 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2335 u_int16_t *data) 2336 { 2337 bus_space_tag_t st = sc->sc_st; 2338 bus_space_handle_t sh = sc->sc_sh; 2339 u_int16_t reg; 2340 int i, x; 2341 2342 for (i = 0; i < wordcnt; i++) { 2343 /* Send CHIP SELECT. */ 2344 reg = EROMAR_EECS; 2345 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2346 2347 /* Shift in the READ opcode. */ 2348 for (x = 3; x > 0; x--) { 2349 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2350 reg |= EROMAR_EEDI; 2351 else 2352 reg &= ~EROMAR_EEDI; 2353 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2354 bus_space_write_4(st, sh, SIP_EROMAR, 2355 reg | EROMAR_EESK); 2356 delay(4); 2357 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2358 delay(4); 2359 } 2360 2361 /* Shift in address. */ 2362 for (x = 6; x > 0; x--) { 2363 if ((word + i) & (1 << (x - 1))) 2364 reg |= EROMAR_EEDI; 2365 else 2366 reg &= ~EROMAR_EEDI; 2367 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2368 bus_space_write_4(st, sh, SIP_EROMAR, 2369 reg | EROMAR_EESK); 2370 delay(4); 2371 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2372 delay(4); 2373 } 2374 2375 /* Shift out data. */ 2376 reg = EROMAR_EECS; 2377 data[i] = 0; 2378 for (x = 16; x > 0; x--) { 2379 bus_space_write_4(st, sh, SIP_EROMAR, 2380 reg | EROMAR_EESK); 2381 delay(4); 2382 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2383 data[i] |= (1 << (x - 1)); 2384 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2385 delay(4); 2386 } 2387 2388 /* Clear CHIP SELECT. */ 2389 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2390 delay(4); 2391 } 2392 } 2393 2394 /* 2395 * sip_add_rxbuf: 2396 * 2397 * Add a receive buffer to the indicated descriptor. 2398 */ 2399 int 2400 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2401 { 2402 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2403 struct mbuf *m; 2404 int error; 2405 2406 MGETHDR(m, M_DONTWAIT, MT_DATA); 2407 if (m == NULL) 2408 return (ENOBUFS); 2409 2410 MCLGET(m, M_DONTWAIT); 2411 if ((m->m_flags & M_EXT) == 0) { 2412 m_freem(m); 2413 return (ENOBUFS); 2414 } 2415 2416 #if defined(DP83820) 2417 m->m_len = SIP_RXBUF_LEN; 2418 #endif /* DP83820 */ 2419 2420 if (rxs->rxs_mbuf != NULL) 2421 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2422 2423 rxs->rxs_mbuf = m; 2424 2425 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2426 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2427 BUS_DMA_READ|BUS_DMA_NOWAIT); 2428 if (error) { 2429 printf("%s: can't load rx DMA map %d, error = %d\n", 2430 sc->sc_dev.dv_xname, idx, error); 2431 panic("sip_add_rxbuf"); /* XXX */ 2432 } 2433 2434 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2435 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2436 2437 SIP_INIT_RXDESC(sc, idx); 2438 2439 return (0); 2440 } 2441 2442 #if !defined(DP83820) 2443 /* 2444 * sip_sis900_set_filter: 2445 * 2446 * Set up the receive filter. 2447 */ 2448 void 2449 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2450 { 2451 bus_space_tag_t st = sc->sc_st; 2452 bus_space_handle_t sh = sc->sc_sh; 2453 struct ethercom *ec = &sc->sc_ethercom; 2454 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2455 struct ether_multi *enm; 2456 u_int8_t *cp; 2457 struct ether_multistep step; 2458 u_int32_t crc, mchash[16]; 2459 2460 /* 2461 * Initialize the prototype RFCR. 2462 */ 2463 sc->sc_rfcr = RFCR_RFEN; 2464 if (ifp->if_flags & IFF_BROADCAST) 2465 sc->sc_rfcr |= RFCR_AAB; 2466 if (ifp->if_flags & IFF_PROMISC) { 2467 sc->sc_rfcr |= RFCR_AAP; 2468 goto allmulti; 2469 } 2470 2471 /* 2472 * Set up the multicast address filter by passing all multicast 2473 * addresses through a CRC generator, and then using the high-order 2474 * 6 bits as an index into the 128 bit multicast hash table (only 2475 * the lower 16 bits of each 32 bit multicast hash register are 2476 * valid). The high order bits select the register, while the 2477 * rest of the bits select the bit within the register. 2478 */ 2479 2480 memset(mchash, 0, sizeof(mchash)); 2481 2482 ETHER_FIRST_MULTI(step, ec, enm); 2483 while (enm != NULL) { 2484 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2485 /* 2486 * We must listen to a range of multicast addresses. 2487 * For now, just accept all multicasts, rather than 2488 * trying to set only those filter bits needed to match 2489 * the range. (At this time, the only use of address 2490 * ranges is for IP multicast routing, for which the 2491 * range is big enough to require all bits set.) 2492 */ 2493 goto allmulti; 2494 } 2495 2496 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2497 2498 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2499 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2500 /* Just want the 8 most significant bits. */ 2501 crc >>= 24; 2502 } else { 2503 /* Just want the 7 most significant bits. */ 2504 crc >>= 25; 2505 } 2506 2507 /* Set the corresponding bit in the hash table. */ 2508 mchash[crc >> 4] |= 1 << (crc & 0xf); 2509 2510 ETHER_NEXT_MULTI(step, enm); 2511 } 2512 2513 ifp->if_flags &= ~IFF_ALLMULTI; 2514 goto setit; 2515 2516 allmulti: 2517 ifp->if_flags |= IFF_ALLMULTI; 2518 sc->sc_rfcr |= RFCR_AAM; 2519 2520 setit: 2521 #define FILTER_EMIT(addr, data) \ 2522 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2523 delay(1); \ 2524 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2525 delay(1) 2526 2527 /* 2528 * Disable receive filter, and program the node address. 2529 */ 2530 cp = LLADDR(ifp->if_sadl); 2531 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2532 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2533 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2534 2535 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2536 /* 2537 * Program the multicast hash table. 2538 */ 2539 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2540 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2541 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2542 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2543 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2544 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2545 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2546 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2547 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2548 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2549 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2550 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2551 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2552 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2553 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2554 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2555 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2556 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2557 } 2558 } 2559 #undef FILTER_EMIT 2560 2561 /* 2562 * Re-enable the receiver filter. 2563 */ 2564 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2565 } 2566 #endif /* ! DP83820 */ 2567 2568 /* 2569 * sip_dp83815_set_filter: 2570 * 2571 * Set up the receive filter. 2572 */ 2573 void 2574 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2575 { 2576 bus_space_tag_t st = sc->sc_st; 2577 bus_space_handle_t sh = sc->sc_sh; 2578 struct ethercom *ec = &sc->sc_ethercom; 2579 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2580 struct ether_multi *enm; 2581 u_int8_t *cp; 2582 struct ether_multistep step; 2583 u_int32_t crc, hash, slot, bit; 2584 #ifdef DP83820 2585 #define MCHASH_NWORDS 128 2586 #else 2587 #define MCHASH_NWORDS 32 2588 #endif /* DP83820 */ 2589 u_int16_t mchash[MCHASH_NWORDS]; 2590 int i; 2591 2592 /* 2593 * Initialize the prototype RFCR. 2594 * Enable the receive filter, and accept on 2595 * Perfect (destination address) Match 2596 * If IFF_BROADCAST, also accept all broadcast packets. 2597 * If IFF_PROMISC, accept all unicast packets (and later, set 2598 * IFF_ALLMULTI and accept all multicast, too). 2599 */ 2600 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2601 if (ifp->if_flags & IFF_BROADCAST) 2602 sc->sc_rfcr |= RFCR_AAB; 2603 if (ifp->if_flags & IFF_PROMISC) { 2604 sc->sc_rfcr |= RFCR_AAP; 2605 goto allmulti; 2606 } 2607 2608 #ifdef DP83820 2609 /* 2610 * Set up the DP83820 multicast address filter by passing all multicast 2611 * addresses through a CRC generator, and then using the high-order 2612 * 11 bits as an index into the 2048 bit multicast hash table. The 2613 * high-order 7 bits select the slot, while the low-order 4 bits 2614 * select the bit within the slot. Note that only the low 16-bits 2615 * of each filter word are used, and there are 128 filter words. 2616 */ 2617 #else 2618 /* 2619 * Set up the DP83815 multicast address filter by passing all multicast 2620 * addresses through a CRC generator, and then using the high-order 2621 * 9 bits as an index into the 512 bit multicast hash table. The 2622 * high-order 5 bits select the slot, while the low-order 4 bits 2623 * select the bit within the slot. Note that only the low 16-bits 2624 * of each filter word are used, and there are 32 filter words. 2625 */ 2626 #endif /* DP83820 */ 2627 2628 memset(mchash, 0, sizeof(mchash)); 2629 2630 ifp->if_flags &= ~IFF_ALLMULTI; 2631 ETHER_FIRST_MULTI(step, ec, enm); 2632 if (enm == NULL) 2633 goto setit; 2634 while (enm != NULL) { 2635 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2636 /* 2637 * We must listen to a range of multicast addresses. 2638 * For now, just accept all multicasts, rather than 2639 * trying to set only those filter bits needed to match 2640 * the range. (At this time, the only use of address 2641 * ranges is for IP multicast routing, for which the 2642 * range is big enough to require all bits set.) 2643 */ 2644 goto allmulti; 2645 } 2646 2647 #ifdef DP83820 2648 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2649 2650 /* Just want the 11 most significant bits. */ 2651 hash = crc >> 21; 2652 #else 2653 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2654 2655 /* Just want the 9 most significant bits. */ 2656 hash = crc >> 23; 2657 #endif /* DP83820 */ 2658 slot = hash >> 4; 2659 bit = hash & 0xf; 2660 2661 /* Set the corresponding bit in the hash table. */ 2662 mchash[slot] |= 1 << bit; 2663 2664 ETHER_NEXT_MULTI(step, enm); 2665 } 2666 sc->sc_rfcr |= RFCR_MHEN; 2667 goto setit; 2668 2669 allmulti: 2670 ifp->if_flags |= IFF_ALLMULTI; 2671 sc->sc_rfcr |= RFCR_AAM; 2672 2673 setit: 2674 #define FILTER_EMIT(addr, data) \ 2675 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2676 delay(1); \ 2677 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2678 delay(1) 2679 2680 /* 2681 * Disable receive filter, and program the node address. 2682 */ 2683 cp = LLADDR(ifp->if_sadl); 2684 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 2685 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 2686 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 2687 2688 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2689 /* 2690 * Program the multicast hash table. 2691 */ 2692 for (i = 0; i < MCHASH_NWORDS; i++) { 2693 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 2694 mchash[i]); 2695 } 2696 } 2697 #undef FILTER_EMIT 2698 #undef MCHASH_NWORDS 2699 2700 /* 2701 * Re-enable the receiver filter. 2702 */ 2703 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2704 } 2705 2706 #if defined(DP83820) 2707 /* 2708 * sip_dp83820_mii_readreg: [mii interface function] 2709 * 2710 * Read a PHY register on the MII of the DP83820. 2711 */ 2712 int 2713 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 2714 { 2715 2716 return (mii_bitbang_readreg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2717 phy, reg)); 2718 } 2719 2720 /* 2721 * sip_dp83820_mii_writereg: [mii interface function] 2722 * 2723 * Write a PHY register on the MII of the DP83820. 2724 */ 2725 void 2726 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 2727 { 2728 2729 mii_bitbang_writereg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2730 phy, reg, val); 2731 } 2732 2733 /* 2734 * sip_dp83815_mii_statchg: [mii interface function] 2735 * 2736 * Callback from MII layer when media changes. 2737 */ 2738 void 2739 SIP_DECL(dp83820_mii_statchg)(struct device *self) 2740 { 2741 struct sip_softc *sc = (struct sip_softc *) self; 2742 u_int32_t cfg; 2743 2744 /* 2745 * Update TXCFG for full-duplex operation. 2746 */ 2747 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2748 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2749 else 2750 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2751 2752 /* 2753 * Update RXCFG for full-duplex or loopback. 2754 */ 2755 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2756 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2757 sc->sc_rxcfg |= RXCFG_ATX; 2758 else 2759 sc->sc_rxcfg &= ~RXCFG_ATX; 2760 2761 /* 2762 * Update CFG for MII/GMII. 2763 */ 2764 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2765 cfg = sc->sc_cfg | CFG_MODE_1000; 2766 else 2767 cfg = sc->sc_cfg; 2768 2769 /* 2770 * XXX 802.3x flow control. 2771 */ 2772 2773 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 2774 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2775 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2776 } 2777 2778 /* 2779 * sip_dp83820_mii_bitbang_read: [mii bit-bang interface function] 2780 * 2781 * Read the MII serial port for the MII bit-bang module. 2782 */ 2783 u_int32_t 2784 SIP_DECL(dp83820_mii_bitbang_read)(struct device *self) 2785 { 2786 struct sip_softc *sc = (void *) self; 2787 2788 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 2789 } 2790 2791 /* 2792 * sip_dp83820_mii_bitbang_write: [mii big-bang interface function] 2793 * 2794 * Write the MII serial port for the MII bit-bang module. 2795 */ 2796 void 2797 SIP_DECL(dp83820_mii_bitbang_write)(struct device *self, u_int32_t val) 2798 { 2799 struct sip_softc *sc = (void *) self; 2800 2801 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 2802 } 2803 #else /* ! DP83820 */ 2804 /* 2805 * sip_sis900_mii_readreg: [mii interface function] 2806 * 2807 * Read a PHY register on the MII. 2808 */ 2809 int 2810 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 2811 { 2812 struct sip_softc *sc = (struct sip_softc *) self; 2813 u_int32_t enphy; 2814 2815 /* 2816 * The SiS 900 has only an internal PHY on the MII. Only allow 2817 * MII address 0. 2818 */ 2819 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 2820 sc->sc_rev < SIS_REV_635 && phy != 0) 2821 return (0); 2822 2823 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2824 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 2825 ENPHY_RWCMD | ENPHY_ACCESS); 2826 do { 2827 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2828 } while (enphy & ENPHY_ACCESS); 2829 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 2830 } 2831 2832 /* 2833 * sip_sis900_mii_writereg: [mii interface function] 2834 * 2835 * Write a PHY register on the MII. 2836 */ 2837 void 2838 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 2839 { 2840 struct sip_softc *sc = (struct sip_softc *) self; 2841 u_int32_t enphy; 2842 2843 /* 2844 * The SiS 900 has only an internal PHY on the MII. Only allow 2845 * MII address 0. 2846 */ 2847 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 2848 sc->sc_rev < SIS_REV_635 && phy != 0) 2849 return; 2850 2851 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2852 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 2853 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 2854 do { 2855 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2856 } while (enphy & ENPHY_ACCESS); 2857 } 2858 2859 /* 2860 * sip_sis900_mii_statchg: [mii interface function] 2861 * 2862 * Callback from MII layer when media changes. 2863 */ 2864 void 2865 SIP_DECL(sis900_mii_statchg)(struct device *self) 2866 { 2867 struct sip_softc *sc = (struct sip_softc *) self; 2868 u_int32_t flowctl; 2869 2870 /* 2871 * Update TXCFG for full-duplex operation. 2872 */ 2873 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2874 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2875 else 2876 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2877 2878 /* 2879 * Update RXCFG for full-duplex or loopback. 2880 */ 2881 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2882 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2883 sc->sc_rxcfg |= RXCFG_ATX; 2884 else 2885 sc->sc_rxcfg &= ~RXCFG_ATX; 2886 2887 /* 2888 * Update IMR for use of 802.3x flow control. 2889 */ 2890 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 2891 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 2892 flowctl = FLOWCTL_FLOWEN; 2893 } else { 2894 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 2895 flowctl = 0; 2896 } 2897 2898 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2899 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2900 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 2901 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 2902 } 2903 2904 /* 2905 * sip_dp83815_mii_readreg: [mii interface function] 2906 * 2907 * Read a PHY register on the MII. 2908 */ 2909 int 2910 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 2911 { 2912 struct sip_softc *sc = (struct sip_softc *) self; 2913 u_int32_t val; 2914 2915 /* 2916 * The DP83815 only has an internal PHY. Only allow 2917 * MII address 0. 2918 */ 2919 if (phy != 0) 2920 return (0); 2921 2922 /* 2923 * Apparently, after a reset, the DP83815 can take a while 2924 * to respond. During this recovery period, the BMSR returns 2925 * a value of 0. Catch this -- it's not supposed to happen 2926 * (the BMSR has some hardcoded-to-1 bits), and wait for the 2927 * PHY to come back to life. 2928 * 2929 * This works out because the BMSR is the first register 2930 * read during the PHY probe process. 2931 */ 2932 do { 2933 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 2934 } while (reg == MII_BMSR && val == 0); 2935 2936 return (val & 0xffff); 2937 } 2938 2939 /* 2940 * sip_dp83815_mii_writereg: [mii interface function] 2941 * 2942 * Write a PHY register to the MII. 2943 */ 2944 void 2945 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 2946 { 2947 struct sip_softc *sc = (struct sip_softc *) self; 2948 2949 /* 2950 * The DP83815 only has an internal PHY. Only allow 2951 * MII address 0. 2952 */ 2953 if (phy != 0) 2954 return; 2955 2956 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 2957 } 2958 2959 /* 2960 * sip_dp83815_mii_statchg: [mii interface function] 2961 * 2962 * Callback from MII layer when media changes. 2963 */ 2964 void 2965 SIP_DECL(dp83815_mii_statchg)(struct device *self) 2966 { 2967 struct sip_softc *sc = (struct sip_softc *) self; 2968 2969 /* 2970 * Update TXCFG for full-duplex operation. 2971 */ 2972 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2973 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2974 else 2975 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2976 2977 /* 2978 * Update RXCFG for full-duplex or loopback. 2979 */ 2980 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2981 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2982 sc->sc_rxcfg |= RXCFG_ATX; 2983 else 2984 sc->sc_rxcfg &= ~RXCFG_ATX; 2985 2986 /* 2987 * XXX 802.3x flow control. 2988 */ 2989 2990 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2991 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2992 } 2993 #endif /* DP83820 */ 2994 2995 #if defined(DP83820) 2996 void 2997 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 2998 const struct pci_attach_args *pa, u_int8_t *enaddr) 2999 { 3000 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3001 u_int8_t cksum, *e, match; 3002 int i; 3003 3004 /* 3005 * EEPROM data format for the DP83820 can be found in 3006 * the DP83820 manual, section 4.2.4. 3007 */ 3008 3009 SIP_DECL(read_eeprom)(sc, 0, 3010 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3011 3012 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3013 match = ~(match - 1); 3014 3015 cksum = 0x55; 3016 e = (u_int8_t *) eeprom_data; 3017 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3018 cksum += *e++; 3019 3020 if (cksum != match) 3021 printf("%s: Checksum (%x) mismatch (%x)", 3022 sc->sc_dev.dv_xname, cksum, match); 3023 3024 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3025 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3026 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3027 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3028 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3029 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3030 3031 /* Get the GPIOR bits. */ 3032 sc->sc_gpior = eeprom_data[0x04]; 3033 3034 /* Get various CFG related bits. */ 3035 if ((eeprom_data[0x05] >> 0) & 1) 3036 sc->sc_cfg |= CFG_EXT_125; 3037 if ((eeprom_data[0x05] >> 9) & 1) 3038 sc->sc_cfg |= CFG_TBI_EN; 3039 } 3040 #else /* ! DP83820 */ 3041 void 3042 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3043 const struct pci_attach_args *pa, u_int8_t *enaddr) 3044 { 3045 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3046 3047 switch (PCI_REVISION(pa->pa_class)) { 3048 case SIS_REV_630S: 3049 case SIS_REV_630E: 3050 case SIS_REV_630EA1: 3051 case SIS_REV_635: 3052 /* 3053 * The MAC address for the on-board Ethernet of 3054 * the SiS 630 chipset is in the NVRAM. Kick 3055 * the chip into re-loading it from NVRAM, and 3056 * read the MAC address out of the filter registers. 3057 */ 3058 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3059 3060 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3061 RFCR_RFADDR_NODE0); 3062 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3063 0xffff; 3064 3065 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3066 RFCR_RFADDR_NODE2); 3067 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3068 0xffff; 3069 3070 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3071 RFCR_RFADDR_NODE4); 3072 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3073 0xffff; 3074 break; 3075 3076 default: 3077 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3078 sizeof(myea) / sizeof(myea[0]), myea); 3079 } 3080 3081 enaddr[0] = myea[0] & 0xff; 3082 enaddr[1] = myea[0] >> 8; 3083 enaddr[2] = myea[1] & 0xff; 3084 enaddr[3] = myea[1] >> 8; 3085 enaddr[4] = myea[2] & 0xff; 3086 enaddr[5] = myea[2] >> 8; 3087 } 3088 3089 /* Table and macro to bit-reverse an octet. */ 3090 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3091 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3092 3093 void 3094 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3095 const struct pci_attach_args *pa, u_int8_t *enaddr) 3096 { 3097 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3098 u_int8_t cksum, *e, match; 3099 int i; 3100 3101 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3102 sizeof(eeprom_data[0]), eeprom_data); 3103 3104 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3105 match = ~(match - 1); 3106 3107 cksum = 0x55; 3108 e = (u_int8_t *) eeprom_data; 3109 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3110 cksum += *e++; 3111 } 3112 if (cksum != match) { 3113 printf("%s: Checksum (%x) mismatch (%x)", 3114 sc->sc_dev.dv_xname, cksum, match); 3115 } 3116 3117 /* 3118 * Unrolled because it makes slightly more sense this way. 3119 * The DP83815 stores the MAC address in bit 0 of word 6 3120 * through bit 15 of word 8. 3121 */ 3122 ea = &eeprom_data[6]; 3123 enaddr[0] = ((*ea & 0x1) << 7); 3124 ea++; 3125 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3126 enaddr[1] = ((*ea & 0x1FE) >> 1); 3127 enaddr[2] = ((*ea & 0x1) << 7); 3128 ea++; 3129 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3130 enaddr[3] = ((*ea & 0x1FE) >> 1); 3131 enaddr[4] = ((*ea & 0x1) << 7); 3132 ea++; 3133 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3134 enaddr[5] = ((*ea & 0x1FE) >> 1); 3135 3136 /* 3137 * In case that's not weird enough, we also need to reverse 3138 * the bits in each byte. This all actually makes more sense 3139 * if you think about the EEPROM storage as an array of bits 3140 * being shifted into bytes, but that's not how we're looking 3141 * at it here... 3142 */ 3143 for (i = 0; i < 6 ;i++) 3144 enaddr[i] = bbr(enaddr[i]); 3145 } 3146 #endif /* DP83820 */ 3147 3148 /* 3149 * sip_mediastatus: [ifmedia interface function] 3150 * 3151 * Get the current interface media status. 3152 */ 3153 void 3154 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3155 { 3156 struct sip_softc *sc = ifp->if_softc; 3157 3158 mii_pollstat(&sc->sc_mii); 3159 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3160 ifmr->ifm_active = sc->sc_mii.mii_media_active; 3161 } 3162 3163 /* 3164 * sip_mediachange: [ifmedia interface function] 3165 * 3166 * Set hardware to newly-selected media. 3167 */ 3168 int 3169 SIP_DECL(mediachange)(struct ifnet *ifp) 3170 { 3171 struct sip_softc *sc = ifp->if_softc; 3172 3173 if (ifp->if_flags & IFF_UP) 3174 mii_mediachg(&sc->sc_mii); 3175 return (0); 3176 } 3177
Indexes created Tue Sep 30 11:09:46 GMT 2025