if_sip.c revision 1.24.2.9
1 /* $NetBSD: if_sip.c,v 1.24.2.9 2002/08/01 02:45:16 nathanw Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Support the 10-bit interface on the DP83820 (for fiber). 80 * 81 * - Reduce the Rx interrupt load. 82 */ 83 84 #include <sys/cdefs.h> 85 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.24.2.9 2002/08/01 02:45:16 nathanw Exp $"); 86 87 #include "bpfilter.h" 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/callout.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/ioctl.h> 97 #include <sys/errno.h> 98 #include <sys/device.h> 99 #include <sys/queue.h> 100 101 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 102 103 #include <net/if.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 #include <net/if_ether.h> 107 108 #if NBPFILTER > 0 109 #include <net/bpf.h> 110 #endif 111 112 #include <machine/bus.h> 113 #include <machine/intr.h> 114 #include <machine/endian.h> 115 116 #include <dev/mii/mii.h> 117 #include <dev/mii/miivar.h> 118 #ifdef DP83820 119 #include <dev/mii/mii_bitbang.h> 120 #endif /* DP83820 */ 121 122 #include <dev/pci/pcireg.h> 123 #include <dev/pci/pcivar.h> 124 #include <dev/pci/pcidevs.h> 125 126 #include <dev/pci/if_sipreg.h> 127 128 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 129 #define SIP_DECL(x) __CONCAT(gsip_,x) 130 #else /* SiS900 and DP83815 */ 131 #define SIP_DECL(x) __CONCAT(sip_,x) 132 #endif 133 134 #define SIP_STR(x) __STRING(SIP_DECL(x)) 135 136 /* 137 * Transmit descriptor list size. This is arbitrary, but allocate 138 * enough descriptors for 128 pending transmissions, and 8 segments 139 * per packet. This MUST work out to a power of 2. 140 */ 141 #define SIP_NTXSEGS 16 142 #define SIP_NTXSEGS_ALLOC 8 143 144 #define SIP_TXQUEUELEN 256 145 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 146 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 147 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 148 149 #if defined(DP83020) 150 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 151 #else 152 #define TX_DMAMAP_SIZE MCLBYTES 153 #endif 154 155 /* 156 * Receive descriptor list size. We have one Rx buffer per incoming 157 * packet, so this logic is a little simpler. 158 * 159 * Actually, on the DP83820, we allow the packet to consume more than 160 * one buffer, in order to support jumbo Ethernet frames. In that 161 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 162 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 163 * so we'd better be quick about handling receive interrupts. 164 */ 165 #if defined(DP83820) 166 #define SIP_NRXDESC 256 167 #else 168 #define SIP_NRXDESC 128 169 #endif /* DP83820 */ 170 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 171 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 172 173 /* 174 * Control structures are DMA'd to the SiS900 chip. We allocate them in 175 * a single clump that maps to a single DMA segment to make several things 176 * easier. 177 */ 178 struct sip_control_data { 179 /* 180 * The transmit descriptors. 181 */ 182 struct sip_desc scd_txdescs[SIP_NTXDESC]; 183 184 /* 185 * The receive descriptors. 186 */ 187 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 188 }; 189 190 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 191 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 192 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 193 194 /* 195 * Software state for transmit jobs. 196 */ 197 struct sip_txsoft { 198 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 199 bus_dmamap_t txs_dmamap; /* our DMA map */ 200 int txs_firstdesc; /* first descriptor in packet */ 201 int txs_lastdesc; /* last descriptor in packet */ 202 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 203 }; 204 205 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 206 207 /* 208 * Software state for receive jobs. 209 */ 210 struct sip_rxsoft { 211 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 212 bus_dmamap_t rxs_dmamap; /* our DMA map */ 213 }; 214 215 /* 216 * Software state per device. 217 */ 218 struct sip_softc { 219 struct device sc_dev; /* generic device information */ 220 bus_space_tag_t sc_st; /* bus space tag */ 221 bus_space_handle_t sc_sh; /* bus space handle */ 222 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 223 struct ethercom sc_ethercom; /* ethernet common data */ 224 void *sc_sdhook; /* shutdown hook */ 225 226 const struct sip_product *sc_model; /* which model are we? */ 227 int sc_rev; /* chip revision */ 228 229 void *sc_ih; /* interrupt cookie */ 230 231 struct mii_data sc_mii; /* MII/media information */ 232 233 struct callout sc_tick_ch; /* tick callout */ 234 235 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 236 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 237 238 /* 239 * Software state for transmit and receive descriptors. 240 */ 241 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 242 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 243 244 /* 245 * Control data structures. 246 */ 247 struct sip_control_data *sc_control_data; 248 #define sc_txdescs sc_control_data->scd_txdescs 249 #define sc_rxdescs sc_control_data->scd_rxdescs 250 251 #ifdef SIP_EVENT_COUNTERS 252 /* 253 * Event counters. 254 */ 255 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 256 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 257 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 258 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 259 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 260 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 261 #ifdef DP83820 262 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 263 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 264 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 265 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 266 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 267 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 268 #endif /* DP83820 */ 269 #endif /* SIP_EVENT_COUNTERS */ 270 271 u_int32_t sc_txcfg; /* prototype TXCFG register */ 272 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 273 u_int32_t sc_imr; /* prototype IMR register */ 274 u_int32_t sc_rfcr; /* prototype RFCR register */ 275 276 u_int32_t sc_cfg; /* prototype CFG register */ 277 278 #ifdef DP83820 279 u_int32_t sc_gpior; /* prototype GPIOR register */ 280 #endif /* DP83820 */ 281 282 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 283 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 284 285 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 286 287 int sc_flags; /* misc. flags; see below */ 288 289 int sc_txfree; /* number of free Tx descriptors */ 290 int sc_txnext; /* next ready Tx descriptor */ 291 int sc_txwin; /* Tx descriptors since last intr */ 292 293 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 294 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 295 296 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 297 #if defined(DP83820) 298 int sc_rxdiscard; 299 int sc_rxlen; 300 struct mbuf *sc_rxhead; 301 struct mbuf *sc_rxtail; 302 struct mbuf **sc_rxtailp; 303 #endif /* DP83820 */ 304 }; 305 306 /* sc_flags */ 307 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 308 309 #ifdef DP83820 310 #define SIP_RXCHAIN_RESET(sc) \ 311 do { \ 312 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 313 *(sc)->sc_rxtailp = NULL; \ 314 (sc)->sc_rxlen = 0; \ 315 } while (/*CONSTCOND*/0) 316 317 #define SIP_RXCHAIN_LINK(sc, m) \ 318 do { \ 319 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 320 (sc)->sc_rxtailp = &(m)->m_next; \ 321 } while (/*CONSTCOND*/0) 322 #endif /* DP83820 */ 323 324 #ifdef SIP_EVENT_COUNTERS 325 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 326 #else 327 #define SIP_EVCNT_INCR(ev) /* nothing */ 328 #endif 329 330 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 331 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 332 333 #define SIP_CDTXSYNC(sc, x, n, ops) \ 334 do { \ 335 int __x, __n; \ 336 \ 337 __x = (x); \ 338 __n = (n); \ 339 \ 340 /* If it will wrap around, sync to the end of the ring. */ \ 341 if ((__x + __n) > SIP_NTXDESC) { \ 342 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 343 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 344 (SIP_NTXDESC - __x), (ops)); \ 345 __n -= (SIP_NTXDESC - __x); \ 346 __x = 0; \ 347 } \ 348 \ 349 /* Now sync whatever is left. */ \ 350 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 351 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 352 } while (0) 353 354 #define SIP_CDRXSYNC(sc, x, ops) \ 355 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 356 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 357 358 #ifdef DP83820 359 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 360 #define SIP_RXBUF_LEN (MCLBYTES - 4) 361 #else 362 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 363 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 364 #endif 365 #define SIP_INIT_RXDESC(sc, x) \ 366 do { \ 367 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 368 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 369 \ 370 __sipd->sipd_link = \ 371 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 372 __sipd->sipd_bufptr = \ 373 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 374 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 375 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 376 SIP_INIT_RXDESC_EXTSTS \ 377 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 378 } while (0) 379 380 #define SIP_CHIP_VERS(sc, v, p, r) \ 381 ((sc)->sc_model->sip_vendor == (v) && \ 382 (sc)->sc_model->sip_product == (p) && \ 383 (sc)->sc_rev == (r)) 384 385 #define SIP_CHIP_MODEL(sc, v, p) \ 386 ((sc)->sc_model->sip_vendor == (v) && \ 387 (sc)->sc_model->sip_product == (p)) 388 389 #if !defined(DP83820) 390 #define SIP_SIS900_REV(sc, rev) \ 391 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 392 #endif 393 394 #define SIP_TIMEOUT 1000 395 396 void SIP_DECL(start)(struct ifnet *); 397 void SIP_DECL(watchdog)(struct ifnet *); 398 int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 399 int SIP_DECL(init)(struct ifnet *); 400 void SIP_DECL(stop)(struct ifnet *, int); 401 402 void SIP_DECL(shutdown)(void *); 403 404 void SIP_DECL(reset)(struct sip_softc *); 405 void SIP_DECL(rxdrain)(struct sip_softc *); 406 int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 407 void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, u_int16_t *); 408 void SIP_DECL(tick)(void *); 409 410 #if !defined(DP83820) 411 void SIP_DECL(sis900_set_filter)(struct sip_softc *); 412 #endif /* ! DP83820 */ 413 void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 414 415 #if defined(DP83820) 416 void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 417 const struct pci_attach_args *, u_int8_t *); 418 #else 419 void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 420 const struct pci_attach_args *, u_int8_t *); 421 void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 422 const struct pci_attach_args *, u_int8_t *); 423 #endif /* DP83820 */ 424 425 int SIP_DECL(intr)(void *); 426 void SIP_DECL(txintr)(struct sip_softc *); 427 void SIP_DECL(rxintr)(struct sip_softc *); 428 429 #if defined(DP83820) 430 int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 431 void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 432 void SIP_DECL(dp83820_mii_statchg)(struct device *); 433 #else 434 int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 435 void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 436 void SIP_DECL(sis900_mii_statchg)(struct device *); 437 438 int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 439 void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 440 void SIP_DECL(dp83815_mii_statchg)(struct device *); 441 #endif /* DP83820 */ 442 443 int SIP_DECL(mediachange)(struct ifnet *); 444 void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 445 446 int SIP_DECL(match)(struct device *, struct cfdata *, void *); 447 void SIP_DECL(attach)(struct device *, struct device *, void *); 448 449 int SIP_DECL(copy_small) = 0; 450 451 struct cfattach SIP_DECL(ca) = { 452 sizeof(struct sip_softc), SIP_DECL(match), SIP_DECL(attach), 453 }; 454 455 /* 456 * Descriptions of the variants of the SiS900. 457 */ 458 struct sip_variant { 459 int (*sipv_mii_readreg)(struct device *, int, int); 460 void (*sipv_mii_writereg)(struct device *, int, int, int); 461 void (*sipv_mii_statchg)(struct device *); 462 void (*sipv_set_filter)(struct sip_softc *); 463 void (*sipv_read_macaddr)(struct sip_softc *, 464 const struct pci_attach_args *, u_int8_t *); 465 }; 466 467 #if defined(DP83820) 468 u_int32_t SIP_DECL(dp83820_mii_bitbang_read)(struct device *); 469 void SIP_DECL(dp83820_mii_bitbang_write)(struct device *, u_int32_t); 470 471 const struct mii_bitbang_ops SIP_DECL(dp83820_mii_bitbang_ops) = { 472 SIP_DECL(dp83820_mii_bitbang_read), 473 SIP_DECL(dp83820_mii_bitbang_write), 474 { 475 EROMAR_MDIO, /* MII_BIT_MDO */ 476 EROMAR_MDIO, /* MII_BIT_MDI */ 477 EROMAR_MDC, /* MII_BIT_MDC */ 478 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 479 0, /* MII_BIT_DIR_PHY_HOST */ 480 } 481 }; 482 #endif /* DP83820 */ 483 484 #if defined(DP83820) 485 const struct sip_variant SIP_DECL(variant_dp83820) = { 486 SIP_DECL(dp83820_mii_readreg), 487 SIP_DECL(dp83820_mii_writereg), 488 SIP_DECL(dp83820_mii_statchg), 489 SIP_DECL(dp83815_set_filter), 490 SIP_DECL(dp83820_read_macaddr), 491 }; 492 #else 493 const struct sip_variant SIP_DECL(variant_sis900) = { 494 SIP_DECL(sis900_mii_readreg), 495 SIP_DECL(sis900_mii_writereg), 496 SIP_DECL(sis900_mii_statchg), 497 SIP_DECL(sis900_set_filter), 498 SIP_DECL(sis900_read_macaddr), 499 }; 500 501 const struct sip_variant SIP_DECL(variant_dp83815) = { 502 SIP_DECL(dp83815_mii_readreg), 503 SIP_DECL(dp83815_mii_writereg), 504 SIP_DECL(dp83815_mii_statchg), 505 SIP_DECL(dp83815_set_filter), 506 SIP_DECL(dp83815_read_macaddr), 507 }; 508 #endif /* DP83820 */ 509 510 /* 511 * Devices supported by this driver. 512 */ 513 const struct sip_product { 514 pci_vendor_id_t sip_vendor; 515 pci_product_id_t sip_product; 516 const char *sip_name; 517 const struct sip_variant *sip_variant; 518 } SIP_DECL(products)[] = { 519 #if defined(DP83820) 520 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 521 "NatSemi DP83820 Gigabit Ethernet", 522 &SIP_DECL(variant_dp83820) }, 523 #else 524 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 525 "SiS 900 10/100 Ethernet", 526 &SIP_DECL(variant_sis900) }, 527 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 528 "SiS 7016 10/100 Ethernet", 529 &SIP_DECL(variant_sis900) }, 530 531 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 532 "NatSemi DP83815 10/100 Ethernet", 533 &SIP_DECL(variant_dp83815) }, 534 #endif /* DP83820 */ 535 536 { 0, 0, 537 NULL, 538 NULL }, 539 }; 540 541 static const struct sip_product * 542 SIP_DECL(lookup)(const struct pci_attach_args *pa) 543 { 544 const struct sip_product *sip; 545 546 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 547 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 548 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 549 return (sip); 550 } 551 return (NULL); 552 } 553 554 #ifdef DP83820 555 /* 556 * I really hate stupid hardware vendors. There's a bit in the EEPROM 557 * which indicates if the card can do 64-bit data transfers. Unfortunately, 558 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 559 * which means we try to use 64-bit data transfers on those cards if we 560 * happen to be plugged into a 32-bit slot. 561 * 562 * What we do is use this table of cards known to be 64-bit cards. If 563 * you have a 64-bit card who's subsystem ID is not listed in this table, 564 * send the output of "pcictl dump ..." of the device to me so that your 565 * card will use the 64-bit data path when plugged into a 64-bit slot. 566 * 567 * -- Jason R. Thorpe <thorpej (at) netbsd.org> 568 * June 30, 2002 569 */ 570 static int 571 SIP_DECL(check_64bit)(const struct pci_attach_args *pa) 572 { 573 static const struct { 574 pci_vendor_id_t c64_vendor; 575 pci_product_id_t c64_product; 576 } card64[] = { 577 /* Asante GigaNIX */ 578 { 0x128a, 0x0002 }, 579 580 /* Accton EN1407-T, Planex GN-1000TE */ 581 { 0x1113, 0x1407 }, 582 583 { 0, 0} 584 }; 585 pcireg_t subsys; 586 int i; 587 588 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 589 590 for (i = 0; card64[i].c64_vendor != 0; i++) { 591 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 592 PCI_PRODUCT(subsys) == card64[i].c64_product) 593 return (1); 594 } 595 596 return (0); 597 } 598 #endif /* DP83820 */ 599 600 int 601 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 602 { 603 struct pci_attach_args *pa = aux; 604 605 if (SIP_DECL(lookup)(pa) != NULL) 606 return (1); 607 608 return (0); 609 } 610 611 void 612 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 613 { 614 struct sip_softc *sc = (struct sip_softc *) self; 615 struct pci_attach_args *pa = aux; 616 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 617 pci_chipset_tag_t pc = pa->pa_pc; 618 pci_intr_handle_t ih; 619 const char *intrstr = NULL; 620 bus_space_tag_t iot, memt; 621 bus_space_handle_t ioh, memh; 622 bus_dma_segment_t seg; 623 int ioh_valid, memh_valid; 624 int i, rseg, error; 625 const struct sip_product *sip; 626 pcireg_t pmode; 627 u_int8_t enaddr[ETHER_ADDR_LEN]; 628 int pmreg; 629 #ifdef DP83820 630 pcireg_t memtype; 631 u_int32_t reg; 632 #endif /* DP83820 */ 633 634 callout_init(&sc->sc_tick_ch); 635 636 sip = SIP_DECL(lookup)(pa); 637 if (sip == NULL) { 638 printf("\n"); 639 panic(SIP_STR(attach) ": impossible"); 640 } 641 sc->sc_rev = PCI_REVISION(pa->pa_class); 642 643 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 644 645 sc->sc_model = sip; 646 647 /* 648 * XXX Work-around broken PXE firmware on some boards. 649 * 650 * The DP83815 shares an address decoder with the MEM BAR 651 * and the ROM BAR. Make sure the ROM BAR is disabled, 652 * so that memory mapped access works. 653 */ 654 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 655 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 656 ~PCI_MAPREG_ROM_ENABLE); 657 658 /* 659 * Map the device. 660 */ 661 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 662 PCI_MAPREG_TYPE_IO, 0, 663 &iot, &ioh, NULL, NULL) == 0); 664 #ifdef DP83820 665 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 666 switch (memtype) { 667 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 668 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 669 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 670 memtype, 0, &memt, &memh, NULL, NULL) == 0); 671 break; 672 default: 673 memh_valid = 0; 674 } 675 #else 676 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 677 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 678 &memt, &memh, NULL, NULL) == 0); 679 #endif /* DP83820 */ 680 681 if (memh_valid) { 682 sc->sc_st = memt; 683 sc->sc_sh = memh; 684 } else if (ioh_valid) { 685 sc->sc_st = iot; 686 sc->sc_sh = ioh; 687 } else { 688 printf("%s: unable to map device registers\n", 689 sc->sc_dev.dv_xname); 690 return; 691 } 692 693 sc->sc_dmat = pa->pa_dmat; 694 695 /* 696 * Make sure bus mastering is enabled. Also make sure 697 * Write/Invalidate is enabled if we're allowed to use it. 698 */ 699 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 700 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 701 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 702 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 703 pmreg | PCI_COMMAND_MASTER_ENABLE); 704 705 /* Get it out of power save mode if needed. */ 706 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 707 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 708 if (pmode == 3) { 709 /* 710 * The card has lost all configuration data in 711 * this state, so punt. 712 */ 713 printf("%s: unable to wake up from power state D3\n", 714 sc->sc_dev.dv_xname); 715 return; 716 } 717 if (pmode != 0) { 718 printf("%s: waking up from power state D%d\n", 719 sc->sc_dev.dv_xname, pmode); 720 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 721 } 722 } 723 724 /* 725 * Map and establish our interrupt. 726 */ 727 if (pci_intr_map(pa, &ih)) { 728 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 729 return; 730 } 731 intrstr = pci_intr_string(pc, ih); 732 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 733 if (sc->sc_ih == NULL) { 734 printf("%s: unable to establish interrupt", 735 sc->sc_dev.dv_xname); 736 if (intrstr != NULL) 737 printf(" at %s", intrstr); 738 printf("\n"); 739 return; 740 } 741 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 742 743 SIMPLEQ_INIT(&sc->sc_txfreeq); 744 SIMPLEQ_INIT(&sc->sc_txdirtyq); 745 746 /* 747 * Allocate the control data structures, and create and load the 748 * DMA map for it. 749 */ 750 if ((error = bus_dmamem_alloc(sc->sc_dmat, 751 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 752 0)) != 0) { 753 printf("%s: unable to allocate control data, error = %d\n", 754 sc->sc_dev.dv_xname, error); 755 goto fail_0; 756 } 757 758 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 759 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 760 BUS_DMA_COHERENT)) != 0) { 761 printf("%s: unable to map control data, error = %d\n", 762 sc->sc_dev.dv_xname, error); 763 goto fail_1; 764 } 765 766 if ((error = bus_dmamap_create(sc->sc_dmat, 767 sizeof(struct sip_control_data), 1, 768 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 769 printf("%s: unable to create control data DMA map, " 770 "error = %d\n", sc->sc_dev.dv_xname, error); 771 goto fail_2; 772 } 773 774 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 775 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 776 0)) != 0) { 777 printf("%s: unable to load control data DMA map, error = %d\n", 778 sc->sc_dev.dv_xname, error); 779 goto fail_3; 780 } 781 782 /* 783 * Create the transmit buffer DMA maps. 784 */ 785 for (i = 0; i < SIP_TXQUEUELEN; i++) { 786 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 787 SIP_NTXSEGS, MCLBYTES, 0, 0, 788 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 789 printf("%s: unable to create tx DMA map %d, " 790 "error = %d\n", sc->sc_dev.dv_xname, i, error); 791 goto fail_4; 792 } 793 } 794 795 /* 796 * Create the receive buffer DMA maps. 797 */ 798 for (i = 0; i < SIP_NRXDESC; i++) { 799 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 800 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 801 printf("%s: unable to create rx DMA map %d, " 802 "error = %d\n", sc->sc_dev.dv_xname, i, error); 803 goto fail_5; 804 } 805 sc->sc_rxsoft[i].rxs_mbuf = NULL; 806 } 807 808 /* 809 * Reset the chip to a known state. 810 */ 811 SIP_DECL(reset)(sc); 812 813 /* 814 * Read the Ethernet address from the EEPROM. This might 815 * also fetch other stuff from the EEPROM and stash it 816 * in the softc. 817 */ 818 sc->sc_cfg = 0; 819 #if !defined(DP83820) 820 if (SIP_SIS900_REV(sc,SIS_REV_635) || 821 SIP_SIS900_REV(sc,SIS_REV_900B)) 822 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 823 #endif 824 825 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 826 827 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 828 ether_sprintf(enaddr)); 829 830 /* 831 * Initialize the configuration register: aggressive PCI 832 * bus request algorithm, default backoff, default OW timer, 833 * default parity error detection. 834 * 835 * NOTE: "Big endian mode" is useless on the SiS900 and 836 * friends -- it affects packet data, not descriptors. 837 */ 838 #ifdef DP83820 839 /* 840 * Cause the chip to load configuration data from the EEPROM. 841 */ 842 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 843 for (i = 0; i < 10000; i++) { 844 delay(10); 845 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 846 PTSCR_EELOAD_EN) == 0) 847 break; 848 } 849 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 850 PTSCR_EELOAD_EN) { 851 printf("%s: timeout loading configuration from EEPROM\n", 852 sc->sc_dev.dv_xname); 853 return; 854 } 855 856 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 857 if (reg & CFG_PCI64_DET) { 858 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 859 /* 860 * Check to see if this card is 64-bit. If so, enable 64-bit 861 * data transfers. 862 * 863 * We can't use the DATA64_EN bit in the EEPROM, because 864 * vendors of 32-bit cards fail to clear that bit in many 865 * cases (yet the card still detects that it's in a 64-bit 866 * slot; go figure). 867 */ 868 if (SIP_DECL(check_64bit)(pa)) { 869 sc->sc_cfg |= CFG_DATA64_EN; 870 printf(", using 64-bit data transfers"); 871 } 872 printf("\n"); 873 } 874 875 /* 876 * XXX Need some PCI flags indicating support for 877 * XXX 64-bit addressing. 878 */ 879 #if 0 880 if (reg & CFG_M64ADDR) 881 sc->sc_cfg |= CFG_M64ADDR; 882 if (reg & CFG_T64ADDR) 883 sc->sc_cfg |= CFG_T64ADDR; 884 #endif 885 886 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 887 const char *sep = ""; 888 printf("%s: using ", sc->sc_dev.dv_xname); 889 if (reg & CFG_EXT_125) { 890 sc->sc_cfg |= CFG_EXT_125; 891 printf("%s125MHz clock", sep); 892 sep = ", "; 893 } 894 if (reg & CFG_TBI_EN) { 895 sc->sc_cfg |= CFG_TBI_EN; 896 printf("%sten-bit interface", sep); 897 sep = ", "; 898 } 899 printf("\n"); 900 } 901 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 902 (reg & CFG_MRM_DIS) != 0) 903 sc->sc_cfg |= CFG_MRM_DIS; 904 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 905 (reg & CFG_MWI_DIS) != 0) 906 sc->sc_cfg |= CFG_MWI_DIS; 907 908 /* 909 * Use the extended descriptor format on the DP83820. This 910 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 911 * checksumming. 912 */ 913 sc->sc_cfg |= CFG_EXTSTS_EN; 914 #endif /* DP83820 */ 915 916 /* 917 * Initialize our media structures and probe the MII. 918 */ 919 sc->sc_mii.mii_ifp = ifp; 920 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 921 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 922 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 923 ifmedia_init(&sc->sc_mii.mii_media, 0, SIP_DECL(mediachange), 924 SIP_DECL(mediastatus)); 925 #ifdef DP83820 926 if (sc->sc_cfg & CFG_TBI_EN) { 927 /* Using ten-bit interface. */ 928 printf("%s: TBI -- FIXME\n", sc->sc_dev.dv_xname); 929 } else { 930 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 931 MII_OFFSET_ANY, 0); 932 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 933 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 934 0, NULL); 935 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 936 } else 937 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 938 } 939 #else 940 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 941 MII_OFFSET_ANY, 0); 942 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 943 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 944 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 945 } else 946 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 947 #endif /* DP83820 */ 948 949 ifp = &sc->sc_ethercom.ec_if; 950 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 951 ifp->if_softc = sc; 952 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 953 ifp->if_ioctl = SIP_DECL(ioctl); 954 ifp->if_start = SIP_DECL(start); 955 ifp->if_watchdog = SIP_DECL(watchdog); 956 ifp->if_init = SIP_DECL(init); 957 ifp->if_stop = SIP_DECL(stop); 958 IFQ_SET_READY(&ifp->if_snd); 959 960 /* 961 * We can support 802.1Q VLAN-sized frames. 962 */ 963 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 964 965 #ifdef DP83820 966 /* 967 * And the DP83820 can do VLAN tagging in hardware, and 968 * support the jumbo Ethernet MTU. 969 */ 970 sc->sc_ethercom.ec_capabilities |= 971 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 972 973 /* 974 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 975 * in hardware. 976 */ 977 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 978 IFCAP_CSUM_UDPv4; 979 #endif /* DP83820 */ 980 981 /* 982 * Attach the interface. 983 */ 984 if_attach(ifp); 985 ether_ifattach(ifp, enaddr); 986 987 /* 988 * The number of bytes that must be available in 989 * the Tx FIFO before the bus master can DMA more 990 * data into the FIFO. 991 */ 992 sc->sc_tx_fill_thresh = 64 / 32; 993 994 /* 995 * Start at a drain threshold of 512 bytes. We will 996 * increase it if a DMA underrun occurs. 997 * 998 * XXX The minimum value of this variable should be 999 * tuned. We may be able to improve performance 1000 * by starting with a lower value. That, however, 1001 * may trash the first few outgoing packets if the 1002 * PCI bus is saturated. 1003 */ 1004 sc->sc_tx_drain_thresh = 1504 / 32; 1005 1006 /* 1007 * Initialize the Rx FIFO drain threshold. 1008 * 1009 * This is in units of 8 bytes. 1010 * 1011 * We should never set this value lower than 2; 14 bytes are 1012 * required to filter the packet. 1013 */ 1014 sc->sc_rx_drain_thresh = 128 / 8; 1015 1016 #ifdef SIP_EVENT_COUNTERS 1017 /* 1018 * Attach event counters. 1019 */ 1020 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1021 NULL, sc->sc_dev.dv_xname, "txsstall"); 1022 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1023 NULL, sc->sc_dev.dv_xname, "txdstall"); 1024 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1025 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1026 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1027 NULL, sc->sc_dev.dv_xname, "txdintr"); 1028 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1029 NULL, sc->sc_dev.dv_xname, "txiintr"); 1030 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1031 NULL, sc->sc_dev.dv_xname, "rxintr"); 1032 #ifdef DP83820 1033 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1034 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1035 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1036 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1037 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1038 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1039 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1040 NULL, sc->sc_dev.dv_xname, "txipsum"); 1041 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1042 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1043 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1044 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1045 #endif /* DP83820 */ 1046 #endif /* SIP_EVENT_COUNTERS */ 1047 1048 /* 1049 * Make sure the interface is shutdown during reboot. 1050 */ 1051 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 1052 if (sc->sc_sdhook == NULL) 1053 printf("%s: WARNING: unable to establish shutdown hook\n", 1054 sc->sc_dev.dv_xname); 1055 return; 1056 1057 /* 1058 * Free any resources we've allocated during the failed attach 1059 * attempt. Do this in reverse order and fall through. 1060 */ 1061 fail_5: 1062 for (i = 0; i < SIP_NRXDESC; i++) { 1063 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1064 bus_dmamap_destroy(sc->sc_dmat, 1065 sc->sc_rxsoft[i].rxs_dmamap); 1066 } 1067 fail_4: 1068 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1069 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1070 bus_dmamap_destroy(sc->sc_dmat, 1071 sc->sc_txsoft[i].txs_dmamap); 1072 } 1073 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1074 fail_3: 1075 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1076 fail_2: 1077 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1078 sizeof(struct sip_control_data)); 1079 fail_1: 1080 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1081 fail_0: 1082 return; 1083 } 1084 1085 /* 1086 * sip_shutdown: 1087 * 1088 * Make sure the interface is stopped at reboot time. 1089 */ 1090 void 1091 SIP_DECL(shutdown)(void *arg) 1092 { 1093 struct sip_softc *sc = arg; 1094 1095 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1096 } 1097 1098 /* 1099 * sip_start: [ifnet interface function] 1100 * 1101 * Start packet transmission on the interface. 1102 */ 1103 void 1104 SIP_DECL(start)(struct ifnet *ifp) 1105 { 1106 struct sip_softc *sc = ifp->if_softc; 1107 struct mbuf *m0, *m; 1108 struct sip_txsoft *txs; 1109 bus_dmamap_t dmamap; 1110 int error, nexttx, lasttx, seg; 1111 int ofree = sc->sc_txfree; 1112 #if 0 1113 int firsttx = sc->sc_txnext; 1114 #endif 1115 #ifdef DP83820 1116 u_int32_t extsts; 1117 #endif 1118 1119 /* 1120 * If we've been told to pause, don't transmit any more packets. 1121 */ 1122 if (sc->sc_flags & SIPF_PAUSED) 1123 ifp->if_flags |= IFF_OACTIVE; 1124 1125 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1126 return; 1127 1128 /* 1129 * Loop through the send queue, setting up transmit descriptors 1130 * until we drain the queue, or use up all available transmit 1131 * descriptors. 1132 */ 1133 for (;;) { 1134 /* Get a work queue entry. */ 1135 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1136 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1137 break; 1138 } 1139 1140 /* 1141 * Grab a packet off the queue. 1142 */ 1143 IFQ_POLL(&ifp->if_snd, m0); 1144 if (m0 == NULL) 1145 break; 1146 #ifndef DP83820 1147 m = NULL; 1148 #endif 1149 1150 dmamap = txs->txs_dmamap; 1151 1152 #ifdef DP83820 1153 /* 1154 * Load the DMA map. If this fails, the packet either 1155 * didn't fit in the allotted number of segments, or we 1156 * were short on resources. For the too-many-segments 1157 * case, we simply report an error and drop the packet, 1158 * since we can't sanely copy a jumbo packet to a single 1159 * buffer. 1160 */ 1161 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1162 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1163 if (error) { 1164 if (error == EFBIG) { 1165 printf("%s: Tx packet consumes too many " 1166 "DMA segments, dropping...\n", 1167 sc->sc_dev.dv_xname); 1168 IFQ_DEQUEUE(&ifp->if_snd, m0); 1169 m_freem(m0); 1170 continue; 1171 } 1172 /* 1173 * Short on resources, just stop for now. 1174 */ 1175 break; 1176 } 1177 #else /* DP83820 */ 1178 /* 1179 * Load the DMA map. If this fails, the packet either 1180 * didn't fit in the alloted number of segments, or we 1181 * were short on resources. In this case, we'll copy 1182 * and try again. 1183 */ 1184 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1185 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1186 MGETHDR(m, M_DONTWAIT, MT_DATA); 1187 if (m == NULL) { 1188 printf("%s: unable to allocate Tx mbuf\n", 1189 sc->sc_dev.dv_xname); 1190 break; 1191 } 1192 if (m0->m_pkthdr.len > MHLEN) { 1193 MCLGET(m, M_DONTWAIT); 1194 if ((m->m_flags & M_EXT) == 0) { 1195 printf("%s: unable to allocate Tx " 1196 "cluster\n", sc->sc_dev.dv_xname); 1197 m_freem(m); 1198 break; 1199 } 1200 } 1201 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1202 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1203 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1204 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1205 if (error) { 1206 printf("%s: unable to load Tx buffer, " 1207 "error = %d\n", sc->sc_dev.dv_xname, error); 1208 break; 1209 } 1210 } 1211 #endif /* DP83820 */ 1212 1213 /* 1214 * Ensure we have enough descriptors free to describe 1215 * the packet. Note, we always reserve one descriptor 1216 * at the end of the ring as a termination point, to 1217 * prevent wrap-around. 1218 */ 1219 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1220 /* 1221 * Not enough free descriptors to transmit this 1222 * packet. We haven't committed anything yet, 1223 * so just unload the DMA map, put the packet 1224 * back on the queue, and punt. Notify the upper 1225 * layer that there are not more slots left. 1226 * 1227 * XXX We could allocate an mbuf and copy, but 1228 * XXX is it worth it? 1229 */ 1230 ifp->if_flags |= IFF_OACTIVE; 1231 bus_dmamap_unload(sc->sc_dmat, dmamap); 1232 #ifndef DP83820 1233 if (m != NULL) 1234 m_freem(m); 1235 #endif 1236 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1237 break; 1238 } 1239 1240 IFQ_DEQUEUE(&ifp->if_snd, m0); 1241 #ifndef DP83820 1242 if (m != NULL) { 1243 m_freem(m0); 1244 m0 = m; 1245 } 1246 #endif 1247 1248 /* 1249 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1250 */ 1251 1252 /* Sync the DMA map. */ 1253 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1254 BUS_DMASYNC_PREWRITE); 1255 1256 /* 1257 * Initialize the transmit descriptors. 1258 */ 1259 for (nexttx = sc->sc_txnext, seg = 0; 1260 seg < dmamap->dm_nsegs; 1261 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1262 /* 1263 * If this is the first descriptor we're 1264 * enqueueing, don't set the OWN bit just 1265 * yet. That could cause a race condition. 1266 * We'll do it below. 1267 */ 1268 sc->sc_txdescs[nexttx].sipd_bufptr = 1269 htole32(dmamap->dm_segs[seg].ds_addr); 1270 sc->sc_txdescs[nexttx].sipd_cmdsts = 1271 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1272 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1273 #ifdef DP83820 1274 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1275 #endif /* DP83820 */ 1276 lasttx = nexttx; 1277 } 1278 1279 /* Clear the MORE bit on the last segment. */ 1280 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1281 1282 /* 1283 * If we're in the interrupt delay window, delay the 1284 * interrupt. 1285 */ 1286 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1287 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1288 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1289 htole32(CMDSTS_INTR); 1290 sc->sc_txwin = 0; 1291 } 1292 1293 #ifdef DP83820 1294 /* 1295 * If VLANs are enabled and the packet has a VLAN tag, set 1296 * up the descriptor to encapsulate the packet for us. 1297 * 1298 * This apparently has to be on the last descriptor of 1299 * the packet. 1300 */ 1301 if (sc->sc_ethercom.ec_nvlans != 0 && 1302 (m = m_aux_find(m0, AF_LINK, ETHERTYPE_VLAN)) != NULL) { 1303 sc->sc_txdescs[lasttx].sipd_extsts |= 1304 htole32(EXTSTS_VPKT | 1305 htons(*mtod(m, int *) & EXTSTS_VTCI)); 1306 } 1307 1308 /* 1309 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1310 * checksumming, set up the descriptor to do this work 1311 * for us. 1312 * 1313 * This apparently has to be on the first descriptor of 1314 * the packet. 1315 * 1316 * Byte-swap constants so the compiler can optimize. 1317 */ 1318 extsts = 0; 1319 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1320 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1321 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1322 extsts |= htole32(EXTSTS_IPPKT); 1323 } 1324 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1325 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1326 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1327 extsts |= htole32(EXTSTS_TCPPKT); 1328 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1329 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1330 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1331 extsts |= htole32(EXTSTS_UDPPKT); 1332 } 1333 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1334 #endif /* DP83820 */ 1335 1336 /* Sync the descriptors we're using. */ 1337 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1338 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1339 1340 /* 1341 * The entire packet is set up. Give the first descrptor 1342 * to the chip now. 1343 */ 1344 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1345 htole32(CMDSTS_OWN); 1346 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1347 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1348 1349 /* 1350 * Store a pointer to the packet so we can free it later, 1351 * and remember what txdirty will be once the packet is 1352 * done. 1353 */ 1354 txs->txs_mbuf = m0; 1355 txs->txs_firstdesc = sc->sc_txnext; 1356 txs->txs_lastdesc = lasttx; 1357 1358 /* Advance the tx pointer. */ 1359 sc->sc_txfree -= dmamap->dm_nsegs; 1360 sc->sc_txnext = nexttx; 1361 1362 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1363 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1364 1365 #if NBPFILTER > 0 1366 /* 1367 * Pass the packet to any BPF listeners. 1368 */ 1369 if (ifp->if_bpf) 1370 bpf_mtap(ifp->if_bpf, m0); 1371 #endif /* NBPFILTER > 0 */ 1372 } 1373 1374 if (txs == NULL || sc->sc_txfree == 0) { 1375 /* No more slots left; notify upper layer. */ 1376 ifp->if_flags |= IFF_OACTIVE; 1377 } 1378 1379 if (sc->sc_txfree != ofree) { 1380 /* 1381 * Start the transmit process. Note, the manual says 1382 * that if there are no pending transmissions in the 1383 * chip's internal queue (indicated by TXE being clear), 1384 * then the driver software must set the TXDP to the 1385 * first descriptor to be transmitted. However, if we 1386 * do this, it causes serious performance degredation on 1387 * the DP83820 under load, not setting TXDP doesn't seem 1388 * to adversely affect the SiS 900 or DP83815. 1389 * 1390 * Well, I guess it wouldn't be the first time a manual 1391 * has lied -- and they could be speaking of the NULL- 1392 * terminated descriptor list case, rather than OWN- 1393 * terminated rings. 1394 */ 1395 #if 0 1396 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1397 CR_TXE) == 0) { 1398 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1399 SIP_CDTXADDR(sc, firsttx)); 1400 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1401 } 1402 #else 1403 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1404 #endif 1405 1406 /* Set a watchdog timer in case the chip flakes out. */ 1407 ifp->if_timer = 5; 1408 } 1409 } 1410 1411 /* 1412 * sip_watchdog: [ifnet interface function] 1413 * 1414 * Watchdog timer handler. 1415 */ 1416 void 1417 SIP_DECL(watchdog)(struct ifnet *ifp) 1418 { 1419 struct sip_softc *sc = ifp->if_softc; 1420 1421 /* 1422 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1423 * If we get a timeout, try and sweep up transmit descriptors. 1424 * If we manage to sweep them all up, ignore the lack of 1425 * interrupt. 1426 */ 1427 SIP_DECL(txintr)(sc); 1428 1429 if (sc->sc_txfree != SIP_NTXDESC) { 1430 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1431 ifp->if_oerrors++; 1432 1433 /* Reset the interface. */ 1434 (void) SIP_DECL(init)(ifp); 1435 } else if (ifp->if_flags & IFF_DEBUG) 1436 printf("%s: recovered from device timeout\n", 1437 sc->sc_dev.dv_xname); 1438 1439 /* Try to get more packets going. */ 1440 SIP_DECL(start)(ifp); 1441 } 1442 1443 /* 1444 * sip_ioctl: [ifnet interface function] 1445 * 1446 * Handle control requests from the operator. 1447 */ 1448 int 1449 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1450 { 1451 struct sip_softc *sc = ifp->if_softc; 1452 struct ifreq *ifr = (struct ifreq *)data; 1453 int s, error; 1454 1455 s = splnet(); 1456 1457 switch (cmd) { 1458 case SIOCSIFMEDIA: 1459 case SIOCGIFMEDIA: 1460 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1461 break; 1462 1463 default: 1464 error = ether_ioctl(ifp, cmd, data); 1465 if (error == ENETRESET) { 1466 /* 1467 * Multicast list has changed; set the hardware filter 1468 * accordingly. 1469 */ 1470 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1471 error = 0; 1472 } 1473 break; 1474 } 1475 1476 /* Try to get more packets going. */ 1477 SIP_DECL(start)(ifp); 1478 1479 splx(s); 1480 return (error); 1481 } 1482 1483 /* 1484 * sip_intr: 1485 * 1486 * Interrupt service routine. 1487 */ 1488 int 1489 SIP_DECL(intr)(void *arg) 1490 { 1491 struct sip_softc *sc = arg; 1492 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1493 u_int32_t isr; 1494 int handled = 0; 1495 1496 for (;;) { 1497 /* Reading clears interrupt. */ 1498 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1499 if ((isr & sc->sc_imr) == 0) 1500 break; 1501 1502 handled = 1; 1503 1504 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1505 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1506 1507 /* Grab any new packets. */ 1508 SIP_DECL(rxintr)(sc); 1509 1510 if (isr & ISR_RXORN) { 1511 printf("%s: receive FIFO overrun\n", 1512 sc->sc_dev.dv_xname); 1513 1514 /* XXX adjust rx_drain_thresh? */ 1515 } 1516 1517 if (isr & ISR_RXIDLE) { 1518 printf("%s: receive ring overrun\n", 1519 sc->sc_dev.dv_xname); 1520 1521 /* Get the receive process going again. */ 1522 bus_space_write_4(sc->sc_st, sc->sc_sh, 1523 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1524 bus_space_write_4(sc->sc_st, sc->sc_sh, 1525 SIP_CR, CR_RXE); 1526 } 1527 } 1528 1529 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1530 #ifdef SIP_EVENT_COUNTERS 1531 if (isr & ISR_TXDESC) 1532 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1533 else if (isr & ISR_TXIDLE) 1534 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1535 #endif 1536 1537 /* Sweep up transmit descriptors. */ 1538 SIP_DECL(txintr)(sc); 1539 1540 if (isr & ISR_TXURN) { 1541 u_int32_t thresh; 1542 1543 printf("%s: transmit FIFO underrun", 1544 sc->sc_dev.dv_xname); 1545 1546 thresh = sc->sc_tx_drain_thresh + 1; 1547 if (thresh <= TXCFG_DRTH && 1548 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1549 (sc->sc_tx_fill_thresh * 32))) { 1550 printf("; increasing Tx drain " 1551 "threshold to %u bytes\n", 1552 thresh * 32); 1553 sc->sc_tx_drain_thresh = thresh; 1554 (void) SIP_DECL(init)(ifp); 1555 } else { 1556 (void) SIP_DECL(init)(ifp); 1557 printf("\n"); 1558 } 1559 } 1560 } 1561 1562 #if !defined(DP83820) 1563 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1564 if (isr & ISR_PAUSE_ST) { 1565 sc->sc_flags |= SIPF_PAUSED; 1566 ifp->if_flags |= IFF_OACTIVE; 1567 } 1568 if (isr & ISR_PAUSE_END) { 1569 sc->sc_flags &= ~SIPF_PAUSED; 1570 ifp->if_flags &= ~IFF_OACTIVE; 1571 } 1572 } 1573 #endif /* ! DP83820 */ 1574 1575 if (isr & ISR_HIBERR) { 1576 #define PRINTERR(bit, str) \ 1577 if (isr & (bit)) \ 1578 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1579 PRINTERR(ISR_DPERR, "parity error"); 1580 PRINTERR(ISR_SSERR, "system error"); 1581 PRINTERR(ISR_RMABT, "master abort"); 1582 PRINTERR(ISR_RTABT, "target abort"); 1583 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1584 (void) SIP_DECL(init)(ifp); 1585 #undef PRINTERR 1586 } 1587 } 1588 1589 /* Try to get more packets going. */ 1590 SIP_DECL(start)(ifp); 1591 1592 return (handled); 1593 } 1594 1595 /* 1596 * sip_txintr: 1597 * 1598 * Helper; handle transmit interrupts. 1599 */ 1600 void 1601 SIP_DECL(txintr)(struct sip_softc *sc) 1602 { 1603 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1604 struct sip_txsoft *txs; 1605 u_int32_t cmdsts; 1606 1607 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1608 ifp->if_flags &= ~IFF_OACTIVE; 1609 1610 /* 1611 * Go through our Tx list and free mbufs for those 1612 * frames which have been transmitted. 1613 */ 1614 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1615 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1616 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1617 1618 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1619 if (cmdsts & CMDSTS_OWN) 1620 break; 1621 1622 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1623 1624 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1625 1626 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1627 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1628 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1629 m_freem(txs->txs_mbuf); 1630 txs->txs_mbuf = NULL; 1631 1632 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1633 1634 /* 1635 * Check for errors and collisions. 1636 */ 1637 if (cmdsts & 1638 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1639 ifp->if_oerrors++; 1640 if (cmdsts & CMDSTS_Tx_EC) 1641 ifp->if_collisions += 16; 1642 if (ifp->if_flags & IFF_DEBUG) { 1643 if (cmdsts & CMDSTS_Tx_ED) 1644 printf("%s: excessive deferral\n", 1645 sc->sc_dev.dv_xname); 1646 if (cmdsts & CMDSTS_Tx_EC) 1647 printf("%s: excessive collisions\n", 1648 sc->sc_dev.dv_xname); 1649 } 1650 } else { 1651 /* Packet was transmitted successfully. */ 1652 ifp->if_opackets++; 1653 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1654 } 1655 } 1656 1657 /* 1658 * If there are no more pending transmissions, cancel the watchdog 1659 * timer. 1660 */ 1661 if (txs == NULL) { 1662 ifp->if_timer = 0; 1663 sc->sc_txwin = 0; 1664 } 1665 } 1666 1667 #if defined(DP83820) 1668 /* 1669 * sip_rxintr: 1670 * 1671 * Helper; handle receive interrupts. 1672 */ 1673 void 1674 SIP_DECL(rxintr)(struct sip_softc *sc) 1675 { 1676 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1677 struct sip_rxsoft *rxs; 1678 struct mbuf *m, *tailm; 1679 u_int32_t cmdsts, extsts; 1680 int i, len; 1681 1682 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1683 rxs = &sc->sc_rxsoft[i]; 1684 1685 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1686 1687 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1688 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1689 1690 /* 1691 * NOTE: OWN is set if owned by _consumer_. We're the 1692 * consumer of the receive ring, so if the bit is clear, 1693 * we have processed all of the packets. 1694 */ 1695 if ((cmdsts & CMDSTS_OWN) == 0) { 1696 /* 1697 * We have processed all of the receive buffers. 1698 */ 1699 break; 1700 } 1701 1702 if (__predict_false(sc->sc_rxdiscard)) { 1703 SIP_INIT_RXDESC(sc, i); 1704 if ((cmdsts & CMDSTS_MORE) == 0) { 1705 /* Reset our state. */ 1706 sc->sc_rxdiscard = 0; 1707 } 1708 continue; 1709 } 1710 1711 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1712 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1713 1714 m = rxs->rxs_mbuf; 1715 1716 /* 1717 * Add a new receive buffer to the ring. 1718 */ 1719 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1720 /* 1721 * Failed, throw away what we've done so 1722 * far, and discard the rest of the packet. 1723 */ 1724 ifp->if_ierrors++; 1725 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1726 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1727 SIP_INIT_RXDESC(sc, i); 1728 if (cmdsts & CMDSTS_MORE) 1729 sc->sc_rxdiscard = 1; 1730 if (sc->sc_rxhead != NULL) 1731 m_freem(sc->sc_rxhead); 1732 SIP_RXCHAIN_RESET(sc); 1733 continue; 1734 } 1735 1736 SIP_RXCHAIN_LINK(sc, m); 1737 1738 /* 1739 * If this is not the end of the packet, keep 1740 * looking. 1741 */ 1742 if (cmdsts & CMDSTS_MORE) { 1743 sc->sc_rxlen += m->m_len; 1744 continue; 1745 } 1746 1747 /* 1748 * Okay, we have the entire packet now... 1749 */ 1750 *sc->sc_rxtailp = NULL; 1751 m = sc->sc_rxhead; 1752 tailm = sc->sc_rxtail; 1753 1754 SIP_RXCHAIN_RESET(sc); 1755 1756 /* 1757 * If an error occurred, update stats and drop the packet. 1758 */ 1759 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1760 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1761 ifp->if_ierrors++; 1762 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1763 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1764 /* Receive overrun handled elsewhere. */ 1765 printf("%s: receive descriptor error\n", 1766 sc->sc_dev.dv_xname); 1767 } 1768 #define PRINTERR(bit, str) \ 1769 if (cmdsts & (bit)) \ 1770 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1771 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1772 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1773 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1774 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1775 #undef PRINTERR 1776 m_freem(m); 1777 continue; 1778 } 1779 1780 /* 1781 * No errors. 1782 * 1783 * Note, the DP83820 includes the CRC with 1784 * every packet. 1785 */ 1786 len = CMDSTS_SIZE(cmdsts); 1787 tailm->m_len = len - sc->sc_rxlen; 1788 1789 /* 1790 * If the packet is small enough to fit in a 1791 * single header mbuf, allocate one and copy 1792 * the data into it. This greatly reduces 1793 * memory consumption when we receive lots 1794 * of small packets. 1795 */ 1796 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1797 struct mbuf *nm; 1798 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1799 if (nm == NULL) { 1800 ifp->if_ierrors++; 1801 m_freem(m); 1802 continue; 1803 } 1804 nm->m_data += 2; 1805 nm->m_pkthdr.len = nm->m_len = len; 1806 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1807 m_freem(m); 1808 m = nm; 1809 } 1810 #ifndef __NO_STRICT_ALIGNMENT 1811 else { 1812 /* 1813 * The DP83820's receive buffers must be 4-byte 1814 * aligned. But this means that the data after 1815 * the Ethernet header is misaligned. To compensate, 1816 * we have artificially shortened the buffer size 1817 * in the descriptor, and we do an overlapping copy 1818 * of the data two bytes further in (in the first 1819 * buffer of the chain only). 1820 */ 1821 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1822 m->m_len); 1823 m->m_data += 2; 1824 } 1825 #endif /* ! __NO_STRICT_ALIGNMENT */ 1826 1827 /* 1828 * If VLANs are enabled, VLAN packets have been unwrapped 1829 * for us. Associate the tag with the packet. 1830 */ 1831 if (sc->sc_ethercom.ec_nvlans != 0 && 1832 (extsts & EXTSTS_VPKT) != 0) { 1833 struct mbuf *vtag; 1834 1835 vtag = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 1836 if (vtag == NULL) { 1837 ifp->if_ierrors++; 1838 printf("%s: unable to allocate VLAN tag\n", 1839 sc->sc_dev.dv_xname); 1840 m_freem(m); 1841 continue; 1842 } 1843 1844 *mtod(vtag, int *) = ntohs(extsts & EXTSTS_VTCI); 1845 vtag->m_len = sizeof(int); 1846 } 1847 1848 /* 1849 * Set the incoming checksum information for the 1850 * packet. 1851 */ 1852 if ((extsts & EXTSTS_IPPKT) != 0) { 1853 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1854 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1855 if (extsts & EXTSTS_Rx_IPERR) 1856 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1857 if (extsts & EXTSTS_TCPPKT) { 1858 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1859 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1860 if (extsts & EXTSTS_Rx_TCPERR) 1861 m->m_pkthdr.csum_flags |= 1862 M_CSUM_TCP_UDP_BAD; 1863 } else if (extsts & EXTSTS_UDPPKT) { 1864 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1865 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1866 if (extsts & EXTSTS_Rx_UDPERR) 1867 m->m_pkthdr.csum_flags |= 1868 M_CSUM_TCP_UDP_BAD; 1869 } 1870 } 1871 1872 ifp->if_ipackets++; 1873 m->m_flags |= M_HASFCS; 1874 m->m_pkthdr.rcvif = ifp; 1875 m->m_pkthdr.len = len; 1876 1877 #if NBPFILTER > 0 1878 /* 1879 * Pass this up to any BPF listeners, but only 1880 * pass if up the stack if it's for us. 1881 */ 1882 if (ifp->if_bpf) 1883 bpf_mtap(ifp->if_bpf, m); 1884 #endif /* NBPFILTER > 0 */ 1885 1886 /* Pass it on. */ 1887 (*ifp->if_input)(ifp, m); 1888 } 1889 1890 /* Update the receive pointer. */ 1891 sc->sc_rxptr = i; 1892 } 1893 #else /* ! DP83820 */ 1894 /* 1895 * sip_rxintr: 1896 * 1897 * Helper; handle receive interrupts. 1898 */ 1899 void 1900 SIP_DECL(rxintr)(struct sip_softc *sc) 1901 { 1902 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1903 struct sip_rxsoft *rxs; 1904 struct mbuf *m; 1905 u_int32_t cmdsts; 1906 int i, len; 1907 1908 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1909 rxs = &sc->sc_rxsoft[i]; 1910 1911 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1912 1913 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1914 1915 /* 1916 * NOTE: OWN is set if owned by _consumer_. We're the 1917 * consumer of the receive ring, so if the bit is clear, 1918 * we have processed all of the packets. 1919 */ 1920 if ((cmdsts & CMDSTS_OWN) == 0) { 1921 /* 1922 * We have processed all of the receive buffers. 1923 */ 1924 break; 1925 } 1926 1927 /* 1928 * If any collisions were seen on the wire, count one. 1929 */ 1930 if (cmdsts & CMDSTS_Rx_COL) 1931 ifp->if_collisions++; 1932 1933 /* 1934 * If an error occurred, update stats, clear the status 1935 * word, and leave the packet buffer in place. It will 1936 * simply be reused the next time the ring comes around. 1937 */ 1938 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1939 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1940 ifp->if_ierrors++; 1941 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1942 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1943 /* Receive overrun handled elsewhere. */ 1944 printf("%s: receive descriptor error\n", 1945 sc->sc_dev.dv_xname); 1946 } 1947 #define PRINTERR(bit, str) \ 1948 if (cmdsts & (bit)) \ 1949 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1950 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1951 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1952 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1953 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1954 #undef PRINTERR 1955 SIP_INIT_RXDESC(sc, i); 1956 continue; 1957 } 1958 1959 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1960 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1961 1962 /* 1963 * No errors; receive the packet. Note, the SiS 900 1964 * includes the CRC with every packet. 1965 */ 1966 len = CMDSTS_SIZE(cmdsts); 1967 1968 #ifdef __NO_STRICT_ALIGNMENT 1969 /* 1970 * If the packet is small enough to fit in a 1971 * single header mbuf, allocate one and copy 1972 * the data into it. This greatly reduces 1973 * memory consumption when we receive lots 1974 * of small packets. 1975 * 1976 * Otherwise, we add a new buffer to the receive 1977 * chain. If this fails, we drop the packet and 1978 * recycle the old buffer. 1979 */ 1980 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 1981 MGETHDR(m, M_DONTWAIT, MT_DATA); 1982 if (m == NULL) 1983 goto dropit; 1984 memcpy(mtod(m, caddr_t), 1985 mtod(rxs->rxs_mbuf, caddr_t), len); 1986 SIP_INIT_RXDESC(sc, i); 1987 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1988 rxs->rxs_dmamap->dm_mapsize, 1989 BUS_DMASYNC_PREREAD); 1990 } else { 1991 m = rxs->rxs_mbuf; 1992 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1993 dropit: 1994 ifp->if_ierrors++; 1995 SIP_INIT_RXDESC(sc, i); 1996 bus_dmamap_sync(sc->sc_dmat, 1997 rxs->rxs_dmamap, 0, 1998 rxs->rxs_dmamap->dm_mapsize, 1999 BUS_DMASYNC_PREREAD); 2000 continue; 2001 } 2002 } 2003 #else 2004 /* 2005 * The SiS 900's receive buffers must be 4-byte aligned. 2006 * But this means that the data after the Ethernet header 2007 * is misaligned. We must allocate a new buffer and 2008 * copy the data, shifted forward 2 bytes. 2009 */ 2010 MGETHDR(m, M_DONTWAIT, MT_DATA); 2011 if (m == NULL) { 2012 dropit: 2013 ifp->if_ierrors++; 2014 SIP_INIT_RXDESC(sc, i); 2015 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2016 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2017 continue; 2018 } 2019 if (len > (MHLEN - 2)) { 2020 MCLGET(m, M_DONTWAIT); 2021 if ((m->m_flags & M_EXT) == 0) { 2022 m_freem(m); 2023 goto dropit; 2024 } 2025 } 2026 m->m_data += 2; 2027 2028 /* 2029 * Note that we use clusters for incoming frames, so the 2030 * buffer is virtually contiguous. 2031 */ 2032 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 2033 2034 /* Allow the receive descriptor to continue using its mbuf. */ 2035 SIP_INIT_RXDESC(sc, i); 2036 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2037 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2038 #endif /* __NO_STRICT_ALIGNMENT */ 2039 2040 ifp->if_ipackets++; 2041 m->m_flags |= M_HASFCS; 2042 m->m_pkthdr.rcvif = ifp; 2043 m->m_pkthdr.len = m->m_len = len; 2044 2045 #if NBPFILTER > 0 2046 /* 2047 * Pass this up to any BPF listeners, but only 2048 * pass if up the stack if it's for us. 2049 */ 2050 if (ifp->if_bpf) 2051 bpf_mtap(ifp->if_bpf, m); 2052 #endif /* NBPFILTER > 0 */ 2053 2054 /* Pass it on. */ 2055 (*ifp->if_input)(ifp, m); 2056 } 2057 2058 /* Update the receive pointer. */ 2059 sc->sc_rxptr = i; 2060 } 2061 #endif /* DP83820 */ 2062 2063 /* 2064 * sip_tick: 2065 * 2066 * One second timer, used to tick the MII. 2067 */ 2068 void 2069 SIP_DECL(tick)(void *arg) 2070 { 2071 struct sip_softc *sc = arg; 2072 int s; 2073 2074 s = splnet(); 2075 mii_tick(&sc->sc_mii); 2076 splx(s); 2077 2078 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2079 } 2080 2081 /* 2082 * sip_reset: 2083 * 2084 * Perform a soft reset on the SiS 900. 2085 */ 2086 void 2087 SIP_DECL(reset)(struct sip_softc *sc) 2088 { 2089 bus_space_tag_t st = sc->sc_st; 2090 bus_space_handle_t sh = sc->sc_sh; 2091 int i; 2092 2093 bus_space_write_4(st, sh, SIP_IER, 0); 2094 bus_space_write_4(st, sh, SIP_IMR, 0); 2095 bus_space_write_4(st, sh, SIP_RFCR, 0); 2096 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2097 2098 for (i = 0; i < SIP_TIMEOUT; i++) { 2099 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2100 break; 2101 delay(2); 2102 } 2103 2104 if (i == SIP_TIMEOUT) 2105 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2106 2107 delay(1000); 2108 2109 #ifdef DP83820 2110 /* 2111 * Set the general purpose I/O bits. Do it here in case we 2112 * need to have GPIO set up to talk to the media interface. 2113 */ 2114 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2115 delay(1000); 2116 #endif /* DP83820 */ 2117 } 2118 2119 /* 2120 * sip_init: [ ifnet interface function ] 2121 * 2122 * Initialize the interface. Must be called at splnet(). 2123 */ 2124 int 2125 SIP_DECL(init)(struct ifnet *ifp) 2126 { 2127 struct sip_softc *sc = ifp->if_softc; 2128 bus_space_tag_t st = sc->sc_st; 2129 bus_space_handle_t sh = sc->sc_sh; 2130 struct sip_txsoft *txs; 2131 struct sip_rxsoft *rxs; 2132 struct sip_desc *sipd; 2133 u_int32_t reg; 2134 int i, error = 0; 2135 2136 /* 2137 * Cancel any pending I/O. 2138 */ 2139 SIP_DECL(stop)(ifp, 0); 2140 2141 /* 2142 * Reset the chip to a known state. 2143 */ 2144 SIP_DECL(reset)(sc); 2145 2146 #if !defined(DP83820) 2147 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2148 /* 2149 * DP83815 manual, page 78: 2150 * 4.4 Recommended Registers Configuration 2151 * For optimum performance of the DP83815, version noted 2152 * as DP83815CVNG (SRR = 203h), the listed register 2153 * modifications must be followed in sequence... 2154 * 2155 * It's not clear if this should be 302h or 203h because that 2156 * chip name is listed as SRR 302h in the description of the 2157 * SRR register. However, my revision 302h DP83815 on the 2158 * Netgear FA311 purchased in 02/2001 needs these settings 2159 * to avoid tons of errors in AcceptPerfectMatch (non- 2160 * IFF_PROMISC) mode. I do not know if other revisions need 2161 * this set or not. [briggs -- 09 March 2001] 2162 * 2163 * Note that only the low-order 12 bits of 0xe4 are documented 2164 * and that this sets reserved bits in that register. 2165 */ 2166 reg = bus_space_read_4(st, sh, SIP_NS_SRR); 2167 if (reg == 0x302) { 2168 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2169 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2170 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2171 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2172 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2173 } 2174 } 2175 #endif /* ! DP83820 */ 2176 2177 /* 2178 * Initialize the transmit descriptor ring. 2179 */ 2180 for (i = 0; i < SIP_NTXDESC; i++) { 2181 sipd = &sc->sc_txdescs[i]; 2182 memset(sipd, 0, sizeof(struct sip_desc)); 2183 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2184 } 2185 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2186 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2187 sc->sc_txfree = SIP_NTXDESC; 2188 sc->sc_txnext = 0; 2189 sc->sc_txwin = 0; 2190 2191 /* 2192 * Initialize the transmit job descriptors. 2193 */ 2194 SIMPLEQ_INIT(&sc->sc_txfreeq); 2195 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2196 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2197 txs = &sc->sc_txsoft[i]; 2198 txs->txs_mbuf = NULL; 2199 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2200 } 2201 2202 /* 2203 * Initialize the receive descriptor and receive job 2204 * descriptor rings. 2205 */ 2206 for (i = 0; i < SIP_NRXDESC; i++) { 2207 rxs = &sc->sc_rxsoft[i]; 2208 if (rxs->rxs_mbuf == NULL) { 2209 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2210 printf("%s: unable to allocate or map rx " 2211 "buffer %d, error = %d\n", 2212 sc->sc_dev.dv_xname, i, error); 2213 /* 2214 * XXX Should attempt to run with fewer receive 2215 * XXX buffers instead of just failing. 2216 */ 2217 SIP_DECL(rxdrain)(sc); 2218 goto out; 2219 } 2220 } else 2221 SIP_INIT_RXDESC(sc, i); 2222 } 2223 sc->sc_rxptr = 0; 2224 #ifdef DP83820 2225 sc->sc_rxdiscard = 0; 2226 SIP_RXCHAIN_RESET(sc); 2227 #endif /* DP83820 */ 2228 2229 /* 2230 * Set the configuration register; it's already initialized 2231 * in sip_attach(). 2232 */ 2233 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2234 2235 /* 2236 * Initialize the prototype TXCFG register. 2237 */ 2238 #if defined(DP83820) 2239 sc->sc_txcfg = TXCFG_MXDMA_512; 2240 sc->sc_rxcfg = RXCFG_MXDMA_512; 2241 #else 2242 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2243 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2244 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & CFG_EDBMASTEN)) { 2245 sc->sc_txcfg = TXCFG_MXDMA_64; 2246 sc->sc_rxcfg = RXCFG_MXDMA_64; 2247 } else { 2248 sc->sc_txcfg = TXCFG_MXDMA_512; 2249 sc->sc_rxcfg = RXCFG_MXDMA_512; 2250 } 2251 #endif /* DP83820 */ 2252 2253 sc->sc_txcfg |= TXCFG_ATP | 2254 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2255 sc->sc_tx_drain_thresh; 2256 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2257 2258 /* 2259 * Initialize the receive drain threshold if we have never 2260 * done so. 2261 */ 2262 if (sc->sc_rx_drain_thresh == 0) { 2263 /* 2264 * XXX This value should be tuned. This is set to the 2265 * maximum of 248 bytes, and we may be able to improve 2266 * performance by decreasing it (although we should never 2267 * set this value lower than 2; 14 bytes are required to 2268 * filter the packet). 2269 */ 2270 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2271 } 2272 2273 /* 2274 * Initialize the prototype RXCFG register. 2275 */ 2276 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2277 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2278 2279 #ifdef DP83820 2280 /* 2281 * Initialize the VLAN/IP receive control register. 2282 * We enable checksum computation on all incoming 2283 * packets, and do not reject packets w/ bad checksums. 2284 */ 2285 reg = 0; 2286 if (ifp->if_capenable & 2287 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2288 reg |= VRCR_IPEN; 2289 if (sc->sc_ethercom.ec_nvlans != 0) 2290 reg |= VRCR_VTDEN|VRCR_VTREN; 2291 bus_space_write_4(st, sh, SIP_VRCR, reg); 2292 2293 /* 2294 * Initialize the VLAN/IP transmit control register. 2295 * We enable outgoing checksum computation on a 2296 * per-packet basis. 2297 */ 2298 reg = 0; 2299 if (ifp->if_capenable & 2300 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2301 reg |= VTCR_PPCHK; 2302 if (sc->sc_ethercom.ec_nvlans != 0) 2303 reg |= VTCR_VPPTI; 2304 bus_space_write_4(st, sh, SIP_VTCR, reg); 2305 2306 /* 2307 * If we're using VLANs, initialize the VLAN data register. 2308 * To understand why we bswap the VLAN Ethertype, see section 2309 * 4.2.36 of the DP83820 manual. 2310 */ 2311 if (sc->sc_ethercom.ec_nvlans != 0) 2312 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2313 #endif /* DP83820 */ 2314 2315 /* 2316 * Give the transmit and receive rings to the chip. 2317 */ 2318 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2319 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2320 2321 /* 2322 * Initialize the interrupt mask. 2323 */ 2324 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2325 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2326 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2327 2328 /* Set up the receive filter. */ 2329 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2330 2331 /* 2332 * Set the current media. Do this after initializing the prototype 2333 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2334 * control. 2335 */ 2336 mii_mediachg(&sc->sc_mii); 2337 2338 /* 2339 * Enable interrupts. 2340 */ 2341 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2342 2343 /* 2344 * Start the transmit and receive processes. 2345 */ 2346 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2347 2348 /* 2349 * Start the one second MII clock. 2350 */ 2351 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2352 2353 /* 2354 * ...all done! 2355 */ 2356 ifp->if_flags |= IFF_RUNNING; 2357 ifp->if_flags &= ~IFF_OACTIVE; 2358 2359 out: 2360 if (error) 2361 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2362 return (error); 2363 } 2364 2365 /* 2366 * sip_drain: 2367 * 2368 * Drain the receive queue. 2369 */ 2370 void 2371 SIP_DECL(rxdrain)(struct sip_softc *sc) 2372 { 2373 struct sip_rxsoft *rxs; 2374 int i; 2375 2376 for (i = 0; i < SIP_NRXDESC; i++) { 2377 rxs = &sc->sc_rxsoft[i]; 2378 if (rxs->rxs_mbuf != NULL) { 2379 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2380 m_freem(rxs->rxs_mbuf); 2381 rxs->rxs_mbuf = NULL; 2382 } 2383 } 2384 } 2385 2386 /* 2387 * sip_stop: [ ifnet interface function ] 2388 * 2389 * Stop transmission on the interface. 2390 */ 2391 void 2392 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2393 { 2394 struct sip_softc *sc = ifp->if_softc; 2395 bus_space_tag_t st = sc->sc_st; 2396 bus_space_handle_t sh = sc->sc_sh; 2397 struct sip_txsoft *txs; 2398 u_int32_t cmdsts = 0; /* DEBUG */ 2399 2400 /* 2401 * Stop the one second clock. 2402 */ 2403 callout_stop(&sc->sc_tick_ch); 2404 2405 /* Down the MII. */ 2406 mii_down(&sc->sc_mii); 2407 2408 /* 2409 * Disable interrupts. 2410 */ 2411 bus_space_write_4(st, sh, SIP_IER, 0); 2412 2413 /* 2414 * Stop receiver and transmitter. 2415 */ 2416 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2417 2418 /* 2419 * Release any queued transmit buffers. 2420 */ 2421 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2422 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2423 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2424 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2425 CMDSTS_INTR) == 0) 2426 printf("%s: sip_stop: last descriptor does not " 2427 "have INTR bit set\n", sc->sc_dev.dv_xname); 2428 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2429 #ifdef DIAGNOSTIC 2430 if (txs->txs_mbuf == NULL) { 2431 printf("%s: dirty txsoft with no mbuf chain\n", 2432 sc->sc_dev.dv_xname); 2433 panic("sip_stop"); 2434 } 2435 #endif 2436 cmdsts |= /* DEBUG */ 2437 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2438 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2439 m_freem(txs->txs_mbuf); 2440 txs->txs_mbuf = NULL; 2441 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2442 } 2443 2444 if (disable) 2445 SIP_DECL(rxdrain)(sc); 2446 2447 /* 2448 * Mark the interface down and cancel the watchdog timer. 2449 */ 2450 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2451 ifp->if_timer = 0; 2452 2453 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2454 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2455 printf("%s: sip_stop: no INTR bits set in dirty tx " 2456 "descriptors\n", sc->sc_dev.dv_xname); 2457 } 2458 2459 /* 2460 * sip_read_eeprom: 2461 * 2462 * Read data from the serial EEPROM. 2463 */ 2464 void 2465 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2466 u_int16_t *data) 2467 { 2468 bus_space_tag_t st = sc->sc_st; 2469 bus_space_handle_t sh = sc->sc_sh; 2470 u_int16_t reg; 2471 int i, x; 2472 2473 for (i = 0; i < wordcnt; i++) { 2474 /* Send CHIP SELECT. */ 2475 reg = EROMAR_EECS; 2476 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2477 2478 /* Shift in the READ opcode. */ 2479 for (x = 3; x > 0; x--) { 2480 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2481 reg |= EROMAR_EEDI; 2482 else 2483 reg &= ~EROMAR_EEDI; 2484 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2485 bus_space_write_4(st, sh, SIP_EROMAR, 2486 reg | EROMAR_EESK); 2487 delay(4); 2488 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2489 delay(4); 2490 } 2491 2492 /* Shift in address. */ 2493 for (x = 6; x > 0; x--) { 2494 if ((word + i) & (1 << (x - 1))) 2495 reg |= EROMAR_EEDI; 2496 else 2497 reg &= ~EROMAR_EEDI; 2498 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2499 bus_space_write_4(st, sh, SIP_EROMAR, 2500 reg | EROMAR_EESK); 2501 delay(4); 2502 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2503 delay(4); 2504 } 2505 2506 /* Shift out data. */ 2507 reg = EROMAR_EECS; 2508 data[i] = 0; 2509 for (x = 16; x > 0; x--) { 2510 bus_space_write_4(st, sh, SIP_EROMAR, 2511 reg | EROMAR_EESK); 2512 delay(4); 2513 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2514 data[i] |= (1 << (x - 1)); 2515 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2516 delay(4); 2517 } 2518 2519 /* Clear CHIP SELECT. */ 2520 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2521 delay(4); 2522 } 2523 } 2524 2525 /* 2526 * sip_add_rxbuf: 2527 * 2528 * Add a receive buffer to the indicated descriptor. 2529 */ 2530 int 2531 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2532 { 2533 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2534 struct mbuf *m; 2535 int error; 2536 2537 MGETHDR(m, M_DONTWAIT, MT_DATA); 2538 if (m == NULL) 2539 return (ENOBUFS); 2540 2541 MCLGET(m, M_DONTWAIT); 2542 if ((m->m_flags & M_EXT) == 0) { 2543 m_freem(m); 2544 return (ENOBUFS); 2545 } 2546 2547 #if defined(DP83820) 2548 m->m_len = SIP_RXBUF_LEN; 2549 #endif /* DP83820 */ 2550 2551 if (rxs->rxs_mbuf != NULL) 2552 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2553 2554 rxs->rxs_mbuf = m; 2555 2556 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2557 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2558 BUS_DMA_READ|BUS_DMA_NOWAIT); 2559 if (error) { 2560 printf("%s: can't load rx DMA map %d, error = %d\n", 2561 sc->sc_dev.dv_xname, idx, error); 2562 panic("sip_add_rxbuf"); /* XXX */ 2563 } 2564 2565 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2566 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2567 2568 SIP_INIT_RXDESC(sc, idx); 2569 2570 return (0); 2571 } 2572 2573 #if !defined(DP83820) 2574 /* 2575 * sip_sis900_set_filter: 2576 * 2577 * Set up the receive filter. 2578 */ 2579 void 2580 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2581 { 2582 bus_space_tag_t st = sc->sc_st; 2583 bus_space_handle_t sh = sc->sc_sh; 2584 struct ethercom *ec = &sc->sc_ethercom; 2585 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2586 struct ether_multi *enm; 2587 u_int8_t *cp; 2588 struct ether_multistep step; 2589 u_int32_t crc, mchash[16]; 2590 2591 /* 2592 * Initialize the prototype RFCR. 2593 */ 2594 sc->sc_rfcr = RFCR_RFEN; 2595 if (ifp->if_flags & IFF_BROADCAST) 2596 sc->sc_rfcr |= RFCR_AAB; 2597 if (ifp->if_flags & IFF_PROMISC) { 2598 sc->sc_rfcr |= RFCR_AAP; 2599 goto allmulti; 2600 } 2601 2602 /* 2603 * Set up the multicast address filter by passing all multicast 2604 * addresses through a CRC generator, and then using the high-order 2605 * 6 bits as an index into the 128 bit multicast hash table (only 2606 * the lower 16 bits of each 32 bit multicast hash register are 2607 * valid). The high order bits select the register, while the 2608 * rest of the bits select the bit within the register. 2609 */ 2610 2611 memset(mchash, 0, sizeof(mchash)); 2612 2613 ETHER_FIRST_MULTI(step, ec, enm); 2614 while (enm != NULL) { 2615 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2616 /* 2617 * We must listen to a range of multicast addresses. 2618 * For now, just accept all multicasts, rather than 2619 * trying to set only those filter bits needed to match 2620 * the range. (At this time, the only use of address 2621 * ranges is for IP multicast routing, for which the 2622 * range is big enough to require all bits set.) 2623 */ 2624 goto allmulti; 2625 } 2626 2627 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2628 2629 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2630 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2631 /* Just want the 8 most significant bits. */ 2632 crc >>= 24; 2633 } else { 2634 /* Just want the 7 most significant bits. */ 2635 crc >>= 25; 2636 } 2637 2638 /* Set the corresponding bit in the hash table. */ 2639 mchash[crc >> 4] |= 1 << (crc & 0xf); 2640 2641 ETHER_NEXT_MULTI(step, enm); 2642 } 2643 2644 ifp->if_flags &= ~IFF_ALLMULTI; 2645 goto setit; 2646 2647 allmulti: 2648 ifp->if_flags |= IFF_ALLMULTI; 2649 sc->sc_rfcr |= RFCR_AAM; 2650 2651 setit: 2652 #define FILTER_EMIT(addr, data) \ 2653 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2654 delay(1); \ 2655 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2656 delay(1) 2657 2658 /* 2659 * Disable receive filter, and program the node address. 2660 */ 2661 cp = LLADDR(ifp->if_sadl); 2662 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2663 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2664 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2665 2666 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2667 /* 2668 * Program the multicast hash table. 2669 */ 2670 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2671 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2672 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2673 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2674 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2675 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2676 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2677 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2678 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2679 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2680 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2681 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2682 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2683 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2684 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2685 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2686 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2687 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2688 } 2689 } 2690 #undef FILTER_EMIT 2691 2692 /* 2693 * Re-enable the receiver filter. 2694 */ 2695 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2696 } 2697 #endif /* ! DP83820 */ 2698 2699 /* 2700 * sip_dp83815_set_filter: 2701 * 2702 * Set up the receive filter. 2703 */ 2704 void 2705 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2706 { 2707 bus_space_tag_t st = sc->sc_st; 2708 bus_space_handle_t sh = sc->sc_sh; 2709 struct ethercom *ec = &sc->sc_ethercom; 2710 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2711 struct ether_multi *enm; 2712 u_int8_t *cp; 2713 struct ether_multistep step; 2714 u_int32_t crc, hash, slot, bit; 2715 #ifdef DP83820 2716 #define MCHASH_NWORDS 128 2717 #else 2718 #define MCHASH_NWORDS 32 2719 #endif /* DP83820 */ 2720 u_int16_t mchash[MCHASH_NWORDS]; 2721 int i; 2722 2723 /* 2724 * Initialize the prototype RFCR. 2725 * Enable the receive filter, and accept on 2726 * Perfect (destination address) Match 2727 * If IFF_BROADCAST, also accept all broadcast packets. 2728 * If IFF_PROMISC, accept all unicast packets (and later, set 2729 * IFF_ALLMULTI and accept all multicast, too). 2730 */ 2731 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2732 if (ifp->if_flags & IFF_BROADCAST) 2733 sc->sc_rfcr |= RFCR_AAB; 2734 if (ifp->if_flags & IFF_PROMISC) { 2735 sc->sc_rfcr |= RFCR_AAP; 2736 goto allmulti; 2737 } 2738 2739 #ifdef DP83820 2740 /* 2741 * Set up the DP83820 multicast address filter by passing all multicast 2742 * addresses through a CRC generator, and then using the high-order 2743 * 11 bits as an index into the 2048 bit multicast hash table. The 2744 * high-order 7 bits select the slot, while the low-order 4 bits 2745 * select the bit within the slot. Note that only the low 16-bits 2746 * of each filter word are used, and there are 128 filter words. 2747 */ 2748 #else 2749 /* 2750 * Set up the DP83815 multicast address filter by passing all multicast 2751 * addresses through a CRC generator, and then using the high-order 2752 * 9 bits as an index into the 512 bit multicast hash table. The 2753 * high-order 5 bits select the slot, while the low-order 4 bits 2754 * select the bit within the slot. Note that only the low 16-bits 2755 * of each filter word are used, and there are 32 filter words. 2756 */ 2757 #endif /* DP83820 */ 2758 2759 memset(mchash, 0, sizeof(mchash)); 2760 2761 ifp->if_flags &= ~IFF_ALLMULTI; 2762 ETHER_FIRST_MULTI(step, ec, enm); 2763 if (enm == NULL) 2764 goto setit; 2765 while (enm != NULL) { 2766 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2767 /* 2768 * We must listen to a range of multicast addresses. 2769 * For now, just accept all multicasts, rather than 2770 * trying to set only those filter bits needed to match 2771 * the range. (At this time, the only use of address 2772 * ranges is for IP multicast routing, for which the 2773 * range is big enough to require all bits set.) 2774 */ 2775 goto allmulti; 2776 } 2777 2778 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2779 2780 #ifdef DP83820 2781 /* Just want the 11 most significant bits. */ 2782 hash = crc >> 21; 2783 #else 2784 /* Just want the 9 most significant bits. */ 2785 hash = crc >> 23; 2786 #endif /* DP83820 */ 2787 2788 slot = hash >> 4; 2789 bit = hash & 0xf; 2790 2791 /* Set the corresponding bit in the hash table. */ 2792 mchash[slot] |= 1 << bit; 2793 2794 ETHER_NEXT_MULTI(step, enm); 2795 } 2796 sc->sc_rfcr |= RFCR_MHEN; 2797 goto setit; 2798 2799 allmulti: 2800 ifp->if_flags |= IFF_ALLMULTI; 2801 sc->sc_rfcr |= RFCR_AAM; 2802 2803 setit: 2804 #define FILTER_EMIT(addr, data) \ 2805 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2806 delay(1); \ 2807 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2808 delay(1) 2809 2810 /* 2811 * Disable receive filter, and program the node address. 2812 */ 2813 cp = LLADDR(ifp->if_sadl); 2814 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 2815 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 2816 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 2817 2818 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2819 /* 2820 * Program the multicast hash table. 2821 */ 2822 for (i = 0; i < MCHASH_NWORDS; i++) { 2823 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 2824 mchash[i]); 2825 } 2826 } 2827 #undef FILTER_EMIT 2828 #undef MCHASH_NWORDS 2829 2830 /* 2831 * Re-enable the receiver filter. 2832 */ 2833 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2834 } 2835 2836 #if defined(DP83820) 2837 /* 2838 * sip_dp83820_mii_readreg: [mii interface function] 2839 * 2840 * Read a PHY register on the MII of the DP83820. 2841 */ 2842 int 2843 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 2844 { 2845 2846 return (mii_bitbang_readreg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2847 phy, reg)); 2848 } 2849 2850 /* 2851 * sip_dp83820_mii_writereg: [mii interface function] 2852 * 2853 * Write a PHY register on the MII of the DP83820. 2854 */ 2855 void 2856 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 2857 { 2858 2859 mii_bitbang_writereg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2860 phy, reg, val); 2861 } 2862 2863 /* 2864 * sip_dp83815_mii_statchg: [mii interface function] 2865 * 2866 * Callback from MII layer when media changes. 2867 */ 2868 void 2869 SIP_DECL(dp83820_mii_statchg)(struct device *self) 2870 { 2871 struct sip_softc *sc = (struct sip_softc *) self; 2872 u_int32_t cfg; 2873 2874 /* 2875 * Update TXCFG for full-duplex operation. 2876 */ 2877 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2878 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2879 else 2880 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2881 2882 /* 2883 * Update RXCFG for full-duplex or loopback. 2884 */ 2885 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2886 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2887 sc->sc_rxcfg |= RXCFG_ATX; 2888 else 2889 sc->sc_rxcfg &= ~RXCFG_ATX; 2890 2891 /* 2892 * Update CFG for MII/GMII. 2893 */ 2894 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2895 cfg = sc->sc_cfg | CFG_MODE_1000; 2896 else 2897 cfg = sc->sc_cfg; 2898 2899 /* 2900 * XXX 802.3x flow control. 2901 */ 2902 2903 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 2904 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2905 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2906 } 2907 2908 /* 2909 * sip_dp83820_mii_bitbang_read: [mii bit-bang interface function] 2910 * 2911 * Read the MII serial port for the MII bit-bang module. 2912 */ 2913 u_int32_t 2914 SIP_DECL(dp83820_mii_bitbang_read)(struct device *self) 2915 { 2916 struct sip_softc *sc = (void *) self; 2917 2918 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 2919 } 2920 2921 /* 2922 * sip_dp83820_mii_bitbang_write: [mii big-bang interface function] 2923 * 2924 * Write the MII serial port for the MII bit-bang module. 2925 */ 2926 void 2927 SIP_DECL(dp83820_mii_bitbang_write)(struct device *self, u_int32_t val) 2928 { 2929 struct sip_softc *sc = (void *) self; 2930 2931 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 2932 } 2933 #else /* ! DP83820 */ 2934 /* 2935 * sip_sis900_mii_readreg: [mii interface function] 2936 * 2937 * Read a PHY register on the MII. 2938 */ 2939 int 2940 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 2941 { 2942 struct sip_softc *sc = (struct sip_softc *) self; 2943 u_int32_t enphy; 2944 2945 /* 2946 * The SiS 900 has only an internal PHY on the MII. Only allow 2947 * MII address 0. 2948 */ 2949 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 2950 sc->sc_rev < SIS_REV_635 && phy != 0) 2951 return (0); 2952 2953 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2954 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 2955 ENPHY_RWCMD | ENPHY_ACCESS); 2956 do { 2957 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2958 } while (enphy & ENPHY_ACCESS); 2959 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 2960 } 2961 2962 /* 2963 * sip_sis900_mii_writereg: [mii interface function] 2964 * 2965 * Write a PHY register on the MII. 2966 */ 2967 void 2968 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 2969 { 2970 struct sip_softc *sc = (struct sip_softc *) self; 2971 u_int32_t enphy; 2972 2973 /* 2974 * The SiS 900 has only an internal PHY on the MII. Only allow 2975 * MII address 0. 2976 */ 2977 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 2978 sc->sc_rev < SIS_REV_635 && phy != 0) 2979 return; 2980 2981 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2982 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 2983 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 2984 do { 2985 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2986 } while (enphy & ENPHY_ACCESS); 2987 } 2988 2989 /* 2990 * sip_sis900_mii_statchg: [mii interface function] 2991 * 2992 * Callback from MII layer when media changes. 2993 */ 2994 void 2995 SIP_DECL(sis900_mii_statchg)(struct device *self) 2996 { 2997 struct sip_softc *sc = (struct sip_softc *) self; 2998 u_int32_t flowctl; 2999 3000 /* 3001 * Update TXCFG for full-duplex operation. 3002 */ 3003 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3004 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3005 else 3006 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3007 3008 /* 3009 * Update RXCFG for full-duplex or loopback. 3010 */ 3011 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3012 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3013 sc->sc_rxcfg |= RXCFG_ATX; 3014 else 3015 sc->sc_rxcfg &= ~RXCFG_ATX; 3016 3017 /* 3018 * Update IMR for use of 802.3x flow control. 3019 */ 3020 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 3021 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3022 flowctl = FLOWCTL_FLOWEN; 3023 } else { 3024 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3025 flowctl = 0; 3026 } 3027 3028 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3029 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3030 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3031 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3032 } 3033 3034 /* 3035 * sip_dp83815_mii_readreg: [mii interface function] 3036 * 3037 * Read a PHY register on the MII. 3038 */ 3039 int 3040 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 3041 { 3042 struct sip_softc *sc = (struct sip_softc *) self; 3043 u_int32_t val; 3044 3045 /* 3046 * The DP83815 only has an internal PHY. Only allow 3047 * MII address 0. 3048 */ 3049 if (phy != 0) 3050 return (0); 3051 3052 /* 3053 * Apparently, after a reset, the DP83815 can take a while 3054 * to respond. During this recovery period, the BMSR returns 3055 * a value of 0. Catch this -- it's not supposed to happen 3056 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3057 * PHY to come back to life. 3058 * 3059 * This works out because the BMSR is the first register 3060 * read during the PHY probe process. 3061 */ 3062 do { 3063 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3064 } while (reg == MII_BMSR && val == 0); 3065 3066 return (val & 0xffff); 3067 } 3068 3069 /* 3070 * sip_dp83815_mii_writereg: [mii interface function] 3071 * 3072 * Write a PHY register to the MII. 3073 */ 3074 void 3075 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3076 { 3077 struct sip_softc *sc = (struct sip_softc *) self; 3078 3079 /* 3080 * The DP83815 only has an internal PHY. Only allow 3081 * MII address 0. 3082 */ 3083 if (phy != 0) 3084 return; 3085 3086 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3087 } 3088 3089 /* 3090 * sip_dp83815_mii_statchg: [mii interface function] 3091 * 3092 * Callback from MII layer when media changes. 3093 */ 3094 void 3095 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3096 { 3097 struct sip_softc *sc = (struct sip_softc *) self; 3098 3099 /* 3100 * Update TXCFG for full-duplex operation. 3101 */ 3102 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3103 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3104 else 3105 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3106 3107 /* 3108 * Update RXCFG for full-duplex or loopback. 3109 */ 3110 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3111 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3112 sc->sc_rxcfg |= RXCFG_ATX; 3113 else 3114 sc->sc_rxcfg &= ~RXCFG_ATX; 3115 3116 /* 3117 * XXX 802.3x flow control. 3118 */ 3119 3120 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3121 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3122 } 3123 #endif /* DP83820 */ 3124 3125 #if defined(DP83820) 3126 void 3127 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3128 const struct pci_attach_args *pa, u_int8_t *enaddr) 3129 { 3130 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3131 u_int8_t cksum, *e, match; 3132 int i; 3133 3134 /* 3135 * EEPROM data format for the DP83820 can be found in 3136 * the DP83820 manual, section 4.2.4. 3137 */ 3138 3139 SIP_DECL(read_eeprom)(sc, 0, 3140 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3141 3142 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3143 match = ~(match - 1); 3144 3145 cksum = 0x55; 3146 e = (u_int8_t *) eeprom_data; 3147 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3148 cksum += *e++; 3149 3150 if (cksum != match) 3151 printf("%s: Checksum (%x) mismatch (%x)", 3152 sc->sc_dev.dv_xname, cksum, match); 3153 3154 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3155 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3156 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3157 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3158 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3159 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3160 3161 /* Get the GPIOR bits. */ 3162 sc->sc_gpior = eeprom_data[0x04]; 3163 } 3164 #else /* ! DP83820 */ 3165 void 3166 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3167 const struct pci_attach_args *pa, u_int8_t *enaddr) 3168 { 3169 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3170 3171 switch (sc->sc_rev) { 3172 case SIS_REV_630S: 3173 case SIS_REV_630E: 3174 case SIS_REV_630EA1: 3175 case SIS_REV_630ET: 3176 case SIS_REV_635: 3177 /* 3178 * The MAC address for the on-board Ethernet of 3179 * the SiS 630 chipset is in the NVRAM. Kick 3180 * the chip into re-loading it from NVRAM, and 3181 * read the MAC address out of the filter registers. 3182 */ 3183 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3184 3185 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3186 RFCR_RFADDR_NODE0); 3187 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3188 0xffff; 3189 3190 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3191 RFCR_RFADDR_NODE2); 3192 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3193 0xffff; 3194 3195 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3196 RFCR_RFADDR_NODE4); 3197 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3198 0xffff; 3199 break; 3200 3201 default: 3202 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3203 sizeof(myea) / sizeof(myea[0]), myea); 3204 } 3205 3206 enaddr[0] = myea[0] & 0xff; 3207 enaddr[1] = myea[0] >> 8; 3208 enaddr[2] = myea[1] & 0xff; 3209 enaddr[3] = myea[1] >> 8; 3210 enaddr[4] = myea[2] & 0xff; 3211 enaddr[5] = myea[2] >> 8; 3212 } 3213 3214 /* Table and macro to bit-reverse an octet. */ 3215 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3216 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3217 3218 void 3219 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3220 const struct pci_attach_args *pa, u_int8_t *enaddr) 3221 { 3222 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3223 u_int8_t cksum, *e, match; 3224 int i; 3225 3226 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3227 sizeof(eeprom_data[0]), eeprom_data); 3228 3229 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3230 match = ~(match - 1); 3231 3232 cksum = 0x55; 3233 e = (u_int8_t *) eeprom_data; 3234 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3235 cksum += *e++; 3236 } 3237 if (cksum != match) { 3238 printf("%s: Checksum (%x) mismatch (%x)", 3239 sc->sc_dev.dv_xname, cksum, match); 3240 } 3241 3242 /* 3243 * Unrolled because it makes slightly more sense this way. 3244 * The DP83815 stores the MAC address in bit 0 of word 6 3245 * through bit 15 of word 8. 3246 */ 3247 ea = &eeprom_data[6]; 3248 enaddr[0] = ((*ea & 0x1) << 7); 3249 ea++; 3250 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3251 enaddr[1] = ((*ea & 0x1FE) >> 1); 3252 enaddr[2] = ((*ea & 0x1) << 7); 3253 ea++; 3254 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3255 enaddr[3] = ((*ea & 0x1FE) >> 1); 3256 enaddr[4] = ((*ea & 0x1) << 7); 3257 ea++; 3258 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3259 enaddr[5] = ((*ea & 0x1FE) >> 1); 3260 3261 /* 3262 * In case that's not weird enough, we also need to reverse 3263 * the bits in each byte. This all actually makes more sense 3264 * if you think about the EEPROM storage as an array of bits 3265 * being shifted into bytes, but that's not how we're looking 3266 * at it here... 3267 */ 3268 for (i = 0; i < 6 ;i++) 3269 enaddr[i] = bbr(enaddr[i]); 3270 } 3271 #endif /* DP83820 */ 3272 3273 /* 3274 * sip_mediastatus: [ifmedia interface function] 3275 * 3276 * Get the current interface media status. 3277 */ 3278 void 3279 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3280 { 3281 struct sip_softc *sc = ifp->if_softc; 3282 3283 mii_pollstat(&sc->sc_mii); 3284 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3285 ifmr->ifm_active = sc->sc_mii.mii_media_active; 3286 } 3287 3288 /* 3289 * sip_mediachange: [ifmedia interface function] 3290 * 3291 * Set hardware to newly-selected media. 3292 */ 3293 int 3294 SIP_DECL(mediachange)(struct ifnet *ifp) 3295 { 3296 struct sip_softc *sc = ifp->if_softc; 3297 3298 if (ifp->if_flags & IFF_UP) 3299 mii_mediachg(&sc->sc_mii); 3300 return (0); 3301 } 3302
Indexes created Tue Sep 30 11:09:46 GMT 2025