if_sip.c revision 1.27
1 /* $NetBSD: if_sip.c,v 1.27 2001/03/24 19:40:51 briggs Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 Network Computer, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of Network Computer, Inc. nor the names of its 16 * contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Silicon Integrated Systems SiS 900 and 34 * SiS 7016 10/100 PCI Ethernet controllers. 35 * 36 * Written by Jason R. Thorpe for Network Computer, Inc. 37 */ 38 39 #include "opt_inet.h" 40 #include "opt_ns.h" 41 #include "bpfilter.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/callout.h> 46 #include <sys/mbuf.h> 47 #include <sys/malloc.h> 48 #include <sys/kernel.h> 49 #include <sys/socket.h> 50 #include <sys/ioctl.h> 51 #include <sys/errno.h> 52 #include <sys/device.h> 53 #include <sys/queue.h> 54 55 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 56 57 #include <net/if.h> 58 #include <net/if_dl.h> 59 #include <net/if_media.h> 60 #include <net/if_ether.h> 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #ifdef INET 67 #include <netinet/in.h> 68 #include <netinet/if_inarp.h> 69 #endif 70 71 #ifdef NS 72 #include <netns/ns.h> 73 #include <netns/ns_if.h> 74 #endif 75 76 #include <machine/bus.h> 77 #include <machine/intr.h> 78 #include <machine/endian.h> 79 80 #include <dev/mii/mii.h> 81 #include <dev/mii/miivar.h> 82 83 #include <dev/pci/pcireg.h> 84 #include <dev/pci/pcivar.h> 85 #include <dev/pci/pcidevs.h> 86 87 #include <dev/pci/if_sipreg.h> 88 89 /* 90 * Transmit descriptor list size. This is arbitrary, but allocate 91 * enough descriptors for 64 pending transmissions, and 16 segments 92 * per packet. This MUST work out to a power of 2. 93 */ 94 #define SIP_NTXSEGS 16 95 96 #define SIP_TXQUEUELEN 64 97 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS) 98 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 99 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 100 101 /* 102 * Receive descriptor list size. We have one Rx buffer per incoming 103 * packet, so this logic is a little simpler. 104 */ 105 #define SIP_NRXDESC 64 106 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 107 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 108 109 /* 110 * Control structures are DMA'd to the SiS900 chip. We allocate them in 111 * a single clump that maps to a single DMA segment to make several things 112 * easier. 113 */ 114 struct sip_control_data { 115 /* 116 * The transmit descriptors. 117 */ 118 struct sip_desc scd_txdescs[SIP_NTXDESC]; 119 120 /* 121 * The receive descriptors. 122 */ 123 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 124 }; 125 126 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 127 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 128 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 129 130 /* 131 * Software state for transmit jobs. 132 */ 133 struct sip_txsoft { 134 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 135 bus_dmamap_t txs_dmamap; /* our DMA map */ 136 int txs_firstdesc; /* first descriptor in packet */ 137 int txs_lastdesc; /* last descriptor in packet */ 138 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 139 }; 140 141 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 142 143 /* 144 * Software state for receive jobs. 145 */ 146 struct sip_rxsoft { 147 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 148 bus_dmamap_t rxs_dmamap; /* our DMA map */ 149 }; 150 151 /* 152 * Software state per device. 153 */ 154 struct sip_softc { 155 struct device sc_dev; /* generic device information */ 156 bus_space_tag_t sc_st; /* bus space tag */ 157 bus_space_handle_t sc_sh; /* bus space handle */ 158 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 159 struct ethercom sc_ethercom; /* ethernet common data */ 160 void *sc_sdhook; /* shutdown hook */ 161 162 const struct sip_product *sc_model; /* which model are we? */ 163 164 void *sc_ih; /* interrupt cookie */ 165 166 struct mii_data sc_mii; /* MII/media information */ 167 168 struct callout sc_tick_ch; /* tick callout */ 169 170 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 171 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 172 173 /* 174 * Software state for transmit and receive descriptors. 175 */ 176 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 177 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 178 179 /* 180 * Control data structures. 181 */ 182 struct sip_control_data *sc_control_data; 183 #define sc_txdescs sc_control_data->scd_txdescs 184 #define sc_rxdescs sc_control_data->scd_rxdescs 185 186 u_int32_t sc_txcfg; /* prototype TXCFG register */ 187 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 188 u_int32_t sc_imr; /* prototype IMR register */ 189 u_int32_t sc_rfcr; /* prototype RFCR register */ 190 191 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 192 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 193 194 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 195 196 int sc_flags; /* misc. flags; see below */ 197 198 int sc_txfree; /* number of free Tx descriptors */ 199 int sc_txnext; /* next ready Tx descriptor */ 200 201 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 202 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 203 204 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 205 }; 206 207 /* sc_flags */ 208 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 209 210 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 211 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 212 213 #define SIP_CDTXSYNC(sc, x, n, ops) \ 214 do { \ 215 int __x, __n; \ 216 \ 217 __x = (x); \ 218 __n = (n); \ 219 \ 220 /* If it will wrap around, sync to the end of the ring. */ \ 221 if ((__x + __n) > SIP_NTXDESC) { \ 222 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 223 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 224 (SIP_NTXDESC - __x), (ops)); \ 225 __n -= (SIP_NTXDESC - __x); \ 226 __x = 0; \ 227 } \ 228 \ 229 /* Now sync whatever is left. */ \ 230 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 231 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 232 } while (0) 233 234 #define SIP_CDRXSYNC(sc, x, ops) \ 235 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 236 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 237 238 /* 239 * Note we rely on MCLBYTES being a power of two below. 240 */ 241 #define SIP_INIT_RXDESC(sc, x) \ 242 do { \ 243 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 244 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 245 \ 246 __sipd->sipd_link = htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 247 __sipd->sipd_bufptr = htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 248 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 249 ((MCLBYTES - 1) & CMDSTS_SIZE_MASK)); \ 250 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 251 } while (0) 252 253 #define SIP_TIMEOUT 1000 254 255 void sip_start __P((struct ifnet *)); 256 void sip_watchdog __P((struct ifnet *)); 257 int sip_ioctl __P((struct ifnet *, u_long, caddr_t)); 258 int sip_init __P((struct ifnet *)); 259 void sip_stop __P((struct ifnet *, int)); 260 261 void sip_shutdown __P((void *)); 262 263 void sip_reset __P((struct sip_softc *)); 264 void sip_rxdrain __P((struct sip_softc *)); 265 int sip_add_rxbuf __P((struct sip_softc *, int)); 266 void sip_read_eeprom __P((struct sip_softc *, int, int, u_int16_t *)); 267 void sip_tick __P((void *)); 268 269 void sip_sis900_set_filter __P((struct sip_softc *)); 270 void sip_dp83815_set_filter __P((struct sip_softc *)); 271 272 void sip_sis900_read_macaddr __P((struct sip_softc *, u_int8_t *)); 273 void sip_dp83815_read_macaddr __P((struct sip_softc *, u_int8_t *)); 274 275 int sip_intr __P((void *)); 276 void sip_txintr __P((struct sip_softc *)); 277 void sip_rxintr __P((struct sip_softc *)); 278 279 int sip_sis900_mii_readreg __P((struct device *, int, int)); 280 void sip_sis900_mii_writereg __P((struct device *, int, int, int)); 281 void sip_sis900_mii_statchg __P((struct device *)); 282 283 int sip_dp83815_mii_readreg __P((struct device *, int, int)); 284 void sip_dp83815_mii_writereg __P((struct device *, int, int, int)); 285 void sip_dp83815_mii_statchg __P((struct device *)); 286 287 int sip_mediachange __P((struct ifnet *)); 288 void sip_mediastatus __P((struct ifnet *, struct ifmediareq *)); 289 290 int sip_match __P((struct device *, struct cfdata *, void *)); 291 void sip_attach __P((struct device *, struct device *, void *)); 292 293 int sip_copy_small = 0; 294 295 struct cfattach sip_ca = { 296 sizeof(struct sip_softc), sip_match, sip_attach, 297 }; 298 299 /* 300 * Descriptions of the variants of the SiS900. 301 */ 302 struct sip_variant { 303 int (*sipv_mii_readreg) __P((struct device *, int, int)); 304 void (*sipv_mii_writereg) __P((struct device *, int, int, int)); 305 void (*sipv_mii_statchg) __P((struct device *)); 306 void (*sipv_set_filter) __P((struct sip_softc *)); 307 void (*sipv_read_macaddr) __P((struct sip_softc *, u_int8_t *)); 308 }; 309 310 const struct sip_variant sip_variant_sis900 = { 311 sip_sis900_mii_readreg, sip_sis900_mii_writereg, 312 sip_sis900_mii_statchg, sip_sis900_set_filter, 313 sip_sis900_read_macaddr 314 }; 315 316 const struct sip_variant sip_variant_dp83815 = { 317 sip_dp83815_mii_readreg, sip_dp83815_mii_writereg, 318 sip_dp83815_mii_statchg, sip_dp83815_set_filter, 319 sip_dp83815_read_macaddr 320 }; 321 322 /* 323 * Devices supported by this driver. 324 */ 325 const struct sip_product { 326 pci_vendor_id_t sip_vendor; 327 pci_product_id_t sip_product; 328 const char *sip_name; 329 const struct sip_variant *sip_variant; 330 } sip_products[] = { 331 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 332 "SiS 900 10/100 Ethernet", 333 &sip_variant_sis900 }, 334 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 335 "SiS 7016 10/100 Ethernet", 336 &sip_variant_sis900 }, 337 338 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 339 "NatSemi DP83815 10/100 Ethernet", 340 &sip_variant_dp83815 }, 341 342 { 0, 0, 343 NULL, 344 NULL }, 345 }; 346 347 const struct sip_product *sip_lookup __P((const struct pci_attach_args *)); 348 349 const struct sip_product * 350 sip_lookup(pa) 351 const struct pci_attach_args *pa; 352 { 353 const struct sip_product *sip; 354 355 for (sip = sip_products; sip->sip_name != NULL; sip++) { 356 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 357 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 358 return (sip); 359 } 360 return (NULL); 361 } 362 363 int 364 sip_match(parent, cf, aux) 365 struct device *parent; 366 struct cfdata *cf; 367 void *aux; 368 { 369 struct pci_attach_args *pa = aux; 370 371 if (sip_lookup(pa) != NULL) 372 return (1); 373 374 return (0); 375 } 376 377 void 378 sip_attach(parent, self, aux) 379 struct device *parent, *self; 380 void *aux; 381 { 382 struct sip_softc *sc = (struct sip_softc *) self; 383 struct pci_attach_args *pa = aux; 384 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 385 pci_chipset_tag_t pc = pa->pa_pc; 386 pci_intr_handle_t ih; 387 const char *intrstr = NULL; 388 bus_space_tag_t iot, memt; 389 bus_space_handle_t ioh, memh; 390 bus_dma_segment_t seg; 391 int ioh_valid, memh_valid; 392 int i, rseg, error; 393 const struct sip_product *sip; 394 pcireg_t pmode; 395 u_int8_t enaddr[ETHER_ADDR_LEN]; 396 int pmreg; 397 398 callout_init(&sc->sc_tick_ch); 399 400 sip = sip_lookup(pa); 401 if (sip == NULL) { 402 printf("\n"); 403 panic("sip_attach: impossible"); 404 } 405 406 printf(": %s\n", sip->sip_name); 407 408 sc->sc_model = sip; 409 410 /* 411 * Map the device. 412 */ 413 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 414 PCI_MAPREG_TYPE_IO, 0, 415 &iot, &ioh, NULL, NULL) == 0); 416 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 417 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 418 &memt, &memh, NULL, NULL) == 0); 419 420 if (memh_valid) { 421 sc->sc_st = memt; 422 sc->sc_sh = memh; 423 } else if (ioh_valid) { 424 sc->sc_st = iot; 425 sc->sc_sh = ioh; 426 } else { 427 printf("%s: unable to map device registers\n", 428 sc->sc_dev.dv_xname); 429 return; 430 } 431 432 sc->sc_dmat = pa->pa_dmat; 433 434 /* Enable bus mastering. */ 435 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 436 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 437 PCI_COMMAND_MASTER_ENABLE); 438 439 /* Get it out of power save mode if needed. */ 440 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 441 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 442 if (pmode == 3) { 443 /* 444 * The card has lost all configuration data in 445 * this state, so punt. 446 */ 447 printf("%s: unable to wake up from power state D3\n", 448 sc->sc_dev.dv_xname); 449 return; 450 } 451 if (pmode != 0) { 452 printf("%s: waking up from power state D%d\n", 453 sc->sc_dev.dv_xname, pmode); 454 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 455 } 456 } 457 458 /* 459 * Map and establish our interrupt. 460 */ 461 if (pci_intr_map(pa, &ih)) { 462 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 463 return; 464 } 465 intrstr = pci_intr_string(pc, ih); 466 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sip_intr, sc); 467 if (sc->sc_ih == NULL) { 468 printf("%s: unable to establish interrupt", 469 sc->sc_dev.dv_xname); 470 if (intrstr != NULL) 471 printf(" at %s", intrstr); 472 printf("\n"); 473 return; 474 } 475 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 476 477 SIMPLEQ_INIT(&sc->sc_txfreeq); 478 SIMPLEQ_INIT(&sc->sc_txdirtyq); 479 480 /* 481 * Allocate the control data structures, and create and load the 482 * DMA map for it. 483 */ 484 if ((error = bus_dmamem_alloc(sc->sc_dmat, 485 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 486 0)) != 0) { 487 printf("%s: unable to allocate control data, error = %d\n", 488 sc->sc_dev.dv_xname, error); 489 goto fail_0; 490 } 491 492 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 493 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 494 BUS_DMA_COHERENT)) != 0) { 495 printf("%s: unable to map control data, error = %d\n", 496 sc->sc_dev.dv_xname, error); 497 goto fail_1; 498 } 499 500 if ((error = bus_dmamap_create(sc->sc_dmat, 501 sizeof(struct sip_control_data), 1, 502 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 503 printf("%s: unable to create control data DMA map, " 504 "error = %d\n", sc->sc_dev.dv_xname, error); 505 goto fail_2; 506 } 507 508 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 509 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 510 0)) != 0) { 511 printf("%s: unable to load control data DMA map, error = %d\n", 512 sc->sc_dev.dv_xname, error); 513 goto fail_3; 514 } 515 516 /* 517 * Create the transmit buffer DMA maps. 518 */ 519 for (i = 0; i < SIP_TXQUEUELEN; i++) { 520 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 521 SIP_NTXSEGS, MCLBYTES, 0, 0, 522 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 523 printf("%s: unable to create tx DMA map %d, " 524 "error = %d\n", sc->sc_dev.dv_xname, i, error); 525 goto fail_4; 526 } 527 } 528 529 /* 530 * Create the receive buffer DMA maps. 531 */ 532 for (i = 0; i < SIP_NRXDESC; i++) { 533 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 534 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 535 printf("%s: unable to create rx DMA map %d, " 536 "error = %d\n", sc->sc_dev.dv_xname, i, error); 537 goto fail_5; 538 } 539 sc->sc_rxsoft[i].rxs_mbuf = NULL; 540 } 541 542 /* 543 * Reset the chip to a known state. 544 */ 545 sip_reset(sc); 546 547 /* 548 * Read the Ethernet address from the EEPROM. 549 */ 550 sip->sip_variant->sipv_read_macaddr(sc, enaddr); 551 552 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 553 ether_sprintf(enaddr)); 554 555 /* 556 * Initialize our media structures and probe the MII. 557 */ 558 sc->sc_mii.mii_ifp = ifp; 559 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 560 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 561 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 562 ifmedia_init(&sc->sc_mii.mii_media, 0, sip_mediachange, 563 sip_mediastatus); 564 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 565 MII_OFFSET_ANY, 0); 566 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 567 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 568 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 569 } else 570 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 571 572 ifp = &sc->sc_ethercom.ec_if; 573 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 574 ifp->if_softc = sc; 575 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 576 ifp->if_ioctl = sip_ioctl; 577 ifp->if_start = sip_start; 578 ifp->if_watchdog = sip_watchdog; 579 ifp->if_init = sip_init; 580 ifp->if_stop = sip_stop; 581 IFQ_SET_READY(&ifp->if_snd); 582 583 /* 584 * Attach the interface. 585 */ 586 if_attach(ifp); 587 ether_ifattach(ifp, enaddr); 588 589 /* 590 * Make sure the interface is shutdown during reboot. 591 */ 592 sc->sc_sdhook = shutdownhook_establish(sip_shutdown, sc); 593 if (sc->sc_sdhook == NULL) 594 printf("%s: WARNING: unable to establish shutdown hook\n", 595 sc->sc_dev.dv_xname); 596 return; 597 598 /* 599 * Free any resources we've allocated during the failed attach 600 * attempt. Do this in reverse order and fall through. 601 */ 602 fail_5: 603 for (i = 0; i < SIP_NRXDESC; i++) { 604 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 605 bus_dmamap_destroy(sc->sc_dmat, 606 sc->sc_rxsoft[i].rxs_dmamap); 607 } 608 fail_4: 609 for (i = 0; i < SIP_TXQUEUELEN; i++) { 610 if (sc->sc_txsoft[i].txs_dmamap != NULL) 611 bus_dmamap_destroy(sc->sc_dmat, 612 sc->sc_txsoft[i].txs_dmamap); 613 } 614 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 615 fail_3: 616 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 617 fail_2: 618 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 619 sizeof(struct sip_control_data)); 620 fail_1: 621 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 622 fail_0: 623 return; 624 } 625 626 /* 627 * sip_shutdown: 628 * 629 * Make sure the interface is stopped at reboot time. 630 */ 631 void 632 sip_shutdown(arg) 633 void *arg; 634 { 635 struct sip_softc *sc = arg; 636 637 sip_stop(&sc->sc_ethercom.ec_if, 1); 638 } 639 640 /* 641 * sip_start: [ifnet interface function] 642 * 643 * Start packet transmission on the interface. 644 */ 645 void 646 sip_start(ifp) 647 struct ifnet *ifp; 648 { 649 struct sip_softc *sc = ifp->if_softc; 650 struct mbuf *m0, *m; 651 struct sip_txsoft *txs; 652 bus_dmamap_t dmamap; 653 int error, firsttx, nexttx, lasttx, ofree, seg; 654 655 /* 656 * If we've been told to pause, don't transmit any more packets. 657 */ 658 if (sc->sc_flags & SIPF_PAUSED) 659 ifp->if_flags |= IFF_OACTIVE; 660 661 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 662 return; 663 664 /* 665 * Remember the previous number of free descriptors and 666 * the first descriptor we'll use. 667 */ 668 ofree = sc->sc_txfree; 669 firsttx = sc->sc_txnext; 670 671 /* 672 * Loop through the send queue, setting up transmit descriptors 673 * until we drain the queue, or use up all available transmit 674 * descriptors. 675 */ 676 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 677 sc->sc_txfree != 0) { 678 /* 679 * Grab a packet off the queue. 680 */ 681 IFQ_POLL(&ifp->if_snd, m0); 682 if (m0 == NULL) 683 break; 684 m = NULL; 685 686 dmamap = txs->txs_dmamap; 687 688 /* 689 * Load the DMA map. If this fails, the packet either 690 * didn't fit in the alloted number of segments, or we 691 * were short on resources. In this case, we'll copy 692 * and try again. 693 */ 694 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 695 BUS_DMA_NOWAIT) != 0) { 696 MGETHDR(m, M_DONTWAIT, MT_DATA); 697 if (m == NULL) { 698 printf("%s: unable to allocate Tx mbuf\n", 699 sc->sc_dev.dv_xname); 700 break; 701 } 702 if (m0->m_pkthdr.len > MHLEN) { 703 MCLGET(m, M_DONTWAIT); 704 if ((m->m_flags & M_EXT) == 0) { 705 printf("%s: unable to allocate Tx " 706 "cluster\n", sc->sc_dev.dv_xname); 707 m_freem(m); 708 break; 709 } 710 } 711 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 712 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 713 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 714 m, BUS_DMA_NOWAIT); 715 if (error) { 716 printf("%s: unable to load Tx buffer, " 717 "error = %d\n", sc->sc_dev.dv_xname, error); 718 break; 719 } 720 } 721 722 /* 723 * Ensure we have enough descriptors free to describe 724 * the packet. 725 */ 726 if (dmamap->dm_nsegs > sc->sc_txfree) { 727 /* 728 * Not enough free descriptors to transmit this 729 * packet. We haven't committed anything yet, 730 * so just unload the DMA map, put the packet 731 * back on the queue, and punt. Notify the upper 732 * layer that there are not more slots left. 733 * 734 * XXX We could allocate an mbuf and copy, but 735 * XXX is it worth it? 736 */ 737 ifp->if_flags |= IFF_OACTIVE; 738 bus_dmamap_unload(sc->sc_dmat, dmamap); 739 if (m != NULL) 740 m_freem(m); 741 break; 742 } 743 744 IFQ_DEQUEUE(&ifp->if_snd, m0); 745 if (m != NULL) { 746 m_freem(m0); 747 m0 = m; 748 } 749 750 /* 751 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 752 */ 753 754 /* Sync the DMA map. */ 755 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 756 BUS_DMASYNC_PREWRITE); 757 758 /* 759 * Initialize the transmit descriptors. 760 */ 761 for (nexttx = sc->sc_txnext, seg = 0; 762 seg < dmamap->dm_nsegs; 763 seg++, nexttx = SIP_NEXTTX(nexttx)) { 764 /* 765 * If this is the first descriptor we're 766 * enqueueing, don't set the OWN bit just 767 * yet. That could cause a race condition. 768 * We'll do it below. 769 */ 770 sc->sc_txdescs[nexttx].sipd_bufptr = 771 htole32(dmamap->dm_segs[seg].ds_addr); 772 sc->sc_txdescs[nexttx].sipd_cmdsts = 773 htole32((nexttx == firsttx ? 0 : CMDSTS_OWN) | 774 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 775 lasttx = nexttx; 776 } 777 778 /* Clear the MORE bit on the last segment. */ 779 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 780 781 /* Sync the descriptors we're using. */ 782 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 783 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 784 785 /* 786 * Store a pointer to the packet so we can free it later, 787 * and remember what txdirty will be once the packet is 788 * done. 789 */ 790 txs->txs_mbuf = m0; 791 txs->txs_firstdesc = sc->sc_txnext; 792 txs->txs_lastdesc = lasttx; 793 794 /* Advance the tx pointer. */ 795 sc->sc_txfree -= dmamap->dm_nsegs; 796 sc->sc_txnext = nexttx; 797 798 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs, txs_q); 799 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 800 801 #if NBPFILTER > 0 802 /* 803 * Pass the packet to any BPF listeners. 804 */ 805 if (ifp->if_bpf) 806 bpf_mtap(ifp->if_bpf, m0); 807 #endif /* NBPFILTER > 0 */ 808 } 809 810 if (txs == NULL || sc->sc_txfree == 0) { 811 /* No more slots left; notify upper layer. */ 812 ifp->if_flags |= IFF_OACTIVE; 813 } 814 815 if (sc->sc_txfree != ofree) { 816 /* 817 * Cause a descriptor interrupt to happen on the 818 * last packet we enqueued. 819 */ 820 sc->sc_txdescs[lasttx].sipd_cmdsts |= htole32(CMDSTS_INTR); 821 SIP_CDTXSYNC(sc, lasttx, 1, 822 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 823 824 /* 825 * The entire packet chain is set up. Give the 826 * first descrptor to the chip now. 827 */ 828 sc->sc_txdescs[firsttx].sipd_cmdsts |= htole32(CMDSTS_OWN); 829 SIP_CDTXSYNC(sc, firsttx, 1, 830 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 831 832 /* Start the transmit process. */ 833 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 834 CR_TXE) == 0) { 835 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 836 SIP_CDTXADDR(sc, firsttx)); 837 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 838 } 839 840 /* Set a watchdog timer in case the chip flakes out. */ 841 ifp->if_timer = 5; 842 } 843 } 844 845 /* 846 * sip_watchdog: [ifnet interface function] 847 * 848 * Watchdog timer handler. 849 */ 850 void 851 sip_watchdog(ifp) 852 struct ifnet *ifp; 853 { 854 struct sip_softc *sc = ifp->if_softc; 855 856 /* 857 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 858 * If we get a timeout, try and sweep up transmit descriptors. 859 * If we manage to sweep them all up, ignore the lack of 860 * interrupt. 861 */ 862 sip_txintr(sc); 863 864 if (sc->sc_txfree != SIP_NTXDESC) { 865 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 866 ifp->if_oerrors++; 867 868 /* Reset the interface. */ 869 (void) sip_init(ifp); 870 } else if (ifp->if_flags & IFF_DEBUG) 871 printf("%s: recovered from device timeout\n", 872 sc->sc_dev.dv_xname); 873 874 /* Try to get more packets going. */ 875 sip_start(ifp); 876 } 877 878 /* 879 * sip_ioctl: [ifnet interface function] 880 * 881 * Handle control requests from the operator. 882 */ 883 int 884 sip_ioctl(ifp, cmd, data) 885 struct ifnet *ifp; 886 u_long cmd; 887 caddr_t data; 888 { 889 struct sip_softc *sc = ifp->if_softc; 890 struct ifreq *ifr = (struct ifreq *)data; 891 int s, error; 892 893 s = splnet(); 894 895 switch (cmd) { 896 case SIOCSIFMEDIA: 897 case SIOCGIFMEDIA: 898 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 899 break; 900 901 default: 902 error = ether_ioctl(ifp, cmd, data); 903 if (error == ENETRESET) { 904 /* 905 * Multicast list has changed; set the hardware filter 906 * accordingly. 907 */ 908 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 909 error = 0; 910 } 911 break; 912 } 913 914 /* Try to get more packets going. */ 915 sip_start(ifp); 916 917 splx(s); 918 return (error); 919 } 920 921 /* 922 * sip_intr: 923 * 924 * Interrupt service routine. 925 */ 926 int 927 sip_intr(arg) 928 void *arg; 929 { 930 struct sip_softc *sc = arg; 931 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 932 u_int32_t isr; 933 int handled = 0; 934 935 for (;;) { 936 /* Reading clears interrupt. */ 937 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 938 if ((isr & sc->sc_imr) == 0) 939 break; 940 941 handled = 1; 942 943 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 944 /* Grab any new packets. */ 945 sip_rxintr(sc); 946 947 if (isr & ISR_RXORN) { 948 printf("%s: receive FIFO overrun\n", 949 sc->sc_dev.dv_xname); 950 951 /* XXX adjust rx_drain_thresh? */ 952 } 953 954 if (isr & ISR_RXIDLE) { 955 printf("%s: receive ring overrun\n", 956 sc->sc_dev.dv_xname); 957 958 /* Get the receive process going again. */ 959 bus_space_write_4(sc->sc_st, sc->sc_sh, 960 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 961 bus_space_write_4(sc->sc_st, sc->sc_sh, 962 SIP_CR, CR_RXE); 963 } 964 } 965 966 if (isr & (ISR_TXURN|ISR_TXDESC)) { 967 /* Sweep up transmit descriptors. */ 968 sip_txintr(sc); 969 970 if (isr & ISR_TXURN) { 971 u_int32_t thresh; 972 973 printf("%s: transmit FIFO underrun", 974 sc->sc_dev.dv_xname); 975 976 thresh = sc->sc_tx_drain_thresh + 1; 977 if (thresh <= TXCFG_DRTH && 978 (thresh * 32) <= (SIP_TXFIFO_SIZE - 979 (sc->sc_tx_fill_thresh * 32))) { 980 printf("; increasing Tx drain " 981 "threshold to %u bytes\n", 982 thresh * 32); 983 sc->sc_tx_drain_thresh = thresh; 984 (void) sip_init(ifp); 985 } else { 986 (void) sip_init(ifp); 987 printf("\n"); 988 } 989 } 990 } 991 992 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 993 if (isr & ISR_PAUSE_ST) { 994 sc->sc_flags |= SIPF_PAUSED; 995 ifp->if_flags |= IFF_OACTIVE; 996 } 997 if (isr & ISR_PAUSE_END) { 998 sc->sc_flags &= ~SIPF_PAUSED; 999 ifp->if_flags &= ~IFF_OACTIVE; 1000 } 1001 } 1002 1003 if (isr & ISR_HIBERR) { 1004 #define PRINTERR(bit, str) \ 1005 if (isr & (bit)) \ 1006 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1007 PRINTERR(ISR_DPERR, "parity error"); 1008 PRINTERR(ISR_SSERR, "system error"); 1009 PRINTERR(ISR_RMABT, "master abort"); 1010 PRINTERR(ISR_RTABT, "target abort"); 1011 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1012 (void) sip_init(ifp); 1013 #undef PRINTERR 1014 } 1015 } 1016 1017 /* Try to get more packets going. */ 1018 sip_start(ifp); 1019 1020 return (handled); 1021 } 1022 1023 /* 1024 * sip_txintr: 1025 * 1026 * Helper; handle transmit interrupts. 1027 */ 1028 void 1029 sip_txintr(sc) 1030 struct sip_softc *sc; 1031 { 1032 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1033 struct sip_txsoft *txs; 1034 u_int32_t cmdsts; 1035 1036 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1037 ifp->if_flags &= ~IFF_OACTIVE; 1038 1039 /* 1040 * Go through our Tx list and free mbufs for those 1041 * frames which have been transmitted. 1042 */ 1043 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1044 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1045 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1046 1047 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1048 if (cmdsts & CMDSTS_OWN) 1049 break; 1050 1051 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1052 1053 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1054 1055 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1056 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1057 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1058 m_freem(txs->txs_mbuf); 1059 txs->txs_mbuf = NULL; 1060 1061 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1062 1063 /* 1064 * Check for errors and collisions. 1065 */ 1066 if (cmdsts & 1067 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1068 if (ifp->if_flags & IFF_DEBUG) { 1069 if (CMDSTS_Tx_ED) 1070 printf("%s: excessive deferral\n", 1071 sc->sc_dev.dv_xname); 1072 if (CMDSTS_Tx_EC) { 1073 printf("%s: excessive collisions\n", 1074 sc->sc_dev.dv_xname); 1075 ifp->if_collisions += 16; 1076 } 1077 } 1078 } else { 1079 /* Packet was transmitted successfully. */ 1080 ifp->if_opackets++; 1081 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1082 } 1083 } 1084 1085 /* 1086 * If there are no more pending transmissions, cancel the watchdog 1087 * timer. 1088 */ 1089 if (txs == NULL) 1090 ifp->if_timer = 0; 1091 } 1092 1093 /* 1094 * sip_rxintr: 1095 * 1096 * Helper; handle receive interrupts. 1097 */ 1098 void 1099 sip_rxintr(sc) 1100 struct sip_softc *sc; 1101 { 1102 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1103 struct sip_rxsoft *rxs; 1104 struct mbuf *m; 1105 u_int32_t cmdsts; 1106 int i, len; 1107 1108 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1109 rxs = &sc->sc_rxsoft[i]; 1110 1111 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1112 1113 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1114 1115 /* 1116 * NOTE: OWN is set if owned by _consumer_. We're the 1117 * consumer of the receive ring, so if the bit is clear, 1118 * we have processed all of the packets. 1119 */ 1120 if ((cmdsts & CMDSTS_OWN) == 0) { 1121 /* 1122 * We have processed all of the receive buffers. 1123 */ 1124 break; 1125 } 1126 1127 /* 1128 * If any collisions were seen on the wire, count one. 1129 */ 1130 if (cmdsts & CMDSTS_Rx_COL) 1131 ifp->if_collisions++; 1132 1133 /* 1134 * If an error occurred, update stats, clear the status 1135 * word, and leave the packet buffer in place. It will 1136 * simply be reused the next time the ring comes around. 1137 */ 1138 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_LONG|CMDSTS_Rx_RUNT| 1139 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1140 ifp->if_ierrors++; 1141 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1142 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1143 /* Receive overrun handled elsewhere. */ 1144 printf("%s: receive descriptor error\n", 1145 sc->sc_dev.dv_xname); 1146 } 1147 #define PRINTERR(bit, str) \ 1148 if (cmdsts & (bit)) \ 1149 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1150 PRINTERR(CMDSTS_Rx_LONG, "packet too long"); 1151 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1152 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1153 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1154 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1155 #undef PRINTERR 1156 SIP_INIT_RXDESC(sc, i); 1157 continue; 1158 } 1159 1160 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1161 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1162 1163 /* 1164 * No errors; receive the packet. Note, the SiS 900 1165 * includes the CRC with every packet. 1166 */ 1167 len = CMDSTS_SIZE(cmdsts); 1168 1169 #ifdef __NO_STRICT_ALIGNMENT 1170 /* 1171 * If the packet is small enough to fit in a 1172 * single header mbuf, allocate one and copy 1173 * the data into it. This greatly reduces 1174 * memory consumption when we receive lots 1175 * of small packets. 1176 * 1177 * Otherwise, we add a new buffer to the receive 1178 * chain. If this fails, we drop the packet and 1179 * recycle the old buffer. 1180 */ 1181 if (sip_copy_small != 0 && len <= MHLEN) { 1182 MGETHDR(m, M_DONTWAIT, MT_DATA); 1183 if (m == NULL) 1184 goto dropit; 1185 memcpy(mtod(m, caddr_t), 1186 mtod(rxs->rxs_mbuf, caddr_t), len); 1187 SIP_INIT_RXDESC(sc, i); 1188 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1189 rxs->rxs_dmamap->dm_mapsize, 1190 BUS_DMASYNC_PREREAD); 1191 } else { 1192 m = rxs->rxs_mbuf; 1193 if (sip_add_rxbuf(sc, i) != 0) { 1194 dropit: 1195 ifp->if_ierrors++; 1196 SIP_INIT_RXDESC(sc, i); 1197 bus_dmamap_sync(sc->sc_dmat, 1198 rxs->rxs_dmamap, 0, 1199 rxs->rxs_dmamap->dm_mapsize, 1200 BUS_DMASYNC_PREREAD); 1201 continue; 1202 } 1203 } 1204 #else 1205 /* 1206 * The SiS 900's receive buffers must be 4-byte aligned. 1207 * But this means that the data after the Ethernet header 1208 * is misaligned. We must allocate a new buffer and 1209 * copy the data, shifted forward 2 bytes. 1210 */ 1211 MGETHDR(m, M_DONTWAIT, MT_DATA); 1212 if (m == NULL) { 1213 dropit: 1214 ifp->if_ierrors++; 1215 SIP_INIT_RXDESC(sc, i); 1216 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1217 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1218 continue; 1219 } 1220 if (len > (MHLEN - 2)) { 1221 MCLGET(m, M_DONTWAIT); 1222 if ((m->m_flags & M_EXT) == 0) { 1223 m_freem(m); 1224 goto dropit; 1225 } 1226 } 1227 m->m_data += 2; 1228 1229 /* 1230 * Note that we use clusters for incoming frames, so the 1231 * buffer is virtually contiguous. 1232 */ 1233 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 1234 1235 /* Allow the receive descriptor to continue using its mbuf. */ 1236 SIP_INIT_RXDESC(sc, i); 1237 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1238 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1239 #endif /* __NO_STRICT_ALIGNMENT */ 1240 1241 ifp->if_ipackets++; 1242 m->m_flags |= M_HASFCS; 1243 m->m_pkthdr.rcvif = ifp; 1244 m->m_pkthdr.len = m->m_len = len; 1245 1246 #if NBPFILTER > 0 1247 /* 1248 * Pass this up to any BPF listeners, but only 1249 * pass if up the stack if it's for us. 1250 */ 1251 if (ifp->if_bpf) 1252 bpf_mtap(ifp->if_bpf, m); 1253 #endif /* NBPFILTER > 0 */ 1254 1255 /* Pass it on. */ 1256 (*ifp->if_input)(ifp, m); 1257 } 1258 1259 /* Update the receive pointer. */ 1260 sc->sc_rxptr = i; 1261 } 1262 1263 /* 1264 * sip_tick: 1265 * 1266 * One second timer, used to tick the MII. 1267 */ 1268 void 1269 sip_tick(arg) 1270 void *arg; 1271 { 1272 struct sip_softc *sc = arg; 1273 int s; 1274 1275 s = splnet(); 1276 mii_tick(&sc->sc_mii); 1277 splx(s); 1278 1279 callout_reset(&sc->sc_tick_ch, hz, sip_tick, sc); 1280 } 1281 1282 /* 1283 * sip_reset: 1284 * 1285 * Perform a soft reset on the SiS 900. 1286 */ 1287 void 1288 sip_reset(sc) 1289 struct sip_softc *sc; 1290 { 1291 bus_space_tag_t st = sc->sc_st; 1292 bus_space_handle_t sh = sc->sc_sh; 1293 int i; 1294 1295 bus_space_write_4(st, sh, SIP_CR, CR_RST); 1296 1297 for (i = 0; i < SIP_TIMEOUT; i++) { 1298 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 1299 break; 1300 delay(2); 1301 } 1302 1303 if (i == SIP_TIMEOUT) 1304 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1305 1306 delay(1000); 1307 } 1308 1309 /* 1310 * sip_init: [ ifnet interface function ] 1311 * 1312 * Initialize the interface. Must be called at splnet(). 1313 */ 1314 int 1315 sip_init(ifp) 1316 struct ifnet *ifp; 1317 { 1318 struct sip_softc *sc = ifp->if_softc; 1319 bus_space_tag_t st = sc->sc_st; 1320 bus_space_handle_t sh = sc->sc_sh; 1321 struct sip_txsoft *txs; 1322 struct sip_rxsoft *rxs; 1323 struct sip_desc *sipd; 1324 u_int32_t cfg; 1325 int i, error = 0; 1326 1327 /* 1328 * Cancel any pending I/O. 1329 */ 1330 sip_stop(ifp, 0); 1331 1332 /* 1333 * Reset the chip to a known state. 1334 */ 1335 sip_reset(sc); 1336 1337 if ( sc->sc_model->sip_vendor == PCI_VENDOR_NS 1338 && sc->sc_model->sip_product == PCI_PRODUCT_NS_DP83815) { 1339 /* 1340 * DP83815 manual, page 78: 1341 * 4.4 Recommended Registers Configuration 1342 * For optimum performance of the DP83815, version noted 1343 * as DP83815CVNG (SRR = 203h), the listed register 1344 * modifications must be followed in sequence... 1345 * 1346 * It's not clear if this should be 302h or 203h because that 1347 * chip name is listed as SRR 302h in the description of the 1348 * SRR register. However, my revision 302h DP83815 on the 1349 * Netgear FA311 purchased in 02/2001 needs these settings 1350 * to avoid tons of errors in AcceptPerfectMatch (non- 1351 * IFF_PROMISC) mode. I do not know if other revisions need 1352 * this set or not. [briggs -- 09 March 2001] 1353 * 1354 * Note that only the low-order 12 bits of 0xe4 are documented 1355 * and that this sets reserved bits in that register. 1356 */ 1357 cfg = bus_space_read_4(st, sh, SIP_NS_SRR); 1358 if (cfg == 0x302) { 1359 bus_space_write_4(st, sh, 0x00cc, 0x0001); 1360 bus_space_write_4(st, sh, 0x00e4, 0x189C); 1361 bus_space_write_4(st, sh, 0x00fc, 0x0000); 1362 bus_space_write_4(st, sh, 0x00f4, 0x5040); 1363 bus_space_write_4(st, sh, 0x00f8, 0x008c); 1364 } 1365 } 1366 1367 /* 1368 * Initialize the transmit descriptor ring. 1369 */ 1370 for (i = 0; i < SIP_NTXDESC; i++) { 1371 sipd = &sc->sc_txdescs[i]; 1372 memset(sipd, 0, sizeof(struct sip_desc)); 1373 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 1374 } 1375 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 1376 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1377 sc->sc_txfree = SIP_NTXDESC; 1378 sc->sc_txnext = 0; 1379 1380 /* 1381 * Initialize the transmit job descriptors. 1382 */ 1383 SIMPLEQ_INIT(&sc->sc_txfreeq); 1384 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1385 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1386 txs = &sc->sc_txsoft[i]; 1387 txs->txs_mbuf = NULL; 1388 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1389 } 1390 1391 /* 1392 * Initialize the receive descriptor and receive job 1393 * descriptor rings. 1394 */ 1395 for (i = 0; i < SIP_NRXDESC; i++) { 1396 rxs = &sc->sc_rxsoft[i]; 1397 if (rxs->rxs_mbuf == NULL) { 1398 if ((error = sip_add_rxbuf(sc, i)) != 0) { 1399 printf("%s: unable to allocate or map rx " 1400 "buffer %d, error = %d\n", 1401 sc->sc_dev.dv_xname, i, error); 1402 /* 1403 * XXX Should attempt to run with fewer receive 1404 * XXX buffers instead of just failing. 1405 */ 1406 sip_rxdrain(sc); 1407 goto out; 1408 } 1409 } 1410 } 1411 sc->sc_rxptr = 0; 1412 1413 /* 1414 * Initialize the configuration register: aggressive PCI 1415 * bus request algorithm, default backoff, default OW timer, 1416 * default parity error detection. 1417 */ 1418 cfg = 0; 1419 #if BYTE_ORDER == BIG_ENDIAN 1420 /* 1421 * ...descriptors in big-endian mode. 1422 */ 1423 #if 0 1424 /* "Big endian mode" does not work properly. */ 1425 cfg |= CFG_BEM; 1426 #endif 1427 #endif 1428 bus_space_write_4(st, sh, SIP_CFG, cfg); 1429 1430 /* 1431 * Initialize the transmit fill and drain thresholds if 1432 * we have never done so. 1433 */ 1434 if (sc->sc_tx_fill_thresh == 0) { 1435 /* 1436 * XXX This value should be tuned. This is the 1437 * minimum (32 bytes), and we may be able to 1438 * improve performance by increasing it. 1439 */ 1440 sc->sc_tx_fill_thresh = 1; 1441 } 1442 if (sc->sc_tx_drain_thresh == 0) { 1443 /* 1444 * Start at a drain threshold of 512 bytes. We will 1445 * increase it if a DMA underrun occurs. 1446 * 1447 * XXX The minimum value of this variable should be 1448 * tuned. We may be able to improve performance 1449 * by starting with a lower value. That, however, 1450 * may trash the first few outgoing packets if the 1451 * PCI bus is saturated. 1452 */ 1453 sc->sc_tx_drain_thresh = 512 / 32; 1454 } 1455 1456 /* 1457 * Initialize the prototype TXCFG register. 1458 */ 1459 sc->sc_txcfg = TXCFG_ATP | TXCFG_MXDMA_512 | 1460 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 1461 sc->sc_tx_drain_thresh; 1462 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 1463 1464 /* 1465 * Initialize the receive drain threshold if we have never 1466 * done so. 1467 */ 1468 if (sc->sc_rx_drain_thresh == 0) { 1469 /* 1470 * XXX This value should be tuned. This is set to the 1471 * maximum of 248 bytes, and we may be able to improve 1472 * performance by decreasing it (although we should never 1473 * set this value lower than 2; 14 bytes are required to 1474 * filter the packet). 1475 */ 1476 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 1477 } 1478 1479 /* 1480 * Initialize the prototype RXCFG register. 1481 */ 1482 sc->sc_rxcfg = RXCFG_MXDMA_512 | 1483 (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 1484 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 1485 1486 /* Set up the receive filter. */ 1487 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1488 1489 /* 1490 * Give the transmit and receive rings to the chip. 1491 */ 1492 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 1493 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1494 1495 /* 1496 * Initialize the interrupt mask. 1497 */ 1498 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 1499 ISR_TXURN|ISR_TXDESC|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 1500 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 1501 1502 /* 1503 * Set the current media. Do this after initializing the prototype 1504 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 1505 * control. 1506 */ 1507 mii_mediachg(&sc->sc_mii); 1508 1509 /* 1510 * Enable interrupts. 1511 */ 1512 bus_space_write_4(st, sh, SIP_IER, IER_IE); 1513 1514 /* 1515 * Start the transmit and receive processes. 1516 */ 1517 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 1518 1519 /* 1520 * Start the one second MII clock. 1521 */ 1522 callout_reset(&sc->sc_tick_ch, hz, sip_tick, sc); 1523 1524 /* 1525 * ...all done! 1526 */ 1527 ifp->if_flags |= IFF_RUNNING; 1528 ifp->if_flags &= ~IFF_OACTIVE; 1529 1530 out: 1531 if (error) 1532 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1533 return (error); 1534 } 1535 1536 /* 1537 * sip_drain: 1538 * 1539 * Drain the receive queue. 1540 */ 1541 void 1542 sip_rxdrain(sc) 1543 struct sip_softc *sc; 1544 { 1545 struct sip_rxsoft *rxs; 1546 int i; 1547 1548 for (i = 0; i < SIP_NRXDESC; i++) { 1549 rxs = &sc->sc_rxsoft[i]; 1550 if (rxs->rxs_mbuf != NULL) { 1551 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1552 m_freem(rxs->rxs_mbuf); 1553 rxs->rxs_mbuf = NULL; 1554 } 1555 } 1556 } 1557 1558 /* 1559 * sip_stop: [ ifnet interface function ] 1560 * 1561 * Stop transmission on the interface. 1562 */ 1563 void 1564 sip_stop(ifp, disable) 1565 struct ifnet *ifp; 1566 int disable; 1567 { 1568 struct sip_softc *sc = ifp->if_softc; 1569 bus_space_tag_t st = sc->sc_st; 1570 bus_space_handle_t sh = sc->sc_sh; 1571 struct sip_txsoft *txs; 1572 u_int32_t cmdsts = 0; /* DEBUG */ 1573 1574 /* 1575 * Stop the one second clock. 1576 */ 1577 callout_stop(&sc->sc_tick_ch); 1578 1579 /* Down the MII. */ 1580 mii_down(&sc->sc_mii); 1581 1582 /* 1583 * Disable interrupts. 1584 */ 1585 bus_space_write_4(st, sh, SIP_IER, 0); 1586 1587 /* 1588 * Stop receiver and transmitter. 1589 */ 1590 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 1591 1592 /* 1593 * Release any queued transmit buffers. 1594 */ 1595 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1596 if ((ifp->if_flags & IFF_DEBUG) != 0 && 1597 SIMPLEQ_NEXT(txs, txs_q) == NULL && 1598 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 1599 CMDSTS_INTR) == 0) 1600 printf("%s: sip_stop: last descriptor does not " 1601 "have INTR bit set\n", sc->sc_dev.dv_xname); 1602 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1603 #ifdef DIAGNOSTIC 1604 if (txs->txs_mbuf == NULL) { 1605 printf("%s: dirty txsoft with no mbuf chain\n", 1606 sc->sc_dev.dv_xname); 1607 panic("sip_stop"); 1608 } 1609 #endif 1610 cmdsts |= /* DEBUG */ 1611 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1612 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1613 m_freem(txs->txs_mbuf); 1614 txs->txs_mbuf = NULL; 1615 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1616 } 1617 1618 if (disable) 1619 sip_rxdrain(sc); 1620 1621 /* 1622 * Mark the interface down and cancel the watchdog timer. 1623 */ 1624 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1625 ifp->if_timer = 0; 1626 1627 if ((ifp->if_flags & IFF_DEBUG) != 0 && 1628 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 1629 printf("%s: sip_stop: no INTR bits set in dirty tx " 1630 "descriptors\n", sc->sc_dev.dv_xname); 1631 } 1632 1633 /* 1634 * sip_read_eeprom: 1635 * 1636 * Read data from the serial EEPROM. 1637 */ 1638 void 1639 sip_read_eeprom(sc, word, wordcnt, data) 1640 struct sip_softc *sc; 1641 int word, wordcnt; 1642 u_int16_t *data; 1643 { 1644 bus_space_tag_t st = sc->sc_st; 1645 bus_space_handle_t sh = sc->sc_sh; 1646 u_int16_t reg; 1647 int i, x; 1648 1649 for (i = 0; i < wordcnt; i++) { 1650 /* Send CHIP SELECT. */ 1651 reg = EROMAR_EECS; 1652 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1653 1654 /* Shift in the READ opcode. */ 1655 for (x = 3; x > 0; x--) { 1656 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 1657 reg |= EROMAR_EEDI; 1658 else 1659 reg &= ~EROMAR_EEDI; 1660 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1661 bus_space_write_4(st, sh, SIP_EROMAR, 1662 reg | EROMAR_EESK); 1663 delay(4); 1664 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1665 delay(4); 1666 } 1667 1668 /* Shift in address. */ 1669 for (x = 6; x > 0; x--) { 1670 if ((word + i) & (1 << (x - 1))) 1671 reg |= EROMAR_EEDI; 1672 else 1673 reg &= ~EROMAR_EEDI; 1674 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1675 bus_space_write_4(st, sh, SIP_EROMAR, 1676 reg | EROMAR_EESK); 1677 delay(4); 1678 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1679 delay(4); 1680 } 1681 1682 /* Shift out data. */ 1683 reg = EROMAR_EECS; 1684 data[i] = 0; 1685 for (x = 16; x > 0; x--) { 1686 bus_space_write_4(st, sh, SIP_EROMAR, 1687 reg | EROMAR_EESK); 1688 delay(4); 1689 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 1690 data[i] |= (1 << (x - 1)); 1691 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1692 delay(4); 1693 } 1694 1695 /* Clear CHIP SELECT. */ 1696 bus_space_write_4(st, sh, SIP_EROMAR, 0); 1697 delay(4); 1698 } 1699 } 1700 1701 /* 1702 * sip_add_rxbuf: 1703 * 1704 * Add a receive buffer to the indicated descriptor. 1705 */ 1706 int 1707 sip_add_rxbuf(sc, idx) 1708 struct sip_softc *sc; 1709 int idx; 1710 { 1711 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1712 struct mbuf *m; 1713 int error; 1714 1715 MGETHDR(m, M_DONTWAIT, MT_DATA); 1716 if (m == NULL) 1717 return (ENOBUFS); 1718 1719 MCLGET(m, M_DONTWAIT); 1720 if ((m->m_flags & M_EXT) == 0) { 1721 m_freem(m); 1722 return (ENOBUFS); 1723 } 1724 1725 if (rxs->rxs_mbuf != NULL) 1726 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1727 1728 rxs->rxs_mbuf = m; 1729 1730 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1731 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1732 if (error) { 1733 printf("%s: can't load rx DMA map %d, error = %d\n", 1734 sc->sc_dev.dv_xname, idx, error); 1735 panic("sip_add_rxbuf"); /* XXX */ 1736 } 1737 1738 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1739 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1740 1741 SIP_INIT_RXDESC(sc, idx); 1742 1743 return (0); 1744 } 1745 1746 /* 1747 * sip_sis900_set_filter: 1748 * 1749 * Set up the receive filter. 1750 */ 1751 void 1752 sip_sis900_set_filter(sc) 1753 struct sip_softc *sc; 1754 { 1755 bus_space_tag_t st = sc->sc_st; 1756 bus_space_handle_t sh = sc->sc_sh; 1757 struct ethercom *ec = &sc->sc_ethercom; 1758 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1759 struct ether_multi *enm; 1760 u_int8_t *cp; 1761 struct ether_multistep step; 1762 u_int32_t crc, mchash[8]; 1763 1764 /* 1765 * Initialize the prototype RFCR. 1766 */ 1767 sc->sc_rfcr = RFCR_RFEN; 1768 if (ifp->if_flags & IFF_BROADCAST) 1769 sc->sc_rfcr |= RFCR_AAB; 1770 if (ifp->if_flags & IFF_PROMISC) { 1771 sc->sc_rfcr |= RFCR_AAP; 1772 goto allmulti; 1773 } 1774 1775 /* 1776 * Set up the multicast address filter by passing all multicast 1777 * addresses through a CRC generator, and then using the high-order 1778 * 6 bits as an index into the 128 bit multicast hash table (only 1779 * the lower 16 bits of each 32 bit multicast hash register are 1780 * valid). The high order bits select the register, while the 1781 * rest of the bits select the bit within the register. 1782 */ 1783 1784 memset(mchash, 0, sizeof(mchash)); 1785 1786 ETHER_FIRST_MULTI(step, ec, enm); 1787 while (enm != NULL) { 1788 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1789 /* 1790 * We must listen to a range of multicast addresses. 1791 * For now, just accept all multicasts, rather than 1792 * trying to set only those filter bits needed to match 1793 * the range. (At this time, the only use of address 1794 * ranges is for IP multicast routing, for which the 1795 * range is big enough to require all bits set.) 1796 */ 1797 goto allmulti; 1798 } 1799 1800 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1801 1802 /* Just want the 7 most significant bits. */ 1803 crc >>= 25; 1804 1805 /* Set the corresponding bit in the hash table. */ 1806 mchash[crc >> 4] |= 1 << (crc & 0xf); 1807 1808 ETHER_NEXT_MULTI(step, enm); 1809 } 1810 1811 ifp->if_flags &= ~IFF_ALLMULTI; 1812 goto setit; 1813 1814 allmulti: 1815 ifp->if_flags |= IFF_ALLMULTI; 1816 sc->sc_rfcr |= RFCR_AAM; 1817 1818 setit: 1819 #define FILTER_EMIT(addr, data) \ 1820 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 1821 delay(1); \ 1822 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 1823 delay(1) 1824 1825 /* 1826 * Disable receive filter, and program the node address. 1827 */ 1828 cp = LLADDR(ifp->if_sadl); 1829 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 1830 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 1831 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 1832 1833 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1834 /* 1835 * Program the multicast hash table. 1836 */ 1837 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 1838 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 1839 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 1840 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 1841 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 1842 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 1843 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 1844 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 1845 } 1846 #undef FILTER_EMIT 1847 1848 /* 1849 * Re-enable the receiver filter. 1850 */ 1851 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 1852 } 1853 1854 /* 1855 * sip_dp83815_set_filter: 1856 * 1857 * Set up the receive filter. 1858 */ 1859 void 1860 sip_dp83815_set_filter(sc) 1861 struct sip_softc *sc; 1862 { 1863 bus_space_tag_t st = sc->sc_st; 1864 bus_space_handle_t sh = sc->sc_sh; 1865 struct ethercom *ec = &sc->sc_ethercom; 1866 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1867 struct ether_multi *enm; 1868 u_int8_t *cp; 1869 struct ether_multistep step; 1870 u_int32_t crc, mchash[16]; 1871 int i; 1872 1873 /* 1874 * Initialize the prototype RFCR. 1875 * Enable the receive filter, and accept on 1876 * Perfect (destination address) Match 1877 * If IFF_BROADCAST, also accept all broadcast packets. 1878 * If IFF_PROMISC, accept all unicast packets (and later, set 1879 * IFF_ALLMULTI and accept all multicast, too). 1880 */ 1881 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 1882 if (ifp->if_flags & IFF_BROADCAST) 1883 sc->sc_rfcr |= RFCR_AAB; 1884 if (ifp->if_flags & IFF_PROMISC) { 1885 sc->sc_rfcr |= RFCR_AAP; 1886 goto allmulti; 1887 } 1888 1889 /* 1890 * Set up the multicast address filter by passing all multicast 1891 * addresses through a CRC generator, and then using the high-order 1892 * 9 bits as an index into the 512 bit multicast hash table. The 1893 * high-order bits select the slot, while the rest of the bits 1894 * select the bit within the slot. Note that only the low 16-bits 1895 * of each filter word are used, and there are 64 filter words. 1896 */ 1897 1898 memset(mchash, 0, sizeof(mchash)); 1899 1900 ifp->if_flags &= ~IFF_ALLMULTI; 1901 ETHER_FIRST_MULTI(step, ec, enm); 1902 if (enm != NULL) { 1903 while (enm != NULL) { 1904 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1905 ETHER_ADDR_LEN)) { 1906 /* 1907 * We must listen to a range of multicast addresses. 1908 * For now, just accept all multicasts, rather than 1909 * trying to set only those filter bits needed to match 1910 * the range. (At this time, the only use of address 1911 * ranges is for IP multicast routing, for which the 1912 * range is big enough to require all bits set.) 1913 */ 1914 goto allmulti; 1915 } 1916 1917 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1918 1919 /* Just want the 9 most significant bits. */ 1920 crc >>= 23; 1921 1922 /* Set the corresponding bit in the hash table. */ 1923 mchash[crc >> 5] |= 1 << (crc & 0x1f); 1924 1925 ETHER_NEXT_MULTI(step, enm); 1926 } 1927 1928 sc->sc_rfcr |= RFCR_MHEN; 1929 } 1930 goto setit; 1931 1932 allmulti: 1933 ifp->if_flags |= IFF_ALLMULTI; 1934 sc->sc_rfcr |= RFCR_AAM; 1935 1936 setit: 1937 #define FILTER_EMIT(addr, data) \ 1938 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 1939 delay(1); \ 1940 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 1941 delay(1); 1942 1943 /* 1944 * Disable receive filter, and program the node address. 1945 */ 1946 cp = LLADDR(ifp->if_sadl); 1947 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 1948 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 1949 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 1950 1951 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1952 /* 1953 * Program the multicast hash table. 1954 */ 1955 for (i = 0; i < 16; i++) { 1956 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 1957 mchash[i] & 0xffff); 1958 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2) + 2, 1959 (mchash[i] >> 16) & 0xffff); 1960 } 1961 } 1962 #undef FILTER_EMIT 1963 1964 /* 1965 * Re-enable the receiver filter. 1966 */ 1967 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 1968 } 1969 1970 /* 1971 * sip_sis900_mii_readreg: [mii interface function] 1972 * 1973 * Read a PHY register on the MII. 1974 */ 1975 int 1976 sip_sis900_mii_readreg(self, phy, reg) 1977 struct device *self; 1978 int phy, reg; 1979 { 1980 struct sip_softc *sc = (struct sip_softc *) self; 1981 u_int32_t enphy; 1982 1983 /* 1984 * The SiS 900 has only an internal PHY on the MII. Only allow 1985 * MII address 0. 1986 */ 1987 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 1988 return (0); 1989 1990 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 1991 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 1992 ENPHY_RWCMD | ENPHY_ACCESS); 1993 do { 1994 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 1995 } while (enphy & ENPHY_ACCESS); 1996 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 1997 } 1998 1999 /* 2000 * sip_sis900_mii_writereg: [mii interface function] 2001 * 2002 * Write a PHY register on the MII. 2003 */ 2004 void 2005 sip_sis900_mii_writereg(self, phy, reg, val) 2006 struct device *self; 2007 int phy, reg, val; 2008 { 2009 struct sip_softc *sc = (struct sip_softc *) self; 2010 u_int32_t enphy; 2011 2012 /* 2013 * The SiS 900 has only an internal PHY on the MII. Only allow 2014 * MII address 0. 2015 */ 2016 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 2017 return; 2018 2019 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2020 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 2021 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 2022 do { 2023 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2024 } while (enphy & ENPHY_ACCESS); 2025 } 2026 2027 /* 2028 * sip_sis900_mii_statchg: [mii interface function] 2029 * 2030 * Callback from MII layer when media changes. 2031 */ 2032 void 2033 sip_sis900_mii_statchg(self) 2034 struct device *self; 2035 { 2036 struct sip_softc *sc = (struct sip_softc *) self; 2037 u_int32_t flowctl; 2038 2039 /* 2040 * Update TXCFG for full-duplex operation. 2041 */ 2042 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2043 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2044 else 2045 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2046 2047 /* 2048 * Update RXCFG for full-duplex or loopback. 2049 */ 2050 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2051 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2052 sc->sc_rxcfg |= RXCFG_ATX; 2053 else 2054 sc->sc_rxcfg &= ~RXCFG_ATX; 2055 2056 /* 2057 * Update IMR for use of 802.3x flow control. 2058 */ 2059 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 2060 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 2061 flowctl = FLOWCTL_FLOWEN; 2062 } else { 2063 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 2064 flowctl = 0; 2065 } 2066 2067 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2068 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2069 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 2070 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 2071 } 2072 2073 /* 2074 * sip_dp83815_mii_readreg: [mii interface function] 2075 * 2076 * Read a PHY register on the MII. 2077 */ 2078 int 2079 sip_dp83815_mii_readreg(self, phy, reg) 2080 struct device *self; 2081 int phy, reg; 2082 { 2083 struct sip_softc *sc = (struct sip_softc *) self; 2084 u_int32_t val; 2085 2086 /* 2087 * The DP83815 only has an internal PHY. Only allow 2088 * MII address 0. 2089 */ 2090 if (phy != 0) 2091 return (0); 2092 2093 /* 2094 * Apparently, after a reset, the DP83815 can take a while 2095 * to respond. During this recovery period, the BMSR returns 2096 * a value of 0. Catch this -- it's not supposed to happen 2097 * (the BMSR has some hardcoded-to-1 bits), and wait for the 2098 * PHY to come back to life. 2099 * 2100 * This works out because the BMSR is the first register 2101 * read during the PHY probe process. 2102 */ 2103 do { 2104 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 2105 } while (reg == MII_BMSR && val == 0); 2106 2107 return (val & 0xffff); 2108 } 2109 2110 /* 2111 * sip_dp83815_mii_writereg: [mii interface function] 2112 * 2113 * Write a PHY register to the MII. 2114 */ 2115 void 2116 sip_dp83815_mii_writereg(self, phy, reg, val) 2117 struct device *self; 2118 int phy, reg, val; 2119 { 2120 struct sip_softc *sc = (struct sip_softc *) self; 2121 2122 /* 2123 * The DP83815 only has an internal PHY. Only allow 2124 * MII address 0. 2125 */ 2126 if (phy != 0) 2127 return; 2128 2129 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 2130 } 2131 2132 /* 2133 * sip_dp83815_mii_statchg: [mii interface function] 2134 * 2135 * Callback from MII layer when media changes. 2136 */ 2137 void 2138 sip_dp83815_mii_statchg(self) 2139 struct device *self; 2140 { 2141 struct sip_softc *sc = (struct sip_softc *) self; 2142 2143 /* 2144 * Update TXCFG for full-duplex operation. 2145 */ 2146 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2147 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2148 else 2149 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2150 2151 /* 2152 * Update RXCFG for full-duplex or loopback. 2153 */ 2154 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2155 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2156 sc->sc_rxcfg |= RXCFG_ATX; 2157 else 2158 sc->sc_rxcfg &= ~RXCFG_ATX; 2159 2160 /* 2161 * XXX 802.3x flow control. 2162 */ 2163 2164 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2165 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2166 } 2167 2168 void 2169 sip_sis900_read_macaddr(sc, enaddr) 2170 struct sip_softc *sc; 2171 u_int8_t *enaddr; 2172 { 2173 u_int16_t myea[ETHER_ADDR_LEN / 2]; 2174 2175 sip_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 2176 sizeof(myea) / sizeof(myea[0]), myea); 2177 2178 enaddr[0] = myea[0] & 0xff; 2179 enaddr[1] = myea[0] >> 8; 2180 enaddr[2] = myea[1] & 0xff; 2181 enaddr[3] = myea[1] >> 8; 2182 enaddr[4] = myea[2] & 0xff; 2183 enaddr[5] = myea[2] >> 8; 2184 } 2185 2186 static u_char bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 2187 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 2188 2189 void 2190 sip_dp83815_read_macaddr(sc, enaddr) 2191 struct sip_softc *sc; 2192 u_int8_t *enaddr; 2193 { 2194 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 2195 u_int8_t cksum, *e, match; 2196 int i; 2197 2198 sip_read_eeprom(sc, 0, sizeof(eeprom_data) / sizeof(eeprom_data[0]), 2199 eeprom_data); 2200 2201 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 2202 match = ~(match - 1); 2203 2204 cksum = 0x55; 2205 e = (u_int8_t *) eeprom_data; 2206 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 2207 cksum += *e++; 2208 } 2209 if (cksum != match) { 2210 printf("%s: Checksum (%x) mismatch (%x)", 2211 sc->sc_dev.dv_xname, cksum, match); 2212 } 2213 2214 /* 2215 * Unrolled because it makes slightly more sense this way. 2216 * The DP83815 stores the MAC address in bit 0 of word 6 2217 * through bit 15 of word 8. 2218 */ 2219 ea = &eeprom_data[6]; 2220 enaddr[0] = ((*ea & 0x1) << 7); 2221 ea++; 2222 enaddr[0] |= ((*ea & 0xFE00) >> 9); 2223 enaddr[1] = ((*ea & 0x1FE) >> 1); 2224 enaddr[2] = ((*ea & 0x1) << 7); 2225 ea++; 2226 enaddr[2] |= ((*ea & 0xFE00) >> 9); 2227 enaddr[3] = ((*ea & 0x1FE) >> 1); 2228 enaddr[4] = ((*ea & 0x1) << 7); 2229 ea++; 2230 enaddr[4] |= ((*ea & 0xFE00) >> 9); 2231 enaddr[5] = ((*ea & 0x1FE) >> 1); 2232 2233 /* 2234 * In case that's not weird enough, we also need to reverse 2235 * the bits in each byte. This all actually makes more sense 2236 * if you think about the EEPROM storage as an array of bits 2237 * being shifted into bytes, but that's not how we're looking 2238 * at it here... 2239 */ 2240 for (i=0 ; i<6 ; i++) 2241 enaddr[i] = bbr(enaddr[i]); 2242 } 2243 2244 /* 2245 * sip_mediastatus: [ifmedia interface function] 2246 * 2247 * Get the current interface media status. 2248 */ 2249 void 2250 sip_mediastatus(ifp, ifmr) 2251 struct ifnet *ifp; 2252 struct ifmediareq *ifmr; 2253 { 2254 struct sip_softc *sc = ifp->if_softc; 2255 2256 mii_pollstat(&sc->sc_mii); 2257 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2258 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2259 } 2260 2261 /* 2262 * sip_mediachange: [ifmedia interface function] 2263 * 2264 * Set hardware to newly-selected media. 2265 */ 2266 int 2267 sip_mediachange(ifp) 2268 struct ifnet *ifp; 2269 { 2270 struct sip_softc *sc = ifp->if_softc; 2271 2272 if (ifp->if_flags & IFF_UP) 2273 mii_mediachg(&sc->sc_mii); 2274 return (0); 2275 } 2276
Indexes created Tue Sep 30 11:09:46 GMT 2025