if_sip.c revision 1.28
1 /* $NetBSD: if_sip.c,v 1.28 2001/05/15 03:06:21 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900 and 70 * SiS 7016 10/100 PCI Ethernet controllers. 71 * 72 * Written by Jason R. Thorpe for Network Computer, Inc. 73 */ 74 75 #include "opt_inet.h" 76 #include "opt_ns.h" 77 #include "bpfilter.h" 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/callout.h> 82 #include <sys/mbuf.h> 83 #include <sys/malloc.h> 84 #include <sys/kernel.h> 85 #include <sys/socket.h> 86 #include <sys/ioctl.h> 87 #include <sys/errno.h> 88 #include <sys/device.h> 89 #include <sys/queue.h> 90 91 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 92 93 #include <net/if.h> 94 #include <net/if_dl.h> 95 #include <net/if_media.h> 96 #include <net/if_ether.h> 97 98 #if NBPFILTER > 0 99 #include <net/bpf.h> 100 #endif 101 102 #ifdef INET 103 #include <netinet/in.h> 104 #include <netinet/if_inarp.h> 105 #endif 106 107 #ifdef NS 108 #include <netns/ns.h> 109 #include <netns/ns_if.h> 110 #endif 111 112 #include <machine/bus.h> 113 #include <machine/intr.h> 114 #include <machine/endian.h> 115 116 #include <dev/mii/mii.h> 117 #include <dev/mii/miivar.h> 118 119 #include <dev/pci/pcireg.h> 120 #include <dev/pci/pcivar.h> 121 #include <dev/pci/pcidevs.h> 122 123 #include <dev/pci/if_sipreg.h> 124 125 #define SIP_DECL(x) __CONCAT(sip_,x) 126 #define SIP_STR(x) __STRING(SIP_DECL(x)) 127 128 /* 129 * Transmit descriptor list size. This is arbitrary, but allocate 130 * enough descriptors for 64 pending transmissions, and 16 segments 131 * per packet. This MUST work out to a power of 2. 132 */ 133 #define SIP_NTXSEGS 16 134 135 #define SIP_TXQUEUELEN 64 136 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS) 137 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 138 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 139 140 /* 141 * Receive descriptor list size. We have one Rx buffer per incoming 142 * packet, so this logic is a little simpler. 143 */ 144 #define SIP_NRXDESC 64 145 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 146 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 147 148 /* 149 * Control structures are DMA'd to the SiS900 chip. We allocate them in 150 * a single clump that maps to a single DMA segment to make several things 151 * easier. 152 */ 153 struct sip_control_data { 154 /* 155 * The transmit descriptors. 156 */ 157 struct sip_desc scd_txdescs[SIP_NTXDESC]; 158 159 /* 160 * The receive descriptors. 161 */ 162 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 163 }; 164 165 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 166 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 167 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 168 169 /* 170 * Software state for transmit jobs. 171 */ 172 struct sip_txsoft { 173 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 174 bus_dmamap_t txs_dmamap; /* our DMA map */ 175 int txs_firstdesc; /* first descriptor in packet */ 176 int txs_lastdesc; /* last descriptor in packet */ 177 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 178 }; 179 180 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 181 182 /* 183 * Software state for receive jobs. 184 */ 185 struct sip_rxsoft { 186 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 187 bus_dmamap_t rxs_dmamap; /* our DMA map */ 188 }; 189 190 /* 191 * Software state per device. 192 */ 193 struct sip_softc { 194 struct device sc_dev; /* generic device information */ 195 bus_space_tag_t sc_st; /* bus space tag */ 196 bus_space_handle_t sc_sh; /* bus space handle */ 197 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 198 struct ethercom sc_ethercom; /* ethernet common data */ 199 void *sc_sdhook; /* shutdown hook */ 200 201 const struct sip_product *sc_model; /* which model are we? */ 202 203 void *sc_ih; /* interrupt cookie */ 204 205 struct mii_data sc_mii; /* MII/media information */ 206 207 struct callout sc_tick_ch; /* tick callout */ 208 209 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 210 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 211 212 /* 213 * Software state for transmit and receive descriptors. 214 */ 215 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 216 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 217 218 /* 219 * Control data structures. 220 */ 221 struct sip_control_data *sc_control_data; 222 #define sc_txdescs sc_control_data->scd_txdescs 223 #define sc_rxdescs sc_control_data->scd_rxdescs 224 225 u_int32_t sc_txcfg; /* prototype TXCFG register */ 226 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 227 u_int32_t sc_imr; /* prototype IMR register */ 228 u_int32_t sc_rfcr; /* prototype RFCR register */ 229 230 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 231 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 232 233 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 234 235 int sc_flags; /* misc. flags; see below */ 236 237 int sc_txfree; /* number of free Tx descriptors */ 238 int sc_txnext; /* next ready Tx descriptor */ 239 240 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 241 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 242 243 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 244 }; 245 246 /* sc_flags */ 247 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 248 249 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 250 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 251 252 #define SIP_CDTXSYNC(sc, x, n, ops) \ 253 do { \ 254 int __x, __n; \ 255 \ 256 __x = (x); \ 257 __n = (n); \ 258 \ 259 /* If it will wrap around, sync to the end of the ring. */ \ 260 if ((__x + __n) > SIP_NTXDESC) { \ 261 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 262 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 263 (SIP_NTXDESC - __x), (ops)); \ 264 __n -= (SIP_NTXDESC - __x); \ 265 __x = 0; \ 266 } \ 267 \ 268 /* Now sync whatever is left. */ \ 269 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 270 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 271 } while (0) 272 273 #define SIP_CDRXSYNC(sc, x, ops) \ 274 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 275 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 276 277 /* 278 * Note we rely on MCLBYTES being a power of two below. 279 */ 280 #define SIP_INIT_RXDESC(sc, x) \ 281 do { \ 282 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 283 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 284 \ 285 __sipd->sipd_link = htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 286 __sipd->sipd_bufptr = htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 287 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 288 ((MCLBYTES - 1) & CMDSTS_SIZE_MASK)); \ 289 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 290 } while (0) 291 292 #define SIP_TIMEOUT 1000 293 294 void SIP_DECL(start)(struct ifnet *); 295 void SIP_DECL(watchdog)(struct ifnet *); 296 int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 297 int SIP_DECL(init)(struct ifnet *); 298 void SIP_DECL(stop)(struct ifnet *, int); 299 300 void SIP_DECL(shutdown)(void *); 301 302 void SIP_DECL(reset)(struct sip_softc *); 303 void SIP_DECL(rxdrain)(struct sip_softc *); 304 int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 305 void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, u_int16_t *); 306 void SIP_DECL(tick)(void *); 307 308 void SIP_DECL(sis900_set_filter)(struct sip_softc *); 309 void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 310 311 void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, u_int8_t *); 312 void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, u_int8_t *); 313 314 int SIP_DECL(intr)(void *); 315 void SIP_DECL(txintr)(struct sip_softc *); 316 void SIP_DECL(rxintr)(struct sip_softc *); 317 318 int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 319 void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 320 void SIP_DECL(sis900_mii_statchg)(struct device *); 321 322 int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 323 void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 324 void SIP_DECL(dp83815_mii_statchg)(struct device *); 325 326 int SIP_DECL(mediachange)(struct ifnet *); 327 void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 328 329 int SIP_DECL(match)(struct device *, struct cfdata *, void *); 330 void SIP_DECL(attach)(struct device *, struct device *, void *); 331 332 int SIP_DECL(copy_small) = 0; 333 334 struct cfattach SIP_DECL(ca) = { 335 sizeof(struct sip_softc), SIP_DECL(match), SIP_DECL(attach), 336 }; 337 338 /* 339 * Descriptions of the variants of the SiS900. 340 */ 341 struct sip_variant { 342 int (*sipv_mii_readreg)(struct device *, int, int); 343 void (*sipv_mii_writereg)(struct device *, int, int, int); 344 void (*sipv_mii_statchg)(struct device *); 345 void (*sipv_set_filter)(struct sip_softc *); 346 void (*sipv_read_macaddr)(struct sip_softc *, u_int8_t *); 347 }; 348 349 const struct sip_variant SIP_DECL(variant_sis900) = { 350 SIP_DECL(sis900_mii_readreg), 351 SIP_DECL(sis900_mii_writereg), 352 SIP_DECL(sis900_mii_statchg), 353 SIP_DECL(sis900_set_filter), 354 SIP_DECL(sis900_read_macaddr), 355 }; 356 357 const struct sip_variant SIP_DECL(variant_dp83815) = { 358 SIP_DECL(dp83815_mii_readreg), 359 SIP_DECL(dp83815_mii_writereg), 360 SIP_DECL(dp83815_mii_statchg), 361 SIP_DECL(dp83815_set_filter), 362 SIP_DECL(dp83815_read_macaddr), 363 }; 364 365 /* 366 * Devices supported by this driver. 367 */ 368 const struct sip_product { 369 pci_vendor_id_t sip_vendor; 370 pci_product_id_t sip_product; 371 const char *sip_name; 372 const struct sip_variant *sip_variant; 373 } SIP_DECL(products)[] = { 374 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 375 "SiS 900 10/100 Ethernet", 376 &SIP_DECL(variant_sis900) }, 377 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 378 "SiS 7016 10/100 Ethernet", 379 &SIP_DECL(variant_sis900) }, 380 381 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 382 "NatSemi DP83815 10/100 Ethernet", 383 &SIP_DECL(variant_dp83815) }, 384 385 { 0, 0, 386 NULL, 387 NULL }, 388 }; 389 390 static const struct sip_product * 391 sip_lookup(const struct pci_attach_args *pa) 392 { 393 const struct sip_product *sip; 394 395 for (sip = sip_products; sip->sip_name != NULL; sip++) { 396 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 397 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 398 return (sip); 399 } 400 return (NULL); 401 } 402 403 int 404 sip_match(struct device *parent, struct cfdata *cf, void *aux) 405 { 406 struct pci_attach_args *pa = aux; 407 408 if (sip_lookup(pa) != NULL) 409 return (1); 410 411 return (0); 412 } 413 414 void 415 sip_attach(struct device *parent, struct device *self, void *aux) 416 { 417 struct sip_softc *sc = (struct sip_softc *) self; 418 struct pci_attach_args *pa = aux; 419 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 420 pci_chipset_tag_t pc = pa->pa_pc; 421 pci_intr_handle_t ih; 422 const char *intrstr = NULL; 423 bus_space_tag_t iot, memt; 424 bus_space_handle_t ioh, memh; 425 bus_dma_segment_t seg; 426 int ioh_valid, memh_valid; 427 int i, rseg, error; 428 const struct sip_product *sip; 429 pcireg_t pmode; 430 u_int8_t enaddr[ETHER_ADDR_LEN]; 431 int pmreg; 432 433 callout_init(&sc->sc_tick_ch); 434 435 sip = SIP_DECL(lookup)(pa); 436 if (sip == NULL) { 437 printf("\n"); 438 panic(SIP_STR(attach) ": impossible"); 439 } 440 441 printf(": %s\n", sip->sip_name); 442 443 sc->sc_model = sip; 444 445 /* 446 * Map the device. 447 */ 448 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 449 PCI_MAPREG_TYPE_IO, 0, 450 &iot, &ioh, NULL, NULL) == 0); 451 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 452 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 453 &memt, &memh, NULL, NULL) == 0); 454 455 if (memh_valid) { 456 sc->sc_st = memt; 457 sc->sc_sh = memh; 458 } else if (ioh_valid) { 459 sc->sc_st = iot; 460 sc->sc_sh = ioh; 461 } else { 462 printf("%s: unable to map device registers\n", 463 sc->sc_dev.dv_xname); 464 return; 465 } 466 467 sc->sc_dmat = pa->pa_dmat; 468 469 /* Enable bus mastering. */ 470 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 471 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 472 PCI_COMMAND_MASTER_ENABLE); 473 474 /* Get it out of power save mode if needed. */ 475 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 476 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 477 if (pmode == 3) { 478 /* 479 * The card has lost all configuration data in 480 * this state, so punt. 481 */ 482 printf("%s: unable to wake up from power state D3\n", 483 sc->sc_dev.dv_xname); 484 return; 485 } 486 if (pmode != 0) { 487 printf("%s: waking up from power state D%d\n", 488 sc->sc_dev.dv_xname, pmode); 489 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 490 } 491 } 492 493 /* 494 * Map and establish our interrupt. 495 */ 496 if (pci_intr_map(pa, &ih)) { 497 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 498 return; 499 } 500 intrstr = pci_intr_string(pc, ih); 501 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sip_intr, sc); 502 if (sc->sc_ih == NULL) { 503 printf("%s: unable to establish interrupt", 504 sc->sc_dev.dv_xname); 505 if (intrstr != NULL) 506 printf(" at %s", intrstr); 507 printf("\n"); 508 return; 509 } 510 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 511 512 SIMPLEQ_INIT(&sc->sc_txfreeq); 513 SIMPLEQ_INIT(&sc->sc_txdirtyq); 514 515 /* 516 * Allocate the control data structures, and create and load the 517 * DMA map for it. 518 */ 519 if ((error = bus_dmamem_alloc(sc->sc_dmat, 520 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 521 0)) != 0) { 522 printf("%s: unable to allocate control data, error = %d\n", 523 sc->sc_dev.dv_xname, error); 524 goto fail_0; 525 } 526 527 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 528 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 529 BUS_DMA_COHERENT)) != 0) { 530 printf("%s: unable to map control data, error = %d\n", 531 sc->sc_dev.dv_xname, error); 532 goto fail_1; 533 } 534 535 if ((error = bus_dmamap_create(sc->sc_dmat, 536 sizeof(struct sip_control_data), 1, 537 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 538 printf("%s: unable to create control data DMA map, " 539 "error = %d\n", sc->sc_dev.dv_xname, error); 540 goto fail_2; 541 } 542 543 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 544 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 545 0)) != 0) { 546 printf("%s: unable to load control data DMA map, error = %d\n", 547 sc->sc_dev.dv_xname, error); 548 goto fail_3; 549 } 550 551 /* 552 * Create the transmit buffer DMA maps. 553 */ 554 for (i = 0; i < SIP_TXQUEUELEN; i++) { 555 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 556 SIP_NTXSEGS, MCLBYTES, 0, 0, 557 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 558 printf("%s: unable to create tx DMA map %d, " 559 "error = %d\n", sc->sc_dev.dv_xname, i, error); 560 goto fail_4; 561 } 562 } 563 564 /* 565 * Create the receive buffer DMA maps. 566 */ 567 for (i = 0; i < SIP_NRXDESC; i++) { 568 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 569 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 570 printf("%s: unable to create rx DMA map %d, " 571 "error = %d\n", sc->sc_dev.dv_xname, i, error); 572 goto fail_5; 573 } 574 sc->sc_rxsoft[i].rxs_mbuf = NULL; 575 } 576 577 /* 578 * Reset the chip to a known state. 579 */ 580 sip_reset(sc); 581 582 /* 583 * Read the Ethernet address from the EEPROM. 584 */ 585 (*sip->sip_variant->sipv_read_macaddr)(sc, enaddr); 586 587 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 588 ether_sprintf(enaddr)); 589 590 /* 591 * Initialize our media structures and probe the MII. 592 */ 593 sc->sc_mii.mii_ifp = ifp; 594 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 595 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 596 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 597 ifmedia_init(&sc->sc_mii.mii_media, 0, sip_mediachange, 598 sip_mediastatus); 599 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 600 MII_OFFSET_ANY, 0); 601 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 602 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 603 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 604 } else 605 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 606 607 ifp = &sc->sc_ethercom.ec_if; 608 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 609 ifp->if_softc = sc; 610 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 611 ifp->if_ioctl = SIP_DECL(ioctl); 612 ifp->if_start = SIP_DECL(start); 613 ifp->if_watchdog = SIP_DECL(watchdog); 614 ifp->if_init = SIP_DECL(init); 615 ifp->if_stop = SIP_DECL(stop); 616 IFQ_SET_READY(&ifp->if_snd); 617 618 /* 619 * Attach the interface. 620 */ 621 if_attach(ifp); 622 ether_ifattach(ifp, enaddr); 623 624 /* 625 * Make sure the interface is shutdown during reboot. 626 */ 627 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 628 if (sc->sc_sdhook == NULL) 629 printf("%s: WARNING: unable to establish shutdown hook\n", 630 sc->sc_dev.dv_xname); 631 return; 632 633 /* 634 * Free any resources we've allocated during the failed attach 635 * attempt. Do this in reverse order and fall through. 636 */ 637 fail_5: 638 for (i = 0; i < SIP_NRXDESC; i++) { 639 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 640 bus_dmamap_destroy(sc->sc_dmat, 641 sc->sc_rxsoft[i].rxs_dmamap); 642 } 643 fail_4: 644 for (i = 0; i < SIP_TXQUEUELEN; i++) { 645 if (sc->sc_txsoft[i].txs_dmamap != NULL) 646 bus_dmamap_destroy(sc->sc_dmat, 647 sc->sc_txsoft[i].txs_dmamap); 648 } 649 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 650 fail_3: 651 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 652 fail_2: 653 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 654 sizeof(struct sip_control_data)); 655 fail_1: 656 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 657 fail_0: 658 return; 659 } 660 661 /* 662 * sip_shutdown: 663 * 664 * Make sure the interface is stopped at reboot time. 665 */ 666 void 667 SIP_DECL(shutdown)(void *arg) 668 { 669 struct sip_softc *sc = arg; 670 671 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 672 } 673 674 /* 675 * sip_start: [ifnet interface function] 676 * 677 * Start packet transmission on the interface. 678 */ 679 void 680 SIP_DECL(start)(struct ifnet *ifp) 681 { 682 struct sip_softc *sc = ifp->if_softc; 683 struct mbuf *m0, *m; 684 struct sip_txsoft *txs; 685 bus_dmamap_t dmamap; 686 int error, firsttx, nexttx, lasttx, ofree, seg; 687 688 /* 689 * If we've been told to pause, don't transmit any more packets. 690 */ 691 if (sc->sc_flags & SIPF_PAUSED) 692 ifp->if_flags |= IFF_OACTIVE; 693 694 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 695 return; 696 697 /* 698 * Remember the previous number of free descriptors and 699 * the first descriptor we'll use. 700 */ 701 ofree = sc->sc_txfree; 702 firsttx = sc->sc_txnext; 703 704 /* 705 * Loop through the send queue, setting up transmit descriptors 706 * until we drain the queue, or use up all available transmit 707 * descriptors. 708 */ 709 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 710 sc->sc_txfree != 0) { 711 /* 712 * Grab a packet off the queue. 713 */ 714 IFQ_POLL(&ifp->if_snd, m0); 715 if (m0 == NULL) 716 break; 717 m = NULL; 718 719 dmamap = txs->txs_dmamap; 720 721 /* 722 * Load the DMA map. If this fails, the packet either 723 * didn't fit in the alloted number of segments, or we 724 * were short on resources. In this case, we'll copy 725 * and try again. 726 */ 727 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 728 BUS_DMA_NOWAIT) != 0) { 729 MGETHDR(m, M_DONTWAIT, MT_DATA); 730 if (m == NULL) { 731 printf("%s: unable to allocate Tx mbuf\n", 732 sc->sc_dev.dv_xname); 733 break; 734 } 735 if (m0->m_pkthdr.len > MHLEN) { 736 MCLGET(m, M_DONTWAIT); 737 if ((m->m_flags & M_EXT) == 0) { 738 printf("%s: unable to allocate Tx " 739 "cluster\n", sc->sc_dev.dv_xname); 740 m_freem(m); 741 break; 742 } 743 } 744 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 745 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 746 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 747 m, BUS_DMA_NOWAIT); 748 if (error) { 749 printf("%s: unable to load Tx buffer, " 750 "error = %d\n", sc->sc_dev.dv_xname, error); 751 break; 752 } 753 } 754 755 /* 756 * Ensure we have enough descriptors free to describe 757 * the packet. 758 */ 759 if (dmamap->dm_nsegs > sc->sc_txfree) { 760 /* 761 * Not enough free descriptors to transmit this 762 * packet. We haven't committed anything yet, 763 * so just unload the DMA map, put the packet 764 * back on the queue, and punt. Notify the upper 765 * layer that there are not more slots left. 766 * 767 * XXX We could allocate an mbuf and copy, but 768 * XXX is it worth it? 769 */ 770 ifp->if_flags |= IFF_OACTIVE; 771 bus_dmamap_unload(sc->sc_dmat, dmamap); 772 if (m != NULL) 773 m_freem(m); 774 break; 775 } 776 777 IFQ_DEQUEUE(&ifp->if_snd, m0); 778 if (m != NULL) { 779 m_freem(m0); 780 m0 = m; 781 } 782 783 /* 784 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 785 */ 786 787 /* Sync the DMA map. */ 788 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 789 BUS_DMASYNC_PREWRITE); 790 791 /* 792 * Initialize the transmit descriptors. 793 */ 794 for (nexttx = sc->sc_txnext, seg = 0; 795 seg < dmamap->dm_nsegs; 796 seg++, nexttx = SIP_NEXTTX(nexttx)) { 797 /* 798 * If this is the first descriptor we're 799 * enqueueing, don't set the OWN bit just 800 * yet. That could cause a race condition. 801 * We'll do it below. 802 */ 803 sc->sc_txdescs[nexttx].sipd_bufptr = 804 htole32(dmamap->dm_segs[seg].ds_addr); 805 sc->sc_txdescs[nexttx].sipd_cmdsts = 806 htole32((nexttx == firsttx ? 0 : CMDSTS_OWN) | 807 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 808 lasttx = nexttx; 809 } 810 811 /* Clear the MORE bit on the last segment. */ 812 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 813 814 /* Sync the descriptors we're using. */ 815 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 816 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 817 818 /* 819 * Store a pointer to the packet so we can free it later, 820 * and remember what txdirty will be once the packet is 821 * done. 822 */ 823 txs->txs_mbuf = m0; 824 txs->txs_firstdesc = sc->sc_txnext; 825 txs->txs_lastdesc = lasttx; 826 827 /* Advance the tx pointer. */ 828 sc->sc_txfree -= dmamap->dm_nsegs; 829 sc->sc_txnext = nexttx; 830 831 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs, txs_q); 832 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 833 834 #if NBPFILTER > 0 835 /* 836 * Pass the packet to any BPF listeners. 837 */ 838 if (ifp->if_bpf) 839 bpf_mtap(ifp->if_bpf, m0); 840 #endif /* NBPFILTER > 0 */ 841 } 842 843 if (txs == NULL || sc->sc_txfree == 0) { 844 /* No more slots left; notify upper layer. */ 845 ifp->if_flags |= IFF_OACTIVE; 846 } 847 848 if (sc->sc_txfree != ofree) { 849 /* 850 * Cause a descriptor interrupt to happen on the 851 * last packet we enqueued. 852 */ 853 sc->sc_txdescs[lasttx].sipd_cmdsts |= htole32(CMDSTS_INTR); 854 SIP_CDTXSYNC(sc, lasttx, 1, 855 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 856 857 /* 858 * The entire packet chain is set up. Give the 859 * first descrptor to the chip now. 860 */ 861 sc->sc_txdescs[firsttx].sipd_cmdsts |= htole32(CMDSTS_OWN); 862 SIP_CDTXSYNC(sc, firsttx, 1, 863 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 864 865 /* Start the transmit process. */ 866 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 867 CR_TXE) == 0) { 868 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 869 SIP_CDTXADDR(sc, firsttx)); 870 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 871 } 872 873 /* Set a watchdog timer in case the chip flakes out. */ 874 ifp->if_timer = 5; 875 } 876 } 877 878 /* 879 * sip_watchdog: [ifnet interface function] 880 * 881 * Watchdog timer handler. 882 */ 883 void 884 SIP_DECL(watchdog)(struct ifnet *ifp) 885 { 886 struct sip_softc *sc = ifp->if_softc; 887 888 /* 889 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 890 * If we get a timeout, try and sweep up transmit descriptors. 891 * If we manage to sweep them all up, ignore the lack of 892 * interrupt. 893 */ 894 SIP_DECL(txintr)(sc); 895 896 if (sc->sc_txfree != SIP_NTXDESC) { 897 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 898 ifp->if_oerrors++; 899 900 /* Reset the interface. */ 901 (void) SIP_DECL(init)(ifp); 902 } else if (ifp->if_flags & IFF_DEBUG) 903 printf("%s: recovered from device timeout\n", 904 sc->sc_dev.dv_xname); 905 906 /* Try to get more packets going. */ 907 SIP_DECL(start)(ifp); 908 } 909 910 /* 911 * sip_ioctl: [ifnet interface function] 912 * 913 * Handle control requests from the operator. 914 */ 915 int 916 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 917 { 918 struct sip_softc *sc = ifp->if_softc; 919 struct ifreq *ifr = (struct ifreq *)data; 920 int s, error; 921 922 s = splnet(); 923 924 switch (cmd) { 925 case SIOCSIFMEDIA: 926 case SIOCGIFMEDIA: 927 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 928 break; 929 930 default: 931 error = ether_ioctl(ifp, cmd, data); 932 if (error == ENETRESET) { 933 /* 934 * Multicast list has changed; set the hardware filter 935 * accordingly. 936 */ 937 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 938 error = 0; 939 } 940 break; 941 } 942 943 /* Try to get more packets going. */ 944 SIP_DECL(start)(ifp); 945 946 splx(s); 947 return (error); 948 } 949 950 /* 951 * sip_intr: 952 * 953 * Interrupt service routine. 954 */ 955 int 956 SIP_DECL(intr)(void *arg) 957 { 958 struct sip_softc *sc = arg; 959 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 960 u_int32_t isr; 961 int handled = 0; 962 963 for (;;) { 964 /* Reading clears interrupt. */ 965 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 966 if ((isr & sc->sc_imr) == 0) 967 break; 968 969 handled = 1; 970 971 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 972 /* Grab any new packets. */ 973 SIP_DECL(rxintr)(sc); 974 975 if (isr & ISR_RXORN) { 976 printf("%s: receive FIFO overrun\n", 977 sc->sc_dev.dv_xname); 978 979 /* XXX adjust rx_drain_thresh? */ 980 } 981 982 if (isr & ISR_RXIDLE) { 983 printf("%s: receive ring overrun\n", 984 sc->sc_dev.dv_xname); 985 986 /* Get the receive process going again. */ 987 bus_space_write_4(sc->sc_st, sc->sc_sh, 988 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 989 bus_space_write_4(sc->sc_st, sc->sc_sh, 990 SIP_CR, CR_RXE); 991 } 992 } 993 994 if (isr & (ISR_TXURN|ISR_TXDESC)) { 995 /* Sweep up transmit descriptors. */ 996 SIP_DECL(txintr)(sc); 997 998 if (isr & ISR_TXURN) { 999 u_int32_t thresh; 1000 1001 printf("%s: transmit FIFO underrun", 1002 sc->sc_dev.dv_xname); 1003 1004 thresh = sc->sc_tx_drain_thresh + 1; 1005 if (thresh <= TXCFG_DRTH && 1006 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1007 (sc->sc_tx_fill_thresh * 32))) { 1008 printf("; increasing Tx drain " 1009 "threshold to %u bytes\n", 1010 thresh * 32); 1011 sc->sc_tx_drain_thresh = thresh; 1012 (void) SIP_DECL(init)(ifp); 1013 } else { 1014 (void) SIP_DECL(init)(ifp); 1015 printf("\n"); 1016 } 1017 } 1018 } 1019 1020 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1021 if (isr & ISR_PAUSE_ST) { 1022 sc->sc_flags |= SIPF_PAUSED; 1023 ifp->if_flags |= IFF_OACTIVE; 1024 } 1025 if (isr & ISR_PAUSE_END) { 1026 sc->sc_flags &= ~SIPF_PAUSED; 1027 ifp->if_flags &= ~IFF_OACTIVE; 1028 } 1029 } 1030 1031 if (isr & ISR_HIBERR) { 1032 #define PRINTERR(bit, str) \ 1033 if (isr & (bit)) \ 1034 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1035 PRINTERR(ISR_DPERR, "parity error"); 1036 PRINTERR(ISR_SSERR, "system error"); 1037 PRINTERR(ISR_RMABT, "master abort"); 1038 PRINTERR(ISR_RTABT, "target abort"); 1039 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1040 (void) sip_init(ifp); 1041 #undef PRINTERR 1042 } 1043 } 1044 1045 /* Try to get more packets going. */ 1046 SIP_DECL(start)(ifp); 1047 1048 return (handled); 1049 } 1050 1051 /* 1052 * sip_txintr: 1053 * 1054 * Helper; handle transmit interrupts. 1055 */ 1056 void 1057 SIP_DECL(txintr)(struct sip_softc *sc) 1058 { 1059 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1060 struct sip_txsoft *txs; 1061 u_int32_t cmdsts; 1062 1063 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1064 ifp->if_flags &= ~IFF_OACTIVE; 1065 1066 /* 1067 * Go through our Tx list and free mbufs for those 1068 * frames which have been transmitted. 1069 */ 1070 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1071 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1072 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1073 1074 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1075 if (cmdsts & CMDSTS_OWN) 1076 break; 1077 1078 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1079 1080 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1081 1082 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1083 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1084 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1085 m_freem(txs->txs_mbuf); 1086 txs->txs_mbuf = NULL; 1087 1088 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1089 1090 /* 1091 * Check for errors and collisions. 1092 */ 1093 if (cmdsts & 1094 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1095 if (ifp->if_flags & IFF_DEBUG) { 1096 if (CMDSTS_Tx_ED) 1097 printf("%s: excessive deferral\n", 1098 sc->sc_dev.dv_xname); 1099 if (CMDSTS_Tx_EC) { 1100 printf("%s: excessive collisions\n", 1101 sc->sc_dev.dv_xname); 1102 ifp->if_collisions += 16; 1103 } 1104 } 1105 } else { 1106 /* Packet was transmitted successfully. */ 1107 ifp->if_opackets++; 1108 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1109 } 1110 } 1111 1112 /* 1113 * If there are no more pending transmissions, cancel the watchdog 1114 * timer. 1115 */ 1116 if (txs == NULL) 1117 ifp->if_timer = 0; 1118 } 1119 1120 /* 1121 * sip_rxintr: 1122 * 1123 * Helper; handle receive interrupts. 1124 */ 1125 void 1126 SIP_DECL(rxintr)(struct sip_softc *sc) 1127 { 1128 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1129 struct sip_rxsoft *rxs; 1130 struct mbuf *m; 1131 u_int32_t cmdsts; 1132 int i, len; 1133 1134 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1135 rxs = &sc->sc_rxsoft[i]; 1136 1137 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1138 1139 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1140 1141 /* 1142 * NOTE: OWN is set if owned by _consumer_. We're the 1143 * consumer of the receive ring, so if the bit is clear, 1144 * we have processed all of the packets. 1145 */ 1146 if ((cmdsts & CMDSTS_OWN) == 0) { 1147 /* 1148 * We have processed all of the receive buffers. 1149 */ 1150 break; 1151 } 1152 1153 /* 1154 * If any collisions were seen on the wire, count one. 1155 */ 1156 if (cmdsts & CMDSTS_Rx_COL) 1157 ifp->if_collisions++; 1158 1159 /* 1160 * If an error occurred, update stats, clear the status 1161 * word, and leave the packet buffer in place. It will 1162 * simply be reused the next time the ring comes around. 1163 */ 1164 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_LONG|CMDSTS_Rx_RUNT| 1165 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1166 ifp->if_ierrors++; 1167 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1168 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1169 /* Receive overrun handled elsewhere. */ 1170 printf("%s: receive descriptor error\n", 1171 sc->sc_dev.dv_xname); 1172 } 1173 #define PRINTERR(bit, str) \ 1174 if (cmdsts & (bit)) \ 1175 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1176 PRINTERR(CMDSTS_Rx_LONG, "packet too long"); 1177 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1178 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1179 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1180 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1181 #undef PRINTERR 1182 SIP_INIT_RXDESC(sc, i); 1183 continue; 1184 } 1185 1186 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1187 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1188 1189 /* 1190 * No errors; receive the packet. Note, the SiS 900 1191 * includes the CRC with every packet. 1192 */ 1193 len = CMDSTS_SIZE(cmdsts); 1194 1195 #ifdef __NO_STRICT_ALIGNMENT 1196 /* 1197 * If the packet is small enough to fit in a 1198 * single header mbuf, allocate one and copy 1199 * the data into it. This greatly reduces 1200 * memory consumption when we receive lots 1201 * of small packets. 1202 * 1203 * Otherwise, we add a new buffer to the receive 1204 * chain. If this fails, we drop the packet and 1205 * recycle the old buffer. 1206 */ 1207 if (sip_copy_small != 0 && len <= MHLEN) { 1208 MGETHDR(m, M_DONTWAIT, MT_DATA); 1209 if (m == NULL) 1210 goto dropit; 1211 memcpy(mtod(m, caddr_t), 1212 mtod(rxs->rxs_mbuf, caddr_t), len); 1213 SIP_INIT_RXDESC(sc, i); 1214 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1215 rxs->rxs_dmamap->dm_mapsize, 1216 BUS_DMASYNC_PREREAD); 1217 } else { 1218 m = rxs->rxs_mbuf; 1219 if (sip_add_rxbuf(sc, i) != 0) { 1220 dropit: 1221 ifp->if_ierrors++; 1222 SIP_INIT_RXDESC(sc, i); 1223 bus_dmamap_sync(sc->sc_dmat, 1224 rxs->rxs_dmamap, 0, 1225 rxs->rxs_dmamap->dm_mapsize, 1226 BUS_DMASYNC_PREREAD); 1227 continue; 1228 } 1229 } 1230 #else 1231 /* 1232 * The SiS 900's receive buffers must be 4-byte aligned. 1233 * But this means that the data after the Ethernet header 1234 * is misaligned. We must allocate a new buffer and 1235 * copy the data, shifted forward 2 bytes. 1236 */ 1237 MGETHDR(m, M_DONTWAIT, MT_DATA); 1238 if (m == NULL) { 1239 dropit: 1240 ifp->if_ierrors++; 1241 SIP_INIT_RXDESC(sc, i); 1242 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1243 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1244 continue; 1245 } 1246 if (len > (MHLEN - 2)) { 1247 MCLGET(m, M_DONTWAIT); 1248 if ((m->m_flags & M_EXT) == 0) { 1249 m_freem(m); 1250 goto dropit; 1251 } 1252 } 1253 m->m_data += 2; 1254 1255 /* 1256 * Note that we use clusters for incoming frames, so the 1257 * buffer is virtually contiguous. 1258 */ 1259 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 1260 1261 /* Allow the receive descriptor to continue using its mbuf. */ 1262 SIP_INIT_RXDESC(sc, i); 1263 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1264 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1265 #endif /* __NO_STRICT_ALIGNMENT */ 1266 1267 ifp->if_ipackets++; 1268 m->m_flags |= M_HASFCS; 1269 m->m_pkthdr.rcvif = ifp; 1270 m->m_pkthdr.len = m->m_len = len; 1271 1272 #if NBPFILTER > 0 1273 /* 1274 * Pass this up to any BPF listeners, but only 1275 * pass if up the stack if it's for us. 1276 */ 1277 if (ifp->if_bpf) 1278 bpf_mtap(ifp->if_bpf, m); 1279 #endif /* NBPFILTER > 0 */ 1280 1281 /* Pass it on. */ 1282 (*ifp->if_input)(ifp, m); 1283 } 1284 1285 /* Update the receive pointer. */ 1286 sc->sc_rxptr = i; 1287 } 1288 1289 /* 1290 * sip_tick: 1291 * 1292 * One second timer, used to tick the MII. 1293 */ 1294 void 1295 SIP_DECL(tick)(void *arg) 1296 { 1297 struct sip_softc *sc = arg; 1298 int s; 1299 1300 s = splnet(); 1301 mii_tick(&sc->sc_mii); 1302 splx(s); 1303 1304 callout_reset(&sc->sc_tick_ch, hz, sip_tick, sc); 1305 } 1306 1307 /* 1308 * sip_reset: 1309 * 1310 * Perform a soft reset on the SiS 900. 1311 */ 1312 void 1313 SIP_DECL(reset)(struct sip_softc *sc) 1314 { 1315 bus_space_tag_t st = sc->sc_st; 1316 bus_space_handle_t sh = sc->sc_sh; 1317 int i; 1318 1319 bus_space_write_4(st, sh, SIP_CR, CR_RST); 1320 1321 for (i = 0; i < SIP_TIMEOUT; i++) { 1322 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 1323 break; 1324 delay(2); 1325 } 1326 1327 if (i == SIP_TIMEOUT) 1328 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1329 1330 delay(1000); 1331 } 1332 1333 /* 1334 * sip_init: [ ifnet interface function ] 1335 * 1336 * Initialize the interface. Must be called at splnet(). 1337 */ 1338 int 1339 SIP_DECL(init)(struct ifnet *ifp) 1340 { 1341 struct sip_softc *sc = ifp->if_softc; 1342 bus_space_tag_t st = sc->sc_st; 1343 bus_space_handle_t sh = sc->sc_sh; 1344 struct sip_txsoft *txs; 1345 struct sip_rxsoft *rxs; 1346 struct sip_desc *sipd; 1347 u_int32_t cfg; 1348 int i, error = 0; 1349 1350 /* 1351 * Cancel any pending I/O. 1352 */ 1353 SIP_DECL(stop)(ifp, 0); 1354 1355 /* 1356 * Reset the chip to a known state. 1357 */ 1358 SIP_DECL(reset)(sc); 1359 1360 if (sc->sc_model->sip_vendor == PCI_VENDOR_NS && 1361 sc->sc_model->sip_product == PCI_PRODUCT_NS_DP83815) { 1362 /* 1363 * DP83815 manual, page 78: 1364 * 4.4 Recommended Registers Configuration 1365 * For optimum performance of the DP83815, version noted 1366 * as DP83815CVNG (SRR = 203h), the listed register 1367 * modifications must be followed in sequence... 1368 * 1369 * It's not clear if this should be 302h or 203h because that 1370 * chip name is listed as SRR 302h in the description of the 1371 * SRR register. However, my revision 302h DP83815 on the 1372 * Netgear FA311 purchased in 02/2001 needs these settings 1373 * to avoid tons of errors in AcceptPerfectMatch (non- 1374 * IFF_PROMISC) mode. I do not know if other revisions need 1375 * this set or not. [briggs -- 09 March 2001] 1376 * 1377 * Note that only the low-order 12 bits of 0xe4 are documented 1378 * and that this sets reserved bits in that register. 1379 */ 1380 cfg = bus_space_read_4(st, sh, SIP_NS_SRR); 1381 if (cfg == 0x302) { 1382 bus_space_write_4(st, sh, 0x00cc, 0x0001); 1383 bus_space_write_4(st, sh, 0x00e4, 0x189C); 1384 bus_space_write_4(st, sh, 0x00fc, 0x0000); 1385 bus_space_write_4(st, sh, 0x00f4, 0x5040); 1386 bus_space_write_4(st, sh, 0x00f8, 0x008c); 1387 } 1388 } 1389 1390 /* 1391 * Initialize the transmit descriptor ring. 1392 */ 1393 for (i = 0; i < SIP_NTXDESC; i++) { 1394 sipd = &sc->sc_txdescs[i]; 1395 memset(sipd, 0, sizeof(struct sip_desc)); 1396 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 1397 } 1398 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 1399 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1400 sc->sc_txfree = SIP_NTXDESC; 1401 sc->sc_txnext = 0; 1402 1403 /* 1404 * Initialize the transmit job descriptors. 1405 */ 1406 SIMPLEQ_INIT(&sc->sc_txfreeq); 1407 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1408 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1409 txs = &sc->sc_txsoft[i]; 1410 txs->txs_mbuf = NULL; 1411 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1412 } 1413 1414 /* 1415 * Initialize the receive descriptor and receive job 1416 * descriptor rings. 1417 */ 1418 for (i = 0; i < SIP_NRXDESC; i++) { 1419 rxs = &sc->sc_rxsoft[i]; 1420 if (rxs->rxs_mbuf == NULL) { 1421 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 1422 printf("%s: unable to allocate or map rx " 1423 "buffer %d, error = %d\n", 1424 sc->sc_dev.dv_xname, i, error); 1425 /* 1426 * XXX Should attempt to run with fewer receive 1427 * XXX buffers instead of just failing. 1428 */ 1429 SIP_DECL(rxdrain)(sc); 1430 goto out; 1431 } 1432 } 1433 } 1434 sc->sc_rxptr = 0; 1435 1436 /* 1437 * Initialize the configuration register: aggressive PCI 1438 * bus request algorithm, default backoff, default OW timer, 1439 * default parity error detection. 1440 */ 1441 cfg = 0; 1442 #if BYTE_ORDER == BIG_ENDIAN 1443 /* 1444 * ...descriptors in big-endian mode. 1445 */ 1446 #if 0 1447 /* "Big endian mode" does not work properly. */ 1448 cfg |= CFG_BEM; 1449 #endif 1450 #endif 1451 bus_space_write_4(st, sh, SIP_CFG, cfg); 1452 1453 /* 1454 * Initialize the transmit fill and drain thresholds if 1455 * we have never done so. 1456 */ 1457 if (sc->sc_tx_fill_thresh == 0) { 1458 /* 1459 * XXX This value should be tuned. This is the 1460 * minimum (32 bytes), and we may be able to 1461 * improve performance by increasing it. 1462 */ 1463 sc->sc_tx_fill_thresh = 1; 1464 } 1465 if (sc->sc_tx_drain_thresh == 0) { 1466 /* 1467 * Start at a drain threshold of 512 bytes. We will 1468 * increase it if a DMA underrun occurs. 1469 * 1470 * XXX The minimum value of this variable should be 1471 * tuned. We may be able to improve performance 1472 * by starting with a lower value. That, however, 1473 * may trash the first few outgoing packets if the 1474 * PCI bus is saturated. 1475 */ 1476 sc->sc_tx_drain_thresh = 512 / 32; 1477 } 1478 1479 /* 1480 * Initialize the prototype TXCFG register. 1481 */ 1482 sc->sc_txcfg = TXCFG_ATP | TXCFG_MXDMA_512 | 1483 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 1484 sc->sc_tx_drain_thresh; 1485 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 1486 1487 /* 1488 * Initialize the receive drain threshold if we have never 1489 * done so. 1490 */ 1491 if (sc->sc_rx_drain_thresh == 0) { 1492 /* 1493 * XXX This value should be tuned. This is set to the 1494 * maximum of 248 bytes, and we may be able to improve 1495 * performance by decreasing it (although we should never 1496 * set this value lower than 2; 14 bytes are required to 1497 * filter the packet). 1498 */ 1499 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 1500 } 1501 1502 /* 1503 * Initialize the prototype RXCFG register. 1504 */ 1505 sc->sc_rxcfg = RXCFG_MXDMA_512 | 1506 (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 1507 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 1508 1509 /* Set up the receive filter. */ 1510 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1511 1512 /* 1513 * Give the transmit and receive rings to the chip. 1514 */ 1515 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 1516 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1517 1518 /* 1519 * Initialize the interrupt mask. 1520 */ 1521 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 1522 ISR_TXURN|ISR_TXDESC|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 1523 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 1524 1525 /* 1526 * Set the current media. Do this after initializing the prototype 1527 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 1528 * control. 1529 */ 1530 mii_mediachg(&sc->sc_mii); 1531 1532 /* 1533 * Enable interrupts. 1534 */ 1535 bus_space_write_4(st, sh, SIP_IER, IER_IE); 1536 1537 /* 1538 * Start the transmit and receive processes. 1539 */ 1540 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 1541 1542 /* 1543 * Start the one second MII clock. 1544 */ 1545 callout_reset(&sc->sc_tick_ch, hz, sip_tick, sc); 1546 1547 /* 1548 * ...all done! 1549 */ 1550 ifp->if_flags |= IFF_RUNNING; 1551 ifp->if_flags &= ~IFF_OACTIVE; 1552 1553 out: 1554 if (error) 1555 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1556 return (error); 1557 } 1558 1559 /* 1560 * sip_drain: 1561 * 1562 * Drain the receive queue. 1563 */ 1564 void 1565 SIP_DECL(rxdrain)(struct sip_softc *sc) 1566 { 1567 struct sip_rxsoft *rxs; 1568 int i; 1569 1570 for (i = 0; i < SIP_NRXDESC; i++) { 1571 rxs = &sc->sc_rxsoft[i]; 1572 if (rxs->rxs_mbuf != NULL) { 1573 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1574 m_freem(rxs->rxs_mbuf); 1575 rxs->rxs_mbuf = NULL; 1576 } 1577 } 1578 } 1579 1580 /* 1581 * sip_stop: [ ifnet interface function ] 1582 * 1583 * Stop transmission on the interface. 1584 */ 1585 void 1586 SIP_DECL(stop)(struct ifnet *ifp, int disable) 1587 { 1588 struct sip_softc *sc = ifp->if_softc; 1589 bus_space_tag_t st = sc->sc_st; 1590 bus_space_handle_t sh = sc->sc_sh; 1591 struct sip_txsoft *txs; 1592 u_int32_t cmdsts = 0; /* DEBUG */ 1593 1594 /* 1595 * Stop the one second clock. 1596 */ 1597 callout_stop(&sc->sc_tick_ch); 1598 1599 /* Down the MII. */ 1600 mii_down(&sc->sc_mii); 1601 1602 /* 1603 * Disable interrupts. 1604 */ 1605 bus_space_write_4(st, sh, SIP_IER, 0); 1606 1607 /* 1608 * Stop receiver and transmitter. 1609 */ 1610 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 1611 1612 /* 1613 * Release any queued transmit buffers. 1614 */ 1615 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1616 if ((ifp->if_flags & IFF_DEBUG) != 0 && 1617 SIMPLEQ_NEXT(txs, txs_q) == NULL && 1618 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 1619 CMDSTS_INTR) == 0) 1620 printf("%s: sip_stop: last descriptor does not " 1621 "have INTR bit set\n", sc->sc_dev.dv_xname); 1622 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1623 #ifdef DIAGNOSTIC 1624 if (txs->txs_mbuf == NULL) { 1625 printf("%s: dirty txsoft with no mbuf chain\n", 1626 sc->sc_dev.dv_xname); 1627 panic("sip_stop"); 1628 } 1629 #endif 1630 cmdsts |= /* DEBUG */ 1631 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1632 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1633 m_freem(txs->txs_mbuf); 1634 txs->txs_mbuf = NULL; 1635 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1636 } 1637 1638 if (disable) 1639 SIP_DECL(rxdrain)(sc); 1640 1641 /* 1642 * Mark the interface down and cancel the watchdog timer. 1643 */ 1644 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1645 ifp->if_timer = 0; 1646 1647 if ((ifp->if_flags & IFF_DEBUG) != 0 && 1648 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 1649 printf("%s: sip_stop: no INTR bits set in dirty tx " 1650 "descriptors\n", sc->sc_dev.dv_xname); 1651 } 1652 1653 /* 1654 * sip_read_eeprom: 1655 * 1656 * Read data from the serial EEPROM. 1657 */ 1658 void 1659 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 1660 u_int16_t *data) 1661 { 1662 bus_space_tag_t st = sc->sc_st; 1663 bus_space_handle_t sh = sc->sc_sh; 1664 u_int16_t reg; 1665 int i, x; 1666 1667 for (i = 0; i < wordcnt; i++) { 1668 /* Send CHIP SELECT. */ 1669 reg = EROMAR_EECS; 1670 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1671 1672 /* Shift in the READ opcode. */ 1673 for (x = 3; x > 0; x--) { 1674 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 1675 reg |= EROMAR_EEDI; 1676 else 1677 reg &= ~EROMAR_EEDI; 1678 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1679 bus_space_write_4(st, sh, SIP_EROMAR, 1680 reg | EROMAR_EESK); 1681 delay(4); 1682 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1683 delay(4); 1684 } 1685 1686 /* Shift in address. */ 1687 for (x = 6; x > 0; x--) { 1688 if ((word + i) & (1 << (x - 1))) 1689 reg |= EROMAR_EEDI; 1690 else 1691 reg &= ~EROMAR_EEDI; 1692 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1693 bus_space_write_4(st, sh, SIP_EROMAR, 1694 reg | EROMAR_EESK); 1695 delay(4); 1696 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1697 delay(4); 1698 } 1699 1700 /* Shift out data. */ 1701 reg = EROMAR_EECS; 1702 data[i] = 0; 1703 for (x = 16; x > 0; x--) { 1704 bus_space_write_4(st, sh, SIP_EROMAR, 1705 reg | EROMAR_EESK); 1706 delay(4); 1707 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 1708 data[i] |= (1 << (x - 1)); 1709 bus_space_write_4(st, sh, SIP_EROMAR, reg); 1710 delay(4); 1711 } 1712 1713 /* Clear CHIP SELECT. */ 1714 bus_space_write_4(st, sh, SIP_EROMAR, 0); 1715 delay(4); 1716 } 1717 } 1718 1719 /* 1720 * sip_add_rxbuf: 1721 * 1722 * Add a receive buffer to the indicated descriptor. 1723 */ 1724 int 1725 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 1726 { 1727 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1728 struct mbuf *m; 1729 int error; 1730 1731 MGETHDR(m, M_DONTWAIT, MT_DATA); 1732 if (m == NULL) 1733 return (ENOBUFS); 1734 1735 MCLGET(m, M_DONTWAIT); 1736 if ((m->m_flags & M_EXT) == 0) { 1737 m_freem(m); 1738 return (ENOBUFS); 1739 } 1740 1741 if (rxs->rxs_mbuf != NULL) 1742 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1743 1744 rxs->rxs_mbuf = m; 1745 1746 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1747 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1748 if (error) { 1749 printf("%s: can't load rx DMA map %d, error = %d\n", 1750 sc->sc_dev.dv_xname, idx, error); 1751 panic("sip_add_rxbuf"); /* XXX */ 1752 } 1753 1754 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1755 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1756 1757 SIP_INIT_RXDESC(sc, idx); 1758 1759 return (0); 1760 } 1761 1762 /* 1763 * sip_sis900_set_filter: 1764 * 1765 * Set up the receive filter. 1766 */ 1767 void 1768 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 1769 { 1770 bus_space_tag_t st = sc->sc_st; 1771 bus_space_handle_t sh = sc->sc_sh; 1772 struct ethercom *ec = &sc->sc_ethercom; 1773 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1774 struct ether_multi *enm; 1775 u_int8_t *cp; 1776 struct ether_multistep step; 1777 u_int32_t crc, mchash[8]; 1778 1779 /* 1780 * Initialize the prototype RFCR. 1781 */ 1782 sc->sc_rfcr = RFCR_RFEN; 1783 if (ifp->if_flags & IFF_BROADCAST) 1784 sc->sc_rfcr |= RFCR_AAB; 1785 if (ifp->if_flags & IFF_PROMISC) { 1786 sc->sc_rfcr |= RFCR_AAP; 1787 goto allmulti; 1788 } 1789 1790 /* 1791 * Set up the multicast address filter by passing all multicast 1792 * addresses through a CRC generator, and then using the high-order 1793 * 6 bits as an index into the 128 bit multicast hash table (only 1794 * the lower 16 bits of each 32 bit multicast hash register are 1795 * valid). The high order bits select the register, while the 1796 * rest of the bits select the bit within the register. 1797 */ 1798 1799 memset(mchash, 0, sizeof(mchash)); 1800 1801 ETHER_FIRST_MULTI(step, ec, enm); 1802 while (enm != NULL) { 1803 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1804 /* 1805 * We must listen to a range of multicast addresses. 1806 * For now, just accept all multicasts, rather than 1807 * trying to set only those filter bits needed to match 1808 * the range. (At this time, the only use of address 1809 * ranges is for IP multicast routing, for which the 1810 * range is big enough to require all bits set.) 1811 */ 1812 goto allmulti; 1813 } 1814 1815 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1816 1817 /* Just want the 7 most significant bits. */ 1818 crc >>= 25; 1819 1820 /* Set the corresponding bit in the hash table. */ 1821 mchash[crc >> 4] |= 1 << (crc & 0xf); 1822 1823 ETHER_NEXT_MULTI(step, enm); 1824 } 1825 1826 ifp->if_flags &= ~IFF_ALLMULTI; 1827 goto setit; 1828 1829 allmulti: 1830 ifp->if_flags |= IFF_ALLMULTI; 1831 sc->sc_rfcr |= RFCR_AAM; 1832 1833 setit: 1834 #define FILTER_EMIT(addr, data) \ 1835 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 1836 delay(1); \ 1837 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 1838 delay(1) 1839 1840 /* 1841 * Disable receive filter, and program the node address. 1842 */ 1843 cp = LLADDR(ifp->if_sadl); 1844 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 1845 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 1846 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 1847 1848 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1849 /* 1850 * Program the multicast hash table. 1851 */ 1852 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 1853 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 1854 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 1855 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 1856 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 1857 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 1858 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 1859 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 1860 } 1861 #undef FILTER_EMIT 1862 1863 /* 1864 * Re-enable the receiver filter. 1865 */ 1866 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 1867 } 1868 1869 /* 1870 * sip_dp83815_set_filter: 1871 * 1872 * Set up the receive filter. 1873 */ 1874 void 1875 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 1876 { 1877 bus_space_tag_t st = sc->sc_st; 1878 bus_space_handle_t sh = sc->sc_sh; 1879 struct ethercom *ec = &sc->sc_ethercom; 1880 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1881 struct ether_multi *enm; 1882 u_int8_t *cp; 1883 struct ether_multistep step; 1884 u_int32_t crc, mchash[16]; 1885 int i; 1886 1887 /* 1888 * Initialize the prototype RFCR. 1889 * Enable the receive filter, and accept on 1890 * Perfect (destination address) Match 1891 * If IFF_BROADCAST, also accept all broadcast packets. 1892 * If IFF_PROMISC, accept all unicast packets (and later, set 1893 * IFF_ALLMULTI and accept all multicast, too). 1894 */ 1895 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 1896 if (ifp->if_flags & IFF_BROADCAST) 1897 sc->sc_rfcr |= RFCR_AAB; 1898 if (ifp->if_flags & IFF_PROMISC) { 1899 sc->sc_rfcr |= RFCR_AAP; 1900 goto allmulti; 1901 } 1902 1903 /* 1904 * Set up the multicast address filter by passing all multicast 1905 * addresses through a CRC generator, and then using the high-order 1906 * 9 bits as an index into the 512 bit multicast hash table. The 1907 * high-order bits select the slot, while the rest of the bits 1908 * select the bit within the slot. Note that only the low 16-bits 1909 * of each filter word are used, and there are 64 filter words. 1910 */ 1911 1912 memset(mchash, 0, sizeof(mchash)); 1913 1914 ifp->if_flags &= ~IFF_ALLMULTI; 1915 ETHER_FIRST_MULTI(step, ec, enm); 1916 if (enm != NULL) { 1917 while (enm != NULL) { 1918 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1919 ETHER_ADDR_LEN)) { 1920 /* 1921 * We must listen to a range of multicast addresses. 1922 * For now, just accept all multicasts, rather than 1923 * trying to set only those filter bits needed to match 1924 * the range. (At this time, the only use of address 1925 * ranges is for IP multicast routing, for which the 1926 * range is big enough to require all bits set.) 1927 */ 1928 goto allmulti; 1929 } 1930 1931 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1932 1933 /* Just want the 9 most significant bits. */ 1934 crc >>= 23; 1935 1936 /* Set the corresponding bit in the hash table. */ 1937 mchash[crc >> 5] |= 1 << (crc & 0x1f); 1938 1939 ETHER_NEXT_MULTI(step, enm); 1940 } 1941 1942 sc->sc_rfcr |= RFCR_MHEN; 1943 } 1944 goto setit; 1945 1946 allmulti: 1947 ifp->if_flags |= IFF_ALLMULTI; 1948 sc->sc_rfcr |= RFCR_AAM; 1949 1950 setit: 1951 #define FILTER_EMIT(addr, data) \ 1952 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 1953 delay(1); \ 1954 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 1955 delay(1); 1956 1957 /* 1958 * Disable receive filter, and program the node address. 1959 */ 1960 cp = LLADDR(ifp->if_sadl); 1961 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 1962 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 1963 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 1964 1965 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1966 /* 1967 * Program the multicast hash table. 1968 */ 1969 for (i = 0; i < 16; i++) { 1970 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 1971 mchash[i] & 0xffff); 1972 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2) + 2, 1973 (mchash[i] >> 16) & 0xffff); 1974 } 1975 } 1976 #undef FILTER_EMIT 1977 1978 /* 1979 * Re-enable the receiver filter. 1980 */ 1981 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 1982 } 1983 1984 /* 1985 * sip_sis900_mii_readreg: [mii interface function] 1986 * 1987 * Read a PHY register on the MII. 1988 */ 1989 int 1990 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 1991 { 1992 struct sip_softc *sc = (struct sip_softc *) self; 1993 u_int32_t enphy; 1994 1995 /* 1996 * The SiS 900 has only an internal PHY on the MII. Only allow 1997 * MII address 0. 1998 */ 1999 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 2000 return (0); 2001 2002 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2003 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 2004 ENPHY_RWCMD | ENPHY_ACCESS); 2005 do { 2006 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2007 } while (enphy & ENPHY_ACCESS); 2008 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 2009 } 2010 2011 /* 2012 * sip_sis900_mii_writereg: [mii interface function] 2013 * 2014 * Write a PHY register on the MII. 2015 */ 2016 void 2017 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 2018 { 2019 struct sip_softc *sc = (struct sip_softc *) self; 2020 u_int32_t enphy; 2021 2022 /* 2023 * The SiS 900 has only an internal PHY on the MII. Only allow 2024 * MII address 0. 2025 */ 2026 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 2027 return; 2028 2029 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2030 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 2031 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 2032 do { 2033 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2034 } while (enphy & ENPHY_ACCESS); 2035 } 2036 2037 /* 2038 * sip_sis900_mii_statchg: [mii interface function] 2039 * 2040 * Callback from MII layer when media changes. 2041 */ 2042 void 2043 SIP_DECL(sis900_mii_statchg)(struct device *self) 2044 { 2045 struct sip_softc *sc = (struct sip_softc *) self; 2046 u_int32_t flowctl; 2047 2048 /* 2049 * Update TXCFG for full-duplex operation. 2050 */ 2051 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2052 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2053 else 2054 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2055 2056 /* 2057 * Update RXCFG for full-duplex or loopback. 2058 */ 2059 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2060 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2061 sc->sc_rxcfg |= RXCFG_ATX; 2062 else 2063 sc->sc_rxcfg &= ~RXCFG_ATX; 2064 2065 /* 2066 * Update IMR for use of 802.3x flow control. 2067 */ 2068 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 2069 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 2070 flowctl = FLOWCTL_FLOWEN; 2071 } else { 2072 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 2073 flowctl = 0; 2074 } 2075 2076 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2077 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2078 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 2079 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 2080 } 2081 2082 /* 2083 * sip_dp83815_mii_readreg: [mii interface function] 2084 * 2085 * Read a PHY register on the MII. 2086 */ 2087 int 2088 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 2089 { 2090 struct sip_softc *sc = (struct sip_softc *) self; 2091 u_int32_t val; 2092 2093 /* 2094 * The DP83815 only has an internal PHY. Only allow 2095 * MII address 0. 2096 */ 2097 if (phy != 0) 2098 return (0); 2099 2100 /* 2101 * Apparently, after a reset, the DP83815 can take a while 2102 * to respond. During this recovery period, the BMSR returns 2103 * a value of 0. Catch this -- it's not supposed to happen 2104 * (the BMSR has some hardcoded-to-1 bits), and wait for the 2105 * PHY to come back to life. 2106 * 2107 * This works out because the BMSR is the first register 2108 * read during the PHY probe process. 2109 */ 2110 do { 2111 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 2112 } while (reg == MII_BMSR && val == 0); 2113 2114 return (val & 0xffff); 2115 } 2116 2117 /* 2118 * sip_dp83815_mii_writereg: [mii interface function] 2119 * 2120 * Write a PHY register to the MII. 2121 */ 2122 void 2123 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 2124 { 2125 struct sip_softc *sc = (struct sip_softc *) self; 2126 2127 /* 2128 * The DP83815 only has an internal PHY. Only allow 2129 * MII address 0. 2130 */ 2131 if (phy != 0) 2132 return; 2133 2134 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 2135 } 2136 2137 /* 2138 * sip_dp83815_mii_statchg: [mii interface function] 2139 * 2140 * Callback from MII layer when media changes. 2141 */ 2142 void 2143 SIP_DECL(dp83815_mii_statchg)(struct device *self) 2144 { 2145 struct sip_softc *sc = (struct sip_softc *) self; 2146 2147 /* 2148 * Update TXCFG for full-duplex operation. 2149 */ 2150 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2151 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2152 else 2153 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2154 2155 /* 2156 * Update RXCFG for full-duplex or loopback. 2157 */ 2158 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2159 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2160 sc->sc_rxcfg |= RXCFG_ATX; 2161 else 2162 sc->sc_rxcfg &= ~RXCFG_ATX; 2163 2164 /* 2165 * XXX 802.3x flow control. 2166 */ 2167 2168 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2169 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2170 } 2171 2172 void 2173 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, u_int8_t *enaddr) 2174 { 2175 u_int16_t myea[ETHER_ADDR_LEN / 2]; 2176 2177 sip_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 2178 sizeof(myea) / sizeof(myea[0]), myea); 2179 2180 enaddr[0] = myea[0] & 0xff; 2181 enaddr[1] = myea[0] >> 8; 2182 enaddr[2] = myea[1] & 0xff; 2183 enaddr[3] = myea[1] >> 8; 2184 enaddr[4] = myea[2] & 0xff; 2185 enaddr[5] = myea[2] >> 8; 2186 } 2187 2188 static u_char bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 2189 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 2190 2191 void 2192 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, u_int8_t *enaddr) 2193 { 2194 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 2195 u_int8_t cksum, *e, match; 2196 int i; 2197 2198 sip_read_eeprom(sc, 0, sizeof(eeprom_data) / sizeof(eeprom_data[0]), 2199 eeprom_data); 2200 2201 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 2202 match = ~(match - 1); 2203 2204 cksum = 0x55; 2205 e = (u_int8_t *) eeprom_data; 2206 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 2207 cksum += *e++; 2208 } 2209 if (cksum != match) { 2210 printf("%s: Checksum (%x) mismatch (%x)", 2211 sc->sc_dev.dv_xname, cksum, match); 2212 } 2213 2214 /* 2215 * Unrolled because it makes slightly more sense this way. 2216 * The DP83815 stores the MAC address in bit 0 of word 6 2217 * through bit 15 of word 8. 2218 */ 2219 ea = &eeprom_data[6]; 2220 enaddr[0] = ((*ea & 0x1) << 7); 2221 ea++; 2222 enaddr[0] |= ((*ea & 0xFE00) >> 9); 2223 enaddr[1] = ((*ea & 0x1FE) >> 1); 2224 enaddr[2] = ((*ea & 0x1) << 7); 2225 ea++; 2226 enaddr[2] |= ((*ea & 0xFE00) >> 9); 2227 enaddr[3] = ((*ea & 0x1FE) >> 1); 2228 enaddr[4] = ((*ea & 0x1) << 7); 2229 ea++; 2230 enaddr[4] |= ((*ea & 0xFE00) >> 9); 2231 enaddr[5] = ((*ea & 0x1FE) >> 1); 2232 2233 /* 2234 * In case that's not weird enough, we also need to reverse 2235 * the bits in each byte. This all actually makes more sense 2236 * if you think about the EEPROM storage as an array of bits 2237 * being shifted into bytes, but that's not how we're looking 2238 * at it here... 2239 */ 2240 for (i = 0; i < 6 ;i++) 2241 enaddr[i] = bbr(enaddr[i]); 2242 } 2243 2244 /* 2245 * sip_mediastatus: [ifmedia interface function] 2246 * 2247 * Get the current interface media status. 2248 */ 2249 void 2250 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 2251 { 2252 struct sip_softc *sc = ifp->if_softc; 2253 2254 mii_pollstat(&sc->sc_mii); 2255 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2256 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2257 } 2258 2259 /* 2260 * sip_mediachange: [ifmedia interface function] 2261 * 2262 * Set hardware to newly-selected media. 2263 */ 2264 int 2265 SIP_DECL(mediachange)(struct ifnet *ifp) 2266 { 2267 struct sip_softc *sc = ifp->if_softc; 2268 2269 if (ifp->if_flags & IFF_UP) 2270 mii_mediachg(&sc->sc_mii); 2271 return (0); 2272 } 2273
Indexes created Sun Sep 21 20:09:37 GMT 2025