if_sip.c revision 1.31
1 /* $NetBSD: if_sip.c,v 1.31 2001/06/02 16:17:07 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written by Jason R. Thorpe for Network Computer, Inc. 75 * 76 * TODO: 77 * 78 * - Support the 10-bit interface on the DP83820 (for fiber). 79 * 80 * - Support jumbo packets on the DP83820. 81 * 82 * - Reduce the interrupt load. 83 */ 84 85 #include "opt_inet.h" 86 #include "opt_ns.h" 87 #include "bpfilter.h" 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/callout.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/ioctl.h> 97 #include <sys/errno.h> 98 #include <sys/device.h> 99 #include <sys/queue.h> 100 101 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 102 103 #include <net/if.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 #include <net/if_ether.h> 107 108 #if NBPFILTER > 0 109 #include <net/bpf.h> 110 #endif 111 112 #ifdef INET 113 #include <netinet/in.h> 114 #include <netinet/if_inarp.h> 115 #endif 116 117 #ifdef NS 118 #include <netns/ns.h> 119 #include <netns/ns_if.h> 120 #endif 121 122 #include <machine/bus.h> 123 #include <machine/intr.h> 124 #include <machine/endian.h> 125 126 #include <dev/mii/mii.h> 127 #include <dev/mii/miivar.h> 128 #ifdef DP83820 129 #include <dev/mii/mii_bitbang.h> 130 #endif /* DP83820 */ 131 132 #include <dev/pci/pcireg.h> 133 #include <dev/pci/pcivar.h> 134 #include <dev/pci/pcidevs.h> 135 136 #include <dev/pci/if_sipreg.h> 137 138 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 139 #define SIP_DECL(x) __CONCAT(gsip_,x) 140 #else /* SiS900 and DP83815 */ 141 #define SIP_DECL(x) __CONCAT(sip_,x) 142 #endif 143 144 #define SIP_STR(x) __STRING(SIP_DECL(x)) 145 146 /* 147 * Transmit descriptor list size. This is arbitrary, but allocate 148 * enough descriptors for 128 pending transmissions, and 8 segments 149 * per packet. This MUST work out to a power of 2. 150 */ 151 #define SIP_NTXSEGS 8 152 153 #define SIP_TXQUEUELEN 256 154 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS) 155 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 156 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 157 158 /* 159 * Receive descriptor list size. We have one Rx buffer per incoming 160 * packet, so this logic is a little simpler. 161 */ 162 #define SIP_NRXDESC 128 163 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 164 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 165 166 /* 167 * Control structures are DMA'd to the SiS900 chip. We allocate them in 168 * a single clump that maps to a single DMA segment to make several things 169 * easier. 170 */ 171 struct sip_control_data { 172 /* 173 * The transmit descriptors. 174 */ 175 struct sip_desc scd_txdescs[SIP_NTXDESC]; 176 177 /* 178 * The receive descriptors. 179 */ 180 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 181 }; 182 183 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 184 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 185 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 186 187 /* 188 * Software state for transmit jobs. 189 */ 190 struct sip_txsoft { 191 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 192 bus_dmamap_t txs_dmamap; /* our DMA map */ 193 int txs_firstdesc; /* first descriptor in packet */ 194 int txs_lastdesc; /* last descriptor in packet */ 195 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 196 }; 197 198 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 199 200 /* 201 * Software state for receive jobs. 202 */ 203 struct sip_rxsoft { 204 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 205 bus_dmamap_t rxs_dmamap; /* our DMA map */ 206 }; 207 208 /* 209 * Software state per device. 210 */ 211 struct sip_softc { 212 struct device sc_dev; /* generic device information */ 213 bus_space_tag_t sc_st; /* bus space tag */ 214 bus_space_handle_t sc_sh; /* bus space handle */ 215 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 216 struct ethercom sc_ethercom; /* ethernet common data */ 217 void *sc_sdhook; /* shutdown hook */ 218 219 const struct sip_product *sc_model; /* which model are we? */ 220 221 void *sc_ih; /* interrupt cookie */ 222 223 struct mii_data sc_mii; /* MII/media information */ 224 225 struct callout sc_tick_ch; /* tick callout */ 226 227 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 228 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 229 230 /* 231 * Software state for transmit and receive descriptors. 232 */ 233 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 234 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 235 236 /* 237 * Control data structures. 238 */ 239 struct sip_control_data *sc_control_data; 240 #define sc_txdescs sc_control_data->scd_txdescs 241 #define sc_rxdescs sc_control_data->scd_rxdescs 242 243 #ifdef SIP_EVENT_COUNTERS 244 /* 245 * Event counters. 246 */ 247 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 248 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 249 struct evcnt sc_ev_txintr; /* Tx interrupts */ 250 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 251 #ifdef DP83820 252 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 253 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 254 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 255 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 256 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 257 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 258 #endif /* DP83820 */ 259 #endif /* SIP_EVENT_COUNTERS */ 260 261 u_int32_t sc_txcfg; /* prototype TXCFG register */ 262 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 263 u_int32_t sc_imr; /* prototype IMR register */ 264 u_int32_t sc_rfcr; /* prototype RFCR register */ 265 266 u_int32_t sc_cfg; /* prototype CFG register */ 267 268 #ifdef DP83820 269 u_int32_t sc_gpior; /* prototype GPIOR register */ 270 #endif /* DP83820 */ 271 272 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 273 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 274 275 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 276 277 int sc_flags; /* misc. flags; see below */ 278 279 int sc_txfree; /* number of free Tx descriptors */ 280 int sc_txnext; /* next ready Tx descriptor */ 281 282 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 283 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 284 285 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 286 }; 287 288 /* sc_flags */ 289 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 290 291 #ifdef SIP_EVENT_COUNTERS 292 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 293 #else 294 #define SIP_EVCNT_INCR(ev) /* nothing */ 295 #endif 296 297 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 298 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 299 300 #define SIP_CDTXSYNC(sc, x, n, ops) \ 301 do { \ 302 int __x, __n; \ 303 \ 304 __x = (x); \ 305 __n = (n); \ 306 \ 307 /* If it will wrap around, sync to the end of the ring. */ \ 308 if ((__x + __n) > SIP_NTXDESC) { \ 309 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 310 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 311 (SIP_NTXDESC - __x), (ops)); \ 312 __n -= (SIP_NTXDESC - __x); \ 313 __x = 0; \ 314 } \ 315 \ 316 /* Now sync whatever is left. */ \ 317 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 318 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 319 } while (0) 320 321 #define SIP_CDRXSYNC(sc, x, ops) \ 322 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 323 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 324 325 /* 326 * Note we rely on MCLBYTES being a power of two below. 327 */ 328 #ifdef DP83820 329 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 330 #else 331 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 332 #endif 333 #define SIP_INIT_RXDESC(sc, x) \ 334 do { \ 335 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 336 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 337 \ 338 __sipd->sipd_link = htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 339 __sipd->sipd_bufptr = htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 340 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 341 ((MCLBYTES - 1) & CMDSTS_SIZE_MASK)); \ 342 SIP_INIT_RXDESC_EXTSTS \ 343 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 344 } while (0) 345 346 #define SIP_TIMEOUT 1000 347 348 void SIP_DECL(start)(struct ifnet *); 349 void SIP_DECL(watchdog)(struct ifnet *); 350 int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 351 int SIP_DECL(init)(struct ifnet *); 352 void SIP_DECL(stop)(struct ifnet *, int); 353 354 void SIP_DECL(shutdown)(void *); 355 356 void SIP_DECL(reset)(struct sip_softc *); 357 void SIP_DECL(rxdrain)(struct sip_softc *); 358 int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 359 void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, u_int16_t *); 360 void SIP_DECL(tick)(void *); 361 362 #if !defined(DP83820) 363 void SIP_DECL(sis900_set_filter)(struct sip_softc *); 364 #endif /* ! DP83820 */ 365 void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 366 367 #if defined(DP83820) 368 void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, u_int8_t *); 369 #else 370 void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, u_int8_t *); 371 void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, u_int8_t *); 372 #endif /* DP83820 */ 373 374 int SIP_DECL(intr)(void *); 375 void SIP_DECL(txintr)(struct sip_softc *); 376 void SIP_DECL(rxintr)(struct sip_softc *); 377 378 #if defined(DP83820) 379 int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 380 void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 381 void SIP_DECL(dp83820_mii_statchg)(struct device *); 382 #else 383 int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 384 void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 385 void SIP_DECL(sis900_mii_statchg)(struct device *); 386 387 int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 388 void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 389 void SIP_DECL(dp83815_mii_statchg)(struct device *); 390 #endif /* DP83820 */ 391 392 int SIP_DECL(mediachange)(struct ifnet *); 393 void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 394 395 int SIP_DECL(match)(struct device *, struct cfdata *, void *); 396 void SIP_DECL(attach)(struct device *, struct device *, void *); 397 398 int SIP_DECL(copy_small) = 0; 399 400 struct cfattach SIP_DECL(ca) = { 401 sizeof(struct sip_softc), SIP_DECL(match), SIP_DECL(attach), 402 }; 403 404 /* 405 * Descriptions of the variants of the SiS900. 406 */ 407 struct sip_variant { 408 int (*sipv_mii_readreg)(struct device *, int, int); 409 void (*sipv_mii_writereg)(struct device *, int, int, int); 410 void (*sipv_mii_statchg)(struct device *); 411 void (*sipv_set_filter)(struct sip_softc *); 412 void (*sipv_read_macaddr)(struct sip_softc *, u_int8_t *); 413 }; 414 415 #if defined(DP83820) 416 u_int32_t SIP_DECL(dp83820_mii_bitbang_read)(struct device *); 417 void SIP_DECL(dp83820_mii_bitbang_write)(struct device *, u_int32_t); 418 419 const struct mii_bitbang_ops SIP_DECL(dp83820_mii_bitbang_ops) = { 420 SIP_DECL(dp83820_mii_bitbang_read), 421 SIP_DECL(dp83820_mii_bitbang_write), 422 { 423 EROMAR_MDIO, /* MII_BIT_MDO */ 424 EROMAR_MDIO, /* MII_BIT_MDI */ 425 EROMAR_MDC, /* MII_BIT_MDC */ 426 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 427 0, /* MII_BIT_DIR_PHY_HOST */ 428 } 429 }; 430 #endif /* DP83820 */ 431 432 #if defined(DP83820) 433 const struct sip_variant SIP_DECL(variant_dp83820) = { 434 SIP_DECL(dp83820_mii_readreg), 435 SIP_DECL(dp83820_mii_writereg), 436 SIP_DECL(dp83820_mii_statchg), 437 SIP_DECL(dp83815_set_filter), 438 SIP_DECL(dp83820_read_macaddr), 439 }; 440 #else 441 const struct sip_variant SIP_DECL(variant_sis900) = { 442 SIP_DECL(sis900_mii_readreg), 443 SIP_DECL(sis900_mii_writereg), 444 SIP_DECL(sis900_mii_statchg), 445 SIP_DECL(sis900_set_filter), 446 SIP_DECL(sis900_read_macaddr), 447 }; 448 449 const struct sip_variant SIP_DECL(variant_dp83815) = { 450 SIP_DECL(dp83815_mii_readreg), 451 SIP_DECL(dp83815_mii_writereg), 452 SIP_DECL(dp83815_mii_statchg), 453 SIP_DECL(dp83815_set_filter), 454 SIP_DECL(dp83815_read_macaddr), 455 }; 456 #endif /* DP83820 */ 457 458 /* 459 * Devices supported by this driver. 460 */ 461 const struct sip_product { 462 pci_vendor_id_t sip_vendor; 463 pci_product_id_t sip_product; 464 const char *sip_name; 465 const struct sip_variant *sip_variant; 466 } SIP_DECL(products)[] = { 467 #if defined(DP83820) 468 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 469 "NatSemi DP83820 Gigabit Ethernet", 470 &SIP_DECL(variant_dp83820) }, 471 #else 472 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 473 "SiS 900 10/100 Ethernet", 474 &SIP_DECL(variant_sis900) }, 475 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 476 "SiS 7016 10/100 Ethernet", 477 &SIP_DECL(variant_sis900) }, 478 479 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 480 "NatSemi DP83815 10/100 Ethernet", 481 &SIP_DECL(variant_dp83815) }, 482 #endif /* DP83820 */ 483 484 { 0, 0, 485 NULL, 486 NULL }, 487 }; 488 489 static const struct sip_product * 490 SIP_DECL(lookup)(const struct pci_attach_args *pa) 491 { 492 const struct sip_product *sip; 493 494 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 495 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 496 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 497 return (sip); 498 } 499 return (NULL); 500 } 501 502 int 503 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 504 { 505 struct pci_attach_args *pa = aux; 506 507 if (SIP_DECL(lookup)(pa) != NULL) 508 return (1); 509 510 return (0); 511 } 512 513 void 514 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 515 { 516 struct sip_softc *sc = (struct sip_softc *) self; 517 struct pci_attach_args *pa = aux; 518 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 519 pci_chipset_tag_t pc = pa->pa_pc; 520 pci_intr_handle_t ih; 521 const char *intrstr = NULL; 522 bus_space_tag_t iot, memt; 523 bus_space_handle_t ioh, memh; 524 bus_dma_segment_t seg; 525 int ioh_valid, memh_valid; 526 int i, rseg, error; 527 const struct sip_product *sip; 528 pcireg_t pmode; 529 u_int8_t enaddr[ETHER_ADDR_LEN]; 530 int pmreg; 531 #ifdef DP83820 532 pcireg_t memtype; 533 u_int32_t reg; 534 #endif /* DP83820 */ 535 536 callout_init(&sc->sc_tick_ch); 537 538 sip = SIP_DECL(lookup)(pa); 539 if (sip == NULL) { 540 printf("\n"); 541 panic(SIP_STR(attach) ": impossible"); 542 } 543 544 printf(": %s\n", sip->sip_name); 545 546 sc->sc_model = sip; 547 548 /* 549 * Map the device. 550 */ 551 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 552 PCI_MAPREG_TYPE_IO, 0, 553 &iot, &ioh, NULL, NULL) == 0); 554 #ifdef DP83820 555 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 556 switch (memtype) { 557 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 558 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 559 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 560 memtype, 0, &memt, &memh, NULL, NULL) == 0); 561 break; 562 default: 563 memh_valid = 0; 564 } 565 #else 566 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 567 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 568 &memt, &memh, NULL, NULL) == 0); 569 #endif /* DP83820 */ 570 571 if (memh_valid) { 572 sc->sc_st = memt; 573 sc->sc_sh = memh; 574 } else if (ioh_valid) { 575 sc->sc_st = iot; 576 sc->sc_sh = ioh; 577 } else { 578 printf("%s: unable to map device registers\n", 579 sc->sc_dev.dv_xname); 580 return; 581 } 582 583 sc->sc_dmat = pa->pa_dmat; 584 585 /* Enable bus mastering. */ 586 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 587 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 588 PCI_COMMAND_MASTER_ENABLE); 589 590 /* Get it out of power save mode if needed. */ 591 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 592 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 593 if (pmode == 3) { 594 /* 595 * The card has lost all configuration data in 596 * this state, so punt. 597 */ 598 printf("%s: unable to wake up from power state D3\n", 599 sc->sc_dev.dv_xname); 600 return; 601 } 602 if (pmode != 0) { 603 printf("%s: waking up from power state D%d\n", 604 sc->sc_dev.dv_xname, pmode); 605 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 606 } 607 } 608 609 /* 610 * Map and establish our interrupt. 611 */ 612 if (pci_intr_map(pa, &ih)) { 613 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 614 return; 615 } 616 intrstr = pci_intr_string(pc, ih); 617 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 618 if (sc->sc_ih == NULL) { 619 printf("%s: unable to establish interrupt", 620 sc->sc_dev.dv_xname); 621 if (intrstr != NULL) 622 printf(" at %s", intrstr); 623 printf("\n"); 624 return; 625 } 626 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 627 628 SIMPLEQ_INIT(&sc->sc_txfreeq); 629 SIMPLEQ_INIT(&sc->sc_txdirtyq); 630 631 /* 632 * Allocate the control data structures, and create and load the 633 * DMA map for it. 634 */ 635 if ((error = bus_dmamem_alloc(sc->sc_dmat, 636 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 637 0)) != 0) { 638 printf("%s: unable to allocate control data, error = %d\n", 639 sc->sc_dev.dv_xname, error); 640 goto fail_0; 641 } 642 643 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 644 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 645 BUS_DMA_COHERENT)) != 0) { 646 printf("%s: unable to map control data, error = %d\n", 647 sc->sc_dev.dv_xname, error); 648 goto fail_1; 649 } 650 651 if ((error = bus_dmamap_create(sc->sc_dmat, 652 sizeof(struct sip_control_data), 1, 653 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 654 printf("%s: unable to create control data DMA map, " 655 "error = %d\n", sc->sc_dev.dv_xname, error); 656 goto fail_2; 657 } 658 659 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 660 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 661 0)) != 0) { 662 printf("%s: unable to load control data DMA map, error = %d\n", 663 sc->sc_dev.dv_xname, error); 664 goto fail_3; 665 } 666 667 /* 668 * Create the transmit buffer DMA maps. 669 */ 670 for (i = 0; i < SIP_TXQUEUELEN; i++) { 671 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 672 SIP_NTXSEGS, MCLBYTES, 0, 0, 673 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 674 printf("%s: unable to create tx DMA map %d, " 675 "error = %d\n", sc->sc_dev.dv_xname, i, error); 676 goto fail_4; 677 } 678 } 679 680 /* 681 * Create the receive buffer DMA maps. 682 */ 683 for (i = 0; i < SIP_NRXDESC; i++) { 684 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 685 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 686 printf("%s: unable to create rx DMA map %d, " 687 "error = %d\n", sc->sc_dev.dv_xname, i, error); 688 goto fail_5; 689 } 690 sc->sc_rxsoft[i].rxs_mbuf = NULL; 691 } 692 693 /* 694 * Reset the chip to a known state. 695 */ 696 SIP_DECL(reset)(sc); 697 698 /* 699 * Read the Ethernet address from the EEPROM. This might 700 * also fetch other stuff from the EEPROM and stash it 701 * in the softc. 702 */ 703 sc->sc_cfg = 0; 704 (*sip->sip_variant->sipv_read_macaddr)(sc, enaddr); 705 706 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 707 ether_sprintf(enaddr)); 708 709 /* 710 * Initialize the configuration register: aggressive PCI 711 * bus request algorithm, default backoff, default OW timer, 712 * default parity error detection. 713 * 714 * NOTE: "Big endian mode" is useless on the SiS900 and 715 * friends -- it affects packet data, not descriptors. 716 */ 717 #ifdef DP83820 718 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 719 if (reg & CFG_PCI64_DET) { 720 printf("%s: 64-bit PCI slot detected\n", sc->sc_dev.dv_xname); 721 /* 722 * XXX Need some PCI flags indicating support for 723 * XXX 64-bit addressing (SAC or DAC) and 64-bit 724 * XXX data path. 725 */ 726 } 727 if (sc->sc_cfg & (CFG_TBI_EN|CFG_EXT_125)) { 728 const char *sep = ""; 729 printf("%s: using ", sc->sc_dev.dv_xname); 730 if (sc->sc_cfg & CFG_EXT_125) { 731 printf("%s125MHz clock", sep); 732 sep = ", "; 733 } 734 if (sc->sc_cfg & CFG_TBI_EN) { 735 printf("%sten-bit interface", sep); 736 sep = ", "; 737 } 738 printf("\n"); 739 } 740 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0) 741 sc->sc_cfg |= CFG_MRM_DIS; 742 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 743 sc->sc_cfg |= CFG_MWI_DIS; 744 745 /* 746 * Use the extended descriptor format on the DP83820. This 747 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 748 * checksumming. 749 */ 750 sc->sc_cfg |= CFG_EXTSTS_EN; 751 #endif /* DP83820 */ 752 753 /* 754 * Initialize our media structures and probe the MII. 755 */ 756 sc->sc_mii.mii_ifp = ifp; 757 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 758 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 759 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 760 ifmedia_init(&sc->sc_mii.mii_media, 0, SIP_DECL(mediachange), 761 SIP_DECL(mediastatus)); 762 #ifdef DP83820 763 if (sc->sc_cfg & CFG_TBI_EN) { 764 /* Using ten-bit interface. */ 765 printf("%s: TBI -- FIXME\n", sc->sc_dev.dv_xname); 766 } else { 767 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 768 MII_OFFSET_ANY, 0); 769 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 770 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 771 0, NULL); 772 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 773 } else 774 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 775 } 776 #else 777 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 778 MII_OFFSET_ANY, 0); 779 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 780 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 781 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 782 } else 783 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 784 #endif /* DP83820 */ 785 786 ifp = &sc->sc_ethercom.ec_if; 787 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 788 ifp->if_softc = sc; 789 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 790 ifp->if_ioctl = SIP_DECL(ioctl); 791 ifp->if_start = SIP_DECL(start); 792 ifp->if_watchdog = SIP_DECL(watchdog); 793 ifp->if_init = SIP_DECL(init); 794 ifp->if_stop = SIP_DECL(stop); 795 IFQ_SET_READY(&ifp->if_snd); 796 797 /* 798 * We can support 802.1Q VLAN-sized frames. 799 */ 800 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 801 802 #ifdef DP83820 803 /* 804 * And the DP83820 can do VLAN tagging in hardware. 805 */ 806 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 807 808 /* 809 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 810 * in hardware. 811 */ 812 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 813 IFCAP_CSUM_UDPv4; 814 #endif /* DP83820 */ 815 816 /* 817 * Attach the interface. 818 */ 819 if_attach(ifp); 820 ether_ifattach(ifp, enaddr); 821 822 #ifdef SIP_EVENT_COUNTERS 823 /* 824 * Attach event counters. 825 */ 826 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 827 NULL, sc->sc_dev.dv_xname, "txsstall"); 828 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 829 NULL, sc->sc_dev.dv_xname, "txdstall"); 830 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 831 NULL, sc->sc_dev.dv_xname, "txintr"); 832 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 833 NULL, sc->sc_dev.dv_xname, "rxintr"); 834 #ifdef DP83820 835 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 836 NULL, sc->sc_dev.dv_xname, "rxipsum"); 837 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 838 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 839 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 840 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 841 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 842 NULL, sc->sc_dev.dv_xname, "txipsum"); 843 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 844 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 845 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 846 NULL, sc->sc_dev.dv_xname, "txudpsum"); 847 #endif /* DP83820 */ 848 #endif /* SIP_EVENT_COUNTERS */ 849 850 /* 851 * Make sure the interface is shutdown during reboot. 852 */ 853 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 854 if (sc->sc_sdhook == NULL) 855 printf("%s: WARNING: unable to establish shutdown hook\n", 856 sc->sc_dev.dv_xname); 857 return; 858 859 /* 860 * Free any resources we've allocated during the failed attach 861 * attempt. Do this in reverse order and fall through. 862 */ 863 fail_5: 864 for (i = 0; i < SIP_NRXDESC; i++) { 865 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 866 bus_dmamap_destroy(sc->sc_dmat, 867 sc->sc_rxsoft[i].rxs_dmamap); 868 } 869 fail_4: 870 for (i = 0; i < SIP_TXQUEUELEN; i++) { 871 if (sc->sc_txsoft[i].txs_dmamap != NULL) 872 bus_dmamap_destroy(sc->sc_dmat, 873 sc->sc_txsoft[i].txs_dmamap); 874 } 875 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 876 fail_3: 877 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 878 fail_2: 879 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 880 sizeof(struct sip_control_data)); 881 fail_1: 882 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 883 fail_0: 884 return; 885 } 886 887 /* 888 * sip_shutdown: 889 * 890 * Make sure the interface is stopped at reboot time. 891 */ 892 void 893 SIP_DECL(shutdown)(void *arg) 894 { 895 struct sip_softc *sc = arg; 896 897 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 898 } 899 900 /* 901 * sip_start: [ifnet interface function] 902 * 903 * Start packet transmission on the interface. 904 */ 905 void 906 SIP_DECL(start)(struct ifnet *ifp) 907 { 908 struct sip_softc *sc = ifp->if_softc; 909 struct mbuf *m0, *m; 910 struct sip_txsoft *txs; 911 bus_dmamap_t dmamap; 912 int error, firsttx, nexttx, lasttx, ofree, seg; 913 #ifdef DP83820 914 u_int32_t extsts; 915 #endif 916 917 /* 918 * If we've been told to pause, don't transmit any more packets. 919 */ 920 if (sc->sc_flags & SIPF_PAUSED) 921 ifp->if_flags |= IFF_OACTIVE; 922 923 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 924 return; 925 926 /* 927 * Remember the previous number of free descriptors and 928 * the first descriptor we'll use. 929 */ 930 ofree = sc->sc_txfree; 931 firsttx = sc->sc_txnext; 932 933 /* 934 * Loop through the send queue, setting up transmit descriptors 935 * until we drain the queue, or use up all available transmit 936 * descriptors. 937 */ 938 for (;;) { 939 /* Get a work queue entry. */ 940 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 941 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 942 break; 943 } 944 945 /* 946 * Grab a packet off the queue. 947 */ 948 IFQ_POLL(&ifp->if_snd, m0); 949 if (m0 == NULL) 950 break; 951 m = NULL; 952 953 dmamap = txs->txs_dmamap; 954 955 /* 956 * Load the DMA map. If this fails, the packet either 957 * didn't fit in the alloted number of segments, or we 958 * were short on resources. In this case, we'll copy 959 * and try again. 960 */ 961 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 962 BUS_DMA_NOWAIT) != 0) { 963 MGETHDR(m, M_DONTWAIT, MT_DATA); 964 if (m == NULL) { 965 printf("%s: unable to allocate Tx mbuf\n", 966 sc->sc_dev.dv_xname); 967 break; 968 } 969 if (m0->m_pkthdr.len > MHLEN) { 970 MCLGET(m, M_DONTWAIT); 971 if ((m->m_flags & M_EXT) == 0) { 972 printf("%s: unable to allocate Tx " 973 "cluster\n", sc->sc_dev.dv_xname); 974 m_freem(m); 975 break; 976 } 977 } 978 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 979 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 980 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 981 m, BUS_DMA_NOWAIT); 982 if (error) { 983 printf("%s: unable to load Tx buffer, " 984 "error = %d\n", sc->sc_dev.dv_xname, error); 985 break; 986 } 987 } 988 989 /* 990 * Ensure we have enough descriptors free to describe 991 * the packet. Note, we always reserve one descriptor 992 * at the end of the ring as a termination point, to 993 * prevent wrap-around. 994 */ 995 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 996 /* 997 * Not enough free descriptors to transmit this 998 * packet. We haven't committed anything yet, 999 * so just unload the DMA map, put the packet 1000 * back on the queue, and punt. Notify the upper 1001 * layer that there are not more slots left. 1002 * 1003 * XXX We could allocate an mbuf and copy, but 1004 * XXX is it worth it? 1005 */ 1006 ifp->if_flags |= IFF_OACTIVE; 1007 bus_dmamap_unload(sc->sc_dmat, dmamap); 1008 if (m != NULL) 1009 m_freem(m); 1010 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1011 break; 1012 } 1013 1014 IFQ_DEQUEUE(&ifp->if_snd, m0); 1015 if (m != NULL) { 1016 m_freem(m0); 1017 m0 = m; 1018 } 1019 1020 /* 1021 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1022 */ 1023 1024 /* Sync the DMA map. */ 1025 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1026 BUS_DMASYNC_PREWRITE); 1027 1028 /* 1029 * Initialize the transmit descriptors. 1030 */ 1031 for (nexttx = sc->sc_txnext, seg = 0; 1032 seg < dmamap->dm_nsegs; 1033 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1034 /* 1035 * If this is the first descriptor we're 1036 * enqueueing, don't set the OWN bit just 1037 * yet. That could cause a race condition. 1038 * We'll do it below. 1039 */ 1040 sc->sc_txdescs[nexttx].sipd_bufptr = 1041 htole32(dmamap->dm_segs[seg].ds_addr); 1042 sc->sc_txdescs[nexttx].sipd_cmdsts = 1043 htole32((nexttx == firsttx ? 0 : CMDSTS_OWN) | 1044 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1045 #ifdef DP83820 1046 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1047 #endif /* DP83820 */ 1048 lasttx = nexttx; 1049 } 1050 1051 /* Clear the MORE bit on the last segment. */ 1052 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1053 1054 #ifdef DP83820 1055 /* 1056 * If VLANs are enabled and the packet has a VLAN tag, set 1057 * up the descriptor to encapsulate the packet for us. 1058 * 1059 * This apparently has to be on the last descriptor of 1060 * the packet. 1061 */ 1062 if (sc->sc_ethercom.ec_nvlans != 0 && 1063 (m = m_aux_find(m0, AF_LINK, ETHERTYPE_VLAN)) != NULL) { 1064 sc->sc_txdescs[lasttx].sipd_extsts |= 1065 htole32(EXTSTS_VPKT | 1066 htons(*mtod(m, int *) & EXTSTS_VTCI)); 1067 } 1068 1069 /* 1070 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1071 * checksumming, set up the descriptor to do this work 1072 * for us. 1073 * 1074 * This apparently has to be on the first descriptor of 1075 * the packet. 1076 * 1077 * Byte-swap constants so the compiler can optimize. 1078 */ 1079 extsts = 0; 1080 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1081 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1082 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1083 extsts |= htole32(EXTSTS_IPPKT); 1084 } 1085 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1086 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1087 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1088 extsts |= htole32(EXTSTS_TCPPKT); 1089 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1090 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1091 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1092 extsts |= htole32(EXTSTS_UDPPKT); 1093 } 1094 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1095 #endif /* DP83820 */ 1096 1097 /* Sync the descriptors we're using. */ 1098 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1099 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1100 1101 /* 1102 * Store a pointer to the packet so we can free it later, 1103 * and remember what txdirty will be once the packet is 1104 * done. 1105 */ 1106 txs->txs_mbuf = m0; 1107 txs->txs_firstdesc = sc->sc_txnext; 1108 txs->txs_lastdesc = lasttx; 1109 1110 /* Advance the tx pointer. */ 1111 sc->sc_txfree -= dmamap->dm_nsegs; 1112 sc->sc_txnext = nexttx; 1113 1114 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs, txs_q); 1115 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1116 1117 #if NBPFILTER > 0 1118 /* 1119 * Pass the packet to any BPF listeners. 1120 */ 1121 if (ifp->if_bpf) 1122 bpf_mtap(ifp->if_bpf, m0); 1123 #endif /* NBPFILTER > 0 */ 1124 } 1125 1126 if (txs == NULL || sc->sc_txfree == 0) { 1127 /* No more slots left; notify upper layer. */ 1128 ifp->if_flags |= IFF_OACTIVE; 1129 } 1130 1131 if (sc->sc_txfree != ofree) { 1132 /* 1133 * Cause a descriptor interrupt to happen on the 1134 * last packet we enqueued. 1135 */ 1136 sc->sc_txdescs[lasttx].sipd_cmdsts |= htole32(CMDSTS_INTR); 1137 SIP_CDTXSYNC(sc, lasttx, 1, 1138 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1139 1140 /* 1141 * The entire packet chain is set up. Give the 1142 * first descrptor to the chip now. 1143 */ 1144 sc->sc_txdescs[firsttx].sipd_cmdsts |= htole32(CMDSTS_OWN); 1145 SIP_CDTXSYNC(sc, firsttx, 1, 1146 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1147 1148 /* 1149 * Start the transmit process. Note, the manual says 1150 * that if there are no pending transmissions in the 1151 * chip's internal queue (indicated by TXE being clear), 1152 * then the driver software must set the TXDP to the 1153 * first descriptor to be transmitted. However, if we 1154 * do this, it causes serious performance degredation on 1155 * the DP83820 under load, not setting TXDP doesn't seem 1156 * to adversely affect the SiS 900 or DP83815. 1157 * 1158 * Well, I guess it wouldn't be the first time a manual 1159 * has lied -- and they could be speaking of the NULL- 1160 * terminated descriptor list case, rather than OWN- 1161 * terminated rings. 1162 */ 1163 #if 0 1164 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1165 CR_TXE) == 0) { 1166 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1167 SIP_CDTXADDR(sc, firsttx)); 1168 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1169 } 1170 #else 1171 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1172 #endif 1173 1174 /* Set a watchdog timer in case the chip flakes out. */ 1175 ifp->if_timer = 5; 1176 } 1177 } 1178 1179 /* 1180 * sip_watchdog: [ifnet interface function] 1181 * 1182 * Watchdog timer handler. 1183 */ 1184 void 1185 SIP_DECL(watchdog)(struct ifnet *ifp) 1186 { 1187 struct sip_softc *sc = ifp->if_softc; 1188 1189 /* 1190 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1191 * If we get a timeout, try and sweep up transmit descriptors. 1192 * If we manage to sweep them all up, ignore the lack of 1193 * interrupt. 1194 */ 1195 SIP_DECL(txintr)(sc); 1196 1197 if (sc->sc_txfree != SIP_NTXDESC) { 1198 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1199 ifp->if_oerrors++; 1200 1201 /* Reset the interface. */ 1202 (void) SIP_DECL(init)(ifp); 1203 } else if (ifp->if_flags & IFF_DEBUG) 1204 printf("%s: recovered from device timeout\n", 1205 sc->sc_dev.dv_xname); 1206 1207 /* Try to get more packets going. */ 1208 SIP_DECL(start)(ifp); 1209 } 1210 1211 /* 1212 * sip_ioctl: [ifnet interface function] 1213 * 1214 * Handle control requests from the operator. 1215 */ 1216 int 1217 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1218 { 1219 struct sip_softc *sc = ifp->if_softc; 1220 struct ifreq *ifr = (struct ifreq *)data; 1221 int s, error; 1222 1223 s = splnet(); 1224 1225 switch (cmd) { 1226 case SIOCSIFMEDIA: 1227 case SIOCGIFMEDIA: 1228 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1229 break; 1230 1231 default: 1232 error = ether_ioctl(ifp, cmd, data); 1233 if (error == ENETRESET) { 1234 /* 1235 * Multicast list has changed; set the hardware filter 1236 * accordingly. 1237 */ 1238 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1239 error = 0; 1240 } 1241 break; 1242 } 1243 1244 /* Try to get more packets going. */ 1245 SIP_DECL(start)(ifp); 1246 1247 splx(s); 1248 return (error); 1249 } 1250 1251 /* 1252 * sip_intr: 1253 * 1254 * Interrupt service routine. 1255 */ 1256 int 1257 SIP_DECL(intr)(void *arg) 1258 { 1259 struct sip_softc *sc = arg; 1260 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1261 u_int32_t isr; 1262 int handled = 0; 1263 1264 for (;;) { 1265 /* Reading clears interrupt. */ 1266 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1267 if ((isr & sc->sc_imr) == 0) 1268 break; 1269 1270 handled = 1; 1271 1272 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1273 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1274 1275 /* Grab any new packets. */ 1276 SIP_DECL(rxintr)(sc); 1277 1278 if (isr & ISR_RXORN) { 1279 printf("%s: receive FIFO overrun\n", 1280 sc->sc_dev.dv_xname); 1281 1282 /* XXX adjust rx_drain_thresh? */ 1283 } 1284 1285 if (isr & ISR_RXIDLE) { 1286 printf("%s: receive ring overrun\n", 1287 sc->sc_dev.dv_xname); 1288 1289 /* Get the receive process going again. */ 1290 bus_space_write_4(sc->sc_st, sc->sc_sh, 1291 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1292 bus_space_write_4(sc->sc_st, sc->sc_sh, 1293 SIP_CR, CR_RXE); 1294 } 1295 } 1296 1297 if (isr & (ISR_TXURN|ISR_TXDESC)) { 1298 SIP_EVCNT_INCR(&sc->sc_ev_txintr); 1299 1300 /* Sweep up transmit descriptors. */ 1301 SIP_DECL(txintr)(sc); 1302 1303 if (isr & ISR_TXURN) { 1304 u_int32_t thresh; 1305 1306 printf("%s: transmit FIFO underrun", 1307 sc->sc_dev.dv_xname); 1308 1309 thresh = sc->sc_tx_drain_thresh + 1; 1310 if (thresh <= TXCFG_DRTH && 1311 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1312 (sc->sc_tx_fill_thresh * 32))) { 1313 printf("; increasing Tx drain " 1314 "threshold to %u bytes\n", 1315 thresh * 32); 1316 sc->sc_tx_drain_thresh = thresh; 1317 (void) SIP_DECL(init)(ifp); 1318 } else { 1319 (void) SIP_DECL(init)(ifp); 1320 printf("\n"); 1321 } 1322 } 1323 } 1324 1325 #if !defined(DP83820) 1326 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1327 if (isr & ISR_PAUSE_ST) { 1328 sc->sc_flags |= SIPF_PAUSED; 1329 ifp->if_flags |= IFF_OACTIVE; 1330 } 1331 if (isr & ISR_PAUSE_END) { 1332 sc->sc_flags &= ~SIPF_PAUSED; 1333 ifp->if_flags &= ~IFF_OACTIVE; 1334 } 1335 } 1336 #endif /* ! DP83820 */ 1337 1338 if (isr & ISR_HIBERR) { 1339 #define PRINTERR(bit, str) \ 1340 if (isr & (bit)) \ 1341 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1342 PRINTERR(ISR_DPERR, "parity error"); 1343 PRINTERR(ISR_SSERR, "system error"); 1344 PRINTERR(ISR_RMABT, "master abort"); 1345 PRINTERR(ISR_RTABT, "target abort"); 1346 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1347 (void) SIP_DECL(init)(ifp); 1348 #undef PRINTERR 1349 } 1350 } 1351 1352 /* Try to get more packets going. */ 1353 SIP_DECL(start)(ifp); 1354 1355 return (handled); 1356 } 1357 1358 /* 1359 * sip_txintr: 1360 * 1361 * Helper; handle transmit interrupts. 1362 */ 1363 void 1364 SIP_DECL(txintr)(struct sip_softc *sc) 1365 { 1366 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1367 struct sip_txsoft *txs; 1368 u_int32_t cmdsts; 1369 1370 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1371 ifp->if_flags &= ~IFF_OACTIVE; 1372 1373 /* 1374 * Go through our Tx list and free mbufs for those 1375 * frames which have been transmitted. 1376 */ 1377 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1378 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1379 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1380 1381 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1382 if (cmdsts & CMDSTS_OWN) 1383 break; 1384 1385 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1386 1387 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1388 1389 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1390 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1391 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1392 m_freem(txs->txs_mbuf); 1393 txs->txs_mbuf = NULL; 1394 1395 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1396 1397 /* 1398 * Check for errors and collisions. 1399 */ 1400 if (cmdsts & 1401 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1402 if (ifp->if_flags & IFF_DEBUG) { 1403 if (CMDSTS_Tx_ED) 1404 printf("%s: excessive deferral\n", 1405 sc->sc_dev.dv_xname); 1406 if (CMDSTS_Tx_EC) { 1407 printf("%s: excessive collisions\n", 1408 sc->sc_dev.dv_xname); 1409 ifp->if_collisions += 16; 1410 } 1411 } 1412 } else { 1413 /* Packet was transmitted successfully. */ 1414 ifp->if_opackets++; 1415 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1416 } 1417 } 1418 1419 /* 1420 * If there are no more pending transmissions, cancel the watchdog 1421 * timer. 1422 */ 1423 if (txs == NULL) 1424 ifp->if_timer = 0; 1425 } 1426 1427 /* 1428 * sip_rxintr: 1429 * 1430 * Helper; handle receive interrupts. 1431 */ 1432 void 1433 SIP_DECL(rxintr)(struct sip_softc *sc) 1434 { 1435 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1436 struct sip_rxsoft *rxs; 1437 struct mbuf *m; 1438 u_int32_t cmdsts; 1439 #ifdef DP83820 1440 u_int32_t extsts; 1441 #endif /* DP83820 */ 1442 int i, len; 1443 1444 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1445 rxs = &sc->sc_rxsoft[i]; 1446 1447 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1448 1449 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1450 #ifdef DP83820 1451 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1452 #endif /* DP83820 */ 1453 1454 /* 1455 * NOTE: OWN is set if owned by _consumer_. We're the 1456 * consumer of the receive ring, so if the bit is clear, 1457 * we have processed all of the packets. 1458 */ 1459 if ((cmdsts & CMDSTS_OWN) == 0) { 1460 /* 1461 * We have processed all of the receive buffers. 1462 */ 1463 break; 1464 } 1465 1466 #if !defined(DP83820) 1467 /* 1468 * If any collisions were seen on the wire, count one. 1469 */ 1470 if (cmdsts & CMDSTS_Rx_COL) 1471 ifp->if_collisions++; 1472 #endif /* ! DP83820 */ 1473 1474 /* 1475 * If an error occurred, update stats, clear the status 1476 * word, and leave the packet buffer in place. It will 1477 * simply be reused the next time the ring comes around. 1478 */ 1479 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_LONG|CMDSTS_Rx_RUNT| 1480 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1481 ifp->if_ierrors++; 1482 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1483 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1484 /* Receive overrun handled elsewhere. */ 1485 printf("%s: receive descriptor error\n", 1486 sc->sc_dev.dv_xname); 1487 } 1488 #define PRINTERR(bit, str) \ 1489 if (cmdsts & (bit)) \ 1490 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1491 PRINTERR(CMDSTS_Rx_LONG, "packet too long"); 1492 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1493 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1494 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1495 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1496 #undef PRINTERR 1497 SIP_INIT_RXDESC(sc, i); 1498 continue; 1499 } 1500 1501 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1502 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1503 1504 /* 1505 * No errors; receive the packet. Note, the SiS 900 1506 * includes the CRC with every packet. 1507 */ 1508 len = CMDSTS_SIZE(cmdsts); 1509 1510 #ifdef __NO_STRICT_ALIGNMENT 1511 /* 1512 * If the packet is small enough to fit in a 1513 * single header mbuf, allocate one and copy 1514 * the data into it. This greatly reduces 1515 * memory consumption when we receive lots 1516 * of small packets. 1517 * 1518 * Otherwise, we add a new buffer to the receive 1519 * chain. If this fails, we drop the packet and 1520 * recycle the old buffer. 1521 */ 1522 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 1523 MGETHDR(m, M_DONTWAIT, MT_DATA); 1524 if (m == NULL) 1525 goto dropit; 1526 memcpy(mtod(m, caddr_t), 1527 mtod(rxs->rxs_mbuf, caddr_t), len); 1528 SIP_INIT_RXDESC(sc, i); 1529 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1530 rxs->rxs_dmamap->dm_mapsize, 1531 BUS_DMASYNC_PREREAD); 1532 } else { 1533 m = rxs->rxs_mbuf; 1534 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1535 dropit: 1536 ifp->if_ierrors++; 1537 SIP_INIT_RXDESC(sc, i); 1538 bus_dmamap_sync(sc->sc_dmat, 1539 rxs->rxs_dmamap, 0, 1540 rxs->rxs_dmamap->dm_mapsize, 1541 BUS_DMASYNC_PREREAD); 1542 continue; 1543 } 1544 } 1545 #else 1546 /* 1547 * The SiS 900's receive buffers must be 4-byte aligned. 1548 * But this means that the data after the Ethernet header 1549 * is misaligned. We must allocate a new buffer and 1550 * copy the data, shifted forward 2 bytes. 1551 */ 1552 MGETHDR(m, M_DONTWAIT, MT_DATA); 1553 if (m == NULL) { 1554 dropit: 1555 ifp->if_ierrors++; 1556 SIP_INIT_RXDESC(sc, i); 1557 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1558 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1559 continue; 1560 } 1561 if (len > (MHLEN - 2)) { 1562 MCLGET(m, M_DONTWAIT); 1563 if ((m->m_flags & M_EXT) == 0) { 1564 m_freem(m); 1565 goto dropit; 1566 } 1567 } 1568 m->m_data += 2; 1569 1570 /* 1571 * Note that we use clusters for incoming frames, so the 1572 * buffer is virtually contiguous. 1573 */ 1574 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 1575 1576 /* Allow the receive descriptor to continue using its mbuf. */ 1577 SIP_INIT_RXDESC(sc, i); 1578 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1579 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1580 #endif /* __NO_STRICT_ALIGNMENT */ 1581 1582 ifp->if_ipackets++; 1583 m->m_flags |= M_HASFCS; 1584 m->m_pkthdr.rcvif = ifp; 1585 m->m_pkthdr.len = m->m_len = len; 1586 1587 #if NBPFILTER > 0 1588 /* 1589 * Pass this up to any BPF listeners, but only 1590 * pass if up the stack if it's for us. 1591 */ 1592 if (ifp->if_bpf) 1593 bpf_mtap(ifp->if_bpf, m); 1594 #endif /* NBPFILTER > 0 */ 1595 1596 #ifdef DP83820 1597 /* 1598 * If VLANs are enabled, VLAN packets have been unwrapped 1599 * for us. Associate the tag with the packet. 1600 */ 1601 if (sc->sc_ethercom.ec_nvlans != 0 && 1602 (extsts & EXTSTS_VPKT) != 0) { 1603 struct mbuf *vtag; 1604 1605 vtag = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 1606 if (vtag == NULL) { 1607 printf("%s: unable to allocate VLAN tag\n", 1608 sc->sc_dev.dv_xname); 1609 m_freem(m); 1610 continue; 1611 } 1612 1613 *mtod(vtag, int *) = ntohs(extsts & EXTSTS_VTCI); 1614 vtag->m_len = sizeof(int); 1615 } 1616 1617 /* 1618 * Set the incoming checksum information for the 1619 * packet. 1620 */ 1621 if ((extsts & EXTSTS_IPPKT) != 0) { 1622 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1623 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1624 if (extsts & EXTSTS_Rx_IPERR) 1625 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1626 if (extsts & EXTSTS_TCPPKT) { 1627 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1628 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1629 if (extsts & EXTSTS_Rx_TCPERR) 1630 m->m_pkthdr.csum_flags |= 1631 M_CSUM_TCP_UDP_BAD; 1632 } else if (extsts & EXTSTS_UDPPKT) { 1633 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1634 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1635 if (extsts & EXTSTS_Rx_UDPERR) 1636 m->m_pkthdr.csum_flags |= 1637 M_CSUM_TCP_UDP_BAD; 1638 } 1639 } 1640 #endif /* DP83820 */ 1641 1642 /* Pass it on. */ 1643 (*ifp->if_input)(ifp, m); 1644 } 1645 1646 /* Update the receive pointer. */ 1647 sc->sc_rxptr = i; 1648 } 1649 1650 /* 1651 * sip_tick: 1652 * 1653 * One second timer, used to tick the MII. 1654 */ 1655 void 1656 SIP_DECL(tick)(void *arg) 1657 { 1658 struct sip_softc *sc = arg; 1659 int s; 1660 1661 s = splnet(); 1662 mii_tick(&sc->sc_mii); 1663 splx(s); 1664 1665 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 1666 } 1667 1668 /* 1669 * sip_reset: 1670 * 1671 * Perform a soft reset on the SiS 900. 1672 */ 1673 void 1674 SIP_DECL(reset)(struct sip_softc *sc) 1675 { 1676 bus_space_tag_t st = sc->sc_st; 1677 bus_space_handle_t sh = sc->sc_sh; 1678 int i; 1679 1680 bus_space_write_4(st, sh, SIP_CR, CR_RST); 1681 1682 for (i = 0; i < SIP_TIMEOUT; i++) { 1683 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 1684 break; 1685 delay(2); 1686 } 1687 1688 if (i == SIP_TIMEOUT) 1689 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1690 1691 delay(1000); 1692 1693 #ifdef DP83820 1694 /* 1695 * Set the general purpose I/O bits. Do it here in case we 1696 * need to have GPIO set up to talk to the media interface. 1697 */ 1698 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 1699 delay(1000); 1700 #endif /* DP83820 */ 1701 } 1702 1703 /* 1704 * sip_init: [ ifnet interface function ] 1705 * 1706 * Initialize the interface. Must be called at splnet(). 1707 */ 1708 int 1709 SIP_DECL(init)(struct ifnet *ifp) 1710 { 1711 struct sip_softc *sc = ifp->if_softc; 1712 bus_space_tag_t st = sc->sc_st; 1713 bus_space_handle_t sh = sc->sc_sh; 1714 struct sip_txsoft *txs; 1715 struct sip_rxsoft *rxs; 1716 struct sip_desc *sipd; 1717 u_int32_t reg; 1718 int i, error = 0; 1719 1720 /* 1721 * Cancel any pending I/O. 1722 */ 1723 SIP_DECL(stop)(ifp, 0); 1724 1725 /* 1726 * Reset the chip to a known state. 1727 */ 1728 SIP_DECL(reset)(sc); 1729 1730 #if !defined(DP83820) 1731 if (sc->sc_model->sip_vendor == PCI_VENDOR_NS && 1732 sc->sc_model->sip_product == PCI_PRODUCT_NS_DP83815) { 1733 /* 1734 * DP83815 manual, page 78: 1735 * 4.4 Recommended Registers Configuration 1736 * For optimum performance of the DP83815, version noted 1737 * as DP83815CVNG (SRR = 203h), the listed register 1738 * modifications must be followed in sequence... 1739 * 1740 * It's not clear if this should be 302h or 203h because that 1741 * chip name is listed as SRR 302h in the description of the 1742 * SRR register. However, my revision 302h DP83815 on the 1743 * Netgear FA311 purchased in 02/2001 needs these settings 1744 * to avoid tons of errors in AcceptPerfectMatch (non- 1745 * IFF_PROMISC) mode. I do not know if other revisions need 1746 * this set or not. [briggs -- 09 March 2001] 1747 * 1748 * Note that only the low-order 12 bits of 0xe4 are documented 1749 * and that this sets reserved bits in that register. 1750 */ 1751 reg = bus_space_read_4(st, sh, SIP_NS_SRR); 1752 if (reg == 0x302) { 1753 bus_space_write_4(st, sh, 0x00cc, 0x0001); 1754 bus_space_write_4(st, sh, 0x00e4, 0x189C); 1755 bus_space_write_4(st, sh, 0x00fc, 0x0000); 1756 bus_space_write_4(st, sh, 0x00f4, 0x5040); 1757 bus_space_write_4(st, sh, 0x00f8, 0x008c); 1758 } 1759 } 1760 #endif /* ! DP83820 */ 1761 1762 /* 1763 * Initialize the transmit descriptor ring. 1764 */ 1765 for (i = 0; i < SIP_NTXDESC; i++) { 1766 sipd = &sc->sc_txdescs[i]; 1767 memset(sipd, 0, sizeof(struct sip_desc)); 1768 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 1769 } 1770 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 1771 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1772 sc->sc_txfree = SIP_NTXDESC; 1773 sc->sc_txnext = 0; 1774 1775 /* 1776 * Initialize the transmit job descriptors. 1777 */ 1778 SIMPLEQ_INIT(&sc->sc_txfreeq); 1779 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1780 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1781 txs = &sc->sc_txsoft[i]; 1782 txs->txs_mbuf = NULL; 1783 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1784 } 1785 1786 /* 1787 * Initialize the receive descriptor and receive job 1788 * descriptor rings. 1789 */ 1790 for (i = 0; i < SIP_NRXDESC; i++) { 1791 rxs = &sc->sc_rxsoft[i]; 1792 if (rxs->rxs_mbuf == NULL) { 1793 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 1794 printf("%s: unable to allocate or map rx " 1795 "buffer %d, error = %d\n", 1796 sc->sc_dev.dv_xname, i, error); 1797 /* 1798 * XXX Should attempt to run with fewer receive 1799 * XXX buffers instead of just failing. 1800 */ 1801 SIP_DECL(rxdrain)(sc); 1802 goto out; 1803 } 1804 } 1805 } 1806 sc->sc_rxptr = 0; 1807 1808 /* 1809 * Set the configuration register; it's already initialized 1810 * in sip_attach(). 1811 */ 1812 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 1813 1814 /* 1815 * Initialize the transmit fill and drain thresholds if 1816 * we have never done so. 1817 */ 1818 if (sc->sc_tx_fill_thresh == 0) { 1819 /* 1820 * XXX This value should be tuned. This is the 1821 * minimum (32 bytes), and we may be able to 1822 * improve performance by increasing it. 1823 */ 1824 sc->sc_tx_fill_thresh = 1; 1825 } 1826 if (sc->sc_tx_drain_thresh == 0) { 1827 /* 1828 * Start at a drain threshold of 512 bytes. We will 1829 * increase it if a DMA underrun occurs. 1830 * 1831 * XXX The minimum value of this variable should be 1832 * tuned. We may be able to improve performance 1833 * by starting with a lower value. That, however, 1834 * may trash the first few outgoing packets if the 1835 * PCI bus is saturated. 1836 */ 1837 sc->sc_tx_drain_thresh = 512 / 32; 1838 } 1839 1840 /* 1841 * Initialize the prototype TXCFG register. 1842 */ 1843 sc->sc_txcfg = TXCFG_ATP | TXCFG_MXDMA_512 | 1844 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 1845 sc->sc_tx_drain_thresh; 1846 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 1847 1848 /* 1849 * Initialize the receive drain threshold if we have never 1850 * done so. 1851 */ 1852 if (sc->sc_rx_drain_thresh == 0) { 1853 /* 1854 * XXX This value should be tuned. This is set to the 1855 * maximum of 248 bytes, and we may be able to improve 1856 * performance by decreasing it (although we should never 1857 * set this value lower than 2; 14 bytes are required to 1858 * filter the packet). 1859 */ 1860 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 1861 } 1862 1863 /* 1864 * Initialize the prototype RXCFG register. 1865 */ 1866 sc->sc_rxcfg = RXCFG_MXDMA_512 | 1867 (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 1868 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 1869 1870 /* Set up the receive filter. */ 1871 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1872 1873 #ifdef DP83820 1874 /* 1875 * Initialize the VLAN/IP receive control register. 1876 * We enable checksum computation on all incoming 1877 * packets, and do not reject packets w/ bad checksums. 1878 */ 1879 reg = 0; 1880 if (ifp->if_capenable & 1881 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1882 reg |= VRCR_IPEN; 1883 if (sc->sc_ethercom.ec_nvlans != 0) 1884 reg |= VRCR_VTDEN|VRCR_VTREN; 1885 bus_space_write_4(st, sh, SIP_VRCR, reg); 1886 1887 /* 1888 * Initialize the VLAN/IP transmit control register. 1889 * We enable outgoing checksum computation on a 1890 * per-packet basis. 1891 */ 1892 reg = 0; 1893 if (ifp->if_capenable & 1894 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1895 reg |= VTCR_PPCHK; 1896 if (sc->sc_ethercom.ec_nvlans != 0) 1897 reg |= VTCR_VPPTI; 1898 bus_space_write_4(st, sh, SIP_VTCR, reg); 1899 1900 /* 1901 * If we're using VLANs, initialize the VLAN data register. 1902 * To understand why we bswap the VLAN Ethertype, see section 1903 * 4.2.36 of the DP83820 manual. 1904 */ 1905 if (sc->sc_ethercom.ec_nvlans != 0) 1906 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 1907 #endif /* DP83820 */ 1908 1909 /* 1910 * Give the transmit and receive rings to the chip. 1911 */ 1912 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 1913 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1914 1915 /* 1916 * Initialize the interrupt mask. 1917 */ 1918 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 1919 ISR_TXURN|ISR_TXDESC|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 1920 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 1921 1922 /* 1923 * Set the current media. Do this after initializing the prototype 1924 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 1925 * control. 1926 */ 1927 mii_mediachg(&sc->sc_mii); 1928 1929 /* 1930 * Enable interrupts. 1931 */ 1932 bus_space_write_4(st, sh, SIP_IER, IER_IE); 1933 1934 /* 1935 * Start the transmit and receive processes. 1936 */ 1937 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 1938 1939 /* 1940 * Start the one second MII clock. 1941 */ 1942 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 1943 1944 /* 1945 * ...all done! 1946 */ 1947 ifp->if_flags |= IFF_RUNNING; 1948 ifp->if_flags &= ~IFF_OACTIVE; 1949 1950 out: 1951 if (error) 1952 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1953 return (error); 1954 } 1955 1956 /* 1957 * sip_drain: 1958 * 1959 * Drain the receive queue. 1960 */ 1961 void 1962 SIP_DECL(rxdrain)(struct sip_softc *sc) 1963 { 1964 struct sip_rxsoft *rxs; 1965 int i; 1966 1967 for (i = 0; i < SIP_NRXDESC; i++) { 1968 rxs = &sc->sc_rxsoft[i]; 1969 if (rxs->rxs_mbuf != NULL) { 1970 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1971 m_freem(rxs->rxs_mbuf); 1972 rxs->rxs_mbuf = NULL; 1973 } 1974 } 1975 } 1976 1977 /* 1978 * sip_stop: [ ifnet interface function ] 1979 * 1980 * Stop transmission on the interface. 1981 */ 1982 void 1983 SIP_DECL(stop)(struct ifnet *ifp, int disable) 1984 { 1985 struct sip_softc *sc = ifp->if_softc; 1986 bus_space_tag_t st = sc->sc_st; 1987 bus_space_handle_t sh = sc->sc_sh; 1988 struct sip_txsoft *txs; 1989 u_int32_t cmdsts = 0; /* DEBUG */ 1990 1991 /* 1992 * Stop the one second clock. 1993 */ 1994 callout_stop(&sc->sc_tick_ch); 1995 1996 /* Down the MII. */ 1997 mii_down(&sc->sc_mii); 1998 1999 /* 2000 * Disable interrupts. 2001 */ 2002 bus_space_write_4(st, sh, SIP_IER, 0); 2003 2004 /* 2005 * Stop receiver and transmitter. 2006 */ 2007 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2008 2009 /* 2010 * Release any queued transmit buffers. 2011 */ 2012 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2013 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2014 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2015 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2016 CMDSTS_INTR) == 0) 2017 printf("%s: sip_stop: last descriptor does not " 2018 "have INTR bit set\n", sc->sc_dev.dv_xname); 2019 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 2020 #ifdef DIAGNOSTIC 2021 if (txs->txs_mbuf == NULL) { 2022 printf("%s: dirty txsoft with no mbuf chain\n", 2023 sc->sc_dev.dv_xname); 2024 panic("sip_stop"); 2025 } 2026 #endif 2027 cmdsts |= /* DEBUG */ 2028 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2029 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2030 m_freem(txs->txs_mbuf); 2031 txs->txs_mbuf = NULL; 2032 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2033 } 2034 2035 if (disable) 2036 SIP_DECL(rxdrain)(sc); 2037 2038 /* 2039 * Mark the interface down and cancel the watchdog timer. 2040 */ 2041 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2042 ifp->if_timer = 0; 2043 2044 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2045 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2046 printf("%s: sip_stop: no INTR bits set in dirty tx " 2047 "descriptors\n", sc->sc_dev.dv_xname); 2048 } 2049 2050 /* 2051 * sip_read_eeprom: 2052 * 2053 * Read data from the serial EEPROM. 2054 */ 2055 void 2056 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2057 u_int16_t *data) 2058 { 2059 bus_space_tag_t st = sc->sc_st; 2060 bus_space_handle_t sh = sc->sc_sh; 2061 u_int16_t reg; 2062 int i, x; 2063 2064 for (i = 0; i < wordcnt; i++) { 2065 /* Send CHIP SELECT. */ 2066 reg = EROMAR_EECS; 2067 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2068 2069 /* Shift in the READ opcode. */ 2070 for (x = 3; x > 0; x--) { 2071 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2072 reg |= EROMAR_EEDI; 2073 else 2074 reg &= ~EROMAR_EEDI; 2075 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2076 bus_space_write_4(st, sh, SIP_EROMAR, 2077 reg | EROMAR_EESK); 2078 delay(4); 2079 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2080 delay(4); 2081 } 2082 2083 /* Shift in address. */ 2084 for (x = 6; x > 0; x--) { 2085 if ((word + i) & (1 << (x - 1))) 2086 reg |= EROMAR_EEDI; 2087 else 2088 reg &= ~EROMAR_EEDI; 2089 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2090 bus_space_write_4(st, sh, SIP_EROMAR, 2091 reg | EROMAR_EESK); 2092 delay(4); 2093 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2094 delay(4); 2095 } 2096 2097 /* Shift out data. */ 2098 reg = EROMAR_EECS; 2099 data[i] = 0; 2100 for (x = 16; x > 0; x--) { 2101 bus_space_write_4(st, sh, SIP_EROMAR, 2102 reg | EROMAR_EESK); 2103 delay(4); 2104 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2105 data[i] |= (1 << (x - 1)); 2106 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2107 delay(4); 2108 } 2109 2110 /* Clear CHIP SELECT. */ 2111 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2112 delay(4); 2113 } 2114 } 2115 2116 /* 2117 * sip_add_rxbuf: 2118 * 2119 * Add a receive buffer to the indicated descriptor. 2120 */ 2121 int 2122 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2123 { 2124 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2125 struct mbuf *m; 2126 int error; 2127 2128 MGETHDR(m, M_DONTWAIT, MT_DATA); 2129 if (m == NULL) 2130 return (ENOBUFS); 2131 2132 MCLGET(m, M_DONTWAIT); 2133 if ((m->m_flags & M_EXT) == 0) { 2134 m_freem(m); 2135 return (ENOBUFS); 2136 } 2137 2138 if (rxs->rxs_mbuf != NULL) 2139 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2140 2141 rxs->rxs_mbuf = m; 2142 2143 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2144 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 2145 if (error) { 2146 printf("%s: can't load rx DMA map %d, error = %d\n", 2147 sc->sc_dev.dv_xname, idx, error); 2148 panic("sip_add_rxbuf"); /* XXX */ 2149 } 2150 2151 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2152 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2153 2154 SIP_INIT_RXDESC(sc, idx); 2155 2156 return (0); 2157 } 2158 2159 #if !defined(DP83820) 2160 /* 2161 * sip_sis900_set_filter: 2162 * 2163 * Set up the receive filter. 2164 */ 2165 void 2166 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2167 { 2168 bus_space_tag_t st = sc->sc_st; 2169 bus_space_handle_t sh = sc->sc_sh; 2170 struct ethercom *ec = &sc->sc_ethercom; 2171 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2172 struct ether_multi *enm; 2173 u_int8_t *cp; 2174 struct ether_multistep step; 2175 u_int32_t crc, mchash[8]; 2176 2177 /* 2178 * Initialize the prototype RFCR. 2179 */ 2180 sc->sc_rfcr = RFCR_RFEN; 2181 if (ifp->if_flags & IFF_BROADCAST) 2182 sc->sc_rfcr |= RFCR_AAB; 2183 if (ifp->if_flags & IFF_PROMISC) { 2184 sc->sc_rfcr |= RFCR_AAP; 2185 goto allmulti; 2186 } 2187 2188 /* 2189 * Set up the multicast address filter by passing all multicast 2190 * addresses through a CRC generator, and then using the high-order 2191 * 6 bits as an index into the 128 bit multicast hash table (only 2192 * the lower 16 bits of each 32 bit multicast hash register are 2193 * valid). The high order bits select the register, while the 2194 * rest of the bits select the bit within the register. 2195 */ 2196 2197 memset(mchash, 0, sizeof(mchash)); 2198 2199 ETHER_FIRST_MULTI(step, ec, enm); 2200 while (enm != NULL) { 2201 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2202 /* 2203 * We must listen to a range of multicast addresses. 2204 * For now, just accept all multicasts, rather than 2205 * trying to set only those filter bits needed to match 2206 * the range. (At this time, the only use of address 2207 * ranges is for IP multicast routing, for which the 2208 * range is big enough to require all bits set.) 2209 */ 2210 goto allmulti; 2211 } 2212 2213 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2214 2215 /* Just want the 7 most significant bits. */ 2216 crc >>= 25; 2217 2218 /* Set the corresponding bit in the hash table. */ 2219 mchash[crc >> 4] |= 1 << (crc & 0xf); 2220 2221 ETHER_NEXT_MULTI(step, enm); 2222 } 2223 2224 ifp->if_flags &= ~IFF_ALLMULTI; 2225 goto setit; 2226 2227 allmulti: 2228 ifp->if_flags |= IFF_ALLMULTI; 2229 sc->sc_rfcr |= RFCR_AAM; 2230 2231 setit: 2232 #define FILTER_EMIT(addr, data) \ 2233 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2234 delay(1); \ 2235 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2236 delay(1) 2237 2238 /* 2239 * Disable receive filter, and program the node address. 2240 */ 2241 cp = LLADDR(ifp->if_sadl); 2242 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2243 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2244 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2245 2246 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2247 /* 2248 * Program the multicast hash table. 2249 */ 2250 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2251 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2252 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2253 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2254 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2255 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2256 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2257 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2258 } 2259 #undef FILTER_EMIT 2260 2261 /* 2262 * Re-enable the receiver filter. 2263 */ 2264 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2265 } 2266 #endif /* ! DP83820 */ 2267 2268 /* 2269 * sip_dp83815_set_filter: 2270 * 2271 * Set up the receive filter. 2272 */ 2273 void 2274 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2275 { 2276 bus_space_tag_t st = sc->sc_st; 2277 bus_space_handle_t sh = sc->sc_sh; 2278 struct ethercom *ec = &sc->sc_ethercom; 2279 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2280 struct ether_multi *enm; 2281 u_int8_t *cp; 2282 struct ether_multistep step; 2283 u_int32_t crc, hash, slot, bit; 2284 #ifdef DP83820 2285 #define MCHASH_NWORDS 128 2286 #else 2287 #define MCHASH_NWORDS 32 2288 #endif /* DP83820 */ 2289 u_int16_t mchash[MCHASH_NWORDS]; 2290 int i; 2291 2292 /* 2293 * Initialize the prototype RFCR. 2294 * Enable the receive filter, and accept on 2295 * Perfect (destination address) Match 2296 * If IFF_BROADCAST, also accept all broadcast packets. 2297 * If IFF_PROMISC, accept all unicast packets (and later, set 2298 * IFF_ALLMULTI and accept all multicast, too). 2299 */ 2300 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2301 if (ifp->if_flags & IFF_BROADCAST) 2302 sc->sc_rfcr |= RFCR_AAB; 2303 if (ifp->if_flags & IFF_PROMISC) { 2304 sc->sc_rfcr |= RFCR_AAP; 2305 goto allmulti; 2306 } 2307 2308 #ifdef DP83820 2309 /* 2310 * Set up the DP83820 multicast address filter by passing all multicast 2311 * addresses through a CRC generator, and then using the high-order 2312 * 11 bits as an index into the 2048 bit multicast hash table. The 2313 * high-order 7 bits select the slot, while the low-order 4 bits 2314 * select the bit within the slot. Note that only the low 16-bits 2315 * of each filter word are used, and there are 128 filter words. 2316 */ 2317 #else 2318 /* 2319 * Set up the DP83815 multicast address filter by passing all multicast 2320 * addresses through a CRC generator, and then using the high-order 2321 * 9 bits as an index into the 512 bit multicast hash table. The 2322 * high-order 5 bits select the slot, while the low-order 4 bits 2323 * select the bit within the slot. Note that only the low 16-bits 2324 * of each filter word are used, and there are 32 filter words. 2325 */ 2326 #endif /* DP83820 */ 2327 2328 memset(mchash, 0, sizeof(mchash)); 2329 2330 ifp->if_flags &= ~IFF_ALLMULTI; 2331 ETHER_FIRST_MULTI(step, ec, enm); 2332 if (enm != NULL) { 2333 while (enm != NULL) { 2334 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2335 ETHER_ADDR_LEN)) { 2336 /* 2337 * We must listen to a range of multicast addresses. 2338 * For now, just accept all multicasts, rather than 2339 * trying to set only those filter bits needed to match 2340 * the range. (At this time, the only use of address 2341 * ranges is for IP multicast routing, for which the 2342 * range is big enough to require all bits set.) 2343 */ 2344 goto allmulti; 2345 } 2346 2347 #ifdef DP83820 2348 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2349 2350 /* Just want the 11 most significant bits. */ 2351 hash = crc >> 21; 2352 #else 2353 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2354 2355 /* Just want the 9 most significant bits. */ 2356 hash = crc >> 23; 2357 #endif /* DP83820 */ 2358 slot = hash >> 4; 2359 bit = hash & 0xf; 2360 2361 /* Set the corresponding bit in the hash table. */ 2362 mchash[slot] |= 1 << bit; 2363 2364 ETHER_NEXT_MULTI(step, enm); 2365 } 2366 2367 sc->sc_rfcr |= RFCR_MHEN; 2368 } 2369 goto setit; 2370 2371 allmulti: 2372 ifp->if_flags |= IFF_ALLMULTI; 2373 sc->sc_rfcr |= RFCR_AAM; 2374 2375 setit: 2376 #define FILTER_EMIT(addr, data) \ 2377 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2378 delay(1); \ 2379 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2380 delay(1); 2381 2382 /* 2383 * Disable receive filter, and program the node address. 2384 */ 2385 cp = LLADDR(ifp->if_sadl); 2386 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 2387 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 2388 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 2389 2390 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2391 /* 2392 * Program the multicast hash table. 2393 */ 2394 for (i = 0; i < MCHASH_NWORDS; i++) 2395 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 2396 mchash[i]); 2397 } 2398 #undef FILTER_EMIT 2399 #undef MCHASH_NWORDS 2400 2401 /* 2402 * Re-enable the receiver filter. 2403 */ 2404 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2405 } 2406 2407 #if defined(DP83820) 2408 /* 2409 * sip_dp83820_mii_readreg: [mii interface function] 2410 * 2411 * Read a PHY register on the MII of the DP83820. 2412 */ 2413 int 2414 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 2415 { 2416 2417 return (mii_bitbang_readreg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2418 phy, reg)); 2419 } 2420 2421 /* 2422 * sip_dp83820_mii_writereg: [mii interface function] 2423 * 2424 * Write a PHY register on the MII of the DP83820. 2425 */ 2426 void 2427 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 2428 { 2429 2430 mii_bitbang_writereg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2431 phy, reg, val); 2432 } 2433 2434 /* 2435 * sip_dp83815_mii_statchg: [mii interface function] 2436 * 2437 * Callback from MII layer when media changes. 2438 */ 2439 void 2440 SIP_DECL(dp83820_mii_statchg)(struct device *self) 2441 { 2442 struct sip_softc *sc = (struct sip_softc *) self; 2443 u_int32_t cfg; 2444 2445 /* 2446 * Update TXCFG for full-duplex operation. 2447 */ 2448 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2449 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2450 else 2451 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2452 2453 /* 2454 * Update RXCFG for full-duplex or loopback. 2455 */ 2456 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2457 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2458 sc->sc_rxcfg |= RXCFG_ATX; 2459 else 2460 sc->sc_rxcfg &= ~RXCFG_ATX; 2461 2462 /* 2463 * Update CFG for MII/GMII. 2464 */ 2465 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2466 cfg = sc->sc_cfg | CFG_MODE_1000; 2467 else 2468 cfg = sc->sc_cfg; 2469 2470 /* 2471 * XXX 802.3x flow control. 2472 */ 2473 2474 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 2475 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2476 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2477 } 2478 2479 /* 2480 * sip_dp83820_mii_bitbang_read: [mii bit-bang interface function] 2481 * 2482 * Read the MII serial port for the MII bit-bang module. 2483 */ 2484 u_int32_t 2485 SIP_DECL(dp83820_mii_bitbang_read)(struct device *self) 2486 { 2487 struct sip_softc *sc = (void *) self; 2488 2489 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 2490 } 2491 2492 /* 2493 * sip_dp83820_mii_bitbang_write: [mii big-bang interface function] 2494 * 2495 * Write the MII serial port for the MII bit-bang module. 2496 */ 2497 void 2498 SIP_DECL(dp83820_mii_bitbang_write)(struct device *self, u_int32_t val) 2499 { 2500 struct sip_softc *sc = (void *) self; 2501 2502 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 2503 } 2504 #else /* ! DP83820 */ 2505 /* 2506 * sip_sis900_mii_readreg: [mii interface function] 2507 * 2508 * Read a PHY register on the MII. 2509 */ 2510 int 2511 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 2512 { 2513 struct sip_softc *sc = (struct sip_softc *) self; 2514 u_int32_t enphy; 2515 2516 /* 2517 * The SiS 900 has only an internal PHY on the MII. Only allow 2518 * MII address 0. 2519 */ 2520 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 2521 return (0); 2522 2523 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2524 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 2525 ENPHY_RWCMD | ENPHY_ACCESS); 2526 do { 2527 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2528 } while (enphy & ENPHY_ACCESS); 2529 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 2530 } 2531 2532 /* 2533 * sip_sis900_mii_writereg: [mii interface function] 2534 * 2535 * Write a PHY register on the MII. 2536 */ 2537 void 2538 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 2539 { 2540 struct sip_softc *sc = (struct sip_softc *) self; 2541 u_int32_t enphy; 2542 2543 /* 2544 * The SiS 900 has only an internal PHY on the MII. Only allow 2545 * MII address 0. 2546 */ 2547 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 2548 return; 2549 2550 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2551 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 2552 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 2553 do { 2554 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2555 } while (enphy & ENPHY_ACCESS); 2556 } 2557 2558 /* 2559 * sip_sis900_mii_statchg: [mii interface function] 2560 * 2561 * Callback from MII layer when media changes. 2562 */ 2563 void 2564 SIP_DECL(sis900_mii_statchg)(struct device *self) 2565 { 2566 struct sip_softc *sc = (struct sip_softc *) self; 2567 u_int32_t flowctl; 2568 2569 /* 2570 * Update TXCFG for full-duplex operation. 2571 */ 2572 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2573 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2574 else 2575 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2576 2577 /* 2578 * Update RXCFG for full-duplex or loopback. 2579 */ 2580 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2581 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2582 sc->sc_rxcfg |= RXCFG_ATX; 2583 else 2584 sc->sc_rxcfg &= ~RXCFG_ATX; 2585 2586 /* 2587 * Update IMR for use of 802.3x flow control. 2588 */ 2589 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 2590 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 2591 flowctl = FLOWCTL_FLOWEN; 2592 } else { 2593 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 2594 flowctl = 0; 2595 } 2596 2597 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2598 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2599 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 2600 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 2601 } 2602 2603 /* 2604 * sip_dp83815_mii_readreg: [mii interface function] 2605 * 2606 * Read a PHY register on the MII. 2607 */ 2608 int 2609 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 2610 { 2611 struct sip_softc *sc = (struct sip_softc *) self; 2612 u_int32_t val; 2613 2614 /* 2615 * The DP83815 only has an internal PHY. Only allow 2616 * MII address 0. 2617 */ 2618 if (phy != 0) 2619 return (0); 2620 2621 /* 2622 * Apparently, after a reset, the DP83815 can take a while 2623 * to respond. During this recovery period, the BMSR returns 2624 * a value of 0. Catch this -- it's not supposed to happen 2625 * (the BMSR has some hardcoded-to-1 bits), and wait for the 2626 * PHY to come back to life. 2627 * 2628 * This works out because the BMSR is the first register 2629 * read during the PHY probe process. 2630 */ 2631 do { 2632 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 2633 } while (reg == MII_BMSR && val == 0); 2634 2635 return (val & 0xffff); 2636 } 2637 2638 /* 2639 * sip_dp83815_mii_writereg: [mii interface function] 2640 * 2641 * Write a PHY register to the MII. 2642 */ 2643 void 2644 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 2645 { 2646 struct sip_softc *sc = (struct sip_softc *) self; 2647 2648 /* 2649 * The DP83815 only has an internal PHY. Only allow 2650 * MII address 0. 2651 */ 2652 if (phy != 0) 2653 return; 2654 2655 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 2656 } 2657 2658 /* 2659 * sip_dp83815_mii_statchg: [mii interface function] 2660 * 2661 * Callback from MII layer when media changes. 2662 */ 2663 void 2664 SIP_DECL(dp83815_mii_statchg)(struct device *self) 2665 { 2666 struct sip_softc *sc = (struct sip_softc *) self; 2667 2668 /* 2669 * Update TXCFG for full-duplex operation. 2670 */ 2671 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2672 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2673 else 2674 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2675 2676 /* 2677 * Update RXCFG for full-duplex or loopback. 2678 */ 2679 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2680 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2681 sc->sc_rxcfg |= RXCFG_ATX; 2682 else 2683 sc->sc_rxcfg &= ~RXCFG_ATX; 2684 2685 /* 2686 * XXX 802.3x flow control. 2687 */ 2688 2689 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2690 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2691 } 2692 #endif /* DP83820 */ 2693 2694 #if defined(DP83820) 2695 void 2696 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, u_int8_t *enaddr) 2697 { 2698 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 2699 u_int8_t cksum, *e, match; 2700 int i; 2701 2702 /* 2703 * EEPROM data format for the DP83820 can be found in 2704 * the DP83820 manual, section 4.2.4. 2705 */ 2706 2707 SIP_DECL(read_eeprom)(sc, 0, 2708 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 2709 2710 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 2711 match = ~(match - 1); 2712 2713 cksum = 0x55; 2714 e = (u_int8_t *) eeprom_data; 2715 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 2716 cksum += *e++; 2717 2718 if (cksum != match) 2719 printf("%s: Checksum (%x) mismatch (%x)", 2720 sc->sc_dev.dv_xname, cksum, match); 2721 2722 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 2723 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 2724 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 2725 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 2726 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 2727 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 2728 2729 /* Get the GPIOR bits. */ 2730 sc->sc_gpior = eeprom_data[0x04]; 2731 2732 /* Get various CFG related bits. */ 2733 if ((eeprom_data[0x05] >> 0) & 1) 2734 sc->sc_cfg |= CFG_EXT_125; 2735 if ((eeprom_data[0x05] >> 9) & 1) 2736 sc->sc_cfg |= CFG_TBI_EN; 2737 } 2738 #else /* ! DP83820 */ 2739 void 2740 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, u_int8_t *enaddr) 2741 { 2742 u_int16_t myea[ETHER_ADDR_LEN / 2]; 2743 2744 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 2745 sizeof(myea) / sizeof(myea[0]), myea); 2746 2747 enaddr[0] = myea[0] & 0xff; 2748 enaddr[1] = myea[0] >> 8; 2749 enaddr[2] = myea[1] & 0xff; 2750 enaddr[3] = myea[1] >> 8; 2751 enaddr[4] = myea[2] & 0xff; 2752 enaddr[5] = myea[2] >> 8; 2753 } 2754 2755 /* Table and macro to bit-reverse an octet. */ 2756 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 2757 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 2758 2759 void 2760 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, u_int8_t *enaddr) 2761 { 2762 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 2763 u_int8_t cksum, *e, match; 2764 int i; 2765 2766 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 2767 sizeof(eeprom_data[0]), eeprom_data); 2768 2769 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 2770 match = ~(match - 1); 2771 2772 cksum = 0x55; 2773 e = (u_int8_t *) eeprom_data; 2774 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 2775 cksum += *e++; 2776 } 2777 if (cksum != match) { 2778 printf("%s: Checksum (%x) mismatch (%x)", 2779 sc->sc_dev.dv_xname, cksum, match); 2780 } 2781 2782 /* 2783 * Unrolled because it makes slightly more sense this way. 2784 * The DP83815 stores the MAC address in bit 0 of word 6 2785 * through bit 15 of word 8. 2786 */ 2787 ea = &eeprom_data[6]; 2788 enaddr[0] = ((*ea & 0x1) << 7); 2789 ea++; 2790 enaddr[0] |= ((*ea & 0xFE00) >> 9); 2791 enaddr[1] = ((*ea & 0x1FE) >> 1); 2792 enaddr[2] = ((*ea & 0x1) << 7); 2793 ea++; 2794 enaddr[2] |= ((*ea & 0xFE00) >> 9); 2795 enaddr[3] = ((*ea & 0x1FE) >> 1); 2796 enaddr[4] = ((*ea & 0x1) << 7); 2797 ea++; 2798 enaddr[4] |= ((*ea & 0xFE00) >> 9); 2799 enaddr[5] = ((*ea & 0x1FE) >> 1); 2800 2801 /* 2802 * In case that's not weird enough, we also need to reverse 2803 * the bits in each byte. This all actually makes more sense 2804 * if you think about the EEPROM storage as an array of bits 2805 * being shifted into bytes, but that's not how we're looking 2806 * at it here... 2807 */ 2808 for (i = 0; i < 6 ;i++) 2809 enaddr[i] = bbr(enaddr[i]); 2810 } 2811 #endif /* DP83820 */ 2812 2813 /* 2814 * sip_mediastatus: [ifmedia interface function] 2815 * 2816 * Get the current interface media status. 2817 */ 2818 void 2819 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 2820 { 2821 struct sip_softc *sc = ifp->if_softc; 2822 2823 mii_pollstat(&sc->sc_mii); 2824 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2825 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2826 } 2827 2828 /* 2829 * sip_mediachange: [ifmedia interface function] 2830 * 2831 * Set hardware to newly-selected media. 2832 */ 2833 int 2834 SIP_DECL(mediachange)(struct ifnet *ifp) 2835 { 2836 struct sip_softc *sc = ifp->if_softc; 2837 2838 if (ifp->if_flags & IFF_UP) 2839 mii_mediachg(&sc->sc_mii); 2840 return (0); 2841 } 2842
Indexes created Tue Sep 30 11:09:46 GMT 2025