if_sip.c revision 1.32
1 /* $NetBSD: if_sip.c,v 1.32 2001/06/03 03:55:10 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Support the 10-bit interface on the DP83820 (for fiber). 80 * 81 * - Support jumbo packets on the DP83820. 82 * 83 * - Reduce the interrupt load. 84 */ 85 86 #include "opt_inet.h" 87 #include "opt_ns.h" 88 #include "bpfilter.h" 89 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/callout.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/socket.h> 97 #include <sys/ioctl.h> 98 #include <sys/errno.h> 99 #include <sys/device.h> 100 #include <sys/queue.h> 101 102 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 103 104 #include <net/if.h> 105 #include <net/if_dl.h> 106 #include <net/if_media.h> 107 #include <net/if_ether.h> 108 109 #if NBPFILTER > 0 110 #include <net/bpf.h> 111 #endif 112 113 #ifdef INET 114 #include <netinet/in.h> 115 #include <netinet/if_inarp.h> 116 #endif 117 118 #ifdef NS 119 #include <netns/ns.h> 120 #include <netns/ns_if.h> 121 #endif 122 123 #include <machine/bus.h> 124 #include <machine/intr.h> 125 #include <machine/endian.h> 126 127 #include <dev/mii/mii.h> 128 #include <dev/mii/miivar.h> 129 #ifdef DP83820 130 #include <dev/mii/mii_bitbang.h> 131 #endif /* DP83820 */ 132 133 #include <dev/pci/pcireg.h> 134 #include <dev/pci/pcivar.h> 135 #include <dev/pci/pcidevs.h> 136 137 #include <dev/pci/if_sipreg.h> 138 139 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 140 #define SIP_DECL(x) __CONCAT(gsip_,x) 141 #else /* SiS900 and DP83815 */ 142 #define SIP_DECL(x) __CONCAT(sip_,x) 143 #endif 144 145 #define SIP_STR(x) __STRING(SIP_DECL(x)) 146 147 /* 148 * Transmit descriptor list size. This is arbitrary, but allocate 149 * enough descriptors for 128 pending transmissions, and 8 segments 150 * per packet. This MUST work out to a power of 2. 151 */ 152 #define SIP_NTXSEGS 8 153 154 #define SIP_TXQUEUELEN 256 155 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS) 156 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 157 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 158 159 /* 160 * Receive descriptor list size. We have one Rx buffer per incoming 161 * packet, so this logic is a little simpler. 162 */ 163 #define SIP_NRXDESC 128 164 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 165 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 166 167 /* 168 * Control structures are DMA'd to the SiS900 chip. We allocate them in 169 * a single clump that maps to a single DMA segment to make several things 170 * easier. 171 */ 172 struct sip_control_data { 173 /* 174 * The transmit descriptors. 175 */ 176 struct sip_desc scd_txdescs[SIP_NTXDESC]; 177 178 /* 179 * The receive descriptors. 180 */ 181 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 182 }; 183 184 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 185 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 186 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 187 188 /* 189 * Software state for transmit jobs. 190 */ 191 struct sip_txsoft { 192 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 193 bus_dmamap_t txs_dmamap; /* our DMA map */ 194 int txs_firstdesc; /* first descriptor in packet */ 195 int txs_lastdesc; /* last descriptor in packet */ 196 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 197 }; 198 199 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 200 201 /* 202 * Software state for receive jobs. 203 */ 204 struct sip_rxsoft { 205 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 206 bus_dmamap_t rxs_dmamap; /* our DMA map */ 207 }; 208 209 /* 210 * Software state per device. 211 */ 212 struct sip_softc { 213 struct device sc_dev; /* generic device information */ 214 bus_space_tag_t sc_st; /* bus space tag */ 215 bus_space_handle_t sc_sh; /* bus space handle */ 216 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 217 struct ethercom sc_ethercom; /* ethernet common data */ 218 void *sc_sdhook; /* shutdown hook */ 219 220 const struct sip_product *sc_model; /* which model are we? */ 221 222 void *sc_ih; /* interrupt cookie */ 223 224 struct mii_data sc_mii; /* MII/media information */ 225 226 struct callout sc_tick_ch; /* tick callout */ 227 228 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 229 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 230 231 /* 232 * Software state for transmit and receive descriptors. 233 */ 234 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 235 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 236 237 /* 238 * Control data structures. 239 */ 240 struct sip_control_data *sc_control_data; 241 #define sc_txdescs sc_control_data->scd_txdescs 242 #define sc_rxdescs sc_control_data->scd_rxdescs 243 244 #ifdef SIP_EVENT_COUNTERS 245 /* 246 * Event counters. 247 */ 248 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 249 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 250 struct evcnt sc_ev_txintr; /* Tx interrupts */ 251 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 252 #ifdef DP83820 253 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 254 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 255 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 256 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 257 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 258 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 259 #endif /* DP83820 */ 260 #endif /* SIP_EVENT_COUNTERS */ 261 262 u_int32_t sc_txcfg; /* prototype TXCFG register */ 263 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 264 u_int32_t sc_imr; /* prototype IMR register */ 265 u_int32_t sc_rfcr; /* prototype RFCR register */ 266 267 u_int32_t sc_cfg; /* prototype CFG register */ 268 269 #ifdef DP83820 270 u_int32_t sc_gpior; /* prototype GPIOR register */ 271 #endif /* DP83820 */ 272 273 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 274 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 275 276 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 277 278 int sc_flags; /* misc. flags; see below */ 279 280 int sc_txfree; /* number of free Tx descriptors */ 281 int sc_txnext; /* next ready Tx descriptor */ 282 283 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 284 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 285 286 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 287 }; 288 289 /* sc_flags */ 290 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 291 292 #ifdef SIP_EVENT_COUNTERS 293 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 294 #else 295 #define SIP_EVCNT_INCR(ev) /* nothing */ 296 #endif 297 298 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 299 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 300 301 #define SIP_CDTXSYNC(sc, x, n, ops) \ 302 do { \ 303 int __x, __n; \ 304 \ 305 __x = (x); \ 306 __n = (n); \ 307 \ 308 /* If it will wrap around, sync to the end of the ring. */ \ 309 if ((__x + __n) > SIP_NTXDESC) { \ 310 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 311 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 312 (SIP_NTXDESC - __x), (ops)); \ 313 __n -= (SIP_NTXDESC - __x); \ 314 __x = 0; \ 315 } \ 316 \ 317 /* Now sync whatever is left. */ \ 318 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 319 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 320 } while (0) 321 322 #define SIP_CDRXSYNC(sc, x, ops) \ 323 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 324 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 325 326 /* 327 * Note we rely on MCLBYTES being a power of two below. 328 */ 329 #ifdef DP83820 330 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 331 #else 332 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 333 #endif 334 #define SIP_INIT_RXDESC(sc, x) \ 335 do { \ 336 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 337 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 338 \ 339 __sipd->sipd_link = htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 340 __sipd->sipd_bufptr = htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 341 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 342 ((MCLBYTES - 1) & CMDSTS_SIZE_MASK)); \ 343 SIP_INIT_RXDESC_EXTSTS \ 344 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 345 } while (0) 346 347 #define SIP_TIMEOUT 1000 348 349 void SIP_DECL(start)(struct ifnet *); 350 void SIP_DECL(watchdog)(struct ifnet *); 351 int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 352 int SIP_DECL(init)(struct ifnet *); 353 void SIP_DECL(stop)(struct ifnet *, int); 354 355 void SIP_DECL(shutdown)(void *); 356 357 void SIP_DECL(reset)(struct sip_softc *); 358 void SIP_DECL(rxdrain)(struct sip_softc *); 359 int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 360 void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, u_int16_t *); 361 void SIP_DECL(tick)(void *); 362 363 #if !defined(DP83820) 364 void SIP_DECL(sis900_set_filter)(struct sip_softc *); 365 #endif /* ! DP83820 */ 366 void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 367 368 #if defined(DP83820) 369 void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, u_int8_t *); 370 #else 371 void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, u_int8_t *); 372 void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, u_int8_t *); 373 #endif /* DP83820 */ 374 375 int SIP_DECL(intr)(void *); 376 void SIP_DECL(txintr)(struct sip_softc *); 377 void SIP_DECL(rxintr)(struct sip_softc *); 378 379 #if defined(DP83820) 380 int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 381 void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 382 void SIP_DECL(dp83820_mii_statchg)(struct device *); 383 #else 384 int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 385 void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 386 void SIP_DECL(sis900_mii_statchg)(struct device *); 387 388 int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 389 void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 390 void SIP_DECL(dp83815_mii_statchg)(struct device *); 391 #endif /* DP83820 */ 392 393 int SIP_DECL(mediachange)(struct ifnet *); 394 void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 395 396 int SIP_DECL(match)(struct device *, struct cfdata *, void *); 397 void SIP_DECL(attach)(struct device *, struct device *, void *); 398 399 int SIP_DECL(copy_small) = 0; 400 401 struct cfattach SIP_DECL(ca) = { 402 sizeof(struct sip_softc), SIP_DECL(match), SIP_DECL(attach), 403 }; 404 405 /* 406 * Descriptions of the variants of the SiS900. 407 */ 408 struct sip_variant { 409 int (*sipv_mii_readreg)(struct device *, int, int); 410 void (*sipv_mii_writereg)(struct device *, int, int, int); 411 void (*sipv_mii_statchg)(struct device *); 412 void (*sipv_set_filter)(struct sip_softc *); 413 void (*sipv_read_macaddr)(struct sip_softc *, u_int8_t *); 414 }; 415 416 #if defined(DP83820) 417 u_int32_t SIP_DECL(dp83820_mii_bitbang_read)(struct device *); 418 void SIP_DECL(dp83820_mii_bitbang_write)(struct device *, u_int32_t); 419 420 const struct mii_bitbang_ops SIP_DECL(dp83820_mii_bitbang_ops) = { 421 SIP_DECL(dp83820_mii_bitbang_read), 422 SIP_DECL(dp83820_mii_bitbang_write), 423 { 424 EROMAR_MDIO, /* MII_BIT_MDO */ 425 EROMAR_MDIO, /* MII_BIT_MDI */ 426 EROMAR_MDC, /* MII_BIT_MDC */ 427 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 428 0, /* MII_BIT_DIR_PHY_HOST */ 429 } 430 }; 431 #endif /* DP83820 */ 432 433 #if defined(DP83820) 434 const struct sip_variant SIP_DECL(variant_dp83820) = { 435 SIP_DECL(dp83820_mii_readreg), 436 SIP_DECL(dp83820_mii_writereg), 437 SIP_DECL(dp83820_mii_statchg), 438 SIP_DECL(dp83815_set_filter), 439 SIP_DECL(dp83820_read_macaddr), 440 }; 441 #else 442 const struct sip_variant SIP_DECL(variant_sis900) = { 443 SIP_DECL(sis900_mii_readreg), 444 SIP_DECL(sis900_mii_writereg), 445 SIP_DECL(sis900_mii_statchg), 446 SIP_DECL(sis900_set_filter), 447 SIP_DECL(sis900_read_macaddr), 448 }; 449 450 const struct sip_variant SIP_DECL(variant_dp83815) = { 451 SIP_DECL(dp83815_mii_readreg), 452 SIP_DECL(dp83815_mii_writereg), 453 SIP_DECL(dp83815_mii_statchg), 454 SIP_DECL(dp83815_set_filter), 455 SIP_DECL(dp83815_read_macaddr), 456 }; 457 #endif /* DP83820 */ 458 459 /* 460 * Devices supported by this driver. 461 */ 462 const struct sip_product { 463 pci_vendor_id_t sip_vendor; 464 pci_product_id_t sip_product; 465 const char *sip_name; 466 const struct sip_variant *sip_variant; 467 } SIP_DECL(products)[] = { 468 #if defined(DP83820) 469 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 470 "NatSemi DP83820 Gigabit Ethernet", 471 &SIP_DECL(variant_dp83820) }, 472 #else 473 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 474 "SiS 900 10/100 Ethernet", 475 &SIP_DECL(variant_sis900) }, 476 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 477 "SiS 7016 10/100 Ethernet", 478 &SIP_DECL(variant_sis900) }, 479 480 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 481 "NatSemi DP83815 10/100 Ethernet", 482 &SIP_DECL(variant_dp83815) }, 483 #endif /* DP83820 */ 484 485 { 0, 0, 486 NULL, 487 NULL }, 488 }; 489 490 static const struct sip_product * 491 SIP_DECL(lookup)(const struct pci_attach_args *pa) 492 { 493 const struct sip_product *sip; 494 495 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 496 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 497 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 498 return (sip); 499 } 500 return (NULL); 501 } 502 503 int 504 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 505 { 506 struct pci_attach_args *pa = aux; 507 508 if (SIP_DECL(lookup)(pa) != NULL) 509 return (1); 510 511 return (0); 512 } 513 514 void 515 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 516 { 517 struct sip_softc *sc = (struct sip_softc *) self; 518 struct pci_attach_args *pa = aux; 519 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 520 pci_chipset_tag_t pc = pa->pa_pc; 521 pci_intr_handle_t ih; 522 const char *intrstr = NULL; 523 bus_space_tag_t iot, memt; 524 bus_space_handle_t ioh, memh; 525 bus_dma_segment_t seg; 526 int ioh_valid, memh_valid; 527 int i, rseg, error; 528 const struct sip_product *sip; 529 pcireg_t pmode; 530 u_int8_t enaddr[ETHER_ADDR_LEN]; 531 int pmreg; 532 #ifdef DP83820 533 pcireg_t memtype; 534 u_int32_t reg; 535 #endif /* DP83820 */ 536 537 callout_init(&sc->sc_tick_ch); 538 539 sip = SIP_DECL(lookup)(pa); 540 if (sip == NULL) { 541 printf("\n"); 542 panic(SIP_STR(attach) ": impossible"); 543 } 544 545 printf(": %s\n", sip->sip_name); 546 547 sc->sc_model = sip; 548 549 /* 550 * Map the device. 551 */ 552 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 553 PCI_MAPREG_TYPE_IO, 0, 554 &iot, &ioh, NULL, NULL) == 0); 555 #ifdef DP83820 556 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 557 switch (memtype) { 558 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 559 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 560 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 561 memtype, 0, &memt, &memh, NULL, NULL) == 0); 562 break; 563 default: 564 memh_valid = 0; 565 } 566 #else 567 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 568 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 569 &memt, &memh, NULL, NULL) == 0); 570 #endif /* DP83820 */ 571 572 if (memh_valid) { 573 sc->sc_st = memt; 574 sc->sc_sh = memh; 575 } else if (ioh_valid) { 576 sc->sc_st = iot; 577 sc->sc_sh = ioh; 578 } else { 579 printf("%s: unable to map device registers\n", 580 sc->sc_dev.dv_xname); 581 return; 582 } 583 584 sc->sc_dmat = pa->pa_dmat; 585 586 /* Enable bus mastering. */ 587 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 588 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 589 PCI_COMMAND_MASTER_ENABLE); 590 591 /* Get it out of power save mode if needed. */ 592 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 593 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 594 if (pmode == 3) { 595 /* 596 * The card has lost all configuration data in 597 * this state, so punt. 598 */ 599 printf("%s: unable to wake up from power state D3\n", 600 sc->sc_dev.dv_xname); 601 return; 602 } 603 if (pmode != 0) { 604 printf("%s: waking up from power state D%d\n", 605 sc->sc_dev.dv_xname, pmode); 606 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 607 } 608 } 609 610 /* 611 * Map and establish our interrupt. 612 */ 613 if (pci_intr_map(pa, &ih)) { 614 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 615 return; 616 } 617 intrstr = pci_intr_string(pc, ih); 618 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 619 if (sc->sc_ih == NULL) { 620 printf("%s: unable to establish interrupt", 621 sc->sc_dev.dv_xname); 622 if (intrstr != NULL) 623 printf(" at %s", intrstr); 624 printf("\n"); 625 return; 626 } 627 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 628 629 SIMPLEQ_INIT(&sc->sc_txfreeq); 630 SIMPLEQ_INIT(&sc->sc_txdirtyq); 631 632 /* 633 * Allocate the control data structures, and create and load the 634 * DMA map for it. 635 */ 636 if ((error = bus_dmamem_alloc(sc->sc_dmat, 637 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 638 0)) != 0) { 639 printf("%s: unable to allocate control data, error = %d\n", 640 sc->sc_dev.dv_xname, error); 641 goto fail_0; 642 } 643 644 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 645 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 646 BUS_DMA_COHERENT)) != 0) { 647 printf("%s: unable to map control data, error = %d\n", 648 sc->sc_dev.dv_xname, error); 649 goto fail_1; 650 } 651 652 if ((error = bus_dmamap_create(sc->sc_dmat, 653 sizeof(struct sip_control_data), 1, 654 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 655 printf("%s: unable to create control data DMA map, " 656 "error = %d\n", sc->sc_dev.dv_xname, error); 657 goto fail_2; 658 } 659 660 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 661 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 662 0)) != 0) { 663 printf("%s: unable to load control data DMA map, error = %d\n", 664 sc->sc_dev.dv_xname, error); 665 goto fail_3; 666 } 667 668 /* 669 * Create the transmit buffer DMA maps. 670 */ 671 for (i = 0; i < SIP_TXQUEUELEN; i++) { 672 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 673 SIP_NTXSEGS, MCLBYTES, 0, 0, 674 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 675 printf("%s: unable to create tx DMA map %d, " 676 "error = %d\n", sc->sc_dev.dv_xname, i, error); 677 goto fail_4; 678 } 679 } 680 681 /* 682 * Create the receive buffer DMA maps. 683 */ 684 for (i = 0; i < SIP_NRXDESC; i++) { 685 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 686 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 687 printf("%s: unable to create rx DMA map %d, " 688 "error = %d\n", sc->sc_dev.dv_xname, i, error); 689 goto fail_5; 690 } 691 sc->sc_rxsoft[i].rxs_mbuf = NULL; 692 } 693 694 /* 695 * Reset the chip to a known state. 696 */ 697 SIP_DECL(reset)(sc); 698 699 /* 700 * Read the Ethernet address from the EEPROM. This might 701 * also fetch other stuff from the EEPROM and stash it 702 * in the softc. 703 */ 704 sc->sc_cfg = 0; 705 (*sip->sip_variant->sipv_read_macaddr)(sc, enaddr); 706 707 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 708 ether_sprintf(enaddr)); 709 710 /* 711 * Initialize the configuration register: aggressive PCI 712 * bus request algorithm, default backoff, default OW timer, 713 * default parity error detection. 714 * 715 * NOTE: "Big endian mode" is useless on the SiS900 and 716 * friends -- it affects packet data, not descriptors. 717 */ 718 #ifdef DP83820 719 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 720 if (reg & CFG_PCI64_DET) { 721 printf("%s: 64-bit PCI slot detected\n", sc->sc_dev.dv_xname); 722 /* 723 * XXX Need some PCI flags indicating support for 724 * XXX 64-bit addressing (SAC or DAC) and 64-bit 725 * XXX data path. 726 */ 727 } 728 if (sc->sc_cfg & (CFG_TBI_EN|CFG_EXT_125)) { 729 const char *sep = ""; 730 printf("%s: using ", sc->sc_dev.dv_xname); 731 if (sc->sc_cfg & CFG_EXT_125) { 732 printf("%s125MHz clock", sep); 733 sep = ", "; 734 } 735 if (sc->sc_cfg & CFG_TBI_EN) { 736 printf("%sten-bit interface", sep); 737 sep = ", "; 738 } 739 printf("\n"); 740 } 741 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0) 742 sc->sc_cfg |= CFG_MRM_DIS; 743 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 744 sc->sc_cfg |= CFG_MWI_DIS; 745 746 /* 747 * Use the extended descriptor format on the DP83820. This 748 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 749 * checksumming. 750 */ 751 sc->sc_cfg |= CFG_EXTSTS_EN; 752 #endif /* DP83820 */ 753 754 /* 755 * Initialize our media structures and probe the MII. 756 */ 757 sc->sc_mii.mii_ifp = ifp; 758 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 759 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 760 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 761 ifmedia_init(&sc->sc_mii.mii_media, 0, SIP_DECL(mediachange), 762 SIP_DECL(mediastatus)); 763 #ifdef DP83820 764 if (sc->sc_cfg & CFG_TBI_EN) { 765 /* Using ten-bit interface. */ 766 printf("%s: TBI -- FIXME\n", sc->sc_dev.dv_xname); 767 } else { 768 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 769 MII_OFFSET_ANY, 0); 770 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 771 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 772 0, NULL); 773 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 774 } else 775 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 776 } 777 #else 778 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 779 MII_OFFSET_ANY, 0); 780 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 781 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 782 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 783 } else 784 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 785 #endif /* DP83820 */ 786 787 ifp = &sc->sc_ethercom.ec_if; 788 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 789 ifp->if_softc = sc; 790 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 791 ifp->if_ioctl = SIP_DECL(ioctl); 792 ifp->if_start = SIP_DECL(start); 793 ifp->if_watchdog = SIP_DECL(watchdog); 794 ifp->if_init = SIP_DECL(init); 795 ifp->if_stop = SIP_DECL(stop); 796 IFQ_SET_READY(&ifp->if_snd); 797 798 /* 799 * We can support 802.1Q VLAN-sized frames. 800 */ 801 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 802 803 #ifdef DP83820 804 /* 805 * And the DP83820 can do VLAN tagging in hardware. 806 */ 807 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 808 809 /* 810 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 811 * in hardware. 812 */ 813 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 814 IFCAP_CSUM_UDPv4; 815 #endif /* DP83820 */ 816 817 /* 818 * Attach the interface. 819 */ 820 if_attach(ifp); 821 ether_ifattach(ifp, enaddr); 822 823 #ifdef SIP_EVENT_COUNTERS 824 /* 825 * Attach event counters. 826 */ 827 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 828 NULL, sc->sc_dev.dv_xname, "txsstall"); 829 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 830 NULL, sc->sc_dev.dv_xname, "txdstall"); 831 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 832 NULL, sc->sc_dev.dv_xname, "txintr"); 833 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 834 NULL, sc->sc_dev.dv_xname, "rxintr"); 835 #ifdef DP83820 836 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 837 NULL, sc->sc_dev.dv_xname, "rxipsum"); 838 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 839 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 840 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 841 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 842 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 843 NULL, sc->sc_dev.dv_xname, "txipsum"); 844 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 845 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 846 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 847 NULL, sc->sc_dev.dv_xname, "txudpsum"); 848 #endif /* DP83820 */ 849 #endif /* SIP_EVENT_COUNTERS */ 850 851 /* 852 * Make sure the interface is shutdown during reboot. 853 */ 854 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 855 if (sc->sc_sdhook == NULL) 856 printf("%s: WARNING: unable to establish shutdown hook\n", 857 sc->sc_dev.dv_xname); 858 return; 859 860 /* 861 * Free any resources we've allocated during the failed attach 862 * attempt. Do this in reverse order and fall through. 863 */ 864 fail_5: 865 for (i = 0; i < SIP_NRXDESC; i++) { 866 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 867 bus_dmamap_destroy(sc->sc_dmat, 868 sc->sc_rxsoft[i].rxs_dmamap); 869 } 870 fail_4: 871 for (i = 0; i < SIP_TXQUEUELEN; i++) { 872 if (sc->sc_txsoft[i].txs_dmamap != NULL) 873 bus_dmamap_destroy(sc->sc_dmat, 874 sc->sc_txsoft[i].txs_dmamap); 875 } 876 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 877 fail_3: 878 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 879 fail_2: 880 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 881 sizeof(struct sip_control_data)); 882 fail_1: 883 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 884 fail_0: 885 return; 886 } 887 888 /* 889 * sip_shutdown: 890 * 891 * Make sure the interface is stopped at reboot time. 892 */ 893 void 894 SIP_DECL(shutdown)(void *arg) 895 { 896 struct sip_softc *sc = arg; 897 898 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 899 } 900 901 /* 902 * sip_start: [ifnet interface function] 903 * 904 * Start packet transmission on the interface. 905 */ 906 void 907 SIP_DECL(start)(struct ifnet *ifp) 908 { 909 struct sip_softc *sc = ifp->if_softc; 910 struct mbuf *m0, *m; 911 struct sip_txsoft *txs; 912 bus_dmamap_t dmamap; 913 int error, firsttx, nexttx, lasttx, ofree, seg; 914 #ifdef DP83820 915 u_int32_t extsts; 916 #endif 917 918 /* 919 * If we've been told to pause, don't transmit any more packets. 920 */ 921 if (sc->sc_flags & SIPF_PAUSED) 922 ifp->if_flags |= IFF_OACTIVE; 923 924 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 925 return; 926 927 /* 928 * Remember the previous number of free descriptors and 929 * the first descriptor we'll use. 930 */ 931 ofree = sc->sc_txfree; 932 firsttx = sc->sc_txnext; 933 934 /* 935 * Loop through the send queue, setting up transmit descriptors 936 * until we drain the queue, or use up all available transmit 937 * descriptors. 938 */ 939 for (;;) { 940 /* Get a work queue entry. */ 941 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 942 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 943 break; 944 } 945 946 /* 947 * Grab a packet off the queue. 948 */ 949 IFQ_POLL(&ifp->if_snd, m0); 950 if (m0 == NULL) 951 break; 952 m = NULL; 953 954 dmamap = txs->txs_dmamap; 955 956 /* 957 * Load the DMA map. If this fails, the packet either 958 * didn't fit in the alloted number of segments, or we 959 * were short on resources. In this case, we'll copy 960 * and try again. 961 */ 962 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 963 BUS_DMA_NOWAIT) != 0) { 964 MGETHDR(m, M_DONTWAIT, MT_DATA); 965 if (m == NULL) { 966 printf("%s: unable to allocate Tx mbuf\n", 967 sc->sc_dev.dv_xname); 968 break; 969 } 970 if (m0->m_pkthdr.len > MHLEN) { 971 MCLGET(m, M_DONTWAIT); 972 if ((m->m_flags & M_EXT) == 0) { 973 printf("%s: unable to allocate Tx " 974 "cluster\n", sc->sc_dev.dv_xname); 975 m_freem(m); 976 break; 977 } 978 } 979 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 980 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 981 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 982 m, BUS_DMA_NOWAIT); 983 if (error) { 984 printf("%s: unable to load Tx buffer, " 985 "error = %d\n", sc->sc_dev.dv_xname, error); 986 break; 987 } 988 } 989 990 /* 991 * Ensure we have enough descriptors free to describe 992 * the packet. Note, we always reserve one descriptor 993 * at the end of the ring as a termination point, to 994 * prevent wrap-around. 995 */ 996 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 997 /* 998 * Not enough free descriptors to transmit this 999 * packet. We haven't committed anything yet, 1000 * so just unload the DMA map, put the packet 1001 * back on the queue, and punt. Notify the upper 1002 * layer that there are not more slots left. 1003 * 1004 * XXX We could allocate an mbuf and copy, but 1005 * XXX is it worth it? 1006 */ 1007 ifp->if_flags |= IFF_OACTIVE; 1008 bus_dmamap_unload(sc->sc_dmat, dmamap); 1009 if (m != NULL) 1010 m_freem(m); 1011 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1012 break; 1013 } 1014 1015 IFQ_DEQUEUE(&ifp->if_snd, m0); 1016 if (m != NULL) { 1017 m_freem(m0); 1018 m0 = m; 1019 } 1020 1021 /* 1022 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1023 */ 1024 1025 /* Sync the DMA map. */ 1026 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1027 BUS_DMASYNC_PREWRITE); 1028 1029 /* 1030 * Initialize the transmit descriptors. 1031 */ 1032 for (nexttx = sc->sc_txnext, seg = 0; 1033 seg < dmamap->dm_nsegs; 1034 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1035 /* 1036 * If this is the first descriptor we're 1037 * enqueueing, don't set the OWN bit just 1038 * yet. That could cause a race condition. 1039 * We'll do it below. 1040 */ 1041 sc->sc_txdescs[nexttx].sipd_bufptr = 1042 htole32(dmamap->dm_segs[seg].ds_addr); 1043 sc->sc_txdescs[nexttx].sipd_cmdsts = 1044 htole32((nexttx == firsttx ? 0 : CMDSTS_OWN) | 1045 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1046 #ifdef DP83820 1047 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1048 #endif /* DP83820 */ 1049 lasttx = nexttx; 1050 } 1051 1052 /* Clear the MORE bit on the last segment. */ 1053 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1054 1055 #ifdef DP83820 1056 /* 1057 * If VLANs are enabled and the packet has a VLAN tag, set 1058 * up the descriptor to encapsulate the packet for us. 1059 * 1060 * This apparently has to be on the last descriptor of 1061 * the packet. 1062 */ 1063 if (sc->sc_ethercom.ec_nvlans != 0 && 1064 (m = m_aux_find(m0, AF_LINK, ETHERTYPE_VLAN)) != NULL) { 1065 sc->sc_txdescs[lasttx].sipd_extsts |= 1066 htole32(EXTSTS_VPKT | 1067 htons(*mtod(m, int *) & EXTSTS_VTCI)); 1068 } 1069 1070 /* 1071 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1072 * checksumming, set up the descriptor to do this work 1073 * for us. 1074 * 1075 * This apparently has to be on the first descriptor of 1076 * the packet. 1077 * 1078 * Byte-swap constants so the compiler can optimize. 1079 */ 1080 extsts = 0; 1081 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1082 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1083 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1084 extsts |= htole32(EXTSTS_IPPKT); 1085 } 1086 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1087 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1088 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1089 extsts |= htole32(EXTSTS_TCPPKT); 1090 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1091 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1092 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1093 extsts |= htole32(EXTSTS_UDPPKT); 1094 } 1095 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1096 #endif /* DP83820 */ 1097 1098 /* Sync the descriptors we're using. */ 1099 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1100 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1101 1102 /* 1103 * Store a pointer to the packet so we can free it later, 1104 * and remember what txdirty will be once the packet is 1105 * done. 1106 */ 1107 txs->txs_mbuf = m0; 1108 txs->txs_firstdesc = sc->sc_txnext; 1109 txs->txs_lastdesc = lasttx; 1110 1111 /* Advance the tx pointer. */ 1112 sc->sc_txfree -= dmamap->dm_nsegs; 1113 sc->sc_txnext = nexttx; 1114 1115 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs, txs_q); 1116 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1117 1118 #if NBPFILTER > 0 1119 /* 1120 * Pass the packet to any BPF listeners. 1121 */ 1122 if (ifp->if_bpf) 1123 bpf_mtap(ifp->if_bpf, m0); 1124 #endif /* NBPFILTER > 0 */ 1125 } 1126 1127 if (txs == NULL || sc->sc_txfree == 0) { 1128 /* No more slots left; notify upper layer. */ 1129 ifp->if_flags |= IFF_OACTIVE; 1130 } 1131 1132 if (sc->sc_txfree != ofree) { 1133 /* 1134 * Cause a descriptor interrupt to happen on the 1135 * last packet we enqueued. 1136 */ 1137 sc->sc_txdescs[lasttx].sipd_cmdsts |= htole32(CMDSTS_INTR); 1138 SIP_CDTXSYNC(sc, lasttx, 1, 1139 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1140 1141 /* 1142 * The entire packet chain is set up. Give the 1143 * first descrptor to the chip now. 1144 */ 1145 sc->sc_txdescs[firsttx].sipd_cmdsts |= htole32(CMDSTS_OWN); 1146 SIP_CDTXSYNC(sc, firsttx, 1, 1147 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1148 1149 /* 1150 * Start the transmit process. Note, the manual says 1151 * that if there are no pending transmissions in the 1152 * chip's internal queue (indicated by TXE being clear), 1153 * then the driver software must set the TXDP to the 1154 * first descriptor to be transmitted. However, if we 1155 * do this, it causes serious performance degredation on 1156 * the DP83820 under load, not setting TXDP doesn't seem 1157 * to adversely affect the SiS 900 or DP83815. 1158 * 1159 * Well, I guess it wouldn't be the first time a manual 1160 * has lied -- and they could be speaking of the NULL- 1161 * terminated descriptor list case, rather than OWN- 1162 * terminated rings. 1163 */ 1164 #if 0 1165 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1166 CR_TXE) == 0) { 1167 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1168 SIP_CDTXADDR(sc, firsttx)); 1169 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1170 } 1171 #else 1172 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1173 #endif 1174 1175 /* Set a watchdog timer in case the chip flakes out. */ 1176 ifp->if_timer = 5; 1177 } 1178 } 1179 1180 /* 1181 * sip_watchdog: [ifnet interface function] 1182 * 1183 * Watchdog timer handler. 1184 */ 1185 void 1186 SIP_DECL(watchdog)(struct ifnet *ifp) 1187 { 1188 struct sip_softc *sc = ifp->if_softc; 1189 1190 /* 1191 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1192 * If we get a timeout, try and sweep up transmit descriptors. 1193 * If we manage to sweep them all up, ignore the lack of 1194 * interrupt. 1195 */ 1196 SIP_DECL(txintr)(sc); 1197 1198 if (sc->sc_txfree != SIP_NTXDESC) { 1199 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1200 ifp->if_oerrors++; 1201 1202 /* Reset the interface. */ 1203 (void) SIP_DECL(init)(ifp); 1204 } else if (ifp->if_flags & IFF_DEBUG) 1205 printf("%s: recovered from device timeout\n", 1206 sc->sc_dev.dv_xname); 1207 1208 /* Try to get more packets going. */ 1209 SIP_DECL(start)(ifp); 1210 } 1211 1212 /* 1213 * sip_ioctl: [ifnet interface function] 1214 * 1215 * Handle control requests from the operator. 1216 */ 1217 int 1218 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1219 { 1220 struct sip_softc *sc = ifp->if_softc; 1221 struct ifreq *ifr = (struct ifreq *)data; 1222 int s, error; 1223 1224 s = splnet(); 1225 1226 switch (cmd) { 1227 case SIOCSIFMEDIA: 1228 case SIOCGIFMEDIA: 1229 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1230 break; 1231 1232 default: 1233 error = ether_ioctl(ifp, cmd, data); 1234 if (error == ENETRESET) { 1235 /* 1236 * Multicast list has changed; set the hardware filter 1237 * accordingly. 1238 */ 1239 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1240 error = 0; 1241 } 1242 break; 1243 } 1244 1245 /* Try to get more packets going. */ 1246 SIP_DECL(start)(ifp); 1247 1248 splx(s); 1249 return (error); 1250 } 1251 1252 /* 1253 * sip_intr: 1254 * 1255 * Interrupt service routine. 1256 */ 1257 int 1258 SIP_DECL(intr)(void *arg) 1259 { 1260 struct sip_softc *sc = arg; 1261 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1262 u_int32_t isr; 1263 int handled = 0; 1264 1265 for (;;) { 1266 /* Reading clears interrupt. */ 1267 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1268 if ((isr & sc->sc_imr) == 0) 1269 break; 1270 1271 handled = 1; 1272 1273 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1274 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1275 1276 /* Grab any new packets. */ 1277 SIP_DECL(rxintr)(sc); 1278 1279 if (isr & ISR_RXORN) { 1280 printf("%s: receive FIFO overrun\n", 1281 sc->sc_dev.dv_xname); 1282 1283 /* XXX adjust rx_drain_thresh? */ 1284 } 1285 1286 if (isr & ISR_RXIDLE) { 1287 printf("%s: receive ring overrun\n", 1288 sc->sc_dev.dv_xname); 1289 1290 /* Get the receive process going again. */ 1291 bus_space_write_4(sc->sc_st, sc->sc_sh, 1292 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1293 bus_space_write_4(sc->sc_st, sc->sc_sh, 1294 SIP_CR, CR_RXE); 1295 } 1296 } 1297 1298 if (isr & (ISR_TXURN|ISR_TXDESC)) { 1299 SIP_EVCNT_INCR(&sc->sc_ev_txintr); 1300 1301 /* Sweep up transmit descriptors. */ 1302 SIP_DECL(txintr)(sc); 1303 1304 if (isr & ISR_TXURN) { 1305 u_int32_t thresh; 1306 1307 printf("%s: transmit FIFO underrun", 1308 sc->sc_dev.dv_xname); 1309 1310 thresh = sc->sc_tx_drain_thresh + 1; 1311 if (thresh <= TXCFG_DRTH && 1312 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1313 (sc->sc_tx_fill_thresh * 32))) { 1314 printf("; increasing Tx drain " 1315 "threshold to %u bytes\n", 1316 thresh * 32); 1317 sc->sc_tx_drain_thresh = thresh; 1318 (void) SIP_DECL(init)(ifp); 1319 } else { 1320 (void) SIP_DECL(init)(ifp); 1321 printf("\n"); 1322 } 1323 } 1324 } 1325 1326 #if !defined(DP83820) 1327 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1328 if (isr & ISR_PAUSE_ST) { 1329 sc->sc_flags |= SIPF_PAUSED; 1330 ifp->if_flags |= IFF_OACTIVE; 1331 } 1332 if (isr & ISR_PAUSE_END) { 1333 sc->sc_flags &= ~SIPF_PAUSED; 1334 ifp->if_flags &= ~IFF_OACTIVE; 1335 } 1336 } 1337 #endif /* ! DP83820 */ 1338 1339 if (isr & ISR_HIBERR) { 1340 #define PRINTERR(bit, str) \ 1341 if (isr & (bit)) \ 1342 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1343 PRINTERR(ISR_DPERR, "parity error"); 1344 PRINTERR(ISR_SSERR, "system error"); 1345 PRINTERR(ISR_RMABT, "master abort"); 1346 PRINTERR(ISR_RTABT, "target abort"); 1347 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1348 (void) SIP_DECL(init)(ifp); 1349 #undef PRINTERR 1350 } 1351 } 1352 1353 /* Try to get more packets going. */ 1354 SIP_DECL(start)(ifp); 1355 1356 return (handled); 1357 } 1358 1359 /* 1360 * sip_txintr: 1361 * 1362 * Helper; handle transmit interrupts. 1363 */ 1364 void 1365 SIP_DECL(txintr)(struct sip_softc *sc) 1366 { 1367 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1368 struct sip_txsoft *txs; 1369 u_int32_t cmdsts; 1370 1371 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1372 ifp->if_flags &= ~IFF_OACTIVE; 1373 1374 /* 1375 * Go through our Tx list and free mbufs for those 1376 * frames which have been transmitted. 1377 */ 1378 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1379 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1380 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1381 1382 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1383 if (cmdsts & CMDSTS_OWN) 1384 break; 1385 1386 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1387 1388 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1389 1390 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1391 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1392 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1393 m_freem(txs->txs_mbuf); 1394 txs->txs_mbuf = NULL; 1395 1396 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1397 1398 /* 1399 * Check for errors and collisions. 1400 */ 1401 if (cmdsts & 1402 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1403 if (ifp->if_flags & IFF_DEBUG) { 1404 if (CMDSTS_Tx_ED) 1405 printf("%s: excessive deferral\n", 1406 sc->sc_dev.dv_xname); 1407 if (CMDSTS_Tx_EC) { 1408 printf("%s: excessive collisions\n", 1409 sc->sc_dev.dv_xname); 1410 ifp->if_collisions += 16; 1411 } 1412 } 1413 } else { 1414 /* Packet was transmitted successfully. */ 1415 ifp->if_opackets++; 1416 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1417 } 1418 } 1419 1420 /* 1421 * If there are no more pending transmissions, cancel the watchdog 1422 * timer. 1423 */ 1424 if (txs == NULL) 1425 ifp->if_timer = 0; 1426 } 1427 1428 /* 1429 * sip_rxintr: 1430 * 1431 * Helper; handle receive interrupts. 1432 */ 1433 void 1434 SIP_DECL(rxintr)(struct sip_softc *sc) 1435 { 1436 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1437 struct sip_rxsoft *rxs; 1438 struct mbuf *m; 1439 u_int32_t cmdsts; 1440 #ifdef DP83820 1441 u_int32_t extsts; 1442 #endif /* DP83820 */ 1443 int i, len; 1444 1445 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1446 rxs = &sc->sc_rxsoft[i]; 1447 1448 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1449 1450 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1451 #ifdef DP83820 1452 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1453 #endif /* DP83820 */ 1454 1455 /* 1456 * NOTE: OWN is set if owned by _consumer_. We're the 1457 * consumer of the receive ring, so if the bit is clear, 1458 * we have processed all of the packets. 1459 */ 1460 if ((cmdsts & CMDSTS_OWN) == 0) { 1461 /* 1462 * We have processed all of the receive buffers. 1463 */ 1464 break; 1465 } 1466 1467 #if !defined(DP83820) 1468 /* 1469 * If any collisions were seen on the wire, count one. 1470 */ 1471 if (cmdsts & CMDSTS_Rx_COL) 1472 ifp->if_collisions++; 1473 #endif /* ! DP83820 */ 1474 1475 /* 1476 * If an error occurred, update stats, clear the status 1477 * word, and leave the packet buffer in place. It will 1478 * simply be reused the next time the ring comes around. 1479 */ 1480 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_LONG|CMDSTS_Rx_RUNT| 1481 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1482 ifp->if_ierrors++; 1483 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1484 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1485 /* Receive overrun handled elsewhere. */ 1486 printf("%s: receive descriptor error\n", 1487 sc->sc_dev.dv_xname); 1488 } 1489 #define PRINTERR(bit, str) \ 1490 if (cmdsts & (bit)) \ 1491 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1492 PRINTERR(CMDSTS_Rx_LONG, "packet too long"); 1493 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1494 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1495 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1496 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1497 #undef PRINTERR 1498 SIP_INIT_RXDESC(sc, i); 1499 continue; 1500 } 1501 1502 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1503 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1504 1505 /* 1506 * No errors; receive the packet. Note, the SiS 900 1507 * includes the CRC with every packet. 1508 */ 1509 len = CMDSTS_SIZE(cmdsts); 1510 1511 #ifdef __NO_STRICT_ALIGNMENT 1512 /* 1513 * If the packet is small enough to fit in a 1514 * single header mbuf, allocate one and copy 1515 * the data into it. This greatly reduces 1516 * memory consumption when we receive lots 1517 * of small packets. 1518 * 1519 * Otherwise, we add a new buffer to the receive 1520 * chain. If this fails, we drop the packet and 1521 * recycle the old buffer. 1522 */ 1523 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 1524 MGETHDR(m, M_DONTWAIT, MT_DATA); 1525 if (m == NULL) 1526 goto dropit; 1527 memcpy(mtod(m, caddr_t), 1528 mtod(rxs->rxs_mbuf, caddr_t), len); 1529 SIP_INIT_RXDESC(sc, i); 1530 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1531 rxs->rxs_dmamap->dm_mapsize, 1532 BUS_DMASYNC_PREREAD); 1533 } else { 1534 m = rxs->rxs_mbuf; 1535 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1536 dropit: 1537 ifp->if_ierrors++; 1538 SIP_INIT_RXDESC(sc, i); 1539 bus_dmamap_sync(sc->sc_dmat, 1540 rxs->rxs_dmamap, 0, 1541 rxs->rxs_dmamap->dm_mapsize, 1542 BUS_DMASYNC_PREREAD); 1543 continue; 1544 } 1545 } 1546 #else 1547 /* 1548 * The SiS 900's receive buffers must be 4-byte aligned. 1549 * But this means that the data after the Ethernet header 1550 * is misaligned. We must allocate a new buffer and 1551 * copy the data, shifted forward 2 bytes. 1552 */ 1553 MGETHDR(m, M_DONTWAIT, MT_DATA); 1554 if (m == NULL) { 1555 dropit: 1556 ifp->if_ierrors++; 1557 SIP_INIT_RXDESC(sc, i); 1558 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1559 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1560 continue; 1561 } 1562 if (len > (MHLEN - 2)) { 1563 MCLGET(m, M_DONTWAIT); 1564 if ((m->m_flags & M_EXT) == 0) { 1565 m_freem(m); 1566 goto dropit; 1567 } 1568 } 1569 m->m_data += 2; 1570 1571 /* 1572 * Note that we use clusters for incoming frames, so the 1573 * buffer is virtually contiguous. 1574 */ 1575 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 1576 1577 /* Allow the receive descriptor to continue using its mbuf. */ 1578 SIP_INIT_RXDESC(sc, i); 1579 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1580 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1581 #endif /* __NO_STRICT_ALIGNMENT */ 1582 1583 ifp->if_ipackets++; 1584 m->m_flags |= M_HASFCS; 1585 m->m_pkthdr.rcvif = ifp; 1586 m->m_pkthdr.len = m->m_len = len; 1587 1588 #if NBPFILTER > 0 1589 /* 1590 * Pass this up to any BPF listeners, but only 1591 * pass if up the stack if it's for us. 1592 */ 1593 if (ifp->if_bpf) 1594 bpf_mtap(ifp->if_bpf, m); 1595 #endif /* NBPFILTER > 0 */ 1596 1597 #ifdef DP83820 1598 /* 1599 * If VLANs are enabled, VLAN packets have been unwrapped 1600 * for us. Associate the tag with the packet. 1601 */ 1602 if (sc->sc_ethercom.ec_nvlans != 0 && 1603 (extsts & EXTSTS_VPKT) != 0) { 1604 struct mbuf *vtag; 1605 1606 vtag = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 1607 if (vtag == NULL) { 1608 printf("%s: unable to allocate VLAN tag\n", 1609 sc->sc_dev.dv_xname); 1610 m_freem(m); 1611 continue; 1612 } 1613 1614 *mtod(vtag, int *) = ntohs(extsts & EXTSTS_VTCI); 1615 vtag->m_len = sizeof(int); 1616 } 1617 1618 /* 1619 * Set the incoming checksum information for the 1620 * packet. 1621 */ 1622 if ((extsts & EXTSTS_IPPKT) != 0) { 1623 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1624 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1625 if (extsts & EXTSTS_Rx_IPERR) 1626 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1627 if (extsts & EXTSTS_TCPPKT) { 1628 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1629 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1630 if (extsts & EXTSTS_Rx_TCPERR) 1631 m->m_pkthdr.csum_flags |= 1632 M_CSUM_TCP_UDP_BAD; 1633 } else if (extsts & EXTSTS_UDPPKT) { 1634 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1635 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1636 if (extsts & EXTSTS_Rx_UDPERR) 1637 m->m_pkthdr.csum_flags |= 1638 M_CSUM_TCP_UDP_BAD; 1639 } 1640 } 1641 #endif /* DP83820 */ 1642 1643 /* Pass it on. */ 1644 (*ifp->if_input)(ifp, m); 1645 } 1646 1647 /* Update the receive pointer. */ 1648 sc->sc_rxptr = i; 1649 } 1650 1651 /* 1652 * sip_tick: 1653 * 1654 * One second timer, used to tick the MII. 1655 */ 1656 void 1657 SIP_DECL(tick)(void *arg) 1658 { 1659 struct sip_softc *sc = arg; 1660 int s; 1661 1662 s = splnet(); 1663 mii_tick(&sc->sc_mii); 1664 splx(s); 1665 1666 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 1667 } 1668 1669 /* 1670 * sip_reset: 1671 * 1672 * Perform a soft reset on the SiS 900. 1673 */ 1674 void 1675 SIP_DECL(reset)(struct sip_softc *sc) 1676 { 1677 bus_space_tag_t st = sc->sc_st; 1678 bus_space_handle_t sh = sc->sc_sh; 1679 int i; 1680 1681 bus_space_write_4(st, sh, SIP_CR, CR_RST); 1682 1683 for (i = 0; i < SIP_TIMEOUT; i++) { 1684 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 1685 break; 1686 delay(2); 1687 } 1688 1689 if (i == SIP_TIMEOUT) 1690 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1691 1692 delay(1000); 1693 1694 #ifdef DP83820 1695 /* 1696 * Set the general purpose I/O bits. Do it here in case we 1697 * need to have GPIO set up to talk to the media interface. 1698 */ 1699 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 1700 delay(1000); 1701 #endif /* DP83820 */ 1702 } 1703 1704 /* 1705 * sip_init: [ ifnet interface function ] 1706 * 1707 * Initialize the interface. Must be called at splnet(). 1708 */ 1709 int 1710 SIP_DECL(init)(struct ifnet *ifp) 1711 { 1712 struct sip_softc *sc = ifp->if_softc; 1713 bus_space_tag_t st = sc->sc_st; 1714 bus_space_handle_t sh = sc->sc_sh; 1715 struct sip_txsoft *txs; 1716 struct sip_rxsoft *rxs; 1717 struct sip_desc *sipd; 1718 u_int32_t reg; 1719 int i, error = 0; 1720 1721 /* 1722 * Cancel any pending I/O. 1723 */ 1724 SIP_DECL(stop)(ifp, 0); 1725 1726 /* 1727 * Reset the chip to a known state. 1728 */ 1729 SIP_DECL(reset)(sc); 1730 1731 #if !defined(DP83820) 1732 if (sc->sc_model->sip_vendor == PCI_VENDOR_NS && 1733 sc->sc_model->sip_product == PCI_PRODUCT_NS_DP83815) { 1734 /* 1735 * DP83815 manual, page 78: 1736 * 4.4 Recommended Registers Configuration 1737 * For optimum performance of the DP83815, version noted 1738 * as DP83815CVNG (SRR = 203h), the listed register 1739 * modifications must be followed in sequence... 1740 * 1741 * It's not clear if this should be 302h or 203h because that 1742 * chip name is listed as SRR 302h in the description of the 1743 * SRR register. However, my revision 302h DP83815 on the 1744 * Netgear FA311 purchased in 02/2001 needs these settings 1745 * to avoid tons of errors in AcceptPerfectMatch (non- 1746 * IFF_PROMISC) mode. I do not know if other revisions need 1747 * this set or not. [briggs -- 09 March 2001] 1748 * 1749 * Note that only the low-order 12 bits of 0xe4 are documented 1750 * and that this sets reserved bits in that register. 1751 */ 1752 reg = bus_space_read_4(st, sh, SIP_NS_SRR); 1753 if (reg == 0x302) { 1754 bus_space_write_4(st, sh, 0x00cc, 0x0001); 1755 bus_space_write_4(st, sh, 0x00e4, 0x189C); 1756 bus_space_write_4(st, sh, 0x00fc, 0x0000); 1757 bus_space_write_4(st, sh, 0x00f4, 0x5040); 1758 bus_space_write_4(st, sh, 0x00f8, 0x008c); 1759 } 1760 } 1761 #endif /* ! DP83820 */ 1762 1763 /* 1764 * Initialize the transmit descriptor ring. 1765 */ 1766 for (i = 0; i < SIP_NTXDESC; i++) { 1767 sipd = &sc->sc_txdescs[i]; 1768 memset(sipd, 0, sizeof(struct sip_desc)); 1769 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 1770 } 1771 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 1772 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1773 sc->sc_txfree = SIP_NTXDESC; 1774 sc->sc_txnext = 0; 1775 1776 /* 1777 * Initialize the transmit job descriptors. 1778 */ 1779 SIMPLEQ_INIT(&sc->sc_txfreeq); 1780 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1781 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1782 txs = &sc->sc_txsoft[i]; 1783 txs->txs_mbuf = NULL; 1784 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1785 } 1786 1787 /* 1788 * Initialize the receive descriptor and receive job 1789 * descriptor rings. 1790 */ 1791 for (i = 0; i < SIP_NRXDESC; i++) { 1792 rxs = &sc->sc_rxsoft[i]; 1793 if (rxs->rxs_mbuf == NULL) { 1794 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 1795 printf("%s: unable to allocate or map rx " 1796 "buffer %d, error = %d\n", 1797 sc->sc_dev.dv_xname, i, error); 1798 /* 1799 * XXX Should attempt to run with fewer receive 1800 * XXX buffers instead of just failing. 1801 */ 1802 SIP_DECL(rxdrain)(sc); 1803 goto out; 1804 } 1805 } 1806 } 1807 sc->sc_rxptr = 0; 1808 1809 /* 1810 * Set the configuration register; it's already initialized 1811 * in sip_attach(). 1812 */ 1813 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 1814 1815 /* 1816 * Initialize the transmit fill and drain thresholds if 1817 * we have never done so. 1818 */ 1819 if (sc->sc_tx_fill_thresh == 0) { 1820 /* 1821 * XXX This value should be tuned. This is the 1822 * minimum (32 bytes), and we may be able to 1823 * improve performance by increasing it. 1824 */ 1825 sc->sc_tx_fill_thresh = 1; 1826 } 1827 if (sc->sc_tx_drain_thresh == 0) { 1828 /* 1829 * Start at a drain threshold of 512 bytes. We will 1830 * increase it if a DMA underrun occurs. 1831 * 1832 * XXX The minimum value of this variable should be 1833 * tuned. We may be able to improve performance 1834 * by starting with a lower value. That, however, 1835 * may trash the first few outgoing packets if the 1836 * PCI bus is saturated. 1837 */ 1838 sc->sc_tx_drain_thresh = 512 / 32; 1839 } 1840 1841 /* 1842 * Initialize the prototype TXCFG register. 1843 */ 1844 sc->sc_txcfg = TXCFG_ATP | TXCFG_MXDMA_512 | 1845 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 1846 sc->sc_tx_drain_thresh; 1847 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 1848 1849 /* 1850 * Initialize the receive drain threshold if we have never 1851 * done so. 1852 */ 1853 if (sc->sc_rx_drain_thresh == 0) { 1854 /* 1855 * XXX This value should be tuned. This is set to the 1856 * maximum of 248 bytes, and we may be able to improve 1857 * performance by decreasing it (although we should never 1858 * set this value lower than 2; 14 bytes are required to 1859 * filter the packet). 1860 */ 1861 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 1862 } 1863 1864 /* 1865 * Initialize the prototype RXCFG register. 1866 */ 1867 sc->sc_rxcfg = RXCFG_MXDMA_512 | 1868 (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 1869 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 1870 1871 /* Set up the receive filter. */ 1872 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1873 1874 #ifdef DP83820 1875 /* 1876 * Initialize the VLAN/IP receive control register. 1877 * We enable checksum computation on all incoming 1878 * packets, and do not reject packets w/ bad checksums. 1879 */ 1880 reg = 0; 1881 if (ifp->if_capenable & 1882 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1883 reg |= VRCR_IPEN; 1884 if (sc->sc_ethercom.ec_nvlans != 0) 1885 reg |= VRCR_VTDEN|VRCR_VTREN; 1886 bus_space_write_4(st, sh, SIP_VRCR, reg); 1887 1888 /* 1889 * Initialize the VLAN/IP transmit control register. 1890 * We enable outgoing checksum computation on a 1891 * per-packet basis. 1892 */ 1893 reg = 0; 1894 if (ifp->if_capenable & 1895 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1896 reg |= VTCR_PPCHK; 1897 if (sc->sc_ethercom.ec_nvlans != 0) 1898 reg |= VTCR_VPPTI; 1899 bus_space_write_4(st, sh, SIP_VTCR, reg); 1900 1901 /* 1902 * If we're using VLANs, initialize the VLAN data register. 1903 * To understand why we bswap the VLAN Ethertype, see section 1904 * 4.2.36 of the DP83820 manual. 1905 */ 1906 if (sc->sc_ethercom.ec_nvlans != 0) 1907 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 1908 #endif /* DP83820 */ 1909 1910 /* 1911 * Give the transmit and receive rings to the chip. 1912 */ 1913 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 1914 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1915 1916 /* 1917 * Initialize the interrupt mask. 1918 */ 1919 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 1920 ISR_TXURN|ISR_TXDESC|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 1921 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 1922 1923 /* 1924 * Set the current media. Do this after initializing the prototype 1925 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 1926 * control. 1927 */ 1928 mii_mediachg(&sc->sc_mii); 1929 1930 /* 1931 * Enable interrupts. 1932 */ 1933 bus_space_write_4(st, sh, SIP_IER, IER_IE); 1934 1935 /* 1936 * Start the transmit and receive processes. 1937 */ 1938 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 1939 1940 /* 1941 * Start the one second MII clock. 1942 */ 1943 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 1944 1945 /* 1946 * ...all done! 1947 */ 1948 ifp->if_flags |= IFF_RUNNING; 1949 ifp->if_flags &= ~IFF_OACTIVE; 1950 1951 out: 1952 if (error) 1953 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1954 return (error); 1955 } 1956 1957 /* 1958 * sip_drain: 1959 * 1960 * Drain the receive queue. 1961 */ 1962 void 1963 SIP_DECL(rxdrain)(struct sip_softc *sc) 1964 { 1965 struct sip_rxsoft *rxs; 1966 int i; 1967 1968 for (i = 0; i < SIP_NRXDESC; i++) { 1969 rxs = &sc->sc_rxsoft[i]; 1970 if (rxs->rxs_mbuf != NULL) { 1971 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1972 m_freem(rxs->rxs_mbuf); 1973 rxs->rxs_mbuf = NULL; 1974 } 1975 } 1976 } 1977 1978 /* 1979 * sip_stop: [ ifnet interface function ] 1980 * 1981 * Stop transmission on the interface. 1982 */ 1983 void 1984 SIP_DECL(stop)(struct ifnet *ifp, int disable) 1985 { 1986 struct sip_softc *sc = ifp->if_softc; 1987 bus_space_tag_t st = sc->sc_st; 1988 bus_space_handle_t sh = sc->sc_sh; 1989 struct sip_txsoft *txs; 1990 u_int32_t cmdsts = 0; /* DEBUG */ 1991 1992 /* 1993 * Stop the one second clock. 1994 */ 1995 callout_stop(&sc->sc_tick_ch); 1996 1997 /* Down the MII. */ 1998 mii_down(&sc->sc_mii); 1999 2000 /* 2001 * Disable interrupts. 2002 */ 2003 bus_space_write_4(st, sh, SIP_IER, 0); 2004 2005 /* 2006 * Stop receiver and transmitter. 2007 */ 2008 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2009 2010 /* 2011 * Release any queued transmit buffers. 2012 */ 2013 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2014 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2015 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2016 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2017 CMDSTS_INTR) == 0) 2018 printf("%s: sip_stop: last descriptor does not " 2019 "have INTR bit set\n", sc->sc_dev.dv_xname); 2020 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 2021 #ifdef DIAGNOSTIC 2022 if (txs->txs_mbuf == NULL) { 2023 printf("%s: dirty txsoft with no mbuf chain\n", 2024 sc->sc_dev.dv_xname); 2025 panic("sip_stop"); 2026 } 2027 #endif 2028 cmdsts |= /* DEBUG */ 2029 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2030 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2031 m_freem(txs->txs_mbuf); 2032 txs->txs_mbuf = NULL; 2033 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2034 } 2035 2036 if (disable) 2037 SIP_DECL(rxdrain)(sc); 2038 2039 /* 2040 * Mark the interface down and cancel the watchdog timer. 2041 */ 2042 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2043 ifp->if_timer = 0; 2044 2045 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2046 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2047 printf("%s: sip_stop: no INTR bits set in dirty tx " 2048 "descriptors\n", sc->sc_dev.dv_xname); 2049 } 2050 2051 /* 2052 * sip_read_eeprom: 2053 * 2054 * Read data from the serial EEPROM. 2055 */ 2056 void 2057 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2058 u_int16_t *data) 2059 { 2060 bus_space_tag_t st = sc->sc_st; 2061 bus_space_handle_t sh = sc->sc_sh; 2062 u_int16_t reg; 2063 int i, x; 2064 2065 for (i = 0; i < wordcnt; i++) { 2066 /* Send CHIP SELECT. */ 2067 reg = EROMAR_EECS; 2068 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2069 2070 /* Shift in the READ opcode. */ 2071 for (x = 3; x > 0; x--) { 2072 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2073 reg |= EROMAR_EEDI; 2074 else 2075 reg &= ~EROMAR_EEDI; 2076 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2077 bus_space_write_4(st, sh, SIP_EROMAR, 2078 reg | EROMAR_EESK); 2079 delay(4); 2080 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2081 delay(4); 2082 } 2083 2084 /* Shift in address. */ 2085 for (x = 6; x > 0; x--) { 2086 if ((word + i) & (1 << (x - 1))) 2087 reg |= EROMAR_EEDI; 2088 else 2089 reg &= ~EROMAR_EEDI; 2090 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2091 bus_space_write_4(st, sh, SIP_EROMAR, 2092 reg | EROMAR_EESK); 2093 delay(4); 2094 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2095 delay(4); 2096 } 2097 2098 /* Shift out data. */ 2099 reg = EROMAR_EECS; 2100 data[i] = 0; 2101 for (x = 16; x > 0; x--) { 2102 bus_space_write_4(st, sh, SIP_EROMAR, 2103 reg | EROMAR_EESK); 2104 delay(4); 2105 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2106 data[i] |= (1 << (x - 1)); 2107 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2108 delay(4); 2109 } 2110 2111 /* Clear CHIP SELECT. */ 2112 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2113 delay(4); 2114 } 2115 } 2116 2117 /* 2118 * sip_add_rxbuf: 2119 * 2120 * Add a receive buffer to the indicated descriptor. 2121 */ 2122 int 2123 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2124 { 2125 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2126 struct mbuf *m; 2127 int error; 2128 2129 MGETHDR(m, M_DONTWAIT, MT_DATA); 2130 if (m == NULL) 2131 return (ENOBUFS); 2132 2133 MCLGET(m, M_DONTWAIT); 2134 if ((m->m_flags & M_EXT) == 0) { 2135 m_freem(m); 2136 return (ENOBUFS); 2137 } 2138 2139 if (rxs->rxs_mbuf != NULL) 2140 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2141 2142 rxs->rxs_mbuf = m; 2143 2144 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2145 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 2146 if (error) { 2147 printf("%s: can't load rx DMA map %d, error = %d\n", 2148 sc->sc_dev.dv_xname, idx, error); 2149 panic("sip_add_rxbuf"); /* XXX */ 2150 } 2151 2152 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2153 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2154 2155 SIP_INIT_RXDESC(sc, idx); 2156 2157 return (0); 2158 } 2159 2160 #if !defined(DP83820) 2161 /* 2162 * sip_sis900_set_filter: 2163 * 2164 * Set up the receive filter. 2165 */ 2166 void 2167 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2168 { 2169 bus_space_tag_t st = sc->sc_st; 2170 bus_space_handle_t sh = sc->sc_sh; 2171 struct ethercom *ec = &sc->sc_ethercom; 2172 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2173 struct ether_multi *enm; 2174 u_int8_t *cp; 2175 struct ether_multistep step; 2176 u_int32_t crc, mchash[8]; 2177 2178 /* 2179 * Initialize the prototype RFCR. 2180 */ 2181 sc->sc_rfcr = RFCR_RFEN; 2182 if (ifp->if_flags & IFF_BROADCAST) 2183 sc->sc_rfcr |= RFCR_AAB; 2184 if (ifp->if_flags & IFF_PROMISC) { 2185 sc->sc_rfcr |= RFCR_AAP; 2186 goto allmulti; 2187 } 2188 2189 /* 2190 * Set up the multicast address filter by passing all multicast 2191 * addresses through a CRC generator, and then using the high-order 2192 * 6 bits as an index into the 128 bit multicast hash table (only 2193 * the lower 16 bits of each 32 bit multicast hash register are 2194 * valid). The high order bits select the register, while the 2195 * rest of the bits select the bit within the register. 2196 */ 2197 2198 memset(mchash, 0, sizeof(mchash)); 2199 2200 ETHER_FIRST_MULTI(step, ec, enm); 2201 while (enm != NULL) { 2202 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2203 /* 2204 * We must listen to a range of multicast addresses. 2205 * For now, just accept all multicasts, rather than 2206 * trying to set only those filter bits needed to match 2207 * the range. (At this time, the only use of address 2208 * ranges is for IP multicast routing, for which the 2209 * range is big enough to require all bits set.) 2210 */ 2211 goto allmulti; 2212 } 2213 2214 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2215 2216 /* Just want the 7 most significant bits. */ 2217 crc >>= 25; 2218 2219 /* Set the corresponding bit in the hash table. */ 2220 mchash[crc >> 4] |= 1 << (crc & 0xf); 2221 2222 ETHER_NEXT_MULTI(step, enm); 2223 } 2224 2225 ifp->if_flags &= ~IFF_ALLMULTI; 2226 goto setit; 2227 2228 allmulti: 2229 ifp->if_flags |= IFF_ALLMULTI; 2230 sc->sc_rfcr |= RFCR_AAM; 2231 2232 setit: 2233 #define FILTER_EMIT(addr, data) \ 2234 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2235 delay(1); \ 2236 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2237 delay(1) 2238 2239 /* 2240 * Disable receive filter, and program the node address. 2241 */ 2242 cp = LLADDR(ifp->if_sadl); 2243 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2244 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2245 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2246 2247 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2248 /* 2249 * Program the multicast hash table. 2250 */ 2251 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2252 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2253 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2254 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2255 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2256 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2257 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2258 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2259 } 2260 #undef FILTER_EMIT 2261 2262 /* 2263 * Re-enable the receiver filter. 2264 */ 2265 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2266 } 2267 #endif /* ! DP83820 */ 2268 2269 /* 2270 * sip_dp83815_set_filter: 2271 * 2272 * Set up the receive filter. 2273 */ 2274 void 2275 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2276 { 2277 bus_space_tag_t st = sc->sc_st; 2278 bus_space_handle_t sh = sc->sc_sh; 2279 struct ethercom *ec = &sc->sc_ethercom; 2280 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2281 struct ether_multi *enm; 2282 u_int8_t *cp; 2283 struct ether_multistep step; 2284 u_int32_t crc, hash, slot, bit; 2285 #ifdef DP83820 2286 #define MCHASH_NWORDS 128 2287 #else 2288 #define MCHASH_NWORDS 32 2289 #endif /* DP83820 */ 2290 u_int16_t mchash[MCHASH_NWORDS]; 2291 int i; 2292 2293 /* 2294 * Initialize the prototype RFCR. 2295 * Enable the receive filter, and accept on 2296 * Perfect (destination address) Match 2297 * If IFF_BROADCAST, also accept all broadcast packets. 2298 * If IFF_PROMISC, accept all unicast packets (and later, set 2299 * IFF_ALLMULTI and accept all multicast, too). 2300 */ 2301 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2302 if (ifp->if_flags & IFF_BROADCAST) 2303 sc->sc_rfcr |= RFCR_AAB; 2304 if (ifp->if_flags & IFF_PROMISC) { 2305 sc->sc_rfcr |= RFCR_AAP; 2306 goto allmulti; 2307 } 2308 2309 #ifdef DP83820 2310 /* 2311 * Set up the DP83820 multicast address filter by passing all multicast 2312 * addresses through a CRC generator, and then using the high-order 2313 * 11 bits as an index into the 2048 bit multicast hash table. The 2314 * high-order 7 bits select the slot, while the low-order 4 bits 2315 * select the bit within the slot. Note that only the low 16-bits 2316 * of each filter word are used, and there are 128 filter words. 2317 */ 2318 #else 2319 /* 2320 * Set up the DP83815 multicast address filter by passing all multicast 2321 * addresses through a CRC generator, and then using the high-order 2322 * 9 bits as an index into the 512 bit multicast hash table. The 2323 * high-order 5 bits select the slot, while the low-order 4 bits 2324 * select the bit within the slot. Note that only the low 16-bits 2325 * of each filter word are used, and there are 32 filter words. 2326 */ 2327 #endif /* DP83820 */ 2328 2329 memset(mchash, 0, sizeof(mchash)); 2330 2331 ifp->if_flags &= ~IFF_ALLMULTI; 2332 ETHER_FIRST_MULTI(step, ec, enm); 2333 if (enm != NULL) { 2334 while (enm != NULL) { 2335 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2336 ETHER_ADDR_LEN)) { 2337 /* 2338 * We must listen to a range of multicast addresses. 2339 * For now, just accept all multicasts, rather than 2340 * trying to set only those filter bits needed to match 2341 * the range. (At this time, the only use of address 2342 * ranges is for IP multicast routing, for which the 2343 * range is big enough to require all bits set.) 2344 */ 2345 goto allmulti; 2346 } 2347 2348 #ifdef DP83820 2349 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2350 2351 /* Just want the 11 most significant bits. */ 2352 hash = crc >> 21; 2353 #else 2354 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2355 2356 /* Just want the 9 most significant bits. */ 2357 hash = crc >> 23; 2358 #endif /* DP83820 */ 2359 slot = hash >> 4; 2360 bit = hash & 0xf; 2361 2362 /* Set the corresponding bit in the hash table. */ 2363 mchash[slot] |= 1 << bit; 2364 2365 ETHER_NEXT_MULTI(step, enm); 2366 } 2367 2368 sc->sc_rfcr |= RFCR_MHEN; 2369 } 2370 goto setit; 2371 2372 allmulti: 2373 ifp->if_flags |= IFF_ALLMULTI; 2374 sc->sc_rfcr |= RFCR_AAM; 2375 2376 setit: 2377 #define FILTER_EMIT(addr, data) \ 2378 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2379 delay(1); \ 2380 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2381 delay(1); 2382 2383 /* 2384 * Disable receive filter, and program the node address. 2385 */ 2386 cp = LLADDR(ifp->if_sadl); 2387 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 2388 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 2389 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 2390 2391 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2392 /* 2393 * Program the multicast hash table. 2394 */ 2395 for (i = 0; i < MCHASH_NWORDS; i++) 2396 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 2397 mchash[i]); 2398 } 2399 #undef FILTER_EMIT 2400 #undef MCHASH_NWORDS 2401 2402 /* 2403 * Re-enable the receiver filter. 2404 */ 2405 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2406 } 2407 2408 #if defined(DP83820) 2409 /* 2410 * sip_dp83820_mii_readreg: [mii interface function] 2411 * 2412 * Read a PHY register on the MII of the DP83820. 2413 */ 2414 int 2415 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 2416 { 2417 2418 return (mii_bitbang_readreg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2419 phy, reg)); 2420 } 2421 2422 /* 2423 * sip_dp83820_mii_writereg: [mii interface function] 2424 * 2425 * Write a PHY register on the MII of the DP83820. 2426 */ 2427 void 2428 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 2429 { 2430 2431 mii_bitbang_writereg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2432 phy, reg, val); 2433 } 2434 2435 /* 2436 * sip_dp83815_mii_statchg: [mii interface function] 2437 * 2438 * Callback from MII layer when media changes. 2439 */ 2440 void 2441 SIP_DECL(dp83820_mii_statchg)(struct device *self) 2442 { 2443 struct sip_softc *sc = (struct sip_softc *) self; 2444 u_int32_t cfg; 2445 2446 /* 2447 * Update TXCFG for full-duplex operation. 2448 */ 2449 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2450 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2451 else 2452 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2453 2454 /* 2455 * Update RXCFG for full-duplex or loopback. 2456 */ 2457 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2458 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2459 sc->sc_rxcfg |= RXCFG_ATX; 2460 else 2461 sc->sc_rxcfg &= ~RXCFG_ATX; 2462 2463 /* 2464 * Update CFG for MII/GMII. 2465 */ 2466 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2467 cfg = sc->sc_cfg | CFG_MODE_1000; 2468 else 2469 cfg = sc->sc_cfg; 2470 2471 /* 2472 * XXX 802.3x flow control. 2473 */ 2474 2475 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 2476 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2477 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2478 } 2479 2480 /* 2481 * sip_dp83820_mii_bitbang_read: [mii bit-bang interface function] 2482 * 2483 * Read the MII serial port for the MII bit-bang module. 2484 */ 2485 u_int32_t 2486 SIP_DECL(dp83820_mii_bitbang_read)(struct device *self) 2487 { 2488 struct sip_softc *sc = (void *) self; 2489 2490 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 2491 } 2492 2493 /* 2494 * sip_dp83820_mii_bitbang_write: [mii big-bang interface function] 2495 * 2496 * Write the MII serial port for the MII bit-bang module. 2497 */ 2498 void 2499 SIP_DECL(dp83820_mii_bitbang_write)(struct device *self, u_int32_t val) 2500 { 2501 struct sip_softc *sc = (void *) self; 2502 2503 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 2504 } 2505 #else /* ! DP83820 */ 2506 /* 2507 * sip_sis900_mii_readreg: [mii interface function] 2508 * 2509 * Read a PHY register on the MII. 2510 */ 2511 int 2512 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 2513 { 2514 struct sip_softc *sc = (struct sip_softc *) self; 2515 u_int32_t enphy; 2516 2517 /* 2518 * The SiS 900 has only an internal PHY on the MII. Only allow 2519 * MII address 0. 2520 */ 2521 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 2522 return (0); 2523 2524 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2525 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 2526 ENPHY_RWCMD | ENPHY_ACCESS); 2527 do { 2528 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2529 } while (enphy & ENPHY_ACCESS); 2530 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 2531 } 2532 2533 /* 2534 * sip_sis900_mii_writereg: [mii interface function] 2535 * 2536 * Write a PHY register on the MII. 2537 */ 2538 void 2539 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 2540 { 2541 struct sip_softc *sc = (struct sip_softc *) self; 2542 u_int32_t enphy; 2543 2544 /* 2545 * The SiS 900 has only an internal PHY on the MII. Only allow 2546 * MII address 0. 2547 */ 2548 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 2549 return; 2550 2551 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2552 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 2553 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 2554 do { 2555 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2556 } while (enphy & ENPHY_ACCESS); 2557 } 2558 2559 /* 2560 * sip_sis900_mii_statchg: [mii interface function] 2561 * 2562 * Callback from MII layer when media changes. 2563 */ 2564 void 2565 SIP_DECL(sis900_mii_statchg)(struct device *self) 2566 { 2567 struct sip_softc *sc = (struct sip_softc *) self; 2568 u_int32_t flowctl; 2569 2570 /* 2571 * Update TXCFG for full-duplex operation. 2572 */ 2573 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2574 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2575 else 2576 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2577 2578 /* 2579 * Update RXCFG for full-duplex or loopback. 2580 */ 2581 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2582 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2583 sc->sc_rxcfg |= RXCFG_ATX; 2584 else 2585 sc->sc_rxcfg &= ~RXCFG_ATX; 2586 2587 /* 2588 * Update IMR for use of 802.3x flow control. 2589 */ 2590 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 2591 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 2592 flowctl = FLOWCTL_FLOWEN; 2593 } else { 2594 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 2595 flowctl = 0; 2596 } 2597 2598 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2599 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2600 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 2601 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 2602 } 2603 2604 /* 2605 * sip_dp83815_mii_readreg: [mii interface function] 2606 * 2607 * Read a PHY register on the MII. 2608 */ 2609 int 2610 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 2611 { 2612 struct sip_softc *sc = (struct sip_softc *) self; 2613 u_int32_t val; 2614 2615 /* 2616 * The DP83815 only has an internal PHY. Only allow 2617 * MII address 0. 2618 */ 2619 if (phy != 0) 2620 return (0); 2621 2622 /* 2623 * Apparently, after a reset, the DP83815 can take a while 2624 * to respond. During this recovery period, the BMSR returns 2625 * a value of 0. Catch this -- it's not supposed to happen 2626 * (the BMSR has some hardcoded-to-1 bits), and wait for the 2627 * PHY to come back to life. 2628 * 2629 * This works out because the BMSR is the first register 2630 * read during the PHY probe process. 2631 */ 2632 do { 2633 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 2634 } while (reg == MII_BMSR && val == 0); 2635 2636 return (val & 0xffff); 2637 } 2638 2639 /* 2640 * sip_dp83815_mii_writereg: [mii interface function] 2641 * 2642 * Write a PHY register to the MII. 2643 */ 2644 void 2645 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 2646 { 2647 struct sip_softc *sc = (struct sip_softc *) self; 2648 2649 /* 2650 * The DP83815 only has an internal PHY. Only allow 2651 * MII address 0. 2652 */ 2653 if (phy != 0) 2654 return; 2655 2656 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 2657 } 2658 2659 /* 2660 * sip_dp83815_mii_statchg: [mii interface function] 2661 * 2662 * Callback from MII layer when media changes. 2663 */ 2664 void 2665 SIP_DECL(dp83815_mii_statchg)(struct device *self) 2666 { 2667 struct sip_softc *sc = (struct sip_softc *) self; 2668 2669 /* 2670 * Update TXCFG for full-duplex operation. 2671 */ 2672 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2673 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2674 else 2675 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2676 2677 /* 2678 * Update RXCFG for full-duplex or loopback. 2679 */ 2680 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2681 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2682 sc->sc_rxcfg |= RXCFG_ATX; 2683 else 2684 sc->sc_rxcfg &= ~RXCFG_ATX; 2685 2686 /* 2687 * XXX 802.3x flow control. 2688 */ 2689 2690 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2691 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2692 } 2693 #endif /* DP83820 */ 2694 2695 #if defined(DP83820) 2696 void 2697 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, u_int8_t *enaddr) 2698 { 2699 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 2700 u_int8_t cksum, *e, match; 2701 int i; 2702 2703 /* 2704 * EEPROM data format for the DP83820 can be found in 2705 * the DP83820 manual, section 4.2.4. 2706 */ 2707 2708 SIP_DECL(read_eeprom)(sc, 0, 2709 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 2710 2711 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 2712 match = ~(match - 1); 2713 2714 cksum = 0x55; 2715 e = (u_int8_t *) eeprom_data; 2716 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 2717 cksum += *e++; 2718 2719 if (cksum != match) 2720 printf("%s: Checksum (%x) mismatch (%x)", 2721 sc->sc_dev.dv_xname, cksum, match); 2722 2723 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 2724 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 2725 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 2726 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 2727 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 2728 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 2729 2730 /* Get the GPIOR bits. */ 2731 sc->sc_gpior = eeprom_data[0x04]; 2732 2733 /* Get various CFG related bits. */ 2734 if ((eeprom_data[0x05] >> 0) & 1) 2735 sc->sc_cfg |= CFG_EXT_125; 2736 if ((eeprom_data[0x05] >> 9) & 1) 2737 sc->sc_cfg |= CFG_TBI_EN; 2738 } 2739 #else /* ! DP83820 */ 2740 void 2741 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, u_int8_t *enaddr) 2742 { 2743 u_int16_t myea[ETHER_ADDR_LEN / 2]; 2744 2745 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 2746 sizeof(myea) / sizeof(myea[0]), myea); 2747 2748 enaddr[0] = myea[0] & 0xff; 2749 enaddr[1] = myea[0] >> 8; 2750 enaddr[2] = myea[1] & 0xff; 2751 enaddr[3] = myea[1] >> 8; 2752 enaddr[4] = myea[2] & 0xff; 2753 enaddr[5] = myea[2] >> 8; 2754 } 2755 2756 /* Table and macro to bit-reverse an octet. */ 2757 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 2758 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 2759 2760 void 2761 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, u_int8_t *enaddr) 2762 { 2763 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 2764 u_int8_t cksum, *e, match; 2765 int i; 2766 2767 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 2768 sizeof(eeprom_data[0]), eeprom_data); 2769 2770 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 2771 match = ~(match - 1); 2772 2773 cksum = 0x55; 2774 e = (u_int8_t *) eeprom_data; 2775 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 2776 cksum += *e++; 2777 } 2778 if (cksum != match) { 2779 printf("%s: Checksum (%x) mismatch (%x)", 2780 sc->sc_dev.dv_xname, cksum, match); 2781 } 2782 2783 /* 2784 * Unrolled because it makes slightly more sense this way. 2785 * The DP83815 stores the MAC address in bit 0 of word 6 2786 * through bit 15 of word 8. 2787 */ 2788 ea = &eeprom_data[6]; 2789 enaddr[0] = ((*ea & 0x1) << 7); 2790 ea++; 2791 enaddr[0] |= ((*ea & 0xFE00) >> 9); 2792 enaddr[1] = ((*ea & 0x1FE) >> 1); 2793 enaddr[2] = ((*ea & 0x1) << 7); 2794 ea++; 2795 enaddr[2] |= ((*ea & 0xFE00) >> 9); 2796 enaddr[3] = ((*ea & 0x1FE) >> 1); 2797 enaddr[4] = ((*ea & 0x1) << 7); 2798 ea++; 2799 enaddr[4] |= ((*ea & 0xFE00) >> 9); 2800 enaddr[5] = ((*ea & 0x1FE) >> 1); 2801 2802 /* 2803 * In case that's not weird enough, we also need to reverse 2804 * the bits in each byte. This all actually makes more sense 2805 * if you think about the EEPROM storage as an array of bits 2806 * being shifted into bytes, but that's not how we're looking 2807 * at it here... 2808 */ 2809 for (i = 0; i < 6 ;i++) 2810 enaddr[i] = bbr(enaddr[i]); 2811 } 2812 #endif /* DP83820 */ 2813 2814 /* 2815 * sip_mediastatus: [ifmedia interface function] 2816 * 2817 * Get the current interface media status. 2818 */ 2819 void 2820 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 2821 { 2822 struct sip_softc *sc = ifp->if_softc; 2823 2824 mii_pollstat(&sc->sc_mii); 2825 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2826 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2827 } 2828 2829 /* 2830 * sip_mediachange: [ifmedia interface function] 2831 * 2832 * Set hardware to newly-selected media. 2833 */ 2834 int 2835 SIP_DECL(mediachange)(struct ifnet *ifp) 2836 { 2837 struct sip_softc *sc = ifp->if_softc; 2838 2839 if (ifp->if_flags & IFF_UP) 2840 mii_mediachg(&sc->sc_mii); 2841 return (0); 2842 } 2843
Indexes created Tue Sep 30 11:09:46 GMT 2025