if_sip.c revision 1.35
1 /* $NetBSD: if_sip.c,v 1.35 2001/06/30 22:35:05 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Support the 10-bit interface on the DP83820 (for fiber). 80 * 81 * - Support jumbo packets on the DP83820. 82 * 83 * - Reduce the interrupt load. 84 */ 85 86 #include "bpfilter.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #include <net/if.h> 103 #include <net/if_dl.h> 104 #include <net/if_media.h> 105 #include <net/if_ether.h> 106 107 #if NBPFILTER > 0 108 #include <net/bpf.h> 109 #endif 110 111 #include <machine/bus.h> 112 #include <machine/intr.h> 113 #include <machine/endian.h> 114 115 #include <dev/mii/mii.h> 116 #include <dev/mii/miivar.h> 117 #ifdef DP83820 118 #include <dev/mii/mii_bitbang.h> 119 #endif /* DP83820 */ 120 121 #include <dev/pci/pcireg.h> 122 #include <dev/pci/pcivar.h> 123 #include <dev/pci/pcidevs.h> 124 125 #include <dev/pci/if_sipreg.h> 126 127 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 128 #define SIP_DECL(x) __CONCAT(gsip_,x) 129 #else /* SiS900 and DP83815 */ 130 #define SIP_DECL(x) __CONCAT(sip_,x) 131 #endif 132 133 #define SIP_STR(x) __STRING(SIP_DECL(x)) 134 135 /* 136 * Transmit descriptor list size. This is arbitrary, but allocate 137 * enough descriptors for 128 pending transmissions, and 8 segments 138 * per packet. This MUST work out to a power of 2. 139 */ 140 #define SIP_NTXSEGS 8 141 142 #define SIP_TXQUEUELEN 256 143 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS) 144 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 145 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 146 147 /* 148 * Receive descriptor list size. We have one Rx buffer per incoming 149 * packet, so this logic is a little simpler. 150 */ 151 #define SIP_NRXDESC 128 152 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 153 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 154 155 /* 156 * Control structures are DMA'd to the SiS900 chip. We allocate them in 157 * a single clump that maps to a single DMA segment to make several things 158 * easier. 159 */ 160 struct sip_control_data { 161 /* 162 * The transmit descriptors. 163 */ 164 struct sip_desc scd_txdescs[SIP_NTXDESC]; 165 166 /* 167 * The receive descriptors. 168 */ 169 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 170 }; 171 172 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 173 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 174 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 175 176 /* 177 * Software state for transmit jobs. 178 */ 179 struct sip_txsoft { 180 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 181 bus_dmamap_t txs_dmamap; /* our DMA map */ 182 int txs_firstdesc; /* first descriptor in packet */ 183 int txs_lastdesc; /* last descriptor in packet */ 184 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 185 }; 186 187 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 188 189 /* 190 * Software state for receive jobs. 191 */ 192 struct sip_rxsoft { 193 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 194 bus_dmamap_t rxs_dmamap; /* our DMA map */ 195 }; 196 197 /* 198 * Software state per device. 199 */ 200 struct sip_softc { 201 struct device sc_dev; /* generic device information */ 202 bus_space_tag_t sc_st; /* bus space tag */ 203 bus_space_handle_t sc_sh; /* bus space handle */ 204 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 205 struct ethercom sc_ethercom; /* ethernet common data */ 206 void *sc_sdhook; /* shutdown hook */ 207 208 const struct sip_product *sc_model; /* which model are we? */ 209 210 void *sc_ih; /* interrupt cookie */ 211 212 struct mii_data sc_mii; /* MII/media information */ 213 214 struct callout sc_tick_ch; /* tick callout */ 215 216 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 217 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 218 219 /* 220 * Software state for transmit and receive descriptors. 221 */ 222 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 223 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 224 225 /* 226 * Control data structures. 227 */ 228 struct sip_control_data *sc_control_data; 229 #define sc_txdescs sc_control_data->scd_txdescs 230 #define sc_rxdescs sc_control_data->scd_rxdescs 231 232 #ifdef SIP_EVENT_COUNTERS 233 /* 234 * Event counters. 235 */ 236 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 237 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 238 struct evcnt sc_ev_txintr; /* Tx interrupts */ 239 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 240 #ifdef DP83820 241 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 242 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 243 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 244 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 245 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 246 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 247 #endif /* DP83820 */ 248 #endif /* SIP_EVENT_COUNTERS */ 249 250 u_int32_t sc_txcfg; /* prototype TXCFG register */ 251 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 252 u_int32_t sc_imr; /* prototype IMR register */ 253 u_int32_t sc_rfcr; /* prototype RFCR register */ 254 255 u_int32_t sc_cfg; /* prototype CFG register */ 256 257 #ifdef DP83820 258 u_int32_t sc_gpior; /* prototype GPIOR register */ 259 #endif /* DP83820 */ 260 261 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 262 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 263 264 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 265 266 int sc_flags; /* misc. flags; see below */ 267 268 int sc_txfree; /* number of free Tx descriptors */ 269 int sc_txnext; /* next ready Tx descriptor */ 270 271 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 272 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 273 274 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 275 }; 276 277 /* sc_flags */ 278 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 279 280 #ifdef SIP_EVENT_COUNTERS 281 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 282 #else 283 #define SIP_EVCNT_INCR(ev) /* nothing */ 284 #endif 285 286 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 287 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 288 289 #define SIP_CDTXSYNC(sc, x, n, ops) \ 290 do { \ 291 int __x, __n; \ 292 \ 293 __x = (x); \ 294 __n = (n); \ 295 \ 296 /* If it will wrap around, sync to the end of the ring. */ \ 297 if ((__x + __n) > SIP_NTXDESC) { \ 298 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 299 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 300 (SIP_NTXDESC - __x), (ops)); \ 301 __n -= (SIP_NTXDESC - __x); \ 302 __x = 0; \ 303 } \ 304 \ 305 /* Now sync whatever is left. */ \ 306 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 307 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 308 } while (0) 309 310 #define SIP_CDRXSYNC(sc, x, ops) \ 311 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 312 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 313 314 /* 315 * Note we rely on MCLBYTES being a power of two below. 316 */ 317 #ifdef DP83820 318 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 319 #else 320 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 321 #endif 322 #define SIP_INIT_RXDESC(sc, x) \ 323 do { \ 324 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 325 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 326 \ 327 __sipd->sipd_link = htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 328 __sipd->sipd_bufptr = htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 329 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 330 ((MCLBYTES - 1) & CMDSTS_SIZE_MASK)); \ 331 SIP_INIT_RXDESC_EXTSTS \ 332 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 333 } while (0) 334 335 #define SIP_TIMEOUT 1000 336 337 void SIP_DECL(start)(struct ifnet *); 338 void SIP_DECL(watchdog)(struct ifnet *); 339 int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 340 int SIP_DECL(init)(struct ifnet *); 341 void SIP_DECL(stop)(struct ifnet *, int); 342 343 void SIP_DECL(shutdown)(void *); 344 345 void SIP_DECL(reset)(struct sip_softc *); 346 void SIP_DECL(rxdrain)(struct sip_softc *); 347 int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 348 void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, u_int16_t *); 349 void SIP_DECL(tick)(void *); 350 351 #if !defined(DP83820) 352 void SIP_DECL(sis900_set_filter)(struct sip_softc *); 353 #endif /* ! DP83820 */ 354 void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 355 356 #if defined(DP83820) 357 void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, u_int8_t *); 358 #else 359 void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, u_int8_t *); 360 void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, u_int8_t *); 361 #endif /* DP83820 */ 362 363 int SIP_DECL(intr)(void *); 364 void SIP_DECL(txintr)(struct sip_softc *); 365 void SIP_DECL(rxintr)(struct sip_softc *); 366 367 #if defined(DP83820) 368 int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 369 void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 370 void SIP_DECL(dp83820_mii_statchg)(struct device *); 371 #else 372 int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 373 void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 374 void SIP_DECL(sis900_mii_statchg)(struct device *); 375 376 int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 377 void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 378 void SIP_DECL(dp83815_mii_statchg)(struct device *); 379 #endif /* DP83820 */ 380 381 int SIP_DECL(mediachange)(struct ifnet *); 382 void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 383 384 int SIP_DECL(match)(struct device *, struct cfdata *, void *); 385 void SIP_DECL(attach)(struct device *, struct device *, void *); 386 387 int SIP_DECL(copy_small) = 0; 388 389 struct cfattach SIP_DECL(ca) = { 390 sizeof(struct sip_softc), SIP_DECL(match), SIP_DECL(attach), 391 }; 392 393 /* 394 * Descriptions of the variants of the SiS900. 395 */ 396 struct sip_variant { 397 int (*sipv_mii_readreg)(struct device *, int, int); 398 void (*sipv_mii_writereg)(struct device *, int, int, int); 399 void (*sipv_mii_statchg)(struct device *); 400 void (*sipv_set_filter)(struct sip_softc *); 401 void (*sipv_read_macaddr)(struct sip_softc *, u_int8_t *); 402 }; 403 404 #if defined(DP83820) 405 u_int32_t SIP_DECL(dp83820_mii_bitbang_read)(struct device *); 406 void SIP_DECL(dp83820_mii_bitbang_write)(struct device *, u_int32_t); 407 408 const struct mii_bitbang_ops SIP_DECL(dp83820_mii_bitbang_ops) = { 409 SIP_DECL(dp83820_mii_bitbang_read), 410 SIP_DECL(dp83820_mii_bitbang_write), 411 { 412 EROMAR_MDIO, /* MII_BIT_MDO */ 413 EROMAR_MDIO, /* MII_BIT_MDI */ 414 EROMAR_MDC, /* MII_BIT_MDC */ 415 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 416 0, /* MII_BIT_DIR_PHY_HOST */ 417 } 418 }; 419 #endif /* DP83820 */ 420 421 #if defined(DP83820) 422 const struct sip_variant SIP_DECL(variant_dp83820) = { 423 SIP_DECL(dp83820_mii_readreg), 424 SIP_DECL(dp83820_mii_writereg), 425 SIP_DECL(dp83820_mii_statchg), 426 SIP_DECL(dp83815_set_filter), 427 SIP_DECL(dp83820_read_macaddr), 428 }; 429 #else 430 const struct sip_variant SIP_DECL(variant_sis900) = { 431 SIP_DECL(sis900_mii_readreg), 432 SIP_DECL(sis900_mii_writereg), 433 SIP_DECL(sis900_mii_statchg), 434 SIP_DECL(sis900_set_filter), 435 SIP_DECL(sis900_read_macaddr), 436 }; 437 438 const struct sip_variant SIP_DECL(variant_dp83815) = { 439 SIP_DECL(dp83815_mii_readreg), 440 SIP_DECL(dp83815_mii_writereg), 441 SIP_DECL(dp83815_mii_statchg), 442 SIP_DECL(dp83815_set_filter), 443 SIP_DECL(dp83815_read_macaddr), 444 }; 445 #endif /* DP83820 */ 446 447 /* 448 * Devices supported by this driver. 449 */ 450 const struct sip_product { 451 pci_vendor_id_t sip_vendor; 452 pci_product_id_t sip_product; 453 const char *sip_name; 454 const struct sip_variant *sip_variant; 455 } SIP_DECL(products)[] = { 456 #if defined(DP83820) 457 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 458 "NatSemi DP83820 Gigabit Ethernet", 459 &SIP_DECL(variant_dp83820) }, 460 #else 461 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 462 "SiS 900 10/100 Ethernet", 463 &SIP_DECL(variant_sis900) }, 464 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 465 "SiS 7016 10/100 Ethernet", 466 &SIP_DECL(variant_sis900) }, 467 468 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 469 "NatSemi DP83815 10/100 Ethernet", 470 &SIP_DECL(variant_dp83815) }, 471 #endif /* DP83820 */ 472 473 { 0, 0, 474 NULL, 475 NULL }, 476 }; 477 478 static const struct sip_product * 479 SIP_DECL(lookup)(const struct pci_attach_args *pa) 480 { 481 const struct sip_product *sip; 482 483 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 484 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 485 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 486 return (sip); 487 } 488 return (NULL); 489 } 490 491 int 492 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 493 { 494 struct pci_attach_args *pa = aux; 495 496 if (SIP_DECL(lookup)(pa) != NULL) 497 return (1); 498 499 return (0); 500 } 501 502 void 503 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 504 { 505 struct sip_softc *sc = (struct sip_softc *) self; 506 struct pci_attach_args *pa = aux; 507 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 508 pci_chipset_tag_t pc = pa->pa_pc; 509 pci_intr_handle_t ih; 510 const char *intrstr = NULL; 511 bus_space_tag_t iot, memt; 512 bus_space_handle_t ioh, memh; 513 bus_dma_segment_t seg; 514 int ioh_valid, memh_valid; 515 int i, rseg, error; 516 const struct sip_product *sip; 517 pcireg_t pmode; 518 u_int8_t enaddr[ETHER_ADDR_LEN]; 519 int pmreg; 520 #ifdef DP83820 521 pcireg_t memtype; 522 u_int32_t reg; 523 #endif /* DP83820 */ 524 525 callout_init(&sc->sc_tick_ch); 526 527 sip = SIP_DECL(lookup)(pa); 528 if (sip == NULL) { 529 printf("\n"); 530 panic(SIP_STR(attach) ": impossible"); 531 } 532 533 printf(": %s\n", sip->sip_name); 534 535 sc->sc_model = sip; 536 537 /* 538 * Map the device. 539 */ 540 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 541 PCI_MAPREG_TYPE_IO, 0, 542 &iot, &ioh, NULL, NULL) == 0); 543 #ifdef DP83820 544 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 545 switch (memtype) { 546 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 547 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 548 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 549 memtype, 0, &memt, &memh, NULL, NULL) == 0); 550 break; 551 default: 552 memh_valid = 0; 553 } 554 #else 555 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 556 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 557 &memt, &memh, NULL, NULL) == 0); 558 #endif /* DP83820 */ 559 560 if (memh_valid) { 561 sc->sc_st = memt; 562 sc->sc_sh = memh; 563 } else if (ioh_valid) { 564 sc->sc_st = iot; 565 sc->sc_sh = ioh; 566 } else { 567 printf("%s: unable to map device registers\n", 568 sc->sc_dev.dv_xname); 569 return; 570 } 571 572 sc->sc_dmat = pa->pa_dmat; 573 574 /* Enable bus mastering. */ 575 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 576 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 577 PCI_COMMAND_MASTER_ENABLE); 578 579 /* Get it out of power save mode if needed. */ 580 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 581 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 582 if (pmode == 3) { 583 /* 584 * The card has lost all configuration data in 585 * this state, so punt. 586 */ 587 printf("%s: unable to wake up from power state D3\n", 588 sc->sc_dev.dv_xname); 589 return; 590 } 591 if (pmode != 0) { 592 printf("%s: waking up from power state D%d\n", 593 sc->sc_dev.dv_xname, pmode); 594 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 595 } 596 } 597 598 /* 599 * Map and establish our interrupt. 600 */ 601 if (pci_intr_map(pa, &ih)) { 602 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 603 return; 604 } 605 intrstr = pci_intr_string(pc, ih); 606 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 607 if (sc->sc_ih == NULL) { 608 printf("%s: unable to establish interrupt", 609 sc->sc_dev.dv_xname); 610 if (intrstr != NULL) 611 printf(" at %s", intrstr); 612 printf("\n"); 613 return; 614 } 615 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 616 617 SIMPLEQ_INIT(&sc->sc_txfreeq); 618 SIMPLEQ_INIT(&sc->sc_txdirtyq); 619 620 /* 621 * Allocate the control data structures, and create and load the 622 * DMA map for it. 623 */ 624 if ((error = bus_dmamem_alloc(sc->sc_dmat, 625 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 626 0)) != 0) { 627 printf("%s: unable to allocate control data, error = %d\n", 628 sc->sc_dev.dv_xname, error); 629 goto fail_0; 630 } 631 632 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 633 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 634 BUS_DMA_COHERENT)) != 0) { 635 printf("%s: unable to map control data, error = %d\n", 636 sc->sc_dev.dv_xname, error); 637 goto fail_1; 638 } 639 640 if ((error = bus_dmamap_create(sc->sc_dmat, 641 sizeof(struct sip_control_data), 1, 642 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 643 printf("%s: unable to create control data DMA map, " 644 "error = %d\n", sc->sc_dev.dv_xname, error); 645 goto fail_2; 646 } 647 648 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 649 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 650 0)) != 0) { 651 printf("%s: unable to load control data DMA map, error = %d\n", 652 sc->sc_dev.dv_xname, error); 653 goto fail_3; 654 } 655 656 /* 657 * Create the transmit buffer DMA maps. 658 */ 659 for (i = 0; i < SIP_TXQUEUELEN; i++) { 660 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 661 SIP_NTXSEGS, MCLBYTES, 0, 0, 662 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 663 printf("%s: unable to create tx DMA map %d, " 664 "error = %d\n", sc->sc_dev.dv_xname, i, error); 665 goto fail_4; 666 } 667 } 668 669 /* 670 * Create the receive buffer DMA maps. 671 */ 672 for (i = 0; i < SIP_NRXDESC; i++) { 673 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 674 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 675 printf("%s: unable to create rx DMA map %d, " 676 "error = %d\n", sc->sc_dev.dv_xname, i, error); 677 goto fail_5; 678 } 679 sc->sc_rxsoft[i].rxs_mbuf = NULL; 680 } 681 682 /* 683 * Reset the chip to a known state. 684 */ 685 SIP_DECL(reset)(sc); 686 687 /* 688 * Read the Ethernet address from the EEPROM. This might 689 * also fetch other stuff from the EEPROM and stash it 690 * in the softc. 691 */ 692 sc->sc_cfg = 0; 693 (*sip->sip_variant->sipv_read_macaddr)(sc, enaddr); 694 695 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 696 ether_sprintf(enaddr)); 697 698 /* 699 * Initialize the configuration register: aggressive PCI 700 * bus request algorithm, default backoff, default OW timer, 701 * default parity error detection. 702 * 703 * NOTE: "Big endian mode" is useless on the SiS900 and 704 * friends -- it affects packet data, not descriptors. 705 */ 706 #ifdef DP83820 707 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 708 if (reg & CFG_PCI64_DET) { 709 printf("%s: 64-bit PCI slot detected\n", sc->sc_dev.dv_xname); 710 /* 711 * XXX Need some PCI flags indicating support for 712 * XXX 64-bit addressing (SAC or DAC) and 64-bit 713 * XXX data path. 714 */ 715 } 716 if (sc->sc_cfg & (CFG_TBI_EN|CFG_EXT_125)) { 717 const char *sep = ""; 718 printf("%s: using ", sc->sc_dev.dv_xname); 719 if (sc->sc_cfg & CFG_EXT_125) { 720 printf("%s125MHz clock", sep); 721 sep = ", "; 722 } 723 if (sc->sc_cfg & CFG_TBI_EN) { 724 printf("%sten-bit interface", sep); 725 sep = ", "; 726 } 727 printf("\n"); 728 } 729 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0) 730 sc->sc_cfg |= CFG_MRM_DIS; 731 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 732 sc->sc_cfg |= CFG_MWI_DIS; 733 734 /* 735 * Use the extended descriptor format on the DP83820. This 736 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 737 * checksumming. 738 */ 739 sc->sc_cfg |= CFG_EXTSTS_EN; 740 #endif /* DP83820 */ 741 742 /* 743 * Initialize our media structures and probe the MII. 744 */ 745 sc->sc_mii.mii_ifp = ifp; 746 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 747 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 748 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 749 ifmedia_init(&sc->sc_mii.mii_media, 0, SIP_DECL(mediachange), 750 SIP_DECL(mediastatus)); 751 #ifdef DP83820 752 if (sc->sc_cfg & CFG_TBI_EN) { 753 /* Using ten-bit interface. */ 754 printf("%s: TBI -- FIXME\n", sc->sc_dev.dv_xname); 755 } else { 756 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 757 MII_OFFSET_ANY, 0); 758 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 759 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 760 0, NULL); 761 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 762 } else 763 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 764 } 765 #else 766 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 767 MII_OFFSET_ANY, 0); 768 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 769 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 770 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 771 } else 772 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 773 #endif /* DP83820 */ 774 775 ifp = &sc->sc_ethercom.ec_if; 776 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 777 ifp->if_softc = sc; 778 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 779 ifp->if_ioctl = SIP_DECL(ioctl); 780 ifp->if_start = SIP_DECL(start); 781 ifp->if_watchdog = SIP_DECL(watchdog); 782 ifp->if_init = SIP_DECL(init); 783 ifp->if_stop = SIP_DECL(stop); 784 IFQ_SET_READY(&ifp->if_snd); 785 786 /* 787 * We can support 802.1Q VLAN-sized frames. 788 */ 789 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 790 791 #ifdef DP83820 792 /* 793 * And the DP83820 can do VLAN tagging in hardware. 794 */ 795 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 796 797 /* 798 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 799 * in hardware. 800 */ 801 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 802 IFCAP_CSUM_UDPv4; 803 #endif /* DP83820 */ 804 805 /* 806 * Attach the interface. 807 */ 808 if_attach(ifp); 809 ether_ifattach(ifp, enaddr); 810 811 #ifdef SIP_EVENT_COUNTERS 812 /* 813 * Attach event counters. 814 */ 815 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 816 NULL, sc->sc_dev.dv_xname, "txsstall"); 817 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 818 NULL, sc->sc_dev.dv_xname, "txdstall"); 819 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 820 NULL, sc->sc_dev.dv_xname, "txintr"); 821 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 822 NULL, sc->sc_dev.dv_xname, "rxintr"); 823 #ifdef DP83820 824 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 825 NULL, sc->sc_dev.dv_xname, "rxipsum"); 826 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 827 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 828 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 829 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 830 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 831 NULL, sc->sc_dev.dv_xname, "txipsum"); 832 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 833 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 834 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 835 NULL, sc->sc_dev.dv_xname, "txudpsum"); 836 #endif /* DP83820 */ 837 #endif /* SIP_EVENT_COUNTERS */ 838 839 /* 840 * Make sure the interface is shutdown during reboot. 841 */ 842 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 843 if (sc->sc_sdhook == NULL) 844 printf("%s: WARNING: unable to establish shutdown hook\n", 845 sc->sc_dev.dv_xname); 846 return; 847 848 /* 849 * Free any resources we've allocated during the failed attach 850 * attempt. Do this in reverse order and fall through. 851 */ 852 fail_5: 853 for (i = 0; i < SIP_NRXDESC; i++) { 854 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 855 bus_dmamap_destroy(sc->sc_dmat, 856 sc->sc_rxsoft[i].rxs_dmamap); 857 } 858 fail_4: 859 for (i = 0; i < SIP_TXQUEUELEN; i++) { 860 if (sc->sc_txsoft[i].txs_dmamap != NULL) 861 bus_dmamap_destroy(sc->sc_dmat, 862 sc->sc_txsoft[i].txs_dmamap); 863 } 864 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 865 fail_3: 866 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 867 fail_2: 868 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 869 sizeof(struct sip_control_data)); 870 fail_1: 871 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 872 fail_0: 873 return; 874 } 875 876 /* 877 * sip_shutdown: 878 * 879 * Make sure the interface is stopped at reboot time. 880 */ 881 void 882 SIP_DECL(shutdown)(void *arg) 883 { 884 struct sip_softc *sc = arg; 885 886 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 887 } 888 889 /* 890 * sip_start: [ifnet interface function] 891 * 892 * Start packet transmission on the interface. 893 */ 894 void 895 SIP_DECL(start)(struct ifnet *ifp) 896 { 897 struct sip_softc *sc = ifp->if_softc; 898 struct mbuf *m0, *m; 899 struct sip_txsoft *txs; 900 bus_dmamap_t dmamap; 901 int error, firsttx, nexttx, lasttx, ofree, seg; 902 #ifdef DP83820 903 u_int32_t extsts; 904 #endif 905 906 /* 907 * If we've been told to pause, don't transmit any more packets. 908 */ 909 if (sc->sc_flags & SIPF_PAUSED) 910 ifp->if_flags |= IFF_OACTIVE; 911 912 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 913 return; 914 915 /* 916 * Remember the previous number of free descriptors and 917 * the first descriptor we'll use. 918 */ 919 ofree = sc->sc_txfree; 920 firsttx = sc->sc_txnext; 921 922 /* 923 * Loop through the send queue, setting up transmit descriptors 924 * until we drain the queue, or use up all available transmit 925 * descriptors. 926 */ 927 for (;;) { 928 /* Get a work queue entry. */ 929 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 930 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 931 break; 932 } 933 934 /* 935 * Grab a packet off the queue. 936 */ 937 IFQ_POLL(&ifp->if_snd, m0); 938 if (m0 == NULL) 939 break; 940 m = NULL; 941 942 dmamap = txs->txs_dmamap; 943 944 /* 945 * Load the DMA map. If this fails, the packet either 946 * didn't fit in the alloted number of segments, or we 947 * were short on resources. In this case, we'll copy 948 * and try again. 949 */ 950 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 951 BUS_DMA_NOWAIT) != 0) { 952 MGETHDR(m, M_DONTWAIT, MT_DATA); 953 if (m == NULL) { 954 printf("%s: unable to allocate Tx mbuf\n", 955 sc->sc_dev.dv_xname); 956 break; 957 } 958 if (m0->m_pkthdr.len > MHLEN) { 959 MCLGET(m, M_DONTWAIT); 960 if ((m->m_flags & M_EXT) == 0) { 961 printf("%s: unable to allocate Tx " 962 "cluster\n", sc->sc_dev.dv_xname); 963 m_freem(m); 964 break; 965 } 966 } 967 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 968 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 969 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 970 m, BUS_DMA_NOWAIT); 971 if (error) { 972 printf("%s: unable to load Tx buffer, " 973 "error = %d\n", sc->sc_dev.dv_xname, error); 974 break; 975 } 976 } 977 978 /* 979 * Ensure we have enough descriptors free to describe 980 * the packet. Note, we always reserve one descriptor 981 * at the end of the ring as a termination point, to 982 * prevent wrap-around. 983 */ 984 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 985 /* 986 * Not enough free descriptors to transmit this 987 * packet. We haven't committed anything yet, 988 * so just unload the DMA map, put the packet 989 * back on the queue, and punt. Notify the upper 990 * layer that there are not more slots left. 991 * 992 * XXX We could allocate an mbuf and copy, but 993 * XXX is it worth it? 994 */ 995 ifp->if_flags |= IFF_OACTIVE; 996 bus_dmamap_unload(sc->sc_dmat, dmamap); 997 if (m != NULL) 998 m_freem(m); 999 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1000 break; 1001 } 1002 1003 IFQ_DEQUEUE(&ifp->if_snd, m0); 1004 if (m != NULL) { 1005 m_freem(m0); 1006 m0 = m; 1007 } 1008 1009 /* 1010 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1011 */ 1012 1013 /* Sync the DMA map. */ 1014 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1015 BUS_DMASYNC_PREWRITE); 1016 1017 /* 1018 * Initialize the transmit descriptors. 1019 */ 1020 for (nexttx = sc->sc_txnext, seg = 0; 1021 seg < dmamap->dm_nsegs; 1022 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1023 /* 1024 * If this is the first descriptor we're 1025 * enqueueing, don't set the OWN bit just 1026 * yet. That could cause a race condition. 1027 * We'll do it below. 1028 */ 1029 sc->sc_txdescs[nexttx].sipd_bufptr = 1030 htole32(dmamap->dm_segs[seg].ds_addr); 1031 sc->sc_txdescs[nexttx].sipd_cmdsts = 1032 htole32((nexttx == firsttx ? 0 : CMDSTS_OWN) | 1033 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1034 #ifdef DP83820 1035 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1036 #endif /* DP83820 */ 1037 lasttx = nexttx; 1038 } 1039 1040 /* Clear the MORE bit on the last segment. */ 1041 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1042 1043 #ifdef DP83820 1044 /* 1045 * If VLANs are enabled and the packet has a VLAN tag, set 1046 * up the descriptor to encapsulate the packet for us. 1047 * 1048 * This apparently has to be on the last descriptor of 1049 * the packet. 1050 */ 1051 if (sc->sc_ethercom.ec_nvlans != 0 && 1052 (m = m_aux_find(m0, AF_LINK, ETHERTYPE_VLAN)) != NULL) { 1053 sc->sc_txdescs[lasttx].sipd_extsts |= 1054 htole32(EXTSTS_VPKT | 1055 htons(*mtod(m, int *) & EXTSTS_VTCI)); 1056 } 1057 1058 /* 1059 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1060 * checksumming, set up the descriptor to do this work 1061 * for us. 1062 * 1063 * This apparently has to be on the first descriptor of 1064 * the packet. 1065 * 1066 * Byte-swap constants so the compiler can optimize. 1067 */ 1068 extsts = 0; 1069 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1070 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1071 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1072 extsts |= htole32(EXTSTS_IPPKT); 1073 } 1074 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1075 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1076 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1077 extsts |= htole32(EXTSTS_TCPPKT); 1078 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1079 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1080 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1081 extsts |= htole32(EXTSTS_UDPPKT); 1082 } 1083 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1084 #endif /* DP83820 */ 1085 1086 /* Sync the descriptors we're using. */ 1087 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1088 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1089 1090 /* 1091 * Store a pointer to the packet so we can free it later, 1092 * and remember what txdirty will be once the packet is 1093 * done. 1094 */ 1095 txs->txs_mbuf = m0; 1096 txs->txs_firstdesc = sc->sc_txnext; 1097 txs->txs_lastdesc = lasttx; 1098 1099 /* Advance the tx pointer. */ 1100 sc->sc_txfree -= dmamap->dm_nsegs; 1101 sc->sc_txnext = nexttx; 1102 1103 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs, txs_q); 1104 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1105 1106 #if NBPFILTER > 0 1107 /* 1108 * Pass the packet to any BPF listeners. 1109 */ 1110 if (ifp->if_bpf) 1111 bpf_mtap(ifp->if_bpf, m0); 1112 #endif /* NBPFILTER > 0 */ 1113 } 1114 1115 if (txs == NULL || sc->sc_txfree == 0) { 1116 /* No more slots left; notify upper layer. */ 1117 ifp->if_flags |= IFF_OACTIVE; 1118 } 1119 1120 if (sc->sc_txfree != ofree) { 1121 /* 1122 * Cause a descriptor interrupt to happen on the 1123 * last packet we enqueued. 1124 */ 1125 sc->sc_txdescs[lasttx].sipd_cmdsts |= htole32(CMDSTS_INTR); 1126 SIP_CDTXSYNC(sc, lasttx, 1, 1127 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1128 1129 /* 1130 * The entire packet chain is set up. Give the 1131 * first descrptor to the chip now. 1132 */ 1133 sc->sc_txdescs[firsttx].sipd_cmdsts |= htole32(CMDSTS_OWN); 1134 SIP_CDTXSYNC(sc, firsttx, 1, 1135 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1136 1137 /* 1138 * Start the transmit process. Note, the manual says 1139 * that if there are no pending transmissions in the 1140 * chip's internal queue (indicated by TXE being clear), 1141 * then the driver software must set the TXDP to the 1142 * first descriptor to be transmitted. However, if we 1143 * do this, it causes serious performance degredation on 1144 * the DP83820 under load, not setting TXDP doesn't seem 1145 * to adversely affect the SiS 900 or DP83815. 1146 * 1147 * Well, I guess it wouldn't be the first time a manual 1148 * has lied -- and they could be speaking of the NULL- 1149 * terminated descriptor list case, rather than OWN- 1150 * terminated rings. 1151 */ 1152 #if 0 1153 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1154 CR_TXE) == 0) { 1155 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1156 SIP_CDTXADDR(sc, firsttx)); 1157 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1158 } 1159 #else 1160 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1161 #endif 1162 1163 /* Set a watchdog timer in case the chip flakes out. */ 1164 ifp->if_timer = 5; 1165 } 1166 } 1167 1168 /* 1169 * sip_watchdog: [ifnet interface function] 1170 * 1171 * Watchdog timer handler. 1172 */ 1173 void 1174 SIP_DECL(watchdog)(struct ifnet *ifp) 1175 { 1176 struct sip_softc *sc = ifp->if_softc; 1177 1178 /* 1179 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1180 * If we get a timeout, try and sweep up transmit descriptors. 1181 * If we manage to sweep them all up, ignore the lack of 1182 * interrupt. 1183 */ 1184 SIP_DECL(txintr)(sc); 1185 1186 if (sc->sc_txfree != SIP_NTXDESC) { 1187 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1188 ifp->if_oerrors++; 1189 1190 /* Reset the interface. */ 1191 (void) SIP_DECL(init)(ifp); 1192 } else if (ifp->if_flags & IFF_DEBUG) 1193 printf("%s: recovered from device timeout\n", 1194 sc->sc_dev.dv_xname); 1195 1196 /* Try to get more packets going. */ 1197 SIP_DECL(start)(ifp); 1198 } 1199 1200 /* 1201 * sip_ioctl: [ifnet interface function] 1202 * 1203 * Handle control requests from the operator. 1204 */ 1205 int 1206 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1207 { 1208 struct sip_softc *sc = ifp->if_softc; 1209 struct ifreq *ifr = (struct ifreq *)data; 1210 int s, error; 1211 1212 s = splnet(); 1213 1214 switch (cmd) { 1215 case SIOCSIFMEDIA: 1216 case SIOCGIFMEDIA: 1217 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1218 break; 1219 1220 default: 1221 error = ether_ioctl(ifp, cmd, data); 1222 if (error == ENETRESET) { 1223 /* 1224 * Multicast list has changed; set the hardware filter 1225 * accordingly. 1226 */ 1227 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1228 error = 0; 1229 } 1230 break; 1231 } 1232 1233 /* Try to get more packets going. */ 1234 SIP_DECL(start)(ifp); 1235 1236 splx(s); 1237 return (error); 1238 } 1239 1240 /* 1241 * sip_intr: 1242 * 1243 * Interrupt service routine. 1244 */ 1245 int 1246 SIP_DECL(intr)(void *arg) 1247 { 1248 struct sip_softc *sc = arg; 1249 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1250 u_int32_t isr; 1251 int handled = 0; 1252 1253 for (;;) { 1254 /* Reading clears interrupt. */ 1255 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1256 if ((isr & sc->sc_imr) == 0) 1257 break; 1258 1259 handled = 1; 1260 1261 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1262 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1263 1264 /* Grab any new packets. */ 1265 SIP_DECL(rxintr)(sc); 1266 1267 if (isr & ISR_RXORN) { 1268 printf("%s: receive FIFO overrun\n", 1269 sc->sc_dev.dv_xname); 1270 1271 /* XXX adjust rx_drain_thresh? */ 1272 } 1273 1274 if (isr & ISR_RXIDLE) { 1275 printf("%s: receive ring overrun\n", 1276 sc->sc_dev.dv_xname); 1277 1278 /* Get the receive process going again. */ 1279 bus_space_write_4(sc->sc_st, sc->sc_sh, 1280 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1281 bus_space_write_4(sc->sc_st, sc->sc_sh, 1282 SIP_CR, CR_RXE); 1283 } 1284 } 1285 1286 if (isr & (ISR_TXURN|ISR_TXDESC)) { 1287 SIP_EVCNT_INCR(&sc->sc_ev_txintr); 1288 1289 /* Sweep up transmit descriptors. */ 1290 SIP_DECL(txintr)(sc); 1291 1292 if (isr & ISR_TXURN) { 1293 u_int32_t thresh; 1294 1295 printf("%s: transmit FIFO underrun", 1296 sc->sc_dev.dv_xname); 1297 1298 thresh = sc->sc_tx_drain_thresh + 1; 1299 if (thresh <= TXCFG_DRTH && 1300 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1301 (sc->sc_tx_fill_thresh * 32))) { 1302 printf("; increasing Tx drain " 1303 "threshold to %u bytes\n", 1304 thresh * 32); 1305 sc->sc_tx_drain_thresh = thresh; 1306 (void) SIP_DECL(init)(ifp); 1307 } else { 1308 (void) SIP_DECL(init)(ifp); 1309 printf("\n"); 1310 } 1311 } 1312 } 1313 1314 #if !defined(DP83820) 1315 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1316 if (isr & ISR_PAUSE_ST) { 1317 sc->sc_flags |= SIPF_PAUSED; 1318 ifp->if_flags |= IFF_OACTIVE; 1319 } 1320 if (isr & ISR_PAUSE_END) { 1321 sc->sc_flags &= ~SIPF_PAUSED; 1322 ifp->if_flags &= ~IFF_OACTIVE; 1323 } 1324 } 1325 #endif /* ! DP83820 */ 1326 1327 if (isr & ISR_HIBERR) { 1328 #define PRINTERR(bit, str) \ 1329 if (isr & (bit)) \ 1330 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1331 PRINTERR(ISR_DPERR, "parity error"); 1332 PRINTERR(ISR_SSERR, "system error"); 1333 PRINTERR(ISR_RMABT, "master abort"); 1334 PRINTERR(ISR_RTABT, "target abort"); 1335 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1336 (void) SIP_DECL(init)(ifp); 1337 #undef PRINTERR 1338 } 1339 } 1340 1341 /* Try to get more packets going. */ 1342 SIP_DECL(start)(ifp); 1343 1344 return (handled); 1345 } 1346 1347 /* 1348 * sip_txintr: 1349 * 1350 * Helper; handle transmit interrupts. 1351 */ 1352 void 1353 SIP_DECL(txintr)(struct sip_softc *sc) 1354 { 1355 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1356 struct sip_txsoft *txs; 1357 u_int32_t cmdsts; 1358 1359 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1360 ifp->if_flags &= ~IFF_OACTIVE; 1361 1362 /* 1363 * Go through our Tx list and free mbufs for those 1364 * frames which have been transmitted. 1365 */ 1366 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1367 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1368 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1369 1370 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1371 if (cmdsts & CMDSTS_OWN) 1372 break; 1373 1374 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1375 1376 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1377 1378 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1379 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1380 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1381 m_freem(txs->txs_mbuf); 1382 txs->txs_mbuf = NULL; 1383 1384 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1385 1386 /* 1387 * Check for errors and collisions. 1388 */ 1389 if (cmdsts & 1390 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1391 ifp->if_oerrors++; 1392 if (cmdsts & CMDSTS_Tx_EC) 1393 ifp->if_collisions += 16; 1394 if (ifp->if_flags & IFF_DEBUG) { 1395 if (cmdsts & CMDSTS_Tx_ED) 1396 printf("%s: excessive deferral\n", 1397 sc->sc_dev.dv_xname); 1398 if (cmdsts & CMDSTS_Tx_EC) 1399 printf("%s: excessive collisions\n", 1400 sc->sc_dev.dv_xname); 1401 } 1402 } else { 1403 /* Packet was transmitted successfully. */ 1404 ifp->if_opackets++; 1405 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1406 } 1407 } 1408 1409 /* 1410 * If there are no more pending transmissions, cancel the watchdog 1411 * timer. 1412 */ 1413 if (txs == NULL) 1414 ifp->if_timer = 0; 1415 } 1416 1417 #if defined(DP83820) 1418 /* 1419 * sip_rxintr: 1420 * 1421 * Helper; handle receive interrupts. 1422 */ 1423 void 1424 SIP_DECL(rxintr)(struct sip_softc *sc) 1425 { 1426 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1427 struct sip_rxsoft *rxs; 1428 struct mbuf *m; 1429 u_int32_t cmdsts, extsts; 1430 int i, len; 1431 1432 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1433 rxs = &sc->sc_rxsoft[i]; 1434 1435 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1436 1437 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1438 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1439 1440 /* 1441 * NOTE: OWN is set if owned by _consumer_. We're the 1442 * consumer of the receive ring, so if the bit is clear, 1443 * we have processed all of the packets. 1444 */ 1445 if ((cmdsts & CMDSTS_OWN) == 0) { 1446 /* 1447 * We have processed all of the receive buffers. 1448 */ 1449 break; 1450 } 1451 1452 /* 1453 * If an error occurred, update stats, clear the status 1454 * word, and leave the packet buffer in place. It will 1455 * simply be reused the next time the ring comes around. 1456 */ 1457 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_LONG|CMDSTS_Rx_RUNT| 1458 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1459 ifp->if_ierrors++; 1460 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1461 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1462 /* Receive overrun handled elsewhere. */ 1463 printf("%s: receive descriptor error\n", 1464 sc->sc_dev.dv_xname); 1465 } 1466 #define PRINTERR(bit, str) \ 1467 if (cmdsts & (bit)) \ 1468 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1469 PRINTERR(CMDSTS_Rx_LONG, "packet too long"); 1470 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1471 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1472 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1473 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1474 #undef PRINTERR 1475 SIP_INIT_RXDESC(sc, i); 1476 continue; 1477 } 1478 1479 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1480 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1481 1482 /* 1483 * No errors; receive the packet. Note, the DP83820 1484 * includes the CRC with every packet. 1485 */ 1486 len = CMDSTS_SIZE(cmdsts); 1487 1488 #ifdef __NO_STRICT_ALIGNMENT 1489 /* 1490 * If the packet is small enough to fit in a 1491 * single header mbuf, allocate one and copy 1492 * the data into it. This greatly reduces 1493 * memory consumption when we receive lots 1494 * of small packets. 1495 * 1496 * Otherwise, we add a new buffer to the receive 1497 * chain. If this fails, we drop the packet and 1498 * recycle the old buffer. 1499 */ 1500 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 1501 MGETHDR(m, M_DONTWAIT, MT_DATA); 1502 if (m == NULL) 1503 goto dropit; 1504 memcpy(mtod(m, caddr_t), 1505 mtod(rxs->rxs_mbuf, caddr_t), len); 1506 SIP_INIT_RXDESC(sc, i); 1507 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1508 rxs->rxs_dmamap->dm_mapsize, 1509 BUS_DMASYNC_PREREAD); 1510 } else { 1511 m = rxs->rxs_mbuf; 1512 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1513 dropit: 1514 ifp->if_ierrors++; 1515 SIP_INIT_RXDESC(sc, i); 1516 bus_dmamap_sync(sc->sc_dmat, 1517 rxs->rxs_dmamap, 0, 1518 rxs->rxs_dmamap->dm_mapsize, 1519 BUS_DMASYNC_PREREAD); 1520 continue; 1521 } 1522 } 1523 #else 1524 /* 1525 * The SiS 900's receive buffers must be 4-byte aligned. 1526 * But this means that the data after the Ethernet header 1527 * is misaligned. We must allocate a new buffer and 1528 * copy the data, shifted forward 2 bytes. 1529 */ 1530 MGETHDR(m, M_DONTWAIT, MT_DATA); 1531 if (m == NULL) { 1532 dropit: 1533 ifp->if_ierrors++; 1534 SIP_INIT_RXDESC(sc, i); 1535 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1536 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1537 continue; 1538 } 1539 if (len > (MHLEN - 2)) { 1540 MCLGET(m, M_DONTWAIT); 1541 if ((m->m_flags & M_EXT) == 0) { 1542 m_freem(m); 1543 goto dropit; 1544 } 1545 } 1546 m->m_data += 2; 1547 1548 /* 1549 * Note that we use clusters for incoming frames, so the 1550 * buffer is virtually contiguous. 1551 */ 1552 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 1553 1554 /* Allow the receive descriptor to continue using its mbuf. */ 1555 SIP_INIT_RXDESC(sc, i); 1556 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1557 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1558 #endif /* __NO_STRICT_ALIGNMENT */ 1559 1560 ifp->if_ipackets++; 1561 m->m_flags |= M_HASFCS; 1562 m->m_pkthdr.rcvif = ifp; 1563 m->m_pkthdr.len = m->m_len = len; 1564 1565 #if NBPFILTER > 0 1566 /* 1567 * Pass this up to any BPF listeners, but only 1568 * pass if up the stack if it's for us. 1569 */ 1570 if (ifp->if_bpf) 1571 bpf_mtap(ifp->if_bpf, m); 1572 #endif /* NBPFILTER > 0 */ 1573 1574 /* 1575 * If VLANs are enabled, VLAN packets have been unwrapped 1576 * for us. Associate the tag with the packet. 1577 */ 1578 if (sc->sc_ethercom.ec_nvlans != 0 && 1579 (extsts & EXTSTS_VPKT) != 0) { 1580 struct mbuf *vtag; 1581 1582 vtag = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 1583 if (vtag == NULL) { 1584 printf("%s: unable to allocate VLAN tag\n", 1585 sc->sc_dev.dv_xname); 1586 m_freem(m); 1587 continue; 1588 } 1589 1590 *mtod(vtag, int *) = ntohs(extsts & EXTSTS_VTCI); 1591 vtag->m_len = sizeof(int); 1592 } 1593 1594 /* 1595 * Set the incoming checksum information for the 1596 * packet. 1597 */ 1598 if ((extsts & EXTSTS_IPPKT) != 0) { 1599 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1600 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1601 if (extsts & EXTSTS_Rx_IPERR) 1602 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1603 if (extsts & EXTSTS_TCPPKT) { 1604 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1605 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1606 if (extsts & EXTSTS_Rx_TCPERR) 1607 m->m_pkthdr.csum_flags |= 1608 M_CSUM_TCP_UDP_BAD; 1609 } else if (extsts & EXTSTS_UDPPKT) { 1610 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1611 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1612 if (extsts & EXTSTS_Rx_UDPERR) 1613 m->m_pkthdr.csum_flags |= 1614 M_CSUM_TCP_UDP_BAD; 1615 } 1616 } 1617 1618 /* Pass it on. */ 1619 (*ifp->if_input)(ifp, m); 1620 } 1621 1622 /* Update the receive pointer. */ 1623 sc->sc_rxptr = i; 1624 } 1625 #else /* ! DP83820 */ 1626 /* 1627 * sip_rxintr: 1628 * 1629 * Helper; handle receive interrupts. 1630 */ 1631 void 1632 SIP_DECL(rxintr)(struct sip_softc *sc) 1633 { 1634 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1635 struct sip_rxsoft *rxs; 1636 struct mbuf *m; 1637 u_int32_t cmdsts; 1638 int i, len; 1639 1640 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1641 rxs = &sc->sc_rxsoft[i]; 1642 1643 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1644 1645 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1646 1647 /* 1648 * NOTE: OWN is set if owned by _consumer_. We're the 1649 * consumer of the receive ring, so if the bit is clear, 1650 * we have processed all of the packets. 1651 */ 1652 if ((cmdsts & CMDSTS_OWN) == 0) { 1653 /* 1654 * We have processed all of the receive buffers. 1655 */ 1656 break; 1657 } 1658 1659 /* 1660 * If any collisions were seen on the wire, count one. 1661 */ 1662 if (cmdsts & CMDSTS_Rx_COL) 1663 ifp->if_collisions++; 1664 1665 /* 1666 * If an error occurred, update stats, clear the status 1667 * word, and leave the packet buffer in place. It will 1668 * simply be reused the next time the ring comes around. 1669 */ 1670 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_LONG|CMDSTS_Rx_RUNT| 1671 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1672 ifp->if_ierrors++; 1673 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1674 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1675 /* Receive overrun handled elsewhere. */ 1676 printf("%s: receive descriptor error\n", 1677 sc->sc_dev.dv_xname); 1678 } 1679 #define PRINTERR(bit, str) \ 1680 if (cmdsts & (bit)) \ 1681 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1682 PRINTERR(CMDSTS_Rx_LONG, "packet too long"); 1683 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1684 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1685 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1686 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1687 #undef PRINTERR 1688 SIP_INIT_RXDESC(sc, i); 1689 continue; 1690 } 1691 1692 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1693 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1694 1695 /* 1696 * No errors; receive the packet. Note, the SiS 900 1697 * includes the CRC with every packet. 1698 */ 1699 len = CMDSTS_SIZE(cmdsts); 1700 1701 #ifdef __NO_STRICT_ALIGNMENT 1702 /* 1703 * If the packet is small enough to fit in a 1704 * single header mbuf, allocate one and copy 1705 * the data into it. This greatly reduces 1706 * memory consumption when we receive lots 1707 * of small packets. 1708 * 1709 * Otherwise, we add a new buffer to the receive 1710 * chain. If this fails, we drop the packet and 1711 * recycle the old buffer. 1712 */ 1713 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 1714 MGETHDR(m, M_DONTWAIT, MT_DATA); 1715 if (m == NULL) 1716 goto dropit; 1717 memcpy(mtod(m, caddr_t), 1718 mtod(rxs->rxs_mbuf, caddr_t), len); 1719 SIP_INIT_RXDESC(sc, i); 1720 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1721 rxs->rxs_dmamap->dm_mapsize, 1722 BUS_DMASYNC_PREREAD); 1723 } else { 1724 m = rxs->rxs_mbuf; 1725 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1726 dropit: 1727 ifp->if_ierrors++; 1728 SIP_INIT_RXDESC(sc, i); 1729 bus_dmamap_sync(sc->sc_dmat, 1730 rxs->rxs_dmamap, 0, 1731 rxs->rxs_dmamap->dm_mapsize, 1732 BUS_DMASYNC_PREREAD); 1733 continue; 1734 } 1735 } 1736 #else 1737 /* 1738 * The SiS 900's receive buffers must be 4-byte aligned. 1739 * But this means that the data after the Ethernet header 1740 * is misaligned. We must allocate a new buffer and 1741 * copy the data, shifted forward 2 bytes. 1742 */ 1743 MGETHDR(m, M_DONTWAIT, MT_DATA); 1744 if (m == NULL) { 1745 dropit: 1746 ifp->if_ierrors++; 1747 SIP_INIT_RXDESC(sc, i); 1748 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1749 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1750 continue; 1751 } 1752 if (len > (MHLEN - 2)) { 1753 MCLGET(m, M_DONTWAIT); 1754 if ((m->m_flags & M_EXT) == 0) { 1755 m_freem(m); 1756 goto dropit; 1757 } 1758 } 1759 m->m_data += 2; 1760 1761 /* 1762 * Note that we use clusters for incoming frames, so the 1763 * buffer is virtually contiguous. 1764 */ 1765 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 1766 1767 /* Allow the receive descriptor to continue using its mbuf. */ 1768 SIP_INIT_RXDESC(sc, i); 1769 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1770 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1771 #endif /* __NO_STRICT_ALIGNMENT */ 1772 1773 ifp->if_ipackets++; 1774 m->m_flags |= M_HASFCS; 1775 m->m_pkthdr.rcvif = ifp; 1776 m->m_pkthdr.len = m->m_len = len; 1777 1778 #if NBPFILTER > 0 1779 /* 1780 * Pass this up to any BPF listeners, but only 1781 * pass if up the stack if it's for us. 1782 */ 1783 if (ifp->if_bpf) 1784 bpf_mtap(ifp->if_bpf, m); 1785 #endif /* NBPFILTER > 0 */ 1786 1787 /* Pass it on. */ 1788 (*ifp->if_input)(ifp, m); 1789 } 1790 1791 /* Update the receive pointer. */ 1792 sc->sc_rxptr = i; 1793 } 1794 #endif /* DP83820 */ 1795 1796 /* 1797 * sip_tick: 1798 * 1799 * One second timer, used to tick the MII. 1800 */ 1801 void 1802 SIP_DECL(tick)(void *arg) 1803 { 1804 struct sip_softc *sc = arg; 1805 int s; 1806 1807 s = splnet(); 1808 mii_tick(&sc->sc_mii); 1809 splx(s); 1810 1811 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 1812 } 1813 1814 /* 1815 * sip_reset: 1816 * 1817 * Perform a soft reset on the SiS 900. 1818 */ 1819 void 1820 SIP_DECL(reset)(struct sip_softc *sc) 1821 { 1822 bus_space_tag_t st = sc->sc_st; 1823 bus_space_handle_t sh = sc->sc_sh; 1824 int i; 1825 1826 bus_space_write_4(st, sh, SIP_CR, CR_RST); 1827 1828 for (i = 0; i < SIP_TIMEOUT; i++) { 1829 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 1830 break; 1831 delay(2); 1832 } 1833 1834 if (i == SIP_TIMEOUT) 1835 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1836 1837 delay(1000); 1838 1839 #ifdef DP83820 1840 /* 1841 * Set the general purpose I/O bits. Do it here in case we 1842 * need to have GPIO set up to talk to the media interface. 1843 */ 1844 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 1845 delay(1000); 1846 #endif /* DP83820 */ 1847 } 1848 1849 /* 1850 * sip_init: [ ifnet interface function ] 1851 * 1852 * Initialize the interface. Must be called at splnet(). 1853 */ 1854 int 1855 SIP_DECL(init)(struct ifnet *ifp) 1856 { 1857 struct sip_softc *sc = ifp->if_softc; 1858 bus_space_tag_t st = sc->sc_st; 1859 bus_space_handle_t sh = sc->sc_sh; 1860 struct sip_txsoft *txs; 1861 struct sip_rxsoft *rxs; 1862 struct sip_desc *sipd; 1863 u_int32_t reg; 1864 int i, error = 0; 1865 1866 /* 1867 * Cancel any pending I/O. 1868 */ 1869 SIP_DECL(stop)(ifp, 0); 1870 1871 /* 1872 * Reset the chip to a known state. 1873 */ 1874 SIP_DECL(reset)(sc); 1875 1876 #if !defined(DP83820) 1877 if (sc->sc_model->sip_vendor == PCI_VENDOR_NS && 1878 sc->sc_model->sip_product == PCI_PRODUCT_NS_DP83815) { 1879 /* 1880 * DP83815 manual, page 78: 1881 * 4.4 Recommended Registers Configuration 1882 * For optimum performance of the DP83815, version noted 1883 * as DP83815CVNG (SRR = 203h), the listed register 1884 * modifications must be followed in sequence... 1885 * 1886 * It's not clear if this should be 302h or 203h because that 1887 * chip name is listed as SRR 302h in the description of the 1888 * SRR register. However, my revision 302h DP83815 on the 1889 * Netgear FA311 purchased in 02/2001 needs these settings 1890 * to avoid tons of errors in AcceptPerfectMatch (non- 1891 * IFF_PROMISC) mode. I do not know if other revisions need 1892 * this set or not. [briggs -- 09 March 2001] 1893 * 1894 * Note that only the low-order 12 bits of 0xe4 are documented 1895 * and that this sets reserved bits in that register. 1896 */ 1897 reg = bus_space_read_4(st, sh, SIP_NS_SRR); 1898 if (reg == 0x302) { 1899 bus_space_write_4(st, sh, 0x00cc, 0x0001); 1900 bus_space_write_4(st, sh, 0x00e4, 0x189C); 1901 bus_space_write_4(st, sh, 0x00fc, 0x0000); 1902 bus_space_write_4(st, sh, 0x00f4, 0x5040); 1903 bus_space_write_4(st, sh, 0x00f8, 0x008c); 1904 } 1905 } 1906 #endif /* ! DP83820 */ 1907 1908 /* 1909 * Initialize the transmit descriptor ring. 1910 */ 1911 for (i = 0; i < SIP_NTXDESC; i++) { 1912 sipd = &sc->sc_txdescs[i]; 1913 memset(sipd, 0, sizeof(struct sip_desc)); 1914 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 1915 } 1916 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 1917 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1918 sc->sc_txfree = SIP_NTXDESC; 1919 sc->sc_txnext = 0; 1920 1921 /* 1922 * Initialize the transmit job descriptors. 1923 */ 1924 SIMPLEQ_INIT(&sc->sc_txfreeq); 1925 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1926 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1927 txs = &sc->sc_txsoft[i]; 1928 txs->txs_mbuf = NULL; 1929 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1930 } 1931 1932 /* 1933 * Initialize the receive descriptor and receive job 1934 * descriptor rings. 1935 */ 1936 for (i = 0; i < SIP_NRXDESC; i++) { 1937 rxs = &sc->sc_rxsoft[i]; 1938 if (rxs->rxs_mbuf == NULL) { 1939 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 1940 printf("%s: unable to allocate or map rx " 1941 "buffer %d, error = %d\n", 1942 sc->sc_dev.dv_xname, i, error); 1943 /* 1944 * XXX Should attempt to run with fewer receive 1945 * XXX buffers instead of just failing. 1946 */ 1947 SIP_DECL(rxdrain)(sc); 1948 goto out; 1949 } 1950 } 1951 } 1952 sc->sc_rxptr = 0; 1953 1954 /* 1955 * Set the configuration register; it's already initialized 1956 * in sip_attach(). 1957 */ 1958 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 1959 1960 /* 1961 * Initialize the transmit fill and drain thresholds if 1962 * we have never done so. 1963 */ 1964 if (sc->sc_tx_fill_thresh == 0) { 1965 /* 1966 * XXX This value should be tuned. This is the 1967 * minimum (32 bytes), and we may be able to 1968 * improve performance by increasing it. 1969 */ 1970 sc->sc_tx_fill_thresh = 1; 1971 } 1972 if (sc->sc_tx_drain_thresh == 0) { 1973 /* 1974 * Start at a drain threshold of 512 bytes. We will 1975 * increase it if a DMA underrun occurs. 1976 * 1977 * XXX The minimum value of this variable should be 1978 * tuned. We may be able to improve performance 1979 * by starting with a lower value. That, however, 1980 * may trash the first few outgoing packets if the 1981 * PCI bus is saturated. 1982 */ 1983 sc->sc_tx_drain_thresh = 512 / 32; 1984 } 1985 1986 /* 1987 * Initialize the prototype TXCFG register. 1988 */ 1989 sc->sc_txcfg = TXCFG_ATP | TXCFG_MXDMA_512 | 1990 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 1991 sc->sc_tx_drain_thresh; 1992 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 1993 1994 /* 1995 * Initialize the receive drain threshold if we have never 1996 * done so. 1997 */ 1998 if (sc->sc_rx_drain_thresh == 0) { 1999 /* 2000 * XXX This value should be tuned. This is set to the 2001 * maximum of 248 bytes, and we may be able to improve 2002 * performance by decreasing it (although we should never 2003 * set this value lower than 2; 14 bytes are required to 2004 * filter the packet). 2005 */ 2006 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2007 } 2008 2009 /* 2010 * Initialize the prototype RXCFG register. 2011 */ 2012 sc->sc_rxcfg = RXCFG_MXDMA_512 | 2013 (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2014 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2015 2016 /* Set up the receive filter. */ 2017 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2018 2019 #ifdef DP83820 2020 /* 2021 * Initialize the VLAN/IP receive control register. 2022 * We enable checksum computation on all incoming 2023 * packets, and do not reject packets w/ bad checksums. 2024 */ 2025 reg = 0; 2026 if (ifp->if_capenable & 2027 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2028 reg |= VRCR_IPEN; 2029 if (sc->sc_ethercom.ec_nvlans != 0) 2030 reg |= VRCR_VTDEN|VRCR_VTREN; 2031 bus_space_write_4(st, sh, SIP_VRCR, reg); 2032 2033 /* 2034 * Initialize the VLAN/IP transmit control register. 2035 * We enable outgoing checksum computation on a 2036 * per-packet basis. 2037 */ 2038 reg = 0; 2039 if (ifp->if_capenable & 2040 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2041 reg |= VTCR_PPCHK; 2042 if (sc->sc_ethercom.ec_nvlans != 0) 2043 reg |= VTCR_VPPTI; 2044 bus_space_write_4(st, sh, SIP_VTCR, reg); 2045 2046 /* 2047 * If we're using VLANs, initialize the VLAN data register. 2048 * To understand why we bswap the VLAN Ethertype, see section 2049 * 4.2.36 of the DP83820 manual. 2050 */ 2051 if (sc->sc_ethercom.ec_nvlans != 0) 2052 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2053 #endif /* DP83820 */ 2054 2055 /* 2056 * Give the transmit and receive rings to the chip. 2057 */ 2058 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2059 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2060 2061 /* 2062 * Initialize the interrupt mask. 2063 */ 2064 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2065 ISR_TXURN|ISR_TXDESC|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2066 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2067 2068 /* 2069 * Set the current media. Do this after initializing the prototype 2070 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2071 * control. 2072 */ 2073 mii_mediachg(&sc->sc_mii); 2074 2075 /* 2076 * Enable interrupts. 2077 */ 2078 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2079 2080 /* 2081 * Start the transmit and receive processes. 2082 */ 2083 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2084 2085 /* 2086 * Start the one second MII clock. 2087 */ 2088 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2089 2090 /* 2091 * ...all done! 2092 */ 2093 ifp->if_flags |= IFF_RUNNING; 2094 ifp->if_flags &= ~IFF_OACTIVE; 2095 2096 out: 2097 if (error) 2098 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2099 return (error); 2100 } 2101 2102 /* 2103 * sip_drain: 2104 * 2105 * Drain the receive queue. 2106 */ 2107 void 2108 SIP_DECL(rxdrain)(struct sip_softc *sc) 2109 { 2110 struct sip_rxsoft *rxs; 2111 int i; 2112 2113 for (i = 0; i < SIP_NRXDESC; i++) { 2114 rxs = &sc->sc_rxsoft[i]; 2115 if (rxs->rxs_mbuf != NULL) { 2116 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2117 m_freem(rxs->rxs_mbuf); 2118 rxs->rxs_mbuf = NULL; 2119 } 2120 } 2121 } 2122 2123 /* 2124 * sip_stop: [ ifnet interface function ] 2125 * 2126 * Stop transmission on the interface. 2127 */ 2128 void 2129 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2130 { 2131 struct sip_softc *sc = ifp->if_softc; 2132 bus_space_tag_t st = sc->sc_st; 2133 bus_space_handle_t sh = sc->sc_sh; 2134 struct sip_txsoft *txs; 2135 u_int32_t cmdsts = 0; /* DEBUG */ 2136 2137 /* 2138 * Stop the one second clock. 2139 */ 2140 callout_stop(&sc->sc_tick_ch); 2141 2142 /* Down the MII. */ 2143 mii_down(&sc->sc_mii); 2144 2145 /* 2146 * Disable interrupts. 2147 */ 2148 bus_space_write_4(st, sh, SIP_IER, 0); 2149 2150 /* 2151 * Stop receiver and transmitter. 2152 */ 2153 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2154 2155 /* 2156 * Release any queued transmit buffers. 2157 */ 2158 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2159 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2160 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2161 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2162 CMDSTS_INTR) == 0) 2163 printf("%s: sip_stop: last descriptor does not " 2164 "have INTR bit set\n", sc->sc_dev.dv_xname); 2165 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 2166 #ifdef DIAGNOSTIC 2167 if (txs->txs_mbuf == NULL) { 2168 printf("%s: dirty txsoft with no mbuf chain\n", 2169 sc->sc_dev.dv_xname); 2170 panic("sip_stop"); 2171 } 2172 #endif 2173 cmdsts |= /* DEBUG */ 2174 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2175 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2176 m_freem(txs->txs_mbuf); 2177 txs->txs_mbuf = NULL; 2178 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2179 } 2180 2181 if (disable) 2182 SIP_DECL(rxdrain)(sc); 2183 2184 /* 2185 * Mark the interface down and cancel the watchdog timer. 2186 */ 2187 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2188 ifp->if_timer = 0; 2189 2190 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2191 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2192 printf("%s: sip_stop: no INTR bits set in dirty tx " 2193 "descriptors\n", sc->sc_dev.dv_xname); 2194 } 2195 2196 /* 2197 * sip_read_eeprom: 2198 * 2199 * Read data from the serial EEPROM. 2200 */ 2201 void 2202 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2203 u_int16_t *data) 2204 { 2205 bus_space_tag_t st = sc->sc_st; 2206 bus_space_handle_t sh = sc->sc_sh; 2207 u_int16_t reg; 2208 int i, x; 2209 2210 for (i = 0; i < wordcnt; i++) { 2211 /* Send CHIP SELECT. */ 2212 reg = EROMAR_EECS; 2213 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2214 2215 /* Shift in the READ opcode. */ 2216 for (x = 3; x > 0; x--) { 2217 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2218 reg |= EROMAR_EEDI; 2219 else 2220 reg &= ~EROMAR_EEDI; 2221 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2222 bus_space_write_4(st, sh, SIP_EROMAR, 2223 reg | EROMAR_EESK); 2224 delay(4); 2225 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2226 delay(4); 2227 } 2228 2229 /* Shift in address. */ 2230 for (x = 6; x > 0; x--) { 2231 if ((word + i) & (1 << (x - 1))) 2232 reg |= EROMAR_EEDI; 2233 else 2234 reg &= ~EROMAR_EEDI; 2235 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2236 bus_space_write_4(st, sh, SIP_EROMAR, 2237 reg | EROMAR_EESK); 2238 delay(4); 2239 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2240 delay(4); 2241 } 2242 2243 /* Shift out data. */ 2244 reg = EROMAR_EECS; 2245 data[i] = 0; 2246 for (x = 16; x > 0; x--) { 2247 bus_space_write_4(st, sh, SIP_EROMAR, 2248 reg | EROMAR_EESK); 2249 delay(4); 2250 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2251 data[i] |= (1 << (x - 1)); 2252 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2253 delay(4); 2254 } 2255 2256 /* Clear CHIP SELECT. */ 2257 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2258 delay(4); 2259 } 2260 } 2261 2262 /* 2263 * sip_add_rxbuf: 2264 * 2265 * Add a receive buffer to the indicated descriptor. 2266 */ 2267 int 2268 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2269 { 2270 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2271 struct mbuf *m; 2272 int error; 2273 2274 MGETHDR(m, M_DONTWAIT, MT_DATA); 2275 if (m == NULL) 2276 return (ENOBUFS); 2277 2278 MCLGET(m, M_DONTWAIT); 2279 if ((m->m_flags & M_EXT) == 0) { 2280 m_freem(m); 2281 return (ENOBUFS); 2282 } 2283 2284 if (rxs->rxs_mbuf != NULL) 2285 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2286 2287 rxs->rxs_mbuf = m; 2288 2289 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2290 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 2291 if (error) { 2292 printf("%s: can't load rx DMA map %d, error = %d\n", 2293 sc->sc_dev.dv_xname, idx, error); 2294 panic("sip_add_rxbuf"); /* XXX */ 2295 } 2296 2297 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2298 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2299 2300 SIP_INIT_RXDESC(sc, idx); 2301 2302 return (0); 2303 } 2304 2305 #if !defined(DP83820) 2306 /* 2307 * sip_sis900_set_filter: 2308 * 2309 * Set up the receive filter. 2310 */ 2311 void 2312 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2313 { 2314 bus_space_tag_t st = sc->sc_st; 2315 bus_space_handle_t sh = sc->sc_sh; 2316 struct ethercom *ec = &sc->sc_ethercom; 2317 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2318 struct ether_multi *enm; 2319 u_int8_t *cp; 2320 struct ether_multistep step; 2321 u_int32_t crc, mchash[8]; 2322 2323 /* 2324 * Initialize the prototype RFCR. 2325 */ 2326 sc->sc_rfcr = RFCR_RFEN; 2327 if (ifp->if_flags & IFF_BROADCAST) 2328 sc->sc_rfcr |= RFCR_AAB; 2329 if (ifp->if_flags & IFF_PROMISC) { 2330 sc->sc_rfcr |= RFCR_AAP; 2331 goto allmulti; 2332 } 2333 2334 /* 2335 * Set up the multicast address filter by passing all multicast 2336 * addresses through a CRC generator, and then using the high-order 2337 * 6 bits as an index into the 128 bit multicast hash table (only 2338 * the lower 16 bits of each 32 bit multicast hash register are 2339 * valid). The high order bits select the register, while the 2340 * rest of the bits select the bit within the register. 2341 */ 2342 2343 memset(mchash, 0, sizeof(mchash)); 2344 2345 ETHER_FIRST_MULTI(step, ec, enm); 2346 while (enm != NULL) { 2347 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2348 /* 2349 * We must listen to a range of multicast addresses. 2350 * For now, just accept all multicasts, rather than 2351 * trying to set only those filter bits needed to match 2352 * the range. (At this time, the only use of address 2353 * ranges is for IP multicast routing, for which the 2354 * range is big enough to require all bits set.) 2355 */ 2356 goto allmulti; 2357 } 2358 2359 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2360 2361 /* Just want the 7 most significant bits. */ 2362 crc >>= 25; 2363 2364 /* Set the corresponding bit in the hash table. */ 2365 mchash[crc >> 4] |= 1 << (crc & 0xf); 2366 2367 ETHER_NEXT_MULTI(step, enm); 2368 } 2369 2370 ifp->if_flags &= ~IFF_ALLMULTI; 2371 goto setit; 2372 2373 allmulti: 2374 ifp->if_flags |= IFF_ALLMULTI; 2375 sc->sc_rfcr |= RFCR_AAM; 2376 2377 setit: 2378 #define FILTER_EMIT(addr, data) \ 2379 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2380 delay(1); \ 2381 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2382 delay(1) 2383 2384 /* 2385 * Disable receive filter, and program the node address. 2386 */ 2387 cp = LLADDR(ifp->if_sadl); 2388 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2389 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2390 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2391 2392 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2393 /* 2394 * Program the multicast hash table. 2395 */ 2396 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2397 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2398 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2399 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2400 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2401 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2402 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2403 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2404 } 2405 #undef FILTER_EMIT 2406 2407 /* 2408 * Re-enable the receiver filter. 2409 */ 2410 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2411 } 2412 #endif /* ! DP83820 */ 2413 2414 /* 2415 * sip_dp83815_set_filter: 2416 * 2417 * Set up the receive filter. 2418 */ 2419 void 2420 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2421 { 2422 bus_space_tag_t st = sc->sc_st; 2423 bus_space_handle_t sh = sc->sc_sh; 2424 struct ethercom *ec = &sc->sc_ethercom; 2425 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2426 struct ether_multi *enm; 2427 u_int8_t *cp; 2428 struct ether_multistep step; 2429 u_int32_t crc, hash, slot, bit; 2430 #ifdef DP83820 2431 #define MCHASH_NWORDS 128 2432 #else 2433 #define MCHASH_NWORDS 32 2434 #endif /* DP83820 */ 2435 u_int16_t mchash[MCHASH_NWORDS]; 2436 int i; 2437 2438 /* 2439 * Initialize the prototype RFCR. 2440 * Enable the receive filter, and accept on 2441 * Perfect (destination address) Match 2442 * If IFF_BROADCAST, also accept all broadcast packets. 2443 * If IFF_PROMISC, accept all unicast packets (and later, set 2444 * IFF_ALLMULTI and accept all multicast, too). 2445 */ 2446 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2447 if (ifp->if_flags & IFF_BROADCAST) 2448 sc->sc_rfcr |= RFCR_AAB; 2449 if (ifp->if_flags & IFF_PROMISC) { 2450 sc->sc_rfcr |= RFCR_AAP; 2451 goto allmulti; 2452 } 2453 2454 #ifdef DP83820 2455 /* 2456 * Set up the DP83820 multicast address filter by passing all multicast 2457 * addresses through a CRC generator, and then using the high-order 2458 * 11 bits as an index into the 2048 bit multicast hash table. The 2459 * high-order 7 bits select the slot, while the low-order 4 bits 2460 * select the bit within the slot. Note that only the low 16-bits 2461 * of each filter word are used, and there are 128 filter words. 2462 */ 2463 #else 2464 /* 2465 * Set up the DP83815 multicast address filter by passing all multicast 2466 * addresses through a CRC generator, and then using the high-order 2467 * 9 bits as an index into the 512 bit multicast hash table. The 2468 * high-order 5 bits select the slot, while the low-order 4 bits 2469 * select the bit within the slot. Note that only the low 16-bits 2470 * of each filter word are used, and there are 32 filter words. 2471 */ 2472 #endif /* DP83820 */ 2473 2474 memset(mchash, 0, sizeof(mchash)); 2475 2476 ifp->if_flags &= ~IFF_ALLMULTI; 2477 ETHER_FIRST_MULTI(step, ec, enm); 2478 if (enm != NULL) { 2479 while (enm != NULL) { 2480 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2481 ETHER_ADDR_LEN)) { 2482 /* 2483 * We must listen to a range of multicast addresses. 2484 * For now, just accept all multicasts, rather than 2485 * trying to set only those filter bits needed to match 2486 * the range. (At this time, the only use of address 2487 * ranges is for IP multicast routing, for which the 2488 * range is big enough to require all bits set.) 2489 */ 2490 goto allmulti; 2491 } 2492 2493 #ifdef DP83820 2494 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2495 2496 /* Just want the 11 most significant bits. */ 2497 hash = crc >> 21; 2498 #else 2499 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2500 2501 /* Just want the 9 most significant bits. */ 2502 hash = crc >> 23; 2503 #endif /* DP83820 */ 2504 slot = hash >> 4; 2505 bit = hash & 0xf; 2506 2507 /* Set the corresponding bit in the hash table. */ 2508 mchash[slot] |= 1 << bit; 2509 2510 ETHER_NEXT_MULTI(step, enm); 2511 } 2512 2513 sc->sc_rfcr |= RFCR_MHEN; 2514 } 2515 goto setit; 2516 2517 allmulti: 2518 ifp->if_flags |= IFF_ALLMULTI; 2519 sc->sc_rfcr |= RFCR_AAM; 2520 2521 setit: 2522 #define FILTER_EMIT(addr, data) \ 2523 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2524 delay(1); \ 2525 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2526 delay(1); 2527 2528 /* 2529 * Disable receive filter, and program the node address. 2530 */ 2531 cp = LLADDR(ifp->if_sadl); 2532 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 2533 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 2534 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 2535 2536 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2537 /* 2538 * Program the multicast hash table. 2539 */ 2540 for (i = 0; i < MCHASH_NWORDS; i++) 2541 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 2542 mchash[i]); 2543 } 2544 #undef FILTER_EMIT 2545 #undef MCHASH_NWORDS 2546 2547 /* 2548 * Re-enable the receiver filter. 2549 */ 2550 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2551 } 2552 2553 #if defined(DP83820) 2554 /* 2555 * sip_dp83820_mii_readreg: [mii interface function] 2556 * 2557 * Read a PHY register on the MII of the DP83820. 2558 */ 2559 int 2560 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 2561 { 2562 2563 return (mii_bitbang_readreg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2564 phy, reg)); 2565 } 2566 2567 /* 2568 * sip_dp83820_mii_writereg: [mii interface function] 2569 * 2570 * Write a PHY register on the MII of the DP83820. 2571 */ 2572 void 2573 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 2574 { 2575 2576 mii_bitbang_writereg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2577 phy, reg, val); 2578 } 2579 2580 /* 2581 * sip_dp83815_mii_statchg: [mii interface function] 2582 * 2583 * Callback from MII layer when media changes. 2584 */ 2585 void 2586 SIP_DECL(dp83820_mii_statchg)(struct device *self) 2587 { 2588 struct sip_softc *sc = (struct sip_softc *) self; 2589 u_int32_t cfg; 2590 2591 /* 2592 * Update TXCFG for full-duplex operation. 2593 */ 2594 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2595 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2596 else 2597 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2598 2599 /* 2600 * Update RXCFG for full-duplex or loopback. 2601 */ 2602 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2603 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2604 sc->sc_rxcfg |= RXCFG_ATX; 2605 else 2606 sc->sc_rxcfg &= ~RXCFG_ATX; 2607 2608 /* 2609 * Update CFG for MII/GMII. 2610 */ 2611 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2612 cfg = sc->sc_cfg | CFG_MODE_1000; 2613 else 2614 cfg = sc->sc_cfg; 2615 2616 /* 2617 * XXX 802.3x flow control. 2618 */ 2619 2620 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 2621 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2622 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2623 } 2624 2625 /* 2626 * sip_dp83820_mii_bitbang_read: [mii bit-bang interface function] 2627 * 2628 * Read the MII serial port for the MII bit-bang module. 2629 */ 2630 u_int32_t 2631 SIP_DECL(dp83820_mii_bitbang_read)(struct device *self) 2632 { 2633 struct sip_softc *sc = (void *) self; 2634 2635 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 2636 } 2637 2638 /* 2639 * sip_dp83820_mii_bitbang_write: [mii big-bang interface function] 2640 * 2641 * Write the MII serial port for the MII bit-bang module. 2642 */ 2643 void 2644 SIP_DECL(dp83820_mii_bitbang_write)(struct device *self, u_int32_t val) 2645 { 2646 struct sip_softc *sc = (void *) self; 2647 2648 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 2649 } 2650 #else /* ! DP83820 */ 2651 /* 2652 * sip_sis900_mii_readreg: [mii interface function] 2653 * 2654 * Read a PHY register on the MII. 2655 */ 2656 int 2657 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 2658 { 2659 struct sip_softc *sc = (struct sip_softc *) self; 2660 u_int32_t enphy; 2661 2662 /* 2663 * The SiS 900 has only an internal PHY on the MII. Only allow 2664 * MII address 0. 2665 */ 2666 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 2667 return (0); 2668 2669 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2670 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 2671 ENPHY_RWCMD | ENPHY_ACCESS); 2672 do { 2673 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2674 } while (enphy & ENPHY_ACCESS); 2675 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 2676 } 2677 2678 /* 2679 * sip_sis900_mii_writereg: [mii interface function] 2680 * 2681 * Write a PHY register on the MII. 2682 */ 2683 void 2684 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 2685 { 2686 struct sip_softc *sc = (struct sip_softc *) self; 2687 u_int32_t enphy; 2688 2689 /* 2690 * The SiS 900 has only an internal PHY on the MII. Only allow 2691 * MII address 0. 2692 */ 2693 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 2694 return; 2695 2696 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2697 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 2698 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 2699 do { 2700 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2701 } while (enphy & ENPHY_ACCESS); 2702 } 2703 2704 /* 2705 * sip_sis900_mii_statchg: [mii interface function] 2706 * 2707 * Callback from MII layer when media changes. 2708 */ 2709 void 2710 SIP_DECL(sis900_mii_statchg)(struct device *self) 2711 { 2712 struct sip_softc *sc = (struct sip_softc *) self; 2713 u_int32_t flowctl; 2714 2715 /* 2716 * Update TXCFG for full-duplex operation. 2717 */ 2718 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2719 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2720 else 2721 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2722 2723 /* 2724 * Update RXCFG for full-duplex or loopback. 2725 */ 2726 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2727 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2728 sc->sc_rxcfg |= RXCFG_ATX; 2729 else 2730 sc->sc_rxcfg &= ~RXCFG_ATX; 2731 2732 /* 2733 * Update IMR for use of 802.3x flow control. 2734 */ 2735 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 2736 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 2737 flowctl = FLOWCTL_FLOWEN; 2738 } else { 2739 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 2740 flowctl = 0; 2741 } 2742 2743 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2744 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2745 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 2746 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 2747 } 2748 2749 /* 2750 * sip_dp83815_mii_readreg: [mii interface function] 2751 * 2752 * Read a PHY register on the MII. 2753 */ 2754 int 2755 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 2756 { 2757 struct sip_softc *sc = (struct sip_softc *) self; 2758 u_int32_t val; 2759 2760 /* 2761 * The DP83815 only has an internal PHY. Only allow 2762 * MII address 0. 2763 */ 2764 if (phy != 0) 2765 return (0); 2766 2767 /* 2768 * Apparently, after a reset, the DP83815 can take a while 2769 * to respond. During this recovery period, the BMSR returns 2770 * a value of 0. Catch this -- it's not supposed to happen 2771 * (the BMSR has some hardcoded-to-1 bits), and wait for the 2772 * PHY to come back to life. 2773 * 2774 * This works out because the BMSR is the first register 2775 * read during the PHY probe process. 2776 */ 2777 do { 2778 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 2779 } while (reg == MII_BMSR && val == 0); 2780 2781 return (val & 0xffff); 2782 } 2783 2784 /* 2785 * sip_dp83815_mii_writereg: [mii interface function] 2786 * 2787 * Write a PHY register to the MII. 2788 */ 2789 void 2790 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 2791 { 2792 struct sip_softc *sc = (struct sip_softc *) self; 2793 2794 /* 2795 * The DP83815 only has an internal PHY. Only allow 2796 * MII address 0. 2797 */ 2798 if (phy != 0) 2799 return; 2800 2801 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 2802 } 2803 2804 /* 2805 * sip_dp83815_mii_statchg: [mii interface function] 2806 * 2807 * Callback from MII layer when media changes. 2808 */ 2809 void 2810 SIP_DECL(dp83815_mii_statchg)(struct device *self) 2811 { 2812 struct sip_softc *sc = (struct sip_softc *) self; 2813 2814 /* 2815 * Update TXCFG for full-duplex operation. 2816 */ 2817 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2818 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2819 else 2820 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2821 2822 /* 2823 * Update RXCFG for full-duplex or loopback. 2824 */ 2825 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2826 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2827 sc->sc_rxcfg |= RXCFG_ATX; 2828 else 2829 sc->sc_rxcfg &= ~RXCFG_ATX; 2830 2831 /* 2832 * XXX 802.3x flow control. 2833 */ 2834 2835 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2836 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2837 } 2838 #endif /* DP83820 */ 2839 2840 #if defined(DP83820) 2841 void 2842 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, u_int8_t *enaddr) 2843 { 2844 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 2845 u_int8_t cksum, *e, match; 2846 int i; 2847 2848 /* 2849 * EEPROM data format for the DP83820 can be found in 2850 * the DP83820 manual, section 4.2.4. 2851 */ 2852 2853 SIP_DECL(read_eeprom)(sc, 0, 2854 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 2855 2856 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 2857 match = ~(match - 1); 2858 2859 cksum = 0x55; 2860 e = (u_int8_t *) eeprom_data; 2861 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 2862 cksum += *e++; 2863 2864 if (cksum != match) 2865 printf("%s: Checksum (%x) mismatch (%x)", 2866 sc->sc_dev.dv_xname, cksum, match); 2867 2868 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 2869 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 2870 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 2871 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 2872 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 2873 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 2874 2875 /* Get the GPIOR bits. */ 2876 sc->sc_gpior = eeprom_data[0x04]; 2877 2878 /* Get various CFG related bits. */ 2879 if ((eeprom_data[0x05] >> 0) & 1) 2880 sc->sc_cfg |= CFG_EXT_125; 2881 if ((eeprom_data[0x05] >> 9) & 1) 2882 sc->sc_cfg |= CFG_TBI_EN; 2883 } 2884 #else /* ! DP83820 */ 2885 void 2886 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, u_int8_t *enaddr) 2887 { 2888 u_int16_t myea[ETHER_ADDR_LEN / 2]; 2889 2890 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 2891 sizeof(myea) / sizeof(myea[0]), myea); 2892 2893 enaddr[0] = myea[0] & 0xff; 2894 enaddr[1] = myea[0] >> 8; 2895 enaddr[2] = myea[1] & 0xff; 2896 enaddr[3] = myea[1] >> 8; 2897 enaddr[4] = myea[2] & 0xff; 2898 enaddr[5] = myea[2] >> 8; 2899 } 2900 2901 /* Table and macro to bit-reverse an octet. */ 2902 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 2903 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 2904 2905 void 2906 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, u_int8_t *enaddr) 2907 { 2908 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 2909 u_int8_t cksum, *e, match; 2910 int i; 2911 2912 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 2913 sizeof(eeprom_data[0]), eeprom_data); 2914 2915 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 2916 match = ~(match - 1); 2917 2918 cksum = 0x55; 2919 e = (u_int8_t *) eeprom_data; 2920 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 2921 cksum += *e++; 2922 } 2923 if (cksum != match) { 2924 printf("%s: Checksum (%x) mismatch (%x)", 2925 sc->sc_dev.dv_xname, cksum, match); 2926 } 2927 2928 /* 2929 * Unrolled because it makes slightly more sense this way. 2930 * The DP83815 stores the MAC address in bit 0 of word 6 2931 * through bit 15 of word 8. 2932 */ 2933 ea = &eeprom_data[6]; 2934 enaddr[0] = ((*ea & 0x1) << 7); 2935 ea++; 2936 enaddr[0] |= ((*ea & 0xFE00) >> 9); 2937 enaddr[1] = ((*ea & 0x1FE) >> 1); 2938 enaddr[2] = ((*ea & 0x1) << 7); 2939 ea++; 2940 enaddr[2] |= ((*ea & 0xFE00) >> 9); 2941 enaddr[3] = ((*ea & 0x1FE) >> 1); 2942 enaddr[4] = ((*ea & 0x1) << 7); 2943 ea++; 2944 enaddr[4] |= ((*ea & 0xFE00) >> 9); 2945 enaddr[5] = ((*ea & 0x1FE) >> 1); 2946 2947 /* 2948 * In case that's not weird enough, we also need to reverse 2949 * the bits in each byte. This all actually makes more sense 2950 * if you think about the EEPROM storage as an array of bits 2951 * being shifted into bytes, but that's not how we're looking 2952 * at it here... 2953 */ 2954 for (i = 0; i < 6 ;i++) 2955 enaddr[i] = bbr(enaddr[i]); 2956 } 2957 #endif /* DP83820 */ 2958 2959 /* 2960 * sip_mediastatus: [ifmedia interface function] 2961 * 2962 * Get the current interface media status. 2963 */ 2964 void 2965 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 2966 { 2967 struct sip_softc *sc = ifp->if_softc; 2968 2969 mii_pollstat(&sc->sc_mii); 2970 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2971 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2972 } 2973 2974 /* 2975 * sip_mediachange: [ifmedia interface function] 2976 * 2977 * Set hardware to newly-selected media. 2978 */ 2979 int 2980 SIP_DECL(mediachange)(struct ifnet *ifp) 2981 { 2982 struct sip_softc *sc = ifp->if_softc; 2983 2984 if (ifp->if_flags & IFF_UP) 2985 mii_mediachg(&sc->sc_mii); 2986 return (0); 2987 } 2988
Indexes created Tue Sep 30 11:09:46 GMT 2025