if_sip.c revision 1.40.2.1
1 /* $NetBSD: if_sip.c,v 1.40.2.1 2001/08/03 04:13:15 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Support the 10-bit interface on the DP83820 (for fiber). 80 * 81 * - Reduce the interrupt load. 82 */ 83 84 #include "bpfilter.h" 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/callout.h> 89 #include <sys/mbuf.h> 90 #include <sys/malloc.h> 91 #include <sys/kernel.h> 92 #include <sys/socket.h> 93 #include <sys/ioctl.h> 94 #include <sys/errno.h> 95 #include <sys/device.h> 96 #include <sys/queue.h> 97 98 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 99 100 #include <net/if.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 #include <net/if_ether.h> 104 105 #if NBPFILTER > 0 106 #include <net/bpf.h> 107 #endif 108 109 #include <machine/bus.h> 110 #include <machine/intr.h> 111 #include <machine/endian.h> 112 113 #include <dev/mii/mii.h> 114 #include <dev/mii/miivar.h> 115 #ifdef DP83820 116 #include <dev/mii/mii_bitbang.h> 117 #endif /* DP83820 */ 118 119 #include <dev/pci/pcireg.h> 120 #include <dev/pci/pcivar.h> 121 #include <dev/pci/pcidevs.h> 122 123 #include <dev/pci/if_sipreg.h> 124 125 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 126 #define SIP_DECL(x) __CONCAT(gsip_,x) 127 #else /* SiS900 and DP83815 */ 128 #define SIP_DECL(x) __CONCAT(sip_,x) 129 #endif 130 131 #define SIP_STR(x) __STRING(SIP_DECL(x)) 132 133 /* 134 * Transmit descriptor list size. This is arbitrary, but allocate 135 * enough descriptors for 128 pending transmissions, and 8 segments 136 * per packet. This MUST work out to a power of 2. 137 */ 138 #define SIP_NTXSEGS 8 139 140 #define SIP_TXQUEUELEN 256 141 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS) 142 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 143 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 144 145 /* 146 * Receive descriptor list size. We have one Rx buffer per incoming 147 * packet, so this logic is a little simpler. 148 * 149 * Actually, on the DP83820, we allow the packet to consume more than 150 * one buffer, in order to support jumbo Ethernet frames. In that 151 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 152 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 153 * so we'd better be quick about handling receive interrupts. 154 */ 155 #if defined(DP83820) 156 #define SIP_NRXDESC 256 157 #else 158 #define SIP_NRXDESC 128 159 #endif /* DP83820 */ 160 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 161 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 162 163 /* 164 * Control structures are DMA'd to the SiS900 chip. We allocate them in 165 * a single clump that maps to a single DMA segment to make several things 166 * easier. 167 */ 168 struct sip_control_data { 169 /* 170 * The transmit descriptors. 171 */ 172 struct sip_desc scd_txdescs[SIP_NTXDESC]; 173 174 /* 175 * The receive descriptors. 176 */ 177 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 178 }; 179 180 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 181 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 182 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 183 184 /* 185 * Software state for transmit jobs. 186 */ 187 struct sip_txsoft { 188 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 189 bus_dmamap_t txs_dmamap; /* our DMA map */ 190 int txs_firstdesc; /* first descriptor in packet */ 191 int txs_lastdesc; /* last descriptor in packet */ 192 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 193 }; 194 195 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 196 197 /* 198 * Software state for receive jobs. 199 */ 200 struct sip_rxsoft { 201 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 202 bus_dmamap_t rxs_dmamap; /* our DMA map */ 203 }; 204 205 /* 206 * Software state per device. 207 */ 208 struct sip_softc { 209 struct device sc_dev; /* generic device information */ 210 bus_space_tag_t sc_st; /* bus space tag */ 211 bus_space_handle_t sc_sh; /* bus space handle */ 212 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 213 struct ethercom sc_ethercom; /* ethernet common data */ 214 void *sc_sdhook; /* shutdown hook */ 215 216 const struct sip_product *sc_model; /* which model are we? */ 217 218 void *sc_ih; /* interrupt cookie */ 219 220 struct mii_data sc_mii; /* MII/media information */ 221 222 struct callout sc_tick_ch; /* tick callout */ 223 224 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 225 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 226 227 /* 228 * Software state for transmit and receive descriptors. 229 */ 230 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 231 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 232 233 /* 234 * Control data structures. 235 */ 236 struct sip_control_data *sc_control_data; 237 #define sc_txdescs sc_control_data->scd_txdescs 238 #define sc_rxdescs sc_control_data->scd_rxdescs 239 240 #ifdef SIP_EVENT_COUNTERS 241 /* 242 * Event counters. 243 */ 244 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 245 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 246 struct evcnt sc_ev_txintr; /* Tx interrupts */ 247 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 248 #ifdef DP83820 249 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 250 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 251 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 252 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 253 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 254 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 255 #endif /* DP83820 */ 256 #endif /* SIP_EVENT_COUNTERS */ 257 258 u_int32_t sc_txcfg; /* prototype TXCFG register */ 259 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 260 u_int32_t sc_imr; /* prototype IMR register */ 261 u_int32_t sc_rfcr; /* prototype RFCR register */ 262 263 u_int32_t sc_cfg; /* prototype CFG register */ 264 265 #ifdef DP83820 266 u_int32_t sc_gpior; /* prototype GPIOR register */ 267 #endif /* DP83820 */ 268 269 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 270 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 271 272 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 273 274 int sc_flags; /* misc. flags; see below */ 275 276 int sc_txfree; /* number of free Tx descriptors */ 277 int sc_txnext; /* next ready Tx descriptor */ 278 279 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 280 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 281 282 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 283 #if defined(DP83820) 284 int sc_rxdiscard; 285 int sc_rxlen; 286 struct mbuf *sc_rxhead; 287 struct mbuf *sc_rxtail; 288 struct mbuf **sc_rxtailp; 289 #endif /* DP83820 */ 290 }; 291 292 /* sc_flags */ 293 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 294 295 #ifdef DP83820 296 #define SIP_RXCHAIN_RESET(sc) \ 297 do { \ 298 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 299 *(sc)->sc_rxtailp = NULL; \ 300 (sc)->sc_rxlen = 0; \ 301 } while (/*CONSTCOND*/0) 302 303 #define SIP_RXCHAIN_LINK(sc, m) \ 304 do { \ 305 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 306 (sc)->sc_rxtailp = &(m)->m_next; \ 307 } while (/*CONSTCOND*/0) 308 #endif /* DP83820 */ 309 310 #ifdef SIP_EVENT_COUNTERS 311 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 312 #else 313 #define SIP_EVCNT_INCR(ev) /* nothing */ 314 #endif 315 316 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 317 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 318 319 #define SIP_CDTXSYNC(sc, x, n, ops) \ 320 do { \ 321 int __x, __n; \ 322 \ 323 __x = (x); \ 324 __n = (n); \ 325 \ 326 /* If it will wrap around, sync to the end of the ring. */ \ 327 if ((__x + __n) > SIP_NTXDESC) { \ 328 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 329 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 330 (SIP_NTXDESC - __x), (ops)); \ 331 __n -= (SIP_NTXDESC - __x); \ 332 __x = 0; \ 333 } \ 334 \ 335 /* Now sync whatever is left. */ \ 336 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 337 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 338 } while (0) 339 340 #define SIP_CDRXSYNC(sc, x, ops) \ 341 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 342 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 343 344 #ifdef DP83820 345 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 346 #define SIP_RXBUF_LEN (MCLBYTES - 4) 347 #else 348 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 349 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 350 #endif 351 #define SIP_INIT_RXDESC(sc, x) \ 352 do { \ 353 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 354 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 355 \ 356 __sipd->sipd_link = \ 357 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 358 __sipd->sipd_bufptr = \ 359 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 360 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 361 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 362 SIP_INIT_RXDESC_EXTSTS \ 363 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 364 } while (0) 365 366 #define SIP_TIMEOUT 1000 367 368 void SIP_DECL(start)(struct ifnet *); 369 void SIP_DECL(watchdog)(struct ifnet *); 370 int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 371 int SIP_DECL(init)(struct ifnet *); 372 void SIP_DECL(stop)(struct ifnet *, int); 373 374 void SIP_DECL(shutdown)(void *); 375 376 void SIP_DECL(reset)(struct sip_softc *); 377 void SIP_DECL(rxdrain)(struct sip_softc *); 378 int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 379 void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, u_int16_t *); 380 void SIP_DECL(tick)(void *); 381 382 #if !defined(DP83820) 383 void SIP_DECL(sis900_set_filter)(struct sip_softc *); 384 #endif /* ! DP83820 */ 385 void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 386 387 #if defined(DP83820) 388 void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, u_int8_t *); 389 #else 390 void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, u_int8_t *); 391 void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, u_int8_t *); 392 #endif /* DP83820 */ 393 394 int SIP_DECL(intr)(void *); 395 void SIP_DECL(txintr)(struct sip_softc *); 396 void SIP_DECL(rxintr)(struct sip_softc *); 397 398 #if defined(DP83820) 399 int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 400 void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 401 void SIP_DECL(dp83820_mii_statchg)(struct device *); 402 #else 403 int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 404 void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 405 void SIP_DECL(sis900_mii_statchg)(struct device *); 406 407 int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 408 void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 409 void SIP_DECL(dp83815_mii_statchg)(struct device *); 410 #endif /* DP83820 */ 411 412 int SIP_DECL(mediachange)(struct ifnet *); 413 void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 414 415 int SIP_DECL(match)(struct device *, struct cfdata *, void *); 416 void SIP_DECL(attach)(struct device *, struct device *, void *); 417 418 int SIP_DECL(copy_small) = 0; 419 420 struct cfattach SIP_DECL(ca) = { 421 sizeof(struct sip_softc), SIP_DECL(match), SIP_DECL(attach), 422 }; 423 424 /* 425 * Descriptions of the variants of the SiS900. 426 */ 427 struct sip_variant { 428 int (*sipv_mii_readreg)(struct device *, int, int); 429 void (*sipv_mii_writereg)(struct device *, int, int, int); 430 void (*sipv_mii_statchg)(struct device *); 431 void (*sipv_set_filter)(struct sip_softc *); 432 void (*sipv_read_macaddr)(struct sip_softc *, u_int8_t *); 433 }; 434 435 #if defined(DP83820) 436 u_int32_t SIP_DECL(dp83820_mii_bitbang_read)(struct device *); 437 void SIP_DECL(dp83820_mii_bitbang_write)(struct device *, u_int32_t); 438 439 const struct mii_bitbang_ops SIP_DECL(dp83820_mii_bitbang_ops) = { 440 SIP_DECL(dp83820_mii_bitbang_read), 441 SIP_DECL(dp83820_mii_bitbang_write), 442 { 443 EROMAR_MDIO, /* MII_BIT_MDO */ 444 EROMAR_MDIO, /* MII_BIT_MDI */ 445 EROMAR_MDC, /* MII_BIT_MDC */ 446 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 447 0, /* MII_BIT_DIR_PHY_HOST */ 448 } 449 }; 450 #endif /* DP83820 */ 451 452 #if defined(DP83820) 453 const struct sip_variant SIP_DECL(variant_dp83820) = { 454 SIP_DECL(dp83820_mii_readreg), 455 SIP_DECL(dp83820_mii_writereg), 456 SIP_DECL(dp83820_mii_statchg), 457 SIP_DECL(dp83815_set_filter), 458 SIP_DECL(dp83820_read_macaddr), 459 }; 460 #else 461 const struct sip_variant SIP_DECL(variant_sis900) = { 462 SIP_DECL(sis900_mii_readreg), 463 SIP_DECL(sis900_mii_writereg), 464 SIP_DECL(sis900_mii_statchg), 465 SIP_DECL(sis900_set_filter), 466 SIP_DECL(sis900_read_macaddr), 467 }; 468 469 const struct sip_variant SIP_DECL(variant_dp83815) = { 470 SIP_DECL(dp83815_mii_readreg), 471 SIP_DECL(dp83815_mii_writereg), 472 SIP_DECL(dp83815_mii_statchg), 473 SIP_DECL(dp83815_set_filter), 474 SIP_DECL(dp83815_read_macaddr), 475 }; 476 #endif /* DP83820 */ 477 478 /* 479 * Devices supported by this driver. 480 */ 481 const struct sip_product { 482 pci_vendor_id_t sip_vendor; 483 pci_product_id_t sip_product; 484 const char *sip_name; 485 const struct sip_variant *sip_variant; 486 } SIP_DECL(products)[] = { 487 #if defined(DP83820) 488 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 489 "NatSemi DP83820 Gigabit Ethernet", 490 &SIP_DECL(variant_dp83820) }, 491 #else 492 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 493 "SiS 900 10/100 Ethernet", 494 &SIP_DECL(variant_sis900) }, 495 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 496 "SiS 7016 10/100 Ethernet", 497 &SIP_DECL(variant_sis900) }, 498 499 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 500 "NatSemi DP83815 10/100 Ethernet", 501 &SIP_DECL(variant_dp83815) }, 502 #endif /* DP83820 */ 503 504 { 0, 0, 505 NULL, 506 NULL }, 507 }; 508 509 static const struct sip_product * 510 SIP_DECL(lookup)(const struct pci_attach_args *pa) 511 { 512 const struct sip_product *sip; 513 514 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 515 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 516 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 517 return (sip); 518 } 519 return (NULL); 520 } 521 522 int 523 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 524 { 525 struct pci_attach_args *pa = aux; 526 527 if (SIP_DECL(lookup)(pa) != NULL) 528 return (1); 529 530 return (0); 531 } 532 533 void 534 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 535 { 536 struct sip_softc *sc = (struct sip_softc *) self; 537 struct pci_attach_args *pa = aux; 538 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 539 pci_chipset_tag_t pc = pa->pa_pc; 540 pci_intr_handle_t ih; 541 const char *intrstr = NULL; 542 bus_space_tag_t iot, memt; 543 bus_space_handle_t ioh, memh; 544 bus_dma_segment_t seg; 545 int ioh_valid, memh_valid; 546 int i, rseg, error; 547 const struct sip_product *sip; 548 pcireg_t pmode; 549 u_int8_t enaddr[ETHER_ADDR_LEN]; 550 int pmreg; 551 #ifdef DP83820 552 pcireg_t memtype; 553 u_int32_t reg; 554 #endif /* DP83820 */ 555 556 callout_init(&sc->sc_tick_ch); 557 558 sip = SIP_DECL(lookup)(pa); 559 if (sip == NULL) { 560 printf("\n"); 561 panic(SIP_STR(attach) ": impossible"); 562 } 563 564 printf(": %s\n", sip->sip_name); 565 566 sc->sc_model = sip; 567 568 /* 569 * Map the device. 570 */ 571 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 572 PCI_MAPREG_TYPE_IO, 0, 573 &iot, &ioh, NULL, NULL) == 0); 574 #ifdef DP83820 575 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 576 switch (memtype) { 577 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 578 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 579 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 580 memtype, 0, &memt, &memh, NULL, NULL) == 0); 581 break; 582 default: 583 memh_valid = 0; 584 } 585 #else 586 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 587 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 588 &memt, &memh, NULL, NULL) == 0); 589 #endif /* DP83820 */ 590 591 if (memh_valid) { 592 printf("%s: using memory mapped registers\n", sc->sc_dev.dv_xname); 593 sc->sc_st = memt; 594 sc->sc_sh = memh; 595 } else if (ioh_valid) { 596 printf("%s: using I/O mapped registers\n", sc->sc_dev.dv_xname); 597 sc->sc_st = iot; 598 sc->sc_sh = ioh; 599 } else { 600 printf("%s: unable to map device registers\n", 601 sc->sc_dev.dv_xname); 602 return; 603 } 604 605 sc->sc_dmat = pa->pa_dmat; 606 607 /* Enable bus mastering. */ 608 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 609 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 610 PCI_COMMAND_MASTER_ENABLE); 611 612 /* Get it out of power save mode if needed. */ 613 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 614 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 615 if (pmode == 3) { 616 /* 617 * The card has lost all configuration data in 618 * this state, so punt. 619 */ 620 printf("%s: unable to wake up from power state D3\n", 621 sc->sc_dev.dv_xname); 622 return; 623 } 624 if (pmode != 0) { 625 printf("%s: waking up from power state D%d\n", 626 sc->sc_dev.dv_xname, pmode); 627 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 628 } 629 } 630 631 /* 632 * Map and establish our interrupt. 633 */ 634 if (pci_intr_map(pa, &ih)) { 635 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 636 return; 637 } 638 intrstr = pci_intr_string(pc, ih); 639 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 640 if (sc->sc_ih == NULL) { 641 printf("%s: unable to establish interrupt", 642 sc->sc_dev.dv_xname); 643 if (intrstr != NULL) 644 printf(" at %s", intrstr); 645 printf("\n"); 646 return; 647 } 648 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 649 650 SIMPLEQ_INIT(&sc->sc_txfreeq); 651 SIMPLEQ_INIT(&sc->sc_txdirtyq); 652 653 /* 654 * Allocate the control data structures, and create and load the 655 * DMA map for it. 656 */ 657 if ((error = bus_dmamem_alloc(sc->sc_dmat, 658 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 659 0)) != 0) { 660 printf("%s: unable to allocate control data, error = %d\n", 661 sc->sc_dev.dv_xname, error); 662 goto fail_0; 663 } 664 665 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 666 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 667 BUS_DMA_COHERENT)) != 0) { 668 printf("%s: unable to map control data, error = %d\n", 669 sc->sc_dev.dv_xname, error); 670 goto fail_1; 671 } 672 673 if ((error = bus_dmamap_create(sc->sc_dmat, 674 sizeof(struct sip_control_data), 1, 675 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 676 printf("%s: unable to create control data DMA map, " 677 "error = %d\n", sc->sc_dev.dv_xname, error); 678 goto fail_2; 679 } 680 681 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 682 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 683 0)) != 0) { 684 printf("%s: unable to load control data DMA map, error = %d\n", 685 sc->sc_dev.dv_xname, error); 686 goto fail_3; 687 } 688 689 /* 690 * Create the transmit buffer DMA maps. 691 */ 692 for (i = 0; i < SIP_TXQUEUELEN; i++) { 693 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 694 SIP_NTXSEGS, MCLBYTES, 0, 0, 695 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 696 printf("%s: unable to create tx DMA map %d, " 697 "error = %d\n", sc->sc_dev.dv_xname, i, error); 698 goto fail_4; 699 } 700 } 701 702 /* 703 * Create the receive buffer DMA maps. 704 */ 705 for (i = 0; i < SIP_NRXDESC; i++) { 706 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 707 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 708 printf("%s: unable to create rx DMA map %d, " 709 "error = %d\n", sc->sc_dev.dv_xname, i, error); 710 goto fail_5; 711 } 712 sc->sc_rxsoft[i].rxs_mbuf = NULL; 713 } 714 715 /* 716 * Reset the chip to a known state. 717 */ 718 SIP_DECL(reset)(sc); 719 720 /* 721 * Read the Ethernet address from the EEPROM. This might 722 * also fetch other stuff from the EEPROM and stash it 723 * in the softc. 724 */ 725 sc->sc_cfg = 0; 726 (*sip->sip_variant->sipv_read_macaddr)(sc, enaddr); 727 728 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 729 ether_sprintf(enaddr)); 730 731 /* 732 * Initialize the configuration register: aggressive PCI 733 * bus request algorithm, default backoff, default OW timer, 734 * default parity error detection. 735 * 736 * NOTE: "Big endian mode" is useless on the SiS900 and 737 * friends -- it affects packet data, not descriptors. 738 */ 739 #ifdef DP83820 740 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 741 if (reg & CFG_PCI64_DET) { 742 printf("%s: 64-bit PCI slot detected\n", sc->sc_dev.dv_xname); 743 /* 744 * XXX Need some PCI flags indicating support for 745 * XXX 64-bit addressing (SAC or DAC) and 64-bit 746 * XXX data path. 747 */ 748 } 749 if (sc->sc_cfg & (CFG_TBI_EN|CFG_EXT_125)) { 750 const char *sep = ""; 751 printf("%s: using ", sc->sc_dev.dv_xname); 752 if (sc->sc_cfg & CFG_EXT_125) { 753 printf("%s125MHz clock", sep); 754 sep = ", "; 755 } 756 if (sc->sc_cfg & CFG_TBI_EN) { 757 printf("%sten-bit interface", sep); 758 sep = ", "; 759 } 760 printf("\n"); 761 } 762 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0) 763 sc->sc_cfg |= CFG_MRM_DIS; 764 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 765 sc->sc_cfg |= CFG_MWI_DIS; 766 767 /* 768 * Use the extended descriptor format on the DP83820. This 769 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 770 * checksumming. 771 */ 772 sc->sc_cfg |= CFG_EXTSTS_EN; 773 #endif /* DP83820 */ 774 775 /* 776 * Initialize our media structures and probe the MII. 777 */ 778 sc->sc_mii.mii_ifp = ifp; 779 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 780 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 781 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 782 ifmedia_init(&sc->sc_mii.mii_media, 0, SIP_DECL(mediachange), 783 SIP_DECL(mediastatus)); 784 #ifdef DP83820 785 if (sc->sc_cfg & CFG_TBI_EN) { 786 /* Using ten-bit interface. */ 787 printf("%s: TBI -- FIXME\n", sc->sc_dev.dv_xname); 788 } else { 789 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 790 MII_OFFSET_ANY, 0); 791 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 792 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 793 0, NULL); 794 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 795 } else 796 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 797 } 798 #else 799 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 800 MII_OFFSET_ANY, 0); 801 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 802 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 803 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 804 } else 805 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 806 #endif /* DP83820 */ 807 808 ifp = &sc->sc_ethercom.ec_if; 809 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 810 ifp->if_softc = sc; 811 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 812 ifp->if_ioctl = SIP_DECL(ioctl); 813 ifp->if_start = SIP_DECL(start); 814 ifp->if_watchdog = SIP_DECL(watchdog); 815 ifp->if_init = SIP_DECL(init); 816 ifp->if_stop = SIP_DECL(stop); 817 IFQ_SET_READY(&ifp->if_snd); 818 819 /* 820 * We can support 802.1Q VLAN-sized frames. 821 */ 822 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 823 824 #ifdef DP83820 825 /* 826 * And the DP83820 can do VLAN tagging in hardware, and 827 * support the jumbo Ethernet MTU. 828 */ 829 sc->sc_ethercom.ec_capabilities |= 830 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 831 832 /* 833 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 834 * in hardware. 835 */ 836 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 837 IFCAP_CSUM_UDPv4; 838 #endif /* DP83820 */ 839 840 /* 841 * Attach the interface. 842 */ 843 if_attach(ifp); 844 ether_ifattach(ifp, enaddr); 845 846 #ifdef SIP_EVENT_COUNTERS 847 /* 848 * Attach event counters. 849 */ 850 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 851 NULL, sc->sc_dev.dv_xname, "txsstall"); 852 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 853 NULL, sc->sc_dev.dv_xname, "txdstall"); 854 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 855 NULL, sc->sc_dev.dv_xname, "txintr"); 856 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 857 NULL, sc->sc_dev.dv_xname, "rxintr"); 858 #ifdef DP83820 859 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 860 NULL, sc->sc_dev.dv_xname, "rxipsum"); 861 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 862 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 863 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 864 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 865 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 866 NULL, sc->sc_dev.dv_xname, "txipsum"); 867 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 868 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 869 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 870 NULL, sc->sc_dev.dv_xname, "txudpsum"); 871 #endif /* DP83820 */ 872 #endif /* SIP_EVENT_COUNTERS */ 873 874 /* 875 * Make sure the interface is shutdown during reboot. 876 */ 877 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 878 if (sc->sc_sdhook == NULL) 879 printf("%s: WARNING: unable to establish shutdown hook\n", 880 sc->sc_dev.dv_xname); 881 return; 882 883 /* 884 * Free any resources we've allocated during the failed attach 885 * attempt. Do this in reverse order and fall through. 886 */ 887 fail_5: 888 for (i = 0; i < SIP_NRXDESC; i++) { 889 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 890 bus_dmamap_destroy(sc->sc_dmat, 891 sc->sc_rxsoft[i].rxs_dmamap); 892 } 893 fail_4: 894 for (i = 0; i < SIP_TXQUEUELEN; i++) { 895 if (sc->sc_txsoft[i].txs_dmamap != NULL) 896 bus_dmamap_destroy(sc->sc_dmat, 897 sc->sc_txsoft[i].txs_dmamap); 898 } 899 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 900 fail_3: 901 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 902 fail_2: 903 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 904 sizeof(struct sip_control_data)); 905 fail_1: 906 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 907 fail_0: 908 return; 909 } 910 911 /* 912 * sip_shutdown: 913 * 914 * Make sure the interface is stopped at reboot time. 915 */ 916 void 917 SIP_DECL(shutdown)(void *arg) 918 { 919 struct sip_softc *sc = arg; 920 921 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 922 } 923 924 /* 925 * sip_start: [ifnet interface function] 926 * 927 * Start packet transmission on the interface. 928 */ 929 void 930 SIP_DECL(start)(struct ifnet *ifp) 931 { 932 struct sip_softc *sc = ifp->if_softc; 933 struct mbuf *m0, *m; 934 struct sip_txsoft *txs; 935 bus_dmamap_t dmamap; 936 int error, firsttx, nexttx, lasttx, ofree, seg; 937 #ifdef DP83820 938 u_int32_t extsts; 939 #endif 940 941 /* 942 * If we've been told to pause, don't transmit any more packets. 943 */ 944 if (sc->sc_flags & SIPF_PAUSED) 945 ifp->if_flags |= IFF_OACTIVE; 946 947 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 948 return; 949 950 /* 951 * Remember the previous number of free descriptors and 952 * the first descriptor we'll use. 953 */ 954 ofree = sc->sc_txfree; 955 firsttx = sc->sc_txnext; 956 957 /* 958 * Loop through the send queue, setting up transmit descriptors 959 * until we drain the queue, or use up all available transmit 960 * descriptors. 961 */ 962 for (;;) { 963 /* Get a work queue entry. */ 964 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 965 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 966 break; 967 } 968 969 /* 970 * Grab a packet off the queue. 971 */ 972 IFQ_POLL(&ifp->if_snd, m0); 973 if (m0 == NULL) 974 break; 975 #ifndef DP83820 976 m = NULL; 977 #endif 978 979 dmamap = txs->txs_dmamap; 980 981 #ifdef DP83820 982 /* 983 * Load the DMA map. If this fails, the packet either 984 * didn't fit in the allotted number of segments, or we 985 * were short on resources. For the too-many-segments 986 * case, we simply report an error and drop the packet, 987 * since we can't sanely copy a jumbo packet to a single 988 * buffer. 989 */ 990 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 991 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 992 if (error) { 993 if (error == EFBIG) { 994 printf("%s: Tx packet consumes too many " 995 "DMA segments, dropping...\n", 996 sc->sc_dev.dv_xname); 997 IFQ_DEQUEUE(&ifp->if_snd, m0); 998 m_freem(m0); 999 continue; 1000 } 1001 /* 1002 * Short on resources, just stop for now. 1003 */ 1004 break; 1005 } 1006 #else /* DP83820 */ 1007 /* 1008 * Load the DMA map. If this fails, the packet either 1009 * didn't fit in the alloted number of segments, or we 1010 * were short on resources. In this case, we'll copy 1011 * and try again. 1012 */ 1013 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1014 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1015 MGETHDR(m, M_DONTWAIT, MT_DATA); 1016 if (m == NULL) { 1017 printf("%s: unable to allocate Tx mbuf\n", 1018 sc->sc_dev.dv_xname); 1019 break; 1020 } 1021 if (m0->m_pkthdr.len > MHLEN) { 1022 MCLGET(m, M_DONTWAIT); 1023 if ((m->m_flags & M_EXT) == 0) { 1024 printf("%s: unable to allocate Tx " 1025 "cluster\n", sc->sc_dev.dv_xname); 1026 m_freem(m); 1027 break; 1028 } 1029 } 1030 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1031 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1032 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1033 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1034 if (error) { 1035 printf("%s: unable to load Tx buffer, " 1036 "error = %d\n", sc->sc_dev.dv_xname, error); 1037 break; 1038 } 1039 } 1040 #endif /* DP83820 */ 1041 1042 /* 1043 * Ensure we have enough descriptors free to describe 1044 * the packet. Note, we always reserve one descriptor 1045 * at the end of the ring as a termination point, to 1046 * prevent wrap-around. 1047 */ 1048 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1049 /* 1050 * Not enough free descriptors to transmit this 1051 * packet. We haven't committed anything yet, 1052 * so just unload the DMA map, put the packet 1053 * back on the queue, and punt. Notify the upper 1054 * layer that there are not more slots left. 1055 * 1056 * XXX We could allocate an mbuf and copy, but 1057 * XXX is it worth it? 1058 */ 1059 ifp->if_flags |= IFF_OACTIVE; 1060 bus_dmamap_unload(sc->sc_dmat, dmamap); 1061 #ifndef DP83820 1062 if (m != NULL) 1063 m_freem(m); 1064 #endif 1065 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1066 break; 1067 } 1068 1069 IFQ_DEQUEUE(&ifp->if_snd, m0); 1070 #ifndef DP83820 1071 if (m != NULL) { 1072 m_freem(m0); 1073 m0 = m; 1074 } 1075 #endif 1076 1077 /* 1078 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1079 */ 1080 1081 /* Sync the DMA map. */ 1082 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1083 BUS_DMASYNC_PREWRITE); 1084 1085 /* 1086 * Initialize the transmit descriptors. 1087 */ 1088 for (nexttx = sc->sc_txnext, seg = 0; 1089 seg < dmamap->dm_nsegs; 1090 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1091 /* 1092 * If this is the first descriptor we're 1093 * enqueueing, don't set the OWN bit just 1094 * yet. That could cause a race condition. 1095 * We'll do it below. 1096 */ 1097 sc->sc_txdescs[nexttx].sipd_bufptr = 1098 htole32(dmamap->dm_segs[seg].ds_addr); 1099 sc->sc_txdescs[nexttx].sipd_cmdsts = 1100 htole32((nexttx == firsttx ? 0 : CMDSTS_OWN) | 1101 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1102 #ifdef DP83820 1103 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1104 #endif /* DP83820 */ 1105 lasttx = nexttx; 1106 } 1107 1108 /* Clear the MORE bit on the last segment. */ 1109 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1110 1111 #ifdef DP83820 1112 /* 1113 * If VLANs are enabled and the packet has a VLAN tag, set 1114 * up the descriptor to encapsulate the packet for us. 1115 * 1116 * This apparently has to be on the last descriptor of 1117 * the packet. 1118 */ 1119 if (sc->sc_ethercom.ec_nvlans != 0 && 1120 (m = m_aux_find(m0, AF_LINK, ETHERTYPE_VLAN)) != NULL) { 1121 sc->sc_txdescs[lasttx].sipd_extsts |= 1122 htole32(EXTSTS_VPKT | 1123 htons(*mtod(m, int *) & EXTSTS_VTCI)); 1124 } 1125 1126 /* 1127 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1128 * checksumming, set up the descriptor to do this work 1129 * for us. 1130 * 1131 * This apparently has to be on the first descriptor of 1132 * the packet. 1133 * 1134 * Byte-swap constants so the compiler can optimize. 1135 */ 1136 extsts = 0; 1137 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1138 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1139 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1140 extsts |= htole32(EXTSTS_IPPKT); 1141 } 1142 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1143 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1144 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1145 extsts |= htole32(EXTSTS_TCPPKT); 1146 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1147 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1148 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1149 extsts |= htole32(EXTSTS_UDPPKT); 1150 } 1151 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1152 #endif /* DP83820 */ 1153 1154 /* Sync the descriptors we're using. */ 1155 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1156 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1157 1158 /* 1159 * Store a pointer to the packet so we can free it later, 1160 * and remember what txdirty will be once the packet is 1161 * done. 1162 */ 1163 txs->txs_mbuf = m0; 1164 txs->txs_firstdesc = sc->sc_txnext; 1165 txs->txs_lastdesc = lasttx; 1166 1167 /* Advance the tx pointer. */ 1168 sc->sc_txfree -= dmamap->dm_nsegs; 1169 sc->sc_txnext = nexttx; 1170 1171 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs, txs_q); 1172 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1173 1174 #if NBPFILTER > 0 1175 /* 1176 * Pass the packet to any BPF listeners. 1177 */ 1178 if (ifp->if_bpf) 1179 bpf_mtap(ifp->if_bpf, m0); 1180 #endif /* NBPFILTER > 0 */ 1181 } 1182 1183 if (txs == NULL || sc->sc_txfree == 0) { 1184 /* No more slots left; notify upper layer. */ 1185 ifp->if_flags |= IFF_OACTIVE; 1186 } 1187 1188 if (sc->sc_txfree != ofree) { 1189 /* 1190 * Cause a descriptor interrupt to happen on the 1191 * last packet we enqueued. 1192 */ 1193 sc->sc_txdescs[lasttx].sipd_cmdsts |= htole32(CMDSTS_INTR); 1194 SIP_CDTXSYNC(sc, lasttx, 1, 1195 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1196 1197 /* 1198 * The entire packet chain is set up. Give the 1199 * first descrptor to the chip now. 1200 */ 1201 sc->sc_txdescs[firsttx].sipd_cmdsts |= htole32(CMDSTS_OWN); 1202 SIP_CDTXSYNC(sc, firsttx, 1, 1203 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1204 1205 /* 1206 * Start the transmit process. Note, the manual says 1207 * that if there are no pending transmissions in the 1208 * chip's internal queue (indicated by TXE being clear), 1209 * then the driver software must set the TXDP to the 1210 * first descriptor to be transmitted. However, if we 1211 * do this, it causes serious performance degredation on 1212 * the DP83820 under load, not setting TXDP doesn't seem 1213 * to adversely affect the SiS 900 or DP83815. 1214 * 1215 * Well, I guess it wouldn't be the first time a manual 1216 * has lied -- and they could be speaking of the NULL- 1217 * terminated descriptor list case, rather than OWN- 1218 * terminated rings. 1219 */ 1220 #if 0 1221 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1222 CR_TXE) == 0) { 1223 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1224 SIP_CDTXADDR(sc, firsttx)); 1225 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1226 } 1227 #else 1228 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1229 #endif 1230 1231 /* Set a watchdog timer in case the chip flakes out. */ 1232 ifp->if_timer = 5; 1233 } 1234 } 1235 1236 /* 1237 * sip_watchdog: [ifnet interface function] 1238 * 1239 * Watchdog timer handler. 1240 */ 1241 void 1242 SIP_DECL(watchdog)(struct ifnet *ifp) 1243 { 1244 struct sip_softc *sc = ifp->if_softc; 1245 1246 /* 1247 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1248 * If we get a timeout, try and sweep up transmit descriptors. 1249 * If we manage to sweep them all up, ignore the lack of 1250 * interrupt. 1251 */ 1252 SIP_DECL(txintr)(sc); 1253 1254 if (sc->sc_txfree != SIP_NTXDESC) { 1255 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1256 ifp->if_oerrors++; 1257 1258 /* Reset the interface. */ 1259 (void) SIP_DECL(init)(ifp); 1260 } else if (ifp->if_flags & IFF_DEBUG) 1261 printf("%s: recovered from device timeout\n", 1262 sc->sc_dev.dv_xname); 1263 1264 /* Try to get more packets going. */ 1265 SIP_DECL(start)(ifp); 1266 } 1267 1268 /* 1269 * sip_ioctl: [ifnet interface function] 1270 * 1271 * Handle control requests from the operator. 1272 */ 1273 int 1274 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1275 { 1276 struct sip_softc *sc = ifp->if_softc; 1277 struct ifreq *ifr = (struct ifreq *)data; 1278 int s, error; 1279 1280 s = splnet(); 1281 1282 switch (cmd) { 1283 case SIOCSIFMEDIA: 1284 case SIOCGIFMEDIA: 1285 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1286 break; 1287 1288 default: 1289 error = ether_ioctl(ifp, cmd, data); 1290 if (error == ENETRESET) { 1291 /* 1292 * Multicast list has changed; set the hardware filter 1293 * accordingly. 1294 */ 1295 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1296 error = 0; 1297 } 1298 break; 1299 } 1300 1301 /* Try to get more packets going. */ 1302 SIP_DECL(start)(ifp); 1303 1304 splx(s); 1305 return (error); 1306 } 1307 1308 /* 1309 * sip_intr: 1310 * 1311 * Interrupt service routine. 1312 */ 1313 int 1314 SIP_DECL(intr)(void *arg) 1315 { 1316 struct sip_softc *sc = arg; 1317 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1318 u_int32_t isr; 1319 int handled = 0; 1320 1321 for (;;) { 1322 /* Reading clears interrupt. */ 1323 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1324 if ((isr & sc->sc_imr) == 0) 1325 break; 1326 1327 handled = 1; 1328 1329 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1330 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1331 1332 /* Grab any new packets. */ 1333 SIP_DECL(rxintr)(sc); 1334 1335 if (isr & ISR_RXORN) { 1336 printf("%s: receive FIFO overrun\n", 1337 sc->sc_dev.dv_xname); 1338 1339 /* XXX adjust rx_drain_thresh? */ 1340 } 1341 1342 if (isr & ISR_RXIDLE) { 1343 printf("%s: receive ring overrun\n", 1344 sc->sc_dev.dv_xname); 1345 1346 /* Get the receive process going again. */ 1347 bus_space_write_4(sc->sc_st, sc->sc_sh, 1348 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1349 bus_space_write_4(sc->sc_st, sc->sc_sh, 1350 SIP_CR, CR_RXE); 1351 } 1352 } 1353 1354 if (isr & (ISR_TXURN|ISR_TXDESC)) { 1355 SIP_EVCNT_INCR(&sc->sc_ev_txintr); 1356 1357 /* Sweep up transmit descriptors. */ 1358 SIP_DECL(txintr)(sc); 1359 1360 if (isr & ISR_TXURN) { 1361 u_int32_t thresh; 1362 1363 printf("%s: transmit FIFO underrun", 1364 sc->sc_dev.dv_xname); 1365 1366 thresh = sc->sc_tx_drain_thresh + 1; 1367 if (thresh <= TXCFG_DRTH && 1368 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1369 (sc->sc_tx_fill_thresh * 32))) { 1370 printf("; increasing Tx drain " 1371 "threshold to %u bytes\n", 1372 thresh * 32); 1373 sc->sc_tx_drain_thresh = thresh; 1374 (void) SIP_DECL(init)(ifp); 1375 } else { 1376 (void) SIP_DECL(init)(ifp); 1377 printf("\n"); 1378 } 1379 } 1380 } 1381 1382 #if !defined(DP83820) 1383 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1384 if (isr & ISR_PAUSE_ST) { 1385 sc->sc_flags |= SIPF_PAUSED; 1386 ifp->if_flags |= IFF_OACTIVE; 1387 } 1388 if (isr & ISR_PAUSE_END) { 1389 sc->sc_flags &= ~SIPF_PAUSED; 1390 ifp->if_flags &= ~IFF_OACTIVE; 1391 } 1392 } 1393 #endif /* ! DP83820 */ 1394 1395 if (isr & ISR_HIBERR) { 1396 #define PRINTERR(bit, str) \ 1397 if (isr & (bit)) \ 1398 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1399 PRINTERR(ISR_DPERR, "parity error"); 1400 PRINTERR(ISR_SSERR, "system error"); 1401 PRINTERR(ISR_RMABT, "master abort"); 1402 PRINTERR(ISR_RTABT, "target abort"); 1403 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1404 (void) SIP_DECL(init)(ifp); 1405 #undef PRINTERR 1406 } 1407 } 1408 1409 /* Try to get more packets going. */ 1410 SIP_DECL(start)(ifp); 1411 1412 return (handled); 1413 } 1414 1415 /* 1416 * sip_txintr: 1417 * 1418 * Helper; handle transmit interrupts. 1419 */ 1420 void 1421 SIP_DECL(txintr)(struct sip_softc *sc) 1422 { 1423 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1424 struct sip_txsoft *txs; 1425 u_int32_t cmdsts; 1426 1427 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1428 ifp->if_flags &= ~IFF_OACTIVE; 1429 1430 /* 1431 * Go through our Tx list and free mbufs for those 1432 * frames which have been transmitted. 1433 */ 1434 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1435 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1436 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1437 1438 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1439 if (cmdsts & CMDSTS_OWN) 1440 break; 1441 1442 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1443 1444 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1445 1446 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1447 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1448 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1449 m_freem(txs->txs_mbuf); 1450 txs->txs_mbuf = NULL; 1451 1452 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1453 1454 /* 1455 * Check for errors and collisions. 1456 */ 1457 if (cmdsts & 1458 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1459 ifp->if_oerrors++; 1460 if (cmdsts & CMDSTS_Tx_EC) 1461 ifp->if_collisions += 16; 1462 if (ifp->if_flags & IFF_DEBUG) { 1463 if (cmdsts & CMDSTS_Tx_ED) 1464 printf("%s: excessive deferral\n", 1465 sc->sc_dev.dv_xname); 1466 if (cmdsts & CMDSTS_Tx_EC) 1467 printf("%s: excessive collisions\n", 1468 sc->sc_dev.dv_xname); 1469 } 1470 } else { 1471 /* Packet was transmitted successfully. */ 1472 ifp->if_opackets++; 1473 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1474 } 1475 } 1476 1477 /* 1478 * If there are no more pending transmissions, cancel the watchdog 1479 * timer. 1480 */ 1481 if (txs == NULL) 1482 ifp->if_timer = 0; 1483 } 1484 1485 #if defined(DP83820) 1486 /* 1487 * sip_rxintr: 1488 * 1489 * Helper; handle receive interrupts. 1490 */ 1491 void 1492 SIP_DECL(rxintr)(struct sip_softc *sc) 1493 { 1494 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1495 struct sip_rxsoft *rxs; 1496 struct mbuf *m, *tailm; 1497 u_int32_t cmdsts, extsts; 1498 int i, len; 1499 1500 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1501 rxs = &sc->sc_rxsoft[i]; 1502 1503 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1504 1505 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1506 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1507 1508 /* 1509 * NOTE: OWN is set if owned by _consumer_. We're the 1510 * consumer of the receive ring, so if the bit is clear, 1511 * we have processed all of the packets. 1512 */ 1513 if ((cmdsts & CMDSTS_OWN) == 0) { 1514 /* 1515 * We have processed all of the receive buffers. 1516 */ 1517 break; 1518 } 1519 1520 if (__predict_false(sc->sc_rxdiscard)) { 1521 SIP_INIT_RXDESC(sc, i); 1522 if ((cmdsts & CMDSTS_MORE) == 0) { 1523 /* Reset our state. */ 1524 sc->sc_rxdiscard = 0; 1525 } 1526 continue; 1527 } 1528 1529 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1530 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1531 1532 m = rxs->rxs_mbuf; 1533 1534 /* 1535 * Add a new receive buffer to the ring. 1536 */ 1537 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1538 /* 1539 * Failed, throw away what we've done so 1540 * far, and discard the rest of the packet. 1541 */ 1542 ifp->if_ierrors++; 1543 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1544 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1545 SIP_INIT_RXDESC(sc, i); 1546 if (cmdsts & CMDSTS_MORE) 1547 sc->sc_rxdiscard = 1; 1548 if (sc->sc_rxhead != NULL) 1549 m_freem(sc->sc_rxhead); 1550 SIP_RXCHAIN_RESET(sc); 1551 continue; 1552 } 1553 1554 SIP_RXCHAIN_LINK(sc, m); 1555 1556 /* 1557 * If this is not the end of the packet, keep 1558 * looking. 1559 */ 1560 if (cmdsts & CMDSTS_MORE) { 1561 sc->sc_rxlen += m->m_len; 1562 continue; 1563 } 1564 1565 /* 1566 * Okay, we have the entire packet now... 1567 */ 1568 *sc->sc_rxtailp = NULL; 1569 m = sc->sc_rxhead; 1570 tailm = sc->sc_rxtail; 1571 1572 SIP_RXCHAIN_RESET(sc); 1573 1574 /* 1575 * If an error occurred, update stats and drop the packet. 1576 */ 1577 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1578 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1579 ifp->if_ierrors++; 1580 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1581 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1582 /* Receive overrun handled elsewhere. */ 1583 printf("%s: receive descriptor error\n", 1584 sc->sc_dev.dv_xname); 1585 } 1586 #define PRINTERR(bit, str) \ 1587 if (cmdsts & (bit)) \ 1588 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1589 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1590 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1591 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1592 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1593 #undef PRINTERR 1594 m_freem(m); 1595 continue; 1596 } 1597 1598 /* 1599 * No errors. 1600 * 1601 * Note, the DP83820 includes the CRC with 1602 * every packet. 1603 */ 1604 len = CMDSTS_SIZE(cmdsts); 1605 tailm->m_len = len - sc->sc_rxlen; 1606 1607 /* 1608 * If the packet is small enough to fit in a 1609 * single header mbuf, allocate one and copy 1610 * the data into it. This greatly reduces 1611 * memory consumption when we receive lots 1612 * of small packets. 1613 */ 1614 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1615 struct mbuf *nm; 1616 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1617 if (nm == NULL) { 1618 ifp->if_ierrors++; 1619 m_freem(m); 1620 continue; 1621 } 1622 nm->m_data += 2; 1623 nm->m_pkthdr.len = nm->m_len = len; 1624 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1625 m_freem(m); 1626 m = nm; 1627 } 1628 #ifndef __NO_STRICT_ALIGNMENT 1629 else { 1630 /* 1631 * The DP83820's receive buffers must be 4-byte 1632 * aligned. But this means that the data after 1633 * the Ethernet header is misaligned. To compensate, 1634 * we have artificially shortened the buffer size 1635 * in the descriptor, and we do an overlapping copy 1636 * of the data two bytes further in (in the first 1637 * buffer of the chain only). 1638 */ 1639 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1640 m->m_len); 1641 m->m_data += 2; 1642 } 1643 #endif /* ! __NO_STRICT_ALIGNMENT */ 1644 1645 /* 1646 * If VLANs are enabled, VLAN packets have been unwrapped 1647 * for us. Associate the tag with the packet. 1648 */ 1649 if (sc->sc_ethercom.ec_nvlans != 0 && 1650 (extsts & EXTSTS_VPKT) != 0) { 1651 struct mbuf *vtag; 1652 1653 vtag = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 1654 if (vtag == NULL) { 1655 ifp->if_ierrors++; 1656 printf("%s: unable to allocate VLAN tag\n", 1657 sc->sc_dev.dv_xname); 1658 m_freem(m); 1659 continue; 1660 } 1661 1662 *mtod(vtag, int *) = ntohs(extsts & EXTSTS_VTCI); 1663 vtag->m_len = sizeof(int); 1664 } 1665 1666 /* 1667 * Set the incoming checksum information for the 1668 * packet. 1669 */ 1670 if ((extsts & EXTSTS_IPPKT) != 0) { 1671 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1672 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1673 if (extsts & EXTSTS_Rx_IPERR) 1674 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1675 if (extsts & EXTSTS_TCPPKT) { 1676 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1677 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1678 if (extsts & EXTSTS_Rx_TCPERR) 1679 m->m_pkthdr.csum_flags |= 1680 M_CSUM_TCP_UDP_BAD; 1681 } else if (extsts & EXTSTS_UDPPKT) { 1682 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1683 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1684 if (extsts & EXTSTS_Rx_UDPERR) 1685 m->m_pkthdr.csum_flags |= 1686 M_CSUM_TCP_UDP_BAD; 1687 } 1688 } 1689 1690 ifp->if_ipackets++; 1691 m->m_flags |= M_HASFCS; 1692 m->m_pkthdr.rcvif = ifp; 1693 m->m_pkthdr.len = len; 1694 1695 #if NBPFILTER > 0 1696 /* 1697 * Pass this up to any BPF listeners, but only 1698 * pass if up the stack if it's for us. 1699 */ 1700 if (ifp->if_bpf) 1701 bpf_mtap(ifp->if_bpf, m); 1702 #endif /* NBPFILTER > 0 */ 1703 1704 /* Pass it on. */ 1705 (*ifp->if_input)(ifp, m); 1706 } 1707 1708 /* Update the receive pointer. */ 1709 sc->sc_rxptr = i; 1710 } 1711 #else /* ! DP83820 */ 1712 /* 1713 * sip_rxintr: 1714 * 1715 * Helper; handle receive interrupts. 1716 */ 1717 void 1718 SIP_DECL(rxintr)(struct sip_softc *sc) 1719 { 1720 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1721 struct sip_rxsoft *rxs; 1722 struct mbuf *m; 1723 u_int32_t cmdsts; 1724 int i, len; 1725 1726 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1727 rxs = &sc->sc_rxsoft[i]; 1728 1729 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1730 1731 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1732 1733 /* 1734 * NOTE: OWN is set if owned by _consumer_. We're the 1735 * consumer of the receive ring, so if the bit is clear, 1736 * we have processed all of the packets. 1737 */ 1738 if ((cmdsts & CMDSTS_OWN) == 0) { 1739 /* 1740 * We have processed all of the receive buffers. 1741 */ 1742 break; 1743 } 1744 1745 /* 1746 * If any collisions were seen on the wire, count one. 1747 */ 1748 if (cmdsts & CMDSTS_Rx_COL) 1749 ifp->if_collisions++; 1750 1751 /* 1752 * If an error occurred, update stats, clear the status 1753 * word, and leave the packet buffer in place. It will 1754 * simply be reused the next time the ring comes around. 1755 */ 1756 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1757 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1758 ifp->if_ierrors++; 1759 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1760 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1761 /* Receive overrun handled elsewhere. */ 1762 printf("%s: receive descriptor error\n", 1763 sc->sc_dev.dv_xname); 1764 } 1765 #define PRINTERR(bit, str) \ 1766 if (cmdsts & (bit)) \ 1767 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1768 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1769 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1770 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1771 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1772 #undef PRINTERR 1773 SIP_INIT_RXDESC(sc, i); 1774 continue; 1775 } 1776 1777 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1778 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1779 1780 /* 1781 * No errors; receive the packet. Note, the SiS 900 1782 * includes the CRC with every packet. 1783 */ 1784 len = CMDSTS_SIZE(cmdsts); 1785 1786 #ifdef __NO_STRICT_ALIGNMENT 1787 /* 1788 * If the packet is small enough to fit in a 1789 * single header mbuf, allocate one and copy 1790 * the data into it. This greatly reduces 1791 * memory consumption when we receive lots 1792 * of small packets. 1793 * 1794 * Otherwise, we add a new buffer to the receive 1795 * chain. If this fails, we drop the packet and 1796 * recycle the old buffer. 1797 */ 1798 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 1799 MGETHDR(m, M_DONTWAIT, MT_DATA); 1800 if (m == NULL) 1801 goto dropit; 1802 memcpy(mtod(m, caddr_t), 1803 mtod(rxs->rxs_mbuf, caddr_t), len); 1804 SIP_INIT_RXDESC(sc, i); 1805 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1806 rxs->rxs_dmamap->dm_mapsize, 1807 BUS_DMASYNC_PREREAD); 1808 } else { 1809 m = rxs->rxs_mbuf; 1810 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1811 dropit: 1812 ifp->if_ierrors++; 1813 SIP_INIT_RXDESC(sc, i); 1814 bus_dmamap_sync(sc->sc_dmat, 1815 rxs->rxs_dmamap, 0, 1816 rxs->rxs_dmamap->dm_mapsize, 1817 BUS_DMASYNC_PREREAD); 1818 continue; 1819 } 1820 } 1821 #else 1822 /* 1823 * The SiS 900's receive buffers must be 4-byte aligned. 1824 * But this means that the data after the Ethernet header 1825 * is misaligned. We must allocate a new buffer and 1826 * copy the data, shifted forward 2 bytes. 1827 */ 1828 MGETHDR(m, M_DONTWAIT, MT_DATA); 1829 if (m == NULL) { 1830 dropit: 1831 ifp->if_ierrors++; 1832 SIP_INIT_RXDESC(sc, i); 1833 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1834 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1835 continue; 1836 } 1837 if (len > (MHLEN - 2)) { 1838 MCLGET(m, M_DONTWAIT); 1839 if ((m->m_flags & M_EXT) == 0) { 1840 m_freem(m); 1841 goto dropit; 1842 } 1843 } 1844 m->m_data += 2; 1845 1846 /* 1847 * Note that we use clusters for incoming frames, so the 1848 * buffer is virtually contiguous. 1849 */ 1850 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 1851 1852 /* Allow the receive descriptor to continue using its mbuf. */ 1853 SIP_INIT_RXDESC(sc, i); 1854 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1855 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1856 #endif /* __NO_STRICT_ALIGNMENT */ 1857 1858 ifp->if_ipackets++; 1859 m->m_flags |= M_HASFCS; 1860 m->m_pkthdr.rcvif = ifp; 1861 m->m_pkthdr.len = m->m_len = len; 1862 1863 #if NBPFILTER > 0 1864 /* 1865 * Pass this up to any BPF listeners, but only 1866 * pass if up the stack if it's for us. 1867 */ 1868 if (ifp->if_bpf) 1869 bpf_mtap(ifp->if_bpf, m); 1870 #endif /* NBPFILTER > 0 */ 1871 1872 /* Pass it on. */ 1873 (*ifp->if_input)(ifp, m); 1874 } 1875 1876 /* Update the receive pointer. */ 1877 sc->sc_rxptr = i; 1878 } 1879 #endif /* DP83820 */ 1880 1881 /* 1882 * sip_tick: 1883 * 1884 * One second timer, used to tick the MII. 1885 */ 1886 void 1887 SIP_DECL(tick)(void *arg) 1888 { 1889 struct sip_softc *sc = arg; 1890 int s; 1891 1892 s = splnet(); 1893 mii_tick(&sc->sc_mii); 1894 splx(s); 1895 1896 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 1897 } 1898 1899 /* 1900 * sip_reset: 1901 * 1902 * Perform a soft reset on the SiS 900. 1903 */ 1904 void 1905 SIP_DECL(reset)(struct sip_softc *sc) 1906 { 1907 bus_space_tag_t st = sc->sc_st; 1908 bus_space_handle_t sh = sc->sc_sh; 1909 int i; 1910 1911 bus_space_write_4(st, sh, SIP_CR, CR_RST); 1912 1913 for (i = 0; i < SIP_TIMEOUT; i++) { 1914 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 1915 break; 1916 delay(2); 1917 } 1918 1919 if (i == SIP_TIMEOUT) 1920 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1921 1922 delay(1000); 1923 1924 #ifdef DP83820 1925 /* 1926 * Set the general purpose I/O bits. Do it here in case we 1927 * need to have GPIO set up to talk to the media interface. 1928 */ 1929 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 1930 delay(1000); 1931 #endif /* DP83820 */ 1932 } 1933 1934 /* 1935 * sip_init: [ ifnet interface function ] 1936 * 1937 * Initialize the interface. Must be called at splnet(). 1938 */ 1939 int 1940 SIP_DECL(init)(struct ifnet *ifp) 1941 { 1942 struct sip_softc *sc = ifp->if_softc; 1943 bus_space_tag_t st = sc->sc_st; 1944 bus_space_handle_t sh = sc->sc_sh; 1945 struct sip_txsoft *txs; 1946 struct sip_rxsoft *rxs; 1947 struct sip_desc *sipd; 1948 u_int32_t reg; 1949 int i, error = 0; 1950 1951 /* 1952 * Cancel any pending I/O. 1953 */ 1954 SIP_DECL(stop)(ifp, 0); 1955 1956 /* 1957 * Reset the chip to a known state. 1958 */ 1959 SIP_DECL(reset)(sc); 1960 1961 #if !defined(DP83820) 1962 if (sc->sc_model->sip_vendor == PCI_VENDOR_NS && 1963 sc->sc_model->sip_product == PCI_PRODUCT_NS_DP83815) { 1964 /* 1965 * DP83815 manual, page 78: 1966 * 4.4 Recommended Registers Configuration 1967 * For optimum performance of the DP83815, version noted 1968 * as DP83815CVNG (SRR = 203h), the listed register 1969 * modifications must be followed in sequence... 1970 * 1971 * It's not clear if this should be 302h or 203h because that 1972 * chip name is listed as SRR 302h in the description of the 1973 * SRR register. However, my revision 302h DP83815 on the 1974 * Netgear FA311 purchased in 02/2001 needs these settings 1975 * to avoid tons of errors in AcceptPerfectMatch (non- 1976 * IFF_PROMISC) mode. I do not know if other revisions need 1977 * this set or not. [briggs -- 09 March 2001] 1978 * 1979 * Note that only the low-order 12 bits of 0xe4 are documented 1980 * and that this sets reserved bits in that register. 1981 */ 1982 reg = bus_space_read_4(st, sh, SIP_NS_SRR); 1983 if (reg == 0x302) { 1984 bus_space_write_4(st, sh, 0x00cc, 0x0001); 1985 bus_space_write_4(st, sh, 0x00e4, 0x189C); 1986 bus_space_write_4(st, sh, 0x00fc, 0x0000); 1987 bus_space_write_4(st, sh, 0x00f4, 0x5040); 1988 bus_space_write_4(st, sh, 0x00f8, 0x008c); 1989 } 1990 } 1991 #endif /* ! DP83820 */ 1992 1993 /* 1994 * Initialize the transmit descriptor ring. 1995 */ 1996 for (i = 0; i < SIP_NTXDESC; i++) { 1997 sipd = &sc->sc_txdescs[i]; 1998 memset(sipd, 0, sizeof(struct sip_desc)); 1999 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2000 } 2001 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2002 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2003 sc->sc_txfree = SIP_NTXDESC; 2004 sc->sc_txnext = 0; 2005 2006 /* 2007 * Initialize the transmit job descriptors. 2008 */ 2009 SIMPLEQ_INIT(&sc->sc_txfreeq); 2010 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2011 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2012 txs = &sc->sc_txsoft[i]; 2013 txs->txs_mbuf = NULL; 2014 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2015 } 2016 2017 /* 2018 * Initialize the receive descriptor and receive job 2019 * descriptor rings. 2020 */ 2021 for (i = 0; i < SIP_NRXDESC; i++) { 2022 rxs = &sc->sc_rxsoft[i]; 2023 if (rxs->rxs_mbuf == NULL) { 2024 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2025 printf("%s: unable to allocate or map rx " 2026 "buffer %d, error = %d\n", 2027 sc->sc_dev.dv_xname, i, error); 2028 /* 2029 * XXX Should attempt to run with fewer receive 2030 * XXX buffers instead of just failing. 2031 */ 2032 SIP_DECL(rxdrain)(sc); 2033 goto out; 2034 } 2035 } else 2036 SIP_INIT_RXDESC(sc, i); 2037 } 2038 sc->sc_rxptr = 0; 2039 #ifdef DP83820 2040 sc->sc_rxdiscard = 0; 2041 SIP_RXCHAIN_RESET(sc); 2042 #endif /* DP83820 */ 2043 2044 /* 2045 * Set the configuration register; it's already initialized 2046 * in sip_attach(). 2047 */ 2048 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2049 2050 /* 2051 * Initialize the transmit fill and drain thresholds if 2052 * we have never done so. 2053 */ 2054 if (sc->sc_tx_fill_thresh == 0) { 2055 /* 2056 * XXX This value should be tuned. This is the 2057 * minimum (32 bytes), and we may be able to 2058 * improve performance by increasing it. 2059 */ 2060 sc->sc_tx_fill_thresh = 1; 2061 } 2062 if (sc->sc_tx_drain_thresh == 0) { 2063 /* 2064 * Start at a drain threshold of 512 bytes. We will 2065 * increase it if a DMA underrun occurs. 2066 * 2067 * XXX The minimum value of this variable should be 2068 * tuned. We may be able to improve performance 2069 * by starting with a lower value. That, however, 2070 * may trash the first few outgoing packets if the 2071 * PCI bus is saturated. 2072 */ 2073 sc->sc_tx_drain_thresh = 512 / 32; 2074 } 2075 2076 /* 2077 * Initialize the prototype TXCFG register. 2078 */ 2079 sc->sc_txcfg = TXCFG_ATP | TXCFG_MXDMA_512 | 2080 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2081 sc->sc_tx_drain_thresh; 2082 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2083 2084 /* 2085 * Initialize the receive drain threshold if we have never 2086 * done so. 2087 */ 2088 if (sc->sc_rx_drain_thresh == 0) { 2089 /* 2090 * XXX This value should be tuned. This is set to the 2091 * maximum of 248 bytes, and we may be able to improve 2092 * performance by decreasing it (although we should never 2093 * set this value lower than 2; 14 bytes are required to 2094 * filter the packet). 2095 */ 2096 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2097 } 2098 2099 /* 2100 * Initialize the prototype RXCFG register. 2101 */ 2102 sc->sc_rxcfg = RXCFG_MXDMA_512 | 2103 (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2104 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2105 2106 /* Set up the receive filter. */ 2107 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2108 2109 #ifdef DP83820 2110 /* 2111 * Initialize the VLAN/IP receive control register. 2112 * We enable checksum computation on all incoming 2113 * packets, and do not reject packets w/ bad checksums. 2114 */ 2115 reg = 0; 2116 if (ifp->if_capenable & 2117 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2118 reg |= VRCR_IPEN; 2119 if (sc->sc_ethercom.ec_nvlans != 0) 2120 reg |= VRCR_VTDEN|VRCR_VTREN; 2121 bus_space_write_4(st, sh, SIP_VRCR, reg); 2122 2123 /* 2124 * Initialize the VLAN/IP transmit control register. 2125 * We enable outgoing checksum computation on a 2126 * per-packet basis. 2127 */ 2128 reg = 0; 2129 if (ifp->if_capenable & 2130 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2131 reg |= VTCR_PPCHK; 2132 if (sc->sc_ethercom.ec_nvlans != 0) 2133 reg |= VTCR_VPPTI; 2134 bus_space_write_4(st, sh, SIP_VTCR, reg); 2135 2136 /* 2137 * If we're using VLANs, initialize the VLAN data register. 2138 * To understand why we bswap the VLAN Ethertype, see section 2139 * 4.2.36 of the DP83820 manual. 2140 */ 2141 if (sc->sc_ethercom.ec_nvlans != 0) 2142 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2143 #endif /* DP83820 */ 2144 2145 /* 2146 * Give the transmit and receive rings to the chip. 2147 */ 2148 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2149 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2150 2151 /* 2152 * Initialize the interrupt mask. 2153 */ 2154 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2155 ISR_TXURN|ISR_TXDESC|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2156 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2157 2158 /* 2159 * Set the current media. Do this after initializing the prototype 2160 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2161 * control. 2162 */ 2163 mii_mediachg(&sc->sc_mii); 2164 2165 /* 2166 * Enable interrupts. 2167 */ 2168 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2169 2170 /* 2171 * Start the transmit and receive processes. 2172 */ 2173 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2174 2175 /* 2176 * Start the one second MII clock. 2177 */ 2178 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2179 2180 /* 2181 * ...all done! 2182 */ 2183 ifp->if_flags |= IFF_RUNNING; 2184 ifp->if_flags &= ~IFF_OACTIVE; 2185 2186 out: 2187 if (error) 2188 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2189 return (error); 2190 } 2191 2192 /* 2193 * sip_drain: 2194 * 2195 * Drain the receive queue. 2196 */ 2197 void 2198 SIP_DECL(rxdrain)(struct sip_softc *sc) 2199 { 2200 struct sip_rxsoft *rxs; 2201 int i; 2202 2203 for (i = 0; i < SIP_NRXDESC; i++) { 2204 rxs = &sc->sc_rxsoft[i]; 2205 if (rxs->rxs_mbuf != NULL) { 2206 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2207 m_freem(rxs->rxs_mbuf); 2208 rxs->rxs_mbuf = NULL; 2209 } 2210 } 2211 } 2212 2213 /* 2214 * sip_stop: [ ifnet interface function ] 2215 * 2216 * Stop transmission on the interface. 2217 */ 2218 void 2219 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2220 { 2221 struct sip_softc *sc = ifp->if_softc; 2222 bus_space_tag_t st = sc->sc_st; 2223 bus_space_handle_t sh = sc->sc_sh; 2224 struct sip_txsoft *txs; 2225 u_int32_t cmdsts = 0; /* DEBUG */ 2226 2227 /* 2228 * Stop the one second clock. 2229 */ 2230 callout_stop(&sc->sc_tick_ch); 2231 2232 /* Down the MII. */ 2233 mii_down(&sc->sc_mii); 2234 2235 /* 2236 * Disable interrupts. 2237 */ 2238 bus_space_write_4(st, sh, SIP_IER, 0); 2239 2240 /* 2241 * Stop receiver and transmitter. 2242 */ 2243 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2244 2245 /* 2246 * Release any queued transmit buffers. 2247 */ 2248 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2249 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2250 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2251 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2252 CMDSTS_INTR) == 0) 2253 printf("%s: sip_stop: last descriptor does not " 2254 "have INTR bit set\n", sc->sc_dev.dv_xname); 2255 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 2256 #ifdef DIAGNOSTIC 2257 if (txs->txs_mbuf == NULL) { 2258 printf("%s: dirty txsoft with no mbuf chain\n", 2259 sc->sc_dev.dv_xname); 2260 panic("sip_stop"); 2261 } 2262 #endif 2263 cmdsts |= /* DEBUG */ 2264 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2265 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2266 m_freem(txs->txs_mbuf); 2267 txs->txs_mbuf = NULL; 2268 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2269 } 2270 2271 if (disable) 2272 SIP_DECL(rxdrain)(sc); 2273 2274 /* 2275 * Mark the interface down and cancel the watchdog timer. 2276 */ 2277 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2278 ifp->if_timer = 0; 2279 2280 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2281 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2282 printf("%s: sip_stop: no INTR bits set in dirty tx " 2283 "descriptors\n", sc->sc_dev.dv_xname); 2284 } 2285 2286 /* 2287 * sip_read_eeprom: 2288 * 2289 * Read data from the serial EEPROM. 2290 */ 2291 void 2292 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2293 u_int16_t *data) 2294 { 2295 bus_space_tag_t st = sc->sc_st; 2296 bus_space_handle_t sh = sc->sc_sh; 2297 u_int16_t reg; 2298 int i, x; 2299 2300 for (i = 0; i < wordcnt; i++) { 2301 /* Send CHIP SELECT. */ 2302 reg = EROMAR_EECS; 2303 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2304 2305 /* Shift in the READ opcode. */ 2306 for (x = 3; x > 0; x--) { 2307 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2308 reg |= EROMAR_EEDI; 2309 else 2310 reg &= ~EROMAR_EEDI; 2311 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2312 bus_space_write_4(st, sh, SIP_EROMAR, 2313 reg | EROMAR_EESK); 2314 delay(4); 2315 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2316 delay(4); 2317 } 2318 2319 /* Shift in address. */ 2320 for (x = 6; x > 0; x--) { 2321 if ((word + i) & (1 << (x - 1))) 2322 reg |= EROMAR_EEDI; 2323 else 2324 reg &= ~EROMAR_EEDI; 2325 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2326 bus_space_write_4(st, sh, SIP_EROMAR, 2327 reg | EROMAR_EESK); 2328 delay(4); 2329 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2330 delay(4); 2331 } 2332 2333 /* Shift out data. */ 2334 reg = EROMAR_EECS; 2335 data[i] = 0; 2336 for (x = 16; x > 0; x--) { 2337 bus_space_write_4(st, sh, SIP_EROMAR, 2338 reg | EROMAR_EESK); 2339 delay(4); 2340 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2341 data[i] |= (1 << (x - 1)); 2342 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2343 delay(4); 2344 } 2345 2346 /* Clear CHIP SELECT. */ 2347 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2348 delay(4); 2349 } 2350 } 2351 2352 /* 2353 * sip_add_rxbuf: 2354 * 2355 * Add a receive buffer to the indicated descriptor. 2356 */ 2357 int 2358 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2359 { 2360 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2361 struct mbuf *m; 2362 int error; 2363 2364 MGETHDR(m, M_DONTWAIT, MT_DATA); 2365 if (m == NULL) 2366 return (ENOBUFS); 2367 2368 MCLGET(m, M_DONTWAIT); 2369 if ((m->m_flags & M_EXT) == 0) { 2370 m_freem(m); 2371 return (ENOBUFS); 2372 } 2373 2374 #if defined(DP83820) 2375 m->m_len = SIP_RXBUF_LEN; 2376 #endif /* DP83820 */ 2377 2378 if (rxs->rxs_mbuf != NULL) 2379 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2380 2381 rxs->rxs_mbuf = m; 2382 2383 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2384 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2385 BUS_DMA_READ|BUS_DMA_NOWAIT); 2386 if (error) { 2387 printf("%s: can't load rx DMA map %d, error = %d\n", 2388 sc->sc_dev.dv_xname, idx, error); 2389 panic("sip_add_rxbuf"); /* XXX */ 2390 } 2391 2392 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2393 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2394 2395 SIP_INIT_RXDESC(sc, idx); 2396 2397 return (0); 2398 } 2399 2400 #if !defined(DP83820) 2401 /* 2402 * sip_sis900_set_filter: 2403 * 2404 * Set up the receive filter. 2405 */ 2406 void 2407 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2408 { 2409 bus_space_tag_t st = sc->sc_st; 2410 bus_space_handle_t sh = sc->sc_sh; 2411 struct ethercom *ec = &sc->sc_ethercom; 2412 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2413 struct ether_multi *enm; 2414 u_int8_t *cp; 2415 struct ether_multistep step; 2416 u_int32_t crc, mchash[8]; 2417 2418 /* 2419 * Initialize the prototype RFCR. 2420 */ 2421 sc->sc_rfcr = RFCR_RFEN; 2422 if (ifp->if_flags & IFF_BROADCAST) 2423 sc->sc_rfcr |= RFCR_AAB; 2424 if (ifp->if_flags & IFF_PROMISC) { 2425 sc->sc_rfcr |= RFCR_AAP; 2426 goto allmulti; 2427 } 2428 2429 /* 2430 * Set up the multicast address filter by passing all multicast 2431 * addresses through a CRC generator, and then using the high-order 2432 * 6 bits as an index into the 128 bit multicast hash table (only 2433 * the lower 16 bits of each 32 bit multicast hash register are 2434 * valid). The high order bits select the register, while the 2435 * rest of the bits select the bit within the register. 2436 */ 2437 2438 memset(mchash, 0, sizeof(mchash)); 2439 2440 ETHER_FIRST_MULTI(step, ec, enm); 2441 while (enm != NULL) { 2442 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2443 /* 2444 * We must listen to a range of multicast addresses. 2445 * For now, just accept all multicasts, rather than 2446 * trying to set only those filter bits needed to match 2447 * the range. (At this time, the only use of address 2448 * ranges is for IP multicast routing, for which the 2449 * range is big enough to require all bits set.) 2450 */ 2451 goto allmulti; 2452 } 2453 2454 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2455 2456 /* Just want the 7 most significant bits. */ 2457 crc >>= 25; 2458 2459 /* Set the corresponding bit in the hash table. */ 2460 mchash[crc >> 4] |= 1 << (crc & 0xf); 2461 2462 ETHER_NEXT_MULTI(step, enm); 2463 } 2464 2465 ifp->if_flags &= ~IFF_ALLMULTI; 2466 goto setit; 2467 2468 allmulti: 2469 ifp->if_flags |= IFF_ALLMULTI; 2470 sc->sc_rfcr |= RFCR_AAM; 2471 2472 setit: 2473 #define FILTER_EMIT(addr, data) \ 2474 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2475 delay(1); \ 2476 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2477 delay(1) 2478 2479 /* 2480 * Disable receive filter, and program the node address. 2481 */ 2482 cp = LLADDR(ifp->if_sadl); 2483 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2484 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2485 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2486 2487 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2488 /* 2489 * Program the multicast hash table. 2490 */ 2491 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2492 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2493 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2494 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2495 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2496 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2497 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2498 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2499 } 2500 #undef FILTER_EMIT 2501 2502 /* 2503 * Re-enable the receiver filter. 2504 */ 2505 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2506 } 2507 #endif /* ! DP83820 */ 2508 2509 /* 2510 * sip_dp83815_set_filter: 2511 * 2512 * Set up the receive filter. 2513 */ 2514 void 2515 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2516 { 2517 bus_space_tag_t st = sc->sc_st; 2518 bus_space_handle_t sh = sc->sc_sh; 2519 struct ethercom *ec = &sc->sc_ethercom; 2520 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2521 struct ether_multi *enm; 2522 u_int8_t *cp; 2523 struct ether_multistep step; 2524 u_int32_t crc, hash, slot, bit; 2525 #ifdef DP83820 2526 #define MCHASH_NWORDS 128 2527 #else 2528 #define MCHASH_NWORDS 32 2529 #endif /* DP83820 */ 2530 u_int16_t mchash[MCHASH_NWORDS]; 2531 int i; 2532 2533 /* 2534 * Initialize the prototype RFCR. 2535 * Enable the receive filter, and accept on 2536 * Perfect (destination address) Match 2537 * If IFF_BROADCAST, also accept all broadcast packets. 2538 * If IFF_PROMISC, accept all unicast packets (and later, set 2539 * IFF_ALLMULTI and accept all multicast, too). 2540 */ 2541 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2542 if (ifp->if_flags & IFF_BROADCAST) 2543 sc->sc_rfcr |= RFCR_AAB; 2544 if (ifp->if_flags & IFF_PROMISC) { 2545 sc->sc_rfcr |= RFCR_AAP; 2546 goto allmulti; 2547 } 2548 2549 #ifdef DP83820 2550 /* 2551 * Set up the DP83820 multicast address filter by passing all multicast 2552 * addresses through a CRC generator, and then using the high-order 2553 * 11 bits as an index into the 2048 bit multicast hash table. The 2554 * high-order 7 bits select the slot, while the low-order 4 bits 2555 * select the bit within the slot. Note that only the low 16-bits 2556 * of each filter word are used, and there are 128 filter words. 2557 */ 2558 #else 2559 /* 2560 * Set up the DP83815 multicast address filter by passing all multicast 2561 * addresses through a CRC generator, and then using the high-order 2562 * 9 bits as an index into the 512 bit multicast hash table. The 2563 * high-order 5 bits select the slot, while the low-order 4 bits 2564 * select the bit within the slot. Note that only the low 16-bits 2565 * of each filter word are used, and there are 32 filter words. 2566 */ 2567 #endif /* DP83820 */ 2568 2569 memset(mchash, 0, sizeof(mchash)); 2570 2571 ifp->if_flags &= ~IFF_ALLMULTI; 2572 ETHER_FIRST_MULTI(step, ec, enm); 2573 if (enm == NULL) 2574 goto setit; 2575 while (enm != NULL) { 2576 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2577 /* 2578 * We must listen to a range of multicast addresses. 2579 * For now, just accept all multicasts, rather than 2580 * trying to set only those filter bits needed to match 2581 * the range. (At this time, the only use of address 2582 * ranges is for IP multicast routing, for which the 2583 * range is big enough to require all bits set.) 2584 */ 2585 goto allmulti; 2586 } 2587 2588 #ifdef DP83820 2589 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2590 2591 /* Just want the 11 most significant bits. */ 2592 hash = crc >> 21; 2593 #else 2594 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2595 2596 /* Just want the 9 most significant bits. */ 2597 hash = crc >> 23; 2598 #endif /* DP83820 */ 2599 slot = hash >> 4; 2600 bit = hash & 0xf; 2601 2602 /* Set the corresponding bit in the hash table. */ 2603 mchash[slot] |= 1 << bit; 2604 2605 ETHER_NEXT_MULTI(step, enm); 2606 } 2607 sc->sc_rfcr |= RFCR_MHEN; 2608 goto setit; 2609 2610 allmulti: 2611 ifp->if_flags |= IFF_ALLMULTI; 2612 sc->sc_rfcr |= RFCR_AAM; 2613 2614 setit: 2615 #define FILTER_EMIT(addr, data) \ 2616 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2617 delay(1); \ 2618 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2619 delay(1) 2620 2621 /* 2622 * Disable receive filter, and program the node address. 2623 */ 2624 cp = LLADDR(ifp->if_sadl); 2625 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 2626 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 2627 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 2628 2629 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2630 /* 2631 * Program the multicast hash table. 2632 */ 2633 for (i = 0; i < MCHASH_NWORDS; i++) { 2634 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 2635 mchash[i]); 2636 } 2637 } 2638 #undef FILTER_EMIT 2639 #undef MCHASH_NWORDS 2640 2641 /* 2642 * Re-enable the receiver filter. 2643 */ 2644 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2645 } 2646 2647 #if defined(DP83820) 2648 /* 2649 * sip_dp83820_mii_readreg: [mii interface function] 2650 * 2651 * Read a PHY register on the MII of the DP83820. 2652 */ 2653 int 2654 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 2655 { 2656 2657 return (mii_bitbang_readreg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2658 phy, reg)); 2659 } 2660 2661 /* 2662 * sip_dp83820_mii_writereg: [mii interface function] 2663 * 2664 * Write a PHY register on the MII of the DP83820. 2665 */ 2666 void 2667 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 2668 { 2669 2670 mii_bitbang_writereg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2671 phy, reg, val); 2672 } 2673 2674 /* 2675 * sip_dp83815_mii_statchg: [mii interface function] 2676 * 2677 * Callback from MII layer when media changes. 2678 */ 2679 void 2680 SIP_DECL(dp83820_mii_statchg)(struct device *self) 2681 { 2682 struct sip_softc *sc = (struct sip_softc *) self; 2683 u_int32_t cfg; 2684 2685 /* 2686 * Update TXCFG for full-duplex operation. 2687 */ 2688 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2689 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2690 else 2691 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2692 2693 /* 2694 * Update RXCFG for full-duplex or loopback. 2695 */ 2696 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2697 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2698 sc->sc_rxcfg |= RXCFG_ATX; 2699 else 2700 sc->sc_rxcfg &= ~RXCFG_ATX; 2701 2702 /* 2703 * Update CFG for MII/GMII. 2704 */ 2705 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2706 cfg = sc->sc_cfg | CFG_MODE_1000; 2707 else 2708 cfg = sc->sc_cfg; 2709 2710 /* 2711 * XXX 802.3x flow control. 2712 */ 2713 2714 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 2715 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2716 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2717 } 2718 2719 /* 2720 * sip_dp83820_mii_bitbang_read: [mii bit-bang interface function] 2721 * 2722 * Read the MII serial port for the MII bit-bang module. 2723 */ 2724 u_int32_t 2725 SIP_DECL(dp83820_mii_bitbang_read)(struct device *self) 2726 { 2727 struct sip_softc *sc = (void *) self; 2728 2729 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 2730 } 2731 2732 /* 2733 * sip_dp83820_mii_bitbang_write: [mii big-bang interface function] 2734 * 2735 * Write the MII serial port for the MII bit-bang module. 2736 */ 2737 void 2738 SIP_DECL(dp83820_mii_bitbang_write)(struct device *self, u_int32_t val) 2739 { 2740 struct sip_softc *sc = (void *) self; 2741 2742 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 2743 } 2744 #else /* ! DP83820 */ 2745 /* 2746 * sip_sis900_mii_readreg: [mii interface function] 2747 * 2748 * Read a PHY register on the MII. 2749 */ 2750 int 2751 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 2752 { 2753 struct sip_softc *sc = (struct sip_softc *) self; 2754 u_int32_t enphy; 2755 2756 /* 2757 * The SiS 900 has only an internal PHY on the MII. Only allow 2758 * MII address 0. 2759 */ 2760 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 2761 return (0); 2762 2763 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2764 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 2765 ENPHY_RWCMD | ENPHY_ACCESS); 2766 do { 2767 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2768 } while (enphy & ENPHY_ACCESS); 2769 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 2770 } 2771 2772 /* 2773 * sip_sis900_mii_writereg: [mii interface function] 2774 * 2775 * Write a PHY register on the MII. 2776 */ 2777 void 2778 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 2779 { 2780 struct sip_softc *sc = (struct sip_softc *) self; 2781 u_int32_t enphy; 2782 2783 /* 2784 * The SiS 900 has only an internal PHY on the MII. Only allow 2785 * MII address 0. 2786 */ 2787 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 2788 return; 2789 2790 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2791 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 2792 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 2793 do { 2794 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2795 } while (enphy & ENPHY_ACCESS); 2796 } 2797 2798 /* 2799 * sip_sis900_mii_statchg: [mii interface function] 2800 * 2801 * Callback from MII layer when media changes. 2802 */ 2803 void 2804 SIP_DECL(sis900_mii_statchg)(struct device *self) 2805 { 2806 struct sip_softc *sc = (struct sip_softc *) self; 2807 u_int32_t flowctl; 2808 2809 /* 2810 * Update TXCFG for full-duplex operation. 2811 */ 2812 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2813 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2814 else 2815 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2816 2817 /* 2818 * Update RXCFG for full-duplex or loopback. 2819 */ 2820 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2821 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2822 sc->sc_rxcfg |= RXCFG_ATX; 2823 else 2824 sc->sc_rxcfg &= ~RXCFG_ATX; 2825 2826 /* 2827 * Update IMR for use of 802.3x flow control. 2828 */ 2829 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 2830 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 2831 flowctl = FLOWCTL_FLOWEN; 2832 } else { 2833 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 2834 flowctl = 0; 2835 } 2836 2837 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2838 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2839 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 2840 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 2841 } 2842 2843 /* 2844 * sip_dp83815_mii_readreg: [mii interface function] 2845 * 2846 * Read a PHY register on the MII. 2847 */ 2848 int 2849 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 2850 { 2851 struct sip_softc *sc = (struct sip_softc *) self; 2852 u_int32_t val; 2853 2854 /* 2855 * The DP83815 only has an internal PHY. Only allow 2856 * MII address 0. 2857 */ 2858 if (phy != 0) 2859 return (0); 2860 2861 /* 2862 * Apparently, after a reset, the DP83815 can take a while 2863 * to respond. During this recovery period, the BMSR returns 2864 * a value of 0. Catch this -- it's not supposed to happen 2865 * (the BMSR has some hardcoded-to-1 bits), and wait for the 2866 * PHY to come back to life. 2867 * 2868 * This works out because the BMSR is the first register 2869 * read during the PHY probe process. 2870 */ 2871 do { 2872 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 2873 } while (reg == MII_BMSR && val == 0); 2874 2875 return (val & 0xffff); 2876 } 2877 2878 /* 2879 * sip_dp83815_mii_writereg: [mii interface function] 2880 * 2881 * Write a PHY register to the MII. 2882 */ 2883 void 2884 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 2885 { 2886 struct sip_softc *sc = (struct sip_softc *) self; 2887 2888 /* 2889 * The DP83815 only has an internal PHY. Only allow 2890 * MII address 0. 2891 */ 2892 if (phy != 0) 2893 return; 2894 2895 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 2896 } 2897 2898 /* 2899 * sip_dp83815_mii_statchg: [mii interface function] 2900 * 2901 * Callback from MII layer when media changes. 2902 */ 2903 void 2904 SIP_DECL(dp83815_mii_statchg)(struct device *self) 2905 { 2906 struct sip_softc *sc = (struct sip_softc *) self; 2907 2908 /* 2909 * Update TXCFG for full-duplex operation. 2910 */ 2911 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2912 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2913 else 2914 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2915 2916 /* 2917 * Update RXCFG for full-duplex or loopback. 2918 */ 2919 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2920 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2921 sc->sc_rxcfg |= RXCFG_ATX; 2922 else 2923 sc->sc_rxcfg &= ~RXCFG_ATX; 2924 2925 /* 2926 * XXX 802.3x flow control. 2927 */ 2928 2929 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2930 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2931 } 2932 #endif /* DP83820 */ 2933 2934 #if defined(DP83820) 2935 void 2936 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, u_int8_t *enaddr) 2937 { 2938 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 2939 u_int8_t cksum, *e, match; 2940 int i; 2941 2942 /* 2943 * EEPROM data format for the DP83820 can be found in 2944 * the DP83820 manual, section 4.2.4. 2945 */ 2946 2947 SIP_DECL(read_eeprom)(sc, 0, 2948 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 2949 2950 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 2951 match = ~(match - 1); 2952 2953 cksum = 0x55; 2954 e = (u_int8_t *) eeprom_data; 2955 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 2956 cksum += *e++; 2957 2958 if (cksum != match) 2959 printf("%s: Checksum (%x) mismatch (%x)", 2960 sc->sc_dev.dv_xname, cksum, match); 2961 2962 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 2963 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 2964 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 2965 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 2966 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 2967 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 2968 2969 /* Get the GPIOR bits. */ 2970 sc->sc_gpior = eeprom_data[0x04]; 2971 2972 /* Get various CFG related bits. */ 2973 if ((eeprom_data[0x05] >> 0) & 1) 2974 sc->sc_cfg |= CFG_EXT_125; 2975 if ((eeprom_data[0x05] >> 9) & 1) 2976 sc->sc_cfg |= CFG_TBI_EN; 2977 } 2978 #else /* ! DP83820 */ 2979 void 2980 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, u_int8_t *enaddr) 2981 { 2982 u_int16_t myea[ETHER_ADDR_LEN / 2]; 2983 2984 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 2985 sizeof(myea) / sizeof(myea[0]), myea); 2986 2987 enaddr[0] = myea[0] & 0xff; 2988 enaddr[1] = myea[0] >> 8; 2989 enaddr[2] = myea[1] & 0xff; 2990 enaddr[3] = myea[1] >> 8; 2991 enaddr[4] = myea[2] & 0xff; 2992 enaddr[5] = myea[2] >> 8; 2993 } 2994 2995 /* Table and macro to bit-reverse an octet. */ 2996 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 2997 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 2998 2999 void 3000 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, u_int8_t *enaddr) 3001 { 3002 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3003 u_int8_t cksum, *e, match; 3004 int i; 3005 3006 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3007 sizeof(eeprom_data[0]), eeprom_data); 3008 3009 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3010 match = ~(match - 1); 3011 3012 cksum = 0x55; 3013 e = (u_int8_t *) eeprom_data; 3014 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3015 cksum += *e++; 3016 } 3017 if (cksum != match) { 3018 printf("%s: Checksum (%x) mismatch (%x)", 3019 sc->sc_dev.dv_xname, cksum, match); 3020 } 3021 3022 /* 3023 * Unrolled because it makes slightly more sense this way. 3024 * The DP83815 stores the MAC address in bit 0 of word 6 3025 * through bit 15 of word 8. 3026 */ 3027 ea = &eeprom_data[6]; 3028 enaddr[0] = ((*ea & 0x1) << 7); 3029 ea++; 3030 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3031 enaddr[1] = ((*ea & 0x1FE) >> 1); 3032 enaddr[2] = ((*ea & 0x1) << 7); 3033 ea++; 3034 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3035 enaddr[3] = ((*ea & 0x1FE) >> 1); 3036 enaddr[4] = ((*ea & 0x1) << 7); 3037 ea++; 3038 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3039 enaddr[5] = ((*ea & 0x1FE) >> 1); 3040 3041 /* 3042 * In case that's not weird enough, we also need to reverse 3043 * the bits in each byte. This all actually makes more sense 3044 * if you think about the EEPROM storage as an array of bits 3045 * being shifted into bytes, but that's not how we're looking 3046 * at it here... 3047 */ 3048 for (i = 0; i < 6 ;i++) 3049 enaddr[i] = bbr(enaddr[i]); 3050 } 3051 #endif /* DP83820 */ 3052 3053 /* 3054 * sip_mediastatus: [ifmedia interface function] 3055 * 3056 * Get the current interface media status. 3057 */ 3058 void 3059 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3060 { 3061 struct sip_softc *sc = ifp->if_softc; 3062 3063 mii_pollstat(&sc->sc_mii); 3064 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3065 ifmr->ifm_active = sc->sc_mii.mii_media_active; 3066 } 3067 3068 /* 3069 * sip_mediachange: [ifmedia interface function] 3070 * 3071 * Set hardware to newly-selected media. 3072 */ 3073 int 3074 SIP_DECL(mediachange)(struct ifnet *ifp) 3075 { 3076 struct sip_softc *sc = ifp->if_softc; 3077 3078 if (ifp->if_flags & IFF_UP) 3079 mii_mediachg(&sc->sc_mii); 3080 return (0); 3081 } 3082
Indexes created Tue Sep 30 11:09:46 GMT 2025