if_sip.c revision 1.40.2.2
1 /* $NetBSD: if_sip.c,v 1.40.2.2 2002/01/10 19:56:43 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Support the 10-bit interface on the DP83820 (for fiber). 80 * 81 * - Reduce the interrupt load. 82 */ 83 84 #include <sys/cdefs.h> 85 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.40.2.2 2002/01/10 19:56:43 thorpej Exp $"); 86 87 #include "bpfilter.h" 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/callout.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/ioctl.h> 97 #include <sys/errno.h> 98 #include <sys/device.h> 99 #include <sys/queue.h> 100 101 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 102 103 #include <net/if.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 #include <net/if_ether.h> 107 108 #if NBPFILTER > 0 109 #include <net/bpf.h> 110 #endif 111 112 #include <machine/bus.h> 113 #include <machine/intr.h> 114 #include <machine/endian.h> 115 116 #include <dev/mii/mii.h> 117 #include <dev/mii/miivar.h> 118 #ifdef DP83820 119 #include <dev/mii/mii_bitbang.h> 120 #endif /* DP83820 */ 121 122 #include <dev/pci/pcireg.h> 123 #include <dev/pci/pcivar.h> 124 #include <dev/pci/pcidevs.h> 125 126 #include <dev/pci/if_sipreg.h> 127 128 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 129 #define SIP_DECL(x) __CONCAT(gsip_,x) 130 #else /* SiS900 and DP83815 */ 131 #define SIP_DECL(x) __CONCAT(sip_,x) 132 #endif 133 134 #define SIP_STR(x) __STRING(SIP_DECL(x)) 135 136 /* 137 * Transmit descriptor list size. This is arbitrary, but allocate 138 * enough descriptors for 128 pending transmissions, and 8 segments 139 * per packet. This MUST work out to a power of 2. 140 */ 141 #define SIP_NTXSEGS 8 142 143 #define SIP_TXQUEUELEN 256 144 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS) 145 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 146 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 147 148 /* 149 * Receive descriptor list size. We have one Rx buffer per incoming 150 * packet, so this logic is a little simpler. 151 * 152 * Actually, on the DP83820, we allow the packet to consume more than 153 * one buffer, in order to support jumbo Ethernet frames. In that 154 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 155 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 156 * so we'd better be quick about handling receive interrupts. 157 */ 158 #if defined(DP83820) 159 #define SIP_NRXDESC 256 160 #else 161 #define SIP_NRXDESC 128 162 #endif /* DP83820 */ 163 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 164 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 165 166 /* 167 * Control structures are DMA'd to the SiS900 chip. We allocate them in 168 * a single clump that maps to a single DMA segment to make several things 169 * easier. 170 */ 171 struct sip_control_data { 172 /* 173 * The transmit descriptors. 174 */ 175 struct sip_desc scd_txdescs[SIP_NTXDESC]; 176 177 /* 178 * The receive descriptors. 179 */ 180 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 181 }; 182 183 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 184 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 185 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 186 187 /* 188 * Software state for transmit jobs. 189 */ 190 struct sip_txsoft { 191 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 192 bus_dmamap_t txs_dmamap; /* our DMA map */ 193 int txs_firstdesc; /* first descriptor in packet */ 194 int txs_lastdesc; /* last descriptor in packet */ 195 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 196 }; 197 198 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 199 200 /* 201 * Software state for receive jobs. 202 */ 203 struct sip_rxsoft { 204 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 205 bus_dmamap_t rxs_dmamap; /* our DMA map */ 206 }; 207 208 /* 209 * Software state per device. 210 */ 211 struct sip_softc { 212 struct device sc_dev; /* generic device information */ 213 bus_space_tag_t sc_st; /* bus space tag */ 214 bus_space_handle_t sc_sh; /* bus space handle */ 215 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 216 struct ethercom sc_ethercom; /* ethernet common data */ 217 void *sc_sdhook; /* shutdown hook */ 218 219 const struct sip_product *sc_model; /* which model are we? */ 220 221 void *sc_ih; /* interrupt cookie */ 222 223 struct mii_data sc_mii; /* MII/media information */ 224 225 struct callout sc_tick_ch; /* tick callout */ 226 227 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 228 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 229 230 /* 231 * Software state for transmit and receive descriptors. 232 */ 233 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 234 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 235 236 /* 237 * Control data structures. 238 */ 239 struct sip_control_data *sc_control_data; 240 #define sc_txdescs sc_control_data->scd_txdescs 241 #define sc_rxdescs sc_control_data->scd_rxdescs 242 243 #ifdef SIP_EVENT_COUNTERS 244 /* 245 * Event counters. 246 */ 247 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 248 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 249 struct evcnt sc_ev_txintr; /* Tx interrupts */ 250 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 251 #ifdef DP83820 252 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 253 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 254 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 255 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 256 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 257 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 258 #endif /* DP83820 */ 259 #endif /* SIP_EVENT_COUNTERS */ 260 261 u_int32_t sc_txcfg; /* prototype TXCFG register */ 262 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 263 u_int32_t sc_imr; /* prototype IMR register */ 264 u_int32_t sc_rfcr; /* prototype RFCR register */ 265 266 u_int32_t sc_cfg; /* prototype CFG register */ 267 268 #ifdef DP83820 269 u_int32_t sc_gpior; /* prototype GPIOR register */ 270 #endif /* DP83820 */ 271 272 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 273 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 274 275 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 276 277 int sc_flags; /* misc. flags; see below */ 278 279 int sc_txfree; /* number of free Tx descriptors */ 280 int sc_txnext; /* next ready Tx descriptor */ 281 282 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 283 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 284 285 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 286 #if defined(DP83820) 287 int sc_rxdiscard; 288 int sc_rxlen; 289 struct mbuf *sc_rxhead; 290 struct mbuf *sc_rxtail; 291 struct mbuf **sc_rxtailp; 292 #endif /* DP83820 */ 293 }; 294 295 /* sc_flags */ 296 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 297 298 #ifdef DP83820 299 #define SIP_RXCHAIN_RESET(sc) \ 300 do { \ 301 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 302 *(sc)->sc_rxtailp = NULL; \ 303 (sc)->sc_rxlen = 0; \ 304 } while (/*CONSTCOND*/0) 305 306 #define SIP_RXCHAIN_LINK(sc, m) \ 307 do { \ 308 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 309 (sc)->sc_rxtailp = &(m)->m_next; \ 310 } while (/*CONSTCOND*/0) 311 #endif /* DP83820 */ 312 313 #ifdef SIP_EVENT_COUNTERS 314 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 315 #else 316 #define SIP_EVCNT_INCR(ev) /* nothing */ 317 #endif 318 319 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 320 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 321 322 #define SIP_CDTXSYNC(sc, x, n, ops) \ 323 do { \ 324 int __x, __n; \ 325 \ 326 __x = (x); \ 327 __n = (n); \ 328 \ 329 /* If it will wrap around, sync to the end of the ring. */ \ 330 if ((__x + __n) > SIP_NTXDESC) { \ 331 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 332 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 333 (SIP_NTXDESC - __x), (ops)); \ 334 __n -= (SIP_NTXDESC - __x); \ 335 __x = 0; \ 336 } \ 337 \ 338 /* Now sync whatever is left. */ \ 339 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 340 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 341 } while (0) 342 343 #define SIP_CDRXSYNC(sc, x, ops) \ 344 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 345 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 346 347 #ifdef DP83820 348 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 349 #define SIP_RXBUF_LEN (MCLBYTES - 4) 350 #else 351 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 352 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 353 #endif 354 #define SIP_INIT_RXDESC(sc, x) \ 355 do { \ 356 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 357 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 358 \ 359 __sipd->sipd_link = \ 360 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 361 __sipd->sipd_bufptr = \ 362 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 363 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 364 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 365 SIP_INIT_RXDESC_EXTSTS \ 366 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 367 } while (0) 368 369 #define SIP_TIMEOUT 1000 370 371 void SIP_DECL(start)(struct ifnet *); 372 void SIP_DECL(watchdog)(struct ifnet *); 373 int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 374 int SIP_DECL(init)(struct ifnet *); 375 void SIP_DECL(stop)(struct ifnet *, int); 376 377 void SIP_DECL(shutdown)(void *); 378 379 void SIP_DECL(reset)(struct sip_softc *); 380 void SIP_DECL(rxdrain)(struct sip_softc *); 381 int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 382 void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, u_int16_t *); 383 void SIP_DECL(tick)(void *); 384 385 #if !defined(DP83820) 386 void SIP_DECL(sis900_set_filter)(struct sip_softc *); 387 #endif /* ! DP83820 */ 388 void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 389 390 #if defined(DP83820) 391 void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 392 const struct pci_attach_args *, u_int8_t *); 393 #else 394 void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 395 const struct pci_attach_args *, u_int8_t *); 396 void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 397 const struct pci_attach_args *, u_int8_t *); 398 #endif /* DP83820 */ 399 400 int SIP_DECL(intr)(void *); 401 void SIP_DECL(txintr)(struct sip_softc *); 402 void SIP_DECL(rxintr)(struct sip_softc *); 403 404 #if defined(DP83820) 405 int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 406 void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 407 void SIP_DECL(dp83820_mii_statchg)(struct device *); 408 #else 409 int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 410 void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 411 void SIP_DECL(sis900_mii_statchg)(struct device *); 412 413 int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 414 void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 415 void SIP_DECL(dp83815_mii_statchg)(struct device *); 416 #endif /* DP83820 */ 417 418 int SIP_DECL(mediachange)(struct ifnet *); 419 void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 420 421 int SIP_DECL(match)(struct device *, struct cfdata *, void *); 422 void SIP_DECL(attach)(struct device *, struct device *, void *); 423 424 int SIP_DECL(copy_small) = 0; 425 426 struct cfattach SIP_DECL(ca) = { 427 sizeof(struct sip_softc), SIP_DECL(match), SIP_DECL(attach), 428 }; 429 430 /* 431 * Descriptions of the variants of the SiS900. 432 */ 433 struct sip_variant { 434 int (*sipv_mii_readreg)(struct device *, int, int); 435 void (*sipv_mii_writereg)(struct device *, int, int, int); 436 void (*sipv_mii_statchg)(struct device *); 437 void (*sipv_set_filter)(struct sip_softc *); 438 void (*sipv_read_macaddr)(struct sip_softc *, 439 const struct pci_attach_args *, u_int8_t *); 440 }; 441 442 #if defined(DP83820) 443 u_int32_t SIP_DECL(dp83820_mii_bitbang_read)(struct device *); 444 void SIP_DECL(dp83820_mii_bitbang_write)(struct device *, u_int32_t); 445 446 const struct mii_bitbang_ops SIP_DECL(dp83820_mii_bitbang_ops) = { 447 SIP_DECL(dp83820_mii_bitbang_read), 448 SIP_DECL(dp83820_mii_bitbang_write), 449 { 450 EROMAR_MDIO, /* MII_BIT_MDO */ 451 EROMAR_MDIO, /* MII_BIT_MDI */ 452 EROMAR_MDC, /* MII_BIT_MDC */ 453 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 454 0, /* MII_BIT_DIR_PHY_HOST */ 455 } 456 }; 457 #endif /* DP83820 */ 458 459 #if defined(DP83820) 460 const struct sip_variant SIP_DECL(variant_dp83820) = { 461 SIP_DECL(dp83820_mii_readreg), 462 SIP_DECL(dp83820_mii_writereg), 463 SIP_DECL(dp83820_mii_statchg), 464 SIP_DECL(dp83815_set_filter), 465 SIP_DECL(dp83820_read_macaddr), 466 }; 467 #else 468 const struct sip_variant SIP_DECL(variant_sis900) = { 469 SIP_DECL(sis900_mii_readreg), 470 SIP_DECL(sis900_mii_writereg), 471 SIP_DECL(sis900_mii_statchg), 472 SIP_DECL(sis900_set_filter), 473 SIP_DECL(sis900_read_macaddr), 474 }; 475 476 const struct sip_variant SIP_DECL(variant_dp83815) = { 477 SIP_DECL(dp83815_mii_readreg), 478 SIP_DECL(dp83815_mii_writereg), 479 SIP_DECL(dp83815_mii_statchg), 480 SIP_DECL(dp83815_set_filter), 481 SIP_DECL(dp83815_read_macaddr), 482 }; 483 #endif /* DP83820 */ 484 485 /* 486 * Devices supported by this driver. 487 */ 488 const struct sip_product { 489 pci_vendor_id_t sip_vendor; 490 pci_product_id_t sip_product; 491 const char *sip_name; 492 const struct sip_variant *sip_variant; 493 } SIP_DECL(products)[] = { 494 #if defined(DP83820) 495 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 496 "NatSemi DP83820 Gigabit Ethernet", 497 &SIP_DECL(variant_dp83820) }, 498 #else 499 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 500 "SiS 900 10/100 Ethernet", 501 &SIP_DECL(variant_sis900) }, 502 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 503 "SiS 7016 10/100 Ethernet", 504 &SIP_DECL(variant_sis900) }, 505 506 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 507 "NatSemi DP83815 10/100 Ethernet", 508 &SIP_DECL(variant_dp83815) }, 509 #endif /* DP83820 */ 510 511 { 0, 0, 512 NULL, 513 NULL }, 514 }; 515 516 static const struct sip_product * 517 SIP_DECL(lookup)(const struct pci_attach_args *pa) 518 { 519 const struct sip_product *sip; 520 521 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 522 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 523 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 524 return (sip); 525 } 526 return (NULL); 527 } 528 529 int 530 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 531 { 532 struct pci_attach_args *pa = aux; 533 534 if (SIP_DECL(lookup)(pa) != NULL) 535 return (1); 536 537 return (0); 538 } 539 540 void 541 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 542 { 543 struct sip_softc *sc = (struct sip_softc *) self; 544 struct pci_attach_args *pa = aux; 545 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 546 pci_chipset_tag_t pc = pa->pa_pc; 547 pci_intr_handle_t ih; 548 const char *intrstr = NULL; 549 bus_space_tag_t iot, memt; 550 bus_space_handle_t ioh, memh; 551 bus_dma_segment_t seg; 552 int ioh_valid, memh_valid; 553 int i, rseg, error; 554 const struct sip_product *sip; 555 pcireg_t pmode; 556 u_int8_t enaddr[ETHER_ADDR_LEN]; 557 int pmreg; 558 #ifdef DP83820 559 pcireg_t memtype; 560 u_int32_t reg; 561 #endif /* DP83820 */ 562 563 callout_init(&sc->sc_tick_ch); 564 565 sip = SIP_DECL(lookup)(pa); 566 if (sip == NULL) { 567 printf("\n"); 568 panic(SIP_STR(attach) ": impossible"); 569 } 570 571 printf(": %s\n", sip->sip_name); 572 573 sc->sc_model = sip; 574 575 /* 576 * Map the device. 577 */ 578 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 579 PCI_MAPREG_TYPE_IO, 0, 580 &iot, &ioh, NULL, NULL) == 0); 581 #ifdef DP83820 582 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 583 switch (memtype) { 584 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 585 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 586 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 587 memtype, 0, &memt, &memh, NULL, NULL) == 0); 588 break; 589 default: 590 memh_valid = 0; 591 } 592 #else 593 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 594 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 595 &memt, &memh, NULL, NULL) == 0); 596 #endif /* DP83820 */ 597 598 if (memh_valid) { 599 printf("%s: using memory mapped registers\n", sc->sc_dev.dv_xname); 600 sc->sc_st = memt; 601 sc->sc_sh = memh; 602 } else if (ioh_valid) { 603 printf("%s: using I/O mapped registers\n", sc->sc_dev.dv_xname); 604 sc->sc_st = iot; 605 sc->sc_sh = ioh; 606 } else { 607 printf("%s: unable to map device registers\n", 608 sc->sc_dev.dv_xname); 609 return; 610 } 611 612 sc->sc_dmat = pa->pa_dmat; 613 614 /* Enable bus mastering. */ 615 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 616 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 617 PCI_COMMAND_MASTER_ENABLE); 618 619 /* Get it out of power save mode if needed. */ 620 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 621 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 622 if (pmode == 3) { 623 /* 624 * The card has lost all configuration data in 625 * this state, so punt. 626 */ 627 printf("%s: unable to wake up from power state D3\n", 628 sc->sc_dev.dv_xname); 629 return; 630 } 631 if (pmode != 0) { 632 printf("%s: waking up from power state D%d\n", 633 sc->sc_dev.dv_xname, pmode); 634 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 635 } 636 } 637 638 /* 639 * Map and establish our interrupt. 640 */ 641 if (pci_intr_map(pa, &ih)) { 642 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 643 return; 644 } 645 intrstr = pci_intr_string(pc, ih); 646 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 647 if (sc->sc_ih == NULL) { 648 printf("%s: unable to establish interrupt", 649 sc->sc_dev.dv_xname); 650 if (intrstr != NULL) 651 printf(" at %s", intrstr); 652 printf("\n"); 653 return; 654 } 655 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 656 657 SIMPLEQ_INIT(&sc->sc_txfreeq); 658 SIMPLEQ_INIT(&sc->sc_txdirtyq); 659 660 /* 661 * Allocate the control data structures, and create and load the 662 * DMA map for it. 663 */ 664 if ((error = bus_dmamem_alloc(sc->sc_dmat, 665 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 666 0)) != 0) { 667 printf("%s: unable to allocate control data, error = %d\n", 668 sc->sc_dev.dv_xname, error); 669 goto fail_0; 670 } 671 672 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 673 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 674 BUS_DMA_COHERENT)) != 0) { 675 printf("%s: unable to map control data, error = %d\n", 676 sc->sc_dev.dv_xname, error); 677 goto fail_1; 678 } 679 680 if ((error = bus_dmamap_create(sc->sc_dmat, 681 sizeof(struct sip_control_data), 1, 682 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 683 printf("%s: unable to create control data DMA map, " 684 "error = %d\n", sc->sc_dev.dv_xname, error); 685 goto fail_2; 686 } 687 688 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 689 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 690 0)) != 0) { 691 printf("%s: unable to load control data DMA map, error = %d\n", 692 sc->sc_dev.dv_xname, error); 693 goto fail_3; 694 } 695 696 /* 697 * Create the transmit buffer DMA maps. 698 */ 699 for (i = 0; i < SIP_TXQUEUELEN; i++) { 700 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 701 SIP_NTXSEGS, MCLBYTES, 0, 0, 702 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 703 printf("%s: unable to create tx DMA map %d, " 704 "error = %d\n", sc->sc_dev.dv_xname, i, error); 705 goto fail_4; 706 } 707 } 708 709 /* 710 * Create the receive buffer DMA maps. 711 */ 712 for (i = 0; i < SIP_NRXDESC; i++) { 713 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 714 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 715 printf("%s: unable to create rx DMA map %d, " 716 "error = %d\n", sc->sc_dev.dv_xname, i, error); 717 goto fail_5; 718 } 719 sc->sc_rxsoft[i].rxs_mbuf = NULL; 720 } 721 722 /* 723 * Reset the chip to a known state. 724 */ 725 SIP_DECL(reset)(sc); 726 727 /* 728 * Read the Ethernet address from the EEPROM. This might 729 * also fetch other stuff from the EEPROM and stash it 730 * in the softc. 731 */ 732 sc->sc_cfg = 0; 733 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 734 735 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 736 ether_sprintf(enaddr)); 737 738 /* 739 * Initialize the configuration register: aggressive PCI 740 * bus request algorithm, default backoff, default OW timer, 741 * default parity error detection. 742 * 743 * NOTE: "Big endian mode" is useless on the SiS900 and 744 * friends -- it affects packet data, not descriptors. 745 */ 746 #ifdef DP83820 747 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 748 if (reg & CFG_PCI64_DET) { 749 printf("%s: 64-bit PCI slot detected\n", sc->sc_dev.dv_xname); 750 /* 751 * XXX Need some PCI flags indicating support for 752 * XXX 64-bit addressing (SAC or DAC) and 64-bit 753 * XXX data path. 754 */ 755 } 756 if (sc->sc_cfg & (CFG_TBI_EN|CFG_EXT_125)) { 757 const char *sep = ""; 758 printf("%s: using ", sc->sc_dev.dv_xname); 759 if (sc->sc_cfg & CFG_EXT_125) { 760 printf("%s125MHz clock", sep); 761 sep = ", "; 762 } 763 if (sc->sc_cfg & CFG_TBI_EN) { 764 printf("%sten-bit interface", sep); 765 sep = ", "; 766 } 767 printf("\n"); 768 } 769 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0) 770 sc->sc_cfg |= CFG_MRM_DIS; 771 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 772 sc->sc_cfg |= CFG_MWI_DIS; 773 774 /* 775 * Use the extended descriptor format on the DP83820. This 776 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 777 * checksumming. 778 */ 779 sc->sc_cfg |= CFG_EXTSTS_EN; 780 #endif /* DP83820 */ 781 782 /* 783 * Initialize our media structures and probe the MII. 784 */ 785 sc->sc_mii.mii_ifp = ifp; 786 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 787 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 788 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 789 ifmedia_init(&sc->sc_mii.mii_media, 0, SIP_DECL(mediachange), 790 SIP_DECL(mediastatus)); 791 #ifdef DP83820 792 if (sc->sc_cfg & CFG_TBI_EN) { 793 /* Using ten-bit interface. */ 794 printf("%s: TBI -- FIXME\n", sc->sc_dev.dv_xname); 795 } else { 796 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 797 MII_OFFSET_ANY, 0); 798 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 799 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 800 0, NULL); 801 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 802 } else 803 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 804 } 805 #else 806 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 807 MII_OFFSET_ANY, 0); 808 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 809 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 810 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 811 } else 812 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 813 #endif /* DP83820 */ 814 815 ifp = &sc->sc_ethercom.ec_if; 816 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 817 ifp->if_softc = sc; 818 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 819 ifp->if_ioctl = SIP_DECL(ioctl); 820 ifp->if_start = SIP_DECL(start); 821 ifp->if_watchdog = SIP_DECL(watchdog); 822 ifp->if_init = SIP_DECL(init); 823 ifp->if_stop = SIP_DECL(stop); 824 IFQ_SET_READY(&ifp->if_snd); 825 826 /* 827 * We can support 802.1Q VLAN-sized frames. 828 */ 829 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 830 831 #ifdef DP83820 832 /* 833 * And the DP83820 can do VLAN tagging in hardware, and 834 * support the jumbo Ethernet MTU. 835 */ 836 sc->sc_ethercom.ec_capabilities |= 837 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 838 839 /* 840 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 841 * in hardware. 842 */ 843 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 844 IFCAP_CSUM_UDPv4; 845 #endif /* DP83820 */ 846 847 /* 848 * Attach the interface. 849 */ 850 if_attach(ifp); 851 ether_ifattach(ifp, enaddr); 852 853 #ifdef SIP_EVENT_COUNTERS 854 /* 855 * Attach event counters. 856 */ 857 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 858 NULL, sc->sc_dev.dv_xname, "txsstall"); 859 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 860 NULL, sc->sc_dev.dv_xname, "txdstall"); 861 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 862 NULL, sc->sc_dev.dv_xname, "txintr"); 863 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 864 NULL, sc->sc_dev.dv_xname, "rxintr"); 865 #ifdef DP83820 866 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 867 NULL, sc->sc_dev.dv_xname, "rxipsum"); 868 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 869 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 870 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 871 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 872 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 873 NULL, sc->sc_dev.dv_xname, "txipsum"); 874 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 875 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 876 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 877 NULL, sc->sc_dev.dv_xname, "txudpsum"); 878 #endif /* DP83820 */ 879 #endif /* SIP_EVENT_COUNTERS */ 880 881 /* 882 * Make sure the interface is shutdown during reboot. 883 */ 884 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 885 if (sc->sc_sdhook == NULL) 886 printf("%s: WARNING: unable to establish shutdown hook\n", 887 sc->sc_dev.dv_xname); 888 return; 889 890 /* 891 * Free any resources we've allocated during the failed attach 892 * attempt. Do this in reverse order and fall through. 893 */ 894 fail_5: 895 for (i = 0; i < SIP_NRXDESC; i++) { 896 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 897 bus_dmamap_destroy(sc->sc_dmat, 898 sc->sc_rxsoft[i].rxs_dmamap); 899 } 900 fail_4: 901 for (i = 0; i < SIP_TXQUEUELEN; i++) { 902 if (sc->sc_txsoft[i].txs_dmamap != NULL) 903 bus_dmamap_destroy(sc->sc_dmat, 904 sc->sc_txsoft[i].txs_dmamap); 905 } 906 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 907 fail_3: 908 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 909 fail_2: 910 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 911 sizeof(struct sip_control_data)); 912 fail_1: 913 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 914 fail_0: 915 return; 916 } 917 918 /* 919 * sip_shutdown: 920 * 921 * Make sure the interface is stopped at reboot time. 922 */ 923 void 924 SIP_DECL(shutdown)(void *arg) 925 { 926 struct sip_softc *sc = arg; 927 928 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 929 } 930 931 /* 932 * sip_start: [ifnet interface function] 933 * 934 * Start packet transmission on the interface. 935 */ 936 void 937 SIP_DECL(start)(struct ifnet *ifp) 938 { 939 struct sip_softc *sc = ifp->if_softc; 940 struct mbuf *m0, *m; 941 struct sip_txsoft *txs; 942 bus_dmamap_t dmamap; 943 int error, firsttx, nexttx, lasttx, ofree, seg; 944 #ifdef DP83820 945 u_int32_t extsts; 946 #endif 947 948 /* 949 * If we've been told to pause, don't transmit any more packets. 950 */ 951 if (sc->sc_flags & SIPF_PAUSED) 952 ifp->if_flags |= IFF_OACTIVE; 953 954 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 955 return; 956 957 /* 958 * Remember the previous number of free descriptors and 959 * the first descriptor we'll use. 960 */ 961 ofree = sc->sc_txfree; 962 firsttx = sc->sc_txnext; 963 964 /* 965 * Loop through the send queue, setting up transmit descriptors 966 * until we drain the queue, or use up all available transmit 967 * descriptors. 968 */ 969 for (;;) { 970 /* Get a work queue entry. */ 971 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 972 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 973 break; 974 } 975 976 /* 977 * Grab a packet off the queue. 978 */ 979 IFQ_POLL(&ifp->if_snd, m0); 980 if (m0 == NULL) 981 break; 982 #ifndef DP83820 983 m = NULL; 984 #endif 985 986 dmamap = txs->txs_dmamap; 987 988 #ifdef DP83820 989 /* 990 * Load the DMA map. If this fails, the packet either 991 * didn't fit in the allotted number of segments, or we 992 * were short on resources. For the too-many-segments 993 * case, we simply report an error and drop the packet, 994 * since we can't sanely copy a jumbo packet to a single 995 * buffer. 996 */ 997 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 998 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 999 if (error) { 1000 if (error == EFBIG) { 1001 printf("%s: Tx packet consumes too many " 1002 "DMA segments, dropping...\n", 1003 sc->sc_dev.dv_xname); 1004 IFQ_DEQUEUE(&ifp->if_snd, m0); 1005 m_freem(m0); 1006 continue; 1007 } 1008 /* 1009 * Short on resources, just stop for now. 1010 */ 1011 break; 1012 } 1013 #else /* DP83820 */ 1014 /* 1015 * Load the DMA map. If this fails, the packet either 1016 * didn't fit in the alloted number of segments, or we 1017 * were short on resources. In this case, we'll copy 1018 * and try again. 1019 */ 1020 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1021 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1022 MGETHDR(m, M_DONTWAIT, MT_DATA); 1023 if (m == NULL) { 1024 printf("%s: unable to allocate Tx mbuf\n", 1025 sc->sc_dev.dv_xname); 1026 break; 1027 } 1028 if (m0->m_pkthdr.len > MHLEN) { 1029 MCLGET(m, M_DONTWAIT); 1030 if ((m->m_flags & M_EXT) == 0) { 1031 printf("%s: unable to allocate Tx " 1032 "cluster\n", sc->sc_dev.dv_xname); 1033 m_freem(m); 1034 break; 1035 } 1036 } 1037 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1038 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1039 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1040 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1041 if (error) { 1042 printf("%s: unable to load Tx buffer, " 1043 "error = %d\n", sc->sc_dev.dv_xname, error); 1044 break; 1045 } 1046 } 1047 #endif /* DP83820 */ 1048 1049 /* 1050 * Ensure we have enough descriptors free to describe 1051 * the packet. Note, we always reserve one descriptor 1052 * at the end of the ring as a termination point, to 1053 * prevent wrap-around. 1054 */ 1055 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1056 /* 1057 * Not enough free descriptors to transmit this 1058 * packet. We haven't committed anything yet, 1059 * so just unload the DMA map, put the packet 1060 * back on the queue, and punt. Notify the upper 1061 * layer that there are not more slots left. 1062 * 1063 * XXX We could allocate an mbuf and copy, but 1064 * XXX is it worth it? 1065 */ 1066 ifp->if_flags |= IFF_OACTIVE; 1067 bus_dmamap_unload(sc->sc_dmat, dmamap); 1068 #ifndef DP83820 1069 if (m != NULL) 1070 m_freem(m); 1071 #endif 1072 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1073 break; 1074 } 1075 1076 IFQ_DEQUEUE(&ifp->if_snd, m0); 1077 #ifndef DP83820 1078 if (m != NULL) { 1079 m_freem(m0); 1080 m0 = m; 1081 } 1082 #endif 1083 1084 /* 1085 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1086 */ 1087 1088 /* Sync the DMA map. */ 1089 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1090 BUS_DMASYNC_PREWRITE); 1091 1092 /* 1093 * Initialize the transmit descriptors. 1094 */ 1095 for (nexttx = sc->sc_txnext, seg = 0; 1096 seg < dmamap->dm_nsegs; 1097 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1098 /* 1099 * If this is the first descriptor we're 1100 * enqueueing, don't set the OWN bit just 1101 * yet. That could cause a race condition. 1102 * We'll do it below. 1103 */ 1104 sc->sc_txdescs[nexttx].sipd_bufptr = 1105 htole32(dmamap->dm_segs[seg].ds_addr); 1106 sc->sc_txdescs[nexttx].sipd_cmdsts = 1107 htole32((nexttx == firsttx ? 0 : CMDSTS_OWN) | 1108 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1109 #ifdef DP83820 1110 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1111 #endif /* DP83820 */ 1112 lasttx = nexttx; 1113 } 1114 1115 /* Clear the MORE bit on the last segment. */ 1116 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1117 1118 #ifdef DP83820 1119 /* 1120 * If VLANs are enabled and the packet has a VLAN tag, set 1121 * up the descriptor to encapsulate the packet for us. 1122 * 1123 * This apparently has to be on the last descriptor of 1124 * the packet. 1125 */ 1126 if (sc->sc_ethercom.ec_nvlans != 0 && 1127 (m = m_aux_find(m0, AF_LINK, ETHERTYPE_VLAN)) != NULL) { 1128 sc->sc_txdescs[lasttx].sipd_extsts |= 1129 htole32(EXTSTS_VPKT | 1130 htons(*mtod(m, int *) & EXTSTS_VTCI)); 1131 } 1132 1133 /* 1134 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1135 * checksumming, set up the descriptor to do this work 1136 * for us. 1137 * 1138 * This apparently has to be on the first descriptor of 1139 * the packet. 1140 * 1141 * Byte-swap constants so the compiler can optimize. 1142 */ 1143 extsts = 0; 1144 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1145 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1146 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1147 extsts |= htole32(EXTSTS_IPPKT); 1148 } 1149 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1150 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1151 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1152 extsts |= htole32(EXTSTS_TCPPKT); 1153 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1154 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1155 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1156 extsts |= htole32(EXTSTS_UDPPKT); 1157 } 1158 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1159 #endif /* DP83820 */ 1160 1161 /* Sync the descriptors we're using. */ 1162 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1163 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1164 1165 /* 1166 * Store a pointer to the packet so we can free it later, 1167 * and remember what txdirty will be once the packet is 1168 * done. 1169 */ 1170 txs->txs_mbuf = m0; 1171 txs->txs_firstdesc = sc->sc_txnext; 1172 txs->txs_lastdesc = lasttx; 1173 1174 /* Advance the tx pointer. */ 1175 sc->sc_txfree -= dmamap->dm_nsegs; 1176 sc->sc_txnext = nexttx; 1177 1178 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs, txs_q); 1179 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1180 1181 #if NBPFILTER > 0 1182 /* 1183 * Pass the packet to any BPF listeners. 1184 */ 1185 if (ifp->if_bpf) 1186 bpf_mtap(ifp->if_bpf, m0); 1187 #endif /* NBPFILTER > 0 */ 1188 } 1189 1190 if (txs == NULL || sc->sc_txfree == 0) { 1191 /* No more slots left; notify upper layer. */ 1192 ifp->if_flags |= IFF_OACTIVE; 1193 } 1194 1195 if (sc->sc_txfree != ofree) { 1196 /* 1197 * Cause a descriptor interrupt to happen on the 1198 * last packet we enqueued. 1199 */ 1200 sc->sc_txdescs[lasttx].sipd_cmdsts |= htole32(CMDSTS_INTR); 1201 SIP_CDTXSYNC(sc, lasttx, 1, 1202 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1203 1204 /* 1205 * The entire packet chain is set up. Give the 1206 * first descrptor to the chip now. 1207 */ 1208 sc->sc_txdescs[firsttx].sipd_cmdsts |= htole32(CMDSTS_OWN); 1209 SIP_CDTXSYNC(sc, firsttx, 1, 1210 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1211 1212 /* 1213 * Start the transmit process. Note, the manual says 1214 * that if there are no pending transmissions in the 1215 * chip's internal queue (indicated by TXE being clear), 1216 * then the driver software must set the TXDP to the 1217 * first descriptor to be transmitted. However, if we 1218 * do this, it causes serious performance degredation on 1219 * the DP83820 under load, not setting TXDP doesn't seem 1220 * to adversely affect the SiS 900 or DP83815. 1221 * 1222 * Well, I guess it wouldn't be the first time a manual 1223 * has lied -- and they could be speaking of the NULL- 1224 * terminated descriptor list case, rather than OWN- 1225 * terminated rings. 1226 */ 1227 #if 0 1228 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1229 CR_TXE) == 0) { 1230 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1231 SIP_CDTXADDR(sc, firsttx)); 1232 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1233 } 1234 #else 1235 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1236 #endif 1237 1238 /* Set a watchdog timer in case the chip flakes out. */ 1239 ifp->if_timer = 5; 1240 } 1241 } 1242 1243 /* 1244 * sip_watchdog: [ifnet interface function] 1245 * 1246 * Watchdog timer handler. 1247 */ 1248 void 1249 SIP_DECL(watchdog)(struct ifnet *ifp) 1250 { 1251 struct sip_softc *sc = ifp->if_softc; 1252 1253 /* 1254 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1255 * If we get a timeout, try and sweep up transmit descriptors. 1256 * If we manage to sweep them all up, ignore the lack of 1257 * interrupt. 1258 */ 1259 SIP_DECL(txintr)(sc); 1260 1261 if (sc->sc_txfree != SIP_NTXDESC) { 1262 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1263 ifp->if_oerrors++; 1264 1265 /* Reset the interface. */ 1266 (void) SIP_DECL(init)(ifp); 1267 } else if (ifp->if_flags & IFF_DEBUG) 1268 printf("%s: recovered from device timeout\n", 1269 sc->sc_dev.dv_xname); 1270 1271 /* Try to get more packets going. */ 1272 SIP_DECL(start)(ifp); 1273 } 1274 1275 /* 1276 * sip_ioctl: [ifnet interface function] 1277 * 1278 * Handle control requests from the operator. 1279 */ 1280 int 1281 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1282 { 1283 struct sip_softc *sc = ifp->if_softc; 1284 struct ifreq *ifr = (struct ifreq *)data; 1285 int s, error; 1286 1287 s = splnet(); 1288 1289 switch (cmd) { 1290 case SIOCSIFMEDIA: 1291 case SIOCGIFMEDIA: 1292 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1293 break; 1294 1295 default: 1296 error = ether_ioctl(ifp, cmd, data); 1297 if (error == ENETRESET) { 1298 /* 1299 * Multicast list has changed; set the hardware filter 1300 * accordingly. 1301 */ 1302 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1303 error = 0; 1304 } 1305 break; 1306 } 1307 1308 /* Try to get more packets going. */ 1309 SIP_DECL(start)(ifp); 1310 1311 splx(s); 1312 return (error); 1313 } 1314 1315 /* 1316 * sip_intr: 1317 * 1318 * Interrupt service routine. 1319 */ 1320 int 1321 SIP_DECL(intr)(void *arg) 1322 { 1323 struct sip_softc *sc = arg; 1324 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1325 u_int32_t isr; 1326 int handled = 0; 1327 1328 for (;;) { 1329 /* Reading clears interrupt. */ 1330 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1331 if ((isr & sc->sc_imr) == 0) 1332 break; 1333 1334 handled = 1; 1335 1336 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1337 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1338 1339 /* Grab any new packets. */ 1340 SIP_DECL(rxintr)(sc); 1341 1342 if (isr & ISR_RXORN) { 1343 printf("%s: receive FIFO overrun\n", 1344 sc->sc_dev.dv_xname); 1345 1346 /* XXX adjust rx_drain_thresh? */ 1347 } 1348 1349 if (isr & ISR_RXIDLE) { 1350 printf("%s: receive ring overrun\n", 1351 sc->sc_dev.dv_xname); 1352 1353 /* Get the receive process going again. */ 1354 bus_space_write_4(sc->sc_st, sc->sc_sh, 1355 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1356 bus_space_write_4(sc->sc_st, sc->sc_sh, 1357 SIP_CR, CR_RXE); 1358 } 1359 } 1360 1361 if (isr & (ISR_TXURN|ISR_TXDESC)) { 1362 SIP_EVCNT_INCR(&sc->sc_ev_txintr); 1363 1364 /* Sweep up transmit descriptors. */ 1365 SIP_DECL(txintr)(sc); 1366 1367 if (isr & ISR_TXURN) { 1368 u_int32_t thresh; 1369 1370 printf("%s: transmit FIFO underrun", 1371 sc->sc_dev.dv_xname); 1372 1373 thresh = sc->sc_tx_drain_thresh + 1; 1374 if (thresh <= TXCFG_DRTH && 1375 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1376 (sc->sc_tx_fill_thresh * 32))) { 1377 printf("; increasing Tx drain " 1378 "threshold to %u bytes\n", 1379 thresh * 32); 1380 sc->sc_tx_drain_thresh = thresh; 1381 (void) SIP_DECL(init)(ifp); 1382 } else { 1383 (void) SIP_DECL(init)(ifp); 1384 printf("\n"); 1385 } 1386 } 1387 } 1388 1389 #if !defined(DP83820) 1390 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1391 if (isr & ISR_PAUSE_ST) { 1392 sc->sc_flags |= SIPF_PAUSED; 1393 ifp->if_flags |= IFF_OACTIVE; 1394 } 1395 if (isr & ISR_PAUSE_END) { 1396 sc->sc_flags &= ~SIPF_PAUSED; 1397 ifp->if_flags &= ~IFF_OACTIVE; 1398 } 1399 } 1400 #endif /* ! DP83820 */ 1401 1402 if (isr & ISR_HIBERR) { 1403 #define PRINTERR(bit, str) \ 1404 if (isr & (bit)) \ 1405 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1406 PRINTERR(ISR_DPERR, "parity error"); 1407 PRINTERR(ISR_SSERR, "system error"); 1408 PRINTERR(ISR_RMABT, "master abort"); 1409 PRINTERR(ISR_RTABT, "target abort"); 1410 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1411 (void) SIP_DECL(init)(ifp); 1412 #undef PRINTERR 1413 } 1414 } 1415 1416 /* Try to get more packets going. */ 1417 SIP_DECL(start)(ifp); 1418 1419 return (handled); 1420 } 1421 1422 /* 1423 * sip_txintr: 1424 * 1425 * Helper; handle transmit interrupts. 1426 */ 1427 void 1428 SIP_DECL(txintr)(struct sip_softc *sc) 1429 { 1430 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1431 struct sip_txsoft *txs; 1432 u_int32_t cmdsts; 1433 1434 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1435 ifp->if_flags &= ~IFF_OACTIVE; 1436 1437 /* 1438 * Go through our Tx list and free mbufs for those 1439 * frames which have been transmitted. 1440 */ 1441 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1442 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1443 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1444 1445 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1446 if (cmdsts & CMDSTS_OWN) 1447 break; 1448 1449 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1450 1451 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1452 1453 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1454 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1455 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1456 m_freem(txs->txs_mbuf); 1457 txs->txs_mbuf = NULL; 1458 1459 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1460 1461 /* 1462 * Check for errors and collisions. 1463 */ 1464 if (cmdsts & 1465 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1466 ifp->if_oerrors++; 1467 if (cmdsts & CMDSTS_Tx_EC) 1468 ifp->if_collisions += 16; 1469 if (ifp->if_flags & IFF_DEBUG) { 1470 if (cmdsts & CMDSTS_Tx_ED) 1471 printf("%s: excessive deferral\n", 1472 sc->sc_dev.dv_xname); 1473 if (cmdsts & CMDSTS_Tx_EC) 1474 printf("%s: excessive collisions\n", 1475 sc->sc_dev.dv_xname); 1476 } 1477 } else { 1478 /* Packet was transmitted successfully. */ 1479 ifp->if_opackets++; 1480 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1481 } 1482 } 1483 1484 /* 1485 * If there are no more pending transmissions, cancel the watchdog 1486 * timer. 1487 */ 1488 if (txs == NULL) 1489 ifp->if_timer = 0; 1490 } 1491 1492 #if defined(DP83820) 1493 /* 1494 * sip_rxintr: 1495 * 1496 * Helper; handle receive interrupts. 1497 */ 1498 void 1499 SIP_DECL(rxintr)(struct sip_softc *sc) 1500 { 1501 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1502 struct sip_rxsoft *rxs; 1503 struct mbuf *m, *tailm; 1504 u_int32_t cmdsts, extsts; 1505 int i, len; 1506 1507 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1508 rxs = &sc->sc_rxsoft[i]; 1509 1510 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1511 1512 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1513 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1514 1515 /* 1516 * NOTE: OWN is set if owned by _consumer_. We're the 1517 * consumer of the receive ring, so if the bit is clear, 1518 * we have processed all of the packets. 1519 */ 1520 if ((cmdsts & CMDSTS_OWN) == 0) { 1521 /* 1522 * We have processed all of the receive buffers. 1523 */ 1524 break; 1525 } 1526 1527 if (__predict_false(sc->sc_rxdiscard)) { 1528 SIP_INIT_RXDESC(sc, i); 1529 if ((cmdsts & CMDSTS_MORE) == 0) { 1530 /* Reset our state. */ 1531 sc->sc_rxdiscard = 0; 1532 } 1533 continue; 1534 } 1535 1536 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1537 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1538 1539 m = rxs->rxs_mbuf; 1540 1541 /* 1542 * Add a new receive buffer to the ring. 1543 */ 1544 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1545 /* 1546 * Failed, throw away what we've done so 1547 * far, and discard the rest of the packet. 1548 */ 1549 ifp->if_ierrors++; 1550 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1551 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1552 SIP_INIT_RXDESC(sc, i); 1553 if (cmdsts & CMDSTS_MORE) 1554 sc->sc_rxdiscard = 1; 1555 if (sc->sc_rxhead != NULL) 1556 m_freem(sc->sc_rxhead); 1557 SIP_RXCHAIN_RESET(sc); 1558 continue; 1559 } 1560 1561 SIP_RXCHAIN_LINK(sc, m); 1562 1563 /* 1564 * If this is not the end of the packet, keep 1565 * looking. 1566 */ 1567 if (cmdsts & CMDSTS_MORE) { 1568 sc->sc_rxlen += m->m_len; 1569 continue; 1570 } 1571 1572 /* 1573 * Okay, we have the entire packet now... 1574 */ 1575 *sc->sc_rxtailp = NULL; 1576 m = sc->sc_rxhead; 1577 tailm = sc->sc_rxtail; 1578 1579 SIP_RXCHAIN_RESET(sc); 1580 1581 /* 1582 * If an error occurred, update stats and drop the packet. 1583 */ 1584 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1585 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1586 ifp->if_ierrors++; 1587 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1588 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1589 /* Receive overrun handled elsewhere. */ 1590 printf("%s: receive descriptor error\n", 1591 sc->sc_dev.dv_xname); 1592 } 1593 #define PRINTERR(bit, str) \ 1594 if (cmdsts & (bit)) \ 1595 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1596 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1597 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1598 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1599 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1600 #undef PRINTERR 1601 m_freem(m); 1602 continue; 1603 } 1604 1605 /* 1606 * No errors. 1607 * 1608 * Note, the DP83820 includes the CRC with 1609 * every packet. 1610 */ 1611 len = CMDSTS_SIZE(cmdsts); 1612 tailm->m_len = len - sc->sc_rxlen; 1613 1614 /* 1615 * If the packet is small enough to fit in a 1616 * single header mbuf, allocate one and copy 1617 * the data into it. This greatly reduces 1618 * memory consumption when we receive lots 1619 * of small packets. 1620 */ 1621 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1622 struct mbuf *nm; 1623 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1624 if (nm == NULL) { 1625 ifp->if_ierrors++; 1626 m_freem(m); 1627 continue; 1628 } 1629 nm->m_data += 2; 1630 nm->m_pkthdr.len = nm->m_len = len; 1631 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1632 m_freem(m); 1633 m = nm; 1634 } 1635 #ifndef __NO_STRICT_ALIGNMENT 1636 else { 1637 /* 1638 * The DP83820's receive buffers must be 4-byte 1639 * aligned. But this means that the data after 1640 * the Ethernet header is misaligned. To compensate, 1641 * we have artificially shortened the buffer size 1642 * in the descriptor, and we do an overlapping copy 1643 * of the data two bytes further in (in the first 1644 * buffer of the chain only). 1645 */ 1646 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1647 m->m_len); 1648 m->m_data += 2; 1649 } 1650 #endif /* ! __NO_STRICT_ALIGNMENT */ 1651 1652 /* 1653 * If VLANs are enabled, VLAN packets have been unwrapped 1654 * for us. Associate the tag with the packet. 1655 */ 1656 if (sc->sc_ethercom.ec_nvlans != 0 && 1657 (extsts & EXTSTS_VPKT) != 0) { 1658 struct mbuf *vtag; 1659 1660 vtag = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 1661 if (vtag == NULL) { 1662 ifp->if_ierrors++; 1663 printf("%s: unable to allocate VLAN tag\n", 1664 sc->sc_dev.dv_xname); 1665 m_freem(m); 1666 continue; 1667 } 1668 1669 *mtod(vtag, int *) = ntohs(extsts & EXTSTS_VTCI); 1670 vtag->m_len = sizeof(int); 1671 } 1672 1673 /* 1674 * Set the incoming checksum information for the 1675 * packet. 1676 */ 1677 if ((extsts & EXTSTS_IPPKT) != 0) { 1678 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1679 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1680 if (extsts & EXTSTS_Rx_IPERR) 1681 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1682 if (extsts & EXTSTS_TCPPKT) { 1683 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1684 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1685 if (extsts & EXTSTS_Rx_TCPERR) 1686 m->m_pkthdr.csum_flags |= 1687 M_CSUM_TCP_UDP_BAD; 1688 } else if (extsts & EXTSTS_UDPPKT) { 1689 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1690 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1691 if (extsts & EXTSTS_Rx_UDPERR) 1692 m->m_pkthdr.csum_flags |= 1693 M_CSUM_TCP_UDP_BAD; 1694 } 1695 } 1696 1697 ifp->if_ipackets++; 1698 m->m_flags |= M_HASFCS; 1699 m->m_pkthdr.rcvif = ifp; 1700 m->m_pkthdr.len = len; 1701 1702 #if NBPFILTER > 0 1703 /* 1704 * Pass this up to any BPF listeners, but only 1705 * pass if up the stack if it's for us. 1706 */ 1707 if (ifp->if_bpf) 1708 bpf_mtap(ifp->if_bpf, m); 1709 #endif /* NBPFILTER > 0 */ 1710 1711 /* Pass it on. */ 1712 (*ifp->if_input)(ifp, m); 1713 } 1714 1715 /* Update the receive pointer. */ 1716 sc->sc_rxptr = i; 1717 } 1718 #else /* ! DP83820 */ 1719 /* 1720 * sip_rxintr: 1721 * 1722 * Helper; handle receive interrupts. 1723 */ 1724 void 1725 SIP_DECL(rxintr)(struct sip_softc *sc) 1726 { 1727 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1728 struct sip_rxsoft *rxs; 1729 struct mbuf *m; 1730 u_int32_t cmdsts; 1731 int i, len; 1732 1733 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1734 rxs = &sc->sc_rxsoft[i]; 1735 1736 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1737 1738 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1739 1740 /* 1741 * NOTE: OWN is set if owned by _consumer_. We're the 1742 * consumer of the receive ring, so if the bit is clear, 1743 * we have processed all of the packets. 1744 */ 1745 if ((cmdsts & CMDSTS_OWN) == 0) { 1746 /* 1747 * We have processed all of the receive buffers. 1748 */ 1749 break; 1750 } 1751 1752 /* 1753 * If any collisions were seen on the wire, count one. 1754 */ 1755 if (cmdsts & CMDSTS_Rx_COL) 1756 ifp->if_collisions++; 1757 1758 /* 1759 * If an error occurred, update stats, clear the status 1760 * word, and leave the packet buffer in place. It will 1761 * simply be reused the next time the ring comes around. 1762 */ 1763 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1764 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1765 ifp->if_ierrors++; 1766 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1767 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1768 /* Receive overrun handled elsewhere. */ 1769 printf("%s: receive descriptor error\n", 1770 sc->sc_dev.dv_xname); 1771 } 1772 #define PRINTERR(bit, str) \ 1773 if (cmdsts & (bit)) \ 1774 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1775 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1776 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1777 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1778 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1779 #undef PRINTERR 1780 SIP_INIT_RXDESC(sc, i); 1781 continue; 1782 } 1783 1784 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1785 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1786 1787 /* 1788 * No errors; receive the packet. Note, the SiS 900 1789 * includes the CRC with every packet. 1790 */ 1791 len = CMDSTS_SIZE(cmdsts); 1792 1793 #ifdef __NO_STRICT_ALIGNMENT 1794 /* 1795 * If the packet is small enough to fit in a 1796 * single header mbuf, allocate one and copy 1797 * the data into it. This greatly reduces 1798 * memory consumption when we receive lots 1799 * of small packets. 1800 * 1801 * Otherwise, we add a new buffer to the receive 1802 * chain. If this fails, we drop the packet and 1803 * recycle the old buffer. 1804 */ 1805 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 1806 MGETHDR(m, M_DONTWAIT, MT_DATA); 1807 if (m == NULL) 1808 goto dropit; 1809 memcpy(mtod(m, caddr_t), 1810 mtod(rxs->rxs_mbuf, caddr_t), len); 1811 SIP_INIT_RXDESC(sc, i); 1812 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1813 rxs->rxs_dmamap->dm_mapsize, 1814 BUS_DMASYNC_PREREAD); 1815 } else { 1816 m = rxs->rxs_mbuf; 1817 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1818 dropit: 1819 ifp->if_ierrors++; 1820 SIP_INIT_RXDESC(sc, i); 1821 bus_dmamap_sync(sc->sc_dmat, 1822 rxs->rxs_dmamap, 0, 1823 rxs->rxs_dmamap->dm_mapsize, 1824 BUS_DMASYNC_PREREAD); 1825 continue; 1826 } 1827 } 1828 #else 1829 /* 1830 * The SiS 900's receive buffers must be 4-byte aligned. 1831 * But this means that the data after the Ethernet header 1832 * is misaligned. We must allocate a new buffer and 1833 * copy the data, shifted forward 2 bytes. 1834 */ 1835 MGETHDR(m, M_DONTWAIT, MT_DATA); 1836 if (m == NULL) { 1837 dropit: 1838 ifp->if_ierrors++; 1839 SIP_INIT_RXDESC(sc, i); 1840 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1841 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1842 continue; 1843 } 1844 if (len > (MHLEN - 2)) { 1845 MCLGET(m, M_DONTWAIT); 1846 if ((m->m_flags & M_EXT) == 0) { 1847 m_freem(m); 1848 goto dropit; 1849 } 1850 } 1851 m->m_data += 2; 1852 1853 /* 1854 * Note that we use clusters for incoming frames, so the 1855 * buffer is virtually contiguous. 1856 */ 1857 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 1858 1859 /* Allow the receive descriptor to continue using its mbuf. */ 1860 SIP_INIT_RXDESC(sc, i); 1861 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1862 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1863 #endif /* __NO_STRICT_ALIGNMENT */ 1864 1865 ifp->if_ipackets++; 1866 m->m_flags |= M_HASFCS; 1867 m->m_pkthdr.rcvif = ifp; 1868 m->m_pkthdr.len = m->m_len = len; 1869 1870 #if NBPFILTER > 0 1871 /* 1872 * Pass this up to any BPF listeners, but only 1873 * pass if up the stack if it's for us. 1874 */ 1875 if (ifp->if_bpf) 1876 bpf_mtap(ifp->if_bpf, m); 1877 #endif /* NBPFILTER > 0 */ 1878 1879 /* Pass it on. */ 1880 (*ifp->if_input)(ifp, m); 1881 } 1882 1883 /* Update the receive pointer. */ 1884 sc->sc_rxptr = i; 1885 } 1886 #endif /* DP83820 */ 1887 1888 /* 1889 * sip_tick: 1890 * 1891 * One second timer, used to tick the MII. 1892 */ 1893 void 1894 SIP_DECL(tick)(void *arg) 1895 { 1896 struct sip_softc *sc = arg; 1897 int s; 1898 1899 s = splnet(); 1900 mii_tick(&sc->sc_mii); 1901 splx(s); 1902 1903 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 1904 } 1905 1906 /* 1907 * sip_reset: 1908 * 1909 * Perform a soft reset on the SiS 900. 1910 */ 1911 void 1912 SIP_DECL(reset)(struct sip_softc *sc) 1913 { 1914 bus_space_tag_t st = sc->sc_st; 1915 bus_space_handle_t sh = sc->sc_sh; 1916 int i; 1917 1918 bus_space_write_4(st, sh, SIP_CR, CR_RST); 1919 1920 for (i = 0; i < SIP_TIMEOUT; i++) { 1921 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 1922 break; 1923 delay(2); 1924 } 1925 1926 if (i == SIP_TIMEOUT) 1927 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1928 1929 delay(1000); 1930 1931 #ifdef DP83820 1932 /* 1933 * Set the general purpose I/O bits. Do it here in case we 1934 * need to have GPIO set up to talk to the media interface. 1935 */ 1936 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 1937 delay(1000); 1938 #endif /* DP83820 */ 1939 } 1940 1941 /* 1942 * sip_init: [ ifnet interface function ] 1943 * 1944 * Initialize the interface. Must be called at splnet(). 1945 */ 1946 int 1947 SIP_DECL(init)(struct ifnet *ifp) 1948 { 1949 struct sip_softc *sc = ifp->if_softc; 1950 bus_space_tag_t st = sc->sc_st; 1951 bus_space_handle_t sh = sc->sc_sh; 1952 struct sip_txsoft *txs; 1953 struct sip_rxsoft *rxs; 1954 struct sip_desc *sipd; 1955 u_int32_t reg; 1956 int i, error = 0; 1957 1958 /* 1959 * Cancel any pending I/O. 1960 */ 1961 SIP_DECL(stop)(ifp, 0); 1962 1963 /* 1964 * Reset the chip to a known state. 1965 */ 1966 SIP_DECL(reset)(sc); 1967 1968 #if !defined(DP83820) 1969 if (sc->sc_model->sip_vendor == PCI_VENDOR_NS && 1970 sc->sc_model->sip_product == PCI_PRODUCT_NS_DP83815) { 1971 /* 1972 * DP83815 manual, page 78: 1973 * 4.4 Recommended Registers Configuration 1974 * For optimum performance of the DP83815, version noted 1975 * as DP83815CVNG (SRR = 203h), the listed register 1976 * modifications must be followed in sequence... 1977 * 1978 * It's not clear if this should be 302h or 203h because that 1979 * chip name is listed as SRR 302h in the description of the 1980 * SRR register. However, my revision 302h DP83815 on the 1981 * Netgear FA311 purchased in 02/2001 needs these settings 1982 * to avoid tons of errors in AcceptPerfectMatch (non- 1983 * IFF_PROMISC) mode. I do not know if other revisions need 1984 * this set or not. [briggs -- 09 March 2001] 1985 * 1986 * Note that only the low-order 12 bits of 0xe4 are documented 1987 * and that this sets reserved bits in that register. 1988 */ 1989 reg = bus_space_read_4(st, sh, SIP_NS_SRR); 1990 if (reg == 0x302) { 1991 bus_space_write_4(st, sh, 0x00cc, 0x0001); 1992 bus_space_write_4(st, sh, 0x00e4, 0x189C); 1993 bus_space_write_4(st, sh, 0x00fc, 0x0000); 1994 bus_space_write_4(st, sh, 0x00f4, 0x5040); 1995 bus_space_write_4(st, sh, 0x00f8, 0x008c); 1996 } 1997 } 1998 #endif /* ! DP83820 */ 1999 2000 /* 2001 * Initialize the transmit descriptor ring. 2002 */ 2003 for (i = 0; i < SIP_NTXDESC; i++) { 2004 sipd = &sc->sc_txdescs[i]; 2005 memset(sipd, 0, sizeof(struct sip_desc)); 2006 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2007 } 2008 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2009 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2010 sc->sc_txfree = SIP_NTXDESC; 2011 sc->sc_txnext = 0; 2012 2013 /* 2014 * Initialize the transmit job descriptors. 2015 */ 2016 SIMPLEQ_INIT(&sc->sc_txfreeq); 2017 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2018 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2019 txs = &sc->sc_txsoft[i]; 2020 txs->txs_mbuf = NULL; 2021 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2022 } 2023 2024 /* 2025 * Initialize the receive descriptor and receive job 2026 * descriptor rings. 2027 */ 2028 for (i = 0; i < SIP_NRXDESC; i++) { 2029 rxs = &sc->sc_rxsoft[i]; 2030 if (rxs->rxs_mbuf == NULL) { 2031 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2032 printf("%s: unable to allocate or map rx " 2033 "buffer %d, error = %d\n", 2034 sc->sc_dev.dv_xname, i, error); 2035 /* 2036 * XXX Should attempt to run with fewer receive 2037 * XXX buffers instead of just failing. 2038 */ 2039 SIP_DECL(rxdrain)(sc); 2040 goto out; 2041 } 2042 } else 2043 SIP_INIT_RXDESC(sc, i); 2044 } 2045 sc->sc_rxptr = 0; 2046 #ifdef DP83820 2047 sc->sc_rxdiscard = 0; 2048 SIP_RXCHAIN_RESET(sc); 2049 #endif /* DP83820 */ 2050 2051 /* 2052 * Set the configuration register; it's already initialized 2053 * in sip_attach(). 2054 */ 2055 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2056 2057 /* 2058 * Initialize the transmit fill and drain thresholds if 2059 * we have never done so. 2060 */ 2061 if (sc->sc_tx_fill_thresh == 0) { 2062 /* 2063 * XXX This value should be tuned. This is the 2064 * minimum (32 bytes), and we may be able to 2065 * improve performance by increasing it. 2066 */ 2067 sc->sc_tx_fill_thresh = 1; 2068 } 2069 if (sc->sc_tx_drain_thresh == 0) { 2070 /* 2071 * Start at a drain threshold of 512 bytes. We will 2072 * increase it if a DMA underrun occurs. 2073 * 2074 * XXX The minimum value of this variable should be 2075 * tuned. We may be able to improve performance 2076 * by starting with a lower value. That, however, 2077 * may trash the first few outgoing packets if the 2078 * PCI bus is saturated. 2079 */ 2080 sc->sc_tx_drain_thresh = 512 / 32; 2081 } 2082 2083 /* 2084 * Initialize the prototype TXCFG register. 2085 */ 2086 sc->sc_txcfg = TXCFG_ATP | TXCFG_MXDMA_512 | 2087 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2088 sc->sc_tx_drain_thresh; 2089 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2090 2091 /* 2092 * Initialize the receive drain threshold if we have never 2093 * done so. 2094 */ 2095 if (sc->sc_rx_drain_thresh == 0) { 2096 /* 2097 * XXX This value should be tuned. This is set to the 2098 * maximum of 248 bytes, and we may be able to improve 2099 * performance by decreasing it (although we should never 2100 * set this value lower than 2; 14 bytes are required to 2101 * filter the packet). 2102 */ 2103 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2104 } 2105 2106 /* 2107 * Initialize the prototype RXCFG register. 2108 */ 2109 sc->sc_rxcfg = RXCFG_MXDMA_512 | 2110 (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2111 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2112 2113 /* Set up the receive filter. */ 2114 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2115 2116 #ifdef DP83820 2117 /* 2118 * Initialize the VLAN/IP receive control register. 2119 * We enable checksum computation on all incoming 2120 * packets, and do not reject packets w/ bad checksums. 2121 */ 2122 reg = 0; 2123 if (ifp->if_capenable & 2124 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2125 reg |= VRCR_IPEN; 2126 if (sc->sc_ethercom.ec_nvlans != 0) 2127 reg |= VRCR_VTDEN|VRCR_VTREN; 2128 bus_space_write_4(st, sh, SIP_VRCR, reg); 2129 2130 /* 2131 * Initialize the VLAN/IP transmit control register. 2132 * We enable outgoing checksum computation on a 2133 * per-packet basis. 2134 */ 2135 reg = 0; 2136 if (ifp->if_capenable & 2137 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2138 reg |= VTCR_PPCHK; 2139 if (sc->sc_ethercom.ec_nvlans != 0) 2140 reg |= VTCR_VPPTI; 2141 bus_space_write_4(st, sh, SIP_VTCR, reg); 2142 2143 /* 2144 * If we're using VLANs, initialize the VLAN data register. 2145 * To understand why we bswap the VLAN Ethertype, see section 2146 * 4.2.36 of the DP83820 manual. 2147 */ 2148 if (sc->sc_ethercom.ec_nvlans != 0) 2149 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2150 #endif /* DP83820 */ 2151 2152 /* 2153 * Give the transmit and receive rings to the chip. 2154 */ 2155 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2156 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2157 2158 /* 2159 * Initialize the interrupt mask. 2160 */ 2161 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2162 ISR_TXURN|ISR_TXDESC|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2163 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2164 2165 /* 2166 * Set the current media. Do this after initializing the prototype 2167 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2168 * control. 2169 */ 2170 mii_mediachg(&sc->sc_mii); 2171 2172 /* 2173 * Enable interrupts. 2174 */ 2175 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2176 2177 /* 2178 * Start the transmit and receive processes. 2179 */ 2180 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2181 2182 /* 2183 * Start the one second MII clock. 2184 */ 2185 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2186 2187 /* 2188 * ...all done! 2189 */ 2190 ifp->if_flags |= IFF_RUNNING; 2191 ifp->if_flags &= ~IFF_OACTIVE; 2192 2193 out: 2194 if (error) 2195 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2196 return (error); 2197 } 2198 2199 /* 2200 * sip_drain: 2201 * 2202 * Drain the receive queue. 2203 */ 2204 void 2205 SIP_DECL(rxdrain)(struct sip_softc *sc) 2206 { 2207 struct sip_rxsoft *rxs; 2208 int i; 2209 2210 for (i = 0; i < SIP_NRXDESC; i++) { 2211 rxs = &sc->sc_rxsoft[i]; 2212 if (rxs->rxs_mbuf != NULL) { 2213 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2214 m_freem(rxs->rxs_mbuf); 2215 rxs->rxs_mbuf = NULL; 2216 } 2217 } 2218 } 2219 2220 /* 2221 * sip_stop: [ ifnet interface function ] 2222 * 2223 * Stop transmission on the interface. 2224 */ 2225 void 2226 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2227 { 2228 struct sip_softc *sc = ifp->if_softc; 2229 bus_space_tag_t st = sc->sc_st; 2230 bus_space_handle_t sh = sc->sc_sh; 2231 struct sip_txsoft *txs; 2232 u_int32_t cmdsts = 0; /* DEBUG */ 2233 2234 /* 2235 * Stop the one second clock. 2236 */ 2237 callout_stop(&sc->sc_tick_ch); 2238 2239 /* Down the MII. */ 2240 mii_down(&sc->sc_mii); 2241 2242 /* 2243 * Disable interrupts. 2244 */ 2245 bus_space_write_4(st, sh, SIP_IER, 0); 2246 2247 /* 2248 * Stop receiver and transmitter. 2249 */ 2250 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2251 2252 /* 2253 * Release any queued transmit buffers. 2254 */ 2255 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2256 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2257 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2258 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2259 CMDSTS_INTR) == 0) 2260 printf("%s: sip_stop: last descriptor does not " 2261 "have INTR bit set\n", sc->sc_dev.dv_xname); 2262 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 2263 #ifdef DIAGNOSTIC 2264 if (txs->txs_mbuf == NULL) { 2265 printf("%s: dirty txsoft with no mbuf chain\n", 2266 sc->sc_dev.dv_xname); 2267 panic("sip_stop"); 2268 } 2269 #endif 2270 cmdsts |= /* DEBUG */ 2271 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2272 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2273 m_freem(txs->txs_mbuf); 2274 txs->txs_mbuf = NULL; 2275 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2276 } 2277 2278 if (disable) 2279 SIP_DECL(rxdrain)(sc); 2280 2281 /* 2282 * Mark the interface down and cancel the watchdog timer. 2283 */ 2284 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2285 ifp->if_timer = 0; 2286 2287 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2288 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2289 printf("%s: sip_stop: no INTR bits set in dirty tx " 2290 "descriptors\n", sc->sc_dev.dv_xname); 2291 } 2292 2293 /* 2294 * sip_read_eeprom: 2295 * 2296 * Read data from the serial EEPROM. 2297 */ 2298 void 2299 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2300 u_int16_t *data) 2301 { 2302 bus_space_tag_t st = sc->sc_st; 2303 bus_space_handle_t sh = sc->sc_sh; 2304 u_int16_t reg; 2305 int i, x; 2306 2307 for (i = 0; i < wordcnt; i++) { 2308 /* Send CHIP SELECT. */ 2309 reg = EROMAR_EECS; 2310 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2311 2312 /* Shift in the READ opcode. */ 2313 for (x = 3; x > 0; x--) { 2314 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2315 reg |= EROMAR_EEDI; 2316 else 2317 reg &= ~EROMAR_EEDI; 2318 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2319 bus_space_write_4(st, sh, SIP_EROMAR, 2320 reg | EROMAR_EESK); 2321 delay(4); 2322 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2323 delay(4); 2324 } 2325 2326 /* Shift in address. */ 2327 for (x = 6; x > 0; x--) { 2328 if ((word + i) & (1 << (x - 1))) 2329 reg |= EROMAR_EEDI; 2330 else 2331 reg &= ~EROMAR_EEDI; 2332 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2333 bus_space_write_4(st, sh, SIP_EROMAR, 2334 reg | EROMAR_EESK); 2335 delay(4); 2336 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2337 delay(4); 2338 } 2339 2340 /* Shift out data. */ 2341 reg = EROMAR_EECS; 2342 data[i] = 0; 2343 for (x = 16; x > 0; x--) { 2344 bus_space_write_4(st, sh, SIP_EROMAR, 2345 reg | EROMAR_EESK); 2346 delay(4); 2347 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2348 data[i] |= (1 << (x - 1)); 2349 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2350 delay(4); 2351 } 2352 2353 /* Clear CHIP SELECT. */ 2354 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2355 delay(4); 2356 } 2357 } 2358 2359 /* 2360 * sip_add_rxbuf: 2361 * 2362 * Add a receive buffer to the indicated descriptor. 2363 */ 2364 int 2365 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2366 { 2367 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2368 struct mbuf *m; 2369 int error; 2370 2371 MGETHDR(m, M_DONTWAIT, MT_DATA); 2372 if (m == NULL) 2373 return (ENOBUFS); 2374 2375 MCLGET(m, M_DONTWAIT); 2376 if ((m->m_flags & M_EXT) == 0) { 2377 m_freem(m); 2378 return (ENOBUFS); 2379 } 2380 2381 #if defined(DP83820) 2382 m->m_len = SIP_RXBUF_LEN; 2383 #endif /* DP83820 */ 2384 2385 if (rxs->rxs_mbuf != NULL) 2386 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2387 2388 rxs->rxs_mbuf = m; 2389 2390 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2391 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2392 BUS_DMA_READ|BUS_DMA_NOWAIT); 2393 if (error) { 2394 printf("%s: can't load rx DMA map %d, error = %d\n", 2395 sc->sc_dev.dv_xname, idx, error); 2396 panic("sip_add_rxbuf"); /* XXX */ 2397 } 2398 2399 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2400 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2401 2402 SIP_INIT_RXDESC(sc, idx); 2403 2404 return (0); 2405 } 2406 2407 #if !defined(DP83820) 2408 /* 2409 * sip_sis900_set_filter: 2410 * 2411 * Set up the receive filter. 2412 */ 2413 void 2414 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2415 { 2416 bus_space_tag_t st = sc->sc_st; 2417 bus_space_handle_t sh = sc->sc_sh; 2418 struct ethercom *ec = &sc->sc_ethercom; 2419 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2420 struct ether_multi *enm; 2421 u_int8_t *cp; 2422 struct ether_multistep step; 2423 u_int32_t crc, mchash[8]; 2424 2425 /* 2426 * Initialize the prototype RFCR. 2427 */ 2428 sc->sc_rfcr = RFCR_RFEN; 2429 if (ifp->if_flags & IFF_BROADCAST) 2430 sc->sc_rfcr |= RFCR_AAB; 2431 if (ifp->if_flags & IFF_PROMISC) { 2432 sc->sc_rfcr |= RFCR_AAP; 2433 goto allmulti; 2434 } 2435 2436 /* 2437 * Set up the multicast address filter by passing all multicast 2438 * addresses through a CRC generator, and then using the high-order 2439 * 6 bits as an index into the 128 bit multicast hash table (only 2440 * the lower 16 bits of each 32 bit multicast hash register are 2441 * valid). The high order bits select the register, while the 2442 * rest of the bits select the bit within the register. 2443 */ 2444 2445 memset(mchash, 0, sizeof(mchash)); 2446 2447 ETHER_FIRST_MULTI(step, ec, enm); 2448 while (enm != NULL) { 2449 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2450 /* 2451 * We must listen to a range of multicast addresses. 2452 * For now, just accept all multicasts, rather than 2453 * trying to set only those filter bits needed to match 2454 * the range. (At this time, the only use of address 2455 * ranges is for IP multicast routing, for which the 2456 * range is big enough to require all bits set.) 2457 */ 2458 goto allmulti; 2459 } 2460 2461 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2462 2463 /* Just want the 7 most significant bits. */ 2464 crc >>= 25; 2465 2466 /* Set the corresponding bit in the hash table. */ 2467 mchash[crc >> 4] |= 1 << (crc & 0xf); 2468 2469 ETHER_NEXT_MULTI(step, enm); 2470 } 2471 2472 ifp->if_flags &= ~IFF_ALLMULTI; 2473 goto setit; 2474 2475 allmulti: 2476 ifp->if_flags |= IFF_ALLMULTI; 2477 sc->sc_rfcr |= RFCR_AAM; 2478 2479 setit: 2480 #define FILTER_EMIT(addr, data) \ 2481 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2482 delay(1); \ 2483 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2484 delay(1) 2485 2486 /* 2487 * Disable receive filter, and program the node address. 2488 */ 2489 cp = LLADDR(ifp->if_sadl); 2490 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2491 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2492 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2493 2494 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2495 /* 2496 * Program the multicast hash table. 2497 */ 2498 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2499 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2500 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2501 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2502 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2503 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2504 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2505 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2506 } 2507 #undef FILTER_EMIT 2508 2509 /* 2510 * Re-enable the receiver filter. 2511 */ 2512 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2513 } 2514 #endif /* ! DP83820 */ 2515 2516 /* 2517 * sip_dp83815_set_filter: 2518 * 2519 * Set up the receive filter. 2520 */ 2521 void 2522 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2523 { 2524 bus_space_tag_t st = sc->sc_st; 2525 bus_space_handle_t sh = sc->sc_sh; 2526 struct ethercom *ec = &sc->sc_ethercom; 2527 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2528 struct ether_multi *enm; 2529 u_int8_t *cp; 2530 struct ether_multistep step; 2531 u_int32_t crc, hash, slot, bit; 2532 #ifdef DP83820 2533 #define MCHASH_NWORDS 128 2534 #else 2535 #define MCHASH_NWORDS 32 2536 #endif /* DP83820 */ 2537 u_int16_t mchash[MCHASH_NWORDS]; 2538 int i; 2539 2540 /* 2541 * Initialize the prototype RFCR. 2542 * Enable the receive filter, and accept on 2543 * Perfect (destination address) Match 2544 * If IFF_BROADCAST, also accept all broadcast packets. 2545 * If IFF_PROMISC, accept all unicast packets (and later, set 2546 * IFF_ALLMULTI and accept all multicast, too). 2547 */ 2548 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2549 if (ifp->if_flags & IFF_BROADCAST) 2550 sc->sc_rfcr |= RFCR_AAB; 2551 if (ifp->if_flags & IFF_PROMISC) { 2552 sc->sc_rfcr |= RFCR_AAP; 2553 goto allmulti; 2554 } 2555 2556 #ifdef DP83820 2557 /* 2558 * Set up the DP83820 multicast address filter by passing all multicast 2559 * addresses through a CRC generator, and then using the high-order 2560 * 11 bits as an index into the 2048 bit multicast hash table. The 2561 * high-order 7 bits select the slot, while the low-order 4 bits 2562 * select the bit within the slot. Note that only the low 16-bits 2563 * of each filter word are used, and there are 128 filter words. 2564 */ 2565 #else 2566 /* 2567 * Set up the DP83815 multicast address filter by passing all multicast 2568 * addresses through a CRC generator, and then using the high-order 2569 * 9 bits as an index into the 512 bit multicast hash table. The 2570 * high-order 5 bits select the slot, while the low-order 4 bits 2571 * select the bit within the slot. Note that only the low 16-bits 2572 * of each filter word are used, and there are 32 filter words. 2573 */ 2574 #endif /* DP83820 */ 2575 2576 memset(mchash, 0, sizeof(mchash)); 2577 2578 ifp->if_flags &= ~IFF_ALLMULTI; 2579 ETHER_FIRST_MULTI(step, ec, enm); 2580 if (enm == NULL) 2581 goto setit; 2582 while (enm != NULL) { 2583 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2584 /* 2585 * We must listen to a range of multicast addresses. 2586 * For now, just accept all multicasts, rather than 2587 * trying to set only those filter bits needed to match 2588 * the range. (At this time, the only use of address 2589 * ranges is for IP multicast routing, for which the 2590 * range is big enough to require all bits set.) 2591 */ 2592 goto allmulti; 2593 } 2594 2595 #ifdef DP83820 2596 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2597 2598 /* Just want the 11 most significant bits. */ 2599 hash = crc >> 21; 2600 #else 2601 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2602 2603 /* Just want the 9 most significant bits. */ 2604 hash = crc >> 23; 2605 #endif /* DP83820 */ 2606 slot = hash >> 4; 2607 bit = hash & 0xf; 2608 2609 /* Set the corresponding bit in the hash table. */ 2610 mchash[slot] |= 1 << bit; 2611 2612 ETHER_NEXT_MULTI(step, enm); 2613 } 2614 sc->sc_rfcr |= RFCR_MHEN; 2615 goto setit; 2616 2617 allmulti: 2618 ifp->if_flags |= IFF_ALLMULTI; 2619 sc->sc_rfcr |= RFCR_AAM; 2620 2621 setit: 2622 #define FILTER_EMIT(addr, data) \ 2623 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2624 delay(1); \ 2625 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2626 delay(1) 2627 2628 /* 2629 * Disable receive filter, and program the node address. 2630 */ 2631 cp = LLADDR(ifp->if_sadl); 2632 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 2633 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 2634 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 2635 2636 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2637 /* 2638 * Program the multicast hash table. 2639 */ 2640 for (i = 0; i < MCHASH_NWORDS; i++) { 2641 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 2642 mchash[i]); 2643 } 2644 } 2645 #undef FILTER_EMIT 2646 #undef MCHASH_NWORDS 2647 2648 /* 2649 * Re-enable the receiver filter. 2650 */ 2651 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2652 } 2653 2654 #if defined(DP83820) 2655 /* 2656 * sip_dp83820_mii_readreg: [mii interface function] 2657 * 2658 * Read a PHY register on the MII of the DP83820. 2659 */ 2660 int 2661 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 2662 { 2663 2664 return (mii_bitbang_readreg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2665 phy, reg)); 2666 } 2667 2668 /* 2669 * sip_dp83820_mii_writereg: [mii interface function] 2670 * 2671 * Write a PHY register on the MII of the DP83820. 2672 */ 2673 void 2674 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 2675 { 2676 2677 mii_bitbang_writereg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2678 phy, reg, val); 2679 } 2680 2681 /* 2682 * sip_dp83815_mii_statchg: [mii interface function] 2683 * 2684 * Callback from MII layer when media changes. 2685 */ 2686 void 2687 SIP_DECL(dp83820_mii_statchg)(struct device *self) 2688 { 2689 struct sip_softc *sc = (struct sip_softc *) self; 2690 u_int32_t cfg; 2691 2692 /* 2693 * Update TXCFG for full-duplex operation. 2694 */ 2695 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2696 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2697 else 2698 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2699 2700 /* 2701 * Update RXCFG for full-duplex or loopback. 2702 */ 2703 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2704 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2705 sc->sc_rxcfg |= RXCFG_ATX; 2706 else 2707 sc->sc_rxcfg &= ~RXCFG_ATX; 2708 2709 /* 2710 * Update CFG for MII/GMII. 2711 */ 2712 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2713 cfg = sc->sc_cfg | CFG_MODE_1000; 2714 else 2715 cfg = sc->sc_cfg; 2716 2717 /* 2718 * XXX 802.3x flow control. 2719 */ 2720 2721 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 2722 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2723 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2724 } 2725 2726 /* 2727 * sip_dp83820_mii_bitbang_read: [mii bit-bang interface function] 2728 * 2729 * Read the MII serial port for the MII bit-bang module. 2730 */ 2731 u_int32_t 2732 SIP_DECL(dp83820_mii_bitbang_read)(struct device *self) 2733 { 2734 struct sip_softc *sc = (void *) self; 2735 2736 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 2737 } 2738 2739 /* 2740 * sip_dp83820_mii_bitbang_write: [mii big-bang interface function] 2741 * 2742 * Write the MII serial port for the MII bit-bang module. 2743 */ 2744 void 2745 SIP_DECL(dp83820_mii_bitbang_write)(struct device *self, u_int32_t val) 2746 { 2747 struct sip_softc *sc = (void *) self; 2748 2749 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 2750 } 2751 #else /* ! DP83820 */ 2752 /* 2753 * sip_sis900_mii_readreg: [mii interface function] 2754 * 2755 * Read a PHY register on the MII. 2756 */ 2757 int 2758 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 2759 { 2760 struct sip_softc *sc = (struct sip_softc *) self; 2761 u_int32_t enphy; 2762 2763 /* 2764 * The SiS 900 has only an internal PHY on the MII. Only allow 2765 * MII address 0. 2766 */ 2767 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 2768 return (0); 2769 2770 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2771 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 2772 ENPHY_RWCMD | ENPHY_ACCESS); 2773 do { 2774 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2775 } while (enphy & ENPHY_ACCESS); 2776 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 2777 } 2778 2779 /* 2780 * sip_sis900_mii_writereg: [mii interface function] 2781 * 2782 * Write a PHY register on the MII. 2783 */ 2784 void 2785 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 2786 { 2787 struct sip_softc *sc = (struct sip_softc *) self; 2788 u_int32_t enphy; 2789 2790 /* 2791 * The SiS 900 has only an internal PHY on the MII. Only allow 2792 * MII address 0. 2793 */ 2794 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 2795 return; 2796 2797 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2798 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 2799 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 2800 do { 2801 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2802 } while (enphy & ENPHY_ACCESS); 2803 } 2804 2805 /* 2806 * sip_sis900_mii_statchg: [mii interface function] 2807 * 2808 * Callback from MII layer when media changes. 2809 */ 2810 void 2811 SIP_DECL(sis900_mii_statchg)(struct device *self) 2812 { 2813 struct sip_softc *sc = (struct sip_softc *) self; 2814 u_int32_t flowctl; 2815 2816 /* 2817 * Update TXCFG for full-duplex operation. 2818 */ 2819 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2820 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2821 else 2822 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2823 2824 /* 2825 * Update RXCFG for full-duplex or loopback. 2826 */ 2827 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2828 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2829 sc->sc_rxcfg |= RXCFG_ATX; 2830 else 2831 sc->sc_rxcfg &= ~RXCFG_ATX; 2832 2833 /* 2834 * Update IMR for use of 802.3x flow control. 2835 */ 2836 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 2837 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 2838 flowctl = FLOWCTL_FLOWEN; 2839 } else { 2840 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 2841 flowctl = 0; 2842 } 2843 2844 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2845 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2846 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 2847 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 2848 } 2849 2850 /* 2851 * sip_dp83815_mii_readreg: [mii interface function] 2852 * 2853 * Read a PHY register on the MII. 2854 */ 2855 int 2856 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 2857 { 2858 struct sip_softc *sc = (struct sip_softc *) self; 2859 u_int32_t val; 2860 2861 /* 2862 * The DP83815 only has an internal PHY. Only allow 2863 * MII address 0. 2864 */ 2865 if (phy != 0) 2866 return (0); 2867 2868 /* 2869 * Apparently, after a reset, the DP83815 can take a while 2870 * to respond. During this recovery period, the BMSR returns 2871 * a value of 0. Catch this -- it's not supposed to happen 2872 * (the BMSR has some hardcoded-to-1 bits), and wait for the 2873 * PHY to come back to life. 2874 * 2875 * This works out because the BMSR is the first register 2876 * read during the PHY probe process. 2877 */ 2878 do { 2879 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 2880 } while (reg == MII_BMSR && val == 0); 2881 2882 return (val & 0xffff); 2883 } 2884 2885 /* 2886 * sip_dp83815_mii_writereg: [mii interface function] 2887 * 2888 * Write a PHY register to the MII. 2889 */ 2890 void 2891 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 2892 { 2893 struct sip_softc *sc = (struct sip_softc *) self; 2894 2895 /* 2896 * The DP83815 only has an internal PHY. Only allow 2897 * MII address 0. 2898 */ 2899 if (phy != 0) 2900 return; 2901 2902 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 2903 } 2904 2905 /* 2906 * sip_dp83815_mii_statchg: [mii interface function] 2907 * 2908 * Callback from MII layer when media changes. 2909 */ 2910 void 2911 SIP_DECL(dp83815_mii_statchg)(struct device *self) 2912 { 2913 struct sip_softc *sc = (struct sip_softc *) self; 2914 2915 /* 2916 * Update TXCFG for full-duplex operation. 2917 */ 2918 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2919 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2920 else 2921 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2922 2923 /* 2924 * Update RXCFG for full-duplex or loopback. 2925 */ 2926 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2927 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2928 sc->sc_rxcfg |= RXCFG_ATX; 2929 else 2930 sc->sc_rxcfg &= ~RXCFG_ATX; 2931 2932 /* 2933 * XXX 802.3x flow control. 2934 */ 2935 2936 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2937 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2938 } 2939 #endif /* DP83820 */ 2940 2941 #if defined(DP83820) 2942 void 2943 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 2944 const struct pci_attach_args *pa, u_int8_t *enaddr) 2945 { 2946 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 2947 u_int8_t cksum, *e, match; 2948 int i; 2949 2950 /* 2951 * EEPROM data format for the DP83820 can be found in 2952 * the DP83820 manual, section 4.2.4. 2953 */ 2954 2955 SIP_DECL(read_eeprom)(sc, 0, 2956 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 2957 2958 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 2959 match = ~(match - 1); 2960 2961 cksum = 0x55; 2962 e = (u_int8_t *) eeprom_data; 2963 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 2964 cksum += *e++; 2965 2966 if (cksum != match) 2967 printf("%s: Checksum (%x) mismatch (%x)", 2968 sc->sc_dev.dv_xname, cksum, match); 2969 2970 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 2971 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 2972 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 2973 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 2974 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 2975 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 2976 2977 /* Get the GPIOR bits. */ 2978 sc->sc_gpior = eeprom_data[0x04]; 2979 2980 /* Get various CFG related bits. */ 2981 if ((eeprom_data[0x05] >> 0) & 1) 2982 sc->sc_cfg |= CFG_EXT_125; 2983 if ((eeprom_data[0x05] >> 9) & 1) 2984 sc->sc_cfg |= CFG_TBI_EN; 2985 } 2986 #else /* ! DP83820 */ 2987 void 2988 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 2989 const struct pci_attach_args *pa, u_int8_t *enaddr) 2990 { 2991 u_int16_t myea[ETHER_ADDR_LEN / 2]; 2992 2993 switch (PCI_REVISION(pa->pa_class)) { 2994 case SIS_REV_630S: 2995 case SIS_REV_630E: 2996 case SIS_REV_630EA1: 2997 /* 2998 * The MAC address for the on-board Ethernet of 2999 * the SiS 630 chipset is in the NVRAM. Kick 3000 * the chip into re-loading it from NVRAM, and 3001 * read the MAC address out of the filter registers. 3002 */ 3003 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3004 3005 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3006 RFCR_RFADDR_NODE0); 3007 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3008 0xffff; 3009 3010 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3011 RFCR_RFADDR_NODE2); 3012 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3013 0xffff; 3014 3015 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3016 RFCR_RFADDR_NODE4); 3017 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3018 0xffff; 3019 break; 3020 3021 default: 3022 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3023 sizeof(myea) / sizeof(myea[0]), myea); 3024 } 3025 3026 enaddr[0] = myea[0] & 0xff; 3027 enaddr[1] = myea[0] >> 8; 3028 enaddr[2] = myea[1] & 0xff; 3029 enaddr[3] = myea[1] >> 8; 3030 enaddr[4] = myea[2] & 0xff; 3031 enaddr[5] = myea[2] >> 8; 3032 } 3033 3034 /* Table and macro to bit-reverse an octet. */ 3035 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3036 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3037 3038 void 3039 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3040 const struct pci_attach_args *pa, u_int8_t *enaddr) 3041 { 3042 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3043 u_int8_t cksum, *e, match; 3044 int i; 3045 3046 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3047 sizeof(eeprom_data[0]), eeprom_data); 3048 3049 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3050 match = ~(match - 1); 3051 3052 cksum = 0x55; 3053 e = (u_int8_t *) eeprom_data; 3054 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3055 cksum += *e++; 3056 } 3057 if (cksum != match) { 3058 printf("%s: Checksum (%x) mismatch (%x)", 3059 sc->sc_dev.dv_xname, cksum, match); 3060 } 3061 3062 /* 3063 * Unrolled because it makes slightly more sense this way. 3064 * The DP83815 stores the MAC address in bit 0 of word 6 3065 * through bit 15 of word 8. 3066 */ 3067 ea = &eeprom_data[6]; 3068 enaddr[0] = ((*ea & 0x1) << 7); 3069 ea++; 3070 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3071 enaddr[1] = ((*ea & 0x1FE) >> 1); 3072 enaddr[2] = ((*ea & 0x1) << 7); 3073 ea++; 3074 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3075 enaddr[3] = ((*ea & 0x1FE) >> 1); 3076 enaddr[4] = ((*ea & 0x1) << 7); 3077 ea++; 3078 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3079 enaddr[5] = ((*ea & 0x1FE) >> 1); 3080 3081 /* 3082 * In case that's not weird enough, we also need to reverse 3083 * the bits in each byte. This all actually makes more sense 3084 * if you think about the EEPROM storage as an array of bits 3085 * being shifted into bytes, but that's not how we're looking 3086 * at it here... 3087 */ 3088 for (i = 0; i < 6 ;i++) 3089 enaddr[i] = bbr(enaddr[i]); 3090 } 3091 #endif /* DP83820 */ 3092 3093 /* 3094 * sip_mediastatus: [ifmedia interface function] 3095 * 3096 * Get the current interface media status. 3097 */ 3098 void 3099 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3100 { 3101 struct sip_softc *sc = ifp->if_softc; 3102 3103 mii_pollstat(&sc->sc_mii); 3104 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3105 ifmr->ifm_active = sc->sc_mii.mii_media_active; 3106 } 3107 3108 /* 3109 * sip_mediachange: [ifmedia interface function] 3110 * 3111 * Set hardware to newly-selected media. 3112 */ 3113 int 3114 SIP_DECL(mediachange)(struct ifnet *ifp) 3115 { 3116 struct sip_softc *sc = ifp->if_softc; 3117 3118 if (ifp->if_flags & IFF_UP) 3119 mii_mediachg(&sc->sc_mii); 3120 return (0); 3121 } 3122
Indexes created Tue Sep 30 11:09:46 GMT 2025