if_sip.c revision 1.40.2.3
1 /* $NetBSD: if_sip.c,v 1.40.2.3 2002/03/16 16:01:13 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Support the 10-bit interface on the DP83820 (for fiber). 80 * 81 * - Reduce the interrupt load. 82 */ 83 84 #include <sys/cdefs.h> 85 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.40.2.3 2002/03/16 16:01:13 jdolecek Exp $"); 86 87 #include "bpfilter.h" 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/callout.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/ioctl.h> 97 #include <sys/errno.h> 98 #include <sys/device.h> 99 #include <sys/queue.h> 100 101 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 102 103 #include <net/if.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 #include <net/if_ether.h> 107 108 #if NBPFILTER > 0 109 #include <net/bpf.h> 110 #endif 111 112 #include <machine/bus.h> 113 #include <machine/intr.h> 114 #include <machine/endian.h> 115 116 #include <dev/mii/mii.h> 117 #include <dev/mii/miivar.h> 118 #ifdef DP83820 119 #include <dev/mii/mii_bitbang.h> 120 #endif /* DP83820 */ 121 122 #include <dev/pci/pcireg.h> 123 #include <dev/pci/pcivar.h> 124 #include <dev/pci/pcidevs.h> 125 126 #include <dev/pci/if_sipreg.h> 127 128 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 129 #define SIP_DECL(x) __CONCAT(gsip_,x) 130 #else /* SiS900 and DP83815 */ 131 #define SIP_DECL(x) __CONCAT(sip_,x) 132 #endif 133 134 #define SIP_STR(x) __STRING(SIP_DECL(x)) 135 136 /* 137 * Transmit descriptor list size. This is arbitrary, but allocate 138 * enough descriptors for 128 pending transmissions, and 8 segments 139 * per packet. This MUST work out to a power of 2. 140 */ 141 #define SIP_NTXSEGS 8 142 143 #define SIP_TXQUEUELEN 256 144 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS) 145 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 146 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 147 148 #if defined(DP83020) 149 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 150 #else 151 #define TX_DMAMAP_SIZE MCLBYTES 152 #endif 153 154 /* 155 * Receive descriptor list size. We have one Rx buffer per incoming 156 * packet, so this logic is a little simpler. 157 * 158 * Actually, on the DP83820, we allow the packet to consume more than 159 * one buffer, in order to support jumbo Ethernet frames. In that 160 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 161 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 162 * so we'd better be quick about handling receive interrupts. 163 */ 164 #if defined(DP83820) 165 #define SIP_NRXDESC 256 166 #else 167 #define SIP_NRXDESC 128 168 #endif /* DP83820 */ 169 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 170 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 171 172 /* 173 * Control structures are DMA'd to the SiS900 chip. We allocate them in 174 * a single clump that maps to a single DMA segment to make several things 175 * easier. 176 */ 177 struct sip_control_data { 178 /* 179 * The transmit descriptors. 180 */ 181 struct sip_desc scd_txdescs[SIP_NTXDESC]; 182 183 /* 184 * The receive descriptors. 185 */ 186 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 187 }; 188 189 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 190 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 191 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 192 193 /* 194 * Software state for transmit jobs. 195 */ 196 struct sip_txsoft { 197 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 198 bus_dmamap_t txs_dmamap; /* our DMA map */ 199 int txs_firstdesc; /* first descriptor in packet */ 200 int txs_lastdesc; /* last descriptor in packet */ 201 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 202 }; 203 204 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 205 206 /* 207 * Software state for receive jobs. 208 */ 209 struct sip_rxsoft { 210 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 211 bus_dmamap_t rxs_dmamap; /* our DMA map */ 212 }; 213 214 /* 215 * Software state per device. 216 */ 217 struct sip_softc { 218 struct device sc_dev; /* generic device information */ 219 bus_space_tag_t sc_st; /* bus space tag */ 220 bus_space_handle_t sc_sh; /* bus space handle */ 221 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 222 struct ethercom sc_ethercom; /* ethernet common data */ 223 void *sc_sdhook; /* shutdown hook */ 224 225 const struct sip_product *sc_model; /* which model are we? */ 226 int sc_rev; /* chip revision */ 227 228 void *sc_ih; /* interrupt cookie */ 229 230 struct mii_data sc_mii; /* MII/media information */ 231 232 struct callout sc_tick_ch; /* tick callout */ 233 234 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 235 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 236 237 /* 238 * Software state for transmit and receive descriptors. 239 */ 240 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 241 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 242 243 /* 244 * Control data structures. 245 */ 246 struct sip_control_data *sc_control_data; 247 #define sc_txdescs sc_control_data->scd_txdescs 248 #define sc_rxdescs sc_control_data->scd_rxdescs 249 250 #ifdef SIP_EVENT_COUNTERS 251 /* 252 * Event counters. 253 */ 254 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 255 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 256 struct evcnt sc_ev_txintr; /* Tx interrupts */ 257 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 258 #ifdef DP83820 259 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 260 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 261 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 262 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 263 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 264 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 265 #endif /* DP83820 */ 266 #endif /* SIP_EVENT_COUNTERS */ 267 268 u_int32_t sc_txcfg; /* prototype TXCFG register */ 269 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 270 u_int32_t sc_imr; /* prototype IMR register */ 271 u_int32_t sc_rfcr; /* prototype RFCR register */ 272 273 u_int32_t sc_cfg; /* prototype CFG register */ 274 275 #ifdef DP83820 276 u_int32_t sc_gpior; /* prototype GPIOR register */ 277 #endif /* DP83820 */ 278 279 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 280 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 281 282 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 283 284 int sc_flags; /* misc. flags; see below */ 285 286 int sc_txfree; /* number of free Tx descriptors */ 287 int sc_txnext; /* next ready Tx descriptor */ 288 289 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 290 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 291 292 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 293 #if defined(DP83820) 294 int sc_rxdiscard; 295 int sc_rxlen; 296 struct mbuf *sc_rxhead; 297 struct mbuf *sc_rxtail; 298 struct mbuf **sc_rxtailp; 299 #endif /* DP83820 */ 300 }; 301 302 /* sc_flags */ 303 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 304 305 #ifdef DP83820 306 #define SIP_RXCHAIN_RESET(sc) \ 307 do { \ 308 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 309 *(sc)->sc_rxtailp = NULL; \ 310 (sc)->sc_rxlen = 0; \ 311 } while (/*CONSTCOND*/0) 312 313 #define SIP_RXCHAIN_LINK(sc, m) \ 314 do { \ 315 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 316 (sc)->sc_rxtailp = &(m)->m_next; \ 317 } while (/*CONSTCOND*/0) 318 #endif /* DP83820 */ 319 320 #ifdef SIP_EVENT_COUNTERS 321 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 322 #else 323 #define SIP_EVCNT_INCR(ev) /* nothing */ 324 #endif 325 326 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 327 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 328 329 #define SIP_CDTXSYNC(sc, x, n, ops) \ 330 do { \ 331 int __x, __n; \ 332 \ 333 __x = (x); \ 334 __n = (n); \ 335 \ 336 /* If it will wrap around, sync to the end of the ring. */ \ 337 if ((__x + __n) > SIP_NTXDESC) { \ 338 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 339 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 340 (SIP_NTXDESC - __x), (ops)); \ 341 __n -= (SIP_NTXDESC - __x); \ 342 __x = 0; \ 343 } \ 344 \ 345 /* Now sync whatever is left. */ \ 346 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 347 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 348 } while (0) 349 350 #define SIP_CDRXSYNC(sc, x, ops) \ 351 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 352 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 353 354 #ifdef DP83820 355 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 356 #define SIP_RXBUF_LEN (MCLBYTES - 4) 357 #else 358 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 359 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 360 #endif 361 #define SIP_INIT_RXDESC(sc, x) \ 362 do { \ 363 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 364 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 365 \ 366 __sipd->sipd_link = \ 367 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 368 __sipd->sipd_bufptr = \ 369 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 370 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 371 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 372 SIP_INIT_RXDESC_EXTSTS \ 373 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 374 } while (0) 375 376 #define SIP_CHIP_VERS(sc, v, p, r) \ 377 ((sc)->sc_model->sip_vendor == (v) && \ 378 (sc)->sc_model->sip_product == (p) && \ 379 (sc)->sc_rev == (r)) 380 381 #define SIP_CHIP_MODEL(sc, v, p) \ 382 ((sc)->sc_model->sip_vendor == (v) && \ 383 (sc)->sc_model->sip_product == (p)) 384 385 #if !defined(DP83820) 386 #define SIP_SIS900_REV(sc, rev) \ 387 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 388 #endif 389 390 #define SIP_TIMEOUT 1000 391 392 void SIP_DECL(start)(struct ifnet *); 393 void SIP_DECL(watchdog)(struct ifnet *); 394 int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 395 int SIP_DECL(init)(struct ifnet *); 396 void SIP_DECL(stop)(struct ifnet *, int); 397 398 void SIP_DECL(shutdown)(void *); 399 400 void SIP_DECL(reset)(struct sip_softc *); 401 void SIP_DECL(rxdrain)(struct sip_softc *); 402 int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 403 void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, u_int16_t *); 404 void SIP_DECL(tick)(void *); 405 406 #if !defined(DP83820) 407 void SIP_DECL(sis900_set_filter)(struct sip_softc *); 408 #endif /* ! DP83820 */ 409 void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 410 411 #if defined(DP83820) 412 void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 413 const struct pci_attach_args *, u_int8_t *); 414 #else 415 void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 416 const struct pci_attach_args *, u_int8_t *); 417 void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 418 const struct pci_attach_args *, u_int8_t *); 419 #endif /* DP83820 */ 420 421 int SIP_DECL(intr)(void *); 422 void SIP_DECL(txintr)(struct sip_softc *); 423 void SIP_DECL(rxintr)(struct sip_softc *); 424 425 #if defined(DP83820) 426 int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 427 void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 428 void SIP_DECL(dp83820_mii_statchg)(struct device *); 429 #else 430 int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 431 void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 432 void SIP_DECL(sis900_mii_statchg)(struct device *); 433 434 int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 435 void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 436 void SIP_DECL(dp83815_mii_statchg)(struct device *); 437 #endif /* DP83820 */ 438 439 int SIP_DECL(mediachange)(struct ifnet *); 440 void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 441 442 int SIP_DECL(match)(struct device *, struct cfdata *, void *); 443 void SIP_DECL(attach)(struct device *, struct device *, void *); 444 445 int SIP_DECL(copy_small) = 0; 446 447 struct cfattach SIP_DECL(ca) = { 448 sizeof(struct sip_softc), SIP_DECL(match), SIP_DECL(attach), 449 }; 450 451 /* 452 * Descriptions of the variants of the SiS900. 453 */ 454 struct sip_variant { 455 int (*sipv_mii_readreg)(struct device *, int, int); 456 void (*sipv_mii_writereg)(struct device *, int, int, int); 457 void (*sipv_mii_statchg)(struct device *); 458 void (*sipv_set_filter)(struct sip_softc *); 459 void (*sipv_read_macaddr)(struct sip_softc *, 460 const struct pci_attach_args *, u_int8_t *); 461 }; 462 463 #if defined(DP83820) 464 u_int32_t SIP_DECL(dp83820_mii_bitbang_read)(struct device *); 465 void SIP_DECL(dp83820_mii_bitbang_write)(struct device *, u_int32_t); 466 467 const struct mii_bitbang_ops SIP_DECL(dp83820_mii_bitbang_ops) = { 468 SIP_DECL(dp83820_mii_bitbang_read), 469 SIP_DECL(dp83820_mii_bitbang_write), 470 { 471 EROMAR_MDIO, /* MII_BIT_MDO */ 472 EROMAR_MDIO, /* MII_BIT_MDI */ 473 EROMAR_MDC, /* MII_BIT_MDC */ 474 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 475 0, /* MII_BIT_DIR_PHY_HOST */ 476 } 477 }; 478 #endif /* DP83820 */ 479 480 #if defined(DP83820) 481 const struct sip_variant SIP_DECL(variant_dp83820) = { 482 SIP_DECL(dp83820_mii_readreg), 483 SIP_DECL(dp83820_mii_writereg), 484 SIP_DECL(dp83820_mii_statchg), 485 SIP_DECL(dp83815_set_filter), 486 SIP_DECL(dp83820_read_macaddr), 487 }; 488 #else 489 const struct sip_variant SIP_DECL(variant_sis900) = { 490 SIP_DECL(sis900_mii_readreg), 491 SIP_DECL(sis900_mii_writereg), 492 SIP_DECL(sis900_mii_statchg), 493 SIP_DECL(sis900_set_filter), 494 SIP_DECL(sis900_read_macaddr), 495 }; 496 497 const struct sip_variant SIP_DECL(variant_dp83815) = { 498 SIP_DECL(dp83815_mii_readreg), 499 SIP_DECL(dp83815_mii_writereg), 500 SIP_DECL(dp83815_mii_statchg), 501 SIP_DECL(dp83815_set_filter), 502 SIP_DECL(dp83815_read_macaddr), 503 }; 504 #endif /* DP83820 */ 505 506 /* 507 * Devices supported by this driver. 508 */ 509 const struct sip_product { 510 pci_vendor_id_t sip_vendor; 511 pci_product_id_t sip_product; 512 const char *sip_name; 513 const struct sip_variant *sip_variant; 514 } SIP_DECL(products)[] = { 515 #if defined(DP83820) 516 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 517 "NatSemi DP83820 Gigabit Ethernet", 518 &SIP_DECL(variant_dp83820) }, 519 #else 520 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 521 "SiS 900 10/100 Ethernet", 522 &SIP_DECL(variant_sis900) }, 523 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 524 "SiS 7016 10/100 Ethernet", 525 &SIP_DECL(variant_sis900) }, 526 527 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 528 "NatSemi DP83815 10/100 Ethernet", 529 &SIP_DECL(variant_dp83815) }, 530 #endif /* DP83820 */ 531 532 { 0, 0, 533 NULL, 534 NULL }, 535 }; 536 537 static const struct sip_product * 538 SIP_DECL(lookup)(const struct pci_attach_args *pa) 539 { 540 const struct sip_product *sip; 541 542 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 543 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 544 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 545 return (sip); 546 } 547 return (NULL); 548 } 549 550 int 551 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 552 { 553 struct pci_attach_args *pa = aux; 554 555 if (SIP_DECL(lookup)(pa) != NULL) 556 return (1); 557 558 return (0); 559 } 560 561 void 562 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 563 { 564 struct sip_softc *sc = (struct sip_softc *) self; 565 struct pci_attach_args *pa = aux; 566 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 567 pci_chipset_tag_t pc = pa->pa_pc; 568 pci_intr_handle_t ih; 569 const char *intrstr = NULL; 570 bus_space_tag_t iot, memt; 571 bus_space_handle_t ioh, memh; 572 bus_dma_segment_t seg; 573 int ioh_valid, memh_valid; 574 int i, rseg, error; 575 const struct sip_product *sip; 576 pcireg_t pmode; 577 u_int8_t enaddr[ETHER_ADDR_LEN]; 578 int pmreg; 579 #ifdef DP83820 580 pcireg_t memtype; 581 u_int32_t reg; 582 #endif /* DP83820 */ 583 584 callout_init(&sc->sc_tick_ch); 585 586 sip = SIP_DECL(lookup)(pa); 587 if (sip == NULL) { 588 printf("\n"); 589 panic(SIP_STR(attach) ": impossible"); 590 } 591 sc->sc_rev = PCI_REVISION(pa->pa_class); 592 593 printf(": %s\n", sip->sip_name); 594 595 sc->sc_model = sip; 596 597 /* 598 * XXX Work-around broken PXE firmware on some boards. 599 * 600 * The DP83815 shares an address decoder with the MEM BAR 601 * and the ROM BAR. Make sure the ROM BAR is disabled, 602 * so that memory mapped access works. 603 */ 604 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 605 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 606 ~PCI_MAPREG_ROM_ENABLE); 607 608 /* 609 * Map the device. 610 */ 611 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 612 PCI_MAPREG_TYPE_IO, 0, 613 &iot, &ioh, NULL, NULL) == 0); 614 #ifdef DP83820 615 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 616 switch (memtype) { 617 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 618 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 619 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 620 memtype, 0, &memt, &memh, NULL, NULL) == 0); 621 break; 622 default: 623 memh_valid = 0; 624 } 625 #else 626 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 627 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 628 &memt, &memh, NULL, NULL) == 0); 629 #endif /* DP83820 */ 630 631 if (memh_valid) { 632 printf("%s: using memory mapped registers\n", sc->sc_dev.dv_xname); 633 sc->sc_st = memt; 634 sc->sc_sh = memh; 635 } else if (ioh_valid) { 636 printf("%s: using I/O mapped registers\n", sc->sc_dev.dv_xname); 637 sc->sc_st = iot; 638 sc->sc_sh = ioh; 639 } else { 640 printf("%s: unable to map device registers\n", 641 sc->sc_dev.dv_xname); 642 return; 643 } 644 645 sc->sc_dmat = pa->pa_dmat; 646 647 /* 648 * Make sure bus mastering is enabled. Also make sure 649 * Write/Invalidate is enabled if we're allowed to use it. 650 */ 651 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 652 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 653 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 654 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 655 pmreg | PCI_COMMAND_MASTER_ENABLE); 656 657 /* Get it out of power save mode if needed. */ 658 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 659 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 660 if (pmode == 3) { 661 /* 662 * The card has lost all configuration data in 663 * this state, so punt. 664 */ 665 printf("%s: unable to wake up from power state D3\n", 666 sc->sc_dev.dv_xname); 667 return; 668 } 669 if (pmode != 0) { 670 printf("%s: waking up from power state D%d\n", 671 sc->sc_dev.dv_xname, pmode); 672 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 673 } 674 } 675 676 /* 677 * Map and establish our interrupt. 678 */ 679 if (pci_intr_map(pa, &ih)) { 680 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 681 return; 682 } 683 intrstr = pci_intr_string(pc, ih); 684 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 685 if (sc->sc_ih == NULL) { 686 printf("%s: unable to establish interrupt", 687 sc->sc_dev.dv_xname); 688 if (intrstr != NULL) 689 printf(" at %s", intrstr); 690 printf("\n"); 691 return; 692 } 693 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 694 695 SIMPLEQ_INIT(&sc->sc_txfreeq); 696 SIMPLEQ_INIT(&sc->sc_txdirtyq); 697 698 /* 699 * Allocate the control data structures, and create and load the 700 * DMA map for it. 701 */ 702 if ((error = bus_dmamem_alloc(sc->sc_dmat, 703 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 704 0)) != 0) { 705 printf("%s: unable to allocate control data, error = %d\n", 706 sc->sc_dev.dv_xname, error); 707 goto fail_0; 708 } 709 710 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 711 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 712 BUS_DMA_COHERENT)) != 0) { 713 printf("%s: unable to map control data, error = %d\n", 714 sc->sc_dev.dv_xname, error); 715 goto fail_1; 716 } 717 718 if ((error = bus_dmamap_create(sc->sc_dmat, 719 sizeof(struct sip_control_data), 1, 720 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 721 printf("%s: unable to create control data DMA map, " 722 "error = %d\n", sc->sc_dev.dv_xname, error); 723 goto fail_2; 724 } 725 726 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 727 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 728 0)) != 0) { 729 printf("%s: unable to load control data DMA map, error = %d\n", 730 sc->sc_dev.dv_xname, error); 731 goto fail_3; 732 } 733 734 /* 735 * Create the transmit buffer DMA maps. 736 */ 737 for (i = 0; i < SIP_TXQUEUELEN; i++) { 738 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 739 SIP_NTXSEGS, MCLBYTES, 0, 0, 740 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 741 printf("%s: unable to create tx DMA map %d, " 742 "error = %d\n", sc->sc_dev.dv_xname, i, error); 743 goto fail_4; 744 } 745 } 746 747 /* 748 * Create the receive buffer DMA maps. 749 */ 750 for (i = 0; i < SIP_NRXDESC; i++) { 751 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 752 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 753 printf("%s: unable to create rx DMA map %d, " 754 "error = %d\n", sc->sc_dev.dv_xname, i, error); 755 goto fail_5; 756 } 757 sc->sc_rxsoft[i].rxs_mbuf = NULL; 758 } 759 760 /* 761 * Reset the chip to a known state. 762 */ 763 SIP_DECL(reset)(sc); 764 765 /* 766 * Read the Ethernet address from the EEPROM. This might 767 * also fetch other stuff from the EEPROM and stash it 768 * in the softc. 769 */ 770 sc->sc_cfg = 0; 771 #if !defined(DP83820) 772 if (SIP_SIS900_REV(sc,SIS_REV_635) || 773 SIP_SIS900_REV(sc,SIS_REV_900B)) 774 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 775 #endif 776 777 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 778 779 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 780 ether_sprintf(enaddr)); 781 782 /* 783 * Initialize the configuration register: aggressive PCI 784 * bus request algorithm, default backoff, default OW timer, 785 * default parity error detection. 786 * 787 * NOTE: "Big endian mode" is useless on the SiS900 and 788 * friends -- it affects packet data, not descriptors. 789 */ 790 #ifdef DP83820 791 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 792 if (reg & CFG_PCI64_DET) { 793 printf("%s: 64-bit PCI slot detected\n", sc->sc_dev.dv_xname); 794 /* 795 * XXX Need some PCI flags indicating support for 796 * XXX 64-bit addressing (SAC or DAC) and 64-bit 797 * XXX data path. 798 */ 799 } 800 if (sc->sc_cfg & (CFG_TBI_EN|CFG_EXT_125)) { 801 const char *sep = ""; 802 printf("%s: using ", sc->sc_dev.dv_xname); 803 if (sc->sc_cfg & CFG_EXT_125) { 804 printf("%s125MHz clock", sep); 805 sep = ", "; 806 } 807 if (sc->sc_cfg & CFG_TBI_EN) { 808 printf("%sten-bit interface", sep); 809 sep = ", "; 810 } 811 printf("\n"); 812 } 813 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0) 814 sc->sc_cfg |= CFG_MRM_DIS; 815 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 816 sc->sc_cfg |= CFG_MWI_DIS; 817 818 /* 819 * Use the extended descriptor format on the DP83820. This 820 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 821 * checksumming. 822 */ 823 sc->sc_cfg |= CFG_EXTSTS_EN; 824 #endif /* DP83820 */ 825 826 /* 827 * Initialize our media structures and probe the MII. 828 */ 829 sc->sc_mii.mii_ifp = ifp; 830 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 831 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 832 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 833 ifmedia_init(&sc->sc_mii.mii_media, 0, SIP_DECL(mediachange), 834 SIP_DECL(mediastatus)); 835 #ifdef DP83820 836 if (sc->sc_cfg & CFG_TBI_EN) { 837 /* Using ten-bit interface. */ 838 printf("%s: TBI -- FIXME\n", sc->sc_dev.dv_xname); 839 } else { 840 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 841 MII_OFFSET_ANY, 0); 842 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 843 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 844 0, NULL); 845 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 846 } else 847 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 848 } 849 #else 850 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 851 MII_OFFSET_ANY, 0); 852 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 853 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 854 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 855 } else 856 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 857 #endif /* DP83820 */ 858 859 ifp = &sc->sc_ethercom.ec_if; 860 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 861 ifp->if_softc = sc; 862 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 863 ifp->if_ioctl = SIP_DECL(ioctl); 864 ifp->if_start = SIP_DECL(start); 865 ifp->if_watchdog = SIP_DECL(watchdog); 866 ifp->if_init = SIP_DECL(init); 867 ifp->if_stop = SIP_DECL(stop); 868 IFQ_SET_READY(&ifp->if_snd); 869 870 /* 871 * We can support 802.1Q VLAN-sized frames. 872 */ 873 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 874 875 #ifdef DP83820 876 /* 877 * And the DP83820 can do VLAN tagging in hardware, and 878 * support the jumbo Ethernet MTU. 879 */ 880 sc->sc_ethercom.ec_capabilities |= 881 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 882 883 /* 884 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 885 * in hardware. 886 */ 887 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 888 IFCAP_CSUM_UDPv4; 889 #endif /* DP83820 */ 890 891 /* 892 * Attach the interface. 893 */ 894 if_attach(ifp); 895 ether_ifattach(ifp, enaddr); 896 897 /* 898 * The number of bytes that must be available in 899 * the Tx FIFO before the bus master can DMA more 900 * data into the FIFO. 901 */ 902 sc->sc_tx_fill_thresh = 64 / 32; 903 904 /* 905 * Start at a drain threshold of 512 bytes. We will 906 * increase it if a DMA underrun occurs. 907 * 908 * XXX The minimum value of this variable should be 909 * tuned. We may be able to improve performance 910 * by starting with a lower value. That, however, 911 * may trash the first few outgoing packets if the 912 * PCI bus is saturated. 913 */ 914 sc->sc_tx_drain_thresh = 512 / 32; 915 916 /* 917 * Initialize the Rx FIFO drain threshold. 918 * 919 * This is in units of 8 bytes. 920 * 921 * We should never set this value lower than 2; 14 bytes are 922 * required to filter the packet. 923 */ 924 sc->sc_rx_drain_thresh = 128 / 8; 925 926 #ifdef SIP_EVENT_COUNTERS 927 /* 928 * Attach event counters. 929 */ 930 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 931 NULL, sc->sc_dev.dv_xname, "txsstall"); 932 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 933 NULL, sc->sc_dev.dv_xname, "txdstall"); 934 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 935 NULL, sc->sc_dev.dv_xname, "txintr"); 936 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 937 NULL, sc->sc_dev.dv_xname, "rxintr"); 938 #ifdef DP83820 939 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 940 NULL, sc->sc_dev.dv_xname, "rxipsum"); 941 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 942 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 943 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 944 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 945 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 946 NULL, sc->sc_dev.dv_xname, "txipsum"); 947 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 948 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 949 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 950 NULL, sc->sc_dev.dv_xname, "txudpsum"); 951 #endif /* DP83820 */ 952 #endif /* SIP_EVENT_COUNTERS */ 953 954 /* 955 * Make sure the interface is shutdown during reboot. 956 */ 957 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 958 if (sc->sc_sdhook == NULL) 959 printf("%s: WARNING: unable to establish shutdown hook\n", 960 sc->sc_dev.dv_xname); 961 return; 962 963 /* 964 * Free any resources we've allocated during the failed attach 965 * attempt. Do this in reverse order and fall through. 966 */ 967 fail_5: 968 for (i = 0; i < SIP_NRXDESC; i++) { 969 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 970 bus_dmamap_destroy(sc->sc_dmat, 971 sc->sc_rxsoft[i].rxs_dmamap); 972 } 973 fail_4: 974 for (i = 0; i < SIP_TXQUEUELEN; i++) { 975 if (sc->sc_txsoft[i].txs_dmamap != NULL) 976 bus_dmamap_destroy(sc->sc_dmat, 977 sc->sc_txsoft[i].txs_dmamap); 978 } 979 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 980 fail_3: 981 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 982 fail_2: 983 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 984 sizeof(struct sip_control_data)); 985 fail_1: 986 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 987 fail_0: 988 return; 989 } 990 991 /* 992 * sip_shutdown: 993 * 994 * Make sure the interface is stopped at reboot time. 995 */ 996 void 997 SIP_DECL(shutdown)(void *arg) 998 { 999 struct sip_softc *sc = arg; 1000 1001 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1002 } 1003 1004 /* 1005 * sip_start: [ifnet interface function] 1006 * 1007 * Start packet transmission on the interface. 1008 */ 1009 void 1010 SIP_DECL(start)(struct ifnet *ifp) 1011 { 1012 struct sip_softc *sc = ifp->if_softc; 1013 struct mbuf *m0, *m; 1014 struct sip_txsoft *txs; 1015 bus_dmamap_t dmamap; 1016 int error, firsttx, nexttx, lasttx, ofree, seg; 1017 #ifdef DP83820 1018 u_int32_t extsts; 1019 #endif 1020 1021 /* 1022 * If we've been told to pause, don't transmit any more packets. 1023 */ 1024 if (sc->sc_flags & SIPF_PAUSED) 1025 ifp->if_flags |= IFF_OACTIVE; 1026 1027 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1028 return; 1029 1030 /* 1031 * Remember the previous number of free descriptors and 1032 * the first descriptor we'll use. 1033 */ 1034 ofree = sc->sc_txfree; 1035 firsttx = sc->sc_txnext; 1036 1037 /* 1038 * Loop through the send queue, setting up transmit descriptors 1039 * until we drain the queue, or use up all available transmit 1040 * descriptors. 1041 */ 1042 for (;;) { 1043 /* Get a work queue entry. */ 1044 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1045 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1046 break; 1047 } 1048 1049 /* 1050 * Grab a packet off the queue. 1051 */ 1052 IFQ_POLL(&ifp->if_snd, m0); 1053 if (m0 == NULL) 1054 break; 1055 #ifndef DP83820 1056 m = NULL; 1057 #endif 1058 1059 dmamap = txs->txs_dmamap; 1060 1061 #ifdef DP83820 1062 /* 1063 * Load the DMA map. If this fails, the packet either 1064 * didn't fit in the allotted number of segments, or we 1065 * were short on resources. For the too-many-segments 1066 * case, we simply report an error and drop the packet, 1067 * since we can't sanely copy a jumbo packet to a single 1068 * buffer. 1069 */ 1070 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1071 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1072 if (error) { 1073 if (error == EFBIG) { 1074 printf("%s: Tx packet consumes too many " 1075 "DMA segments, dropping...\n", 1076 sc->sc_dev.dv_xname); 1077 IFQ_DEQUEUE(&ifp->if_snd, m0); 1078 m_freem(m0); 1079 continue; 1080 } 1081 /* 1082 * Short on resources, just stop for now. 1083 */ 1084 break; 1085 } 1086 #else /* DP83820 */ 1087 /* 1088 * Load the DMA map. If this fails, the packet either 1089 * didn't fit in the alloted number of segments, or we 1090 * were short on resources. In this case, we'll copy 1091 * and try again. 1092 */ 1093 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1094 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1095 MGETHDR(m, M_DONTWAIT, MT_DATA); 1096 if (m == NULL) { 1097 printf("%s: unable to allocate Tx mbuf\n", 1098 sc->sc_dev.dv_xname); 1099 break; 1100 } 1101 if (m0->m_pkthdr.len > MHLEN) { 1102 MCLGET(m, M_DONTWAIT); 1103 if ((m->m_flags & M_EXT) == 0) { 1104 printf("%s: unable to allocate Tx " 1105 "cluster\n", sc->sc_dev.dv_xname); 1106 m_freem(m); 1107 break; 1108 } 1109 } 1110 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1111 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1112 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1113 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1114 if (error) { 1115 printf("%s: unable to load Tx buffer, " 1116 "error = %d\n", sc->sc_dev.dv_xname, error); 1117 break; 1118 } 1119 } 1120 #endif /* DP83820 */ 1121 1122 /* 1123 * Ensure we have enough descriptors free to describe 1124 * the packet. Note, we always reserve one descriptor 1125 * at the end of the ring as a termination point, to 1126 * prevent wrap-around. 1127 */ 1128 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1129 /* 1130 * Not enough free descriptors to transmit this 1131 * packet. We haven't committed anything yet, 1132 * so just unload the DMA map, put the packet 1133 * back on the queue, and punt. Notify the upper 1134 * layer that there are not more slots left. 1135 * 1136 * XXX We could allocate an mbuf and copy, but 1137 * XXX is it worth it? 1138 */ 1139 ifp->if_flags |= IFF_OACTIVE; 1140 bus_dmamap_unload(sc->sc_dmat, dmamap); 1141 #ifndef DP83820 1142 if (m != NULL) 1143 m_freem(m); 1144 #endif 1145 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1146 break; 1147 } 1148 1149 IFQ_DEQUEUE(&ifp->if_snd, m0); 1150 #ifndef DP83820 1151 if (m != NULL) { 1152 m_freem(m0); 1153 m0 = m; 1154 } 1155 #endif 1156 1157 /* 1158 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1159 */ 1160 1161 /* Sync the DMA map. */ 1162 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1163 BUS_DMASYNC_PREWRITE); 1164 1165 /* 1166 * Initialize the transmit descriptors. 1167 */ 1168 for (nexttx = sc->sc_txnext, seg = 0; 1169 seg < dmamap->dm_nsegs; 1170 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1171 /* 1172 * If this is the first descriptor we're 1173 * enqueueing, don't set the OWN bit just 1174 * yet. That could cause a race condition. 1175 * We'll do it below. 1176 */ 1177 sc->sc_txdescs[nexttx].sipd_bufptr = 1178 htole32(dmamap->dm_segs[seg].ds_addr); 1179 sc->sc_txdescs[nexttx].sipd_cmdsts = 1180 htole32((nexttx == firsttx ? 0 : CMDSTS_OWN) | 1181 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1182 #ifdef DP83820 1183 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1184 #endif /* DP83820 */ 1185 lasttx = nexttx; 1186 } 1187 1188 /* Clear the MORE bit on the last segment. */ 1189 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1190 1191 #ifdef DP83820 1192 /* 1193 * If VLANs are enabled and the packet has a VLAN tag, set 1194 * up the descriptor to encapsulate the packet for us. 1195 * 1196 * This apparently has to be on the last descriptor of 1197 * the packet. 1198 */ 1199 if (sc->sc_ethercom.ec_nvlans != 0 && 1200 (m = m_aux_find(m0, AF_LINK, ETHERTYPE_VLAN)) != NULL) { 1201 sc->sc_txdescs[lasttx].sipd_extsts |= 1202 htole32(EXTSTS_VPKT | 1203 htons(*mtod(m, int *) & EXTSTS_VTCI)); 1204 } 1205 1206 /* 1207 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1208 * checksumming, set up the descriptor to do this work 1209 * for us. 1210 * 1211 * This apparently has to be on the first descriptor of 1212 * the packet. 1213 * 1214 * Byte-swap constants so the compiler can optimize. 1215 */ 1216 extsts = 0; 1217 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1218 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1219 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1220 extsts |= htole32(EXTSTS_IPPKT); 1221 } 1222 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1223 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1224 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1225 extsts |= htole32(EXTSTS_TCPPKT); 1226 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1227 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1228 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1229 extsts |= htole32(EXTSTS_UDPPKT); 1230 } 1231 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1232 #endif /* DP83820 */ 1233 1234 /* Sync the descriptors we're using. */ 1235 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1236 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1237 1238 /* 1239 * Store a pointer to the packet so we can free it later, 1240 * and remember what txdirty will be once the packet is 1241 * done. 1242 */ 1243 txs->txs_mbuf = m0; 1244 txs->txs_firstdesc = sc->sc_txnext; 1245 txs->txs_lastdesc = lasttx; 1246 1247 /* Advance the tx pointer. */ 1248 sc->sc_txfree -= dmamap->dm_nsegs; 1249 sc->sc_txnext = nexttx; 1250 1251 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs, txs_q); 1252 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1253 1254 #if NBPFILTER > 0 1255 /* 1256 * Pass the packet to any BPF listeners. 1257 */ 1258 if (ifp->if_bpf) 1259 bpf_mtap(ifp->if_bpf, m0); 1260 #endif /* NBPFILTER > 0 */ 1261 } 1262 1263 if (txs == NULL || sc->sc_txfree == 0) { 1264 /* No more slots left; notify upper layer. */ 1265 ifp->if_flags |= IFF_OACTIVE; 1266 } 1267 1268 if (sc->sc_txfree != ofree) { 1269 /* 1270 * Cause a descriptor interrupt to happen on the 1271 * last packet we enqueued. 1272 */ 1273 sc->sc_txdescs[lasttx].sipd_cmdsts |= htole32(CMDSTS_INTR); 1274 SIP_CDTXSYNC(sc, lasttx, 1, 1275 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1276 1277 /* 1278 * The entire packet chain is set up. Give the 1279 * first descrptor to the chip now. 1280 */ 1281 sc->sc_txdescs[firsttx].sipd_cmdsts |= htole32(CMDSTS_OWN); 1282 SIP_CDTXSYNC(sc, firsttx, 1, 1283 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1284 1285 /* 1286 * Start the transmit process. Note, the manual says 1287 * that if there are no pending transmissions in the 1288 * chip's internal queue (indicated by TXE being clear), 1289 * then the driver software must set the TXDP to the 1290 * first descriptor to be transmitted. However, if we 1291 * do this, it causes serious performance degredation on 1292 * the DP83820 under load, not setting TXDP doesn't seem 1293 * to adversely affect the SiS 900 or DP83815. 1294 * 1295 * Well, I guess it wouldn't be the first time a manual 1296 * has lied -- and they could be speaking of the NULL- 1297 * terminated descriptor list case, rather than OWN- 1298 * terminated rings. 1299 */ 1300 #if 0 1301 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1302 CR_TXE) == 0) { 1303 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1304 SIP_CDTXADDR(sc, firsttx)); 1305 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1306 } 1307 #else 1308 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1309 #endif 1310 1311 /* Set a watchdog timer in case the chip flakes out. */ 1312 ifp->if_timer = 5; 1313 } 1314 } 1315 1316 /* 1317 * sip_watchdog: [ifnet interface function] 1318 * 1319 * Watchdog timer handler. 1320 */ 1321 void 1322 SIP_DECL(watchdog)(struct ifnet *ifp) 1323 { 1324 struct sip_softc *sc = ifp->if_softc; 1325 1326 /* 1327 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1328 * If we get a timeout, try and sweep up transmit descriptors. 1329 * If we manage to sweep them all up, ignore the lack of 1330 * interrupt. 1331 */ 1332 SIP_DECL(txintr)(sc); 1333 1334 if (sc->sc_txfree != SIP_NTXDESC) { 1335 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1336 ifp->if_oerrors++; 1337 1338 /* Reset the interface. */ 1339 (void) SIP_DECL(init)(ifp); 1340 } else if (ifp->if_flags & IFF_DEBUG) 1341 printf("%s: recovered from device timeout\n", 1342 sc->sc_dev.dv_xname); 1343 1344 /* Try to get more packets going. */ 1345 SIP_DECL(start)(ifp); 1346 } 1347 1348 /* 1349 * sip_ioctl: [ifnet interface function] 1350 * 1351 * Handle control requests from the operator. 1352 */ 1353 int 1354 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1355 { 1356 struct sip_softc *sc = ifp->if_softc; 1357 struct ifreq *ifr = (struct ifreq *)data; 1358 int s, error; 1359 1360 s = splnet(); 1361 1362 switch (cmd) { 1363 case SIOCSIFMEDIA: 1364 case SIOCGIFMEDIA: 1365 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1366 break; 1367 1368 default: 1369 error = ether_ioctl(ifp, cmd, data); 1370 if (error == ENETRESET) { 1371 /* 1372 * Multicast list has changed; set the hardware filter 1373 * accordingly. 1374 */ 1375 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1376 error = 0; 1377 } 1378 break; 1379 } 1380 1381 /* Try to get more packets going. */ 1382 SIP_DECL(start)(ifp); 1383 1384 splx(s); 1385 return (error); 1386 } 1387 1388 /* 1389 * sip_intr: 1390 * 1391 * Interrupt service routine. 1392 */ 1393 int 1394 SIP_DECL(intr)(void *arg) 1395 { 1396 struct sip_softc *sc = arg; 1397 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1398 u_int32_t isr; 1399 int handled = 0; 1400 1401 for (;;) { 1402 /* Reading clears interrupt. */ 1403 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1404 if ((isr & sc->sc_imr) == 0) 1405 break; 1406 1407 handled = 1; 1408 1409 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1410 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1411 1412 /* Grab any new packets. */ 1413 SIP_DECL(rxintr)(sc); 1414 1415 if (isr & ISR_RXORN) { 1416 printf("%s: receive FIFO overrun\n", 1417 sc->sc_dev.dv_xname); 1418 1419 /* XXX adjust rx_drain_thresh? */ 1420 } 1421 1422 if (isr & ISR_RXIDLE) { 1423 printf("%s: receive ring overrun\n", 1424 sc->sc_dev.dv_xname); 1425 1426 /* Get the receive process going again. */ 1427 bus_space_write_4(sc->sc_st, sc->sc_sh, 1428 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1429 bus_space_write_4(sc->sc_st, sc->sc_sh, 1430 SIP_CR, CR_RXE); 1431 } 1432 } 1433 1434 if (isr & (ISR_TXURN|ISR_TXDESC)) { 1435 SIP_EVCNT_INCR(&sc->sc_ev_txintr); 1436 1437 /* Sweep up transmit descriptors. */ 1438 SIP_DECL(txintr)(sc); 1439 1440 if (isr & ISR_TXURN) { 1441 u_int32_t thresh; 1442 1443 printf("%s: transmit FIFO underrun", 1444 sc->sc_dev.dv_xname); 1445 1446 thresh = sc->sc_tx_drain_thresh + 1; 1447 if (thresh <= TXCFG_DRTH && 1448 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1449 (sc->sc_tx_fill_thresh * 32))) { 1450 printf("; increasing Tx drain " 1451 "threshold to %u bytes\n", 1452 thresh * 32); 1453 sc->sc_tx_drain_thresh = thresh; 1454 (void) SIP_DECL(init)(ifp); 1455 } else { 1456 (void) SIP_DECL(init)(ifp); 1457 printf("\n"); 1458 } 1459 } 1460 } 1461 1462 #if !defined(DP83820) 1463 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1464 if (isr & ISR_PAUSE_ST) { 1465 sc->sc_flags |= SIPF_PAUSED; 1466 ifp->if_flags |= IFF_OACTIVE; 1467 } 1468 if (isr & ISR_PAUSE_END) { 1469 sc->sc_flags &= ~SIPF_PAUSED; 1470 ifp->if_flags &= ~IFF_OACTIVE; 1471 } 1472 } 1473 #endif /* ! DP83820 */ 1474 1475 if (isr & ISR_HIBERR) { 1476 #define PRINTERR(bit, str) \ 1477 if (isr & (bit)) \ 1478 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1479 PRINTERR(ISR_DPERR, "parity error"); 1480 PRINTERR(ISR_SSERR, "system error"); 1481 PRINTERR(ISR_RMABT, "master abort"); 1482 PRINTERR(ISR_RTABT, "target abort"); 1483 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1484 (void) SIP_DECL(init)(ifp); 1485 #undef PRINTERR 1486 } 1487 } 1488 1489 /* Try to get more packets going. */ 1490 SIP_DECL(start)(ifp); 1491 1492 return (handled); 1493 } 1494 1495 /* 1496 * sip_txintr: 1497 * 1498 * Helper; handle transmit interrupts. 1499 */ 1500 void 1501 SIP_DECL(txintr)(struct sip_softc *sc) 1502 { 1503 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1504 struct sip_txsoft *txs; 1505 u_int32_t cmdsts; 1506 1507 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1508 ifp->if_flags &= ~IFF_OACTIVE; 1509 1510 /* 1511 * Go through our Tx list and free mbufs for those 1512 * frames which have been transmitted. 1513 */ 1514 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1515 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1516 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1517 1518 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1519 if (cmdsts & CMDSTS_OWN) 1520 break; 1521 1522 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1523 1524 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1525 1526 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1527 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1528 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1529 m_freem(txs->txs_mbuf); 1530 txs->txs_mbuf = NULL; 1531 1532 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1533 1534 /* 1535 * Check for errors and collisions. 1536 */ 1537 if (cmdsts & 1538 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1539 ifp->if_oerrors++; 1540 if (cmdsts & CMDSTS_Tx_EC) 1541 ifp->if_collisions += 16; 1542 if (ifp->if_flags & IFF_DEBUG) { 1543 if (cmdsts & CMDSTS_Tx_ED) 1544 printf("%s: excessive deferral\n", 1545 sc->sc_dev.dv_xname); 1546 if (cmdsts & CMDSTS_Tx_EC) 1547 printf("%s: excessive collisions\n", 1548 sc->sc_dev.dv_xname); 1549 } 1550 } else { 1551 /* Packet was transmitted successfully. */ 1552 ifp->if_opackets++; 1553 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1554 } 1555 } 1556 1557 /* 1558 * If there are no more pending transmissions, cancel the watchdog 1559 * timer. 1560 */ 1561 if (txs == NULL) 1562 ifp->if_timer = 0; 1563 } 1564 1565 #if defined(DP83820) 1566 /* 1567 * sip_rxintr: 1568 * 1569 * Helper; handle receive interrupts. 1570 */ 1571 void 1572 SIP_DECL(rxintr)(struct sip_softc *sc) 1573 { 1574 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1575 struct sip_rxsoft *rxs; 1576 struct mbuf *m, *tailm; 1577 u_int32_t cmdsts, extsts; 1578 int i, len; 1579 1580 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1581 rxs = &sc->sc_rxsoft[i]; 1582 1583 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1584 1585 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1586 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1587 1588 /* 1589 * NOTE: OWN is set if owned by _consumer_. We're the 1590 * consumer of the receive ring, so if the bit is clear, 1591 * we have processed all of the packets. 1592 */ 1593 if ((cmdsts & CMDSTS_OWN) == 0) { 1594 /* 1595 * We have processed all of the receive buffers. 1596 */ 1597 break; 1598 } 1599 1600 if (__predict_false(sc->sc_rxdiscard)) { 1601 SIP_INIT_RXDESC(sc, i); 1602 if ((cmdsts & CMDSTS_MORE) == 0) { 1603 /* Reset our state. */ 1604 sc->sc_rxdiscard = 0; 1605 } 1606 continue; 1607 } 1608 1609 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1610 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1611 1612 m = rxs->rxs_mbuf; 1613 1614 /* 1615 * Add a new receive buffer to the ring. 1616 */ 1617 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1618 /* 1619 * Failed, throw away what we've done so 1620 * far, and discard the rest of the packet. 1621 */ 1622 ifp->if_ierrors++; 1623 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1624 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1625 SIP_INIT_RXDESC(sc, i); 1626 if (cmdsts & CMDSTS_MORE) 1627 sc->sc_rxdiscard = 1; 1628 if (sc->sc_rxhead != NULL) 1629 m_freem(sc->sc_rxhead); 1630 SIP_RXCHAIN_RESET(sc); 1631 continue; 1632 } 1633 1634 SIP_RXCHAIN_LINK(sc, m); 1635 1636 /* 1637 * If this is not the end of the packet, keep 1638 * looking. 1639 */ 1640 if (cmdsts & CMDSTS_MORE) { 1641 sc->sc_rxlen += m->m_len; 1642 continue; 1643 } 1644 1645 /* 1646 * Okay, we have the entire packet now... 1647 */ 1648 *sc->sc_rxtailp = NULL; 1649 m = sc->sc_rxhead; 1650 tailm = sc->sc_rxtail; 1651 1652 SIP_RXCHAIN_RESET(sc); 1653 1654 /* 1655 * If an error occurred, update stats and drop the packet. 1656 */ 1657 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1658 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1659 ifp->if_ierrors++; 1660 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1661 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1662 /* Receive overrun handled elsewhere. */ 1663 printf("%s: receive descriptor error\n", 1664 sc->sc_dev.dv_xname); 1665 } 1666 #define PRINTERR(bit, str) \ 1667 if (cmdsts & (bit)) \ 1668 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1669 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1670 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1671 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1672 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1673 #undef PRINTERR 1674 m_freem(m); 1675 continue; 1676 } 1677 1678 /* 1679 * No errors. 1680 * 1681 * Note, the DP83820 includes the CRC with 1682 * every packet. 1683 */ 1684 len = CMDSTS_SIZE(cmdsts); 1685 tailm->m_len = len - sc->sc_rxlen; 1686 1687 /* 1688 * If the packet is small enough to fit in a 1689 * single header mbuf, allocate one and copy 1690 * the data into it. This greatly reduces 1691 * memory consumption when we receive lots 1692 * of small packets. 1693 */ 1694 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1695 struct mbuf *nm; 1696 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1697 if (nm == NULL) { 1698 ifp->if_ierrors++; 1699 m_freem(m); 1700 continue; 1701 } 1702 nm->m_data += 2; 1703 nm->m_pkthdr.len = nm->m_len = len; 1704 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1705 m_freem(m); 1706 m = nm; 1707 } 1708 #ifndef __NO_STRICT_ALIGNMENT 1709 else { 1710 /* 1711 * The DP83820's receive buffers must be 4-byte 1712 * aligned. But this means that the data after 1713 * the Ethernet header is misaligned. To compensate, 1714 * we have artificially shortened the buffer size 1715 * in the descriptor, and we do an overlapping copy 1716 * of the data two bytes further in (in the first 1717 * buffer of the chain only). 1718 */ 1719 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1720 m->m_len); 1721 m->m_data += 2; 1722 } 1723 #endif /* ! __NO_STRICT_ALIGNMENT */ 1724 1725 /* 1726 * If VLANs are enabled, VLAN packets have been unwrapped 1727 * for us. Associate the tag with the packet. 1728 */ 1729 if (sc->sc_ethercom.ec_nvlans != 0 && 1730 (extsts & EXTSTS_VPKT) != 0) { 1731 struct mbuf *vtag; 1732 1733 vtag = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 1734 if (vtag == NULL) { 1735 ifp->if_ierrors++; 1736 printf("%s: unable to allocate VLAN tag\n", 1737 sc->sc_dev.dv_xname); 1738 m_freem(m); 1739 continue; 1740 } 1741 1742 *mtod(vtag, int *) = ntohs(extsts & EXTSTS_VTCI); 1743 vtag->m_len = sizeof(int); 1744 } 1745 1746 /* 1747 * Set the incoming checksum information for the 1748 * packet. 1749 */ 1750 if ((extsts & EXTSTS_IPPKT) != 0) { 1751 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1752 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1753 if (extsts & EXTSTS_Rx_IPERR) 1754 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1755 if (extsts & EXTSTS_TCPPKT) { 1756 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1757 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1758 if (extsts & EXTSTS_Rx_TCPERR) 1759 m->m_pkthdr.csum_flags |= 1760 M_CSUM_TCP_UDP_BAD; 1761 } else if (extsts & EXTSTS_UDPPKT) { 1762 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1763 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1764 if (extsts & EXTSTS_Rx_UDPERR) 1765 m->m_pkthdr.csum_flags |= 1766 M_CSUM_TCP_UDP_BAD; 1767 } 1768 } 1769 1770 ifp->if_ipackets++; 1771 m->m_flags |= M_HASFCS; 1772 m->m_pkthdr.rcvif = ifp; 1773 m->m_pkthdr.len = len; 1774 1775 #if NBPFILTER > 0 1776 /* 1777 * Pass this up to any BPF listeners, but only 1778 * pass if up the stack if it's for us. 1779 */ 1780 if (ifp->if_bpf) 1781 bpf_mtap(ifp->if_bpf, m); 1782 #endif /* NBPFILTER > 0 */ 1783 1784 /* Pass it on. */ 1785 (*ifp->if_input)(ifp, m); 1786 } 1787 1788 /* Update the receive pointer. */ 1789 sc->sc_rxptr = i; 1790 } 1791 #else /* ! DP83820 */ 1792 /* 1793 * sip_rxintr: 1794 * 1795 * Helper; handle receive interrupts. 1796 */ 1797 void 1798 SIP_DECL(rxintr)(struct sip_softc *sc) 1799 { 1800 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1801 struct sip_rxsoft *rxs; 1802 struct mbuf *m; 1803 u_int32_t cmdsts; 1804 int i, len; 1805 1806 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1807 rxs = &sc->sc_rxsoft[i]; 1808 1809 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1810 1811 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1812 1813 /* 1814 * NOTE: OWN is set if owned by _consumer_. We're the 1815 * consumer of the receive ring, so if the bit is clear, 1816 * we have processed all of the packets. 1817 */ 1818 if ((cmdsts & CMDSTS_OWN) == 0) { 1819 /* 1820 * We have processed all of the receive buffers. 1821 */ 1822 break; 1823 } 1824 1825 /* 1826 * If any collisions were seen on the wire, count one. 1827 */ 1828 if (cmdsts & CMDSTS_Rx_COL) 1829 ifp->if_collisions++; 1830 1831 /* 1832 * If an error occurred, update stats, clear the status 1833 * word, and leave the packet buffer in place. It will 1834 * simply be reused the next time the ring comes around. 1835 */ 1836 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1837 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1838 ifp->if_ierrors++; 1839 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1840 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1841 /* Receive overrun handled elsewhere. */ 1842 printf("%s: receive descriptor error\n", 1843 sc->sc_dev.dv_xname); 1844 } 1845 #define PRINTERR(bit, str) \ 1846 if (cmdsts & (bit)) \ 1847 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1848 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1849 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1850 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1851 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1852 #undef PRINTERR 1853 SIP_INIT_RXDESC(sc, i); 1854 continue; 1855 } 1856 1857 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1858 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1859 1860 /* 1861 * No errors; receive the packet. Note, the SiS 900 1862 * includes the CRC with every packet. 1863 */ 1864 len = CMDSTS_SIZE(cmdsts); 1865 1866 #ifdef __NO_STRICT_ALIGNMENT 1867 /* 1868 * If the packet is small enough to fit in a 1869 * single header mbuf, allocate one and copy 1870 * the data into it. This greatly reduces 1871 * memory consumption when we receive lots 1872 * of small packets. 1873 * 1874 * Otherwise, we add a new buffer to the receive 1875 * chain. If this fails, we drop the packet and 1876 * recycle the old buffer. 1877 */ 1878 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 1879 MGETHDR(m, M_DONTWAIT, MT_DATA); 1880 if (m == NULL) 1881 goto dropit; 1882 memcpy(mtod(m, caddr_t), 1883 mtod(rxs->rxs_mbuf, caddr_t), len); 1884 SIP_INIT_RXDESC(sc, i); 1885 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1886 rxs->rxs_dmamap->dm_mapsize, 1887 BUS_DMASYNC_PREREAD); 1888 } else { 1889 m = rxs->rxs_mbuf; 1890 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1891 dropit: 1892 ifp->if_ierrors++; 1893 SIP_INIT_RXDESC(sc, i); 1894 bus_dmamap_sync(sc->sc_dmat, 1895 rxs->rxs_dmamap, 0, 1896 rxs->rxs_dmamap->dm_mapsize, 1897 BUS_DMASYNC_PREREAD); 1898 continue; 1899 } 1900 } 1901 #else 1902 /* 1903 * The SiS 900's receive buffers must be 4-byte aligned. 1904 * But this means that the data after the Ethernet header 1905 * is misaligned. We must allocate a new buffer and 1906 * copy the data, shifted forward 2 bytes. 1907 */ 1908 MGETHDR(m, M_DONTWAIT, MT_DATA); 1909 if (m == NULL) { 1910 dropit: 1911 ifp->if_ierrors++; 1912 SIP_INIT_RXDESC(sc, i); 1913 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1914 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1915 continue; 1916 } 1917 if (len > (MHLEN - 2)) { 1918 MCLGET(m, M_DONTWAIT); 1919 if ((m->m_flags & M_EXT) == 0) { 1920 m_freem(m); 1921 goto dropit; 1922 } 1923 } 1924 m->m_data += 2; 1925 1926 /* 1927 * Note that we use clusters for incoming frames, so the 1928 * buffer is virtually contiguous. 1929 */ 1930 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 1931 1932 /* Allow the receive descriptor to continue using its mbuf. */ 1933 SIP_INIT_RXDESC(sc, i); 1934 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1935 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1936 #endif /* __NO_STRICT_ALIGNMENT */ 1937 1938 ifp->if_ipackets++; 1939 m->m_flags |= M_HASFCS; 1940 m->m_pkthdr.rcvif = ifp; 1941 m->m_pkthdr.len = m->m_len = len; 1942 1943 #if NBPFILTER > 0 1944 /* 1945 * Pass this up to any BPF listeners, but only 1946 * pass if up the stack if it's for us. 1947 */ 1948 if (ifp->if_bpf) 1949 bpf_mtap(ifp->if_bpf, m); 1950 #endif /* NBPFILTER > 0 */ 1951 1952 /* Pass it on. */ 1953 (*ifp->if_input)(ifp, m); 1954 } 1955 1956 /* Update the receive pointer. */ 1957 sc->sc_rxptr = i; 1958 } 1959 #endif /* DP83820 */ 1960 1961 /* 1962 * sip_tick: 1963 * 1964 * One second timer, used to tick the MII. 1965 */ 1966 void 1967 SIP_DECL(tick)(void *arg) 1968 { 1969 struct sip_softc *sc = arg; 1970 int s; 1971 1972 s = splnet(); 1973 mii_tick(&sc->sc_mii); 1974 splx(s); 1975 1976 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 1977 } 1978 1979 /* 1980 * sip_reset: 1981 * 1982 * Perform a soft reset on the SiS 900. 1983 */ 1984 void 1985 SIP_DECL(reset)(struct sip_softc *sc) 1986 { 1987 bus_space_tag_t st = sc->sc_st; 1988 bus_space_handle_t sh = sc->sc_sh; 1989 int i; 1990 1991 bus_space_write_4(st, sh, SIP_IER, 0); 1992 bus_space_write_4(st, sh, SIP_IMR, 0); 1993 bus_space_write_4(st, sh, SIP_RFCR, 0); 1994 bus_space_write_4(st, sh, SIP_CR, CR_RST); 1995 1996 for (i = 0; i < SIP_TIMEOUT; i++) { 1997 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 1998 break; 1999 delay(2); 2000 } 2001 2002 if (i == SIP_TIMEOUT) 2003 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2004 2005 delay(1000); 2006 2007 #ifdef DP83820 2008 /* 2009 * Set the general purpose I/O bits. Do it here in case we 2010 * need to have GPIO set up to talk to the media interface. 2011 */ 2012 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2013 delay(1000); 2014 #endif /* DP83820 */ 2015 } 2016 2017 /* 2018 * sip_init: [ ifnet interface function ] 2019 * 2020 * Initialize the interface. Must be called at splnet(). 2021 */ 2022 int 2023 SIP_DECL(init)(struct ifnet *ifp) 2024 { 2025 struct sip_softc *sc = ifp->if_softc; 2026 bus_space_tag_t st = sc->sc_st; 2027 bus_space_handle_t sh = sc->sc_sh; 2028 struct sip_txsoft *txs; 2029 struct sip_rxsoft *rxs; 2030 struct sip_desc *sipd; 2031 u_int32_t reg; 2032 int i, error = 0; 2033 2034 /* 2035 * Cancel any pending I/O. 2036 */ 2037 SIP_DECL(stop)(ifp, 0); 2038 2039 /* 2040 * Reset the chip to a known state. 2041 */ 2042 SIP_DECL(reset)(sc); 2043 2044 #if !defined(DP83820) 2045 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2046 /* 2047 * DP83815 manual, page 78: 2048 * 4.4 Recommended Registers Configuration 2049 * For optimum performance of the DP83815, version noted 2050 * as DP83815CVNG (SRR = 203h), the listed register 2051 * modifications must be followed in sequence... 2052 * 2053 * It's not clear if this should be 302h or 203h because that 2054 * chip name is listed as SRR 302h in the description of the 2055 * SRR register. However, my revision 302h DP83815 on the 2056 * Netgear FA311 purchased in 02/2001 needs these settings 2057 * to avoid tons of errors in AcceptPerfectMatch (non- 2058 * IFF_PROMISC) mode. I do not know if other revisions need 2059 * this set or not. [briggs -- 09 March 2001] 2060 * 2061 * Note that only the low-order 12 bits of 0xe4 are documented 2062 * and that this sets reserved bits in that register. 2063 */ 2064 reg = bus_space_read_4(st, sh, SIP_NS_SRR); 2065 if (reg == 0x302) { 2066 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2067 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2068 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2069 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2070 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2071 } 2072 } 2073 #endif /* ! DP83820 */ 2074 2075 /* 2076 * Initialize the transmit descriptor ring. 2077 */ 2078 for (i = 0; i < SIP_NTXDESC; i++) { 2079 sipd = &sc->sc_txdescs[i]; 2080 memset(sipd, 0, sizeof(struct sip_desc)); 2081 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2082 } 2083 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2084 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2085 sc->sc_txfree = SIP_NTXDESC; 2086 sc->sc_txnext = 0; 2087 2088 /* 2089 * Initialize the transmit job descriptors. 2090 */ 2091 SIMPLEQ_INIT(&sc->sc_txfreeq); 2092 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2093 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2094 txs = &sc->sc_txsoft[i]; 2095 txs->txs_mbuf = NULL; 2096 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2097 } 2098 2099 /* 2100 * Initialize the receive descriptor and receive job 2101 * descriptor rings. 2102 */ 2103 for (i = 0; i < SIP_NRXDESC; i++) { 2104 rxs = &sc->sc_rxsoft[i]; 2105 if (rxs->rxs_mbuf == NULL) { 2106 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2107 printf("%s: unable to allocate or map rx " 2108 "buffer %d, error = %d\n", 2109 sc->sc_dev.dv_xname, i, error); 2110 /* 2111 * XXX Should attempt to run with fewer receive 2112 * XXX buffers instead of just failing. 2113 */ 2114 SIP_DECL(rxdrain)(sc); 2115 goto out; 2116 } 2117 } else 2118 SIP_INIT_RXDESC(sc, i); 2119 } 2120 sc->sc_rxptr = 0; 2121 #ifdef DP83820 2122 sc->sc_rxdiscard = 0; 2123 SIP_RXCHAIN_RESET(sc); 2124 #endif /* DP83820 */ 2125 2126 /* 2127 * Set the configuration register; it's already initialized 2128 * in sip_attach(). 2129 */ 2130 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2131 2132 /* 2133 * Initialize the prototype TXCFG register. 2134 */ 2135 #if defined(DP83820) 2136 sc->sc_txcfg = TXCFG_MXDMA_512; 2137 sc->sc_rxcfg = RXCFG_MXDMA_512; 2138 #else 2139 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2140 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2141 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & CFG_EDBMASTEN)) { 2142 sc->sc_txcfg = TXCFG_MXDMA_64; 2143 sc->sc_rxcfg = RXCFG_MXDMA_64; 2144 } else { 2145 sc->sc_txcfg = TXCFG_MXDMA_512; 2146 sc->sc_rxcfg = RXCFG_MXDMA_512; 2147 } 2148 #endif /* DP83820 */ 2149 2150 sc->sc_txcfg |= TXCFG_ATP | 2151 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2152 sc->sc_tx_drain_thresh; 2153 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2154 2155 /* 2156 * Initialize the receive drain threshold if we have never 2157 * done so. 2158 */ 2159 if (sc->sc_rx_drain_thresh == 0) { 2160 /* 2161 * XXX This value should be tuned. This is set to the 2162 * maximum of 248 bytes, and we may be able to improve 2163 * performance by decreasing it (although we should never 2164 * set this value lower than 2; 14 bytes are required to 2165 * filter the packet). 2166 */ 2167 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2168 } 2169 2170 /* 2171 * Initialize the prototype RXCFG register. 2172 */ 2173 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2174 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2175 2176 #ifdef DP83820 2177 /* 2178 * Initialize the VLAN/IP receive control register. 2179 * We enable checksum computation on all incoming 2180 * packets, and do not reject packets w/ bad checksums. 2181 */ 2182 reg = 0; 2183 if (ifp->if_capenable & 2184 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2185 reg |= VRCR_IPEN; 2186 if (sc->sc_ethercom.ec_nvlans != 0) 2187 reg |= VRCR_VTDEN|VRCR_VTREN; 2188 bus_space_write_4(st, sh, SIP_VRCR, reg); 2189 2190 /* 2191 * Initialize the VLAN/IP transmit control register. 2192 * We enable outgoing checksum computation on a 2193 * per-packet basis. 2194 */ 2195 reg = 0; 2196 if (ifp->if_capenable & 2197 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2198 reg |= VTCR_PPCHK; 2199 if (sc->sc_ethercom.ec_nvlans != 0) 2200 reg |= VTCR_VPPTI; 2201 bus_space_write_4(st, sh, SIP_VTCR, reg); 2202 2203 /* 2204 * If we're using VLANs, initialize the VLAN data register. 2205 * To understand why we bswap the VLAN Ethertype, see section 2206 * 4.2.36 of the DP83820 manual. 2207 */ 2208 if (sc->sc_ethercom.ec_nvlans != 0) 2209 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2210 #endif /* DP83820 */ 2211 2212 /* 2213 * Give the transmit and receive rings to the chip. 2214 */ 2215 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2216 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2217 2218 /* 2219 * Initialize the interrupt mask. 2220 */ 2221 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2222 ISR_TXURN|ISR_TXDESC|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2223 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2224 2225 /* Set up the receive filter. */ 2226 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2227 2228 /* 2229 * Set the current media. Do this after initializing the prototype 2230 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2231 * control. 2232 */ 2233 mii_mediachg(&sc->sc_mii); 2234 2235 /* 2236 * Enable interrupts. 2237 */ 2238 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2239 2240 /* 2241 * Start the transmit and receive processes. 2242 */ 2243 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2244 2245 /* 2246 * Start the one second MII clock. 2247 */ 2248 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2249 2250 /* 2251 * ...all done! 2252 */ 2253 ifp->if_flags |= IFF_RUNNING; 2254 ifp->if_flags &= ~IFF_OACTIVE; 2255 2256 out: 2257 if (error) 2258 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2259 return (error); 2260 } 2261 2262 /* 2263 * sip_drain: 2264 * 2265 * Drain the receive queue. 2266 */ 2267 void 2268 SIP_DECL(rxdrain)(struct sip_softc *sc) 2269 { 2270 struct sip_rxsoft *rxs; 2271 int i; 2272 2273 for (i = 0; i < SIP_NRXDESC; i++) { 2274 rxs = &sc->sc_rxsoft[i]; 2275 if (rxs->rxs_mbuf != NULL) { 2276 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2277 m_freem(rxs->rxs_mbuf); 2278 rxs->rxs_mbuf = NULL; 2279 } 2280 } 2281 } 2282 2283 /* 2284 * sip_stop: [ ifnet interface function ] 2285 * 2286 * Stop transmission on the interface. 2287 */ 2288 void 2289 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2290 { 2291 struct sip_softc *sc = ifp->if_softc; 2292 bus_space_tag_t st = sc->sc_st; 2293 bus_space_handle_t sh = sc->sc_sh; 2294 struct sip_txsoft *txs; 2295 u_int32_t cmdsts = 0; /* DEBUG */ 2296 2297 /* 2298 * Stop the one second clock. 2299 */ 2300 callout_stop(&sc->sc_tick_ch); 2301 2302 /* Down the MII. */ 2303 mii_down(&sc->sc_mii); 2304 2305 /* 2306 * Disable interrupts. 2307 */ 2308 bus_space_write_4(st, sh, SIP_IER, 0); 2309 2310 /* 2311 * Stop receiver and transmitter. 2312 */ 2313 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2314 2315 /* 2316 * Release any queued transmit buffers. 2317 */ 2318 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2319 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2320 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2321 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2322 CMDSTS_INTR) == 0) 2323 printf("%s: sip_stop: last descriptor does not " 2324 "have INTR bit set\n", sc->sc_dev.dv_xname); 2325 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 2326 #ifdef DIAGNOSTIC 2327 if (txs->txs_mbuf == NULL) { 2328 printf("%s: dirty txsoft with no mbuf chain\n", 2329 sc->sc_dev.dv_xname); 2330 panic("sip_stop"); 2331 } 2332 #endif 2333 cmdsts |= /* DEBUG */ 2334 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2335 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2336 m_freem(txs->txs_mbuf); 2337 txs->txs_mbuf = NULL; 2338 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2339 } 2340 2341 if (disable) 2342 SIP_DECL(rxdrain)(sc); 2343 2344 /* 2345 * Mark the interface down and cancel the watchdog timer. 2346 */ 2347 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2348 ifp->if_timer = 0; 2349 2350 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2351 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2352 printf("%s: sip_stop: no INTR bits set in dirty tx " 2353 "descriptors\n", sc->sc_dev.dv_xname); 2354 } 2355 2356 /* 2357 * sip_read_eeprom: 2358 * 2359 * Read data from the serial EEPROM. 2360 */ 2361 void 2362 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2363 u_int16_t *data) 2364 { 2365 bus_space_tag_t st = sc->sc_st; 2366 bus_space_handle_t sh = sc->sc_sh; 2367 u_int16_t reg; 2368 int i, x; 2369 2370 for (i = 0; i < wordcnt; i++) { 2371 /* Send CHIP SELECT. */ 2372 reg = EROMAR_EECS; 2373 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2374 2375 /* Shift in the READ opcode. */ 2376 for (x = 3; x > 0; x--) { 2377 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2378 reg |= EROMAR_EEDI; 2379 else 2380 reg &= ~EROMAR_EEDI; 2381 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2382 bus_space_write_4(st, sh, SIP_EROMAR, 2383 reg | EROMAR_EESK); 2384 delay(4); 2385 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2386 delay(4); 2387 } 2388 2389 /* Shift in address. */ 2390 for (x = 6; x > 0; x--) { 2391 if ((word + i) & (1 << (x - 1))) 2392 reg |= EROMAR_EEDI; 2393 else 2394 reg &= ~EROMAR_EEDI; 2395 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2396 bus_space_write_4(st, sh, SIP_EROMAR, 2397 reg | EROMAR_EESK); 2398 delay(4); 2399 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2400 delay(4); 2401 } 2402 2403 /* Shift out data. */ 2404 reg = EROMAR_EECS; 2405 data[i] = 0; 2406 for (x = 16; x > 0; x--) { 2407 bus_space_write_4(st, sh, SIP_EROMAR, 2408 reg | EROMAR_EESK); 2409 delay(4); 2410 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2411 data[i] |= (1 << (x - 1)); 2412 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2413 delay(4); 2414 } 2415 2416 /* Clear CHIP SELECT. */ 2417 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2418 delay(4); 2419 } 2420 } 2421 2422 /* 2423 * sip_add_rxbuf: 2424 * 2425 * Add a receive buffer to the indicated descriptor. 2426 */ 2427 int 2428 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2429 { 2430 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2431 struct mbuf *m; 2432 int error; 2433 2434 MGETHDR(m, M_DONTWAIT, MT_DATA); 2435 if (m == NULL) 2436 return (ENOBUFS); 2437 2438 MCLGET(m, M_DONTWAIT); 2439 if ((m->m_flags & M_EXT) == 0) { 2440 m_freem(m); 2441 return (ENOBUFS); 2442 } 2443 2444 #if defined(DP83820) 2445 m->m_len = SIP_RXBUF_LEN; 2446 #endif /* DP83820 */ 2447 2448 if (rxs->rxs_mbuf != NULL) 2449 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2450 2451 rxs->rxs_mbuf = m; 2452 2453 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2454 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2455 BUS_DMA_READ|BUS_DMA_NOWAIT); 2456 if (error) { 2457 printf("%s: can't load rx DMA map %d, error = %d\n", 2458 sc->sc_dev.dv_xname, idx, error); 2459 panic("sip_add_rxbuf"); /* XXX */ 2460 } 2461 2462 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2463 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2464 2465 SIP_INIT_RXDESC(sc, idx); 2466 2467 return (0); 2468 } 2469 2470 #if !defined(DP83820) 2471 /* 2472 * sip_sis900_set_filter: 2473 * 2474 * Set up the receive filter. 2475 */ 2476 void 2477 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2478 { 2479 bus_space_tag_t st = sc->sc_st; 2480 bus_space_handle_t sh = sc->sc_sh; 2481 struct ethercom *ec = &sc->sc_ethercom; 2482 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2483 struct ether_multi *enm; 2484 u_int8_t *cp; 2485 struct ether_multistep step; 2486 u_int32_t crc, mchash[16]; 2487 2488 /* 2489 * Initialize the prototype RFCR. 2490 */ 2491 sc->sc_rfcr = RFCR_RFEN; 2492 if (ifp->if_flags & IFF_BROADCAST) 2493 sc->sc_rfcr |= RFCR_AAB; 2494 if (ifp->if_flags & IFF_PROMISC) { 2495 sc->sc_rfcr |= RFCR_AAP; 2496 goto allmulti; 2497 } 2498 2499 /* 2500 * Set up the multicast address filter by passing all multicast 2501 * addresses through a CRC generator, and then using the high-order 2502 * 6 bits as an index into the 128 bit multicast hash table (only 2503 * the lower 16 bits of each 32 bit multicast hash register are 2504 * valid). The high order bits select the register, while the 2505 * rest of the bits select the bit within the register. 2506 */ 2507 2508 memset(mchash, 0, sizeof(mchash)); 2509 2510 ETHER_FIRST_MULTI(step, ec, enm); 2511 while (enm != NULL) { 2512 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2513 /* 2514 * We must listen to a range of multicast addresses. 2515 * For now, just accept all multicasts, rather than 2516 * trying to set only those filter bits needed to match 2517 * the range. (At this time, the only use of address 2518 * ranges is for IP multicast routing, for which the 2519 * range is big enough to require all bits set.) 2520 */ 2521 goto allmulti; 2522 } 2523 2524 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2525 2526 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2527 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2528 /* Just want the 8 most significant bits. */ 2529 crc >>= 24; 2530 } else { 2531 /* Just want the 7 most significant bits. */ 2532 crc >>= 25; 2533 } 2534 2535 /* Set the corresponding bit in the hash table. */ 2536 mchash[crc >> 4] |= 1 << (crc & 0xf); 2537 2538 ETHER_NEXT_MULTI(step, enm); 2539 } 2540 2541 ifp->if_flags &= ~IFF_ALLMULTI; 2542 goto setit; 2543 2544 allmulti: 2545 ifp->if_flags |= IFF_ALLMULTI; 2546 sc->sc_rfcr |= RFCR_AAM; 2547 2548 setit: 2549 #define FILTER_EMIT(addr, data) \ 2550 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2551 delay(1); \ 2552 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2553 delay(1) 2554 2555 /* 2556 * Disable receive filter, and program the node address. 2557 */ 2558 cp = LLADDR(ifp->if_sadl); 2559 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2560 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2561 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2562 2563 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2564 /* 2565 * Program the multicast hash table. 2566 */ 2567 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2568 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2569 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2570 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2571 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2572 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2573 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2574 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2575 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2576 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2577 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2578 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2579 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2580 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2581 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2582 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2583 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2584 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2585 } 2586 } 2587 #undef FILTER_EMIT 2588 2589 /* 2590 * Re-enable the receiver filter. 2591 */ 2592 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2593 } 2594 #endif /* ! DP83820 */ 2595 2596 /* 2597 * sip_dp83815_set_filter: 2598 * 2599 * Set up the receive filter. 2600 */ 2601 void 2602 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2603 { 2604 bus_space_tag_t st = sc->sc_st; 2605 bus_space_handle_t sh = sc->sc_sh; 2606 struct ethercom *ec = &sc->sc_ethercom; 2607 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2608 struct ether_multi *enm; 2609 u_int8_t *cp; 2610 struct ether_multistep step; 2611 u_int32_t crc, hash, slot, bit; 2612 #ifdef DP83820 2613 #define MCHASH_NWORDS 128 2614 #else 2615 #define MCHASH_NWORDS 32 2616 #endif /* DP83820 */ 2617 u_int16_t mchash[MCHASH_NWORDS]; 2618 int i; 2619 2620 /* 2621 * Initialize the prototype RFCR. 2622 * Enable the receive filter, and accept on 2623 * Perfect (destination address) Match 2624 * If IFF_BROADCAST, also accept all broadcast packets. 2625 * If IFF_PROMISC, accept all unicast packets (and later, set 2626 * IFF_ALLMULTI and accept all multicast, too). 2627 */ 2628 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2629 if (ifp->if_flags & IFF_BROADCAST) 2630 sc->sc_rfcr |= RFCR_AAB; 2631 if (ifp->if_flags & IFF_PROMISC) { 2632 sc->sc_rfcr |= RFCR_AAP; 2633 goto allmulti; 2634 } 2635 2636 #ifdef DP83820 2637 /* 2638 * Set up the DP83820 multicast address filter by passing all multicast 2639 * addresses through a CRC generator, and then using the high-order 2640 * 11 bits as an index into the 2048 bit multicast hash table. The 2641 * high-order 7 bits select the slot, while the low-order 4 bits 2642 * select the bit within the slot. Note that only the low 16-bits 2643 * of each filter word are used, and there are 128 filter words. 2644 */ 2645 #else 2646 /* 2647 * Set up the DP83815 multicast address filter by passing all multicast 2648 * addresses through a CRC generator, and then using the high-order 2649 * 9 bits as an index into the 512 bit multicast hash table. The 2650 * high-order 5 bits select the slot, while the low-order 4 bits 2651 * select the bit within the slot. Note that only the low 16-bits 2652 * of each filter word are used, and there are 32 filter words. 2653 */ 2654 #endif /* DP83820 */ 2655 2656 memset(mchash, 0, sizeof(mchash)); 2657 2658 ifp->if_flags &= ~IFF_ALLMULTI; 2659 ETHER_FIRST_MULTI(step, ec, enm); 2660 if (enm == NULL) 2661 goto setit; 2662 while (enm != NULL) { 2663 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2664 /* 2665 * We must listen to a range of multicast addresses. 2666 * For now, just accept all multicasts, rather than 2667 * trying to set only those filter bits needed to match 2668 * the range. (At this time, the only use of address 2669 * ranges is for IP multicast routing, for which the 2670 * range is big enough to require all bits set.) 2671 */ 2672 goto allmulti; 2673 } 2674 2675 #ifdef DP83820 2676 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2677 2678 /* Just want the 11 most significant bits. */ 2679 hash = crc >> 21; 2680 #else 2681 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2682 2683 /* Just want the 9 most significant bits. */ 2684 hash = crc >> 23; 2685 #endif /* DP83820 */ 2686 slot = hash >> 4; 2687 bit = hash & 0xf; 2688 2689 /* Set the corresponding bit in the hash table. */ 2690 mchash[slot] |= 1 << bit; 2691 2692 ETHER_NEXT_MULTI(step, enm); 2693 } 2694 sc->sc_rfcr |= RFCR_MHEN; 2695 goto setit; 2696 2697 allmulti: 2698 ifp->if_flags |= IFF_ALLMULTI; 2699 sc->sc_rfcr |= RFCR_AAM; 2700 2701 setit: 2702 #define FILTER_EMIT(addr, data) \ 2703 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2704 delay(1); \ 2705 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2706 delay(1) 2707 2708 /* 2709 * Disable receive filter, and program the node address. 2710 */ 2711 cp = LLADDR(ifp->if_sadl); 2712 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 2713 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 2714 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 2715 2716 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2717 /* 2718 * Program the multicast hash table. 2719 */ 2720 for (i = 0; i < MCHASH_NWORDS; i++) { 2721 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 2722 mchash[i]); 2723 } 2724 } 2725 #undef FILTER_EMIT 2726 #undef MCHASH_NWORDS 2727 2728 /* 2729 * Re-enable the receiver filter. 2730 */ 2731 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2732 } 2733 2734 #if defined(DP83820) 2735 /* 2736 * sip_dp83820_mii_readreg: [mii interface function] 2737 * 2738 * Read a PHY register on the MII of the DP83820. 2739 */ 2740 int 2741 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 2742 { 2743 2744 return (mii_bitbang_readreg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2745 phy, reg)); 2746 } 2747 2748 /* 2749 * sip_dp83820_mii_writereg: [mii interface function] 2750 * 2751 * Write a PHY register on the MII of the DP83820. 2752 */ 2753 void 2754 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 2755 { 2756 2757 mii_bitbang_writereg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2758 phy, reg, val); 2759 } 2760 2761 /* 2762 * sip_dp83815_mii_statchg: [mii interface function] 2763 * 2764 * Callback from MII layer when media changes. 2765 */ 2766 void 2767 SIP_DECL(dp83820_mii_statchg)(struct device *self) 2768 { 2769 struct sip_softc *sc = (struct sip_softc *) self; 2770 u_int32_t cfg; 2771 2772 /* 2773 * Update TXCFG for full-duplex operation. 2774 */ 2775 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2776 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2777 else 2778 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2779 2780 /* 2781 * Update RXCFG for full-duplex or loopback. 2782 */ 2783 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2784 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2785 sc->sc_rxcfg |= RXCFG_ATX; 2786 else 2787 sc->sc_rxcfg &= ~RXCFG_ATX; 2788 2789 /* 2790 * Update CFG for MII/GMII. 2791 */ 2792 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2793 cfg = sc->sc_cfg | CFG_MODE_1000; 2794 else 2795 cfg = sc->sc_cfg; 2796 2797 /* 2798 * XXX 802.3x flow control. 2799 */ 2800 2801 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 2802 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2803 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2804 } 2805 2806 /* 2807 * sip_dp83820_mii_bitbang_read: [mii bit-bang interface function] 2808 * 2809 * Read the MII serial port for the MII bit-bang module. 2810 */ 2811 u_int32_t 2812 SIP_DECL(dp83820_mii_bitbang_read)(struct device *self) 2813 { 2814 struct sip_softc *sc = (void *) self; 2815 2816 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 2817 } 2818 2819 /* 2820 * sip_dp83820_mii_bitbang_write: [mii big-bang interface function] 2821 * 2822 * Write the MII serial port for the MII bit-bang module. 2823 */ 2824 void 2825 SIP_DECL(dp83820_mii_bitbang_write)(struct device *self, u_int32_t val) 2826 { 2827 struct sip_softc *sc = (void *) self; 2828 2829 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 2830 } 2831 #else /* ! DP83820 */ 2832 /* 2833 * sip_sis900_mii_readreg: [mii interface function] 2834 * 2835 * Read a PHY register on the MII. 2836 */ 2837 int 2838 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 2839 { 2840 struct sip_softc *sc = (struct sip_softc *) self; 2841 u_int32_t enphy; 2842 2843 /* 2844 * The SiS 900 has only an internal PHY on the MII. Only allow 2845 * MII address 0. 2846 */ 2847 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 2848 sc->sc_rev < SIS_REV_635 && phy != 0) 2849 return (0); 2850 2851 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2852 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 2853 ENPHY_RWCMD | ENPHY_ACCESS); 2854 do { 2855 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2856 } while (enphy & ENPHY_ACCESS); 2857 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 2858 } 2859 2860 /* 2861 * sip_sis900_mii_writereg: [mii interface function] 2862 * 2863 * Write a PHY register on the MII. 2864 */ 2865 void 2866 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 2867 { 2868 struct sip_softc *sc = (struct sip_softc *) self; 2869 u_int32_t enphy; 2870 2871 /* 2872 * The SiS 900 has only an internal PHY on the MII. Only allow 2873 * MII address 0. 2874 */ 2875 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 2876 sc->sc_rev < SIS_REV_635 && phy != 0) 2877 return; 2878 2879 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2880 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 2881 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 2882 do { 2883 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2884 } while (enphy & ENPHY_ACCESS); 2885 } 2886 2887 /* 2888 * sip_sis900_mii_statchg: [mii interface function] 2889 * 2890 * Callback from MII layer when media changes. 2891 */ 2892 void 2893 SIP_DECL(sis900_mii_statchg)(struct device *self) 2894 { 2895 struct sip_softc *sc = (struct sip_softc *) self; 2896 u_int32_t flowctl; 2897 2898 /* 2899 * Update TXCFG for full-duplex operation. 2900 */ 2901 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2902 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2903 else 2904 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2905 2906 /* 2907 * Update RXCFG for full-duplex or loopback. 2908 */ 2909 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2910 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2911 sc->sc_rxcfg |= RXCFG_ATX; 2912 else 2913 sc->sc_rxcfg &= ~RXCFG_ATX; 2914 2915 /* 2916 * Update IMR for use of 802.3x flow control. 2917 */ 2918 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 2919 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 2920 flowctl = FLOWCTL_FLOWEN; 2921 } else { 2922 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 2923 flowctl = 0; 2924 } 2925 2926 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2927 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2928 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 2929 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 2930 } 2931 2932 /* 2933 * sip_dp83815_mii_readreg: [mii interface function] 2934 * 2935 * Read a PHY register on the MII. 2936 */ 2937 int 2938 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 2939 { 2940 struct sip_softc *sc = (struct sip_softc *) self; 2941 u_int32_t val; 2942 2943 /* 2944 * The DP83815 only has an internal PHY. Only allow 2945 * MII address 0. 2946 */ 2947 if (phy != 0) 2948 return (0); 2949 2950 /* 2951 * Apparently, after a reset, the DP83815 can take a while 2952 * to respond. During this recovery period, the BMSR returns 2953 * a value of 0. Catch this -- it's not supposed to happen 2954 * (the BMSR has some hardcoded-to-1 bits), and wait for the 2955 * PHY to come back to life. 2956 * 2957 * This works out because the BMSR is the first register 2958 * read during the PHY probe process. 2959 */ 2960 do { 2961 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 2962 } while (reg == MII_BMSR && val == 0); 2963 2964 return (val & 0xffff); 2965 } 2966 2967 /* 2968 * sip_dp83815_mii_writereg: [mii interface function] 2969 * 2970 * Write a PHY register to the MII. 2971 */ 2972 void 2973 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 2974 { 2975 struct sip_softc *sc = (struct sip_softc *) self; 2976 2977 /* 2978 * The DP83815 only has an internal PHY. Only allow 2979 * MII address 0. 2980 */ 2981 if (phy != 0) 2982 return; 2983 2984 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 2985 } 2986 2987 /* 2988 * sip_dp83815_mii_statchg: [mii interface function] 2989 * 2990 * Callback from MII layer when media changes. 2991 */ 2992 void 2993 SIP_DECL(dp83815_mii_statchg)(struct device *self) 2994 { 2995 struct sip_softc *sc = (struct sip_softc *) self; 2996 2997 /* 2998 * Update TXCFG for full-duplex operation. 2999 */ 3000 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3001 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3002 else 3003 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3004 3005 /* 3006 * Update RXCFG for full-duplex or loopback. 3007 */ 3008 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3009 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3010 sc->sc_rxcfg |= RXCFG_ATX; 3011 else 3012 sc->sc_rxcfg &= ~RXCFG_ATX; 3013 3014 /* 3015 * XXX 802.3x flow control. 3016 */ 3017 3018 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3019 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3020 } 3021 #endif /* DP83820 */ 3022 3023 #if defined(DP83820) 3024 void 3025 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3026 const struct pci_attach_args *pa, u_int8_t *enaddr) 3027 { 3028 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3029 u_int8_t cksum, *e, match; 3030 int i; 3031 3032 /* 3033 * EEPROM data format for the DP83820 can be found in 3034 * the DP83820 manual, section 4.2.4. 3035 */ 3036 3037 SIP_DECL(read_eeprom)(sc, 0, 3038 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3039 3040 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3041 match = ~(match - 1); 3042 3043 cksum = 0x55; 3044 e = (u_int8_t *) eeprom_data; 3045 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3046 cksum += *e++; 3047 3048 if (cksum != match) 3049 printf("%s: Checksum (%x) mismatch (%x)", 3050 sc->sc_dev.dv_xname, cksum, match); 3051 3052 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3053 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3054 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3055 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3056 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3057 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3058 3059 /* Get the GPIOR bits. */ 3060 sc->sc_gpior = eeprom_data[0x04]; 3061 3062 /* Get various CFG related bits. */ 3063 if ((eeprom_data[0x05] >> 0) & 1) 3064 sc->sc_cfg |= CFG_EXT_125; 3065 if ((eeprom_data[0x05] >> 9) & 1) 3066 sc->sc_cfg |= CFG_TBI_EN; 3067 } 3068 #else /* ! DP83820 */ 3069 void 3070 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3071 const struct pci_attach_args *pa, u_int8_t *enaddr) 3072 { 3073 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3074 3075 switch (PCI_REVISION(pa->pa_class)) { 3076 case SIS_REV_630S: 3077 case SIS_REV_630E: 3078 case SIS_REV_630EA1: 3079 case SIS_REV_635: 3080 /* 3081 * The MAC address for the on-board Ethernet of 3082 * the SiS 630 chipset is in the NVRAM. Kick 3083 * the chip into re-loading it from NVRAM, and 3084 * read the MAC address out of the filter registers. 3085 */ 3086 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3087 3088 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3089 RFCR_RFADDR_NODE0); 3090 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3091 0xffff; 3092 3093 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3094 RFCR_RFADDR_NODE2); 3095 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3096 0xffff; 3097 3098 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3099 RFCR_RFADDR_NODE4); 3100 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3101 0xffff; 3102 break; 3103 3104 default: 3105 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3106 sizeof(myea) / sizeof(myea[0]), myea); 3107 } 3108 3109 enaddr[0] = myea[0] & 0xff; 3110 enaddr[1] = myea[0] >> 8; 3111 enaddr[2] = myea[1] & 0xff; 3112 enaddr[3] = myea[1] >> 8; 3113 enaddr[4] = myea[2] & 0xff; 3114 enaddr[5] = myea[2] >> 8; 3115 } 3116 3117 /* Table and macro to bit-reverse an octet. */ 3118 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3119 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3120 3121 void 3122 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3123 const struct pci_attach_args *pa, u_int8_t *enaddr) 3124 { 3125 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3126 u_int8_t cksum, *e, match; 3127 int i; 3128 3129 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3130 sizeof(eeprom_data[0]), eeprom_data); 3131 3132 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3133 match = ~(match - 1); 3134 3135 cksum = 0x55; 3136 e = (u_int8_t *) eeprom_data; 3137 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3138 cksum += *e++; 3139 } 3140 if (cksum != match) { 3141 printf("%s: Checksum (%x) mismatch (%x)", 3142 sc->sc_dev.dv_xname, cksum, match); 3143 } 3144 3145 /* 3146 * Unrolled because it makes slightly more sense this way. 3147 * The DP83815 stores the MAC address in bit 0 of word 6 3148 * through bit 15 of word 8. 3149 */ 3150 ea = &eeprom_data[6]; 3151 enaddr[0] = ((*ea & 0x1) << 7); 3152 ea++; 3153 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3154 enaddr[1] = ((*ea & 0x1FE) >> 1); 3155 enaddr[2] = ((*ea & 0x1) << 7); 3156 ea++; 3157 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3158 enaddr[3] = ((*ea & 0x1FE) >> 1); 3159 enaddr[4] = ((*ea & 0x1) << 7); 3160 ea++; 3161 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3162 enaddr[5] = ((*ea & 0x1FE) >> 1); 3163 3164 /* 3165 * In case that's not weird enough, we also need to reverse 3166 * the bits in each byte. This all actually makes more sense 3167 * if you think about the EEPROM storage as an array of bits 3168 * being shifted into bytes, but that's not how we're looking 3169 * at it here... 3170 */ 3171 for (i = 0; i < 6 ;i++) 3172 enaddr[i] = bbr(enaddr[i]); 3173 } 3174 #endif /* DP83820 */ 3175 3176 /* 3177 * sip_mediastatus: [ifmedia interface function] 3178 * 3179 * Get the current interface media status. 3180 */ 3181 void 3182 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3183 { 3184 struct sip_softc *sc = ifp->if_softc; 3185 3186 mii_pollstat(&sc->sc_mii); 3187 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3188 ifmr->ifm_active = sc->sc_mii.mii_media_active; 3189 } 3190 3191 /* 3192 * sip_mediachange: [ifmedia interface function] 3193 * 3194 * Set hardware to newly-selected media. 3195 */ 3196 int 3197 SIP_DECL(mediachange)(struct ifnet *ifp) 3198 { 3199 struct sip_softc *sc = ifp->if_softc; 3200 3201 if (ifp->if_flags & IFF_UP) 3202 mii_mediachg(&sc->sc_mii); 3203 return (0); 3204 } 3205
Indexes created Tue Sep 30 11:09:46 GMT 2025