if_sip.c revision 1.40.2.4
1 /* $NetBSD: if_sip.c,v 1.40.2.4 2002/06/23 17:47:41 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Support the 10-bit interface on the DP83820 (for fiber). 80 * 81 * - Reduce the interrupt load. 82 */ 83 84 #include <sys/cdefs.h> 85 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.40.2.4 2002/06/23 17:47:41 jdolecek Exp $"); 86 87 #include "bpfilter.h" 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/callout.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/ioctl.h> 97 #include <sys/errno.h> 98 #include <sys/device.h> 99 #include <sys/queue.h> 100 101 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 102 103 #include <net/if.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 #include <net/if_ether.h> 107 108 #if NBPFILTER > 0 109 #include <net/bpf.h> 110 #endif 111 112 #include <machine/bus.h> 113 #include <machine/intr.h> 114 #include <machine/endian.h> 115 116 #include <dev/mii/mii.h> 117 #include <dev/mii/miivar.h> 118 #ifdef DP83820 119 #include <dev/mii/mii_bitbang.h> 120 #endif /* DP83820 */ 121 122 #include <dev/pci/pcireg.h> 123 #include <dev/pci/pcivar.h> 124 #include <dev/pci/pcidevs.h> 125 126 #include <dev/pci/if_sipreg.h> 127 128 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 129 #define SIP_DECL(x) __CONCAT(gsip_,x) 130 #else /* SiS900 and DP83815 */ 131 #define SIP_DECL(x) __CONCAT(sip_,x) 132 #endif 133 134 #define SIP_STR(x) __STRING(SIP_DECL(x)) 135 136 /* 137 * Transmit descriptor list size. This is arbitrary, but allocate 138 * enough descriptors for 128 pending transmissions, and 8 segments 139 * per packet. This MUST work out to a power of 2. 140 */ 141 #define SIP_NTXSEGS 16 142 #define SIP_NTXSEGS_ALLOC 8 143 144 #define SIP_TXQUEUELEN 256 145 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 146 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 147 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 148 149 #if defined(DP83020) 150 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 151 #else 152 #define TX_DMAMAP_SIZE MCLBYTES 153 #endif 154 155 /* 156 * Receive descriptor list size. We have one Rx buffer per incoming 157 * packet, so this logic is a little simpler. 158 * 159 * Actually, on the DP83820, we allow the packet to consume more than 160 * one buffer, in order to support jumbo Ethernet frames. In that 161 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 162 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 163 * so we'd better be quick about handling receive interrupts. 164 */ 165 #if defined(DP83820) 166 #define SIP_NRXDESC 256 167 #else 168 #define SIP_NRXDESC 128 169 #endif /* DP83820 */ 170 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 171 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 172 173 /* 174 * Control structures are DMA'd to the SiS900 chip. We allocate them in 175 * a single clump that maps to a single DMA segment to make several things 176 * easier. 177 */ 178 struct sip_control_data { 179 /* 180 * The transmit descriptors. 181 */ 182 struct sip_desc scd_txdescs[SIP_NTXDESC]; 183 184 /* 185 * The receive descriptors. 186 */ 187 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 188 }; 189 190 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 191 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 192 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 193 194 /* 195 * Software state for transmit jobs. 196 */ 197 struct sip_txsoft { 198 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 199 bus_dmamap_t txs_dmamap; /* our DMA map */ 200 int txs_firstdesc; /* first descriptor in packet */ 201 int txs_lastdesc; /* last descriptor in packet */ 202 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 203 }; 204 205 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 206 207 /* 208 * Software state for receive jobs. 209 */ 210 struct sip_rxsoft { 211 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 212 bus_dmamap_t rxs_dmamap; /* our DMA map */ 213 }; 214 215 /* 216 * Software state per device. 217 */ 218 struct sip_softc { 219 struct device sc_dev; /* generic device information */ 220 bus_space_tag_t sc_st; /* bus space tag */ 221 bus_space_handle_t sc_sh; /* bus space handle */ 222 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 223 struct ethercom sc_ethercom; /* ethernet common data */ 224 void *sc_sdhook; /* shutdown hook */ 225 226 const struct sip_product *sc_model; /* which model are we? */ 227 int sc_rev; /* chip revision */ 228 229 void *sc_ih; /* interrupt cookie */ 230 231 struct mii_data sc_mii; /* MII/media information */ 232 233 struct callout sc_tick_ch; /* tick callout */ 234 235 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 236 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 237 238 /* 239 * Software state for transmit and receive descriptors. 240 */ 241 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 242 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 243 244 /* 245 * Control data structures. 246 */ 247 struct sip_control_data *sc_control_data; 248 #define sc_txdescs sc_control_data->scd_txdescs 249 #define sc_rxdescs sc_control_data->scd_rxdescs 250 251 #ifdef SIP_EVENT_COUNTERS 252 /* 253 * Event counters. 254 */ 255 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 256 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 257 struct evcnt sc_ev_txintr; /* Tx interrupts */ 258 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 259 #ifdef DP83820 260 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 261 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 262 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 263 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 264 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 265 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 266 #endif /* DP83820 */ 267 #endif /* SIP_EVENT_COUNTERS */ 268 269 u_int32_t sc_txcfg; /* prototype TXCFG register */ 270 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 271 u_int32_t sc_imr; /* prototype IMR register */ 272 u_int32_t sc_rfcr; /* prototype RFCR register */ 273 274 u_int32_t sc_cfg; /* prototype CFG register */ 275 276 #ifdef DP83820 277 u_int32_t sc_gpior; /* prototype GPIOR register */ 278 #endif /* DP83820 */ 279 280 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 281 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 282 283 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 284 285 int sc_flags; /* misc. flags; see below */ 286 287 int sc_txfree; /* number of free Tx descriptors */ 288 int sc_txnext; /* next ready Tx descriptor */ 289 290 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 291 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 292 293 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 294 #if defined(DP83820) 295 int sc_rxdiscard; 296 int sc_rxlen; 297 struct mbuf *sc_rxhead; 298 struct mbuf *sc_rxtail; 299 struct mbuf **sc_rxtailp; 300 #endif /* DP83820 */ 301 }; 302 303 /* sc_flags */ 304 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 305 306 #ifdef DP83820 307 #define SIP_RXCHAIN_RESET(sc) \ 308 do { \ 309 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 310 *(sc)->sc_rxtailp = NULL; \ 311 (sc)->sc_rxlen = 0; \ 312 } while (/*CONSTCOND*/0) 313 314 #define SIP_RXCHAIN_LINK(sc, m) \ 315 do { \ 316 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 317 (sc)->sc_rxtailp = &(m)->m_next; \ 318 } while (/*CONSTCOND*/0) 319 #endif /* DP83820 */ 320 321 #ifdef SIP_EVENT_COUNTERS 322 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 323 #else 324 #define SIP_EVCNT_INCR(ev) /* nothing */ 325 #endif 326 327 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 328 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 329 330 #define SIP_CDTXSYNC(sc, x, n, ops) \ 331 do { \ 332 int __x, __n; \ 333 \ 334 __x = (x); \ 335 __n = (n); \ 336 \ 337 /* If it will wrap around, sync to the end of the ring. */ \ 338 if ((__x + __n) > SIP_NTXDESC) { \ 339 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 340 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 341 (SIP_NTXDESC - __x), (ops)); \ 342 __n -= (SIP_NTXDESC - __x); \ 343 __x = 0; \ 344 } \ 345 \ 346 /* Now sync whatever is left. */ \ 347 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 348 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 349 } while (0) 350 351 #define SIP_CDRXSYNC(sc, x, ops) \ 352 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 353 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 354 355 #ifdef DP83820 356 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 357 #define SIP_RXBUF_LEN (MCLBYTES - 4) 358 #else 359 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 360 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 361 #endif 362 #define SIP_INIT_RXDESC(sc, x) \ 363 do { \ 364 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 365 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 366 \ 367 __sipd->sipd_link = \ 368 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 369 __sipd->sipd_bufptr = \ 370 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 371 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 372 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 373 SIP_INIT_RXDESC_EXTSTS \ 374 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 375 } while (0) 376 377 #define SIP_CHIP_VERS(sc, v, p, r) \ 378 ((sc)->sc_model->sip_vendor == (v) && \ 379 (sc)->sc_model->sip_product == (p) && \ 380 (sc)->sc_rev == (r)) 381 382 #define SIP_CHIP_MODEL(sc, v, p) \ 383 ((sc)->sc_model->sip_vendor == (v) && \ 384 (sc)->sc_model->sip_product == (p)) 385 386 #if !defined(DP83820) 387 #define SIP_SIS900_REV(sc, rev) \ 388 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 389 #endif 390 391 #define SIP_TIMEOUT 1000 392 393 void SIP_DECL(start)(struct ifnet *); 394 void SIP_DECL(watchdog)(struct ifnet *); 395 int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 396 int SIP_DECL(init)(struct ifnet *); 397 void SIP_DECL(stop)(struct ifnet *, int); 398 399 void SIP_DECL(shutdown)(void *); 400 401 void SIP_DECL(reset)(struct sip_softc *); 402 void SIP_DECL(rxdrain)(struct sip_softc *); 403 int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 404 void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, u_int16_t *); 405 void SIP_DECL(tick)(void *); 406 407 #if !defined(DP83820) 408 void SIP_DECL(sis900_set_filter)(struct sip_softc *); 409 #endif /* ! DP83820 */ 410 void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 411 412 #if defined(DP83820) 413 void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 414 const struct pci_attach_args *, u_int8_t *); 415 #else 416 void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 417 const struct pci_attach_args *, u_int8_t *); 418 void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 419 const struct pci_attach_args *, u_int8_t *); 420 #endif /* DP83820 */ 421 422 int SIP_DECL(intr)(void *); 423 void SIP_DECL(txintr)(struct sip_softc *); 424 void SIP_DECL(rxintr)(struct sip_softc *); 425 426 #if defined(DP83820) 427 int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 428 void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 429 void SIP_DECL(dp83820_mii_statchg)(struct device *); 430 #else 431 int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 432 void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 433 void SIP_DECL(sis900_mii_statchg)(struct device *); 434 435 int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 436 void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 437 void SIP_DECL(dp83815_mii_statchg)(struct device *); 438 #endif /* DP83820 */ 439 440 int SIP_DECL(mediachange)(struct ifnet *); 441 void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 442 443 int SIP_DECL(match)(struct device *, struct cfdata *, void *); 444 void SIP_DECL(attach)(struct device *, struct device *, void *); 445 446 int SIP_DECL(copy_small) = 0; 447 448 struct cfattach SIP_DECL(ca) = { 449 sizeof(struct sip_softc), SIP_DECL(match), SIP_DECL(attach), 450 }; 451 452 /* 453 * Descriptions of the variants of the SiS900. 454 */ 455 struct sip_variant { 456 int (*sipv_mii_readreg)(struct device *, int, int); 457 void (*sipv_mii_writereg)(struct device *, int, int, int); 458 void (*sipv_mii_statchg)(struct device *); 459 void (*sipv_set_filter)(struct sip_softc *); 460 void (*sipv_read_macaddr)(struct sip_softc *, 461 const struct pci_attach_args *, u_int8_t *); 462 }; 463 464 #if defined(DP83820) 465 u_int32_t SIP_DECL(dp83820_mii_bitbang_read)(struct device *); 466 void SIP_DECL(dp83820_mii_bitbang_write)(struct device *, u_int32_t); 467 468 const struct mii_bitbang_ops SIP_DECL(dp83820_mii_bitbang_ops) = { 469 SIP_DECL(dp83820_mii_bitbang_read), 470 SIP_DECL(dp83820_mii_bitbang_write), 471 { 472 EROMAR_MDIO, /* MII_BIT_MDO */ 473 EROMAR_MDIO, /* MII_BIT_MDI */ 474 EROMAR_MDC, /* MII_BIT_MDC */ 475 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 476 0, /* MII_BIT_DIR_PHY_HOST */ 477 } 478 }; 479 #endif /* DP83820 */ 480 481 #if defined(DP83820) 482 const struct sip_variant SIP_DECL(variant_dp83820) = { 483 SIP_DECL(dp83820_mii_readreg), 484 SIP_DECL(dp83820_mii_writereg), 485 SIP_DECL(dp83820_mii_statchg), 486 SIP_DECL(dp83815_set_filter), 487 SIP_DECL(dp83820_read_macaddr), 488 }; 489 #else 490 const struct sip_variant SIP_DECL(variant_sis900) = { 491 SIP_DECL(sis900_mii_readreg), 492 SIP_DECL(sis900_mii_writereg), 493 SIP_DECL(sis900_mii_statchg), 494 SIP_DECL(sis900_set_filter), 495 SIP_DECL(sis900_read_macaddr), 496 }; 497 498 const struct sip_variant SIP_DECL(variant_dp83815) = { 499 SIP_DECL(dp83815_mii_readreg), 500 SIP_DECL(dp83815_mii_writereg), 501 SIP_DECL(dp83815_mii_statchg), 502 SIP_DECL(dp83815_set_filter), 503 SIP_DECL(dp83815_read_macaddr), 504 }; 505 #endif /* DP83820 */ 506 507 /* 508 * Devices supported by this driver. 509 */ 510 const struct sip_product { 511 pci_vendor_id_t sip_vendor; 512 pci_product_id_t sip_product; 513 const char *sip_name; 514 const struct sip_variant *sip_variant; 515 } SIP_DECL(products)[] = { 516 #if defined(DP83820) 517 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 518 "NatSemi DP83820 Gigabit Ethernet", 519 &SIP_DECL(variant_dp83820) }, 520 #else 521 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 522 "SiS 900 10/100 Ethernet", 523 &SIP_DECL(variant_sis900) }, 524 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 525 "SiS 7016 10/100 Ethernet", 526 &SIP_DECL(variant_sis900) }, 527 528 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 529 "NatSemi DP83815 10/100 Ethernet", 530 &SIP_DECL(variant_dp83815) }, 531 #endif /* DP83820 */ 532 533 { 0, 0, 534 NULL, 535 NULL }, 536 }; 537 538 static const struct sip_product * 539 SIP_DECL(lookup)(const struct pci_attach_args *pa) 540 { 541 const struct sip_product *sip; 542 543 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 544 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 545 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 546 return (sip); 547 } 548 return (NULL); 549 } 550 551 int 552 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 553 { 554 struct pci_attach_args *pa = aux; 555 556 if (SIP_DECL(lookup)(pa) != NULL) 557 return (1); 558 559 return (0); 560 } 561 562 void 563 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 564 { 565 struct sip_softc *sc = (struct sip_softc *) self; 566 struct pci_attach_args *pa = aux; 567 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 568 pci_chipset_tag_t pc = pa->pa_pc; 569 pci_intr_handle_t ih; 570 const char *intrstr = NULL; 571 bus_space_tag_t iot, memt; 572 bus_space_handle_t ioh, memh; 573 bus_dma_segment_t seg; 574 int ioh_valid, memh_valid; 575 int i, rseg, error; 576 const struct sip_product *sip; 577 pcireg_t pmode; 578 u_int8_t enaddr[ETHER_ADDR_LEN]; 579 int pmreg; 580 #ifdef DP83820 581 pcireg_t memtype; 582 u_int32_t reg; 583 #endif /* DP83820 */ 584 585 callout_init(&sc->sc_tick_ch); 586 587 sip = SIP_DECL(lookup)(pa); 588 if (sip == NULL) { 589 printf("\n"); 590 panic(SIP_STR(attach) ": impossible"); 591 } 592 sc->sc_rev = PCI_REVISION(pa->pa_class); 593 594 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 595 596 sc->sc_model = sip; 597 598 /* 599 * XXX Work-around broken PXE firmware on some boards. 600 * 601 * The DP83815 shares an address decoder with the MEM BAR 602 * and the ROM BAR. Make sure the ROM BAR is disabled, 603 * so that memory mapped access works. 604 */ 605 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 606 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 607 ~PCI_MAPREG_ROM_ENABLE); 608 609 /* 610 * Map the device. 611 */ 612 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 613 PCI_MAPREG_TYPE_IO, 0, 614 &iot, &ioh, NULL, NULL) == 0); 615 #ifdef DP83820 616 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 617 switch (memtype) { 618 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 619 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 620 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 621 memtype, 0, &memt, &memh, NULL, NULL) == 0); 622 break; 623 default: 624 memh_valid = 0; 625 } 626 #else 627 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 628 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 629 &memt, &memh, NULL, NULL) == 0); 630 #endif /* DP83820 */ 631 632 if (memh_valid) { 633 printf("%s: using memory mapped registers\n", sc->sc_dev.dv_xname); 634 sc->sc_st = memt; 635 sc->sc_sh = memh; 636 } else if (ioh_valid) { 637 printf("%s: using I/O mapped registers\n", sc->sc_dev.dv_xname); 638 sc->sc_st = iot; 639 sc->sc_sh = ioh; 640 } else { 641 printf("%s: unable to map device registers\n", 642 sc->sc_dev.dv_xname); 643 return; 644 } 645 646 sc->sc_dmat = pa->pa_dmat; 647 648 /* 649 * Make sure bus mastering is enabled. Also make sure 650 * Write/Invalidate is enabled if we're allowed to use it. 651 */ 652 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 653 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 654 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 655 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 656 pmreg | PCI_COMMAND_MASTER_ENABLE); 657 658 /* Get it out of power save mode if needed. */ 659 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 660 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 661 if (pmode == 3) { 662 /* 663 * The card has lost all configuration data in 664 * this state, so punt. 665 */ 666 printf("%s: unable to wake up from power state D3\n", 667 sc->sc_dev.dv_xname); 668 return; 669 } 670 if (pmode != 0) { 671 printf("%s: waking up from power state D%d\n", 672 sc->sc_dev.dv_xname, pmode); 673 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 674 } 675 } 676 677 /* 678 * Map and establish our interrupt. 679 */ 680 if (pci_intr_map(pa, &ih)) { 681 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 682 return; 683 } 684 intrstr = pci_intr_string(pc, ih); 685 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 686 if (sc->sc_ih == NULL) { 687 printf("%s: unable to establish interrupt", 688 sc->sc_dev.dv_xname); 689 if (intrstr != NULL) 690 printf(" at %s", intrstr); 691 printf("\n"); 692 return; 693 } 694 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 695 696 SIMPLEQ_INIT(&sc->sc_txfreeq); 697 SIMPLEQ_INIT(&sc->sc_txdirtyq); 698 699 /* 700 * Allocate the control data structures, and create and load the 701 * DMA map for it. 702 */ 703 if ((error = bus_dmamem_alloc(sc->sc_dmat, 704 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 705 0)) != 0) { 706 printf("%s: unable to allocate control data, error = %d\n", 707 sc->sc_dev.dv_xname, error); 708 goto fail_0; 709 } 710 711 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 712 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 713 BUS_DMA_COHERENT)) != 0) { 714 printf("%s: unable to map control data, error = %d\n", 715 sc->sc_dev.dv_xname, error); 716 goto fail_1; 717 } 718 719 if ((error = bus_dmamap_create(sc->sc_dmat, 720 sizeof(struct sip_control_data), 1, 721 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 722 printf("%s: unable to create control data DMA map, " 723 "error = %d\n", sc->sc_dev.dv_xname, error); 724 goto fail_2; 725 } 726 727 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 728 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 729 0)) != 0) { 730 printf("%s: unable to load control data DMA map, error = %d\n", 731 sc->sc_dev.dv_xname, error); 732 goto fail_3; 733 } 734 735 /* 736 * Create the transmit buffer DMA maps. 737 */ 738 for (i = 0; i < SIP_TXQUEUELEN; i++) { 739 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 740 SIP_NTXSEGS, MCLBYTES, 0, 0, 741 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 742 printf("%s: unable to create tx DMA map %d, " 743 "error = %d\n", sc->sc_dev.dv_xname, i, error); 744 goto fail_4; 745 } 746 } 747 748 /* 749 * Create the receive buffer DMA maps. 750 */ 751 for (i = 0; i < SIP_NRXDESC; i++) { 752 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 753 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 754 printf("%s: unable to create rx DMA map %d, " 755 "error = %d\n", sc->sc_dev.dv_xname, i, error); 756 goto fail_5; 757 } 758 sc->sc_rxsoft[i].rxs_mbuf = NULL; 759 } 760 761 /* 762 * Reset the chip to a known state. 763 */ 764 SIP_DECL(reset)(sc); 765 766 /* 767 * Read the Ethernet address from the EEPROM. This might 768 * also fetch other stuff from the EEPROM and stash it 769 * in the softc. 770 */ 771 sc->sc_cfg = 0; 772 #if !defined(DP83820) 773 if (SIP_SIS900_REV(sc,SIS_REV_635) || 774 SIP_SIS900_REV(sc,SIS_REV_900B)) 775 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 776 #endif 777 778 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 779 780 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 781 ether_sprintf(enaddr)); 782 783 /* 784 * Initialize the configuration register: aggressive PCI 785 * bus request algorithm, default backoff, default OW timer, 786 * default parity error detection. 787 * 788 * NOTE: "Big endian mode" is useless on the SiS900 and 789 * friends -- it affects packet data, not descriptors. 790 */ 791 #ifdef DP83820 792 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 793 if (reg & CFG_PCI64_DET) { 794 printf("%s: 64-bit PCI slot detected\n", sc->sc_dev.dv_xname); 795 /* 796 * XXX Need some PCI flags indicating support for 797 * XXX 64-bit addressing (SAC or DAC) and 64-bit 798 * XXX data path. 799 */ 800 } 801 if (sc->sc_cfg & (CFG_TBI_EN|CFG_EXT_125)) { 802 const char *sep = ""; 803 printf("%s: using ", sc->sc_dev.dv_xname); 804 if (sc->sc_cfg & CFG_EXT_125) { 805 printf("%s125MHz clock", sep); 806 sep = ", "; 807 } 808 if (sc->sc_cfg & CFG_TBI_EN) { 809 printf("%sten-bit interface", sep); 810 sep = ", "; 811 } 812 printf("\n"); 813 } 814 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0) 815 sc->sc_cfg |= CFG_MRM_DIS; 816 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 817 sc->sc_cfg |= CFG_MWI_DIS; 818 819 /* 820 * Use the extended descriptor format on the DP83820. This 821 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 822 * checksumming. 823 */ 824 sc->sc_cfg |= CFG_EXTSTS_EN; 825 #endif /* DP83820 */ 826 827 /* 828 * Initialize our media structures and probe the MII. 829 */ 830 sc->sc_mii.mii_ifp = ifp; 831 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 832 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 833 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 834 ifmedia_init(&sc->sc_mii.mii_media, 0, SIP_DECL(mediachange), 835 SIP_DECL(mediastatus)); 836 #ifdef DP83820 837 if (sc->sc_cfg & CFG_TBI_EN) { 838 /* Using ten-bit interface. */ 839 printf("%s: TBI -- FIXME\n", sc->sc_dev.dv_xname); 840 } else { 841 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 842 MII_OFFSET_ANY, 0); 843 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 844 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 845 0, NULL); 846 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 847 } else 848 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 849 } 850 #else 851 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 852 MII_OFFSET_ANY, 0); 853 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 854 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 855 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 856 } else 857 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 858 #endif /* DP83820 */ 859 860 ifp = &sc->sc_ethercom.ec_if; 861 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 862 ifp->if_softc = sc; 863 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 864 ifp->if_ioctl = SIP_DECL(ioctl); 865 ifp->if_start = SIP_DECL(start); 866 ifp->if_watchdog = SIP_DECL(watchdog); 867 ifp->if_init = SIP_DECL(init); 868 ifp->if_stop = SIP_DECL(stop); 869 IFQ_SET_READY(&ifp->if_snd); 870 871 /* 872 * We can support 802.1Q VLAN-sized frames. 873 */ 874 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 875 876 #ifdef DP83820 877 /* 878 * And the DP83820 can do VLAN tagging in hardware, and 879 * support the jumbo Ethernet MTU. 880 */ 881 sc->sc_ethercom.ec_capabilities |= 882 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 883 884 /* 885 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 886 * in hardware. 887 */ 888 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 889 IFCAP_CSUM_UDPv4; 890 #endif /* DP83820 */ 891 892 /* 893 * Attach the interface. 894 */ 895 if_attach(ifp); 896 ether_ifattach(ifp, enaddr); 897 898 /* 899 * The number of bytes that must be available in 900 * the Tx FIFO before the bus master can DMA more 901 * data into the FIFO. 902 */ 903 sc->sc_tx_fill_thresh = 64 / 32; 904 905 /* 906 * Start at a drain threshold of 512 bytes. We will 907 * increase it if a DMA underrun occurs. 908 * 909 * XXX The minimum value of this variable should be 910 * tuned. We may be able to improve performance 911 * by starting with a lower value. That, however, 912 * may trash the first few outgoing packets if the 913 * PCI bus is saturated. 914 */ 915 sc->sc_tx_drain_thresh = 1504 / 32; 916 917 /* 918 * Initialize the Rx FIFO drain threshold. 919 * 920 * This is in units of 8 bytes. 921 * 922 * We should never set this value lower than 2; 14 bytes are 923 * required to filter the packet. 924 */ 925 sc->sc_rx_drain_thresh = 128 / 8; 926 927 #ifdef SIP_EVENT_COUNTERS 928 /* 929 * Attach event counters. 930 */ 931 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 932 NULL, sc->sc_dev.dv_xname, "txsstall"); 933 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 934 NULL, sc->sc_dev.dv_xname, "txdstall"); 935 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 936 NULL, sc->sc_dev.dv_xname, "txintr"); 937 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 938 NULL, sc->sc_dev.dv_xname, "rxintr"); 939 #ifdef DP83820 940 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 941 NULL, sc->sc_dev.dv_xname, "rxipsum"); 942 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 943 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 944 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 945 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 946 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 947 NULL, sc->sc_dev.dv_xname, "txipsum"); 948 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 949 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 950 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 951 NULL, sc->sc_dev.dv_xname, "txudpsum"); 952 #endif /* DP83820 */ 953 #endif /* SIP_EVENT_COUNTERS */ 954 955 /* 956 * Make sure the interface is shutdown during reboot. 957 */ 958 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 959 if (sc->sc_sdhook == NULL) 960 printf("%s: WARNING: unable to establish shutdown hook\n", 961 sc->sc_dev.dv_xname); 962 return; 963 964 /* 965 * Free any resources we've allocated during the failed attach 966 * attempt. Do this in reverse order and fall through. 967 */ 968 fail_5: 969 for (i = 0; i < SIP_NRXDESC; i++) { 970 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 971 bus_dmamap_destroy(sc->sc_dmat, 972 sc->sc_rxsoft[i].rxs_dmamap); 973 } 974 fail_4: 975 for (i = 0; i < SIP_TXQUEUELEN; i++) { 976 if (sc->sc_txsoft[i].txs_dmamap != NULL) 977 bus_dmamap_destroy(sc->sc_dmat, 978 sc->sc_txsoft[i].txs_dmamap); 979 } 980 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 981 fail_3: 982 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 983 fail_2: 984 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 985 sizeof(struct sip_control_data)); 986 fail_1: 987 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 988 fail_0: 989 return; 990 } 991 992 /* 993 * sip_shutdown: 994 * 995 * Make sure the interface is stopped at reboot time. 996 */ 997 void 998 SIP_DECL(shutdown)(void *arg) 999 { 1000 struct sip_softc *sc = arg; 1001 1002 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1003 } 1004 1005 /* 1006 * sip_start: [ifnet interface function] 1007 * 1008 * Start packet transmission on the interface. 1009 */ 1010 void 1011 SIP_DECL(start)(struct ifnet *ifp) 1012 { 1013 struct sip_softc *sc = ifp->if_softc; 1014 struct mbuf *m0, *m; 1015 struct sip_txsoft *txs; 1016 bus_dmamap_t dmamap; 1017 int error, firsttx, nexttx, lasttx, ofree, seg; 1018 #ifdef DP83820 1019 u_int32_t extsts; 1020 #endif 1021 1022 /* 1023 * If we've been told to pause, don't transmit any more packets. 1024 */ 1025 if (sc->sc_flags & SIPF_PAUSED) 1026 ifp->if_flags |= IFF_OACTIVE; 1027 1028 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1029 return; 1030 1031 /* 1032 * Remember the previous number of free descriptors and 1033 * the first descriptor we'll use. 1034 */ 1035 ofree = sc->sc_txfree; 1036 firsttx = sc->sc_txnext; 1037 1038 /* 1039 * Loop through the send queue, setting up transmit descriptors 1040 * until we drain the queue, or use up all available transmit 1041 * descriptors. 1042 */ 1043 for (;;) { 1044 /* Get a work queue entry. */ 1045 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1046 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1047 break; 1048 } 1049 1050 /* 1051 * Grab a packet off the queue. 1052 */ 1053 IFQ_POLL(&ifp->if_snd, m0); 1054 if (m0 == NULL) 1055 break; 1056 #ifndef DP83820 1057 m = NULL; 1058 #endif 1059 1060 dmamap = txs->txs_dmamap; 1061 1062 #ifdef DP83820 1063 /* 1064 * Load the DMA map. If this fails, the packet either 1065 * didn't fit in the allotted number of segments, or we 1066 * were short on resources. For the too-many-segments 1067 * case, we simply report an error and drop the packet, 1068 * since we can't sanely copy a jumbo packet to a single 1069 * buffer. 1070 */ 1071 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1072 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1073 if (error) { 1074 if (error == EFBIG) { 1075 printf("%s: Tx packet consumes too many " 1076 "DMA segments, dropping...\n", 1077 sc->sc_dev.dv_xname); 1078 IFQ_DEQUEUE(&ifp->if_snd, m0); 1079 m_freem(m0); 1080 continue; 1081 } 1082 /* 1083 * Short on resources, just stop for now. 1084 */ 1085 break; 1086 } 1087 #else /* DP83820 */ 1088 /* 1089 * Load the DMA map. If this fails, the packet either 1090 * didn't fit in the alloted number of segments, or we 1091 * were short on resources. In this case, we'll copy 1092 * and try again. 1093 */ 1094 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1095 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1096 MGETHDR(m, M_DONTWAIT, MT_DATA); 1097 if (m == NULL) { 1098 printf("%s: unable to allocate Tx mbuf\n", 1099 sc->sc_dev.dv_xname); 1100 break; 1101 } 1102 if (m0->m_pkthdr.len > MHLEN) { 1103 MCLGET(m, M_DONTWAIT); 1104 if ((m->m_flags & M_EXT) == 0) { 1105 printf("%s: unable to allocate Tx " 1106 "cluster\n", sc->sc_dev.dv_xname); 1107 m_freem(m); 1108 break; 1109 } 1110 } 1111 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1112 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1113 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1114 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1115 if (error) { 1116 printf("%s: unable to load Tx buffer, " 1117 "error = %d\n", sc->sc_dev.dv_xname, error); 1118 break; 1119 } 1120 } 1121 #endif /* DP83820 */ 1122 1123 /* 1124 * Ensure we have enough descriptors free to describe 1125 * the packet. Note, we always reserve one descriptor 1126 * at the end of the ring as a termination point, to 1127 * prevent wrap-around. 1128 */ 1129 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1130 /* 1131 * Not enough free descriptors to transmit this 1132 * packet. We haven't committed anything yet, 1133 * so just unload the DMA map, put the packet 1134 * back on the queue, and punt. Notify the upper 1135 * layer that there are not more slots left. 1136 * 1137 * XXX We could allocate an mbuf and copy, but 1138 * XXX is it worth it? 1139 */ 1140 ifp->if_flags |= IFF_OACTIVE; 1141 bus_dmamap_unload(sc->sc_dmat, dmamap); 1142 #ifndef DP83820 1143 if (m != NULL) 1144 m_freem(m); 1145 #endif 1146 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1147 break; 1148 } 1149 1150 IFQ_DEQUEUE(&ifp->if_snd, m0); 1151 #ifndef DP83820 1152 if (m != NULL) { 1153 m_freem(m0); 1154 m0 = m; 1155 } 1156 #endif 1157 1158 /* 1159 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1160 */ 1161 1162 /* Sync the DMA map. */ 1163 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1164 BUS_DMASYNC_PREWRITE); 1165 1166 /* 1167 * Initialize the transmit descriptors. 1168 */ 1169 for (nexttx = sc->sc_txnext, seg = 0; 1170 seg < dmamap->dm_nsegs; 1171 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1172 /* 1173 * If this is the first descriptor we're 1174 * enqueueing, don't set the OWN bit just 1175 * yet. That could cause a race condition. 1176 * We'll do it below. 1177 */ 1178 sc->sc_txdescs[nexttx].sipd_bufptr = 1179 htole32(dmamap->dm_segs[seg].ds_addr); 1180 sc->sc_txdescs[nexttx].sipd_cmdsts = 1181 htole32((nexttx == firsttx ? 0 : CMDSTS_OWN) | 1182 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1183 #ifdef DP83820 1184 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1185 #endif /* DP83820 */ 1186 lasttx = nexttx; 1187 } 1188 1189 /* Clear the MORE bit on the last segment. */ 1190 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1191 1192 #ifdef DP83820 1193 /* 1194 * If VLANs are enabled and the packet has a VLAN tag, set 1195 * up the descriptor to encapsulate the packet for us. 1196 * 1197 * This apparently has to be on the last descriptor of 1198 * the packet. 1199 */ 1200 if (sc->sc_ethercom.ec_nvlans != 0 && 1201 (m = m_aux_find(m0, AF_LINK, ETHERTYPE_VLAN)) != NULL) { 1202 sc->sc_txdescs[lasttx].sipd_extsts |= 1203 htole32(EXTSTS_VPKT | 1204 htons(*mtod(m, int *) & EXTSTS_VTCI)); 1205 } 1206 1207 /* 1208 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1209 * checksumming, set up the descriptor to do this work 1210 * for us. 1211 * 1212 * This apparently has to be on the first descriptor of 1213 * the packet. 1214 * 1215 * Byte-swap constants so the compiler can optimize. 1216 */ 1217 extsts = 0; 1218 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1219 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1220 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1221 extsts |= htole32(EXTSTS_IPPKT); 1222 } 1223 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1224 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1225 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1226 extsts |= htole32(EXTSTS_TCPPKT); 1227 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1228 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1229 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1230 extsts |= htole32(EXTSTS_UDPPKT); 1231 } 1232 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1233 #endif /* DP83820 */ 1234 1235 /* Sync the descriptors we're using. */ 1236 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1237 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1238 1239 /* 1240 * Store a pointer to the packet so we can free it later, 1241 * and remember what txdirty will be once the packet is 1242 * done. 1243 */ 1244 txs->txs_mbuf = m0; 1245 txs->txs_firstdesc = sc->sc_txnext; 1246 txs->txs_lastdesc = lasttx; 1247 1248 /* Advance the tx pointer. */ 1249 sc->sc_txfree -= dmamap->dm_nsegs; 1250 sc->sc_txnext = nexttx; 1251 1252 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1253 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1254 1255 #if NBPFILTER > 0 1256 /* 1257 * Pass the packet to any BPF listeners. 1258 */ 1259 if (ifp->if_bpf) 1260 bpf_mtap(ifp->if_bpf, m0); 1261 #endif /* NBPFILTER > 0 */ 1262 } 1263 1264 if (txs == NULL || sc->sc_txfree == 0) { 1265 /* No more slots left; notify upper layer. */ 1266 ifp->if_flags |= IFF_OACTIVE; 1267 } 1268 1269 if (sc->sc_txfree != ofree) { 1270 /* 1271 * Cause a descriptor interrupt to happen on the 1272 * last packet we enqueued. 1273 */ 1274 sc->sc_txdescs[lasttx].sipd_cmdsts |= htole32(CMDSTS_INTR); 1275 SIP_CDTXSYNC(sc, lasttx, 1, 1276 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1277 1278 /* 1279 * The entire packet chain is set up. Give the 1280 * first descrptor to the chip now. 1281 */ 1282 sc->sc_txdescs[firsttx].sipd_cmdsts |= htole32(CMDSTS_OWN); 1283 SIP_CDTXSYNC(sc, firsttx, 1, 1284 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1285 1286 /* 1287 * Start the transmit process. Note, the manual says 1288 * that if there are no pending transmissions in the 1289 * chip's internal queue (indicated by TXE being clear), 1290 * then the driver software must set the TXDP to the 1291 * first descriptor to be transmitted. However, if we 1292 * do this, it causes serious performance degredation on 1293 * the DP83820 under load, not setting TXDP doesn't seem 1294 * to adversely affect the SiS 900 or DP83815. 1295 * 1296 * Well, I guess it wouldn't be the first time a manual 1297 * has lied -- and they could be speaking of the NULL- 1298 * terminated descriptor list case, rather than OWN- 1299 * terminated rings. 1300 */ 1301 #if 0 1302 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1303 CR_TXE) == 0) { 1304 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1305 SIP_CDTXADDR(sc, firsttx)); 1306 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1307 } 1308 #else 1309 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1310 #endif 1311 1312 /* Set a watchdog timer in case the chip flakes out. */ 1313 ifp->if_timer = 5; 1314 } 1315 } 1316 1317 /* 1318 * sip_watchdog: [ifnet interface function] 1319 * 1320 * Watchdog timer handler. 1321 */ 1322 void 1323 SIP_DECL(watchdog)(struct ifnet *ifp) 1324 { 1325 struct sip_softc *sc = ifp->if_softc; 1326 1327 /* 1328 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1329 * If we get a timeout, try and sweep up transmit descriptors. 1330 * If we manage to sweep them all up, ignore the lack of 1331 * interrupt. 1332 */ 1333 SIP_DECL(txintr)(sc); 1334 1335 if (sc->sc_txfree != SIP_NTXDESC) { 1336 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1337 ifp->if_oerrors++; 1338 1339 /* Reset the interface. */ 1340 (void) SIP_DECL(init)(ifp); 1341 } else if (ifp->if_flags & IFF_DEBUG) 1342 printf("%s: recovered from device timeout\n", 1343 sc->sc_dev.dv_xname); 1344 1345 /* Try to get more packets going. */ 1346 SIP_DECL(start)(ifp); 1347 } 1348 1349 /* 1350 * sip_ioctl: [ifnet interface function] 1351 * 1352 * Handle control requests from the operator. 1353 */ 1354 int 1355 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1356 { 1357 struct sip_softc *sc = ifp->if_softc; 1358 struct ifreq *ifr = (struct ifreq *)data; 1359 int s, error; 1360 1361 s = splnet(); 1362 1363 switch (cmd) { 1364 case SIOCSIFMEDIA: 1365 case SIOCGIFMEDIA: 1366 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1367 break; 1368 1369 default: 1370 error = ether_ioctl(ifp, cmd, data); 1371 if (error == ENETRESET) { 1372 /* 1373 * Multicast list has changed; set the hardware filter 1374 * accordingly. 1375 */ 1376 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1377 error = 0; 1378 } 1379 break; 1380 } 1381 1382 /* Try to get more packets going. */ 1383 SIP_DECL(start)(ifp); 1384 1385 splx(s); 1386 return (error); 1387 } 1388 1389 /* 1390 * sip_intr: 1391 * 1392 * Interrupt service routine. 1393 */ 1394 int 1395 SIP_DECL(intr)(void *arg) 1396 { 1397 struct sip_softc *sc = arg; 1398 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1399 u_int32_t isr; 1400 int handled = 0; 1401 1402 for (;;) { 1403 /* Reading clears interrupt. */ 1404 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1405 if ((isr & sc->sc_imr) == 0) 1406 break; 1407 1408 handled = 1; 1409 1410 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1411 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1412 1413 /* Grab any new packets. */ 1414 SIP_DECL(rxintr)(sc); 1415 1416 if (isr & ISR_RXORN) { 1417 printf("%s: receive FIFO overrun\n", 1418 sc->sc_dev.dv_xname); 1419 1420 /* XXX adjust rx_drain_thresh? */ 1421 } 1422 1423 if (isr & ISR_RXIDLE) { 1424 printf("%s: receive ring overrun\n", 1425 sc->sc_dev.dv_xname); 1426 1427 /* Get the receive process going again. */ 1428 bus_space_write_4(sc->sc_st, sc->sc_sh, 1429 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1430 bus_space_write_4(sc->sc_st, sc->sc_sh, 1431 SIP_CR, CR_RXE); 1432 } 1433 } 1434 1435 if (isr & (ISR_TXURN|ISR_TXDESC)) { 1436 SIP_EVCNT_INCR(&sc->sc_ev_txintr); 1437 1438 /* Sweep up transmit descriptors. */ 1439 SIP_DECL(txintr)(sc); 1440 1441 if (isr & ISR_TXURN) { 1442 u_int32_t thresh; 1443 1444 printf("%s: transmit FIFO underrun", 1445 sc->sc_dev.dv_xname); 1446 1447 thresh = sc->sc_tx_drain_thresh + 1; 1448 if (thresh <= TXCFG_DRTH && 1449 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1450 (sc->sc_tx_fill_thresh * 32))) { 1451 printf("; increasing Tx drain " 1452 "threshold to %u bytes\n", 1453 thresh * 32); 1454 sc->sc_tx_drain_thresh = thresh; 1455 (void) SIP_DECL(init)(ifp); 1456 } else { 1457 (void) SIP_DECL(init)(ifp); 1458 printf("\n"); 1459 } 1460 } 1461 } 1462 1463 #if !defined(DP83820) 1464 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1465 if (isr & ISR_PAUSE_ST) { 1466 sc->sc_flags |= SIPF_PAUSED; 1467 ifp->if_flags |= IFF_OACTIVE; 1468 } 1469 if (isr & ISR_PAUSE_END) { 1470 sc->sc_flags &= ~SIPF_PAUSED; 1471 ifp->if_flags &= ~IFF_OACTIVE; 1472 } 1473 } 1474 #endif /* ! DP83820 */ 1475 1476 if (isr & ISR_HIBERR) { 1477 #define PRINTERR(bit, str) \ 1478 if (isr & (bit)) \ 1479 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1480 PRINTERR(ISR_DPERR, "parity error"); 1481 PRINTERR(ISR_SSERR, "system error"); 1482 PRINTERR(ISR_RMABT, "master abort"); 1483 PRINTERR(ISR_RTABT, "target abort"); 1484 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1485 (void) SIP_DECL(init)(ifp); 1486 #undef PRINTERR 1487 } 1488 } 1489 1490 /* Try to get more packets going. */ 1491 SIP_DECL(start)(ifp); 1492 1493 return (handled); 1494 } 1495 1496 /* 1497 * sip_txintr: 1498 * 1499 * Helper; handle transmit interrupts. 1500 */ 1501 void 1502 SIP_DECL(txintr)(struct sip_softc *sc) 1503 { 1504 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1505 struct sip_txsoft *txs; 1506 u_int32_t cmdsts; 1507 1508 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1509 ifp->if_flags &= ~IFF_OACTIVE; 1510 1511 /* 1512 * Go through our Tx list and free mbufs for those 1513 * frames which have been transmitted. 1514 */ 1515 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1516 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1517 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1518 1519 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1520 if (cmdsts & CMDSTS_OWN) 1521 break; 1522 1523 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1524 1525 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1526 1527 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1528 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1529 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1530 m_freem(txs->txs_mbuf); 1531 txs->txs_mbuf = NULL; 1532 1533 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1534 1535 /* 1536 * Check for errors and collisions. 1537 */ 1538 if (cmdsts & 1539 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1540 ifp->if_oerrors++; 1541 if (cmdsts & CMDSTS_Tx_EC) 1542 ifp->if_collisions += 16; 1543 if (ifp->if_flags & IFF_DEBUG) { 1544 if (cmdsts & CMDSTS_Tx_ED) 1545 printf("%s: excessive deferral\n", 1546 sc->sc_dev.dv_xname); 1547 if (cmdsts & CMDSTS_Tx_EC) 1548 printf("%s: excessive collisions\n", 1549 sc->sc_dev.dv_xname); 1550 } 1551 } else { 1552 /* Packet was transmitted successfully. */ 1553 ifp->if_opackets++; 1554 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1555 } 1556 } 1557 1558 /* 1559 * If there are no more pending transmissions, cancel the watchdog 1560 * timer. 1561 */ 1562 if (txs == NULL) 1563 ifp->if_timer = 0; 1564 } 1565 1566 #if defined(DP83820) 1567 /* 1568 * sip_rxintr: 1569 * 1570 * Helper; handle receive interrupts. 1571 */ 1572 void 1573 SIP_DECL(rxintr)(struct sip_softc *sc) 1574 { 1575 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1576 struct sip_rxsoft *rxs; 1577 struct mbuf *m, *tailm; 1578 u_int32_t cmdsts, extsts; 1579 int i, len; 1580 1581 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1582 rxs = &sc->sc_rxsoft[i]; 1583 1584 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1585 1586 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1587 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1588 1589 /* 1590 * NOTE: OWN is set if owned by _consumer_. We're the 1591 * consumer of the receive ring, so if the bit is clear, 1592 * we have processed all of the packets. 1593 */ 1594 if ((cmdsts & CMDSTS_OWN) == 0) { 1595 /* 1596 * We have processed all of the receive buffers. 1597 */ 1598 break; 1599 } 1600 1601 if (__predict_false(sc->sc_rxdiscard)) { 1602 SIP_INIT_RXDESC(sc, i); 1603 if ((cmdsts & CMDSTS_MORE) == 0) { 1604 /* Reset our state. */ 1605 sc->sc_rxdiscard = 0; 1606 } 1607 continue; 1608 } 1609 1610 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1611 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1612 1613 m = rxs->rxs_mbuf; 1614 1615 /* 1616 * Add a new receive buffer to the ring. 1617 */ 1618 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1619 /* 1620 * Failed, throw away what we've done so 1621 * far, and discard the rest of the packet. 1622 */ 1623 ifp->if_ierrors++; 1624 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1625 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1626 SIP_INIT_RXDESC(sc, i); 1627 if (cmdsts & CMDSTS_MORE) 1628 sc->sc_rxdiscard = 1; 1629 if (sc->sc_rxhead != NULL) 1630 m_freem(sc->sc_rxhead); 1631 SIP_RXCHAIN_RESET(sc); 1632 continue; 1633 } 1634 1635 SIP_RXCHAIN_LINK(sc, m); 1636 1637 /* 1638 * If this is not the end of the packet, keep 1639 * looking. 1640 */ 1641 if (cmdsts & CMDSTS_MORE) { 1642 sc->sc_rxlen += m->m_len; 1643 continue; 1644 } 1645 1646 /* 1647 * Okay, we have the entire packet now... 1648 */ 1649 *sc->sc_rxtailp = NULL; 1650 m = sc->sc_rxhead; 1651 tailm = sc->sc_rxtail; 1652 1653 SIP_RXCHAIN_RESET(sc); 1654 1655 /* 1656 * If an error occurred, update stats and drop the packet. 1657 */ 1658 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1659 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1660 ifp->if_ierrors++; 1661 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1662 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1663 /* Receive overrun handled elsewhere. */ 1664 printf("%s: receive descriptor error\n", 1665 sc->sc_dev.dv_xname); 1666 } 1667 #define PRINTERR(bit, str) \ 1668 if (cmdsts & (bit)) \ 1669 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1670 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1671 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1672 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1673 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1674 #undef PRINTERR 1675 m_freem(m); 1676 continue; 1677 } 1678 1679 /* 1680 * No errors. 1681 * 1682 * Note, the DP83820 includes the CRC with 1683 * every packet. 1684 */ 1685 len = CMDSTS_SIZE(cmdsts); 1686 tailm->m_len = len - sc->sc_rxlen; 1687 1688 /* 1689 * If the packet is small enough to fit in a 1690 * single header mbuf, allocate one and copy 1691 * the data into it. This greatly reduces 1692 * memory consumption when we receive lots 1693 * of small packets. 1694 */ 1695 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1696 struct mbuf *nm; 1697 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1698 if (nm == NULL) { 1699 ifp->if_ierrors++; 1700 m_freem(m); 1701 continue; 1702 } 1703 nm->m_data += 2; 1704 nm->m_pkthdr.len = nm->m_len = len; 1705 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1706 m_freem(m); 1707 m = nm; 1708 } 1709 #ifndef __NO_STRICT_ALIGNMENT 1710 else { 1711 /* 1712 * The DP83820's receive buffers must be 4-byte 1713 * aligned. But this means that the data after 1714 * the Ethernet header is misaligned. To compensate, 1715 * we have artificially shortened the buffer size 1716 * in the descriptor, and we do an overlapping copy 1717 * of the data two bytes further in (in the first 1718 * buffer of the chain only). 1719 */ 1720 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1721 m->m_len); 1722 m->m_data += 2; 1723 } 1724 #endif /* ! __NO_STRICT_ALIGNMENT */ 1725 1726 /* 1727 * If VLANs are enabled, VLAN packets have been unwrapped 1728 * for us. Associate the tag with the packet. 1729 */ 1730 if (sc->sc_ethercom.ec_nvlans != 0 && 1731 (extsts & EXTSTS_VPKT) != 0) { 1732 struct mbuf *vtag; 1733 1734 vtag = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 1735 if (vtag == NULL) { 1736 ifp->if_ierrors++; 1737 printf("%s: unable to allocate VLAN tag\n", 1738 sc->sc_dev.dv_xname); 1739 m_freem(m); 1740 continue; 1741 } 1742 1743 *mtod(vtag, int *) = ntohs(extsts & EXTSTS_VTCI); 1744 vtag->m_len = sizeof(int); 1745 } 1746 1747 /* 1748 * Set the incoming checksum information for the 1749 * packet. 1750 */ 1751 if ((extsts & EXTSTS_IPPKT) != 0) { 1752 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1753 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1754 if (extsts & EXTSTS_Rx_IPERR) 1755 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1756 if (extsts & EXTSTS_TCPPKT) { 1757 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1758 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1759 if (extsts & EXTSTS_Rx_TCPERR) 1760 m->m_pkthdr.csum_flags |= 1761 M_CSUM_TCP_UDP_BAD; 1762 } else if (extsts & EXTSTS_UDPPKT) { 1763 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1764 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1765 if (extsts & EXTSTS_Rx_UDPERR) 1766 m->m_pkthdr.csum_flags |= 1767 M_CSUM_TCP_UDP_BAD; 1768 } 1769 } 1770 1771 ifp->if_ipackets++; 1772 m->m_flags |= M_HASFCS; 1773 m->m_pkthdr.rcvif = ifp; 1774 m->m_pkthdr.len = len; 1775 1776 #if NBPFILTER > 0 1777 /* 1778 * Pass this up to any BPF listeners, but only 1779 * pass if up the stack if it's for us. 1780 */ 1781 if (ifp->if_bpf) 1782 bpf_mtap(ifp->if_bpf, m); 1783 #endif /* NBPFILTER > 0 */ 1784 1785 /* Pass it on. */ 1786 (*ifp->if_input)(ifp, m); 1787 } 1788 1789 /* Update the receive pointer. */ 1790 sc->sc_rxptr = i; 1791 } 1792 #else /* ! DP83820 */ 1793 /* 1794 * sip_rxintr: 1795 * 1796 * Helper; handle receive interrupts. 1797 */ 1798 void 1799 SIP_DECL(rxintr)(struct sip_softc *sc) 1800 { 1801 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1802 struct sip_rxsoft *rxs; 1803 struct mbuf *m; 1804 u_int32_t cmdsts; 1805 int i, len; 1806 1807 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1808 rxs = &sc->sc_rxsoft[i]; 1809 1810 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1811 1812 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1813 1814 /* 1815 * NOTE: OWN is set if owned by _consumer_. We're the 1816 * consumer of the receive ring, so if the bit is clear, 1817 * we have processed all of the packets. 1818 */ 1819 if ((cmdsts & CMDSTS_OWN) == 0) { 1820 /* 1821 * We have processed all of the receive buffers. 1822 */ 1823 break; 1824 } 1825 1826 /* 1827 * If any collisions were seen on the wire, count one. 1828 */ 1829 if (cmdsts & CMDSTS_Rx_COL) 1830 ifp->if_collisions++; 1831 1832 /* 1833 * If an error occurred, update stats, clear the status 1834 * word, and leave the packet buffer in place. It will 1835 * simply be reused the next time the ring comes around. 1836 */ 1837 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1838 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1839 ifp->if_ierrors++; 1840 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1841 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1842 /* Receive overrun handled elsewhere. */ 1843 printf("%s: receive descriptor error\n", 1844 sc->sc_dev.dv_xname); 1845 } 1846 #define PRINTERR(bit, str) \ 1847 if (cmdsts & (bit)) \ 1848 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1849 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1850 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1851 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1852 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1853 #undef PRINTERR 1854 SIP_INIT_RXDESC(sc, i); 1855 continue; 1856 } 1857 1858 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1859 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1860 1861 /* 1862 * No errors; receive the packet. Note, the SiS 900 1863 * includes the CRC with every packet. 1864 */ 1865 len = CMDSTS_SIZE(cmdsts); 1866 1867 #ifdef __NO_STRICT_ALIGNMENT 1868 /* 1869 * If the packet is small enough to fit in a 1870 * single header mbuf, allocate one and copy 1871 * the data into it. This greatly reduces 1872 * memory consumption when we receive lots 1873 * of small packets. 1874 * 1875 * Otherwise, we add a new buffer to the receive 1876 * chain. If this fails, we drop the packet and 1877 * recycle the old buffer. 1878 */ 1879 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 1880 MGETHDR(m, M_DONTWAIT, MT_DATA); 1881 if (m == NULL) 1882 goto dropit; 1883 memcpy(mtod(m, caddr_t), 1884 mtod(rxs->rxs_mbuf, caddr_t), len); 1885 SIP_INIT_RXDESC(sc, i); 1886 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1887 rxs->rxs_dmamap->dm_mapsize, 1888 BUS_DMASYNC_PREREAD); 1889 } else { 1890 m = rxs->rxs_mbuf; 1891 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1892 dropit: 1893 ifp->if_ierrors++; 1894 SIP_INIT_RXDESC(sc, i); 1895 bus_dmamap_sync(sc->sc_dmat, 1896 rxs->rxs_dmamap, 0, 1897 rxs->rxs_dmamap->dm_mapsize, 1898 BUS_DMASYNC_PREREAD); 1899 continue; 1900 } 1901 } 1902 #else 1903 /* 1904 * The SiS 900's receive buffers must be 4-byte aligned. 1905 * But this means that the data after the Ethernet header 1906 * is misaligned. We must allocate a new buffer and 1907 * copy the data, shifted forward 2 bytes. 1908 */ 1909 MGETHDR(m, M_DONTWAIT, MT_DATA); 1910 if (m == NULL) { 1911 dropit: 1912 ifp->if_ierrors++; 1913 SIP_INIT_RXDESC(sc, i); 1914 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1915 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1916 continue; 1917 } 1918 if (len > (MHLEN - 2)) { 1919 MCLGET(m, M_DONTWAIT); 1920 if ((m->m_flags & M_EXT) == 0) { 1921 m_freem(m); 1922 goto dropit; 1923 } 1924 } 1925 m->m_data += 2; 1926 1927 /* 1928 * Note that we use clusters for incoming frames, so the 1929 * buffer is virtually contiguous. 1930 */ 1931 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 1932 1933 /* Allow the receive descriptor to continue using its mbuf. */ 1934 SIP_INIT_RXDESC(sc, i); 1935 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1936 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1937 #endif /* __NO_STRICT_ALIGNMENT */ 1938 1939 ifp->if_ipackets++; 1940 m->m_flags |= M_HASFCS; 1941 m->m_pkthdr.rcvif = ifp; 1942 m->m_pkthdr.len = m->m_len = len; 1943 1944 #if NBPFILTER > 0 1945 /* 1946 * Pass this up to any BPF listeners, but only 1947 * pass if up the stack if it's for us. 1948 */ 1949 if (ifp->if_bpf) 1950 bpf_mtap(ifp->if_bpf, m); 1951 #endif /* NBPFILTER > 0 */ 1952 1953 /* Pass it on. */ 1954 (*ifp->if_input)(ifp, m); 1955 } 1956 1957 /* Update the receive pointer. */ 1958 sc->sc_rxptr = i; 1959 } 1960 #endif /* DP83820 */ 1961 1962 /* 1963 * sip_tick: 1964 * 1965 * One second timer, used to tick the MII. 1966 */ 1967 void 1968 SIP_DECL(tick)(void *arg) 1969 { 1970 struct sip_softc *sc = arg; 1971 int s; 1972 1973 s = splnet(); 1974 mii_tick(&sc->sc_mii); 1975 splx(s); 1976 1977 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 1978 } 1979 1980 /* 1981 * sip_reset: 1982 * 1983 * Perform a soft reset on the SiS 900. 1984 */ 1985 void 1986 SIP_DECL(reset)(struct sip_softc *sc) 1987 { 1988 bus_space_tag_t st = sc->sc_st; 1989 bus_space_handle_t sh = sc->sc_sh; 1990 int i; 1991 1992 bus_space_write_4(st, sh, SIP_IER, 0); 1993 bus_space_write_4(st, sh, SIP_IMR, 0); 1994 bus_space_write_4(st, sh, SIP_RFCR, 0); 1995 bus_space_write_4(st, sh, SIP_CR, CR_RST); 1996 1997 for (i = 0; i < SIP_TIMEOUT; i++) { 1998 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 1999 break; 2000 delay(2); 2001 } 2002 2003 if (i == SIP_TIMEOUT) 2004 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2005 2006 delay(1000); 2007 2008 #ifdef DP83820 2009 /* 2010 * Set the general purpose I/O bits. Do it here in case we 2011 * need to have GPIO set up to talk to the media interface. 2012 */ 2013 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2014 delay(1000); 2015 #endif /* DP83820 */ 2016 } 2017 2018 /* 2019 * sip_init: [ ifnet interface function ] 2020 * 2021 * Initialize the interface. Must be called at splnet(). 2022 */ 2023 int 2024 SIP_DECL(init)(struct ifnet *ifp) 2025 { 2026 struct sip_softc *sc = ifp->if_softc; 2027 bus_space_tag_t st = sc->sc_st; 2028 bus_space_handle_t sh = sc->sc_sh; 2029 struct sip_txsoft *txs; 2030 struct sip_rxsoft *rxs; 2031 struct sip_desc *sipd; 2032 u_int32_t reg; 2033 int i, error = 0; 2034 2035 /* 2036 * Cancel any pending I/O. 2037 */ 2038 SIP_DECL(stop)(ifp, 0); 2039 2040 /* 2041 * Reset the chip to a known state. 2042 */ 2043 SIP_DECL(reset)(sc); 2044 2045 #if !defined(DP83820) 2046 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2047 /* 2048 * DP83815 manual, page 78: 2049 * 4.4 Recommended Registers Configuration 2050 * For optimum performance of the DP83815, version noted 2051 * as DP83815CVNG (SRR = 203h), the listed register 2052 * modifications must be followed in sequence... 2053 * 2054 * It's not clear if this should be 302h or 203h because that 2055 * chip name is listed as SRR 302h in the description of the 2056 * SRR register. However, my revision 302h DP83815 on the 2057 * Netgear FA311 purchased in 02/2001 needs these settings 2058 * to avoid tons of errors in AcceptPerfectMatch (non- 2059 * IFF_PROMISC) mode. I do not know if other revisions need 2060 * this set or not. [briggs -- 09 March 2001] 2061 * 2062 * Note that only the low-order 12 bits of 0xe4 are documented 2063 * and that this sets reserved bits in that register. 2064 */ 2065 reg = bus_space_read_4(st, sh, SIP_NS_SRR); 2066 if (reg == 0x302) { 2067 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2068 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2069 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2070 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2071 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2072 } 2073 } 2074 #endif /* ! DP83820 */ 2075 2076 /* 2077 * Initialize the transmit descriptor ring. 2078 */ 2079 for (i = 0; i < SIP_NTXDESC; i++) { 2080 sipd = &sc->sc_txdescs[i]; 2081 memset(sipd, 0, sizeof(struct sip_desc)); 2082 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2083 } 2084 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2085 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2086 sc->sc_txfree = SIP_NTXDESC; 2087 sc->sc_txnext = 0; 2088 2089 /* 2090 * Initialize the transmit job descriptors. 2091 */ 2092 SIMPLEQ_INIT(&sc->sc_txfreeq); 2093 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2094 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2095 txs = &sc->sc_txsoft[i]; 2096 txs->txs_mbuf = NULL; 2097 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2098 } 2099 2100 /* 2101 * Initialize the receive descriptor and receive job 2102 * descriptor rings. 2103 */ 2104 for (i = 0; i < SIP_NRXDESC; i++) { 2105 rxs = &sc->sc_rxsoft[i]; 2106 if (rxs->rxs_mbuf == NULL) { 2107 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2108 printf("%s: unable to allocate or map rx " 2109 "buffer %d, error = %d\n", 2110 sc->sc_dev.dv_xname, i, error); 2111 /* 2112 * XXX Should attempt to run with fewer receive 2113 * XXX buffers instead of just failing. 2114 */ 2115 SIP_DECL(rxdrain)(sc); 2116 goto out; 2117 } 2118 } else 2119 SIP_INIT_RXDESC(sc, i); 2120 } 2121 sc->sc_rxptr = 0; 2122 #ifdef DP83820 2123 sc->sc_rxdiscard = 0; 2124 SIP_RXCHAIN_RESET(sc); 2125 #endif /* DP83820 */ 2126 2127 /* 2128 * Set the configuration register; it's already initialized 2129 * in sip_attach(). 2130 */ 2131 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2132 2133 /* 2134 * Initialize the prototype TXCFG register. 2135 */ 2136 #if defined(DP83820) 2137 sc->sc_txcfg = TXCFG_MXDMA_512; 2138 sc->sc_rxcfg = RXCFG_MXDMA_512; 2139 #else 2140 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2141 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2142 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & CFG_EDBMASTEN)) { 2143 sc->sc_txcfg = TXCFG_MXDMA_64; 2144 sc->sc_rxcfg = RXCFG_MXDMA_64; 2145 } else { 2146 sc->sc_txcfg = TXCFG_MXDMA_512; 2147 sc->sc_rxcfg = RXCFG_MXDMA_512; 2148 } 2149 #endif /* DP83820 */ 2150 2151 sc->sc_txcfg |= TXCFG_ATP | 2152 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2153 sc->sc_tx_drain_thresh; 2154 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2155 2156 /* 2157 * Initialize the receive drain threshold if we have never 2158 * done so. 2159 */ 2160 if (sc->sc_rx_drain_thresh == 0) { 2161 /* 2162 * XXX This value should be tuned. This is set to the 2163 * maximum of 248 bytes, and we may be able to improve 2164 * performance by decreasing it (although we should never 2165 * set this value lower than 2; 14 bytes are required to 2166 * filter the packet). 2167 */ 2168 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2169 } 2170 2171 /* 2172 * Initialize the prototype RXCFG register. 2173 */ 2174 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2175 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2176 2177 #ifdef DP83820 2178 /* 2179 * Initialize the VLAN/IP receive control register. 2180 * We enable checksum computation on all incoming 2181 * packets, and do not reject packets w/ bad checksums. 2182 */ 2183 reg = 0; 2184 if (ifp->if_capenable & 2185 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2186 reg |= VRCR_IPEN; 2187 if (sc->sc_ethercom.ec_nvlans != 0) 2188 reg |= VRCR_VTDEN|VRCR_VTREN; 2189 bus_space_write_4(st, sh, SIP_VRCR, reg); 2190 2191 /* 2192 * Initialize the VLAN/IP transmit control register. 2193 * We enable outgoing checksum computation on a 2194 * per-packet basis. 2195 */ 2196 reg = 0; 2197 if (ifp->if_capenable & 2198 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2199 reg |= VTCR_PPCHK; 2200 if (sc->sc_ethercom.ec_nvlans != 0) 2201 reg |= VTCR_VPPTI; 2202 bus_space_write_4(st, sh, SIP_VTCR, reg); 2203 2204 /* 2205 * If we're using VLANs, initialize the VLAN data register. 2206 * To understand why we bswap the VLAN Ethertype, see section 2207 * 4.2.36 of the DP83820 manual. 2208 */ 2209 if (sc->sc_ethercom.ec_nvlans != 0) 2210 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2211 #endif /* DP83820 */ 2212 2213 /* 2214 * Give the transmit and receive rings to the chip. 2215 */ 2216 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2217 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2218 2219 /* 2220 * Initialize the interrupt mask. 2221 */ 2222 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2223 ISR_TXURN|ISR_TXDESC|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2224 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2225 2226 /* Set up the receive filter. */ 2227 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2228 2229 /* 2230 * Set the current media. Do this after initializing the prototype 2231 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2232 * control. 2233 */ 2234 mii_mediachg(&sc->sc_mii); 2235 2236 /* 2237 * Enable interrupts. 2238 */ 2239 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2240 2241 /* 2242 * Start the transmit and receive processes. 2243 */ 2244 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2245 2246 /* 2247 * Start the one second MII clock. 2248 */ 2249 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2250 2251 /* 2252 * ...all done! 2253 */ 2254 ifp->if_flags |= IFF_RUNNING; 2255 ifp->if_flags &= ~IFF_OACTIVE; 2256 2257 out: 2258 if (error) 2259 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2260 return (error); 2261 } 2262 2263 /* 2264 * sip_drain: 2265 * 2266 * Drain the receive queue. 2267 */ 2268 void 2269 SIP_DECL(rxdrain)(struct sip_softc *sc) 2270 { 2271 struct sip_rxsoft *rxs; 2272 int i; 2273 2274 for (i = 0; i < SIP_NRXDESC; i++) { 2275 rxs = &sc->sc_rxsoft[i]; 2276 if (rxs->rxs_mbuf != NULL) { 2277 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2278 m_freem(rxs->rxs_mbuf); 2279 rxs->rxs_mbuf = NULL; 2280 } 2281 } 2282 } 2283 2284 /* 2285 * sip_stop: [ ifnet interface function ] 2286 * 2287 * Stop transmission on the interface. 2288 */ 2289 void 2290 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2291 { 2292 struct sip_softc *sc = ifp->if_softc; 2293 bus_space_tag_t st = sc->sc_st; 2294 bus_space_handle_t sh = sc->sc_sh; 2295 struct sip_txsoft *txs; 2296 u_int32_t cmdsts = 0; /* DEBUG */ 2297 2298 /* 2299 * Stop the one second clock. 2300 */ 2301 callout_stop(&sc->sc_tick_ch); 2302 2303 /* Down the MII. */ 2304 mii_down(&sc->sc_mii); 2305 2306 /* 2307 * Disable interrupts. 2308 */ 2309 bus_space_write_4(st, sh, SIP_IER, 0); 2310 2311 /* 2312 * Stop receiver and transmitter. 2313 */ 2314 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2315 2316 /* 2317 * Release any queued transmit buffers. 2318 */ 2319 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2320 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2321 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2322 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2323 CMDSTS_INTR) == 0) 2324 printf("%s: sip_stop: last descriptor does not " 2325 "have INTR bit set\n", sc->sc_dev.dv_xname); 2326 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2327 #ifdef DIAGNOSTIC 2328 if (txs->txs_mbuf == NULL) { 2329 printf("%s: dirty txsoft with no mbuf chain\n", 2330 sc->sc_dev.dv_xname); 2331 panic("sip_stop"); 2332 } 2333 #endif 2334 cmdsts |= /* DEBUG */ 2335 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2336 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2337 m_freem(txs->txs_mbuf); 2338 txs->txs_mbuf = NULL; 2339 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2340 } 2341 2342 if (disable) 2343 SIP_DECL(rxdrain)(sc); 2344 2345 /* 2346 * Mark the interface down and cancel the watchdog timer. 2347 */ 2348 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2349 ifp->if_timer = 0; 2350 2351 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2352 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2353 printf("%s: sip_stop: no INTR bits set in dirty tx " 2354 "descriptors\n", sc->sc_dev.dv_xname); 2355 } 2356 2357 /* 2358 * sip_read_eeprom: 2359 * 2360 * Read data from the serial EEPROM. 2361 */ 2362 void 2363 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2364 u_int16_t *data) 2365 { 2366 bus_space_tag_t st = sc->sc_st; 2367 bus_space_handle_t sh = sc->sc_sh; 2368 u_int16_t reg; 2369 int i, x; 2370 2371 for (i = 0; i < wordcnt; i++) { 2372 /* Send CHIP SELECT. */ 2373 reg = EROMAR_EECS; 2374 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2375 2376 /* Shift in the READ opcode. */ 2377 for (x = 3; x > 0; x--) { 2378 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2379 reg |= EROMAR_EEDI; 2380 else 2381 reg &= ~EROMAR_EEDI; 2382 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2383 bus_space_write_4(st, sh, SIP_EROMAR, 2384 reg | EROMAR_EESK); 2385 delay(4); 2386 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2387 delay(4); 2388 } 2389 2390 /* Shift in address. */ 2391 for (x = 6; x > 0; x--) { 2392 if ((word + i) & (1 << (x - 1))) 2393 reg |= EROMAR_EEDI; 2394 else 2395 reg &= ~EROMAR_EEDI; 2396 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2397 bus_space_write_4(st, sh, SIP_EROMAR, 2398 reg | EROMAR_EESK); 2399 delay(4); 2400 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2401 delay(4); 2402 } 2403 2404 /* Shift out data. */ 2405 reg = EROMAR_EECS; 2406 data[i] = 0; 2407 for (x = 16; x > 0; x--) { 2408 bus_space_write_4(st, sh, SIP_EROMAR, 2409 reg | EROMAR_EESK); 2410 delay(4); 2411 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2412 data[i] |= (1 << (x - 1)); 2413 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2414 delay(4); 2415 } 2416 2417 /* Clear CHIP SELECT. */ 2418 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2419 delay(4); 2420 } 2421 } 2422 2423 /* 2424 * sip_add_rxbuf: 2425 * 2426 * Add a receive buffer to the indicated descriptor. 2427 */ 2428 int 2429 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2430 { 2431 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2432 struct mbuf *m; 2433 int error; 2434 2435 MGETHDR(m, M_DONTWAIT, MT_DATA); 2436 if (m == NULL) 2437 return (ENOBUFS); 2438 2439 MCLGET(m, M_DONTWAIT); 2440 if ((m->m_flags & M_EXT) == 0) { 2441 m_freem(m); 2442 return (ENOBUFS); 2443 } 2444 2445 #if defined(DP83820) 2446 m->m_len = SIP_RXBUF_LEN; 2447 #endif /* DP83820 */ 2448 2449 if (rxs->rxs_mbuf != NULL) 2450 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2451 2452 rxs->rxs_mbuf = m; 2453 2454 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2455 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2456 BUS_DMA_READ|BUS_DMA_NOWAIT); 2457 if (error) { 2458 printf("%s: can't load rx DMA map %d, error = %d\n", 2459 sc->sc_dev.dv_xname, idx, error); 2460 panic("sip_add_rxbuf"); /* XXX */ 2461 } 2462 2463 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2464 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2465 2466 SIP_INIT_RXDESC(sc, idx); 2467 2468 return (0); 2469 } 2470 2471 #if !defined(DP83820) 2472 /* 2473 * sip_sis900_set_filter: 2474 * 2475 * Set up the receive filter. 2476 */ 2477 void 2478 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2479 { 2480 bus_space_tag_t st = sc->sc_st; 2481 bus_space_handle_t sh = sc->sc_sh; 2482 struct ethercom *ec = &sc->sc_ethercom; 2483 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2484 struct ether_multi *enm; 2485 u_int8_t *cp; 2486 struct ether_multistep step; 2487 u_int32_t crc, mchash[16]; 2488 2489 /* 2490 * Initialize the prototype RFCR. 2491 */ 2492 sc->sc_rfcr = RFCR_RFEN; 2493 if (ifp->if_flags & IFF_BROADCAST) 2494 sc->sc_rfcr |= RFCR_AAB; 2495 if (ifp->if_flags & IFF_PROMISC) { 2496 sc->sc_rfcr |= RFCR_AAP; 2497 goto allmulti; 2498 } 2499 2500 /* 2501 * Set up the multicast address filter by passing all multicast 2502 * addresses through a CRC generator, and then using the high-order 2503 * 6 bits as an index into the 128 bit multicast hash table (only 2504 * the lower 16 bits of each 32 bit multicast hash register are 2505 * valid). The high order bits select the register, while the 2506 * rest of the bits select the bit within the register. 2507 */ 2508 2509 memset(mchash, 0, sizeof(mchash)); 2510 2511 ETHER_FIRST_MULTI(step, ec, enm); 2512 while (enm != NULL) { 2513 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2514 /* 2515 * We must listen to a range of multicast addresses. 2516 * For now, just accept all multicasts, rather than 2517 * trying to set only those filter bits needed to match 2518 * the range. (At this time, the only use of address 2519 * ranges is for IP multicast routing, for which the 2520 * range is big enough to require all bits set.) 2521 */ 2522 goto allmulti; 2523 } 2524 2525 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2526 2527 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2528 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2529 /* Just want the 8 most significant bits. */ 2530 crc >>= 24; 2531 } else { 2532 /* Just want the 7 most significant bits. */ 2533 crc >>= 25; 2534 } 2535 2536 /* Set the corresponding bit in the hash table. */ 2537 mchash[crc >> 4] |= 1 << (crc & 0xf); 2538 2539 ETHER_NEXT_MULTI(step, enm); 2540 } 2541 2542 ifp->if_flags &= ~IFF_ALLMULTI; 2543 goto setit; 2544 2545 allmulti: 2546 ifp->if_flags |= IFF_ALLMULTI; 2547 sc->sc_rfcr |= RFCR_AAM; 2548 2549 setit: 2550 #define FILTER_EMIT(addr, data) \ 2551 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2552 delay(1); \ 2553 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2554 delay(1) 2555 2556 /* 2557 * Disable receive filter, and program the node address. 2558 */ 2559 cp = LLADDR(ifp->if_sadl); 2560 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2561 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2562 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2563 2564 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2565 /* 2566 * Program the multicast hash table. 2567 */ 2568 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2569 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2570 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2571 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2572 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2573 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2574 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2575 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2576 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2577 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2578 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2579 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2580 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2581 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2582 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2583 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2584 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2585 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2586 } 2587 } 2588 #undef FILTER_EMIT 2589 2590 /* 2591 * Re-enable the receiver filter. 2592 */ 2593 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2594 } 2595 #endif /* ! DP83820 */ 2596 2597 /* 2598 * sip_dp83815_set_filter: 2599 * 2600 * Set up the receive filter. 2601 */ 2602 void 2603 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2604 { 2605 bus_space_tag_t st = sc->sc_st; 2606 bus_space_handle_t sh = sc->sc_sh; 2607 struct ethercom *ec = &sc->sc_ethercom; 2608 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2609 struct ether_multi *enm; 2610 u_int8_t *cp; 2611 struct ether_multistep step; 2612 u_int32_t crc, hash, slot, bit; 2613 #ifdef DP83820 2614 #define MCHASH_NWORDS 128 2615 #else 2616 #define MCHASH_NWORDS 32 2617 #endif /* DP83820 */ 2618 u_int16_t mchash[MCHASH_NWORDS]; 2619 int i; 2620 2621 /* 2622 * Initialize the prototype RFCR. 2623 * Enable the receive filter, and accept on 2624 * Perfect (destination address) Match 2625 * If IFF_BROADCAST, also accept all broadcast packets. 2626 * If IFF_PROMISC, accept all unicast packets (and later, set 2627 * IFF_ALLMULTI and accept all multicast, too). 2628 */ 2629 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2630 if (ifp->if_flags & IFF_BROADCAST) 2631 sc->sc_rfcr |= RFCR_AAB; 2632 if (ifp->if_flags & IFF_PROMISC) { 2633 sc->sc_rfcr |= RFCR_AAP; 2634 goto allmulti; 2635 } 2636 2637 #ifdef DP83820 2638 /* 2639 * Set up the DP83820 multicast address filter by passing all multicast 2640 * addresses through a CRC generator, and then using the high-order 2641 * 11 bits as an index into the 2048 bit multicast hash table. The 2642 * high-order 7 bits select the slot, while the low-order 4 bits 2643 * select the bit within the slot. Note that only the low 16-bits 2644 * of each filter word are used, and there are 128 filter words. 2645 */ 2646 #else 2647 /* 2648 * Set up the DP83815 multicast address filter by passing all multicast 2649 * addresses through a CRC generator, and then using the high-order 2650 * 9 bits as an index into the 512 bit multicast hash table. The 2651 * high-order 5 bits select the slot, while the low-order 4 bits 2652 * select the bit within the slot. Note that only the low 16-bits 2653 * of each filter word are used, and there are 32 filter words. 2654 */ 2655 #endif /* DP83820 */ 2656 2657 memset(mchash, 0, sizeof(mchash)); 2658 2659 ifp->if_flags &= ~IFF_ALLMULTI; 2660 ETHER_FIRST_MULTI(step, ec, enm); 2661 if (enm == NULL) 2662 goto setit; 2663 while (enm != NULL) { 2664 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2665 /* 2666 * We must listen to a range of multicast addresses. 2667 * For now, just accept all multicasts, rather than 2668 * trying to set only those filter bits needed to match 2669 * the range. (At this time, the only use of address 2670 * ranges is for IP multicast routing, for which the 2671 * range is big enough to require all bits set.) 2672 */ 2673 goto allmulti; 2674 } 2675 2676 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2677 2678 #ifdef DP83820 2679 /* Just want the 11 most significant bits. */ 2680 hash = crc >> 21; 2681 #else 2682 /* Just want the 9 most significant bits. */ 2683 hash = crc >> 23; 2684 #endif /* DP83820 */ 2685 2686 slot = hash >> 4; 2687 bit = hash & 0xf; 2688 2689 /* Set the corresponding bit in the hash table. */ 2690 mchash[slot] |= 1 << bit; 2691 2692 ETHER_NEXT_MULTI(step, enm); 2693 } 2694 sc->sc_rfcr |= RFCR_MHEN; 2695 goto setit; 2696 2697 allmulti: 2698 ifp->if_flags |= IFF_ALLMULTI; 2699 sc->sc_rfcr |= RFCR_AAM; 2700 2701 setit: 2702 #define FILTER_EMIT(addr, data) \ 2703 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2704 delay(1); \ 2705 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2706 delay(1) 2707 2708 /* 2709 * Disable receive filter, and program the node address. 2710 */ 2711 cp = LLADDR(ifp->if_sadl); 2712 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 2713 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 2714 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 2715 2716 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2717 /* 2718 * Program the multicast hash table. 2719 */ 2720 for (i = 0; i < MCHASH_NWORDS; i++) { 2721 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 2722 mchash[i]); 2723 } 2724 } 2725 #undef FILTER_EMIT 2726 #undef MCHASH_NWORDS 2727 2728 /* 2729 * Re-enable the receiver filter. 2730 */ 2731 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2732 } 2733 2734 #if defined(DP83820) 2735 /* 2736 * sip_dp83820_mii_readreg: [mii interface function] 2737 * 2738 * Read a PHY register on the MII of the DP83820. 2739 */ 2740 int 2741 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 2742 { 2743 2744 return (mii_bitbang_readreg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2745 phy, reg)); 2746 } 2747 2748 /* 2749 * sip_dp83820_mii_writereg: [mii interface function] 2750 * 2751 * Write a PHY register on the MII of the DP83820. 2752 */ 2753 void 2754 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 2755 { 2756 2757 mii_bitbang_writereg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2758 phy, reg, val); 2759 } 2760 2761 /* 2762 * sip_dp83815_mii_statchg: [mii interface function] 2763 * 2764 * Callback from MII layer when media changes. 2765 */ 2766 void 2767 SIP_DECL(dp83820_mii_statchg)(struct device *self) 2768 { 2769 struct sip_softc *sc = (struct sip_softc *) self; 2770 u_int32_t cfg; 2771 2772 /* 2773 * Update TXCFG for full-duplex operation. 2774 */ 2775 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2776 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2777 else 2778 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2779 2780 /* 2781 * Update RXCFG for full-duplex or loopback. 2782 */ 2783 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2784 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2785 sc->sc_rxcfg |= RXCFG_ATX; 2786 else 2787 sc->sc_rxcfg &= ~RXCFG_ATX; 2788 2789 /* 2790 * Update CFG for MII/GMII. 2791 */ 2792 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2793 cfg = sc->sc_cfg | CFG_MODE_1000; 2794 else 2795 cfg = sc->sc_cfg; 2796 2797 /* 2798 * XXX 802.3x flow control. 2799 */ 2800 2801 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 2802 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2803 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2804 } 2805 2806 /* 2807 * sip_dp83820_mii_bitbang_read: [mii bit-bang interface function] 2808 * 2809 * Read the MII serial port for the MII bit-bang module. 2810 */ 2811 u_int32_t 2812 SIP_DECL(dp83820_mii_bitbang_read)(struct device *self) 2813 { 2814 struct sip_softc *sc = (void *) self; 2815 2816 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 2817 } 2818 2819 /* 2820 * sip_dp83820_mii_bitbang_write: [mii big-bang interface function] 2821 * 2822 * Write the MII serial port for the MII bit-bang module. 2823 */ 2824 void 2825 SIP_DECL(dp83820_mii_bitbang_write)(struct device *self, u_int32_t val) 2826 { 2827 struct sip_softc *sc = (void *) self; 2828 2829 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 2830 } 2831 #else /* ! DP83820 */ 2832 /* 2833 * sip_sis900_mii_readreg: [mii interface function] 2834 * 2835 * Read a PHY register on the MII. 2836 */ 2837 int 2838 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 2839 { 2840 struct sip_softc *sc = (struct sip_softc *) self; 2841 u_int32_t enphy; 2842 2843 /* 2844 * The SiS 900 has only an internal PHY on the MII. Only allow 2845 * MII address 0. 2846 */ 2847 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 2848 sc->sc_rev < SIS_REV_635 && phy != 0) 2849 return (0); 2850 2851 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2852 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 2853 ENPHY_RWCMD | ENPHY_ACCESS); 2854 do { 2855 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2856 } while (enphy & ENPHY_ACCESS); 2857 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 2858 } 2859 2860 /* 2861 * sip_sis900_mii_writereg: [mii interface function] 2862 * 2863 * Write a PHY register on the MII. 2864 */ 2865 void 2866 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 2867 { 2868 struct sip_softc *sc = (struct sip_softc *) self; 2869 u_int32_t enphy; 2870 2871 /* 2872 * The SiS 900 has only an internal PHY on the MII. Only allow 2873 * MII address 0. 2874 */ 2875 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 2876 sc->sc_rev < SIS_REV_635 && phy != 0) 2877 return; 2878 2879 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2880 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 2881 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 2882 do { 2883 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2884 } while (enphy & ENPHY_ACCESS); 2885 } 2886 2887 /* 2888 * sip_sis900_mii_statchg: [mii interface function] 2889 * 2890 * Callback from MII layer when media changes. 2891 */ 2892 void 2893 SIP_DECL(sis900_mii_statchg)(struct device *self) 2894 { 2895 struct sip_softc *sc = (struct sip_softc *) self; 2896 u_int32_t flowctl; 2897 2898 /* 2899 * Update TXCFG for full-duplex operation. 2900 */ 2901 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2902 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2903 else 2904 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2905 2906 /* 2907 * Update RXCFG for full-duplex or loopback. 2908 */ 2909 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2910 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2911 sc->sc_rxcfg |= RXCFG_ATX; 2912 else 2913 sc->sc_rxcfg &= ~RXCFG_ATX; 2914 2915 /* 2916 * Update IMR for use of 802.3x flow control. 2917 */ 2918 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 2919 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 2920 flowctl = FLOWCTL_FLOWEN; 2921 } else { 2922 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 2923 flowctl = 0; 2924 } 2925 2926 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2927 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2928 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 2929 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 2930 } 2931 2932 /* 2933 * sip_dp83815_mii_readreg: [mii interface function] 2934 * 2935 * Read a PHY register on the MII. 2936 */ 2937 int 2938 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 2939 { 2940 struct sip_softc *sc = (struct sip_softc *) self; 2941 u_int32_t val; 2942 2943 /* 2944 * The DP83815 only has an internal PHY. Only allow 2945 * MII address 0. 2946 */ 2947 if (phy != 0) 2948 return (0); 2949 2950 /* 2951 * Apparently, after a reset, the DP83815 can take a while 2952 * to respond. During this recovery period, the BMSR returns 2953 * a value of 0. Catch this -- it's not supposed to happen 2954 * (the BMSR has some hardcoded-to-1 bits), and wait for the 2955 * PHY to come back to life. 2956 * 2957 * This works out because the BMSR is the first register 2958 * read during the PHY probe process. 2959 */ 2960 do { 2961 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 2962 } while (reg == MII_BMSR && val == 0); 2963 2964 return (val & 0xffff); 2965 } 2966 2967 /* 2968 * sip_dp83815_mii_writereg: [mii interface function] 2969 * 2970 * Write a PHY register to the MII. 2971 */ 2972 void 2973 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 2974 { 2975 struct sip_softc *sc = (struct sip_softc *) self; 2976 2977 /* 2978 * The DP83815 only has an internal PHY. Only allow 2979 * MII address 0. 2980 */ 2981 if (phy != 0) 2982 return; 2983 2984 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 2985 } 2986 2987 /* 2988 * sip_dp83815_mii_statchg: [mii interface function] 2989 * 2990 * Callback from MII layer when media changes. 2991 */ 2992 void 2993 SIP_DECL(dp83815_mii_statchg)(struct device *self) 2994 { 2995 struct sip_softc *sc = (struct sip_softc *) self; 2996 2997 /* 2998 * Update TXCFG for full-duplex operation. 2999 */ 3000 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3001 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3002 else 3003 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3004 3005 /* 3006 * Update RXCFG for full-duplex or loopback. 3007 */ 3008 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3009 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3010 sc->sc_rxcfg |= RXCFG_ATX; 3011 else 3012 sc->sc_rxcfg &= ~RXCFG_ATX; 3013 3014 /* 3015 * XXX 802.3x flow control. 3016 */ 3017 3018 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3019 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3020 } 3021 #endif /* DP83820 */ 3022 3023 #if defined(DP83820) 3024 void 3025 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3026 const struct pci_attach_args *pa, u_int8_t *enaddr) 3027 { 3028 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3029 u_int8_t cksum, *e, match; 3030 int i; 3031 3032 /* 3033 * EEPROM data format for the DP83820 can be found in 3034 * the DP83820 manual, section 4.2.4. 3035 */ 3036 3037 SIP_DECL(read_eeprom)(sc, 0, 3038 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3039 3040 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3041 match = ~(match - 1); 3042 3043 cksum = 0x55; 3044 e = (u_int8_t *) eeprom_data; 3045 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3046 cksum += *e++; 3047 3048 if (cksum != match) 3049 printf("%s: Checksum (%x) mismatch (%x)", 3050 sc->sc_dev.dv_xname, cksum, match); 3051 3052 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3053 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3054 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3055 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3056 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3057 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3058 3059 /* Get the GPIOR bits. */ 3060 sc->sc_gpior = eeprom_data[0x04]; 3061 3062 /* Get various CFG related bits. */ 3063 if ((eeprom_data[0x05] >> 0) & 1) 3064 sc->sc_cfg |= CFG_EXT_125; 3065 if ((eeprom_data[0x05] >> 9) & 1) 3066 sc->sc_cfg |= CFG_TBI_EN; 3067 } 3068 #else /* ! DP83820 */ 3069 void 3070 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3071 const struct pci_attach_args *pa, u_int8_t *enaddr) 3072 { 3073 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3074 3075 switch (sc->sc_rev) { 3076 case SIS_REV_630S: 3077 case SIS_REV_630E: 3078 case SIS_REV_630EA1: 3079 case SIS_REV_630ET: 3080 case SIS_REV_635: 3081 /* 3082 * The MAC address for the on-board Ethernet of 3083 * the SiS 630 chipset is in the NVRAM. Kick 3084 * the chip into re-loading it from NVRAM, and 3085 * read the MAC address out of the filter registers. 3086 */ 3087 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3088 3089 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3090 RFCR_RFADDR_NODE0); 3091 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3092 0xffff; 3093 3094 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3095 RFCR_RFADDR_NODE2); 3096 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3097 0xffff; 3098 3099 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3100 RFCR_RFADDR_NODE4); 3101 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3102 0xffff; 3103 break; 3104 3105 default: 3106 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3107 sizeof(myea) / sizeof(myea[0]), myea); 3108 } 3109 3110 enaddr[0] = myea[0] & 0xff; 3111 enaddr[1] = myea[0] >> 8; 3112 enaddr[2] = myea[1] & 0xff; 3113 enaddr[3] = myea[1] >> 8; 3114 enaddr[4] = myea[2] & 0xff; 3115 enaddr[5] = myea[2] >> 8; 3116 } 3117 3118 /* Table and macro to bit-reverse an octet. */ 3119 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3120 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3121 3122 void 3123 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3124 const struct pci_attach_args *pa, u_int8_t *enaddr) 3125 { 3126 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3127 u_int8_t cksum, *e, match; 3128 int i; 3129 3130 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3131 sizeof(eeprom_data[0]), eeprom_data); 3132 3133 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3134 match = ~(match - 1); 3135 3136 cksum = 0x55; 3137 e = (u_int8_t *) eeprom_data; 3138 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3139 cksum += *e++; 3140 } 3141 if (cksum != match) { 3142 printf("%s: Checksum (%x) mismatch (%x)", 3143 sc->sc_dev.dv_xname, cksum, match); 3144 } 3145 3146 /* 3147 * Unrolled because it makes slightly more sense this way. 3148 * The DP83815 stores the MAC address in bit 0 of word 6 3149 * through bit 15 of word 8. 3150 */ 3151 ea = &eeprom_data[6]; 3152 enaddr[0] = ((*ea & 0x1) << 7); 3153 ea++; 3154 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3155 enaddr[1] = ((*ea & 0x1FE) >> 1); 3156 enaddr[2] = ((*ea & 0x1) << 7); 3157 ea++; 3158 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3159 enaddr[3] = ((*ea & 0x1FE) >> 1); 3160 enaddr[4] = ((*ea & 0x1) << 7); 3161 ea++; 3162 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3163 enaddr[5] = ((*ea & 0x1FE) >> 1); 3164 3165 /* 3166 * In case that's not weird enough, we also need to reverse 3167 * the bits in each byte. This all actually makes more sense 3168 * if you think about the EEPROM storage as an array of bits 3169 * being shifted into bytes, but that's not how we're looking 3170 * at it here... 3171 */ 3172 for (i = 0; i < 6 ;i++) 3173 enaddr[i] = bbr(enaddr[i]); 3174 } 3175 #endif /* DP83820 */ 3176 3177 /* 3178 * sip_mediastatus: [ifmedia interface function] 3179 * 3180 * Get the current interface media status. 3181 */ 3182 void 3183 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3184 { 3185 struct sip_softc *sc = ifp->if_softc; 3186 3187 mii_pollstat(&sc->sc_mii); 3188 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3189 ifmr->ifm_active = sc->sc_mii.mii_media_active; 3190 } 3191 3192 /* 3193 * sip_mediachange: [ifmedia interface function] 3194 * 3195 * Set hardware to newly-selected media. 3196 */ 3197 int 3198 SIP_DECL(mediachange)(struct ifnet *ifp) 3199 { 3200 struct sip_softc *sc = ifp->if_softc; 3201 3202 if (ifp->if_flags & IFF_UP) 3203 mii_mediachg(&sc->sc_mii); 3204 return (0); 3205 } 3206
Indexes created Tue Sep 30 11:09:46 GMT 2025