if_sip.c revision 1.40.2.5
1 /* $NetBSD: if_sip.c,v 1.40.2.5 2002/09/06 08:45:17 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.40.2.5 2002/09/06 08:45:17 jdolecek Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <machine/bus.h> 116 #include <machine/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #ifdef DP83820 122 #include <dev/mii/mii_bitbang.h> 123 #endif /* DP83820 */ 124 125 #include <dev/pci/pcireg.h> 126 #include <dev/pci/pcivar.h> 127 #include <dev/pci/pcidevs.h> 128 129 #include <dev/pci/if_sipreg.h> 130 131 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 132 #define SIP_DECL(x) __CONCAT(gsip_,x) 133 #else /* SiS900 and DP83815 */ 134 #define SIP_DECL(x) __CONCAT(sip_,x) 135 #endif 136 137 #define SIP_STR(x) __STRING(SIP_DECL(x)) 138 139 /* 140 * Transmit descriptor list size. This is arbitrary, but allocate 141 * enough descriptors for 128 pending transmissions, and 8 segments 142 * per packet. This MUST work out to a power of 2. 143 */ 144 #define SIP_NTXSEGS 16 145 #define SIP_NTXSEGS_ALLOC 8 146 147 #define SIP_TXQUEUELEN 256 148 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 149 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 150 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 151 152 #if defined(DP83020) 153 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 154 #else 155 #define TX_DMAMAP_SIZE MCLBYTES 156 #endif 157 158 /* 159 * Receive descriptor list size. We have one Rx buffer per incoming 160 * packet, so this logic is a little simpler. 161 * 162 * Actually, on the DP83820, we allow the packet to consume more than 163 * one buffer, in order to support jumbo Ethernet frames. In that 164 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 165 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 166 * so we'd better be quick about handling receive interrupts. 167 */ 168 #if defined(DP83820) 169 #define SIP_NRXDESC 256 170 #else 171 #define SIP_NRXDESC 128 172 #endif /* DP83820 */ 173 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 174 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 175 176 /* 177 * Control structures are DMA'd to the SiS900 chip. We allocate them in 178 * a single clump that maps to a single DMA segment to make several things 179 * easier. 180 */ 181 struct sip_control_data { 182 /* 183 * The transmit descriptors. 184 */ 185 struct sip_desc scd_txdescs[SIP_NTXDESC]; 186 187 /* 188 * The receive descriptors. 189 */ 190 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 191 }; 192 193 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 194 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 195 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 196 197 /* 198 * Software state for transmit jobs. 199 */ 200 struct sip_txsoft { 201 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 202 bus_dmamap_t txs_dmamap; /* our DMA map */ 203 int txs_firstdesc; /* first descriptor in packet */ 204 int txs_lastdesc; /* last descriptor in packet */ 205 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 206 }; 207 208 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 209 210 /* 211 * Software state for receive jobs. 212 */ 213 struct sip_rxsoft { 214 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 215 bus_dmamap_t rxs_dmamap; /* our DMA map */ 216 }; 217 218 /* 219 * Software state per device. 220 */ 221 struct sip_softc { 222 struct device sc_dev; /* generic device information */ 223 bus_space_tag_t sc_st; /* bus space tag */ 224 bus_space_handle_t sc_sh; /* bus space handle */ 225 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 226 struct ethercom sc_ethercom; /* ethernet common data */ 227 void *sc_sdhook; /* shutdown hook */ 228 229 const struct sip_product *sc_model; /* which model are we? */ 230 int sc_rev; /* chip revision */ 231 232 void *sc_ih; /* interrupt cookie */ 233 234 struct mii_data sc_mii; /* MII/media information */ 235 236 struct callout sc_tick_ch; /* tick callout */ 237 238 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 239 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 240 241 /* 242 * Software state for transmit and receive descriptors. 243 */ 244 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 245 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 246 247 /* 248 * Control data structures. 249 */ 250 struct sip_control_data *sc_control_data; 251 #define sc_txdescs sc_control_data->scd_txdescs 252 #define sc_rxdescs sc_control_data->scd_rxdescs 253 254 #ifdef SIP_EVENT_COUNTERS 255 /* 256 * Event counters. 257 */ 258 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 259 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 260 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 261 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 262 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 263 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 264 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 265 #ifdef DP83820 266 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 267 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 268 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 269 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 270 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 271 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 272 #endif /* DP83820 */ 273 #endif /* SIP_EVENT_COUNTERS */ 274 275 u_int32_t sc_txcfg; /* prototype TXCFG register */ 276 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 277 u_int32_t sc_imr; /* prototype IMR register */ 278 u_int32_t sc_rfcr; /* prototype RFCR register */ 279 280 u_int32_t sc_cfg; /* prototype CFG register */ 281 282 #ifdef DP83820 283 u_int32_t sc_gpior; /* prototype GPIOR register */ 284 #endif /* DP83820 */ 285 286 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 287 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 288 289 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 290 291 int sc_flags; /* misc. flags; see below */ 292 293 int sc_txfree; /* number of free Tx descriptors */ 294 int sc_txnext; /* next ready Tx descriptor */ 295 int sc_txwin; /* Tx descriptors since last intr */ 296 297 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 298 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 299 300 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 301 #if defined(DP83820) 302 int sc_rxdiscard; 303 int sc_rxlen; 304 struct mbuf *sc_rxhead; 305 struct mbuf *sc_rxtail; 306 struct mbuf **sc_rxtailp; 307 #endif /* DP83820 */ 308 309 #if NRND > 0 310 rndsource_element_t rnd_source; /* random source */ 311 #endif 312 }; 313 314 /* sc_flags */ 315 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 316 317 #ifdef DP83820 318 #define SIP_RXCHAIN_RESET(sc) \ 319 do { \ 320 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 321 *(sc)->sc_rxtailp = NULL; \ 322 (sc)->sc_rxlen = 0; \ 323 } while (/*CONSTCOND*/0) 324 325 #define SIP_RXCHAIN_LINK(sc, m) \ 326 do { \ 327 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 328 (sc)->sc_rxtailp = &(m)->m_next; \ 329 } while (/*CONSTCOND*/0) 330 #endif /* DP83820 */ 331 332 #ifdef SIP_EVENT_COUNTERS 333 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 334 #else 335 #define SIP_EVCNT_INCR(ev) /* nothing */ 336 #endif 337 338 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 339 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 340 341 #define SIP_CDTXSYNC(sc, x, n, ops) \ 342 do { \ 343 int __x, __n; \ 344 \ 345 __x = (x); \ 346 __n = (n); \ 347 \ 348 /* If it will wrap around, sync to the end of the ring. */ \ 349 if ((__x + __n) > SIP_NTXDESC) { \ 350 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 351 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 352 (SIP_NTXDESC - __x), (ops)); \ 353 __n -= (SIP_NTXDESC - __x); \ 354 __x = 0; \ 355 } \ 356 \ 357 /* Now sync whatever is left. */ \ 358 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 359 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 360 } while (0) 361 362 #define SIP_CDRXSYNC(sc, x, ops) \ 363 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 364 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 365 366 #ifdef DP83820 367 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 368 #define SIP_RXBUF_LEN (MCLBYTES - 4) 369 #else 370 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 371 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 372 #endif 373 #define SIP_INIT_RXDESC(sc, x) \ 374 do { \ 375 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 376 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 377 \ 378 __sipd->sipd_link = \ 379 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 380 __sipd->sipd_bufptr = \ 381 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 382 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 383 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 384 SIP_INIT_RXDESC_EXTSTS \ 385 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 386 } while (0) 387 388 #define SIP_CHIP_VERS(sc, v, p, r) \ 389 ((sc)->sc_model->sip_vendor == (v) && \ 390 (sc)->sc_model->sip_product == (p) && \ 391 (sc)->sc_rev == (r)) 392 393 #define SIP_CHIP_MODEL(sc, v, p) \ 394 ((sc)->sc_model->sip_vendor == (v) && \ 395 (sc)->sc_model->sip_product == (p)) 396 397 #if !defined(DP83820) 398 #define SIP_SIS900_REV(sc, rev) \ 399 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 400 #endif 401 402 #define SIP_TIMEOUT 1000 403 404 void SIP_DECL(start)(struct ifnet *); 405 void SIP_DECL(watchdog)(struct ifnet *); 406 int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 407 int SIP_DECL(init)(struct ifnet *); 408 void SIP_DECL(stop)(struct ifnet *, int); 409 410 void SIP_DECL(shutdown)(void *); 411 412 void SIP_DECL(reset)(struct sip_softc *); 413 void SIP_DECL(rxdrain)(struct sip_softc *); 414 int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 415 void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, u_int16_t *); 416 void SIP_DECL(tick)(void *); 417 418 #if !defined(DP83820) 419 void SIP_DECL(sis900_set_filter)(struct sip_softc *); 420 #endif /* ! DP83820 */ 421 void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 422 423 #if defined(DP83820) 424 void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 425 const struct pci_attach_args *, u_int8_t *); 426 #else 427 void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 428 const struct pci_attach_args *, u_int8_t *); 429 void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 430 const struct pci_attach_args *, u_int8_t *); 431 #endif /* DP83820 */ 432 433 int SIP_DECL(intr)(void *); 434 void SIP_DECL(txintr)(struct sip_softc *); 435 void SIP_DECL(rxintr)(struct sip_softc *); 436 437 #if defined(DP83820) 438 int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 439 void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 440 void SIP_DECL(dp83820_mii_statchg)(struct device *); 441 #else 442 int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 443 void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 444 void SIP_DECL(sis900_mii_statchg)(struct device *); 445 446 int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 447 void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 448 void SIP_DECL(dp83815_mii_statchg)(struct device *); 449 #endif /* DP83820 */ 450 451 int SIP_DECL(mediachange)(struct ifnet *); 452 void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 453 454 int SIP_DECL(match)(struct device *, struct cfdata *, void *); 455 void SIP_DECL(attach)(struct device *, struct device *, void *); 456 457 int SIP_DECL(copy_small) = 0; 458 459 struct cfattach SIP_DECL(ca) = { 460 sizeof(struct sip_softc), SIP_DECL(match), SIP_DECL(attach), 461 }; 462 463 /* 464 * Descriptions of the variants of the SiS900. 465 */ 466 struct sip_variant { 467 int (*sipv_mii_readreg)(struct device *, int, int); 468 void (*sipv_mii_writereg)(struct device *, int, int, int); 469 void (*sipv_mii_statchg)(struct device *); 470 void (*sipv_set_filter)(struct sip_softc *); 471 void (*sipv_read_macaddr)(struct sip_softc *, 472 const struct pci_attach_args *, u_int8_t *); 473 }; 474 475 #if defined(DP83820) 476 u_int32_t SIP_DECL(dp83820_mii_bitbang_read)(struct device *); 477 void SIP_DECL(dp83820_mii_bitbang_write)(struct device *, u_int32_t); 478 479 const struct mii_bitbang_ops SIP_DECL(dp83820_mii_bitbang_ops) = { 480 SIP_DECL(dp83820_mii_bitbang_read), 481 SIP_DECL(dp83820_mii_bitbang_write), 482 { 483 EROMAR_MDIO, /* MII_BIT_MDO */ 484 EROMAR_MDIO, /* MII_BIT_MDI */ 485 EROMAR_MDC, /* MII_BIT_MDC */ 486 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 487 0, /* MII_BIT_DIR_PHY_HOST */ 488 } 489 }; 490 #endif /* DP83820 */ 491 492 #if defined(DP83820) 493 const struct sip_variant SIP_DECL(variant_dp83820) = { 494 SIP_DECL(dp83820_mii_readreg), 495 SIP_DECL(dp83820_mii_writereg), 496 SIP_DECL(dp83820_mii_statchg), 497 SIP_DECL(dp83815_set_filter), 498 SIP_DECL(dp83820_read_macaddr), 499 }; 500 #else 501 const struct sip_variant SIP_DECL(variant_sis900) = { 502 SIP_DECL(sis900_mii_readreg), 503 SIP_DECL(sis900_mii_writereg), 504 SIP_DECL(sis900_mii_statchg), 505 SIP_DECL(sis900_set_filter), 506 SIP_DECL(sis900_read_macaddr), 507 }; 508 509 const struct sip_variant SIP_DECL(variant_dp83815) = { 510 SIP_DECL(dp83815_mii_readreg), 511 SIP_DECL(dp83815_mii_writereg), 512 SIP_DECL(dp83815_mii_statchg), 513 SIP_DECL(dp83815_set_filter), 514 SIP_DECL(dp83815_read_macaddr), 515 }; 516 #endif /* DP83820 */ 517 518 /* 519 * Devices supported by this driver. 520 */ 521 const struct sip_product { 522 pci_vendor_id_t sip_vendor; 523 pci_product_id_t sip_product; 524 const char *sip_name; 525 const struct sip_variant *sip_variant; 526 } SIP_DECL(products)[] = { 527 #if defined(DP83820) 528 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 529 "NatSemi DP83820 Gigabit Ethernet", 530 &SIP_DECL(variant_dp83820) }, 531 #else 532 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 533 "SiS 900 10/100 Ethernet", 534 &SIP_DECL(variant_sis900) }, 535 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 536 "SiS 7016 10/100 Ethernet", 537 &SIP_DECL(variant_sis900) }, 538 539 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 540 "NatSemi DP83815 10/100 Ethernet", 541 &SIP_DECL(variant_dp83815) }, 542 #endif /* DP83820 */ 543 544 { 0, 0, 545 NULL, 546 NULL }, 547 }; 548 549 static const struct sip_product * 550 SIP_DECL(lookup)(const struct pci_attach_args *pa) 551 { 552 const struct sip_product *sip; 553 554 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 555 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 556 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 557 return (sip); 558 } 559 return (NULL); 560 } 561 562 #ifdef DP83820 563 /* 564 * I really hate stupid hardware vendors. There's a bit in the EEPROM 565 * which indicates if the card can do 64-bit data transfers. Unfortunately, 566 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 567 * which means we try to use 64-bit data transfers on those cards if we 568 * happen to be plugged into a 32-bit slot. 569 * 570 * What we do is use this table of cards known to be 64-bit cards. If 571 * you have a 64-bit card who's subsystem ID is not listed in this table, 572 * send the output of "pcictl dump ..." of the device to me so that your 573 * card will use the 64-bit data path when plugged into a 64-bit slot. 574 * 575 * -- Jason R. Thorpe <thorpej (at) netbsd.org> 576 * June 30, 2002 577 */ 578 static int 579 SIP_DECL(check_64bit)(const struct pci_attach_args *pa) 580 { 581 static const struct { 582 pci_vendor_id_t c64_vendor; 583 pci_product_id_t c64_product; 584 } card64[] = { 585 /* Asante GigaNIX */ 586 { 0x128a, 0x0002 }, 587 588 /* Accton EN1407-T, Planex GN-1000TE */ 589 { 0x1113, 0x1407 }, 590 591 /* Netgear GA-621 */ 592 { 0x1385, 0x621a }, 593 594 { 0, 0} 595 }; 596 pcireg_t subsys; 597 int i; 598 599 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 600 601 for (i = 0; card64[i].c64_vendor != 0; i++) { 602 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 603 PCI_PRODUCT(subsys) == card64[i].c64_product) 604 return (1); 605 } 606 607 return (0); 608 } 609 #endif /* DP83820 */ 610 611 int 612 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 613 { 614 struct pci_attach_args *pa = aux; 615 616 if (SIP_DECL(lookup)(pa) != NULL) 617 return (1); 618 619 return (0); 620 } 621 622 void 623 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 624 { 625 struct sip_softc *sc = (struct sip_softc *) self; 626 struct pci_attach_args *pa = aux; 627 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 628 pci_chipset_tag_t pc = pa->pa_pc; 629 pci_intr_handle_t ih; 630 const char *intrstr = NULL; 631 bus_space_tag_t iot, memt; 632 bus_space_handle_t ioh, memh; 633 bus_dma_segment_t seg; 634 int ioh_valid, memh_valid; 635 int i, rseg, error; 636 const struct sip_product *sip; 637 pcireg_t pmode; 638 u_int8_t enaddr[ETHER_ADDR_LEN]; 639 int pmreg; 640 #ifdef DP83820 641 pcireg_t memtype; 642 u_int32_t reg; 643 #endif /* DP83820 */ 644 645 callout_init(&sc->sc_tick_ch); 646 647 sip = SIP_DECL(lookup)(pa); 648 if (sip == NULL) { 649 printf("\n"); 650 panic(SIP_STR(attach) ": impossible"); 651 } 652 sc->sc_rev = PCI_REVISION(pa->pa_class); 653 654 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 655 656 sc->sc_model = sip; 657 658 /* 659 * XXX Work-around broken PXE firmware on some boards. 660 * 661 * The DP83815 shares an address decoder with the MEM BAR 662 * and the ROM BAR. Make sure the ROM BAR is disabled, 663 * so that memory mapped access works. 664 */ 665 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 666 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 667 ~PCI_MAPREG_ROM_ENABLE); 668 669 /* 670 * Map the device. 671 */ 672 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 673 PCI_MAPREG_TYPE_IO, 0, 674 &iot, &ioh, NULL, NULL) == 0); 675 #ifdef DP83820 676 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 677 switch (memtype) { 678 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 679 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 680 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 681 memtype, 0, &memt, &memh, NULL, NULL) == 0); 682 break; 683 default: 684 memh_valid = 0; 685 } 686 #else 687 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 688 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 689 &memt, &memh, NULL, NULL) == 0); 690 #endif /* DP83820 */ 691 692 if (memh_valid) { 693 printf("%s: using memory mapped registers\n", sc->sc_dev.dv_xname); 694 sc->sc_st = memt; 695 sc->sc_sh = memh; 696 } else if (ioh_valid) { 697 printf("%s: using I/O mapped registers\n", sc->sc_dev.dv_xname); 698 sc->sc_st = iot; 699 sc->sc_sh = ioh; 700 } else { 701 printf("%s: unable to map device registers\n", 702 sc->sc_dev.dv_xname); 703 return; 704 } 705 706 sc->sc_dmat = pa->pa_dmat; 707 708 /* 709 * Make sure bus mastering is enabled. Also make sure 710 * Write/Invalidate is enabled if we're allowed to use it. 711 */ 712 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 713 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 714 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 715 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 716 pmreg | PCI_COMMAND_MASTER_ENABLE); 717 718 /* Get it out of power save mode if needed. */ 719 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 720 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 721 if (pmode == 3) { 722 /* 723 * The card has lost all configuration data in 724 * this state, so punt. 725 */ 726 printf("%s: unable to wake up from power state D3\n", 727 sc->sc_dev.dv_xname); 728 return; 729 } 730 if (pmode != 0) { 731 printf("%s: waking up from power state D%d\n", 732 sc->sc_dev.dv_xname, pmode); 733 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 734 } 735 } 736 737 /* 738 * Map and establish our interrupt. 739 */ 740 if (pci_intr_map(pa, &ih)) { 741 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 742 return; 743 } 744 intrstr = pci_intr_string(pc, ih); 745 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 746 if (sc->sc_ih == NULL) { 747 printf("%s: unable to establish interrupt", 748 sc->sc_dev.dv_xname); 749 if (intrstr != NULL) 750 printf(" at %s", intrstr); 751 printf("\n"); 752 return; 753 } 754 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 755 756 SIMPLEQ_INIT(&sc->sc_txfreeq); 757 SIMPLEQ_INIT(&sc->sc_txdirtyq); 758 759 /* 760 * Allocate the control data structures, and create and load the 761 * DMA map for it. 762 */ 763 if ((error = bus_dmamem_alloc(sc->sc_dmat, 764 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 765 0)) != 0) { 766 printf("%s: unable to allocate control data, error = %d\n", 767 sc->sc_dev.dv_xname, error); 768 goto fail_0; 769 } 770 771 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 772 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 773 BUS_DMA_COHERENT)) != 0) { 774 printf("%s: unable to map control data, error = %d\n", 775 sc->sc_dev.dv_xname, error); 776 goto fail_1; 777 } 778 779 if ((error = bus_dmamap_create(sc->sc_dmat, 780 sizeof(struct sip_control_data), 1, 781 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 782 printf("%s: unable to create control data DMA map, " 783 "error = %d\n", sc->sc_dev.dv_xname, error); 784 goto fail_2; 785 } 786 787 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 788 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 789 0)) != 0) { 790 printf("%s: unable to load control data DMA map, error = %d\n", 791 sc->sc_dev.dv_xname, error); 792 goto fail_3; 793 } 794 795 /* 796 * Create the transmit buffer DMA maps. 797 */ 798 for (i = 0; i < SIP_TXQUEUELEN; i++) { 799 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 800 SIP_NTXSEGS, MCLBYTES, 0, 0, 801 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 802 printf("%s: unable to create tx DMA map %d, " 803 "error = %d\n", sc->sc_dev.dv_xname, i, error); 804 goto fail_4; 805 } 806 } 807 808 /* 809 * Create the receive buffer DMA maps. 810 */ 811 for (i = 0; i < SIP_NRXDESC; i++) { 812 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 813 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 814 printf("%s: unable to create rx DMA map %d, " 815 "error = %d\n", sc->sc_dev.dv_xname, i, error); 816 goto fail_5; 817 } 818 sc->sc_rxsoft[i].rxs_mbuf = NULL; 819 } 820 821 /* 822 * Reset the chip to a known state. 823 */ 824 SIP_DECL(reset)(sc); 825 826 /* 827 * Read the Ethernet address from the EEPROM. This might 828 * also fetch other stuff from the EEPROM and stash it 829 * in the softc. 830 */ 831 sc->sc_cfg = 0; 832 #if !defined(DP83820) 833 if (SIP_SIS900_REV(sc,SIS_REV_635) || 834 SIP_SIS900_REV(sc,SIS_REV_900B)) 835 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 836 #endif 837 838 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 839 840 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 841 ether_sprintf(enaddr)); 842 843 /* 844 * Initialize the configuration register: aggressive PCI 845 * bus request algorithm, default backoff, default OW timer, 846 * default parity error detection. 847 * 848 * NOTE: "Big endian mode" is useless on the SiS900 and 849 * friends -- it affects packet data, not descriptors. 850 */ 851 #ifdef DP83820 852 /* 853 * Cause the chip to load configuration data from the EEPROM. 854 */ 855 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 856 for (i = 0; i < 10000; i++) { 857 delay(10); 858 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 859 PTSCR_EELOAD_EN) == 0) 860 break; 861 } 862 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 863 PTSCR_EELOAD_EN) { 864 printf("%s: timeout loading configuration from EEPROM\n", 865 sc->sc_dev.dv_xname); 866 return; 867 } 868 869 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 870 871 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 872 if (reg & CFG_PCI64_DET) { 873 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 874 /* 875 * Check to see if this card is 64-bit. If so, enable 64-bit 876 * data transfers. 877 * 878 * We can't use the DATA64_EN bit in the EEPROM, because 879 * vendors of 32-bit cards fail to clear that bit in many 880 * cases (yet the card still detects that it's in a 64-bit 881 * slot; go figure). 882 */ 883 if (SIP_DECL(check_64bit)(pa)) { 884 sc->sc_cfg |= CFG_DATA64_EN; 885 printf(", using 64-bit data transfers"); 886 } 887 printf("\n"); 888 } 889 890 /* 891 * XXX Need some PCI flags indicating support for 892 * XXX 64-bit addressing. 893 */ 894 #if 0 895 if (reg & CFG_M64ADDR) 896 sc->sc_cfg |= CFG_M64ADDR; 897 if (reg & CFG_T64ADDR) 898 sc->sc_cfg |= CFG_T64ADDR; 899 #endif 900 901 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 902 const char *sep = ""; 903 printf("%s: using ", sc->sc_dev.dv_xname); 904 if (reg & CFG_EXT_125) { 905 sc->sc_cfg |= CFG_EXT_125; 906 printf("%s125MHz clock", sep); 907 sep = ", "; 908 } 909 if (reg & CFG_TBI_EN) { 910 sc->sc_cfg |= CFG_TBI_EN; 911 printf("%sten-bit interface", sep); 912 sep = ", "; 913 } 914 printf("\n"); 915 } 916 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 917 (reg & CFG_MRM_DIS) != 0) 918 sc->sc_cfg |= CFG_MRM_DIS; 919 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 920 (reg & CFG_MWI_DIS) != 0) 921 sc->sc_cfg |= CFG_MWI_DIS; 922 923 /* 924 * Use the extended descriptor format on the DP83820. This 925 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 926 * checksumming. 927 */ 928 sc->sc_cfg |= CFG_EXTSTS_EN; 929 #endif /* DP83820 */ 930 931 /* 932 * Initialize our media structures and probe the MII. 933 */ 934 sc->sc_mii.mii_ifp = ifp; 935 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 936 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 937 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 938 ifmedia_init(&sc->sc_mii.mii_media, 0, SIP_DECL(mediachange), 939 SIP_DECL(mediastatus)); 940 941 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 942 MII_OFFSET_ANY, 0); 943 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 944 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 945 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 946 } else 947 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 948 949 ifp = &sc->sc_ethercom.ec_if; 950 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 951 ifp->if_softc = sc; 952 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 953 ifp->if_ioctl = SIP_DECL(ioctl); 954 ifp->if_start = SIP_DECL(start); 955 ifp->if_watchdog = SIP_DECL(watchdog); 956 ifp->if_init = SIP_DECL(init); 957 ifp->if_stop = SIP_DECL(stop); 958 IFQ_SET_READY(&ifp->if_snd); 959 960 /* 961 * We can support 802.1Q VLAN-sized frames. 962 */ 963 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 964 965 #ifdef DP83820 966 /* 967 * And the DP83820 can do VLAN tagging in hardware, and 968 * support the jumbo Ethernet MTU. 969 */ 970 sc->sc_ethercom.ec_capabilities |= 971 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 972 973 /* 974 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 975 * in hardware. 976 */ 977 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 978 IFCAP_CSUM_UDPv4; 979 #endif /* DP83820 */ 980 981 /* 982 * Attach the interface. 983 */ 984 if_attach(ifp); 985 ether_ifattach(ifp, enaddr); 986 #if NRND > 0 987 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 988 RND_TYPE_NET, 0); 989 #endif 990 991 /* 992 * The number of bytes that must be available in 993 * the Tx FIFO before the bus master can DMA more 994 * data into the FIFO. 995 */ 996 sc->sc_tx_fill_thresh = 64 / 32; 997 998 /* 999 * Start at a drain threshold of 512 bytes. We will 1000 * increase it if a DMA underrun occurs. 1001 * 1002 * XXX The minimum value of this variable should be 1003 * tuned. We may be able to improve performance 1004 * by starting with a lower value. That, however, 1005 * may trash the first few outgoing packets if the 1006 * PCI bus is saturated. 1007 */ 1008 sc->sc_tx_drain_thresh = 1504 / 32; 1009 1010 /* 1011 * Initialize the Rx FIFO drain threshold. 1012 * 1013 * This is in units of 8 bytes. 1014 * 1015 * We should never set this value lower than 2; 14 bytes are 1016 * required to filter the packet. 1017 */ 1018 sc->sc_rx_drain_thresh = 128 / 8; 1019 1020 #ifdef SIP_EVENT_COUNTERS 1021 /* 1022 * Attach event counters. 1023 */ 1024 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1025 NULL, sc->sc_dev.dv_xname, "txsstall"); 1026 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1027 NULL, sc->sc_dev.dv_xname, "txdstall"); 1028 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1029 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1030 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1031 NULL, sc->sc_dev.dv_xname, "txdintr"); 1032 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1033 NULL, sc->sc_dev.dv_xname, "txiintr"); 1034 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1035 NULL, sc->sc_dev.dv_xname, "rxintr"); 1036 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1037 NULL, sc->sc_dev.dv_xname, "hiberr"); 1038 #ifdef DP83820 1039 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1040 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1041 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1042 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1043 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1044 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1045 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1046 NULL, sc->sc_dev.dv_xname, "txipsum"); 1047 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1048 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1049 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1050 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1051 #endif /* DP83820 */ 1052 #endif /* SIP_EVENT_COUNTERS */ 1053 1054 /* 1055 * Make sure the interface is shutdown during reboot. 1056 */ 1057 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 1058 if (sc->sc_sdhook == NULL) 1059 printf("%s: WARNING: unable to establish shutdown hook\n", 1060 sc->sc_dev.dv_xname); 1061 return; 1062 1063 /* 1064 * Free any resources we've allocated during the failed attach 1065 * attempt. Do this in reverse order and fall through. 1066 */ 1067 fail_5: 1068 for (i = 0; i < SIP_NRXDESC; i++) { 1069 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1070 bus_dmamap_destroy(sc->sc_dmat, 1071 sc->sc_rxsoft[i].rxs_dmamap); 1072 } 1073 fail_4: 1074 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1075 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1076 bus_dmamap_destroy(sc->sc_dmat, 1077 sc->sc_txsoft[i].txs_dmamap); 1078 } 1079 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1080 fail_3: 1081 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1082 fail_2: 1083 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1084 sizeof(struct sip_control_data)); 1085 fail_1: 1086 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1087 fail_0: 1088 return; 1089 } 1090 1091 /* 1092 * sip_shutdown: 1093 * 1094 * Make sure the interface is stopped at reboot time. 1095 */ 1096 void 1097 SIP_DECL(shutdown)(void *arg) 1098 { 1099 struct sip_softc *sc = arg; 1100 1101 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1102 } 1103 1104 /* 1105 * sip_start: [ifnet interface function] 1106 * 1107 * Start packet transmission on the interface. 1108 */ 1109 void 1110 SIP_DECL(start)(struct ifnet *ifp) 1111 { 1112 struct sip_softc *sc = ifp->if_softc; 1113 struct mbuf *m0, *m; 1114 struct sip_txsoft *txs; 1115 bus_dmamap_t dmamap; 1116 int error, nexttx, lasttx, seg; 1117 int ofree = sc->sc_txfree; 1118 #if 0 1119 int firsttx = sc->sc_txnext; 1120 #endif 1121 #ifdef DP83820 1122 u_int32_t extsts; 1123 #endif 1124 1125 /* 1126 * If we've been told to pause, don't transmit any more packets. 1127 */ 1128 if (sc->sc_flags & SIPF_PAUSED) 1129 ifp->if_flags |= IFF_OACTIVE; 1130 1131 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1132 return; 1133 1134 /* 1135 * Loop through the send queue, setting up transmit descriptors 1136 * until we drain the queue, or use up all available transmit 1137 * descriptors. 1138 */ 1139 for (;;) { 1140 /* Get a work queue entry. */ 1141 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1142 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1143 break; 1144 } 1145 1146 /* 1147 * Grab a packet off the queue. 1148 */ 1149 IFQ_POLL(&ifp->if_snd, m0); 1150 if (m0 == NULL) 1151 break; 1152 #ifndef DP83820 1153 m = NULL; 1154 #endif 1155 1156 dmamap = txs->txs_dmamap; 1157 1158 #ifdef DP83820 1159 /* 1160 * Load the DMA map. If this fails, the packet either 1161 * didn't fit in the allotted number of segments, or we 1162 * were short on resources. For the too-many-segments 1163 * case, we simply report an error and drop the packet, 1164 * since we can't sanely copy a jumbo packet to a single 1165 * buffer. 1166 */ 1167 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1168 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1169 if (error) { 1170 if (error == EFBIG) { 1171 printf("%s: Tx packet consumes too many " 1172 "DMA segments, dropping...\n", 1173 sc->sc_dev.dv_xname); 1174 IFQ_DEQUEUE(&ifp->if_snd, m0); 1175 m_freem(m0); 1176 continue; 1177 } 1178 /* 1179 * Short on resources, just stop for now. 1180 */ 1181 break; 1182 } 1183 #else /* DP83820 */ 1184 /* 1185 * Load the DMA map. If this fails, the packet either 1186 * didn't fit in the alloted number of segments, or we 1187 * were short on resources. In this case, we'll copy 1188 * and try again. 1189 */ 1190 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1191 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1192 MGETHDR(m, M_DONTWAIT, MT_DATA); 1193 if (m == NULL) { 1194 printf("%s: unable to allocate Tx mbuf\n", 1195 sc->sc_dev.dv_xname); 1196 break; 1197 } 1198 if (m0->m_pkthdr.len > MHLEN) { 1199 MCLGET(m, M_DONTWAIT); 1200 if ((m->m_flags & M_EXT) == 0) { 1201 printf("%s: unable to allocate Tx " 1202 "cluster\n", sc->sc_dev.dv_xname); 1203 m_freem(m); 1204 break; 1205 } 1206 } 1207 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1208 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1209 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1210 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1211 if (error) { 1212 printf("%s: unable to load Tx buffer, " 1213 "error = %d\n", sc->sc_dev.dv_xname, error); 1214 break; 1215 } 1216 } 1217 #endif /* DP83820 */ 1218 1219 /* 1220 * Ensure we have enough descriptors free to describe 1221 * the packet. Note, we always reserve one descriptor 1222 * at the end of the ring as a termination point, to 1223 * prevent wrap-around. 1224 */ 1225 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1226 /* 1227 * Not enough free descriptors to transmit this 1228 * packet. We haven't committed anything yet, 1229 * so just unload the DMA map, put the packet 1230 * back on the queue, and punt. Notify the upper 1231 * layer that there are not more slots left. 1232 * 1233 * XXX We could allocate an mbuf and copy, but 1234 * XXX is it worth it? 1235 */ 1236 ifp->if_flags |= IFF_OACTIVE; 1237 bus_dmamap_unload(sc->sc_dmat, dmamap); 1238 #ifndef DP83820 1239 if (m != NULL) 1240 m_freem(m); 1241 #endif 1242 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1243 break; 1244 } 1245 1246 IFQ_DEQUEUE(&ifp->if_snd, m0); 1247 #ifndef DP83820 1248 if (m != NULL) { 1249 m_freem(m0); 1250 m0 = m; 1251 } 1252 #endif 1253 1254 /* 1255 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1256 */ 1257 1258 /* Sync the DMA map. */ 1259 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1260 BUS_DMASYNC_PREWRITE); 1261 1262 /* 1263 * Initialize the transmit descriptors. 1264 */ 1265 for (nexttx = sc->sc_txnext, seg = 0; 1266 seg < dmamap->dm_nsegs; 1267 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1268 /* 1269 * If this is the first descriptor we're 1270 * enqueueing, don't set the OWN bit just 1271 * yet. That could cause a race condition. 1272 * We'll do it below. 1273 */ 1274 sc->sc_txdescs[nexttx].sipd_bufptr = 1275 htole32(dmamap->dm_segs[seg].ds_addr); 1276 sc->sc_txdescs[nexttx].sipd_cmdsts = 1277 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1278 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1279 #ifdef DP83820 1280 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1281 #endif /* DP83820 */ 1282 lasttx = nexttx; 1283 } 1284 1285 /* Clear the MORE bit on the last segment. */ 1286 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1287 1288 /* 1289 * If we're in the interrupt delay window, delay the 1290 * interrupt. 1291 */ 1292 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1293 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1294 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1295 htole32(CMDSTS_INTR); 1296 sc->sc_txwin = 0; 1297 } 1298 1299 #ifdef DP83820 1300 /* 1301 * If VLANs are enabled and the packet has a VLAN tag, set 1302 * up the descriptor to encapsulate the packet for us. 1303 * 1304 * This apparently has to be on the last descriptor of 1305 * the packet. 1306 */ 1307 if (sc->sc_ethercom.ec_nvlans != 0 && 1308 (m = m_aux_find(m0, AF_LINK, ETHERTYPE_VLAN)) != NULL) { 1309 sc->sc_txdescs[lasttx].sipd_extsts |= 1310 htole32(EXTSTS_VPKT | 1311 htons(*mtod(m, int *) & EXTSTS_VTCI)); 1312 } 1313 1314 /* 1315 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1316 * checksumming, set up the descriptor to do this work 1317 * for us. 1318 * 1319 * This apparently has to be on the first descriptor of 1320 * the packet. 1321 * 1322 * Byte-swap constants so the compiler can optimize. 1323 */ 1324 extsts = 0; 1325 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1326 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1327 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1328 extsts |= htole32(EXTSTS_IPPKT); 1329 } 1330 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1331 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1332 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1333 extsts |= htole32(EXTSTS_TCPPKT); 1334 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1335 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1336 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1337 extsts |= htole32(EXTSTS_UDPPKT); 1338 } 1339 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1340 #endif /* DP83820 */ 1341 1342 /* Sync the descriptors we're using. */ 1343 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1344 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1345 1346 /* 1347 * The entire packet is set up. Give the first descrptor 1348 * to the chip now. 1349 */ 1350 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1351 htole32(CMDSTS_OWN); 1352 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1353 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1354 1355 /* 1356 * Store a pointer to the packet so we can free it later, 1357 * and remember what txdirty will be once the packet is 1358 * done. 1359 */ 1360 txs->txs_mbuf = m0; 1361 txs->txs_firstdesc = sc->sc_txnext; 1362 txs->txs_lastdesc = lasttx; 1363 1364 /* Advance the tx pointer. */ 1365 sc->sc_txfree -= dmamap->dm_nsegs; 1366 sc->sc_txnext = nexttx; 1367 1368 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1369 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1370 1371 #if NBPFILTER > 0 1372 /* 1373 * Pass the packet to any BPF listeners. 1374 */ 1375 if (ifp->if_bpf) 1376 bpf_mtap(ifp->if_bpf, m0); 1377 #endif /* NBPFILTER > 0 */ 1378 } 1379 1380 if (txs == NULL || sc->sc_txfree == 0) { 1381 /* No more slots left; notify upper layer. */ 1382 ifp->if_flags |= IFF_OACTIVE; 1383 } 1384 1385 if (sc->sc_txfree != ofree) { 1386 /* 1387 * Start the transmit process. Note, the manual says 1388 * that if there are no pending transmissions in the 1389 * chip's internal queue (indicated by TXE being clear), 1390 * then the driver software must set the TXDP to the 1391 * first descriptor to be transmitted. However, if we 1392 * do this, it causes serious performance degredation on 1393 * the DP83820 under load, not setting TXDP doesn't seem 1394 * to adversely affect the SiS 900 or DP83815. 1395 * 1396 * Well, I guess it wouldn't be the first time a manual 1397 * has lied -- and they could be speaking of the NULL- 1398 * terminated descriptor list case, rather than OWN- 1399 * terminated rings. 1400 */ 1401 #if 0 1402 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1403 CR_TXE) == 0) { 1404 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1405 SIP_CDTXADDR(sc, firsttx)); 1406 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1407 } 1408 #else 1409 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1410 #endif 1411 1412 /* Set a watchdog timer in case the chip flakes out. */ 1413 ifp->if_timer = 5; 1414 } 1415 } 1416 1417 /* 1418 * sip_watchdog: [ifnet interface function] 1419 * 1420 * Watchdog timer handler. 1421 */ 1422 void 1423 SIP_DECL(watchdog)(struct ifnet *ifp) 1424 { 1425 struct sip_softc *sc = ifp->if_softc; 1426 1427 /* 1428 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1429 * If we get a timeout, try and sweep up transmit descriptors. 1430 * If we manage to sweep them all up, ignore the lack of 1431 * interrupt. 1432 */ 1433 SIP_DECL(txintr)(sc); 1434 1435 if (sc->sc_txfree != SIP_NTXDESC) { 1436 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1437 ifp->if_oerrors++; 1438 1439 /* Reset the interface. */ 1440 (void) SIP_DECL(init)(ifp); 1441 } else if (ifp->if_flags & IFF_DEBUG) 1442 printf("%s: recovered from device timeout\n", 1443 sc->sc_dev.dv_xname); 1444 1445 /* Try to get more packets going. */ 1446 SIP_DECL(start)(ifp); 1447 } 1448 1449 /* 1450 * sip_ioctl: [ifnet interface function] 1451 * 1452 * Handle control requests from the operator. 1453 */ 1454 int 1455 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1456 { 1457 struct sip_softc *sc = ifp->if_softc; 1458 struct ifreq *ifr = (struct ifreq *)data; 1459 int s, error; 1460 1461 s = splnet(); 1462 1463 switch (cmd) { 1464 case SIOCSIFMEDIA: 1465 case SIOCGIFMEDIA: 1466 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1467 break; 1468 1469 default: 1470 error = ether_ioctl(ifp, cmd, data); 1471 if (error == ENETRESET) { 1472 /* 1473 * Multicast list has changed; set the hardware filter 1474 * accordingly. 1475 */ 1476 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1477 error = 0; 1478 } 1479 break; 1480 } 1481 1482 /* Try to get more packets going. */ 1483 SIP_DECL(start)(ifp); 1484 1485 splx(s); 1486 return (error); 1487 } 1488 1489 /* 1490 * sip_intr: 1491 * 1492 * Interrupt service routine. 1493 */ 1494 int 1495 SIP_DECL(intr)(void *arg) 1496 { 1497 struct sip_softc *sc = arg; 1498 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1499 u_int32_t isr; 1500 int handled = 0; 1501 1502 for (;;) { 1503 /* Reading clears interrupt. */ 1504 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1505 if ((isr & sc->sc_imr) == 0) 1506 break; 1507 1508 #if NRND > 0 1509 if (RND_ENABLED(&sc->rnd_source)) 1510 rnd_add_uint32(&sc->rnd_source, isr); 1511 #endif 1512 1513 handled = 1; 1514 1515 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1516 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1517 1518 /* Grab any new packets. */ 1519 SIP_DECL(rxintr)(sc); 1520 1521 if (isr & ISR_RXORN) { 1522 printf("%s: receive FIFO overrun\n", 1523 sc->sc_dev.dv_xname); 1524 1525 /* XXX adjust rx_drain_thresh? */ 1526 } 1527 1528 if (isr & ISR_RXIDLE) { 1529 printf("%s: receive ring overrun\n", 1530 sc->sc_dev.dv_xname); 1531 1532 /* Get the receive process going again. */ 1533 bus_space_write_4(sc->sc_st, sc->sc_sh, 1534 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1535 bus_space_write_4(sc->sc_st, sc->sc_sh, 1536 SIP_CR, CR_RXE); 1537 } 1538 } 1539 1540 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1541 #ifdef SIP_EVENT_COUNTERS 1542 if (isr & ISR_TXDESC) 1543 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1544 else if (isr & ISR_TXIDLE) 1545 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1546 #endif 1547 1548 /* Sweep up transmit descriptors. */ 1549 SIP_DECL(txintr)(sc); 1550 1551 if (isr & ISR_TXURN) { 1552 u_int32_t thresh; 1553 1554 printf("%s: transmit FIFO underrun", 1555 sc->sc_dev.dv_xname); 1556 1557 thresh = sc->sc_tx_drain_thresh + 1; 1558 if (thresh <= TXCFG_DRTH && 1559 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1560 (sc->sc_tx_fill_thresh * 32))) { 1561 printf("; increasing Tx drain " 1562 "threshold to %u bytes\n", 1563 thresh * 32); 1564 sc->sc_tx_drain_thresh = thresh; 1565 (void) SIP_DECL(init)(ifp); 1566 } else { 1567 (void) SIP_DECL(init)(ifp); 1568 printf("\n"); 1569 } 1570 } 1571 } 1572 1573 #if !defined(DP83820) 1574 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1575 if (isr & ISR_PAUSE_ST) { 1576 sc->sc_flags |= SIPF_PAUSED; 1577 ifp->if_flags |= IFF_OACTIVE; 1578 } 1579 if (isr & ISR_PAUSE_END) { 1580 sc->sc_flags &= ~SIPF_PAUSED; 1581 ifp->if_flags &= ~IFF_OACTIVE; 1582 } 1583 } 1584 #endif /* ! DP83820 */ 1585 1586 if (isr & ISR_HIBERR) { 1587 int want_init = 0; 1588 1589 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1590 1591 #define PRINTERR(bit, str) \ 1592 do { \ 1593 if ((isr & (bit)) != 0) { \ 1594 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1595 printf("%s: %s\n", \ 1596 sc->sc_dev.dv_xname, str); \ 1597 want_init = 1; \ 1598 } \ 1599 } while (/*CONSTCOND*/0) 1600 1601 PRINTERR(ISR_DPERR, "parity error"); 1602 PRINTERR(ISR_SSERR, "system error"); 1603 PRINTERR(ISR_RMABT, "master abort"); 1604 PRINTERR(ISR_RTABT, "target abort"); 1605 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1606 /* 1607 * Ignore: 1608 * Tx reset complete 1609 * Rx reset complete 1610 */ 1611 if (want_init) 1612 (void) SIP_DECL(init)(ifp); 1613 #undef PRINTERR 1614 } 1615 } 1616 1617 /* Try to get more packets going. */ 1618 SIP_DECL(start)(ifp); 1619 1620 return (handled); 1621 } 1622 1623 /* 1624 * sip_txintr: 1625 * 1626 * Helper; handle transmit interrupts. 1627 */ 1628 void 1629 SIP_DECL(txintr)(struct sip_softc *sc) 1630 { 1631 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1632 struct sip_txsoft *txs; 1633 u_int32_t cmdsts; 1634 1635 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1636 ifp->if_flags &= ~IFF_OACTIVE; 1637 1638 /* 1639 * Go through our Tx list and free mbufs for those 1640 * frames which have been transmitted. 1641 */ 1642 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1643 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1644 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1645 1646 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1647 if (cmdsts & CMDSTS_OWN) 1648 break; 1649 1650 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1651 1652 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1653 1654 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1655 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1656 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1657 m_freem(txs->txs_mbuf); 1658 txs->txs_mbuf = NULL; 1659 1660 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1661 1662 /* 1663 * Check for errors and collisions. 1664 */ 1665 if (cmdsts & 1666 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1667 ifp->if_oerrors++; 1668 if (cmdsts & CMDSTS_Tx_EC) 1669 ifp->if_collisions += 16; 1670 if (ifp->if_flags & IFF_DEBUG) { 1671 if (cmdsts & CMDSTS_Tx_ED) 1672 printf("%s: excessive deferral\n", 1673 sc->sc_dev.dv_xname); 1674 if (cmdsts & CMDSTS_Tx_EC) 1675 printf("%s: excessive collisions\n", 1676 sc->sc_dev.dv_xname); 1677 } 1678 } else { 1679 /* Packet was transmitted successfully. */ 1680 ifp->if_opackets++; 1681 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1682 } 1683 } 1684 1685 /* 1686 * If there are no more pending transmissions, cancel the watchdog 1687 * timer. 1688 */ 1689 if (txs == NULL) { 1690 ifp->if_timer = 0; 1691 sc->sc_txwin = 0; 1692 } 1693 } 1694 1695 #if defined(DP83820) 1696 /* 1697 * sip_rxintr: 1698 * 1699 * Helper; handle receive interrupts. 1700 */ 1701 void 1702 SIP_DECL(rxintr)(struct sip_softc *sc) 1703 { 1704 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1705 struct sip_rxsoft *rxs; 1706 struct mbuf *m, *tailm; 1707 u_int32_t cmdsts, extsts; 1708 int i, len; 1709 1710 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1711 rxs = &sc->sc_rxsoft[i]; 1712 1713 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1714 1715 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1716 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1717 1718 /* 1719 * NOTE: OWN is set if owned by _consumer_. We're the 1720 * consumer of the receive ring, so if the bit is clear, 1721 * we have processed all of the packets. 1722 */ 1723 if ((cmdsts & CMDSTS_OWN) == 0) { 1724 /* 1725 * We have processed all of the receive buffers. 1726 */ 1727 break; 1728 } 1729 1730 if (__predict_false(sc->sc_rxdiscard)) { 1731 SIP_INIT_RXDESC(sc, i); 1732 if ((cmdsts & CMDSTS_MORE) == 0) { 1733 /* Reset our state. */ 1734 sc->sc_rxdiscard = 0; 1735 } 1736 continue; 1737 } 1738 1739 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1740 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1741 1742 m = rxs->rxs_mbuf; 1743 1744 /* 1745 * Add a new receive buffer to the ring. 1746 */ 1747 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1748 /* 1749 * Failed, throw away what we've done so 1750 * far, and discard the rest of the packet. 1751 */ 1752 ifp->if_ierrors++; 1753 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1754 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1755 SIP_INIT_RXDESC(sc, i); 1756 if (cmdsts & CMDSTS_MORE) 1757 sc->sc_rxdiscard = 1; 1758 if (sc->sc_rxhead != NULL) 1759 m_freem(sc->sc_rxhead); 1760 SIP_RXCHAIN_RESET(sc); 1761 continue; 1762 } 1763 1764 SIP_RXCHAIN_LINK(sc, m); 1765 1766 /* 1767 * If this is not the end of the packet, keep 1768 * looking. 1769 */ 1770 if (cmdsts & CMDSTS_MORE) { 1771 sc->sc_rxlen += m->m_len; 1772 continue; 1773 } 1774 1775 /* 1776 * Okay, we have the entire packet now... 1777 */ 1778 *sc->sc_rxtailp = NULL; 1779 m = sc->sc_rxhead; 1780 tailm = sc->sc_rxtail; 1781 1782 SIP_RXCHAIN_RESET(sc); 1783 1784 /* 1785 * If an error occurred, update stats and drop the packet. 1786 */ 1787 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1788 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1789 ifp->if_ierrors++; 1790 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1791 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1792 /* Receive overrun handled elsewhere. */ 1793 printf("%s: receive descriptor error\n", 1794 sc->sc_dev.dv_xname); 1795 } 1796 #define PRINTERR(bit, str) \ 1797 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1798 (cmdsts & (bit)) != 0) \ 1799 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1800 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1801 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1802 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1803 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1804 #undef PRINTERR 1805 m_freem(m); 1806 continue; 1807 } 1808 1809 /* 1810 * No errors. 1811 * 1812 * Note, the DP83820 includes the CRC with 1813 * every packet. 1814 */ 1815 len = CMDSTS_SIZE(cmdsts); 1816 tailm->m_len = len - sc->sc_rxlen; 1817 1818 /* 1819 * If the packet is small enough to fit in a 1820 * single header mbuf, allocate one and copy 1821 * the data into it. This greatly reduces 1822 * memory consumption when we receive lots 1823 * of small packets. 1824 */ 1825 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1826 struct mbuf *nm; 1827 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1828 if (nm == NULL) { 1829 ifp->if_ierrors++; 1830 m_freem(m); 1831 continue; 1832 } 1833 nm->m_data += 2; 1834 nm->m_pkthdr.len = nm->m_len = len; 1835 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1836 m_freem(m); 1837 m = nm; 1838 } 1839 #ifndef __NO_STRICT_ALIGNMENT 1840 else { 1841 /* 1842 * The DP83820's receive buffers must be 4-byte 1843 * aligned. But this means that the data after 1844 * the Ethernet header is misaligned. To compensate, 1845 * we have artificially shortened the buffer size 1846 * in the descriptor, and we do an overlapping copy 1847 * of the data two bytes further in (in the first 1848 * buffer of the chain only). 1849 */ 1850 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1851 m->m_len); 1852 m->m_data += 2; 1853 } 1854 #endif /* ! __NO_STRICT_ALIGNMENT */ 1855 1856 /* 1857 * If VLANs are enabled, VLAN packets have been unwrapped 1858 * for us. Associate the tag with the packet. 1859 */ 1860 if (sc->sc_ethercom.ec_nvlans != 0 && 1861 (extsts & EXTSTS_VPKT) != 0) { 1862 struct mbuf *vtag; 1863 1864 vtag = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 1865 if (vtag == NULL) { 1866 ifp->if_ierrors++; 1867 printf("%s: unable to allocate VLAN tag\n", 1868 sc->sc_dev.dv_xname); 1869 m_freem(m); 1870 continue; 1871 } 1872 1873 *mtod(vtag, int *) = ntohs(extsts & EXTSTS_VTCI); 1874 vtag->m_len = sizeof(int); 1875 } 1876 1877 /* 1878 * Set the incoming checksum information for the 1879 * packet. 1880 */ 1881 if ((extsts & EXTSTS_IPPKT) != 0) { 1882 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1883 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1884 if (extsts & EXTSTS_Rx_IPERR) 1885 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1886 if (extsts & EXTSTS_TCPPKT) { 1887 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1888 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1889 if (extsts & EXTSTS_Rx_TCPERR) 1890 m->m_pkthdr.csum_flags |= 1891 M_CSUM_TCP_UDP_BAD; 1892 } else if (extsts & EXTSTS_UDPPKT) { 1893 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1894 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1895 if (extsts & EXTSTS_Rx_UDPERR) 1896 m->m_pkthdr.csum_flags |= 1897 M_CSUM_TCP_UDP_BAD; 1898 } 1899 } 1900 1901 ifp->if_ipackets++; 1902 m->m_flags |= M_HASFCS; 1903 m->m_pkthdr.rcvif = ifp; 1904 m->m_pkthdr.len = len; 1905 1906 #if NBPFILTER > 0 1907 /* 1908 * Pass this up to any BPF listeners, but only 1909 * pass if up the stack if it's for us. 1910 */ 1911 if (ifp->if_bpf) 1912 bpf_mtap(ifp->if_bpf, m); 1913 #endif /* NBPFILTER > 0 */ 1914 1915 /* Pass it on. */ 1916 (*ifp->if_input)(ifp, m); 1917 } 1918 1919 /* Update the receive pointer. */ 1920 sc->sc_rxptr = i; 1921 } 1922 #else /* ! DP83820 */ 1923 /* 1924 * sip_rxintr: 1925 * 1926 * Helper; handle receive interrupts. 1927 */ 1928 void 1929 SIP_DECL(rxintr)(struct sip_softc *sc) 1930 { 1931 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1932 struct sip_rxsoft *rxs; 1933 struct mbuf *m; 1934 u_int32_t cmdsts; 1935 int i, len; 1936 1937 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1938 rxs = &sc->sc_rxsoft[i]; 1939 1940 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1941 1942 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1943 1944 /* 1945 * NOTE: OWN is set if owned by _consumer_. We're the 1946 * consumer of the receive ring, so if the bit is clear, 1947 * we have processed all of the packets. 1948 */ 1949 if ((cmdsts & CMDSTS_OWN) == 0) { 1950 /* 1951 * We have processed all of the receive buffers. 1952 */ 1953 break; 1954 } 1955 1956 /* 1957 * If any collisions were seen on the wire, count one. 1958 */ 1959 if (cmdsts & CMDSTS_Rx_COL) 1960 ifp->if_collisions++; 1961 1962 /* 1963 * If an error occurred, update stats, clear the status 1964 * word, and leave the packet buffer in place. It will 1965 * simply be reused the next time the ring comes around. 1966 */ 1967 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1968 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1969 ifp->if_ierrors++; 1970 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1971 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1972 /* Receive overrun handled elsewhere. */ 1973 printf("%s: receive descriptor error\n", 1974 sc->sc_dev.dv_xname); 1975 } 1976 #define PRINTERR(bit, str) \ 1977 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1978 (cmdsts & (bit)) != 0) \ 1979 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1980 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1981 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1982 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1983 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1984 #undef PRINTERR 1985 SIP_INIT_RXDESC(sc, i); 1986 continue; 1987 } 1988 1989 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1990 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1991 1992 /* 1993 * No errors; receive the packet. Note, the SiS 900 1994 * includes the CRC with every packet. 1995 */ 1996 len = CMDSTS_SIZE(cmdsts); 1997 1998 #ifdef __NO_STRICT_ALIGNMENT 1999 /* 2000 * If the packet is small enough to fit in a 2001 * single header mbuf, allocate one and copy 2002 * the data into it. This greatly reduces 2003 * memory consumption when we receive lots 2004 * of small packets. 2005 * 2006 * Otherwise, we add a new buffer to the receive 2007 * chain. If this fails, we drop the packet and 2008 * recycle the old buffer. 2009 */ 2010 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 2011 MGETHDR(m, M_DONTWAIT, MT_DATA); 2012 if (m == NULL) 2013 goto dropit; 2014 memcpy(mtod(m, caddr_t), 2015 mtod(rxs->rxs_mbuf, caddr_t), len); 2016 SIP_INIT_RXDESC(sc, i); 2017 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2018 rxs->rxs_dmamap->dm_mapsize, 2019 BUS_DMASYNC_PREREAD); 2020 } else { 2021 m = rxs->rxs_mbuf; 2022 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 2023 dropit: 2024 ifp->if_ierrors++; 2025 SIP_INIT_RXDESC(sc, i); 2026 bus_dmamap_sync(sc->sc_dmat, 2027 rxs->rxs_dmamap, 0, 2028 rxs->rxs_dmamap->dm_mapsize, 2029 BUS_DMASYNC_PREREAD); 2030 continue; 2031 } 2032 } 2033 #else 2034 /* 2035 * The SiS 900's receive buffers must be 4-byte aligned. 2036 * But this means that the data after the Ethernet header 2037 * is misaligned. We must allocate a new buffer and 2038 * copy the data, shifted forward 2 bytes. 2039 */ 2040 MGETHDR(m, M_DONTWAIT, MT_DATA); 2041 if (m == NULL) { 2042 dropit: 2043 ifp->if_ierrors++; 2044 SIP_INIT_RXDESC(sc, i); 2045 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2046 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2047 continue; 2048 } 2049 if (len > (MHLEN - 2)) { 2050 MCLGET(m, M_DONTWAIT); 2051 if ((m->m_flags & M_EXT) == 0) { 2052 m_freem(m); 2053 goto dropit; 2054 } 2055 } 2056 m->m_data += 2; 2057 2058 /* 2059 * Note that we use clusters for incoming frames, so the 2060 * buffer is virtually contiguous. 2061 */ 2062 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 2063 2064 /* Allow the receive descriptor to continue using its mbuf. */ 2065 SIP_INIT_RXDESC(sc, i); 2066 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2067 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2068 #endif /* __NO_STRICT_ALIGNMENT */ 2069 2070 ifp->if_ipackets++; 2071 m->m_flags |= M_HASFCS; 2072 m->m_pkthdr.rcvif = ifp; 2073 m->m_pkthdr.len = m->m_len = len; 2074 2075 #if NBPFILTER > 0 2076 /* 2077 * Pass this up to any BPF listeners, but only 2078 * pass if up the stack if it's for us. 2079 */ 2080 if (ifp->if_bpf) 2081 bpf_mtap(ifp->if_bpf, m); 2082 #endif /* NBPFILTER > 0 */ 2083 2084 /* Pass it on. */ 2085 (*ifp->if_input)(ifp, m); 2086 } 2087 2088 /* Update the receive pointer. */ 2089 sc->sc_rxptr = i; 2090 } 2091 #endif /* DP83820 */ 2092 2093 /* 2094 * sip_tick: 2095 * 2096 * One second timer, used to tick the MII. 2097 */ 2098 void 2099 SIP_DECL(tick)(void *arg) 2100 { 2101 struct sip_softc *sc = arg; 2102 int s; 2103 2104 s = splnet(); 2105 mii_tick(&sc->sc_mii); 2106 splx(s); 2107 2108 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2109 } 2110 2111 /* 2112 * sip_reset: 2113 * 2114 * Perform a soft reset on the SiS 900. 2115 */ 2116 void 2117 SIP_DECL(reset)(struct sip_softc *sc) 2118 { 2119 bus_space_tag_t st = sc->sc_st; 2120 bus_space_handle_t sh = sc->sc_sh; 2121 int i; 2122 2123 bus_space_write_4(st, sh, SIP_IER, 0); 2124 bus_space_write_4(st, sh, SIP_IMR, 0); 2125 bus_space_write_4(st, sh, SIP_RFCR, 0); 2126 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2127 2128 for (i = 0; i < SIP_TIMEOUT; i++) { 2129 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2130 break; 2131 delay(2); 2132 } 2133 2134 if (i == SIP_TIMEOUT) 2135 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2136 2137 delay(1000); 2138 2139 #ifdef DP83820 2140 /* 2141 * Set the general purpose I/O bits. Do it here in case we 2142 * need to have GPIO set up to talk to the media interface. 2143 */ 2144 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2145 delay(1000); 2146 #endif /* DP83820 */ 2147 } 2148 2149 /* 2150 * sip_init: [ ifnet interface function ] 2151 * 2152 * Initialize the interface. Must be called at splnet(). 2153 */ 2154 int 2155 SIP_DECL(init)(struct ifnet *ifp) 2156 { 2157 struct sip_softc *sc = ifp->if_softc; 2158 bus_space_tag_t st = sc->sc_st; 2159 bus_space_handle_t sh = sc->sc_sh; 2160 struct sip_txsoft *txs; 2161 struct sip_rxsoft *rxs; 2162 struct sip_desc *sipd; 2163 u_int32_t reg; 2164 int i, error = 0; 2165 2166 /* 2167 * Cancel any pending I/O. 2168 */ 2169 SIP_DECL(stop)(ifp, 0); 2170 2171 /* 2172 * Reset the chip to a known state. 2173 */ 2174 SIP_DECL(reset)(sc); 2175 2176 #if !defined(DP83820) 2177 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2178 /* 2179 * DP83815 manual, page 78: 2180 * 4.4 Recommended Registers Configuration 2181 * For optimum performance of the DP83815, version noted 2182 * as DP83815CVNG (SRR = 203h), the listed register 2183 * modifications must be followed in sequence... 2184 * 2185 * It's not clear if this should be 302h or 203h because that 2186 * chip name is listed as SRR 302h in the description of the 2187 * SRR register. However, my revision 302h DP83815 on the 2188 * Netgear FA311 purchased in 02/2001 needs these settings 2189 * to avoid tons of errors in AcceptPerfectMatch (non- 2190 * IFF_PROMISC) mode. I do not know if other revisions need 2191 * this set or not. [briggs -- 09 March 2001] 2192 * 2193 * Note that only the low-order 12 bits of 0xe4 are documented 2194 * and that this sets reserved bits in that register. 2195 */ 2196 reg = bus_space_read_4(st, sh, SIP_NS_SRR); 2197 if (reg == 0x302) { 2198 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2199 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2200 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2201 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2202 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2203 } 2204 } 2205 #endif /* ! DP83820 */ 2206 2207 /* 2208 * Initialize the transmit descriptor ring. 2209 */ 2210 for (i = 0; i < SIP_NTXDESC; i++) { 2211 sipd = &sc->sc_txdescs[i]; 2212 memset(sipd, 0, sizeof(struct sip_desc)); 2213 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2214 } 2215 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2216 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2217 sc->sc_txfree = SIP_NTXDESC; 2218 sc->sc_txnext = 0; 2219 sc->sc_txwin = 0; 2220 2221 /* 2222 * Initialize the transmit job descriptors. 2223 */ 2224 SIMPLEQ_INIT(&sc->sc_txfreeq); 2225 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2226 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2227 txs = &sc->sc_txsoft[i]; 2228 txs->txs_mbuf = NULL; 2229 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2230 } 2231 2232 /* 2233 * Initialize the receive descriptor and receive job 2234 * descriptor rings. 2235 */ 2236 for (i = 0; i < SIP_NRXDESC; i++) { 2237 rxs = &sc->sc_rxsoft[i]; 2238 if (rxs->rxs_mbuf == NULL) { 2239 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2240 printf("%s: unable to allocate or map rx " 2241 "buffer %d, error = %d\n", 2242 sc->sc_dev.dv_xname, i, error); 2243 /* 2244 * XXX Should attempt to run with fewer receive 2245 * XXX buffers instead of just failing. 2246 */ 2247 SIP_DECL(rxdrain)(sc); 2248 goto out; 2249 } 2250 } else 2251 SIP_INIT_RXDESC(sc, i); 2252 } 2253 sc->sc_rxptr = 0; 2254 #ifdef DP83820 2255 sc->sc_rxdiscard = 0; 2256 SIP_RXCHAIN_RESET(sc); 2257 #endif /* DP83820 */ 2258 2259 /* 2260 * Set the configuration register; it's already initialized 2261 * in sip_attach(). 2262 */ 2263 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2264 2265 /* 2266 * Initialize the prototype TXCFG register. 2267 */ 2268 #if defined(DP83820) 2269 sc->sc_txcfg = TXCFG_MXDMA_512; 2270 sc->sc_rxcfg = RXCFG_MXDMA_512; 2271 #else 2272 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2273 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2274 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & CFG_EDBMASTEN)) { 2275 sc->sc_txcfg = TXCFG_MXDMA_64; 2276 sc->sc_rxcfg = RXCFG_MXDMA_64; 2277 } else { 2278 sc->sc_txcfg = TXCFG_MXDMA_512; 2279 sc->sc_rxcfg = RXCFG_MXDMA_512; 2280 } 2281 #endif /* DP83820 */ 2282 2283 sc->sc_txcfg |= TXCFG_ATP | 2284 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2285 sc->sc_tx_drain_thresh; 2286 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2287 2288 /* 2289 * Initialize the receive drain threshold if we have never 2290 * done so. 2291 */ 2292 if (sc->sc_rx_drain_thresh == 0) { 2293 /* 2294 * XXX This value should be tuned. This is set to the 2295 * maximum of 248 bytes, and we may be able to improve 2296 * performance by decreasing it (although we should never 2297 * set this value lower than 2; 14 bytes are required to 2298 * filter the packet). 2299 */ 2300 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2301 } 2302 2303 /* 2304 * Initialize the prototype RXCFG register. 2305 */ 2306 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2307 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2308 2309 #ifdef DP83820 2310 /* 2311 * Initialize the VLAN/IP receive control register. 2312 * We enable checksum computation on all incoming 2313 * packets, and do not reject packets w/ bad checksums. 2314 */ 2315 reg = 0; 2316 if (ifp->if_capenable & 2317 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2318 reg |= VRCR_IPEN; 2319 if (sc->sc_ethercom.ec_nvlans != 0) 2320 reg |= VRCR_VTDEN|VRCR_VTREN; 2321 bus_space_write_4(st, sh, SIP_VRCR, reg); 2322 2323 /* 2324 * Initialize the VLAN/IP transmit control register. 2325 * We enable outgoing checksum computation on a 2326 * per-packet basis. 2327 */ 2328 reg = 0; 2329 if (ifp->if_capenable & 2330 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2331 reg |= VTCR_PPCHK; 2332 if (sc->sc_ethercom.ec_nvlans != 0) 2333 reg |= VTCR_VPPTI; 2334 bus_space_write_4(st, sh, SIP_VTCR, reg); 2335 2336 /* 2337 * If we're using VLANs, initialize the VLAN data register. 2338 * To understand why we bswap the VLAN Ethertype, see section 2339 * 4.2.36 of the DP83820 manual. 2340 */ 2341 if (sc->sc_ethercom.ec_nvlans != 0) 2342 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2343 #endif /* DP83820 */ 2344 2345 /* 2346 * Give the transmit and receive rings to the chip. 2347 */ 2348 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2349 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2350 2351 /* 2352 * Initialize the interrupt mask. 2353 */ 2354 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2355 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2356 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2357 2358 /* Set up the receive filter. */ 2359 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2360 2361 /* 2362 * Set the current media. Do this after initializing the prototype 2363 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2364 * control. 2365 */ 2366 mii_mediachg(&sc->sc_mii); 2367 2368 /* 2369 * Enable interrupts. 2370 */ 2371 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2372 2373 /* 2374 * Start the transmit and receive processes. 2375 */ 2376 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2377 2378 /* 2379 * Start the one second MII clock. 2380 */ 2381 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2382 2383 /* 2384 * ...all done! 2385 */ 2386 ifp->if_flags |= IFF_RUNNING; 2387 ifp->if_flags &= ~IFF_OACTIVE; 2388 2389 out: 2390 if (error) 2391 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2392 return (error); 2393 } 2394 2395 /* 2396 * sip_drain: 2397 * 2398 * Drain the receive queue. 2399 */ 2400 void 2401 SIP_DECL(rxdrain)(struct sip_softc *sc) 2402 { 2403 struct sip_rxsoft *rxs; 2404 int i; 2405 2406 for (i = 0; i < SIP_NRXDESC; i++) { 2407 rxs = &sc->sc_rxsoft[i]; 2408 if (rxs->rxs_mbuf != NULL) { 2409 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2410 m_freem(rxs->rxs_mbuf); 2411 rxs->rxs_mbuf = NULL; 2412 } 2413 } 2414 } 2415 2416 /* 2417 * sip_stop: [ ifnet interface function ] 2418 * 2419 * Stop transmission on the interface. 2420 */ 2421 void 2422 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2423 { 2424 struct sip_softc *sc = ifp->if_softc; 2425 bus_space_tag_t st = sc->sc_st; 2426 bus_space_handle_t sh = sc->sc_sh; 2427 struct sip_txsoft *txs; 2428 u_int32_t cmdsts = 0; /* DEBUG */ 2429 2430 /* 2431 * Stop the one second clock. 2432 */ 2433 callout_stop(&sc->sc_tick_ch); 2434 2435 /* Down the MII. */ 2436 mii_down(&sc->sc_mii); 2437 2438 /* 2439 * Disable interrupts. 2440 */ 2441 bus_space_write_4(st, sh, SIP_IER, 0); 2442 2443 /* 2444 * Stop receiver and transmitter. 2445 */ 2446 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2447 2448 /* 2449 * Release any queued transmit buffers. 2450 */ 2451 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2452 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2453 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2454 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2455 CMDSTS_INTR) == 0) 2456 printf("%s: sip_stop: last descriptor does not " 2457 "have INTR bit set\n", sc->sc_dev.dv_xname); 2458 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2459 #ifdef DIAGNOSTIC 2460 if (txs->txs_mbuf == NULL) { 2461 printf("%s: dirty txsoft with no mbuf chain\n", 2462 sc->sc_dev.dv_xname); 2463 panic("sip_stop"); 2464 } 2465 #endif 2466 cmdsts |= /* DEBUG */ 2467 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2468 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2469 m_freem(txs->txs_mbuf); 2470 txs->txs_mbuf = NULL; 2471 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2472 } 2473 2474 if (disable) 2475 SIP_DECL(rxdrain)(sc); 2476 2477 /* 2478 * Mark the interface down and cancel the watchdog timer. 2479 */ 2480 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2481 ifp->if_timer = 0; 2482 2483 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2484 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2485 printf("%s: sip_stop: no INTR bits set in dirty tx " 2486 "descriptors\n", sc->sc_dev.dv_xname); 2487 } 2488 2489 /* 2490 * sip_read_eeprom: 2491 * 2492 * Read data from the serial EEPROM. 2493 */ 2494 void 2495 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2496 u_int16_t *data) 2497 { 2498 bus_space_tag_t st = sc->sc_st; 2499 bus_space_handle_t sh = sc->sc_sh; 2500 u_int16_t reg; 2501 int i, x; 2502 2503 for (i = 0; i < wordcnt; i++) { 2504 /* Send CHIP SELECT. */ 2505 reg = EROMAR_EECS; 2506 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2507 2508 /* Shift in the READ opcode. */ 2509 for (x = 3; x > 0; x--) { 2510 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2511 reg |= EROMAR_EEDI; 2512 else 2513 reg &= ~EROMAR_EEDI; 2514 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2515 bus_space_write_4(st, sh, SIP_EROMAR, 2516 reg | EROMAR_EESK); 2517 delay(4); 2518 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2519 delay(4); 2520 } 2521 2522 /* Shift in address. */ 2523 for (x = 6; x > 0; x--) { 2524 if ((word + i) & (1 << (x - 1))) 2525 reg |= EROMAR_EEDI; 2526 else 2527 reg &= ~EROMAR_EEDI; 2528 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2529 bus_space_write_4(st, sh, SIP_EROMAR, 2530 reg | EROMAR_EESK); 2531 delay(4); 2532 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2533 delay(4); 2534 } 2535 2536 /* Shift out data. */ 2537 reg = EROMAR_EECS; 2538 data[i] = 0; 2539 for (x = 16; x > 0; x--) { 2540 bus_space_write_4(st, sh, SIP_EROMAR, 2541 reg | EROMAR_EESK); 2542 delay(4); 2543 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2544 data[i] |= (1 << (x - 1)); 2545 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2546 delay(4); 2547 } 2548 2549 /* Clear CHIP SELECT. */ 2550 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2551 delay(4); 2552 } 2553 } 2554 2555 /* 2556 * sip_add_rxbuf: 2557 * 2558 * Add a receive buffer to the indicated descriptor. 2559 */ 2560 int 2561 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2562 { 2563 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2564 struct mbuf *m; 2565 int error; 2566 2567 MGETHDR(m, M_DONTWAIT, MT_DATA); 2568 if (m == NULL) 2569 return (ENOBUFS); 2570 2571 MCLGET(m, M_DONTWAIT); 2572 if ((m->m_flags & M_EXT) == 0) { 2573 m_freem(m); 2574 return (ENOBUFS); 2575 } 2576 2577 #if defined(DP83820) 2578 m->m_len = SIP_RXBUF_LEN; 2579 #endif /* DP83820 */ 2580 2581 if (rxs->rxs_mbuf != NULL) 2582 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2583 2584 rxs->rxs_mbuf = m; 2585 2586 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2587 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2588 BUS_DMA_READ|BUS_DMA_NOWAIT); 2589 if (error) { 2590 printf("%s: can't load rx DMA map %d, error = %d\n", 2591 sc->sc_dev.dv_xname, idx, error); 2592 panic("sip_add_rxbuf"); /* XXX */ 2593 } 2594 2595 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2596 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2597 2598 SIP_INIT_RXDESC(sc, idx); 2599 2600 return (0); 2601 } 2602 2603 #if !defined(DP83820) 2604 /* 2605 * sip_sis900_set_filter: 2606 * 2607 * Set up the receive filter. 2608 */ 2609 void 2610 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2611 { 2612 bus_space_tag_t st = sc->sc_st; 2613 bus_space_handle_t sh = sc->sc_sh; 2614 struct ethercom *ec = &sc->sc_ethercom; 2615 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2616 struct ether_multi *enm; 2617 u_int8_t *cp; 2618 struct ether_multistep step; 2619 u_int32_t crc, mchash[16]; 2620 2621 /* 2622 * Initialize the prototype RFCR. 2623 */ 2624 sc->sc_rfcr = RFCR_RFEN; 2625 if (ifp->if_flags & IFF_BROADCAST) 2626 sc->sc_rfcr |= RFCR_AAB; 2627 if (ifp->if_flags & IFF_PROMISC) { 2628 sc->sc_rfcr |= RFCR_AAP; 2629 goto allmulti; 2630 } 2631 2632 /* 2633 * Set up the multicast address filter by passing all multicast 2634 * addresses through a CRC generator, and then using the high-order 2635 * 6 bits as an index into the 128 bit multicast hash table (only 2636 * the lower 16 bits of each 32 bit multicast hash register are 2637 * valid). The high order bits select the register, while the 2638 * rest of the bits select the bit within the register. 2639 */ 2640 2641 memset(mchash, 0, sizeof(mchash)); 2642 2643 ETHER_FIRST_MULTI(step, ec, enm); 2644 while (enm != NULL) { 2645 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2646 /* 2647 * We must listen to a range of multicast addresses. 2648 * For now, just accept all multicasts, rather than 2649 * trying to set only those filter bits needed to match 2650 * the range. (At this time, the only use of address 2651 * ranges is for IP multicast routing, for which the 2652 * range is big enough to require all bits set.) 2653 */ 2654 goto allmulti; 2655 } 2656 2657 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2658 2659 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2660 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2661 /* Just want the 8 most significant bits. */ 2662 crc >>= 24; 2663 } else { 2664 /* Just want the 7 most significant bits. */ 2665 crc >>= 25; 2666 } 2667 2668 /* Set the corresponding bit in the hash table. */ 2669 mchash[crc >> 4] |= 1 << (crc & 0xf); 2670 2671 ETHER_NEXT_MULTI(step, enm); 2672 } 2673 2674 ifp->if_flags &= ~IFF_ALLMULTI; 2675 goto setit; 2676 2677 allmulti: 2678 ifp->if_flags |= IFF_ALLMULTI; 2679 sc->sc_rfcr |= RFCR_AAM; 2680 2681 setit: 2682 #define FILTER_EMIT(addr, data) \ 2683 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2684 delay(1); \ 2685 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2686 delay(1) 2687 2688 /* 2689 * Disable receive filter, and program the node address. 2690 */ 2691 cp = LLADDR(ifp->if_sadl); 2692 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2693 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2694 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2695 2696 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2697 /* 2698 * Program the multicast hash table. 2699 */ 2700 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2701 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2702 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2703 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2704 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2705 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2706 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2707 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2708 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2709 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2710 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2711 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2712 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2713 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2714 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2715 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2716 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2717 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2718 } 2719 } 2720 #undef FILTER_EMIT 2721 2722 /* 2723 * Re-enable the receiver filter. 2724 */ 2725 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2726 } 2727 #endif /* ! DP83820 */ 2728 2729 /* 2730 * sip_dp83815_set_filter: 2731 * 2732 * Set up the receive filter. 2733 */ 2734 void 2735 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2736 { 2737 bus_space_tag_t st = sc->sc_st; 2738 bus_space_handle_t sh = sc->sc_sh; 2739 struct ethercom *ec = &sc->sc_ethercom; 2740 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2741 struct ether_multi *enm; 2742 u_int8_t *cp; 2743 struct ether_multistep step; 2744 u_int32_t crc, hash, slot, bit; 2745 #ifdef DP83820 2746 #define MCHASH_NWORDS 128 2747 #else 2748 #define MCHASH_NWORDS 32 2749 #endif /* DP83820 */ 2750 u_int16_t mchash[MCHASH_NWORDS]; 2751 int i; 2752 2753 /* 2754 * Initialize the prototype RFCR. 2755 * Enable the receive filter, and accept on 2756 * Perfect (destination address) Match 2757 * If IFF_BROADCAST, also accept all broadcast packets. 2758 * If IFF_PROMISC, accept all unicast packets (and later, set 2759 * IFF_ALLMULTI and accept all multicast, too). 2760 */ 2761 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2762 if (ifp->if_flags & IFF_BROADCAST) 2763 sc->sc_rfcr |= RFCR_AAB; 2764 if (ifp->if_flags & IFF_PROMISC) { 2765 sc->sc_rfcr |= RFCR_AAP; 2766 goto allmulti; 2767 } 2768 2769 #ifdef DP83820 2770 /* 2771 * Set up the DP83820 multicast address filter by passing all multicast 2772 * addresses through a CRC generator, and then using the high-order 2773 * 11 bits as an index into the 2048 bit multicast hash table. The 2774 * high-order 7 bits select the slot, while the low-order 4 bits 2775 * select the bit within the slot. Note that only the low 16-bits 2776 * of each filter word are used, and there are 128 filter words. 2777 */ 2778 #else 2779 /* 2780 * Set up the DP83815 multicast address filter by passing all multicast 2781 * addresses through a CRC generator, and then using the high-order 2782 * 9 bits as an index into the 512 bit multicast hash table. The 2783 * high-order 5 bits select the slot, while the low-order 4 bits 2784 * select the bit within the slot. Note that only the low 16-bits 2785 * of each filter word are used, and there are 32 filter words. 2786 */ 2787 #endif /* DP83820 */ 2788 2789 memset(mchash, 0, sizeof(mchash)); 2790 2791 ifp->if_flags &= ~IFF_ALLMULTI; 2792 ETHER_FIRST_MULTI(step, ec, enm); 2793 if (enm == NULL) 2794 goto setit; 2795 while (enm != NULL) { 2796 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2797 /* 2798 * We must listen to a range of multicast addresses. 2799 * For now, just accept all multicasts, rather than 2800 * trying to set only those filter bits needed to match 2801 * the range. (At this time, the only use of address 2802 * ranges is for IP multicast routing, for which the 2803 * range is big enough to require all bits set.) 2804 */ 2805 goto allmulti; 2806 } 2807 2808 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2809 2810 #ifdef DP83820 2811 /* Just want the 11 most significant bits. */ 2812 hash = crc >> 21; 2813 #else 2814 /* Just want the 9 most significant bits. */ 2815 hash = crc >> 23; 2816 #endif /* DP83820 */ 2817 2818 slot = hash >> 4; 2819 bit = hash & 0xf; 2820 2821 /* Set the corresponding bit in the hash table. */ 2822 mchash[slot] |= 1 << bit; 2823 2824 ETHER_NEXT_MULTI(step, enm); 2825 } 2826 sc->sc_rfcr |= RFCR_MHEN; 2827 goto setit; 2828 2829 allmulti: 2830 ifp->if_flags |= IFF_ALLMULTI; 2831 sc->sc_rfcr |= RFCR_AAM; 2832 2833 setit: 2834 #define FILTER_EMIT(addr, data) \ 2835 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2836 delay(1); \ 2837 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2838 delay(1) 2839 2840 /* 2841 * Disable receive filter, and program the node address. 2842 */ 2843 cp = LLADDR(ifp->if_sadl); 2844 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 2845 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 2846 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 2847 2848 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2849 /* 2850 * Program the multicast hash table. 2851 */ 2852 for (i = 0; i < MCHASH_NWORDS; i++) { 2853 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 2854 mchash[i]); 2855 } 2856 } 2857 #undef FILTER_EMIT 2858 #undef MCHASH_NWORDS 2859 2860 /* 2861 * Re-enable the receiver filter. 2862 */ 2863 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2864 } 2865 2866 #if defined(DP83820) 2867 /* 2868 * sip_dp83820_mii_readreg: [mii interface function] 2869 * 2870 * Read a PHY register on the MII of the DP83820. 2871 */ 2872 int 2873 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 2874 { 2875 struct sip_softc *sc = (void *) self; 2876 2877 if (sc->sc_cfg & CFG_TBI_EN) { 2878 bus_addr_t tbireg; 2879 int rv; 2880 2881 if (phy != 0) 2882 return (0); 2883 2884 switch (reg) { 2885 case MII_BMCR: tbireg = SIP_TBICR; break; 2886 case MII_BMSR: tbireg = SIP_TBISR; break; 2887 case MII_ANAR: tbireg = SIP_TANAR; break; 2888 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 2889 case MII_ANER: tbireg = SIP_TANER; break; 2890 case MII_EXTSR: 2891 /* 2892 * Don't even bother reading the TESR register. 2893 * The manual documents that the device has 2894 * 1000baseX full/half capability, but the 2895 * register itself seems read back 0 on some 2896 * boards. Just hard-code the result. 2897 */ 2898 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 2899 2900 default: 2901 return (0); 2902 } 2903 2904 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 2905 if (tbireg == SIP_TBISR) { 2906 /* LINK and ACOMP are switched! */ 2907 int val = rv; 2908 2909 rv = 0; 2910 if (val & TBISR_MR_LINK_STATUS) 2911 rv |= BMSR_LINK; 2912 if (val & TBISR_MR_AN_COMPLETE) 2913 rv |= BMSR_ACOMP; 2914 2915 /* 2916 * The manual claims this register reads back 0 2917 * on hard and soft reset. But we want to let 2918 * the gentbi driver know that we support auto- 2919 * negotiation, so hard-code this bit in the 2920 * result. 2921 */ 2922 rv |= BMSR_ANEG | BMSR_EXTSTAT; 2923 } 2924 2925 return (rv); 2926 } 2927 2928 return (mii_bitbang_readreg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2929 phy, reg)); 2930 } 2931 2932 /* 2933 * sip_dp83820_mii_writereg: [mii interface function] 2934 * 2935 * Write a PHY register on the MII of the DP83820. 2936 */ 2937 void 2938 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 2939 { 2940 struct sip_softc *sc = (void *) self; 2941 2942 if (sc->sc_cfg & CFG_TBI_EN) { 2943 bus_addr_t tbireg; 2944 2945 if (phy != 0) 2946 return; 2947 2948 switch (reg) { 2949 case MII_BMCR: tbireg = SIP_TBICR; break; 2950 case MII_ANAR: tbireg = SIP_TANAR; break; 2951 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 2952 default: 2953 return; 2954 } 2955 2956 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 2957 return; 2958 } 2959 2960 mii_bitbang_writereg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2961 phy, reg, val); 2962 } 2963 2964 /* 2965 * sip_dp83815_mii_statchg: [mii interface function] 2966 * 2967 * Callback from MII layer when media changes. 2968 */ 2969 void 2970 SIP_DECL(dp83820_mii_statchg)(struct device *self) 2971 { 2972 struct sip_softc *sc = (struct sip_softc *) self; 2973 u_int32_t cfg; 2974 2975 /* 2976 * Update TXCFG for full-duplex operation. 2977 */ 2978 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2979 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2980 else 2981 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2982 2983 /* 2984 * Update RXCFG for full-duplex or loopback. 2985 */ 2986 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2987 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2988 sc->sc_rxcfg |= RXCFG_ATX; 2989 else 2990 sc->sc_rxcfg &= ~RXCFG_ATX; 2991 2992 /* 2993 * Update CFG for MII/GMII. 2994 */ 2995 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2996 cfg = sc->sc_cfg | CFG_MODE_1000; 2997 else 2998 cfg = sc->sc_cfg; 2999 3000 /* 3001 * XXX 802.3x flow control. 3002 */ 3003 3004 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3005 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3006 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3007 } 3008 3009 /* 3010 * sip_dp83820_mii_bitbang_read: [mii bit-bang interface function] 3011 * 3012 * Read the MII serial port for the MII bit-bang module. 3013 */ 3014 u_int32_t 3015 SIP_DECL(dp83820_mii_bitbang_read)(struct device *self) 3016 { 3017 struct sip_softc *sc = (void *) self; 3018 3019 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3020 } 3021 3022 /* 3023 * sip_dp83820_mii_bitbang_write: [mii big-bang interface function] 3024 * 3025 * Write the MII serial port for the MII bit-bang module. 3026 */ 3027 void 3028 SIP_DECL(dp83820_mii_bitbang_write)(struct device *self, u_int32_t val) 3029 { 3030 struct sip_softc *sc = (void *) self; 3031 3032 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3033 } 3034 #else /* ! DP83820 */ 3035 /* 3036 * sip_sis900_mii_readreg: [mii interface function] 3037 * 3038 * Read a PHY register on the MII. 3039 */ 3040 int 3041 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 3042 { 3043 struct sip_softc *sc = (struct sip_softc *) self; 3044 u_int32_t enphy; 3045 3046 /* 3047 * The SiS 900 has only an internal PHY on the MII. Only allow 3048 * MII address 0. 3049 */ 3050 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 3051 sc->sc_rev < SIS_REV_635 && phy != 0) 3052 return (0); 3053 3054 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3055 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3056 ENPHY_RWCMD | ENPHY_ACCESS); 3057 do { 3058 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3059 } while (enphy & ENPHY_ACCESS); 3060 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3061 } 3062 3063 /* 3064 * sip_sis900_mii_writereg: [mii interface function] 3065 * 3066 * Write a PHY register on the MII. 3067 */ 3068 void 3069 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 3070 { 3071 struct sip_softc *sc = (struct sip_softc *) self; 3072 u_int32_t enphy; 3073 3074 /* 3075 * The SiS 900 has only an internal PHY on the MII. Only allow 3076 * MII address 0. 3077 */ 3078 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 3079 sc->sc_rev < SIS_REV_635 && phy != 0) 3080 return; 3081 3082 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3083 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3084 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3085 do { 3086 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3087 } while (enphy & ENPHY_ACCESS); 3088 } 3089 3090 /* 3091 * sip_sis900_mii_statchg: [mii interface function] 3092 * 3093 * Callback from MII layer when media changes. 3094 */ 3095 void 3096 SIP_DECL(sis900_mii_statchg)(struct device *self) 3097 { 3098 struct sip_softc *sc = (struct sip_softc *) self; 3099 u_int32_t flowctl; 3100 3101 /* 3102 * Update TXCFG for full-duplex operation. 3103 */ 3104 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3105 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3106 else 3107 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3108 3109 /* 3110 * Update RXCFG for full-duplex or loopback. 3111 */ 3112 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3113 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3114 sc->sc_rxcfg |= RXCFG_ATX; 3115 else 3116 sc->sc_rxcfg &= ~RXCFG_ATX; 3117 3118 /* 3119 * Update IMR for use of 802.3x flow control. 3120 */ 3121 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 3122 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3123 flowctl = FLOWCTL_FLOWEN; 3124 } else { 3125 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3126 flowctl = 0; 3127 } 3128 3129 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3130 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3131 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3132 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3133 } 3134 3135 /* 3136 * sip_dp83815_mii_readreg: [mii interface function] 3137 * 3138 * Read a PHY register on the MII. 3139 */ 3140 int 3141 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 3142 { 3143 struct sip_softc *sc = (struct sip_softc *) self; 3144 u_int32_t val; 3145 3146 /* 3147 * The DP83815 only has an internal PHY. Only allow 3148 * MII address 0. 3149 */ 3150 if (phy != 0) 3151 return (0); 3152 3153 /* 3154 * Apparently, after a reset, the DP83815 can take a while 3155 * to respond. During this recovery period, the BMSR returns 3156 * a value of 0. Catch this -- it's not supposed to happen 3157 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3158 * PHY to come back to life. 3159 * 3160 * This works out because the BMSR is the first register 3161 * read during the PHY probe process. 3162 */ 3163 do { 3164 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3165 } while (reg == MII_BMSR && val == 0); 3166 3167 return (val & 0xffff); 3168 } 3169 3170 /* 3171 * sip_dp83815_mii_writereg: [mii interface function] 3172 * 3173 * Write a PHY register to the MII. 3174 */ 3175 void 3176 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3177 { 3178 struct sip_softc *sc = (struct sip_softc *) self; 3179 3180 /* 3181 * The DP83815 only has an internal PHY. Only allow 3182 * MII address 0. 3183 */ 3184 if (phy != 0) 3185 return; 3186 3187 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3188 } 3189 3190 /* 3191 * sip_dp83815_mii_statchg: [mii interface function] 3192 * 3193 * Callback from MII layer when media changes. 3194 */ 3195 void 3196 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3197 { 3198 struct sip_softc *sc = (struct sip_softc *) self; 3199 3200 /* 3201 * Update TXCFG for full-duplex operation. 3202 */ 3203 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3204 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3205 else 3206 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3207 3208 /* 3209 * Update RXCFG for full-duplex or loopback. 3210 */ 3211 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3212 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3213 sc->sc_rxcfg |= RXCFG_ATX; 3214 else 3215 sc->sc_rxcfg &= ~RXCFG_ATX; 3216 3217 /* 3218 * XXX 802.3x flow control. 3219 */ 3220 3221 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3222 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3223 } 3224 #endif /* DP83820 */ 3225 3226 #if defined(DP83820) 3227 void 3228 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3229 const struct pci_attach_args *pa, u_int8_t *enaddr) 3230 { 3231 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3232 u_int8_t cksum, *e, match; 3233 int i; 3234 3235 /* 3236 * EEPROM data format for the DP83820 can be found in 3237 * the DP83820 manual, section 4.2.4. 3238 */ 3239 3240 SIP_DECL(read_eeprom)(sc, 0, 3241 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3242 3243 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3244 match = ~(match - 1); 3245 3246 cksum = 0x55; 3247 e = (u_int8_t *) eeprom_data; 3248 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3249 cksum += *e++; 3250 3251 if (cksum != match) 3252 printf("%s: Checksum (%x) mismatch (%x)", 3253 sc->sc_dev.dv_xname, cksum, match); 3254 3255 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3256 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3257 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3258 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3259 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3260 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3261 } 3262 #else /* ! DP83820 */ 3263 void 3264 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3265 const struct pci_attach_args *pa, u_int8_t *enaddr) 3266 { 3267 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3268 3269 switch (sc->sc_rev) { 3270 case SIS_REV_630S: 3271 case SIS_REV_630E: 3272 case SIS_REV_630EA1: 3273 case SIS_REV_630ET: 3274 case SIS_REV_635: 3275 /* 3276 * The MAC address for the on-board Ethernet of 3277 * the SiS 630 chipset is in the NVRAM. Kick 3278 * the chip into re-loading it from NVRAM, and 3279 * read the MAC address out of the filter registers. 3280 */ 3281 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3282 3283 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3284 RFCR_RFADDR_NODE0); 3285 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3286 0xffff; 3287 3288 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3289 RFCR_RFADDR_NODE2); 3290 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3291 0xffff; 3292 3293 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3294 RFCR_RFADDR_NODE4); 3295 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3296 0xffff; 3297 break; 3298 3299 default: 3300 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3301 sizeof(myea) / sizeof(myea[0]), myea); 3302 } 3303 3304 enaddr[0] = myea[0] & 0xff; 3305 enaddr[1] = myea[0] >> 8; 3306 enaddr[2] = myea[1] & 0xff; 3307 enaddr[3] = myea[1] >> 8; 3308 enaddr[4] = myea[2] & 0xff; 3309 enaddr[5] = myea[2] >> 8; 3310 } 3311 3312 /* Table and macro to bit-reverse an octet. */ 3313 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3314 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3315 3316 void 3317 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3318 const struct pci_attach_args *pa, u_int8_t *enaddr) 3319 { 3320 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3321 u_int8_t cksum, *e, match; 3322 int i; 3323 3324 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3325 sizeof(eeprom_data[0]), eeprom_data); 3326 3327 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3328 match = ~(match - 1); 3329 3330 cksum = 0x55; 3331 e = (u_int8_t *) eeprom_data; 3332 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3333 cksum += *e++; 3334 } 3335 if (cksum != match) { 3336 printf("%s: Checksum (%x) mismatch (%x)", 3337 sc->sc_dev.dv_xname, cksum, match); 3338 } 3339 3340 /* 3341 * Unrolled because it makes slightly more sense this way. 3342 * The DP83815 stores the MAC address in bit 0 of word 6 3343 * through bit 15 of word 8. 3344 */ 3345 ea = &eeprom_data[6]; 3346 enaddr[0] = ((*ea & 0x1) << 7); 3347 ea++; 3348 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3349 enaddr[1] = ((*ea & 0x1FE) >> 1); 3350 enaddr[2] = ((*ea & 0x1) << 7); 3351 ea++; 3352 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3353 enaddr[3] = ((*ea & 0x1FE) >> 1); 3354 enaddr[4] = ((*ea & 0x1) << 7); 3355 ea++; 3356 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3357 enaddr[5] = ((*ea & 0x1FE) >> 1); 3358 3359 /* 3360 * In case that's not weird enough, we also need to reverse 3361 * the bits in each byte. This all actually makes more sense 3362 * if you think about the EEPROM storage as an array of bits 3363 * being shifted into bytes, but that's not how we're looking 3364 * at it here... 3365 */ 3366 for (i = 0; i < 6 ;i++) 3367 enaddr[i] = bbr(enaddr[i]); 3368 } 3369 #endif /* DP83820 */ 3370 3371 /* 3372 * sip_mediastatus: [ifmedia interface function] 3373 * 3374 * Get the current interface media status. 3375 */ 3376 void 3377 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3378 { 3379 struct sip_softc *sc = ifp->if_softc; 3380 3381 mii_pollstat(&sc->sc_mii); 3382 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3383 ifmr->ifm_active = sc->sc_mii.mii_media_active; 3384 } 3385 3386 /* 3387 * sip_mediachange: [ifmedia interface function] 3388 * 3389 * Set hardware to newly-selected media. 3390 */ 3391 int 3392 SIP_DECL(mediachange)(struct ifnet *ifp) 3393 { 3394 struct sip_softc *sc = ifp->if_softc; 3395 3396 if (ifp->if_flags & IFF_UP) 3397 mii_mediachg(&sc->sc_mii); 3398 return (0); 3399 } 3400
Indexes created Tue Sep 30 11:09:46 GMT 2025