if_sip.c revision 1.41
1 /* $NetBSD: if_sip.c,v 1.41 2001/07/19 16:36:14 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Support the 10-bit interface on the DP83820 (for fiber). 80 * 81 * - Reduce the interrupt load. 82 */ 83 84 #include "bpfilter.h" 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/callout.h> 89 #include <sys/mbuf.h> 90 #include <sys/malloc.h> 91 #include <sys/kernel.h> 92 #include <sys/socket.h> 93 #include <sys/ioctl.h> 94 #include <sys/errno.h> 95 #include <sys/device.h> 96 #include <sys/queue.h> 97 98 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 99 100 #include <net/if.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 #include <net/if_ether.h> 104 105 #if NBPFILTER > 0 106 #include <net/bpf.h> 107 #endif 108 109 #include <machine/bus.h> 110 #include <machine/intr.h> 111 #include <machine/endian.h> 112 113 #include <dev/mii/mii.h> 114 #include <dev/mii/miivar.h> 115 #ifdef DP83820 116 #include <dev/mii/mii_bitbang.h> 117 #endif /* DP83820 */ 118 119 #include <dev/pci/pcireg.h> 120 #include <dev/pci/pcivar.h> 121 #include <dev/pci/pcidevs.h> 122 123 #include <dev/pci/if_sipreg.h> 124 125 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 126 #define SIP_DECL(x) __CONCAT(gsip_,x) 127 #else /* SiS900 and DP83815 */ 128 #define SIP_DECL(x) __CONCAT(sip_,x) 129 #endif 130 131 #define SIP_STR(x) __STRING(SIP_DECL(x)) 132 133 /* 134 * Transmit descriptor list size. This is arbitrary, but allocate 135 * enough descriptors for 128 pending transmissions, and 8 segments 136 * per packet. This MUST work out to a power of 2. 137 */ 138 #define SIP_NTXSEGS 8 139 140 #define SIP_TXQUEUELEN 256 141 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS) 142 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 143 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 144 145 /* 146 * Receive descriptor list size. We have one Rx buffer per incoming 147 * packet, so this logic is a little simpler. 148 * 149 * Actually, on the DP83820, we allow the packet to consume more than 150 * one buffer, in order to support jumbo Ethernet frames. In that 151 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 152 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 153 * so we'd better be quick about handling receive interrupts. 154 */ 155 #if defined(DP83820) 156 #define SIP_NRXDESC 256 157 #else 158 #define SIP_NRXDESC 128 159 #endif /* DP83820 */ 160 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 161 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 162 163 /* 164 * Control structures are DMA'd to the SiS900 chip. We allocate them in 165 * a single clump that maps to a single DMA segment to make several things 166 * easier. 167 */ 168 struct sip_control_data { 169 /* 170 * The transmit descriptors. 171 */ 172 struct sip_desc scd_txdescs[SIP_NTXDESC]; 173 174 /* 175 * The receive descriptors. 176 */ 177 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 178 }; 179 180 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 181 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 182 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 183 184 /* 185 * Software state for transmit jobs. 186 */ 187 struct sip_txsoft { 188 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 189 bus_dmamap_t txs_dmamap; /* our DMA map */ 190 int txs_firstdesc; /* first descriptor in packet */ 191 int txs_lastdesc; /* last descriptor in packet */ 192 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 193 }; 194 195 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 196 197 /* 198 * Software state for receive jobs. 199 */ 200 struct sip_rxsoft { 201 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 202 bus_dmamap_t rxs_dmamap; /* our DMA map */ 203 }; 204 205 /* 206 * Software state per device. 207 */ 208 struct sip_softc { 209 struct device sc_dev; /* generic device information */ 210 bus_space_tag_t sc_st; /* bus space tag */ 211 bus_space_handle_t sc_sh; /* bus space handle */ 212 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 213 struct ethercom sc_ethercom; /* ethernet common data */ 214 void *sc_sdhook; /* shutdown hook */ 215 216 const struct sip_product *sc_model; /* which model are we? */ 217 218 void *sc_ih; /* interrupt cookie */ 219 220 struct mii_data sc_mii; /* MII/media information */ 221 222 struct callout sc_tick_ch; /* tick callout */ 223 224 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 225 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 226 227 /* 228 * Software state for transmit and receive descriptors. 229 */ 230 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 231 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 232 233 /* 234 * Control data structures. 235 */ 236 struct sip_control_data *sc_control_data; 237 #define sc_txdescs sc_control_data->scd_txdescs 238 #define sc_rxdescs sc_control_data->scd_rxdescs 239 240 #ifdef SIP_EVENT_COUNTERS 241 /* 242 * Event counters. 243 */ 244 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 245 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 246 struct evcnt sc_ev_txintr; /* Tx interrupts */ 247 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 248 #ifdef DP83820 249 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 250 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 251 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 252 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 253 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 254 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 255 #endif /* DP83820 */ 256 #endif /* SIP_EVENT_COUNTERS */ 257 258 u_int32_t sc_txcfg; /* prototype TXCFG register */ 259 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 260 u_int32_t sc_imr; /* prototype IMR register */ 261 u_int32_t sc_rfcr; /* prototype RFCR register */ 262 263 u_int32_t sc_cfg; /* prototype CFG register */ 264 265 #ifdef DP83820 266 u_int32_t sc_gpior; /* prototype GPIOR register */ 267 #endif /* DP83820 */ 268 269 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 270 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 271 272 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 273 274 int sc_flags; /* misc. flags; see below */ 275 276 int sc_txfree; /* number of free Tx descriptors */ 277 int sc_txnext; /* next ready Tx descriptor */ 278 279 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 280 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 281 282 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 283 #if defined(DP83820) 284 int sc_rxdiscard; 285 int sc_rxlen; 286 struct mbuf *sc_rxhead; 287 struct mbuf *sc_rxtail; 288 struct mbuf **sc_rxtailp; 289 #endif /* DP83820 */ 290 }; 291 292 /* sc_flags */ 293 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 294 295 #ifdef DP83820 296 #define SIP_RXCHAIN_RESET(sc) \ 297 do { \ 298 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 299 *(sc)->sc_rxtailp = NULL; \ 300 (sc)->sc_rxlen = 0; \ 301 } while (/*CONSTCOND*/0) 302 303 #define SIP_RXCHAIN_LINK(sc, m) \ 304 do { \ 305 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 306 (sc)->sc_rxtailp = &(m)->m_next; \ 307 } while (/*CONSTCOND*/0) 308 #endif /* DP83820 */ 309 310 #ifdef SIP_EVENT_COUNTERS 311 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 312 #else 313 #define SIP_EVCNT_INCR(ev) /* nothing */ 314 #endif 315 316 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 317 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 318 319 #define SIP_CDTXSYNC(sc, x, n, ops) \ 320 do { \ 321 int __x, __n; \ 322 \ 323 __x = (x); \ 324 __n = (n); \ 325 \ 326 /* If it will wrap around, sync to the end of the ring. */ \ 327 if ((__x + __n) > SIP_NTXDESC) { \ 328 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 329 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 330 (SIP_NTXDESC - __x), (ops)); \ 331 __n -= (SIP_NTXDESC - __x); \ 332 __x = 0; \ 333 } \ 334 \ 335 /* Now sync whatever is left. */ \ 336 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 337 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 338 } while (0) 339 340 #define SIP_CDRXSYNC(sc, x, ops) \ 341 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 342 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 343 344 #ifdef DP83820 345 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 346 #define SIP_RXBUF_LEN (MCLBYTES - 4) 347 #else 348 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 349 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 350 #endif 351 #define SIP_INIT_RXDESC(sc, x) \ 352 do { \ 353 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 354 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 355 \ 356 __sipd->sipd_link = \ 357 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 358 __sipd->sipd_bufptr = \ 359 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 360 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 361 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 362 SIP_INIT_RXDESC_EXTSTS \ 363 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 364 } while (0) 365 366 #define SIP_TIMEOUT 1000 367 368 void SIP_DECL(start)(struct ifnet *); 369 void SIP_DECL(watchdog)(struct ifnet *); 370 int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 371 int SIP_DECL(init)(struct ifnet *); 372 void SIP_DECL(stop)(struct ifnet *, int); 373 374 void SIP_DECL(shutdown)(void *); 375 376 void SIP_DECL(reset)(struct sip_softc *); 377 void SIP_DECL(rxdrain)(struct sip_softc *); 378 int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 379 void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, u_int16_t *); 380 void SIP_DECL(tick)(void *); 381 382 #if !defined(DP83820) 383 void SIP_DECL(sis900_set_filter)(struct sip_softc *); 384 #endif /* ! DP83820 */ 385 void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 386 387 #if defined(DP83820) 388 void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, u_int8_t *); 389 #else 390 void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, u_int8_t *); 391 void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, u_int8_t *); 392 #endif /* DP83820 */ 393 394 int SIP_DECL(intr)(void *); 395 void SIP_DECL(txintr)(struct sip_softc *); 396 void SIP_DECL(rxintr)(struct sip_softc *); 397 398 #if defined(DP83820) 399 int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 400 void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 401 void SIP_DECL(dp83820_mii_statchg)(struct device *); 402 #else 403 int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 404 void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 405 void SIP_DECL(sis900_mii_statchg)(struct device *); 406 407 int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 408 void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 409 void SIP_DECL(dp83815_mii_statchg)(struct device *); 410 #endif /* DP83820 */ 411 412 int SIP_DECL(mediachange)(struct ifnet *); 413 void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 414 415 int SIP_DECL(match)(struct device *, struct cfdata *, void *); 416 void SIP_DECL(attach)(struct device *, struct device *, void *); 417 418 int SIP_DECL(copy_small) = 0; 419 420 struct cfattach SIP_DECL(ca) = { 421 sizeof(struct sip_softc), SIP_DECL(match), SIP_DECL(attach), 422 }; 423 424 /* 425 * Descriptions of the variants of the SiS900. 426 */ 427 struct sip_variant { 428 int (*sipv_mii_readreg)(struct device *, int, int); 429 void (*sipv_mii_writereg)(struct device *, int, int, int); 430 void (*sipv_mii_statchg)(struct device *); 431 void (*sipv_set_filter)(struct sip_softc *); 432 void (*sipv_read_macaddr)(struct sip_softc *, u_int8_t *); 433 }; 434 435 #if defined(DP83820) 436 u_int32_t SIP_DECL(dp83820_mii_bitbang_read)(struct device *); 437 void SIP_DECL(dp83820_mii_bitbang_write)(struct device *, u_int32_t); 438 439 const struct mii_bitbang_ops SIP_DECL(dp83820_mii_bitbang_ops) = { 440 SIP_DECL(dp83820_mii_bitbang_read), 441 SIP_DECL(dp83820_mii_bitbang_write), 442 { 443 EROMAR_MDIO, /* MII_BIT_MDO */ 444 EROMAR_MDIO, /* MII_BIT_MDI */ 445 EROMAR_MDC, /* MII_BIT_MDC */ 446 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 447 0, /* MII_BIT_DIR_PHY_HOST */ 448 } 449 }; 450 #endif /* DP83820 */ 451 452 #if defined(DP83820) 453 const struct sip_variant SIP_DECL(variant_dp83820) = { 454 SIP_DECL(dp83820_mii_readreg), 455 SIP_DECL(dp83820_mii_writereg), 456 SIP_DECL(dp83820_mii_statchg), 457 SIP_DECL(dp83815_set_filter), 458 SIP_DECL(dp83820_read_macaddr), 459 }; 460 #else 461 const struct sip_variant SIP_DECL(variant_sis900) = { 462 SIP_DECL(sis900_mii_readreg), 463 SIP_DECL(sis900_mii_writereg), 464 SIP_DECL(sis900_mii_statchg), 465 SIP_DECL(sis900_set_filter), 466 SIP_DECL(sis900_read_macaddr), 467 }; 468 469 const struct sip_variant SIP_DECL(variant_dp83815) = { 470 SIP_DECL(dp83815_mii_readreg), 471 SIP_DECL(dp83815_mii_writereg), 472 SIP_DECL(dp83815_mii_statchg), 473 SIP_DECL(dp83815_set_filter), 474 SIP_DECL(dp83815_read_macaddr), 475 }; 476 #endif /* DP83820 */ 477 478 /* 479 * Devices supported by this driver. 480 */ 481 const struct sip_product { 482 pci_vendor_id_t sip_vendor; 483 pci_product_id_t sip_product; 484 const char *sip_name; 485 const struct sip_variant *sip_variant; 486 } SIP_DECL(products)[] = { 487 #if defined(DP83820) 488 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 489 "NatSemi DP83820 Gigabit Ethernet", 490 &SIP_DECL(variant_dp83820) }, 491 #else 492 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 493 "SiS 900 10/100 Ethernet", 494 &SIP_DECL(variant_sis900) }, 495 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 496 "SiS 7016 10/100 Ethernet", 497 &SIP_DECL(variant_sis900) }, 498 499 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 500 "NatSemi DP83815 10/100 Ethernet", 501 &SIP_DECL(variant_dp83815) }, 502 #endif /* DP83820 */ 503 504 { 0, 0, 505 NULL, 506 NULL }, 507 }; 508 509 static const struct sip_product * 510 SIP_DECL(lookup)(const struct pci_attach_args *pa) 511 { 512 const struct sip_product *sip; 513 514 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 515 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 516 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 517 return (sip); 518 } 519 return (NULL); 520 } 521 522 int 523 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 524 { 525 struct pci_attach_args *pa = aux; 526 527 if (SIP_DECL(lookup)(pa) != NULL) 528 return (1); 529 530 return (0); 531 } 532 533 void 534 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 535 { 536 struct sip_softc *sc = (struct sip_softc *) self; 537 struct pci_attach_args *pa = aux; 538 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 539 pci_chipset_tag_t pc = pa->pa_pc; 540 pci_intr_handle_t ih; 541 const char *intrstr = NULL; 542 bus_space_tag_t iot, memt; 543 bus_space_handle_t ioh, memh; 544 bus_dma_segment_t seg; 545 int ioh_valid, memh_valid; 546 int i, rseg, error; 547 const struct sip_product *sip; 548 pcireg_t pmode; 549 u_int8_t enaddr[ETHER_ADDR_LEN]; 550 int pmreg; 551 #ifdef DP83820 552 pcireg_t memtype; 553 u_int32_t reg; 554 #endif /* DP83820 */ 555 556 callout_init(&sc->sc_tick_ch); 557 558 sip = SIP_DECL(lookup)(pa); 559 if (sip == NULL) { 560 printf("\n"); 561 panic(SIP_STR(attach) ": impossible"); 562 } 563 564 printf(": %s\n", sip->sip_name); 565 566 sc->sc_model = sip; 567 568 /* 569 * Map the device. 570 */ 571 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 572 PCI_MAPREG_TYPE_IO, 0, 573 &iot, &ioh, NULL, NULL) == 0); 574 #ifdef DP83820 575 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 576 switch (memtype) { 577 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 578 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 579 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 580 memtype, 0, &memt, &memh, NULL, NULL) == 0); 581 break; 582 default: 583 memh_valid = 0; 584 } 585 #else 586 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 587 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 588 &memt, &memh, NULL, NULL) == 0); 589 #endif /* DP83820 */ 590 591 if (memh_valid) { 592 sc->sc_st = memt; 593 sc->sc_sh = memh; 594 } else if (ioh_valid) { 595 sc->sc_st = iot; 596 sc->sc_sh = ioh; 597 } else { 598 printf("%s: unable to map device registers\n", 599 sc->sc_dev.dv_xname); 600 return; 601 } 602 603 sc->sc_dmat = pa->pa_dmat; 604 605 /* Enable bus mastering. */ 606 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 607 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 608 PCI_COMMAND_MASTER_ENABLE); 609 610 /* Get it out of power save mode if needed. */ 611 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 612 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 613 if (pmode == 3) { 614 /* 615 * The card has lost all configuration data in 616 * this state, so punt. 617 */ 618 printf("%s: unable to wake up from power state D3\n", 619 sc->sc_dev.dv_xname); 620 return; 621 } 622 if (pmode != 0) { 623 printf("%s: waking up from power state D%d\n", 624 sc->sc_dev.dv_xname, pmode); 625 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 626 } 627 } 628 629 /* 630 * Map and establish our interrupt. 631 */ 632 if (pci_intr_map(pa, &ih)) { 633 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 634 return; 635 } 636 intrstr = pci_intr_string(pc, ih); 637 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 638 if (sc->sc_ih == NULL) { 639 printf("%s: unable to establish interrupt", 640 sc->sc_dev.dv_xname); 641 if (intrstr != NULL) 642 printf(" at %s", intrstr); 643 printf("\n"); 644 return; 645 } 646 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 647 648 SIMPLEQ_INIT(&sc->sc_txfreeq); 649 SIMPLEQ_INIT(&sc->sc_txdirtyq); 650 651 /* 652 * Allocate the control data structures, and create and load the 653 * DMA map for it. 654 */ 655 if ((error = bus_dmamem_alloc(sc->sc_dmat, 656 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 657 0)) != 0) { 658 printf("%s: unable to allocate control data, error = %d\n", 659 sc->sc_dev.dv_xname, error); 660 goto fail_0; 661 } 662 663 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 664 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 665 BUS_DMA_COHERENT)) != 0) { 666 printf("%s: unable to map control data, error = %d\n", 667 sc->sc_dev.dv_xname, error); 668 goto fail_1; 669 } 670 671 if ((error = bus_dmamap_create(sc->sc_dmat, 672 sizeof(struct sip_control_data), 1, 673 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 674 printf("%s: unable to create control data DMA map, " 675 "error = %d\n", sc->sc_dev.dv_xname, error); 676 goto fail_2; 677 } 678 679 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 680 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 681 0)) != 0) { 682 printf("%s: unable to load control data DMA map, error = %d\n", 683 sc->sc_dev.dv_xname, error); 684 goto fail_3; 685 } 686 687 /* 688 * Create the transmit buffer DMA maps. 689 */ 690 for (i = 0; i < SIP_TXQUEUELEN; i++) { 691 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 692 SIP_NTXSEGS, MCLBYTES, 0, 0, 693 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 694 printf("%s: unable to create tx DMA map %d, " 695 "error = %d\n", sc->sc_dev.dv_xname, i, error); 696 goto fail_4; 697 } 698 } 699 700 /* 701 * Create the receive buffer DMA maps. 702 */ 703 for (i = 0; i < SIP_NRXDESC; i++) { 704 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 705 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 706 printf("%s: unable to create rx DMA map %d, " 707 "error = %d\n", sc->sc_dev.dv_xname, i, error); 708 goto fail_5; 709 } 710 sc->sc_rxsoft[i].rxs_mbuf = NULL; 711 } 712 713 /* 714 * Reset the chip to a known state. 715 */ 716 SIP_DECL(reset)(sc); 717 718 /* 719 * Read the Ethernet address from the EEPROM. This might 720 * also fetch other stuff from the EEPROM and stash it 721 * in the softc. 722 */ 723 sc->sc_cfg = 0; 724 (*sip->sip_variant->sipv_read_macaddr)(sc, enaddr); 725 726 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 727 ether_sprintf(enaddr)); 728 729 /* 730 * Initialize the configuration register: aggressive PCI 731 * bus request algorithm, default backoff, default OW timer, 732 * default parity error detection. 733 * 734 * NOTE: "Big endian mode" is useless on the SiS900 and 735 * friends -- it affects packet data, not descriptors. 736 */ 737 #ifdef DP83820 738 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 739 if (reg & CFG_PCI64_DET) { 740 printf("%s: 64-bit PCI slot detected\n", sc->sc_dev.dv_xname); 741 /* 742 * XXX Need some PCI flags indicating support for 743 * XXX 64-bit addressing (SAC or DAC) and 64-bit 744 * XXX data path. 745 */ 746 } 747 if (sc->sc_cfg & (CFG_TBI_EN|CFG_EXT_125)) { 748 const char *sep = ""; 749 printf("%s: using ", sc->sc_dev.dv_xname); 750 if (sc->sc_cfg & CFG_EXT_125) { 751 printf("%s125MHz clock", sep); 752 sep = ", "; 753 } 754 if (sc->sc_cfg & CFG_TBI_EN) { 755 printf("%sten-bit interface", sep); 756 sep = ", "; 757 } 758 printf("\n"); 759 } 760 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0) 761 sc->sc_cfg |= CFG_MRM_DIS; 762 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 763 sc->sc_cfg |= CFG_MWI_DIS; 764 765 /* 766 * Use the extended descriptor format on the DP83820. This 767 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 768 * checksumming. 769 */ 770 sc->sc_cfg |= CFG_EXTSTS_EN; 771 #endif /* DP83820 */ 772 773 /* 774 * Initialize our media structures and probe the MII. 775 */ 776 sc->sc_mii.mii_ifp = ifp; 777 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 778 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 779 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 780 ifmedia_init(&sc->sc_mii.mii_media, 0, SIP_DECL(mediachange), 781 SIP_DECL(mediastatus)); 782 #ifdef DP83820 783 if (sc->sc_cfg & CFG_TBI_EN) { 784 /* Using ten-bit interface. */ 785 printf("%s: TBI -- FIXME\n", sc->sc_dev.dv_xname); 786 } else { 787 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 788 MII_OFFSET_ANY, 0); 789 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 790 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 791 0, NULL); 792 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 793 } else 794 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 795 } 796 #else 797 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 798 MII_OFFSET_ANY, 0); 799 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 800 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 801 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 802 } else 803 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 804 #endif /* DP83820 */ 805 806 ifp = &sc->sc_ethercom.ec_if; 807 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 808 ifp->if_softc = sc; 809 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 810 ifp->if_ioctl = SIP_DECL(ioctl); 811 ifp->if_start = SIP_DECL(start); 812 ifp->if_watchdog = SIP_DECL(watchdog); 813 ifp->if_init = SIP_DECL(init); 814 ifp->if_stop = SIP_DECL(stop); 815 IFQ_SET_READY(&ifp->if_snd); 816 817 /* 818 * We can support 802.1Q VLAN-sized frames. 819 */ 820 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 821 822 #ifdef DP83820 823 /* 824 * And the DP83820 can do VLAN tagging in hardware, and 825 * support the jumbo Ethernet MTU. 826 */ 827 sc->sc_ethercom.ec_capabilities |= 828 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 829 830 /* 831 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 832 * in hardware. 833 */ 834 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 835 IFCAP_CSUM_UDPv4; 836 #endif /* DP83820 */ 837 838 /* 839 * Attach the interface. 840 */ 841 if_attach(ifp); 842 ether_ifattach(ifp, enaddr); 843 844 #ifdef SIP_EVENT_COUNTERS 845 /* 846 * Attach event counters. 847 */ 848 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 849 NULL, sc->sc_dev.dv_xname, "txsstall"); 850 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 851 NULL, sc->sc_dev.dv_xname, "txdstall"); 852 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 853 NULL, sc->sc_dev.dv_xname, "txintr"); 854 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 855 NULL, sc->sc_dev.dv_xname, "rxintr"); 856 #ifdef DP83820 857 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 858 NULL, sc->sc_dev.dv_xname, "rxipsum"); 859 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 860 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 861 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 862 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 863 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 864 NULL, sc->sc_dev.dv_xname, "txipsum"); 865 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 866 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 867 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 868 NULL, sc->sc_dev.dv_xname, "txudpsum"); 869 #endif /* DP83820 */ 870 #endif /* SIP_EVENT_COUNTERS */ 871 872 /* 873 * Make sure the interface is shutdown during reboot. 874 */ 875 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 876 if (sc->sc_sdhook == NULL) 877 printf("%s: WARNING: unable to establish shutdown hook\n", 878 sc->sc_dev.dv_xname); 879 return; 880 881 /* 882 * Free any resources we've allocated during the failed attach 883 * attempt. Do this in reverse order and fall through. 884 */ 885 fail_5: 886 for (i = 0; i < SIP_NRXDESC; i++) { 887 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 888 bus_dmamap_destroy(sc->sc_dmat, 889 sc->sc_rxsoft[i].rxs_dmamap); 890 } 891 fail_4: 892 for (i = 0; i < SIP_TXQUEUELEN; i++) { 893 if (sc->sc_txsoft[i].txs_dmamap != NULL) 894 bus_dmamap_destroy(sc->sc_dmat, 895 sc->sc_txsoft[i].txs_dmamap); 896 } 897 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 898 fail_3: 899 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 900 fail_2: 901 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 902 sizeof(struct sip_control_data)); 903 fail_1: 904 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 905 fail_0: 906 return; 907 } 908 909 /* 910 * sip_shutdown: 911 * 912 * Make sure the interface is stopped at reboot time. 913 */ 914 void 915 SIP_DECL(shutdown)(void *arg) 916 { 917 struct sip_softc *sc = arg; 918 919 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 920 } 921 922 /* 923 * sip_start: [ifnet interface function] 924 * 925 * Start packet transmission on the interface. 926 */ 927 void 928 SIP_DECL(start)(struct ifnet *ifp) 929 { 930 struct sip_softc *sc = ifp->if_softc; 931 struct mbuf *m0, *m; 932 struct sip_txsoft *txs; 933 bus_dmamap_t dmamap; 934 int error, firsttx, nexttx, lasttx, ofree, seg; 935 #ifdef DP83820 936 u_int32_t extsts; 937 #endif 938 939 /* 940 * If we've been told to pause, don't transmit any more packets. 941 */ 942 if (sc->sc_flags & SIPF_PAUSED) 943 ifp->if_flags |= IFF_OACTIVE; 944 945 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 946 return; 947 948 /* 949 * Remember the previous number of free descriptors and 950 * the first descriptor we'll use. 951 */ 952 ofree = sc->sc_txfree; 953 firsttx = sc->sc_txnext; 954 955 /* 956 * Loop through the send queue, setting up transmit descriptors 957 * until we drain the queue, or use up all available transmit 958 * descriptors. 959 */ 960 for (;;) { 961 /* Get a work queue entry. */ 962 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 963 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 964 break; 965 } 966 967 /* 968 * Grab a packet off the queue. 969 */ 970 IFQ_POLL(&ifp->if_snd, m0); 971 if (m0 == NULL) 972 break; 973 #ifndef DP83820 974 m = NULL; 975 #endif 976 977 dmamap = txs->txs_dmamap; 978 979 #ifdef DP83820 980 /* 981 * Load the DMA map. If this fails, the packet either 982 * didn't fit in the allotted number of segments, or we 983 * were short on resources. For the too-many-segments 984 * case, we simply report an error and drop the packet, 985 * since we can't sanely copy a jumbo packet to a single 986 * buffer. 987 */ 988 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 989 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 990 if (error) { 991 if (error == EFBIG) { 992 printf("%s: Tx packet consumes too many " 993 "DMA segments, dropping...\n", 994 sc->sc_dev.dv_xname); 995 IFQ_DEQUEUE(&ifp->if_snd, m0); 996 m_freem(m0); 997 continue; 998 } 999 /* 1000 * Short on resources, just stop for now. 1001 */ 1002 break; 1003 } 1004 #else /* DP83820 */ 1005 /* 1006 * Load the DMA map. If this fails, the packet either 1007 * didn't fit in the alloted number of segments, or we 1008 * were short on resources. In this case, we'll copy 1009 * and try again. 1010 */ 1011 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1012 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1013 MGETHDR(m, M_DONTWAIT, MT_DATA); 1014 if (m == NULL) { 1015 printf("%s: unable to allocate Tx mbuf\n", 1016 sc->sc_dev.dv_xname); 1017 break; 1018 } 1019 if (m0->m_pkthdr.len > MHLEN) { 1020 MCLGET(m, M_DONTWAIT); 1021 if ((m->m_flags & M_EXT) == 0) { 1022 printf("%s: unable to allocate Tx " 1023 "cluster\n", sc->sc_dev.dv_xname); 1024 m_freem(m); 1025 break; 1026 } 1027 } 1028 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1029 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1030 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1031 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1032 if (error) { 1033 printf("%s: unable to load Tx buffer, " 1034 "error = %d\n", sc->sc_dev.dv_xname, error); 1035 break; 1036 } 1037 } 1038 #endif /* DP83820 */ 1039 1040 /* 1041 * Ensure we have enough descriptors free to describe 1042 * the packet. Note, we always reserve one descriptor 1043 * at the end of the ring as a termination point, to 1044 * prevent wrap-around. 1045 */ 1046 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1047 /* 1048 * Not enough free descriptors to transmit this 1049 * packet. We haven't committed anything yet, 1050 * so just unload the DMA map, put the packet 1051 * back on the queue, and punt. Notify the upper 1052 * layer that there are not more slots left. 1053 * 1054 * XXX We could allocate an mbuf and copy, but 1055 * XXX is it worth it? 1056 */ 1057 ifp->if_flags |= IFF_OACTIVE; 1058 bus_dmamap_unload(sc->sc_dmat, dmamap); 1059 #ifndef DP83820 1060 if (m != NULL) 1061 m_freem(m); 1062 #endif 1063 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1064 break; 1065 } 1066 1067 IFQ_DEQUEUE(&ifp->if_snd, m0); 1068 #ifndef DP83820 1069 if (m != NULL) { 1070 m_freem(m0); 1071 m0 = m; 1072 } 1073 #endif 1074 1075 /* 1076 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1077 */ 1078 1079 /* Sync the DMA map. */ 1080 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1081 BUS_DMASYNC_PREWRITE); 1082 1083 /* 1084 * Initialize the transmit descriptors. 1085 */ 1086 for (nexttx = sc->sc_txnext, seg = 0; 1087 seg < dmamap->dm_nsegs; 1088 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1089 /* 1090 * If this is the first descriptor we're 1091 * enqueueing, don't set the OWN bit just 1092 * yet. That could cause a race condition. 1093 * We'll do it below. 1094 */ 1095 sc->sc_txdescs[nexttx].sipd_bufptr = 1096 htole32(dmamap->dm_segs[seg].ds_addr); 1097 sc->sc_txdescs[nexttx].sipd_cmdsts = 1098 htole32((nexttx == firsttx ? 0 : CMDSTS_OWN) | 1099 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1100 #ifdef DP83820 1101 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1102 #endif /* DP83820 */ 1103 lasttx = nexttx; 1104 } 1105 1106 /* Clear the MORE bit on the last segment. */ 1107 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1108 1109 #ifdef DP83820 1110 /* 1111 * If VLANs are enabled and the packet has a VLAN tag, set 1112 * up the descriptor to encapsulate the packet for us. 1113 * 1114 * This apparently has to be on the last descriptor of 1115 * the packet. 1116 */ 1117 if (sc->sc_ethercom.ec_nvlans != 0 && 1118 (m = m_aux_find(m0, AF_LINK, ETHERTYPE_VLAN)) != NULL) { 1119 sc->sc_txdescs[lasttx].sipd_extsts |= 1120 htole32(EXTSTS_VPKT | 1121 htons(*mtod(m, int *) & EXTSTS_VTCI)); 1122 } 1123 1124 /* 1125 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1126 * checksumming, set up the descriptor to do this work 1127 * for us. 1128 * 1129 * This apparently has to be on the first descriptor of 1130 * the packet. 1131 * 1132 * Byte-swap constants so the compiler can optimize. 1133 */ 1134 extsts = 0; 1135 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1136 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1137 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1138 extsts |= htole32(EXTSTS_IPPKT); 1139 } 1140 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1141 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1142 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1143 extsts |= htole32(EXTSTS_TCPPKT); 1144 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1145 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1146 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1147 extsts |= htole32(EXTSTS_UDPPKT); 1148 } 1149 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1150 #endif /* DP83820 */ 1151 1152 /* Sync the descriptors we're using. */ 1153 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1154 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1155 1156 /* 1157 * Store a pointer to the packet so we can free it later, 1158 * and remember what txdirty will be once the packet is 1159 * done. 1160 */ 1161 txs->txs_mbuf = m0; 1162 txs->txs_firstdesc = sc->sc_txnext; 1163 txs->txs_lastdesc = lasttx; 1164 1165 /* Advance the tx pointer. */ 1166 sc->sc_txfree -= dmamap->dm_nsegs; 1167 sc->sc_txnext = nexttx; 1168 1169 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs, txs_q); 1170 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1171 1172 #if NBPFILTER > 0 1173 /* 1174 * Pass the packet to any BPF listeners. 1175 */ 1176 if (ifp->if_bpf) 1177 bpf_mtap(ifp->if_bpf, m0); 1178 #endif /* NBPFILTER > 0 */ 1179 } 1180 1181 if (txs == NULL || sc->sc_txfree == 0) { 1182 /* No more slots left; notify upper layer. */ 1183 ifp->if_flags |= IFF_OACTIVE; 1184 } 1185 1186 if (sc->sc_txfree != ofree) { 1187 /* 1188 * Cause a descriptor interrupt to happen on the 1189 * last packet we enqueued. 1190 */ 1191 sc->sc_txdescs[lasttx].sipd_cmdsts |= htole32(CMDSTS_INTR); 1192 SIP_CDTXSYNC(sc, lasttx, 1, 1193 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1194 1195 /* 1196 * The entire packet chain is set up. Give the 1197 * first descrptor to the chip now. 1198 */ 1199 sc->sc_txdescs[firsttx].sipd_cmdsts |= htole32(CMDSTS_OWN); 1200 SIP_CDTXSYNC(sc, firsttx, 1, 1201 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1202 1203 /* 1204 * Start the transmit process. Note, the manual says 1205 * that if there are no pending transmissions in the 1206 * chip's internal queue (indicated by TXE being clear), 1207 * then the driver software must set the TXDP to the 1208 * first descriptor to be transmitted. However, if we 1209 * do this, it causes serious performance degredation on 1210 * the DP83820 under load, not setting TXDP doesn't seem 1211 * to adversely affect the SiS 900 or DP83815. 1212 * 1213 * Well, I guess it wouldn't be the first time a manual 1214 * has lied -- and they could be speaking of the NULL- 1215 * terminated descriptor list case, rather than OWN- 1216 * terminated rings. 1217 */ 1218 #if 0 1219 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1220 CR_TXE) == 0) { 1221 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1222 SIP_CDTXADDR(sc, firsttx)); 1223 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1224 } 1225 #else 1226 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1227 #endif 1228 1229 /* Set a watchdog timer in case the chip flakes out. */ 1230 ifp->if_timer = 5; 1231 } 1232 } 1233 1234 /* 1235 * sip_watchdog: [ifnet interface function] 1236 * 1237 * Watchdog timer handler. 1238 */ 1239 void 1240 SIP_DECL(watchdog)(struct ifnet *ifp) 1241 { 1242 struct sip_softc *sc = ifp->if_softc; 1243 1244 /* 1245 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1246 * If we get a timeout, try and sweep up transmit descriptors. 1247 * If we manage to sweep them all up, ignore the lack of 1248 * interrupt. 1249 */ 1250 SIP_DECL(txintr)(sc); 1251 1252 if (sc->sc_txfree != SIP_NTXDESC) { 1253 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1254 ifp->if_oerrors++; 1255 1256 /* Reset the interface. */ 1257 (void) SIP_DECL(init)(ifp); 1258 } else if (ifp->if_flags & IFF_DEBUG) 1259 printf("%s: recovered from device timeout\n", 1260 sc->sc_dev.dv_xname); 1261 1262 /* Try to get more packets going. */ 1263 SIP_DECL(start)(ifp); 1264 } 1265 1266 /* 1267 * sip_ioctl: [ifnet interface function] 1268 * 1269 * Handle control requests from the operator. 1270 */ 1271 int 1272 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1273 { 1274 struct sip_softc *sc = ifp->if_softc; 1275 struct ifreq *ifr = (struct ifreq *)data; 1276 int s, error; 1277 1278 s = splnet(); 1279 1280 switch (cmd) { 1281 case SIOCSIFMEDIA: 1282 case SIOCGIFMEDIA: 1283 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1284 break; 1285 1286 default: 1287 error = ether_ioctl(ifp, cmd, data); 1288 if (error == ENETRESET) { 1289 /* 1290 * Multicast list has changed; set the hardware filter 1291 * accordingly. 1292 */ 1293 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1294 error = 0; 1295 } 1296 break; 1297 } 1298 1299 /* Try to get more packets going. */ 1300 SIP_DECL(start)(ifp); 1301 1302 splx(s); 1303 return (error); 1304 } 1305 1306 /* 1307 * sip_intr: 1308 * 1309 * Interrupt service routine. 1310 */ 1311 int 1312 SIP_DECL(intr)(void *arg) 1313 { 1314 struct sip_softc *sc = arg; 1315 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1316 u_int32_t isr; 1317 int handled = 0; 1318 1319 for (;;) { 1320 /* Reading clears interrupt. */ 1321 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1322 if ((isr & sc->sc_imr) == 0) 1323 break; 1324 1325 handled = 1; 1326 1327 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1328 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1329 1330 /* Grab any new packets. */ 1331 SIP_DECL(rxintr)(sc); 1332 1333 if (isr & ISR_RXORN) { 1334 printf("%s: receive FIFO overrun\n", 1335 sc->sc_dev.dv_xname); 1336 1337 /* XXX adjust rx_drain_thresh? */ 1338 } 1339 1340 if (isr & ISR_RXIDLE) { 1341 printf("%s: receive ring overrun\n", 1342 sc->sc_dev.dv_xname); 1343 1344 /* Get the receive process going again. */ 1345 bus_space_write_4(sc->sc_st, sc->sc_sh, 1346 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1347 bus_space_write_4(sc->sc_st, sc->sc_sh, 1348 SIP_CR, CR_RXE); 1349 } 1350 } 1351 1352 if (isr & (ISR_TXURN|ISR_TXDESC)) { 1353 SIP_EVCNT_INCR(&sc->sc_ev_txintr); 1354 1355 /* Sweep up transmit descriptors. */ 1356 SIP_DECL(txintr)(sc); 1357 1358 if (isr & ISR_TXURN) { 1359 u_int32_t thresh; 1360 1361 printf("%s: transmit FIFO underrun", 1362 sc->sc_dev.dv_xname); 1363 1364 thresh = sc->sc_tx_drain_thresh + 1; 1365 if (thresh <= TXCFG_DRTH && 1366 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1367 (sc->sc_tx_fill_thresh * 32))) { 1368 printf("; increasing Tx drain " 1369 "threshold to %u bytes\n", 1370 thresh * 32); 1371 sc->sc_tx_drain_thresh = thresh; 1372 (void) SIP_DECL(init)(ifp); 1373 } else { 1374 (void) SIP_DECL(init)(ifp); 1375 printf("\n"); 1376 } 1377 } 1378 } 1379 1380 #if !defined(DP83820) 1381 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1382 if (isr & ISR_PAUSE_ST) { 1383 sc->sc_flags |= SIPF_PAUSED; 1384 ifp->if_flags |= IFF_OACTIVE; 1385 } 1386 if (isr & ISR_PAUSE_END) { 1387 sc->sc_flags &= ~SIPF_PAUSED; 1388 ifp->if_flags &= ~IFF_OACTIVE; 1389 } 1390 } 1391 #endif /* ! DP83820 */ 1392 1393 if (isr & ISR_HIBERR) { 1394 #define PRINTERR(bit, str) \ 1395 if (isr & (bit)) \ 1396 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1397 PRINTERR(ISR_DPERR, "parity error"); 1398 PRINTERR(ISR_SSERR, "system error"); 1399 PRINTERR(ISR_RMABT, "master abort"); 1400 PRINTERR(ISR_RTABT, "target abort"); 1401 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1402 (void) SIP_DECL(init)(ifp); 1403 #undef PRINTERR 1404 } 1405 } 1406 1407 /* Try to get more packets going. */ 1408 SIP_DECL(start)(ifp); 1409 1410 return (handled); 1411 } 1412 1413 /* 1414 * sip_txintr: 1415 * 1416 * Helper; handle transmit interrupts. 1417 */ 1418 void 1419 SIP_DECL(txintr)(struct sip_softc *sc) 1420 { 1421 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1422 struct sip_txsoft *txs; 1423 u_int32_t cmdsts; 1424 1425 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1426 ifp->if_flags &= ~IFF_OACTIVE; 1427 1428 /* 1429 * Go through our Tx list and free mbufs for those 1430 * frames which have been transmitted. 1431 */ 1432 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1433 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1434 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1435 1436 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1437 if (cmdsts & CMDSTS_OWN) 1438 break; 1439 1440 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1441 1442 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1443 1444 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1445 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1446 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1447 m_freem(txs->txs_mbuf); 1448 txs->txs_mbuf = NULL; 1449 1450 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1451 1452 /* 1453 * Check for errors and collisions. 1454 */ 1455 if (cmdsts & 1456 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1457 ifp->if_oerrors++; 1458 if (cmdsts & CMDSTS_Tx_EC) 1459 ifp->if_collisions += 16; 1460 if (ifp->if_flags & IFF_DEBUG) { 1461 if (cmdsts & CMDSTS_Tx_ED) 1462 printf("%s: excessive deferral\n", 1463 sc->sc_dev.dv_xname); 1464 if (cmdsts & CMDSTS_Tx_EC) 1465 printf("%s: excessive collisions\n", 1466 sc->sc_dev.dv_xname); 1467 } 1468 } else { 1469 /* Packet was transmitted successfully. */ 1470 ifp->if_opackets++; 1471 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1472 } 1473 } 1474 1475 /* 1476 * If there are no more pending transmissions, cancel the watchdog 1477 * timer. 1478 */ 1479 if (txs == NULL) 1480 ifp->if_timer = 0; 1481 } 1482 1483 #if defined(DP83820) 1484 /* 1485 * sip_rxintr: 1486 * 1487 * Helper; handle receive interrupts. 1488 */ 1489 void 1490 SIP_DECL(rxintr)(struct sip_softc *sc) 1491 { 1492 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1493 struct sip_rxsoft *rxs; 1494 struct mbuf *m, *tailm; 1495 u_int32_t cmdsts, extsts; 1496 int i, len; 1497 1498 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1499 rxs = &sc->sc_rxsoft[i]; 1500 1501 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1502 1503 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1504 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1505 1506 /* 1507 * NOTE: OWN is set if owned by _consumer_. We're the 1508 * consumer of the receive ring, so if the bit is clear, 1509 * we have processed all of the packets. 1510 */ 1511 if ((cmdsts & CMDSTS_OWN) == 0) { 1512 /* 1513 * We have processed all of the receive buffers. 1514 */ 1515 break; 1516 } 1517 1518 if (__predict_false(sc->sc_rxdiscard)) { 1519 SIP_INIT_RXDESC(sc, i); 1520 if ((cmdsts & CMDSTS_MORE) == 0) { 1521 /* Reset our state. */ 1522 sc->sc_rxdiscard = 0; 1523 } 1524 continue; 1525 } 1526 1527 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1528 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1529 1530 m = rxs->rxs_mbuf; 1531 1532 /* 1533 * Add a new receive buffer to the ring. 1534 */ 1535 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1536 /* 1537 * Failed, throw away what we've done so 1538 * far, and discard the rest of the packet. 1539 */ 1540 ifp->if_ierrors++; 1541 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1542 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1543 SIP_INIT_RXDESC(sc, i); 1544 if (cmdsts & CMDSTS_MORE) 1545 sc->sc_rxdiscard = 1; 1546 if (sc->sc_rxhead != NULL) 1547 m_freem(sc->sc_rxhead); 1548 SIP_RXCHAIN_RESET(sc); 1549 continue; 1550 } 1551 1552 SIP_RXCHAIN_LINK(sc, m); 1553 1554 /* 1555 * If this is not the end of the packet, keep 1556 * looking. 1557 */ 1558 if (cmdsts & CMDSTS_MORE) { 1559 sc->sc_rxlen += m->m_len; 1560 continue; 1561 } 1562 1563 /* 1564 * Okay, we have the entire packet now... 1565 */ 1566 *sc->sc_rxtailp = NULL; 1567 m = sc->sc_rxhead; 1568 tailm = sc->sc_rxtail; 1569 1570 SIP_RXCHAIN_RESET(sc); 1571 1572 /* 1573 * If an error occurred, update stats and drop the packet. 1574 */ 1575 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1576 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1577 ifp->if_ierrors++; 1578 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1579 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1580 /* Receive overrun handled elsewhere. */ 1581 printf("%s: receive descriptor error\n", 1582 sc->sc_dev.dv_xname); 1583 } 1584 #define PRINTERR(bit, str) \ 1585 if (cmdsts & (bit)) \ 1586 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1587 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1588 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1589 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1590 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1591 #undef PRINTERR 1592 m_freem(m); 1593 continue; 1594 } 1595 1596 /* 1597 * No errors. 1598 * 1599 * Note, the DP83820 includes the CRC with 1600 * every packet. 1601 */ 1602 len = CMDSTS_SIZE(cmdsts); 1603 tailm->m_len = len - sc->sc_rxlen; 1604 1605 /* 1606 * If the packet is small enough to fit in a 1607 * single header mbuf, allocate one and copy 1608 * the data into it. This greatly reduces 1609 * memory consumption when we receive lots 1610 * of small packets. 1611 */ 1612 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1613 struct mbuf *nm; 1614 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1615 if (nm == NULL) { 1616 ifp->if_ierrors++; 1617 m_freem(m); 1618 continue; 1619 } 1620 nm->m_data += 2; 1621 nm->m_pkthdr.len = nm->m_len = len; 1622 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1623 m_freem(m); 1624 m = nm; 1625 } 1626 #ifndef __NO_STRICT_ALIGNMENT 1627 else { 1628 /* 1629 * The DP83820's receive buffers must be 4-byte 1630 * aligned. But this means that the data after 1631 * the Ethernet header is misaligned. To compensate, 1632 * we have artificially shortened the buffer size 1633 * in the descriptor, and we do an overlapping copy 1634 * of the data two bytes further in (in the first 1635 * buffer of the chain only). 1636 */ 1637 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1638 m->m_len); 1639 m->m_data += 2; 1640 } 1641 #endif /* ! __NO_STRICT_ALIGNMENT */ 1642 1643 /* 1644 * If VLANs are enabled, VLAN packets have been unwrapped 1645 * for us. Associate the tag with the packet. 1646 */ 1647 if (sc->sc_ethercom.ec_nvlans != 0 && 1648 (extsts & EXTSTS_VPKT) != 0) { 1649 struct mbuf *vtag; 1650 1651 vtag = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 1652 if (vtag == NULL) { 1653 ifp->if_ierrors++; 1654 printf("%s: unable to allocate VLAN tag\n", 1655 sc->sc_dev.dv_xname); 1656 m_freem(m); 1657 continue; 1658 } 1659 1660 *mtod(vtag, int *) = ntohs(extsts & EXTSTS_VTCI); 1661 vtag->m_len = sizeof(int); 1662 } 1663 1664 /* 1665 * Set the incoming checksum information for the 1666 * packet. 1667 */ 1668 if ((extsts & EXTSTS_IPPKT) != 0) { 1669 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1670 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1671 if (extsts & EXTSTS_Rx_IPERR) 1672 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1673 if (extsts & EXTSTS_TCPPKT) { 1674 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1675 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1676 if (extsts & EXTSTS_Rx_TCPERR) 1677 m->m_pkthdr.csum_flags |= 1678 M_CSUM_TCP_UDP_BAD; 1679 } else if (extsts & EXTSTS_UDPPKT) { 1680 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1681 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1682 if (extsts & EXTSTS_Rx_UDPERR) 1683 m->m_pkthdr.csum_flags |= 1684 M_CSUM_TCP_UDP_BAD; 1685 } 1686 } 1687 1688 ifp->if_ipackets++; 1689 m->m_flags |= M_HASFCS; 1690 m->m_pkthdr.rcvif = ifp; 1691 m->m_pkthdr.len = len; 1692 1693 #if NBPFILTER > 0 1694 /* 1695 * Pass this up to any BPF listeners, but only 1696 * pass if up the stack if it's for us. 1697 */ 1698 if (ifp->if_bpf) 1699 bpf_mtap(ifp->if_bpf, m); 1700 #endif /* NBPFILTER > 0 */ 1701 1702 /* Pass it on. */ 1703 (*ifp->if_input)(ifp, m); 1704 } 1705 1706 /* Update the receive pointer. */ 1707 sc->sc_rxptr = i; 1708 } 1709 #else /* ! DP83820 */ 1710 /* 1711 * sip_rxintr: 1712 * 1713 * Helper; handle receive interrupts. 1714 */ 1715 void 1716 SIP_DECL(rxintr)(struct sip_softc *sc) 1717 { 1718 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1719 struct sip_rxsoft *rxs; 1720 struct mbuf *m; 1721 u_int32_t cmdsts; 1722 int i, len; 1723 1724 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1725 rxs = &sc->sc_rxsoft[i]; 1726 1727 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1728 1729 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1730 1731 /* 1732 * NOTE: OWN is set if owned by _consumer_. We're the 1733 * consumer of the receive ring, so if the bit is clear, 1734 * we have processed all of the packets. 1735 */ 1736 if ((cmdsts & CMDSTS_OWN) == 0) { 1737 /* 1738 * We have processed all of the receive buffers. 1739 */ 1740 break; 1741 } 1742 1743 /* 1744 * If any collisions were seen on the wire, count one. 1745 */ 1746 if (cmdsts & CMDSTS_Rx_COL) 1747 ifp->if_collisions++; 1748 1749 /* 1750 * If an error occurred, update stats, clear the status 1751 * word, and leave the packet buffer in place. It will 1752 * simply be reused the next time the ring comes around. 1753 */ 1754 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1755 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1756 ifp->if_ierrors++; 1757 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1758 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1759 /* Receive overrun handled elsewhere. */ 1760 printf("%s: receive descriptor error\n", 1761 sc->sc_dev.dv_xname); 1762 } 1763 #define PRINTERR(bit, str) \ 1764 if (cmdsts & (bit)) \ 1765 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1766 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1767 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1768 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1769 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1770 #undef PRINTERR 1771 SIP_INIT_RXDESC(sc, i); 1772 continue; 1773 } 1774 1775 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1776 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1777 1778 /* 1779 * No errors; receive the packet. Note, the SiS 900 1780 * includes the CRC with every packet. 1781 */ 1782 len = CMDSTS_SIZE(cmdsts); 1783 1784 #ifdef __NO_STRICT_ALIGNMENT 1785 /* 1786 * If the packet is small enough to fit in a 1787 * single header mbuf, allocate one and copy 1788 * the data into it. This greatly reduces 1789 * memory consumption when we receive lots 1790 * of small packets. 1791 * 1792 * Otherwise, we add a new buffer to the receive 1793 * chain. If this fails, we drop the packet and 1794 * recycle the old buffer. 1795 */ 1796 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 1797 MGETHDR(m, M_DONTWAIT, MT_DATA); 1798 if (m == NULL) 1799 goto dropit; 1800 memcpy(mtod(m, caddr_t), 1801 mtod(rxs->rxs_mbuf, caddr_t), len); 1802 SIP_INIT_RXDESC(sc, i); 1803 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1804 rxs->rxs_dmamap->dm_mapsize, 1805 BUS_DMASYNC_PREREAD); 1806 } else { 1807 m = rxs->rxs_mbuf; 1808 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1809 dropit: 1810 ifp->if_ierrors++; 1811 SIP_INIT_RXDESC(sc, i); 1812 bus_dmamap_sync(sc->sc_dmat, 1813 rxs->rxs_dmamap, 0, 1814 rxs->rxs_dmamap->dm_mapsize, 1815 BUS_DMASYNC_PREREAD); 1816 continue; 1817 } 1818 } 1819 #else 1820 /* 1821 * The SiS 900's receive buffers must be 4-byte aligned. 1822 * But this means that the data after the Ethernet header 1823 * is misaligned. We must allocate a new buffer and 1824 * copy the data, shifted forward 2 bytes. 1825 */ 1826 MGETHDR(m, M_DONTWAIT, MT_DATA); 1827 if (m == NULL) { 1828 dropit: 1829 ifp->if_ierrors++; 1830 SIP_INIT_RXDESC(sc, i); 1831 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1832 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1833 continue; 1834 } 1835 if (len > (MHLEN - 2)) { 1836 MCLGET(m, M_DONTWAIT); 1837 if ((m->m_flags & M_EXT) == 0) { 1838 m_freem(m); 1839 goto dropit; 1840 } 1841 } 1842 m->m_data += 2; 1843 1844 /* 1845 * Note that we use clusters for incoming frames, so the 1846 * buffer is virtually contiguous. 1847 */ 1848 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 1849 1850 /* Allow the receive descriptor to continue using its mbuf. */ 1851 SIP_INIT_RXDESC(sc, i); 1852 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1853 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1854 #endif /* __NO_STRICT_ALIGNMENT */ 1855 1856 ifp->if_ipackets++; 1857 m->m_flags |= M_HASFCS; 1858 m->m_pkthdr.rcvif = ifp; 1859 m->m_pkthdr.len = m->m_len = len; 1860 1861 #if NBPFILTER > 0 1862 /* 1863 * Pass this up to any BPF listeners, but only 1864 * pass if up the stack if it's for us. 1865 */ 1866 if (ifp->if_bpf) 1867 bpf_mtap(ifp->if_bpf, m); 1868 #endif /* NBPFILTER > 0 */ 1869 1870 /* Pass it on. */ 1871 (*ifp->if_input)(ifp, m); 1872 } 1873 1874 /* Update the receive pointer. */ 1875 sc->sc_rxptr = i; 1876 } 1877 #endif /* DP83820 */ 1878 1879 /* 1880 * sip_tick: 1881 * 1882 * One second timer, used to tick the MII. 1883 */ 1884 void 1885 SIP_DECL(tick)(void *arg) 1886 { 1887 struct sip_softc *sc = arg; 1888 int s; 1889 1890 s = splnet(); 1891 mii_tick(&sc->sc_mii); 1892 splx(s); 1893 1894 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 1895 } 1896 1897 /* 1898 * sip_reset: 1899 * 1900 * Perform a soft reset on the SiS 900. 1901 */ 1902 void 1903 SIP_DECL(reset)(struct sip_softc *sc) 1904 { 1905 bus_space_tag_t st = sc->sc_st; 1906 bus_space_handle_t sh = sc->sc_sh; 1907 int i; 1908 1909 bus_space_write_4(st, sh, SIP_CR, CR_RST); 1910 1911 for (i = 0; i < SIP_TIMEOUT; i++) { 1912 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 1913 break; 1914 delay(2); 1915 } 1916 1917 if (i == SIP_TIMEOUT) 1918 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 1919 1920 delay(1000); 1921 1922 #ifdef DP83820 1923 /* 1924 * Set the general purpose I/O bits. Do it here in case we 1925 * need to have GPIO set up to talk to the media interface. 1926 */ 1927 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 1928 delay(1000); 1929 #endif /* DP83820 */ 1930 } 1931 1932 /* 1933 * sip_init: [ ifnet interface function ] 1934 * 1935 * Initialize the interface. Must be called at splnet(). 1936 */ 1937 int 1938 SIP_DECL(init)(struct ifnet *ifp) 1939 { 1940 struct sip_softc *sc = ifp->if_softc; 1941 bus_space_tag_t st = sc->sc_st; 1942 bus_space_handle_t sh = sc->sc_sh; 1943 struct sip_txsoft *txs; 1944 struct sip_rxsoft *rxs; 1945 struct sip_desc *sipd; 1946 u_int32_t reg; 1947 int i, error = 0; 1948 1949 /* 1950 * Cancel any pending I/O. 1951 */ 1952 SIP_DECL(stop)(ifp, 0); 1953 1954 /* 1955 * Reset the chip to a known state. 1956 */ 1957 SIP_DECL(reset)(sc); 1958 1959 #if !defined(DP83820) 1960 if (sc->sc_model->sip_vendor == PCI_VENDOR_NS && 1961 sc->sc_model->sip_product == PCI_PRODUCT_NS_DP83815) { 1962 /* 1963 * DP83815 manual, page 78: 1964 * 4.4 Recommended Registers Configuration 1965 * For optimum performance of the DP83815, version noted 1966 * as DP83815CVNG (SRR = 203h), the listed register 1967 * modifications must be followed in sequence... 1968 * 1969 * It's not clear if this should be 302h or 203h because that 1970 * chip name is listed as SRR 302h in the description of the 1971 * SRR register. However, my revision 302h DP83815 on the 1972 * Netgear FA311 purchased in 02/2001 needs these settings 1973 * to avoid tons of errors in AcceptPerfectMatch (non- 1974 * IFF_PROMISC) mode. I do not know if other revisions need 1975 * this set or not. [briggs -- 09 March 2001] 1976 * 1977 * Note that only the low-order 12 bits of 0xe4 are documented 1978 * and that this sets reserved bits in that register. 1979 */ 1980 reg = bus_space_read_4(st, sh, SIP_NS_SRR); 1981 if (reg == 0x302) { 1982 bus_space_write_4(st, sh, 0x00cc, 0x0001); 1983 bus_space_write_4(st, sh, 0x00e4, 0x189C); 1984 bus_space_write_4(st, sh, 0x00fc, 0x0000); 1985 bus_space_write_4(st, sh, 0x00f4, 0x5040); 1986 bus_space_write_4(st, sh, 0x00f8, 0x008c); 1987 } 1988 } 1989 #endif /* ! DP83820 */ 1990 1991 /* 1992 * Initialize the transmit descriptor ring. 1993 */ 1994 for (i = 0; i < SIP_NTXDESC; i++) { 1995 sipd = &sc->sc_txdescs[i]; 1996 memset(sipd, 0, sizeof(struct sip_desc)); 1997 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 1998 } 1999 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2000 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2001 sc->sc_txfree = SIP_NTXDESC; 2002 sc->sc_txnext = 0; 2003 2004 /* 2005 * Initialize the transmit job descriptors. 2006 */ 2007 SIMPLEQ_INIT(&sc->sc_txfreeq); 2008 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2009 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2010 txs = &sc->sc_txsoft[i]; 2011 txs->txs_mbuf = NULL; 2012 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2013 } 2014 2015 /* 2016 * Initialize the receive descriptor and receive job 2017 * descriptor rings. 2018 */ 2019 for (i = 0; i < SIP_NRXDESC; i++) { 2020 rxs = &sc->sc_rxsoft[i]; 2021 if (rxs->rxs_mbuf == NULL) { 2022 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2023 printf("%s: unable to allocate or map rx " 2024 "buffer %d, error = %d\n", 2025 sc->sc_dev.dv_xname, i, error); 2026 /* 2027 * XXX Should attempt to run with fewer receive 2028 * XXX buffers instead of just failing. 2029 */ 2030 SIP_DECL(rxdrain)(sc); 2031 goto out; 2032 } 2033 } 2034 } 2035 sc->sc_rxptr = 0; 2036 #ifdef DP83820 2037 sc->sc_rxdiscard = 0; 2038 SIP_RXCHAIN_RESET(sc); 2039 #endif /* DP83820 */ 2040 2041 /* 2042 * Set the configuration register; it's already initialized 2043 * in sip_attach(). 2044 */ 2045 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2046 2047 /* 2048 * Initialize the transmit fill and drain thresholds if 2049 * we have never done so. 2050 */ 2051 if (sc->sc_tx_fill_thresh == 0) { 2052 /* 2053 * XXX This value should be tuned. This is the 2054 * minimum (32 bytes), and we may be able to 2055 * improve performance by increasing it. 2056 */ 2057 sc->sc_tx_fill_thresh = 1; 2058 } 2059 if (sc->sc_tx_drain_thresh == 0) { 2060 /* 2061 * Start at a drain threshold of 512 bytes. We will 2062 * increase it if a DMA underrun occurs. 2063 * 2064 * XXX The minimum value of this variable should be 2065 * tuned. We may be able to improve performance 2066 * by starting with a lower value. That, however, 2067 * may trash the first few outgoing packets if the 2068 * PCI bus is saturated. 2069 */ 2070 sc->sc_tx_drain_thresh = 512 / 32; 2071 } 2072 2073 /* 2074 * Initialize the prototype TXCFG register. 2075 */ 2076 sc->sc_txcfg = TXCFG_ATP | TXCFG_MXDMA_512 | 2077 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2078 sc->sc_tx_drain_thresh; 2079 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2080 2081 /* 2082 * Initialize the receive drain threshold if we have never 2083 * done so. 2084 */ 2085 if (sc->sc_rx_drain_thresh == 0) { 2086 /* 2087 * XXX This value should be tuned. This is set to the 2088 * maximum of 248 bytes, and we may be able to improve 2089 * performance by decreasing it (although we should never 2090 * set this value lower than 2; 14 bytes are required to 2091 * filter the packet). 2092 */ 2093 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2094 } 2095 2096 /* 2097 * Initialize the prototype RXCFG register. 2098 */ 2099 sc->sc_rxcfg = RXCFG_MXDMA_512 | 2100 (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2101 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2102 2103 /* Set up the receive filter. */ 2104 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2105 2106 #ifdef DP83820 2107 /* 2108 * Initialize the VLAN/IP receive control register. 2109 * We enable checksum computation on all incoming 2110 * packets, and do not reject packets w/ bad checksums. 2111 */ 2112 reg = 0; 2113 if (ifp->if_capenable & 2114 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2115 reg |= VRCR_IPEN; 2116 if (sc->sc_ethercom.ec_nvlans != 0) 2117 reg |= VRCR_VTDEN|VRCR_VTREN; 2118 bus_space_write_4(st, sh, SIP_VRCR, reg); 2119 2120 /* 2121 * Initialize the VLAN/IP transmit control register. 2122 * We enable outgoing checksum computation on a 2123 * per-packet basis. 2124 */ 2125 reg = 0; 2126 if (ifp->if_capenable & 2127 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2128 reg |= VTCR_PPCHK; 2129 if (sc->sc_ethercom.ec_nvlans != 0) 2130 reg |= VTCR_VPPTI; 2131 bus_space_write_4(st, sh, SIP_VTCR, reg); 2132 2133 /* 2134 * If we're using VLANs, initialize the VLAN data register. 2135 * To understand why we bswap the VLAN Ethertype, see section 2136 * 4.2.36 of the DP83820 manual. 2137 */ 2138 if (sc->sc_ethercom.ec_nvlans != 0) 2139 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2140 #endif /* DP83820 */ 2141 2142 /* 2143 * Give the transmit and receive rings to the chip. 2144 */ 2145 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2146 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2147 2148 /* 2149 * Initialize the interrupt mask. 2150 */ 2151 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2152 ISR_TXURN|ISR_TXDESC|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2153 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2154 2155 /* 2156 * Set the current media. Do this after initializing the prototype 2157 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2158 * control. 2159 */ 2160 mii_mediachg(&sc->sc_mii); 2161 2162 /* 2163 * Enable interrupts. 2164 */ 2165 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2166 2167 /* 2168 * Start the transmit and receive processes. 2169 */ 2170 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2171 2172 /* 2173 * Start the one second MII clock. 2174 */ 2175 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2176 2177 /* 2178 * ...all done! 2179 */ 2180 ifp->if_flags |= IFF_RUNNING; 2181 ifp->if_flags &= ~IFF_OACTIVE; 2182 2183 out: 2184 if (error) 2185 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2186 return (error); 2187 } 2188 2189 /* 2190 * sip_drain: 2191 * 2192 * Drain the receive queue. 2193 */ 2194 void 2195 SIP_DECL(rxdrain)(struct sip_softc *sc) 2196 { 2197 struct sip_rxsoft *rxs; 2198 int i; 2199 2200 for (i = 0; i < SIP_NRXDESC; i++) { 2201 rxs = &sc->sc_rxsoft[i]; 2202 if (rxs->rxs_mbuf != NULL) { 2203 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2204 m_freem(rxs->rxs_mbuf); 2205 rxs->rxs_mbuf = NULL; 2206 } 2207 } 2208 } 2209 2210 /* 2211 * sip_stop: [ ifnet interface function ] 2212 * 2213 * Stop transmission on the interface. 2214 */ 2215 void 2216 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2217 { 2218 struct sip_softc *sc = ifp->if_softc; 2219 bus_space_tag_t st = sc->sc_st; 2220 bus_space_handle_t sh = sc->sc_sh; 2221 struct sip_txsoft *txs; 2222 u_int32_t cmdsts = 0; /* DEBUG */ 2223 2224 /* 2225 * Stop the one second clock. 2226 */ 2227 callout_stop(&sc->sc_tick_ch); 2228 2229 /* Down the MII. */ 2230 mii_down(&sc->sc_mii); 2231 2232 /* 2233 * Disable interrupts. 2234 */ 2235 bus_space_write_4(st, sh, SIP_IER, 0); 2236 2237 /* 2238 * Stop receiver and transmitter. 2239 */ 2240 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2241 2242 /* 2243 * Release any queued transmit buffers. 2244 */ 2245 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2246 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2247 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2248 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2249 CMDSTS_INTR) == 0) 2250 printf("%s: sip_stop: last descriptor does not " 2251 "have INTR bit set\n", sc->sc_dev.dv_xname); 2252 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 2253 #ifdef DIAGNOSTIC 2254 if (txs->txs_mbuf == NULL) { 2255 printf("%s: dirty txsoft with no mbuf chain\n", 2256 sc->sc_dev.dv_xname); 2257 panic("sip_stop"); 2258 } 2259 #endif 2260 cmdsts |= /* DEBUG */ 2261 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2262 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2263 m_freem(txs->txs_mbuf); 2264 txs->txs_mbuf = NULL; 2265 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2266 } 2267 2268 if (disable) 2269 SIP_DECL(rxdrain)(sc); 2270 2271 /* 2272 * Mark the interface down and cancel the watchdog timer. 2273 */ 2274 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2275 ifp->if_timer = 0; 2276 2277 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2278 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2279 printf("%s: sip_stop: no INTR bits set in dirty tx " 2280 "descriptors\n", sc->sc_dev.dv_xname); 2281 } 2282 2283 /* 2284 * sip_read_eeprom: 2285 * 2286 * Read data from the serial EEPROM. 2287 */ 2288 void 2289 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2290 u_int16_t *data) 2291 { 2292 bus_space_tag_t st = sc->sc_st; 2293 bus_space_handle_t sh = sc->sc_sh; 2294 u_int16_t reg; 2295 int i, x; 2296 2297 for (i = 0; i < wordcnt; i++) { 2298 /* Send CHIP SELECT. */ 2299 reg = EROMAR_EECS; 2300 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2301 2302 /* Shift in the READ opcode. */ 2303 for (x = 3; x > 0; x--) { 2304 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2305 reg |= EROMAR_EEDI; 2306 else 2307 reg &= ~EROMAR_EEDI; 2308 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2309 bus_space_write_4(st, sh, SIP_EROMAR, 2310 reg | EROMAR_EESK); 2311 delay(4); 2312 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2313 delay(4); 2314 } 2315 2316 /* Shift in address. */ 2317 for (x = 6; x > 0; x--) { 2318 if ((word + i) & (1 << (x - 1))) 2319 reg |= EROMAR_EEDI; 2320 else 2321 reg &= ~EROMAR_EEDI; 2322 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2323 bus_space_write_4(st, sh, SIP_EROMAR, 2324 reg | EROMAR_EESK); 2325 delay(4); 2326 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2327 delay(4); 2328 } 2329 2330 /* Shift out data. */ 2331 reg = EROMAR_EECS; 2332 data[i] = 0; 2333 for (x = 16; x > 0; x--) { 2334 bus_space_write_4(st, sh, SIP_EROMAR, 2335 reg | EROMAR_EESK); 2336 delay(4); 2337 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2338 data[i] |= (1 << (x - 1)); 2339 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2340 delay(4); 2341 } 2342 2343 /* Clear CHIP SELECT. */ 2344 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2345 delay(4); 2346 } 2347 } 2348 2349 /* 2350 * sip_add_rxbuf: 2351 * 2352 * Add a receive buffer to the indicated descriptor. 2353 */ 2354 int 2355 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2356 { 2357 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2358 struct mbuf *m; 2359 int error; 2360 2361 MGETHDR(m, M_DONTWAIT, MT_DATA); 2362 if (m == NULL) 2363 return (ENOBUFS); 2364 2365 MCLGET(m, M_DONTWAIT); 2366 if ((m->m_flags & M_EXT) == 0) { 2367 m_freem(m); 2368 return (ENOBUFS); 2369 } 2370 2371 #if defined(DP83820) 2372 m->m_len = SIP_RXBUF_LEN; 2373 #endif /* DP83820 */ 2374 2375 if (rxs->rxs_mbuf != NULL) 2376 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2377 2378 rxs->rxs_mbuf = m; 2379 2380 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2381 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2382 BUS_DMA_READ|BUS_DMA_NOWAIT); 2383 if (error) { 2384 printf("%s: can't load rx DMA map %d, error = %d\n", 2385 sc->sc_dev.dv_xname, idx, error); 2386 panic("sip_add_rxbuf"); /* XXX */ 2387 } 2388 2389 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2390 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2391 2392 SIP_INIT_RXDESC(sc, idx); 2393 2394 return (0); 2395 } 2396 2397 #if !defined(DP83820) 2398 /* 2399 * sip_sis900_set_filter: 2400 * 2401 * Set up the receive filter. 2402 */ 2403 void 2404 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2405 { 2406 bus_space_tag_t st = sc->sc_st; 2407 bus_space_handle_t sh = sc->sc_sh; 2408 struct ethercom *ec = &sc->sc_ethercom; 2409 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2410 struct ether_multi *enm; 2411 u_int8_t *cp; 2412 struct ether_multistep step; 2413 u_int32_t crc, mchash[8]; 2414 2415 /* 2416 * Initialize the prototype RFCR. 2417 */ 2418 sc->sc_rfcr = RFCR_RFEN; 2419 if (ifp->if_flags & IFF_BROADCAST) 2420 sc->sc_rfcr |= RFCR_AAB; 2421 if (ifp->if_flags & IFF_PROMISC) { 2422 sc->sc_rfcr |= RFCR_AAP; 2423 goto allmulti; 2424 } 2425 2426 /* 2427 * Set up the multicast address filter by passing all multicast 2428 * addresses through a CRC generator, and then using the high-order 2429 * 6 bits as an index into the 128 bit multicast hash table (only 2430 * the lower 16 bits of each 32 bit multicast hash register are 2431 * valid). The high order bits select the register, while the 2432 * rest of the bits select the bit within the register. 2433 */ 2434 2435 memset(mchash, 0, sizeof(mchash)); 2436 2437 ETHER_FIRST_MULTI(step, ec, enm); 2438 while (enm != NULL) { 2439 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2440 /* 2441 * We must listen to a range of multicast addresses. 2442 * For now, just accept all multicasts, rather than 2443 * trying to set only those filter bits needed to match 2444 * the range. (At this time, the only use of address 2445 * ranges is for IP multicast routing, for which the 2446 * range is big enough to require all bits set.) 2447 */ 2448 goto allmulti; 2449 } 2450 2451 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2452 2453 /* Just want the 7 most significant bits. */ 2454 crc >>= 25; 2455 2456 /* Set the corresponding bit in the hash table. */ 2457 mchash[crc >> 4] |= 1 << (crc & 0xf); 2458 2459 ETHER_NEXT_MULTI(step, enm); 2460 } 2461 2462 ifp->if_flags &= ~IFF_ALLMULTI; 2463 goto setit; 2464 2465 allmulti: 2466 ifp->if_flags |= IFF_ALLMULTI; 2467 sc->sc_rfcr |= RFCR_AAM; 2468 2469 setit: 2470 #define FILTER_EMIT(addr, data) \ 2471 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2472 delay(1); \ 2473 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2474 delay(1) 2475 2476 /* 2477 * Disable receive filter, and program the node address. 2478 */ 2479 cp = LLADDR(ifp->if_sadl); 2480 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2481 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2482 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2483 2484 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2485 /* 2486 * Program the multicast hash table. 2487 */ 2488 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2489 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2490 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2491 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2492 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2493 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2494 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2495 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2496 } 2497 #undef FILTER_EMIT 2498 2499 /* 2500 * Re-enable the receiver filter. 2501 */ 2502 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2503 } 2504 #endif /* ! DP83820 */ 2505 2506 /* 2507 * sip_dp83815_set_filter: 2508 * 2509 * Set up the receive filter. 2510 */ 2511 void 2512 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2513 { 2514 bus_space_tag_t st = sc->sc_st; 2515 bus_space_handle_t sh = sc->sc_sh; 2516 struct ethercom *ec = &sc->sc_ethercom; 2517 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2518 struct ether_multi *enm; 2519 u_int8_t *cp; 2520 struct ether_multistep step; 2521 u_int32_t crc, hash, slot, bit; 2522 #ifdef DP83820 2523 #define MCHASH_NWORDS 128 2524 #else 2525 #define MCHASH_NWORDS 32 2526 #endif /* DP83820 */ 2527 u_int16_t mchash[MCHASH_NWORDS]; 2528 int i; 2529 2530 /* 2531 * Initialize the prototype RFCR. 2532 * Enable the receive filter, and accept on 2533 * Perfect (destination address) Match 2534 * If IFF_BROADCAST, also accept all broadcast packets. 2535 * If IFF_PROMISC, accept all unicast packets (and later, set 2536 * IFF_ALLMULTI and accept all multicast, too). 2537 */ 2538 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2539 if (ifp->if_flags & IFF_BROADCAST) 2540 sc->sc_rfcr |= RFCR_AAB; 2541 if (ifp->if_flags & IFF_PROMISC) { 2542 sc->sc_rfcr |= RFCR_AAP; 2543 goto allmulti; 2544 } 2545 2546 #ifdef DP83820 2547 /* 2548 * Set up the DP83820 multicast address filter by passing all multicast 2549 * addresses through a CRC generator, and then using the high-order 2550 * 11 bits as an index into the 2048 bit multicast hash table. The 2551 * high-order 7 bits select the slot, while the low-order 4 bits 2552 * select the bit within the slot. Note that only the low 16-bits 2553 * of each filter word are used, and there are 128 filter words. 2554 */ 2555 #else 2556 /* 2557 * Set up the DP83815 multicast address filter by passing all multicast 2558 * addresses through a CRC generator, and then using the high-order 2559 * 9 bits as an index into the 512 bit multicast hash table. The 2560 * high-order 5 bits select the slot, while the low-order 4 bits 2561 * select the bit within the slot. Note that only the low 16-bits 2562 * of each filter word are used, and there are 32 filter words. 2563 */ 2564 #endif /* DP83820 */ 2565 2566 memset(mchash, 0, sizeof(mchash)); 2567 2568 ifp->if_flags &= ~IFF_ALLMULTI; 2569 ETHER_FIRST_MULTI(step, ec, enm); 2570 if (enm == NULL) 2571 goto setit; 2572 while (enm != NULL) { 2573 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2574 /* 2575 * We must listen to a range of multicast addresses. 2576 * For now, just accept all multicasts, rather than 2577 * trying to set only those filter bits needed to match 2578 * the range. (At this time, the only use of address 2579 * ranges is for IP multicast routing, for which the 2580 * range is big enough to require all bits set.) 2581 */ 2582 goto allmulti; 2583 } 2584 2585 #ifdef DP83820 2586 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2587 2588 /* Just want the 11 most significant bits. */ 2589 hash = crc >> 21; 2590 #else 2591 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2592 2593 /* Just want the 9 most significant bits. */ 2594 hash = crc >> 23; 2595 #endif /* DP83820 */ 2596 slot = hash >> 4; 2597 bit = hash & 0xf; 2598 2599 /* Set the corresponding bit in the hash table. */ 2600 mchash[slot] |= 1 << bit; 2601 2602 ETHER_NEXT_MULTI(step, enm); 2603 } 2604 sc->sc_rfcr |= RFCR_MHEN; 2605 goto setit; 2606 2607 allmulti: 2608 ifp->if_flags |= IFF_ALLMULTI; 2609 sc->sc_rfcr |= RFCR_AAM; 2610 2611 setit: 2612 #define FILTER_EMIT(addr, data) \ 2613 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2614 delay(1); \ 2615 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2616 delay(1) 2617 2618 /* 2619 * Disable receive filter, and program the node address. 2620 */ 2621 cp = LLADDR(ifp->if_sadl); 2622 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 2623 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 2624 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 2625 2626 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2627 /* 2628 * Program the multicast hash table. 2629 */ 2630 for (i = 0; i < MCHASH_NWORDS; i++) { 2631 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 2632 mchash[i]); 2633 } 2634 } 2635 #undef FILTER_EMIT 2636 #undef MCHASH_NWORDS 2637 2638 /* 2639 * Re-enable the receiver filter. 2640 */ 2641 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2642 } 2643 2644 #if defined(DP83820) 2645 /* 2646 * sip_dp83820_mii_readreg: [mii interface function] 2647 * 2648 * Read a PHY register on the MII of the DP83820. 2649 */ 2650 int 2651 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 2652 { 2653 2654 return (mii_bitbang_readreg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2655 phy, reg)); 2656 } 2657 2658 /* 2659 * sip_dp83820_mii_writereg: [mii interface function] 2660 * 2661 * Write a PHY register on the MII of the DP83820. 2662 */ 2663 void 2664 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 2665 { 2666 2667 mii_bitbang_writereg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2668 phy, reg, val); 2669 } 2670 2671 /* 2672 * sip_dp83815_mii_statchg: [mii interface function] 2673 * 2674 * Callback from MII layer when media changes. 2675 */ 2676 void 2677 SIP_DECL(dp83820_mii_statchg)(struct device *self) 2678 { 2679 struct sip_softc *sc = (struct sip_softc *) self; 2680 u_int32_t cfg; 2681 2682 /* 2683 * Update TXCFG for full-duplex operation. 2684 */ 2685 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2686 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2687 else 2688 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2689 2690 /* 2691 * Update RXCFG for full-duplex or loopback. 2692 */ 2693 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2694 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2695 sc->sc_rxcfg |= RXCFG_ATX; 2696 else 2697 sc->sc_rxcfg &= ~RXCFG_ATX; 2698 2699 /* 2700 * Update CFG for MII/GMII. 2701 */ 2702 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2703 cfg = sc->sc_cfg | CFG_MODE_1000; 2704 else 2705 cfg = sc->sc_cfg; 2706 2707 /* 2708 * XXX 802.3x flow control. 2709 */ 2710 2711 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 2712 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2713 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2714 } 2715 2716 /* 2717 * sip_dp83820_mii_bitbang_read: [mii bit-bang interface function] 2718 * 2719 * Read the MII serial port for the MII bit-bang module. 2720 */ 2721 u_int32_t 2722 SIP_DECL(dp83820_mii_bitbang_read)(struct device *self) 2723 { 2724 struct sip_softc *sc = (void *) self; 2725 2726 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 2727 } 2728 2729 /* 2730 * sip_dp83820_mii_bitbang_write: [mii big-bang interface function] 2731 * 2732 * Write the MII serial port for the MII bit-bang module. 2733 */ 2734 void 2735 SIP_DECL(dp83820_mii_bitbang_write)(struct device *self, u_int32_t val) 2736 { 2737 struct sip_softc *sc = (void *) self; 2738 2739 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 2740 } 2741 #else /* ! DP83820 */ 2742 /* 2743 * sip_sis900_mii_readreg: [mii interface function] 2744 * 2745 * Read a PHY register on the MII. 2746 */ 2747 int 2748 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 2749 { 2750 struct sip_softc *sc = (struct sip_softc *) self; 2751 u_int32_t enphy; 2752 2753 /* 2754 * The SiS 900 has only an internal PHY on the MII. Only allow 2755 * MII address 0. 2756 */ 2757 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 2758 return (0); 2759 2760 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2761 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 2762 ENPHY_RWCMD | ENPHY_ACCESS); 2763 do { 2764 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2765 } while (enphy & ENPHY_ACCESS); 2766 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 2767 } 2768 2769 /* 2770 * sip_sis900_mii_writereg: [mii interface function] 2771 * 2772 * Write a PHY register on the MII. 2773 */ 2774 void 2775 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 2776 { 2777 struct sip_softc *sc = (struct sip_softc *) self; 2778 u_int32_t enphy; 2779 2780 /* 2781 * The SiS 900 has only an internal PHY on the MII. Only allow 2782 * MII address 0. 2783 */ 2784 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 2785 return; 2786 2787 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2788 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 2789 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 2790 do { 2791 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2792 } while (enphy & ENPHY_ACCESS); 2793 } 2794 2795 /* 2796 * sip_sis900_mii_statchg: [mii interface function] 2797 * 2798 * Callback from MII layer when media changes. 2799 */ 2800 void 2801 SIP_DECL(sis900_mii_statchg)(struct device *self) 2802 { 2803 struct sip_softc *sc = (struct sip_softc *) self; 2804 u_int32_t flowctl; 2805 2806 /* 2807 * Update TXCFG for full-duplex operation. 2808 */ 2809 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2810 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2811 else 2812 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2813 2814 /* 2815 * Update RXCFG for full-duplex or loopback. 2816 */ 2817 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2818 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2819 sc->sc_rxcfg |= RXCFG_ATX; 2820 else 2821 sc->sc_rxcfg &= ~RXCFG_ATX; 2822 2823 /* 2824 * Update IMR for use of 802.3x flow control. 2825 */ 2826 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 2827 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 2828 flowctl = FLOWCTL_FLOWEN; 2829 } else { 2830 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 2831 flowctl = 0; 2832 } 2833 2834 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2835 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2836 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 2837 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 2838 } 2839 2840 /* 2841 * sip_dp83815_mii_readreg: [mii interface function] 2842 * 2843 * Read a PHY register on the MII. 2844 */ 2845 int 2846 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 2847 { 2848 struct sip_softc *sc = (struct sip_softc *) self; 2849 u_int32_t val; 2850 2851 /* 2852 * The DP83815 only has an internal PHY. Only allow 2853 * MII address 0. 2854 */ 2855 if (phy != 0) 2856 return (0); 2857 2858 /* 2859 * Apparently, after a reset, the DP83815 can take a while 2860 * to respond. During this recovery period, the BMSR returns 2861 * a value of 0. Catch this -- it's not supposed to happen 2862 * (the BMSR has some hardcoded-to-1 bits), and wait for the 2863 * PHY to come back to life. 2864 * 2865 * This works out because the BMSR is the first register 2866 * read during the PHY probe process. 2867 */ 2868 do { 2869 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 2870 } while (reg == MII_BMSR && val == 0); 2871 2872 return (val & 0xffff); 2873 } 2874 2875 /* 2876 * sip_dp83815_mii_writereg: [mii interface function] 2877 * 2878 * Write a PHY register to the MII. 2879 */ 2880 void 2881 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 2882 { 2883 struct sip_softc *sc = (struct sip_softc *) self; 2884 2885 /* 2886 * The DP83815 only has an internal PHY. Only allow 2887 * MII address 0. 2888 */ 2889 if (phy != 0) 2890 return; 2891 2892 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 2893 } 2894 2895 /* 2896 * sip_dp83815_mii_statchg: [mii interface function] 2897 * 2898 * Callback from MII layer when media changes. 2899 */ 2900 void 2901 SIP_DECL(dp83815_mii_statchg)(struct device *self) 2902 { 2903 struct sip_softc *sc = (struct sip_softc *) self; 2904 2905 /* 2906 * Update TXCFG for full-duplex operation. 2907 */ 2908 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2909 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2910 else 2911 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2912 2913 /* 2914 * Update RXCFG for full-duplex or loopback. 2915 */ 2916 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2917 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2918 sc->sc_rxcfg |= RXCFG_ATX; 2919 else 2920 sc->sc_rxcfg &= ~RXCFG_ATX; 2921 2922 /* 2923 * XXX 802.3x flow control. 2924 */ 2925 2926 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2927 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2928 } 2929 #endif /* DP83820 */ 2930 2931 #if defined(DP83820) 2932 void 2933 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, u_int8_t *enaddr) 2934 { 2935 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 2936 u_int8_t cksum, *e, match; 2937 int i; 2938 2939 /* 2940 * EEPROM data format for the DP83820 can be found in 2941 * the DP83820 manual, section 4.2.4. 2942 */ 2943 2944 SIP_DECL(read_eeprom)(sc, 0, 2945 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 2946 2947 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 2948 match = ~(match - 1); 2949 2950 cksum = 0x55; 2951 e = (u_int8_t *) eeprom_data; 2952 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 2953 cksum += *e++; 2954 2955 if (cksum != match) 2956 printf("%s: Checksum (%x) mismatch (%x)", 2957 sc->sc_dev.dv_xname, cksum, match); 2958 2959 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 2960 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 2961 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 2962 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 2963 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 2964 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 2965 2966 /* Get the GPIOR bits. */ 2967 sc->sc_gpior = eeprom_data[0x04]; 2968 2969 /* Get various CFG related bits. */ 2970 if ((eeprom_data[0x05] >> 0) & 1) 2971 sc->sc_cfg |= CFG_EXT_125; 2972 if ((eeprom_data[0x05] >> 9) & 1) 2973 sc->sc_cfg |= CFG_TBI_EN; 2974 } 2975 #else /* ! DP83820 */ 2976 void 2977 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, u_int8_t *enaddr) 2978 { 2979 u_int16_t myea[ETHER_ADDR_LEN / 2]; 2980 2981 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 2982 sizeof(myea) / sizeof(myea[0]), myea); 2983 2984 enaddr[0] = myea[0] & 0xff; 2985 enaddr[1] = myea[0] >> 8; 2986 enaddr[2] = myea[1] & 0xff; 2987 enaddr[3] = myea[1] >> 8; 2988 enaddr[4] = myea[2] & 0xff; 2989 enaddr[5] = myea[2] >> 8; 2990 } 2991 2992 /* Table and macro to bit-reverse an octet. */ 2993 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 2994 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 2995 2996 void 2997 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, u_int8_t *enaddr) 2998 { 2999 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3000 u_int8_t cksum, *e, match; 3001 int i; 3002 3003 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3004 sizeof(eeprom_data[0]), eeprom_data); 3005 3006 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3007 match = ~(match - 1); 3008 3009 cksum = 0x55; 3010 e = (u_int8_t *) eeprom_data; 3011 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3012 cksum += *e++; 3013 } 3014 if (cksum != match) { 3015 printf("%s: Checksum (%x) mismatch (%x)", 3016 sc->sc_dev.dv_xname, cksum, match); 3017 } 3018 3019 /* 3020 * Unrolled because it makes slightly more sense this way. 3021 * The DP83815 stores the MAC address in bit 0 of word 6 3022 * through bit 15 of word 8. 3023 */ 3024 ea = &eeprom_data[6]; 3025 enaddr[0] = ((*ea & 0x1) << 7); 3026 ea++; 3027 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3028 enaddr[1] = ((*ea & 0x1FE) >> 1); 3029 enaddr[2] = ((*ea & 0x1) << 7); 3030 ea++; 3031 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3032 enaddr[3] = ((*ea & 0x1FE) >> 1); 3033 enaddr[4] = ((*ea & 0x1) << 7); 3034 ea++; 3035 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3036 enaddr[5] = ((*ea & 0x1FE) >> 1); 3037 3038 /* 3039 * In case that's not weird enough, we also need to reverse 3040 * the bits in each byte. This all actually makes more sense 3041 * if you think about the EEPROM storage as an array of bits 3042 * being shifted into bytes, but that's not how we're looking 3043 * at it here... 3044 */ 3045 for (i = 0; i < 6 ;i++) 3046 enaddr[i] = bbr(enaddr[i]); 3047 } 3048 #endif /* DP83820 */ 3049 3050 /* 3051 * sip_mediastatus: [ifmedia interface function] 3052 * 3053 * Get the current interface media status. 3054 */ 3055 void 3056 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3057 { 3058 struct sip_softc *sc = ifp->if_softc; 3059 3060 mii_pollstat(&sc->sc_mii); 3061 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3062 ifmr->ifm_active = sc->sc_mii.mii_media_active; 3063 } 3064 3065 /* 3066 * sip_mediachange: [ifmedia interface function] 3067 * 3068 * Set hardware to newly-selected media. 3069 */ 3070 int 3071 SIP_DECL(mediachange)(struct ifnet *ifp) 3072 { 3073 struct sip_softc *sc = ifp->if_softc; 3074 3075 if (ifp->if_flags & IFF_UP) 3076 mii_mediachg(&sc->sc_mii); 3077 return (0); 3078 } 3079
Indexes created Tue Sep 30 11:09:46 GMT 2025