if_sip.c revision 1.52.4.5
1 /* $NetBSD: if_sip.c,v 1.52.4.5 2002/11/01 18:28:14 tron Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Support the 10-bit interface on the DP83820 (for fiber). 80 * 81 * - Reduce the Rx interrupt load. 82 */ 83 84 #include <sys/cdefs.h> 85 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.52.4.5 2002/11/01 18:28:14 tron Exp $"); 86 87 #include "bpfilter.h" 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/callout.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/ioctl.h> 97 #include <sys/errno.h> 98 #include <sys/device.h> 99 #include <sys/queue.h> 100 101 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 102 103 #include <net/if.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 #include <net/if_ether.h> 107 108 #if NBPFILTER > 0 109 #include <net/bpf.h> 110 #endif 111 112 #include <machine/bus.h> 113 #include <machine/intr.h> 114 #include <machine/endian.h> 115 116 #include <dev/mii/mii.h> 117 #include <dev/mii/miivar.h> 118 #ifdef DP83820 119 #include <dev/mii/mii_bitbang.h> 120 #endif /* DP83820 */ 121 122 #include <dev/pci/pcireg.h> 123 #include <dev/pci/pcivar.h> 124 #include <dev/pci/pcidevs.h> 125 126 #include <dev/pci/if_sipreg.h> 127 128 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 129 #define SIP_DECL(x) __CONCAT(gsip_,x) 130 #else /* SiS900 and DP83815 */ 131 #define SIP_DECL(x) __CONCAT(sip_,x) 132 #endif 133 134 #define SIP_STR(x) __STRING(SIP_DECL(x)) 135 136 /* 137 * Transmit descriptor list size. This is arbitrary, but allocate 138 * enough descriptors for 128 pending transmissions, and 8 segments 139 * per packet. This MUST work out to a power of 2. 140 */ 141 #define SIP_NTXSEGS 16 142 #define SIP_NTXSEGS_ALLOC 8 143 144 #define SIP_TXQUEUELEN 256 145 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 146 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 147 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 148 149 #if defined(DP83020) 150 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 151 #else 152 #define TX_DMAMAP_SIZE MCLBYTES 153 #endif 154 155 /* 156 * Receive descriptor list size. We have one Rx buffer per incoming 157 * packet, so this logic is a little simpler. 158 * 159 * Actually, on the DP83820, we allow the packet to consume more than 160 * one buffer, in order to support jumbo Ethernet frames. In that 161 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 162 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 163 * so we'd better be quick about handling receive interrupts. 164 */ 165 #if defined(DP83820) 166 #define SIP_NRXDESC 256 167 #else 168 #define SIP_NRXDESC 128 169 #endif /* DP83820 */ 170 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 171 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 172 173 /* 174 * Control structures are DMA'd to the SiS900 chip. We allocate them in 175 * a single clump that maps to a single DMA segment to make several things 176 * easier. 177 */ 178 struct sip_control_data { 179 /* 180 * The transmit descriptors. 181 */ 182 struct sip_desc scd_txdescs[SIP_NTXDESC]; 183 184 /* 185 * The receive descriptors. 186 */ 187 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 188 }; 189 190 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 191 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 192 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 193 194 /* 195 * Software state for transmit jobs. 196 */ 197 struct sip_txsoft { 198 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 199 bus_dmamap_t txs_dmamap; /* our DMA map */ 200 int txs_firstdesc; /* first descriptor in packet */ 201 int txs_lastdesc; /* last descriptor in packet */ 202 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 203 }; 204 205 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 206 207 /* 208 * Software state for receive jobs. 209 */ 210 struct sip_rxsoft { 211 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 212 bus_dmamap_t rxs_dmamap; /* our DMA map */ 213 }; 214 215 /* 216 * Software state per device. 217 */ 218 struct sip_softc { 219 struct device sc_dev; /* generic device information */ 220 bus_space_tag_t sc_st; /* bus space tag */ 221 bus_space_handle_t sc_sh; /* bus space handle */ 222 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 223 struct ethercom sc_ethercom; /* ethernet common data */ 224 void *sc_sdhook; /* shutdown hook */ 225 226 const struct sip_product *sc_model; /* which model are we? */ 227 int sc_rev; /* chip revision */ 228 229 void *sc_ih; /* interrupt cookie */ 230 231 struct mii_data sc_mii; /* MII/media information */ 232 233 struct callout sc_tick_ch; /* tick callout */ 234 235 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 236 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 237 238 /* 239 * Software state for transmit and receive descriptors. 240 */ 241 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 242 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 243 244 /* 245 * Control data structures. 246 */ 247 struct sip_control_data *sc_control_data; 248 #define sc_txdescs sc_control_data->scd_txdescs 249 #define sc_rxdescs sc_control_data->scd_rxdescs 250 251 #ifdef SIP_EVENT_COUNTERS 252 /* 253 * Event counters. 254 */ 255 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 256 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 257 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 258 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 259 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 260 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 261 #ifdef DP83820 262 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 263 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 264 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 265 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 266 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 267 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 268 #endif /* DP83820 */ 269 #endif /* SIP_EVENT_COUNTERS */ 270 271 u_int32_t sc_txcfg; /* prototype TXCFG register */ 272 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 273 u_int32_t sc_imr; /* prototype IMR register */ 274 u_int32_t sc_rfcr; /* prototype RFCR register */ 275 276 u_int32_t sc_cfg; /* prototype CFG register */ 277 278 #ifdef DP83820 279 u_int32_t sc_gpior; /* prototype GPIOR register */ 280 #endif /* DP83820 */ 281 282 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 283 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 284 285 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 286 287 int sc_flags; /* misc. flags; see below */ 288 289 int sc_txfree; /* number of free Tx descriptors */ 290 int sc_txnext; /* next ready Tx descriptor */ 291 int sc_txwin; /* Tx descriptors since last intr */ 292 293 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 294 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 295 296 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 297 #if defined(DP83820) 298 int sc_rxdiscard; 299 int sc_rxlen; 300 struct mbuf *sc_rxhead; 301 struct mbuf *sc_rxtail; 302 struct mbuf **sc_rxtailp; 303 #endif /* DP83820 */ 304 }; 305 306 /* sc_flags */ 307 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 308 309 #ifdef DP83820 310 #define SIP_RXCHAIN_RESET(sc) \ 311 do { \ 312 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 313 *(sc)->sc_rxtailp = NULL; \ 314 (sc)->sc_rxlen = 0; \ 315 } while (/*CONSTCOND*/0) 316 317 #define SIP_RXCHAIN_LINK(sc, m) \ 318 do { \ 319 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 320 (sc)->sc_rxtailp = &(m)->m_next; \ 321 } while (/*CONSTCOND*/0) 322 #endif /* DP83820 */ 323 324 #ifdef SIP_EVENT_COUNTERS 325 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 326 #else 327 #define SIP_EVCNT_INCR(ev) /* nothing */ 328 #endif 329 330 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 331 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 332 333 #define SIP_CDTXSYNC(sc, x, n, ops) \ 334 do { \ 335 int __x, __n; \ 336 \ 337 __x = (x); \ 338 __n = (n); \ 339 \ 340 /* If it will wrap around, sync to the end of the ring. */ \ 341 if ((__x + __n) > SIP_NTXDESC) { \ 342 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 343 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 344 (SIP_NTXDESC - __x), (ops)); \ 345 __n -= (SIP_NTXDESC - __x); \ 346 __x = 0; \ 347 } \ 348 \ 349 /* Now sync whatever is left. */ \ 350 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 351 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 352 } while (0) 353 354 #define SIP_CDRXSYNC(sc, x, ops) \ 355 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 356 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 357 358 #ifdef DP83820 359 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 360 #define SIP_RXBUF_LEN (MCLBYTES - 4) 361 #else 362 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 363 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 364 #endif 365 #define SIP_INIT_RXDESC(sc, x) \ 366 do { \ 367 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 368 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 369 \ 370 __sipd->sipd_link = \ 371 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 372 __sipd->sipd_bufptr = \ 373 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 374 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 375 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 376 SIP_INIT_RXDESC_EXTSTS \ 377 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 378 } while (0) 379 380 #define SIP_CHIP_VERS(sc, v, p, r) \ 381 ((sc)->sc_model->sip_vendor == (v) && \ 382 (sc)->sc_model->sip_product == (p) && \ 383 (sc)->sc_rev == (r)) 384 385 #define SIP_CHIP_MODEL(sc, v, p) \ 386 ((sc)->sc_model->sip_vendor == (v) && \ 387 (sc)->sc_model->sip_product == (p)) 388 389 #if !defined(DP83820) 390 #define SIP_SIS900_REV(sc, rev) \ 391 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 392 #endif 393 394 #define SIP_TIMEOUT 1000 395 396 void SIP_DECL(start)(struct ifnet *); 397 void SIP_DECL(watchdog)(struct ifnet *); 398 int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 399 int SIP_DECL(init)(struct ifnet *); 400 void SIP_DECL(stop)(struct ifnet *, int); 401 402 void SIP_DECL(shutdown)(void *); 403 404 void SIP_DECL(reset)(struct sip_softc *); 405 void SIP_DECL(rxdrain)(struct sip_softc *); 406 int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 407 void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, u_int16_t *); 408 void SIP_DECL(tick)(void *); 409 410 #if !defined(DP83820) 411 void SIP_DECL(sis900_set_filter)(struct sip_softc *); 412 #endif /* ! DP83820 */ 413 void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 414 415 #if defined(DP83820) 416 void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 417 const struct pci_attach_args *, u_int8_t *); 418 #else 419 void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 420 const struct pci_attach_args *, u_int8_t *); 421 void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 422 const struct pci_attach_args *, u_int8_t *); 423 #endif /* DP83820 */ 424 425 int SIP_DECL(intr)(void *); 426 void SIP_DECL(txintr)(struct sip_softc *); 427 void SIP_DECL(rxintr)(struct sip_softc *); 428 429 #if defined(DP83820) 430 int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 431 void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 432 void SIP_DECL(dp83820_mii_statchg)(struct device *); 433 #else 434 int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 435 void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 436 void SIP_DECL(sis900_mii_statchg)(struct device *); 437 438 int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 439 void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 440 void SIP_DECL(dp83815_mii_statchg)(struct device *); 441 #endif /* DP83820 */ 442 443 int SIP_DECL(mediachange)(struct ifnet *); 444 void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 445 446 int SIP_DECL(match)(struct device *, struct cfdata *, void *); 447 void SIP_DECL(attach)(struct device *, struct device *, void *); 448 449 int SIP_DECL(copy_small) = 0; 450 451 struct cfattach SIP_DECL(ca) = { 452 sizeof(struct sip_softc), SIP_DECL(match), SIP_DECL(attach), 453 }; 454 455 /* 456 * Descriptions of the variants of the SiS900. 457 */ 458 struct sip_variant { 459 int (*sipv_mii_readreg)(struct device *, int, int); 460 void (*sipv_mii_writereg)(struct device *, int, int, int); 461 void (*sipv_mii_statchg)(struct device *); 462 void (*sipv_set_filter)(struct sip_softc *); 463 void (*sipv_read_macaddr)(struct sip_softc *, 464 const struct pci_attach_args *, u_int8_t *); 465 }; 466 467 #if defined(DP83820) 468 u_int32_t SIP_DECL(dp83820_mii_bitbang_read)(struct device *); 469 void SIP_DECL(dp83820_mii_bitbang_write)(struct device *, u_int32_t); 470 471 const struct mii_bitbang_ops SIP_DECL(dp83820_mii_bitbang_ops) = { 472 SIP_DECL(dp83820_mii_bitbang_read), 473 SIP_DECL(dp83820_mii_bitbang_write), 474 { 475 EROMAR_MDIO, /* MII_BIT_MDO */ 476 EROMAR_MDIO, /* MII_BIT_MDI */ 477 EROMAR_MDC, /* MII_BIT_MDC */ 478 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 479 0, /* MII_BIT_DIR_PHY_HOST */ 480 } 481 }; 482 #endif /* DP83820 */ 483 484 #if defined(DP83820) 485 const struct sip_variant SIP_DECL(variant_dp83820) = { 486 SIP_DECL(dp83820_mii_readreg), 487 SIP_DECL(dp83820_mii_writereg), 488 SIP_DECL(dp83820_mii_statchg), 489 SIP_DECL(dp83815_set_filter), 490 SIP_DECL(dp83820_read_macaddr), 491 }; 492 #else 493 const struct sip_variant SIP_DECL(variant_sis900) = { 494 SIP_DECL(sis900_mii_readreg), 495 SIP_DECL(sis900_mii_writereg), 496 SIP_DECL(sis900_mii_statchg), 497 SIP_DECL(sis900_set_filter), 498 SIP_DECL(sis900_read_macaddr), 499 }; 500 501 const struct sip_variant SIP_DECL(variant_dp83815) = { 502 SIP_DECL(dp83815_mii_readreg), 503 SIP_DECL(dp83815_mii_writereg), 504 SIP_DECL(dp83815_mii_statchg), 505 SIP_DECL(dp83815_set_filter), 506 SIP_DECL(dp83815_read_macaddr), 507 }; 508 #endif /* DP83820 */ 509 510 /* 511 * Devices supported by this driver. 512 */ 513 const struct sip_product { 514 pci_vendor_id_t sip_vendor; 515 pci_product_id_t sip_product; 516 const char *sip_name; 517 const struct sip_variant *sip_variant; 518 } SIP_DECL(products)[] = { 519 #if defined(DP83820) 520 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 521 "NatSemi DP83820 Gigabit Ethernet", 522 &SIP_DECL(variant_dp83820) }, 523 #else 524 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 525 "SiS 900 10/100 Ethernet", 526 &SIP_DECL(variant_sis900) }, 527 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 528 "SiS 7016 10/100 Ethernet", 529 &SIP_DECL(variant_sis900) }, 530 531 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 532 "NatSemi DP83815 10/100 Ethernet", 533 &SIP_DECL(variant_dp83815) }, 534 #endif /* DP83820 */ 535 536 { 0, 0, 537 NULL, 538 NULL }, 539 }; 540 541 static const struct sip_product * 542 SIP_DECL(lookup)(const struct pci_attach_args *pa) 543 { 544 const struct sip_product *sip; 545 546 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 547 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 548 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 549 return (sip); 550 } 551 return (NULL); 552 } 553 554 int 555 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 556 { 557 struct pci_attach_args *pa = aux; 558 559 if (SIP_DECL(lookup)(pa) != NULL) 560 return (1); 561 562 return (0); 563 } 564 565 void 566 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 567 { 568 struct sip_softc *sc = (struct sip_softc *) self; 569 struct pci_attach_args *pa = aux; 570 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 571 pci_chipset_tag_t pc = pa->pa_pc; 572 pci_intr_handle_t ih; 573 const char *intrstr = NULL; 574 bus_space_tag_t iot, memt; 575 bus_space_handle_t ioh, memh; 576 bus_dma_segment_t seg; 577 int ioh_valid, memh_valid; 578 int i, rseg, error; 579 const struct sip_product *sip; 580 pcireg_t pmode; 581 u_int8_t enaddr[ETHER_ADDR_LEN]; 582 int pmreg; 583 #ifdef DP83820 584 pcireg_t memtype; 585 u_int32_t reg; 586 #endif /* DP83820 */ 587 588 callout_init(&sc->sc_tick_ch); 589 590 sip = SIP_DECL(lookup)(pa); 591 if (sip == NULL) { 592 printf("\n"); 593 panic(SIP_STR(attach) ": impossible"); 594 } 595 sc->sc_rev = PCI_REVISION(pa->pa_class); 596 597 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 598 599 sc->sc_model = sip; 600 601 /* 602 * XXX Work-around broken PXE firmware on some boards. 603 * 604 * The DP83815 shares an address decoder with the MEM BAR 605 * and the ROM BAR. Make sure the ROM BAR is disabled, 606 * so that memory mapped access works. 607 */ 608 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 609 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 610 ~PCI_MAPREG_ROM_ENABLE); 611 612 /* 613 * Map the device. 614 */ 615 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 616 PCI_MAPREG_TYPE_IO, 0, 617 &iot, &ioh, NULL, NULL) == 0); 618 #ifdef DP83820 619 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 620 switch (memtype) { 621 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 622 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 623 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 624 memtype, 0, &memt, &memh, NULL, NULL) == 0); 625 break; 626 default: 627 memh_valid = 0; 628 } 629 #else 630 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 631 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 632 &memt, &memh, NULL, NULL) == 0); 633 #endif /* DP83820 */ 634 635 if (memh_valid) { 636 sc->sc_st = memt; 637 sc->sc_sh = memh; 638 } else if (ioh_valid) { 639 sc->sc_st = iot; 640 sc->sc_sh = ioh; 641 } else { 642 printf("%s: unable to map device registers\n", 643 sc->sc_dev.dv_xname); 644 return; 645 } 646 647 sc->sc_dmat = pa->pa_dmat; 648 649 /* 650 * Make sure bus mastering is enabled. Also make sure 651 * Write/Invalidate is enabled if we're allowed to use it. 652 */ 653 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 654 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 655 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 656 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 657 pmreg | PCI_COMMAND_MASTER_ENABLE); 658 659 /* Get it out of power save mode if needed. */ 660 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 661 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 662 if (pmode == 3) { 663 /* 664 * The card has lost all configuration data in 665 * this state, so punt. 666 */ 667 printf("%s: unable to wake up from power state D3\n", 668 sc->sc_dev.dv_xname); 669 return; 670 } 671 if (pmode != 0) { 672 printf("%s: waking up from power state D%d\n", 673 sc->sc_dev.dv_xname, pmode); 674 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 675 } 676 } 677 678 /* 679 * Map and establish our interrupt. 680 */ 681 if (pci_intr_map(pa, &ih)) { 682 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 683 return; 684 } 685 intrstr = pci_intr_string(pc, ih); 686 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 687 if (sc->sc_ih == NULL) { 688 printf("%s: unable to establish interrupt", 689 sc->sc_dev.dv_xname); 690 if (intrstr != NULL) 691 printf(" at %s", intrstr); 692 printf("\n"); 693 return; 694 } 695 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 696 697 SIMPLEQ_INIT(&sc->sc_txfreeq); 698 SIMPLEQ_INIT(&sc->sc_txdirtyq); 699 700 /* 701 * Allocate the control data structures, and create and load the 702 * DMA map for it. 703 */ 704 if ((error = bus_dmamem_alloc(sc->sc_dmat, 705 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 706 0)) != 0) { 707 printf("%s: unable to allocate control data, error = %d\n", 708 sc->sc_dev.dv_xname, error); 709 goto fail_0; 710 } 711 712 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 713 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 714 BUS_DMA_COHERENT)) != 0) { 715 printf("%s: unable to map control data, error = %d\n", 716 sc->sc_dev.dv_xname, error); 717 goto fail_1; 718 } 719 720 if ((error = bus_dmamap_create(sc->sc_dmat, 721 sizeof(struct sip_control_data), 1, 722 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 723 printf("%s: unable to create control data DMA map, " 724 "error = %d\n", sc->sc_dev.dv_xname, error); 725 goto fail_2; 726 } 727 728 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 729 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 730 0)) != 0) { 731 printf("%s: unable to load control data DMA map, error = %d\n", 732 sc->sc_dev.dv_xname, error); 733 goto fail_3; 734 } 735 736 /* 737 * Create the transmit buffer DMA maps. 738 */ 739 for (i = 0; i < SIP_TXQUEUELEN; i++) { 740 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 741 SIP_NTXSEGS, MCLBYTES, 0, 0, 742 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 743 printf("%s: unable to create tx DMA map %d, " 744 "error = %d\n", sc->sc_dev.dv_xname, i, error); 745 goto fail_4; 746 } 747 } 748 749 /* 750 * Create the receive buffer DMA maps. 751 */ 752 for (i = 0; i < SIP_NRXDESC; i++) { 753 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 754 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 755 printf("%s: unable to create rx DMA map %d, " 756 "error = %d\n", sc->sc_dev.dv_xname, i, error); 757 goto fail_5; 758 } 759 sc->sc_rxsoft[i].rxs_mbuf = NULL; 760 } 761 762 /* 763 * Reset the chip to a known state. 764 */ 765 SIP_DECL(reset)(sc); 766 767 /* 768 * Read the Ethernet address from the EEPROM. This might 769 * also fetch other stuff from the EEPROM and stash it 770 * in the softc. 771 */ 772 sc->sc_cfg = 0; 773 #if !defined(DP83820) 774 if (SIP_SIS900_REV(sc,SIS_REV_635) || 775 SIP_SIS900_REV(sc,SIS_REV_900B)) 776 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 777 #endif 778 779 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 780 781 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 782 ether_sprintf(enaddr)); 783 784 /* 785 * Initialize the configuration register: aggressive PCI 786 * bus request algorithm, default backoff, default OW timer, 787 * default parity error detection. 788 * 789 * NOTE: "Big endian mode" is useless on the SiS900 and 790 * friends -- it affects packet data, not descriptors. 791 */ 792 #ifdef DP83820 793 /* 794 * Cause the chip to load configuration data from the EEPROM. 795 */ 796 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 797 for (i = 0; i < 10000; i++) { 798 delay(10); 799 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 800 PTSCR_EELOAD_EN) == 0) 801 break; 802 } 803 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 804 PTSCR_EELOAD_EN) { 805 printf("%s: timeout loading configuration from EEPROM\n", 806 sc->sc_dev.dv_xname); 807 return; 808 } 809 810 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 811 if (reg & CFG_PCI64_DET) { 812 printf("%s: 64-bit PCI slot detected\n", sc->sc_dev.dv_xname); 813 if (reg & CFG_DATA64_EN) 814 sc->sc_cfg |= CFG_DATA64_EN; 815 else 816 printf("%s: 64-bit data transfers disabled in EEPROM\n", 817 sc->sc_dev.dv_xname); 818 } 819 820 /* 821 * XXX Need some PCI flags indicating support for 822 * XXX 64-bit addressing. 823 */ 824 #if 0 825 if (reg & CFG_M64ADDR) 826 sc->sc_cfg |= CFG_M64ADDR; 827 if (reg & CFG_T64ADDR) 828 sc->sc_cfg |= CFG_T64ADDR; 829 #endif 830 831 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 832 const char *sep = ""; 833 printf("%s: using ", sc->sc_dev.dv_xname); 834 if (reg & CFG_EXT_125) { 835 sc->sc_cfg |= CFG_EXT_125; 836 printf("%s125MHz clock", sep); 837 sep = ", "; 838 } 839 if (reg & CFG_TBI_EN) { 840 sc->sc_cfg |= CFG_TBI_EN; 841 printf("%sten-bit interface", sep); 842 sep = ", "; 843 } 844 printf("\n"); 845 } 846 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 847 (reg & CFG_MRM_DIS) != 0) 848 sc->sc_cfg |= CFG_MRM_DIS; 849 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 850 (reg & CFG_MWI_DIS) != 0) 851 sc->sc_cfg |= CFG_MWI_DIS; 852 853 /* 854 * Use the extended descriptor format on the DP83820. This 855 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 856 * checksumming. 857 */ 858 sc->sc_cfg |= CFG_EXTSTS_EN; 859 #endif /* DP83820 */ 860 861 /* 862 * Initialize our media structures and probe the MII. 863 */ 864 sc->sc_mii.mii_ifp = ifp; 865 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 866 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 867 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 868 ifmedia_init(&sc->sc_mii.mii_media, 0, SIP_DECL(mediachange), 869 SIP_DECL(mediastatus)); 870 #ifdef DP83820 871 if (sc->sc_cfg & CFG_TBI_EN) { 872 /* Using ten-bit interface. */ 873 printf("%s: TBI -- FIXME\n", sc->sc_dev.dv_xname); 874 } else { 875 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 876 MII_OFFSET_ANY, 0); 877 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 878 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 879 0, NULL); 880 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 881 } else 882 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 883 } 884 #else 885 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 886 MII_OFFSET_ANY, 0); 887 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 888 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 889 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 890 } else 891 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 892 #endif /* DP83820 */ 893 894 ifp = &sc->sc_ethercom.ec_if; 895 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 896 ifp->if_softc = sc; 897 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 898 ifp->if_ioctl = SIP_DECL(ioctl); 899 ifp->if_start = SIP_DECL(start); 900 ifp->if_watchdog = SIP_DECL(watchdog); 901 ifp->if_init = SIP_DECL(init); 902 ifp->if_stop = SIP_DECL(stop); 903 IFQ_SET_READY(&ifp->if_snd); 904 905 /* 906 * We can support 802.1Q VLAN-sized frames. 907 */ 908 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 909 910 #ifdef DP83820 911 /* 912 * And the DP83820 can do VLAN tagging in hardware, and 913 * support the jumbo Ethernet MTU. 914 */ 915 sc->sc_ethercom.ec_capabilities |= 916 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 917 918 /* 919 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 920 * in hardware. 921 */ 922 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 923 IFCAP_CSUM_UDPv4; 924 #endif /* DP83820 */ 925 926 /* 927 * Attach the interface. 928 */ 929 if_attach(ifp); 930 ether_ifattach(ifp, enaddr); 931 932 /* 933 * The number of bytes that must be available in 934 * the Tx FIFO before the bus master can DMA more 935 * data into the FIFO. 936 */ 937 sc->sc_tx_fill_thresh = 64 / 32; 938 939 /* 940 * Start at a drain threshold of 512 bytes. We will 941 * increase it if a DMA underrun occurs. 942 * 943 * XXX The minimum value of this variable should be 944 * tuned. We may be able to improve performance 945 * by starting with a lower value. That, however, 946 * may trash the first few outgoing packets if the 947 * PCI bus is saturated. 948 */ 949 sc->sc_tx_drain_thresh = 1504 / 32; 950 951 /* 952 * Initialize the Rx FIFO drain threshold. 953 * 954 * This is in units of 8 bytes. 955 * 956 * We should never set this value lower than 2; 14 bytes are 957 * required to filter the packet. 958 */ 959 sc->sc_rx_drain_thresh = 128 / 8; 960 961 #ifdef SIP_EVENT_COUNTERS 962 /* 963 * Attach event counters. 964 */ 965 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 966 NULL, sc->sc_dev.dv_xname, "txsstall"); 967 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 968 NULL, sc->sc_dev.dv_xname, "txdstall"); 969 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 970 NULL, sc->sc_dev.dv_xname, "txforceintr"); 971 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 972 NULL, sc->sc_dev.dv_xname, "txdintr"); 973 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 974 NULL, sc->sc_dev.dv_xname, "txiintr"); 975 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 976 NULL, sc->sc_dev.dv_xname, "rxintr"); 977 #ifdef DP83820 978 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 979 NULL, sc->sc_dev.dv_xname, "rxipsum"); 980 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 981 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 982 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 983 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 984 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 985 NULL, sc->sc_dev.dv_xname, "txipsum"); 986 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 987 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 988 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 989 NULL, sc->sc_dev.dv_xname, "txudpsum"); 990 #endif /* DP83820 */ 991 #endif /* SIP_EVENT_COUNTERS */ 992 993 /* 994 * Make sure the interface is shutdown during reboot. 995 */ 996 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 997 if (sc->sc_sdhook == NULL) 998 printf("%s: WARNING: unable to establish shutdown hook\n", 999 sc->sc_dev.dv_xname); 1000 return; 1001 1002 /* 1003 * Free any resources we've allocated during the failed attach 1004 * attempt. Do this in reverse order and fall through. 1005 */ 1006 fail_5: 1007 for (i = 0; i < SIP_NRXDESC; i++) { 1008 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1009 bus_dmamap_destroy(sc->sc_dmat, 1010 sc->sc_rxsoft[i].rxs_dmamap); 1011 } 1012 fail_4: 1013 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1014 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1015 bus_dmamap_destroy(sc->sc_dmat, 1016 sc->sc_txsoft[i].txs_dmamap); 1017 } 1018 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1019 fail_3: 1020 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1021 fail_2: 1022 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1023 sizeof(struct sip_control_data)); 1024 fail_1: 1025 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1026 fail_0: 1027 return; 1028 } 1029 1030 /* 1031 * sip_shutdown: 1032 * 1033 * Make sure the interface is stopped at reboot time. 1034 */ 1035 void 1036 SIP_DECL(shutdown)(void *arg) 1037 { 1038 struct sip_softc *sc = arg; 1039 1040 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1041 } 1042 1043 /* 1044 * sip_start: [ifnet interface function] 1045 * 1046 * Start packet transmission on the interface. 1047 */ 1048 void 1049 SIP_DECL(start)(struct ifnet *ifp) 1050 { 1051 struct sip_softc *sc = ifp->if_softc; 1052 struct mbuf *m0, *m; 1053 struct sip_txsoft *txs; 1054 bus_dmamap_t dmamap; 1055 int error, firsttx, nexttx, lasttx, ofree, seg; 1056 #ifdef DP83820 1057 u_int32_t extsts; 1058 #endif 1059 1060 /* 1061 * If we've been told to pause, don't transmit any more packets. 1062 */ 1063 if (sc->sc_flags & SIPF_PAUSED) 1064 ifp->if_flags |= IFF_OACTIVE; 1065 1066 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1067 return; 1068 1069 /* 1070 * Remember the previous number of free descriptors and 1071 * the first descriptor we'll use. 1072 */ 1073 ofree = sc->sc_txfree; 1074 firsttx = sc->sc_txnext; 1075 1076 /* 1077 * Loop through the send queue, setting up transmit descriptors 1078 * until we drain the queue, or use up all available transmit 1079 * descriptors. 1080 */ 1081 for (;;) { 1082 /* Get a work queue entry. */ 1083 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1084 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1085 break; 1086 } 1087 1088 /* 1089 * Grab a packet off the queue. 1090 */ 1091 IFQ_POLL(&ifp->if_snd, m0); 1092 if (m0 == NULL) 1093 break; 1094 #ifndef DP83820 1095 m = NULL; 1096 #endif 1097 1098 dmamap = txs->txs_dmamap; 1099 1100 #ifdef DP83820 1101 /* 1102 * Load the DMA map. If this fails, the packet either 1103 * didn't fit in the allotted number of segments, or we 1104 * were short on resources. For the too-many-segments 1105 * case, we simply report an error and drop the packet, 1106 * since we can't sanely copy a jumbo packet to a single 1107 * buffer. 1108 */ 1109 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1110 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1111 if (error) { 1112 if (error == EFBIG) { 1113 printf("%s: Tx packet consumes too many " 1114 "DMA segments, dropping...\n", 1115 sc->sc_dev.dv_xname); 1116 IFQ_DEQUEUE(&ifp->if_snd, m0); 1117 m_freem(m0); 1118 continue; 1119 } 1120 /* 1121 * Short on resources, just stop for now. 1122 */ 1123 break; 1124 } 1125 #else /* DP83820 */ 1126 /* 1127 * Load the DMA map. If this fails, the packet either 1128 * didn't fit in the alloted number of segments, or we 1129 * were short on resources. In this case, we'll copy 1130 * and try again. 1131 */ 1132 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1133 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1134 MGETHDR(m, M_DONTWAIT, MT_DATA); 1135 if (m == NULL) { 1136 printf("%s: unable to allocate Tx mbuf\n", 1137 sc->sc_dev.dv_xname); 1138 break; 1139 } 1140 if (m0->m_pkthdr.len > MHLEN) { 1141 MCLGET(m, M_DONTWAIT); 1142 if ((m->m_flags & M_EXT) == 0) { 1143 printf("%s: unable to allocate Tx " 1144 "cluster\n", sc->sc_dev.dv_xname); 1145 m_freem(m); 1146 break; 1147 } 1148 } 1149 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1150 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1151 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1152 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1153 if (error) { 1154 printf("%s: unable to load Tx buffer, " 1155 "error = %d\n", sc->sc_dev.dv_xname, error); 1156 break; 1157 } 1158 } 1159 #endif /* DP83820 */ 1160 1161 /* 1162 * Ensure we have enough descriptors free to describe 1163 * the packet. Note, we always reserve one descriptor 1164 * at the end of the ring as a termination point, to 1165 * prevent wrap-around. 1166 */ 1167 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1168 /* 1169 * Not enough free descriptors to transmit this 1170 * packet. We haven't committed anything yet, 1171 * so just unload the DMA map, put the packet 1172 * back on the queue, and punt. Notify the upper 1173 * layer that there are not more slots left. 1174 * 1175 * XXX We could allocate an mbuf and copy, but 1176 * XXX is it worth it? 1177 */ 1178 ifp->if_flags |= IFF_OACTIVE; 1179 bus_dmamap_unload(sc->sc_dmat, dmamap); 1180 #ifndef DP83820 1181 if (m != NULL) 1182 m_freem(m); 1183 #endif 1184 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1185 break; 1186 } 1187 1188 IFQ_DEQUEUE(&ifp->if_snd, m0); 1189 #ifndef DP83820 1190 if (m != NULL) { 1191 m_freem(m0); 1192 m0 = m; 1193 } 1194 #endif 1195 1196 /* 1197 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1198 */ 1199 1200 /* Sync the DMA map. */ 1201 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1202 BUS_DMASYNC_PREWRITE); 1203 1204 /* 1205 * Initialize the transmit descriptors. 1206 */ 1207 for (nexttx = sc->sc_txnext, seg = 0; 1208 seg < dmamap->dm_nsegs; 1209 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1210 /* 1211 * If this is the first descriptor we're 1212 * enqueueing, don't set the OWN bit just 1213 * yet. That could cause a race condition. 1214 * We'll do it below. 1215 */ 1216 sc->sc_txdescs[nexttx].sipd_bufptr = 1217 htole32(dmamap->dm_segs[seg].ds_addr); 1218 sc->sc_txdescs[nexttx].sipd_cmdsts = 1219 htole32((nexttx == firsttx ? 0 : CMDSTS_OWN) | 1220 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1221 #ifdef DP83820 1222 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1223 #endif /* DP83820 */ 1224 lasttx = nexttx; 1225 } 1226 1227 /* Clear the MORE bit on the last segment. */ 1228 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1229 1230 /* 1231 * If we're in the interrupt delay window, delay the 1232 * interrupt. 1233 */ 1234 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1235 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1236 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1237 htole32(CMDSTS_INTR); 1238 sc->sc_txwin = 0; 1239 } 1240 1241 #ifdef DP83820 1242 /* 1243 * If VLANs are enabled and the packet has a VLAN tag, set 1244 * up the descriptor to encapsulate the packet for us. 1245 * 1246 * This apparently has to be on the last descriptor of 1247 * the packet. 1248 */ 1249 if (sc->sc_ethercom.ec_nvlans != 0 && 1250 (m = m_aux_find(m0, AF_LINK, ETHERTYPE_VLAN)) != NULL) { 1251 sc->sc_txdescs[lasttx].sipd_extsts |= 1252 htole32(EXTSTS_VPKT | 1253 htons(*mtod(m, int *) & EXTSTS_VTCI)); 1254 } 1255 1256 /* 1257 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1258 * checksumming, set up the descriptor to do this work 1259 * for us. 1260 * 1261 * This apparently has to be on the first descriptor of 1262 * the packet. 1263 * 1264 * Byte-swap constants so the compiler can optimize. 1265 */ 1266 extsts = 0; 1267 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1268 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1269 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1270 extsts |= htole32(EXTSTS_IPPKT); 1271 } 1272 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1273 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1274 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1275 extsts |= htole32(EXTSTS_TCPPKT); 1276 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1277 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1278 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1279 extsts |= htole32(EXTSTS_UDPPKT); 1280 } 1281 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1282 #endif /* DP83820 */ 1283 1284 /* Sync the descriptors we're using. */ 1285 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1286 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1287 1288 /* 1289 * Store a pointer to the packet so we can free it later, 1290 * and remember what txdirty will be once the packet is 1291 * done. 1292 */ 1293 txs->txs_mbuf = m0; 1294 txs->txs_firstdesc = sc->sc_txnext; 1295 txs->txs_lastdesc = lasttx; 1296 1297 /* Advance the tx pointer. */ 1298 sc->sc_txfree -= dmamap->dm_nsegs; 1299 sc->sc_txnext = nexttx; 1300 1301 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs, txs_q); 1302 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1303 1304 #if NBPFILTER > 0 1305 /* 1306 * Pass the packet to any BPF listeners. 1307 */ 1308 if (ifp->if_bpf) 1309 bpf_mtap(ifp->if_bpf, m0); 1310 #endif /* NBPFILTER > 0 */ 1311 } 1312 1313 if (txs == NULL || sc->sc_txfree == 0) { 1314 /* No more slots left; notify upper layer. */ 1315 ifp->if_flags |= IFF_OACTIVE; 1316 } 1317 1318 if (sc->sc_txfree != ofree) { 1319 /* 1320 * The entire packet chain is set up. Give the 1321 * first descrptor to the chip now. 1322 */ 1323 sc->sc_txdescs[firsttx].sipd_cmdsts |= htole32(CMDSTS_OWN); 1324 SIP_CDTXSYNC(sc, firsttx, 1, 1325 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1326 1327 /* 1328 * Start the transmit process. Note, the manual says 1329 * that if there are no pending transmissions in the 1330 * chip's internal queue (indicated by TXE being clear), 1331 * then the driver software must set the TXDP to the 1332 * first descriptor to be transmitted. However, if we 1333 * do this, it causes serious performance degredation on 1334 * the DP83820 under load, not setting TXDP doesn't seem 1335 * to adversely affect the SiS 900 or DP83815. 1336 * 1337 * Well, I guess it wouldn't be the first time a manual 1338 * has lied -- and they could be speaking of the NULL- 1339 * terminated descriptor list case, rather than OWN- 1340 * terminated rings. 1341 */ 1342 #if 0 1343 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1344 CR_TXE) == 0) { 1345 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1346 SIP_CDTXADDR(sc, firsttx)); 1347 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1348 } 1349 #else 1350 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1351 #endif 1352 1353 /* Set a watchdog timer in case the chip flakes out. */ 1354 ifp->if_timer = 5; 1355 } 1356 } 1357 1358 /* 1359 * sip_watchdog: [ifnet interface function] 1360 * 1361 * Watchdog timer handler. 1362 */ 1363 void 1364 SIP_DECL(watchdog)(struct ifnet *ifp) 1365 { 1366 struct sip_softc *sc = ifp->if_softc; 1367 1368 /* 1369 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1370 * If we get a timeout, try and sweep up transmit descriptors. 1371 * If we manage to sweep them all up, ignore the lack of 1372 * interrupt. 1373 */ 1374 SIP_DECL(txintr)(sc); 1375 1376 if (sc->sc_txfree != SIP_NTXDESC) { 1377 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1378 ifp->if_oerrors++; 1379 1380 /* Reset the interface. */ 1381 (void) SIP_DECL(init)(ifp); 1382 } else if (ifp->if_flags & IFF_DEBUG) 1383 printf("%s: recovered from device timeout\n", 1384 sc->sc_dev.dv_xname); 1385 1386 /* Try to get more packets going. */ 1387 SIP_DECL(start)(ifp); 1388 } 1389 1390 /* 1391 * sip_ioctl: [ifnet interface function] 1392 * 1393 * Handle control requests from the operator. 1394 */ 1395 int 1396 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1397 { 1398 struct sip_softc *sc = ifp->if_softc; 1399 struct ifreq *ifr = (struct ifreq *)data; 1400 int s, error; 1401 1402 s = splnet(); 1403 1404 switch (cmd) { 1405 case SIOCSIFMEDIA: 1406 case SIOCGIFMEDIA: 1407 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1408 break; 1409 1410 default: 1411 error = ether_ioctl(ifp, cmd, data); 1412 if (error == ENETRESET) { 1413 /* 1414 * Multicast list has changed; set the hardware filter 1415 * accordingly. 1416 */ 1417 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1418 error = 0; 1419 } 1420 break; 1421 } 1422 1423 /* Try to get more packets going. */ 1424 SIP_DECL(start)(ifp); 1425 1426 splx(s); 1427 return (error); 1428 } 1429 1430 /* 1431 * sip_intr: 1432 * 1433 * Interrupt service routine. 1434 */ 1435 int 1436 SIP_DECL(intr)(void *arg) 1437 { 1438 struct sip_softc *sc = arg; 1439 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1440 u_int32_t isr; 1441 int handled = 0; 1442 1443 for (;;) { 1444 /* Reading clears interrupt. */ 1445 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1446 if ((isr & sc->sc_imr) == 0) 1447 break; 1448 1449 handled = 1; 1450 1451 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1452 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1453 1454 /* Grab any new packets. */ 1455 SIP_DECL(rxintr)(sc); 1456 1457 if (isr & ISR_RXORN) { 1458 printf("%s: receive FIFO overrun\n", 1459 sc->sc_dev.dv_xname); 1460 1461 /* XXX adjust rx_drain_thresh? */ 1462 } 1463 1464 if (isr & ISR_RXIDLE) { 1465 printf("%s: receive ring overrun\n", 1466 sc->sc_dev.dv_xname); 1467 1468 /* Get the receive process going again. */ 1469 bus_space_write_4(sc->sc_st, sc->sc_sh, 1470 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1471 bus_space_write_4(sc->sc_st, sc->sc_sh, 1472 SIP_CR, CR_RXE); 1473 } 1474 } 1475 1476 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1477 #ifdef SIP_EVENT_COUNTERS 1478 if (isr & ISR_TXDESC) 1479 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1480 else if (isr & ISR_TXIDLE) 1481 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1482 #endif 1483 1484 /* Sweep up transmit descriptors. */ 1485 SIP_DECL(txintr)(sc); 1486 1487 if (isr & ISR_TXURN) { 1488 u_int32_t thresh; 1489 1490 printf("%s: transmit FIFO underrun", 1491 sc->sc_dev.dv_xname); 1492 1493 thresh = sc->sc_tx_drain_thresh + 1; 1494 if (thresh <= TXCFG_DRTH && 1495 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1496 (sc->sc_tx_fill_thresh * 32))) { 1497 printf("; increasing Tx drain " 1498 "threshold to %u bytes\n", 1499 thresh * 32); 1500 sc->sc_tx_drain_thresh = thresh; 1501 (void) SIP_DECL(init)(ifp); 1502 } else { 1503 (void) SIP_DECL(init)(ifp); 1504 printf("\n"); 1505 } 1506 } 1507 } 1508 1509 #if !defined(DP83820) 1510 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1511 if (isr & ISR_PAUSE_ST) { 1512 sc->sc_flags |= SIPF_PAUSED; 1513 ifp->if_flags |= IFF_OACTIVE; 1514 } 1515 if (isr & ISR_PAUSE_END) { 1516 sc->sc_flags &= ~SIPF_PAUSED; 1517 ifp->if_flags &= ~IFF_OACTIVE; 1518 } 1519 } 1520 #endif /* ! DP83820 */ 1521 1522 if (isr & ISR_HIBERR) { 1523 #define PRINTERR(bit, str) \ 1524 if (isr & (bit)) \ 1525 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1526 PRINTERR(ISR_DPERR, "parity error"); 1527 PRINTERR(ISR_SSERR, "system error"); 1528 PRINTERR(ISR_RMABT, "master abort"); 1529 PRINTERR(ISR_RTABT, "target abort"); 1530 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1531 (void) SIP_DECL(init)(ifp); 1532 #undef PRINTERR 1533 } 1534 } 1535 1536 /* Try to get more packets going. */ 1537 SIP_DECL(start)(ifp); 1538 1539 return (handled); 1540 } 1541 1542 /* 1543 * sip_txintr: 1544 * 1545 * Helper; handle transmit interrupts. 1546 */ 1547 void 1548 SIP_DECL(txintr)(struct sip_softc *sc) 1549 { 1550 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1551 struct sip_txsoft *txs; 1552 u_int32_t cmdsts; 1553 1554 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1555 ifp->if_flags &= ~IFF_OACTIVE; 1556 1557 /* 1558 * Go through our Tx list and free mbufs for those 1559 * frames which have been transmitted. 1560 */ 1561 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1562 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1563 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1564 1565 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1566 if (cmdsts & CMDSTS_OWN) 1567 break; 1568 1569 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1570 1571 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1572 1573 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1574 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1575 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1576 m_freem(txs->txs_mbuf); 1577 txs->txs_mbuf = NULL; 1578 1579 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1580 1581 /* 1582 * Check for errors and collisions. 1583 */ 1584 if (cmdsts & 1585 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1586 ifp->if_oerrors++; 1587 if (cmdsts & CMDSTS_Tx_EC) 1588 ifp->if_collisions += 16; 1589 if (ifp->if_flags & IFF_DEBUG) { 1590 if (cmdsts & CMDSTS_Tx_ED) 1591 printf("%s: excessive deferral\n", 1592 sc->sc_dev.dv_xname); 1593 if (cmdsts & CMDSTS_Tx_EC) 1594 printf("%s: excessive collisions\n", 1595 sc->sc_dev.dv_xname); 1596 } 1597 } else { 1598 /* Packet was transmitted successfully. */ 1599 ifp->if_opackets++; 1600 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1601 } 1602 } 1603 1604 /* 1605 * If there are no more pending transmissions, cancel the watchdog 1606 * timer. 1607 */ 1608 if (txs == NULL) { 1609 ifp->if_timer = 0; 1610 sc->sc_txwin = 0; 1611 } 1612 } 1613 1614 #if defined(DP83820) 1615 /* 1616 * sip_rxintr: 1617 * 1618 * Helper; handle receive interrupts. 1619 */ 1620 void 1621 SIP_DECL(rxintr)(struct sip_softc *sc) 1622 { 1623 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1624 struct sip_rxsoft *rxs; 1625 struct mbuf *m, *tailm; 1626 u_int32_t cmdsts, extsts; 1627 int i, len; 1628 1629 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1630 rxs = &sc->sc_rxsoft[i]; 1631 1632 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1633 1634 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1635 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1636 1637 /* 1638 * NOTE: OWN is set if owned by _consumer_. We're the 1639 * consumer of the receive ring, so if the bit is clear, 1640 * we have processed all of the packets. 1641 */ 1642 if ((cmdsts & CMDSTS_OWN) == 0) { 1643 /* 1644 * We have processed all of the receive buffers. 1645 */ 1646 break; 1647 } 1648 1649 if (__predict_false(sc->sc_rxdiscard)) { 1650 SIP_INIT_RXDESC(sc, i); 1651 if ((cmdsts & CMDSTS_MORE) == 0) { 1652 /* Reset our state. */ 1653 sc->sc_rxdiscard = 0; 1654 } 1655 continue; 1656 } 1657 1658 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1659 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1660 1661 m = rxs->rxs_mbuf; 1662 1663 /* 1664 * Add a new receive buffer to the ring. 1665 */ 1666 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1667 /* 1668 * Failed, throw away what we've done so 1669 * far, and discard the rest of the packet. 1670 */ 1671 ifp->if_ierrors++; 1672 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1673 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1674 SIP_INIT_RXDESC(sc, i); 1675 if (cmdsts & CMDSTS_MORE) 1676 sc->sc_rxdiscard = 1; 1677 if (sc->sc_rxhead != NULL) 1678 m_freem(sc->sc_rxhead); 1679 SIP_RXCHAIN_RESET(sc); 1680 continue; 1681 } 1682 1683 SIP_RXCHAIN_LINK(sc, m); 1684 1685 /* 1686 * If this is not the end of the packet, keep 1687 * looking. 1688 */ 1689 if (cmdsts & CMDSTS_MORE) { 1690 sc->sc_rxlen += m->m_len; 1691 continue; 1692 } 1693 1694 /* 1695 * Okay, we have the entire packet now... 1696 */ 1697 *sc->sc_rxtailp = NULL; 1698 m = sc->sc_rxhead; 1699 tailm = sc->sc_rxtail; 1700 1701 SIP_RXCHAIN_RESET(sc); 1702 1703 /* 1704 * If an error occurred, update stats and drop the packet. 1705 */ 1706 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1707 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1708 ifp->if_ierrors++; 1709 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1710 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1711 /* Receive overrun handled elsewhere. */ 1712 printf("%s: receive descriptor error\n", 1713 sc->sc_dev.dv_xname); 1714 } 1715 #define PRINTERR(bit, str) \ 1716 if (cmdsts & (bit)) \ 1717 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1718 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1719 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1720 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1721 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1722 #undef PRINTERR 1723 m_freem(m); 1724 continue; 1725 } 1726 1727 /* 1728 * No errors. 1729 * 1730 * Note, the DP83820 includes the CRC with 1731 * every packet. 1732 */ 1733 len = CMDSTS_SIZE(cmdsts); 1734 tailm->m_len = len - sc->sc_rxlen; 1735 1736 /* 1737 * If the packet is small enough to fit in a 1738 * single header mbuf, allocate one and copy 1739 * the data into it. This greatly reduces 1740 * memory consumption when we receive lots 1741 * of small packets. 1742 */ 1743 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1744 struct mbuf *nm; 1745 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1746 if (nm == NULL) { 1747 ifp->if_ierrors++; 1748 m_freem(m); 1749 continue; 1750 } 1751 nm->m_data += 2; 1752 nm->m_pkthdr.len = nm->m_len = len; 1753 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1754 m_freem(m); 1755 m = nm; 1756 } 1757 #ifndef __NO_STRICT_ALIGNMENT 1758 else { 1759 /* 1760 * The DP83820's receive buffers must be 4-byte 1761 * aligned. But this means that the data after 1762 * the Ethernet header is misaligned. To compensate, 1763 * we have artificially shortened the buffer size 1764 * in the descriptor, and we do an overlapping copy 1765 * of the data two bytes further in (in the first 1766 * buffer of the chain only). 1767 */ 1768 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1769 m->m_len); 1770 m->m_data += 2; 1771 } 1772 #endif /* ! __NO_STRICT_ALIGNMENT */ 1773 1774 /* 1775 * If VLANs are enabled, VLAN packets have been unwrapped 1776 * for us. Associate the tag with the packet. 1777 */ 1778 if (sc->sc_ethercom.ec_nvlans != 0 && 1779 (extsts & EXTSTS_VPKT) != 0) { 1780 struct mbuf *vtag; 1781 1782 vtag = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 1783 if (vtag == NULL) { 1784 ifp->if_ierrors++; 1785 printf("%s: unable to allocate VLAN tag\n", 1786 sc->sc_dev.dv_xname); 1787 m_freem(m); 1788 continue; 1789 } 1790 1791 *mtod(vtag, int *) = ntohs(extsts & EXTSTS_VTCI); 1792 vtag->m_len = sizeof(int); 1793 } 1794 1795 /* 1796 * Set the incoming checksum information for the 1797 * packet. 1798 */ 1799 if ((extsts & EXTSTS_IPPKT) != 0) { 1800 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1801 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1802 if (extsts & EXTSTS_Rx_IPERR) 1803 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1804 if (extsts & EXTSTS_TCPPKT) { 1805 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1806 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1807 if (extsts & EXTSTS_Rx_TCPERR) 1808 m->m_pkthdr.csum_flags |= 1809 M_CSUM_TCP_UDP_BAD; 1810 } else if (extsts & EXTSTS_UDPPKT) { 1811 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1812 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1813 if (extsts & EXTSTS_Rx_UDPERR) 1814 m->m_pkthdr.csum_flags |= 1815 M_CSUM_TCP_UDP_BAD; 1816 } 1817 } 1818 1819 ifp->if_ipackets++; 1820 m->m_flags |= M_HASFCS; 1821 m->m_pkthdr.rcvif = ifp; 1822 m->m_pkthdr.len = len; 1823 1824 #if NBPFILTER > 0 1825 /* 1826 * Pass this up to any BPF listeners, but only 1827 * pass if up the stack if it's for us. 1828 */ 1829 if (ifp->if_bpf) 1830 bpf_mtap(ifp->if_bpf, m); 1831 #endif /* NBPFILTER > 0 */ 1832 1833 /* Pass it on. */ 1834 (*ifp->if_input)(ifp, m); 1835 } 1836 1837 /* Update the receive pointer. */ 1838 sc->sc_rxptr = i; 1839 } 1840 #else /* ! DP83820 */ 1841 /* 1842 * sip_rxintr: 1843 * 1844 * Helper; handle receive interrupts. 1845 */ 1846 void 1847 SIP_DECL(rxintr)(struct sip_softc *sc) 1848 { 1849 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1850 struct sip_rxsoft *rxs; 1851 struct mbuf *m; 1852 u_int32_t cmdsts; 1853 int i, len; 1854 1855 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1856 rxs = &sc->sc_rxsoft[i]; 1857 1858 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1859 1860 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1861 1862 /* 1863 * NOTE: OWN is set if owned by _consumer_. We're the 1864 * consumer of the receive ring, so if the bit is clear, 1865 * we have processed all of the packets. 1866 */ 1867 if ((cmdsts & CMDSTS_OWN) == 0) { 1868 /* 1869 * We have processed all of the receive buffers. 1870 */ 1871 break; 1872 } 1873 1874 /* 1875 * If any collisions were seen on the wire, count one. 1876 */ 1877 if (cmdsts & CMDSTS_Rx_COL) 1878 ifp->if_collisions++; 1879 1880 /* 1881 * If an error occurred, update stats, clear the status 1882 * word, and leave the packet buffer in place. It will 1883 * simply be reused the next time the ring comes around. 1884 */ 1885 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1886 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1887 ifp->if_ierrors++; 1888 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1889 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1890 /* Receive overrun handled elsewhere. */ 1891 printf("%s: receive descriptor error\n", 1892 sc->sc_dev.dv_xname); 1893 } 1894 #define PRINTERR(bit, str) \ 1895 if (cmdsts & (bit)) \ 1896 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1897 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1898 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1899 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1900 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1901 #undef PRINTERR 1902 SIP_INIT_RXDESC(sc, i); 1903 continue; 1904 } 1905 1906 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1907 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1908 1909 /* 1910 * No errors; receive the packet. Note, the SiS 900 1911 * includes the CRC with every packet. 1912 */ 1913 len = CMDSTS_SIZE(cmdsts); 1914 1915 #ifdef __NO_STRICT_ALIGNMENT 1916 /* 1917 * If the packet is small enough to fit in a 1918 * single header mbuf, allocate one and copy 1919 * the data into it. This greatly reduces 1920 * memory consumption when we receive lots 1921 * of small packets. 1922 * 1923 * Otherwise, we add a new buffer to the receive 1924 * chain. If this fails, we drop the packet and 1925 * recycle the old buffer. 1926 */ 1927 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 1928 MGETHDR(m, M_DONTWAIT, MT_DATA); 1929 if (m == NULL) 1930 goto dropit; 1931 memcpy(mtod(m, caddr_t), 1932 mtod(rxs->rxs_mbuf, caddr_t), len); 1933 SIP_INIT_RXDESC(sc, i); 1934 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1935 rxs->rxs_dmamap->dm_mapsize, 1936 BUS_DMASYNC_PREREAD); 1937 } else { 1938 m = rxs->rxs_mbuf; 1939 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1940 dropit: 1941 ifp->if_ierrors++; 1942 SIP_INIT_RXDESC(sc, i); 1943 bus_dmamap_sync(sc->sc_dmat, 1944 rxs->rxs_dmamap, 0, 1945 rxs->rxs_dmamap->dm_mapsize, 1946 BUS_DMASYNC_PREREAD); 1947 continue; 1948 } 1949 } 1950 #else 1951 /* 1952 * The SiS 900's receive buffers must be 4-byte aligned. 1953 * But this means that the data after the Ethernet header 1954 * is misaligned. We must allocate a new buffer and 1955 * copy the data, shifted forward 2 bytes. 1956 */ 1957 MGETHDR(m, M_DONTWAIT, MT_DATA); 1958 if (m == NULL) { 1959 dropit: 1960 ifp->if_ierrors++; 1961 SIP_INIT_RXDESC(sc, i); 1962 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1963 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1964 continue; 1965 } 1966 if (len > (MHLEN - 2)) { 1967 MCLGET(m, M_DONTWAIT); 1968 if ((m->m_flags & M_EXT) == 0) { 1969 m_freem(m); 1970 goto dropit; 1971 } 1972 } 1973 m->m_data += 2; 1974 1975 /* 1976 * Note that we use clusters for incoming frames, so the 1977 * buffer is virtually contiguous. 1978 */ 1979 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 1980 1981 /* Allow the receive descriptor to continue using its mbuf. */ 1982 SIP_INIT_RXDESC(sc, i); 1983 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1984 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1985 #endif /* __NO_STRICT_ALIGNMENT */ 1986 1987 ifp->if_ipackets++; 1988 m->m_flags |= M_HASFCS; 1989 m->m_pkthdr.rcvif = ifp; 1990 m->m_pkthdr.len = m->m_len = len; 1991 1992 #if NBPFILTER > 0 1993 /* 1994 * Pass this up to any BPF listeners, but only 1995 * pass if up the stack if it's for us. 1996 */ 1997 if (ifp->if_bpf) 1998 bpf_mtap(ifp->if_bpf, m); 1999 #endif /* NBPFILTER > 0 */ 2000 2001 /* Pass it on. */ 2002 (*ifp->if_input)(ifp, m); 2003 } 2004 2005 /* Update the receive pointer. */ 2006 sc->sc_rxptr = i; 2007 } 2008 #endif /* DP83820 */ 2009 2010 /* 2011 * sip_tick: 2012 * 2013 * One second timer, used to tick the MII. 2014 */ 2015 void 2016 SIP_DECL(tick)(void *arg) 2017 { 2018 struct sip_softc *sc = arg; 2019 int s; 2020 2021 s = splnet(); 2022 mii_tick(&sc->sc_mii); 2023 splx(s); 2024 2025 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2026 } 2027 2028 /* 2029 * sip_reset: 2030 * 2031 * Perform a soft reset on the SiS 900. 2032 */ 2033 void 2034 SIP_DECL(reset)(struct sip_softc *sc) 2035 { 2036 bus_space_tag_t st = sc->sc_st; 2037 bus_space_handle_t sh = sc->sc_sh; 2038 int i; 2039 2040 bus_space_write_4(st, sh, SIP_IER, 0); 2041 bus_space_write_4(st, sh, SIP_IMR, 0); 2042 bus_space_write_4(st, sh, SIP_RFCR, 0); 2043 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2044 2045 for (i = 0; i < SIP_TIMEOUT; i++) { 2046 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2047 break; 2048 delay(2); 2049 } 2050 2051 if (i == SIP_TIMEOUT) 2052 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2053 2054 delay(1000); 2055 2056 #ifdef DP83820 2057 /* 2058 * Set the general purpose I/O bits. Do it here in case we 2059 * need to have GPIO set up to talk to the media interface. 2060 */ 2061 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2062 delay(1000); 2063 #endif /* DP83820 */ 2064 } 2065 2066 /* 2067 * sip_init: [ ifnet interface function ] 2068 * 2069 * Initialize the interface. Must be called at splnet(). 2070 */ 2071 int 2072 SIP_DECL(init)(struct ifnet *ifp) 2073 { 2074 struct sip_softc *sc = ifp->if_softc; 2075 bus_space_tag_t st = sc->sc_st; 2076 bus_space_handle_t sh = sc->sc_sh; 2077 struct sip_txsoft *txs; 2078 struct sip_rxsoft *rxs; 2079 struct sip_desc *sipd; 2080 u_int32_t reg; 2081 int i, error = 0; 2082 2083 /* 2084 * Cancel any pending I/O. 2085 */ 2086 SIP_DECL(stop)(ifp, 0); 2087 2088 /* 2089 * Reset the chip to a known state. 2090 */ 2091 SIP_DECL(reset)(sc); 2092 2093 #if !defined(DP83820) 2094 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2095 /* 2096 * DP83815 manual, page 78: 2097 * 4.4 Recommended Registers Configuration 2098 * For optimum performance of the DP83815, version noted 2099 * as DP83815CVNG (SRR = 203h), the listed register 2100 * modifications must be followed in sequence... 2101 * 2102 * It's not clear if this should be 302h or 203h because that 2103 * chip name is listed as SRR 302h in the description of the 2104 * SRR register. However, my revision 302h DP83815 on the 2105 * Netgear FA311 purchased in 02/2001 needs these settings 2106 * to avoid tons of errors in AcceptPerfectMatch (non- 2107 * IFF_PROMISC) mode. I do not know if other revisions need 2108 * this set or not. [briggs -- 09 March 2001] 2109 * 2110 * Note that only the low-order 12 bits of 0xe4 are documented 2111 * and that this sets reserved bits in that register. 2112 */ 2113 reg = bus_space_read_4(st, sh, SIP_NS_SRR); 2114 if (reg == 0x302) { 2115 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2116 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2117 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2118 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2119 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2120 } 2121 } 2122 #endif /* ! DP83820 */ 2123 2124 /* 2125 * Initialize the transmit descriptor ring. 2126 */ 2127 for (i = 0; i < SIP_NTXDESC; i++) { 2128 sipd = &sc->sc_txdescs[i]; 2129 memset(sipd, 0, sizeof(struct sip_desc)); 2130 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2131 } 2132 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2133 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2134 sc->sc_txfree = SIP_NTXDESC; 2135 sc->sc_txnext = 0; 2136 sc->sc_txwin = 0; 2137 2138 /* 2139 * Initialize the transmit job descriptors. 2140 */ 2141 SIMPLEQ_INIT(&sc->sc_txfreeq); 2142 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2143 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2144 txs = &sc->sc_txsoft[i]; 2145 txs->txs_mbuf = NULL; 2146 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2147 } 2148 2149 /* 2150 * Initialize the receive descriptor and receive job 2151 * descriptor rings. 2152 */ 2153 for (i = 0; i < SIP_NRXDESC; i++) { 2154 rxs = &sc->sc_rxsoft[i]; 2155 if (rxs->rxs_mbuf == NULL) { 2156 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2157 printf("%s: unable to allocate or map rx " 2158 "buffer %d, error = %d\n", 2159 sc->sc_dev.dv_xname, i, error); 2160 /* 2161 * XXX Should attempt to run with fewer receive 2162 * XXX buffers instead of just failing. 2163 */ 2164 SIP_DECL(rxdrain)(sc); 2165 goto out; 2166 } 2167 } else 2168 SIP_INIT_RXDESC(sc, i); 2169 } 2170 sc->sc_rxptr = 0; 2171 #ifdef DP83820 2172 sc->sc_rxdiscard = 0; 2173 SIP_RXCHAIN_RESET(sc); 2174 #endif /* DP83820 */ 2175 2176 /* 2177 * Set the configuration register; it's already initialized 2178 * in sip_attach(). 2179 */ 2180 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2181 2182 /* 2183 * Initialize the prototype TXCFG register. 2184 */ 2185 #if defined(DP83820) 2186 sc->sc_txcfg = TXCFG_MXDMA_512; 2187 sc->sc_rxcfg = RXCFG_MXDMA_512; 2188 #else 2189 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2190 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2191 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & CFG_EDBMASTEN)) { 2192 sc->sc_txcfg = TXCFG_MXDMA_64; 2193 sc->sc_rxcfg = RXCFG_MXDMA_64; 2194 } else { 2195 sc->sc_txcfg = TXCFG_MXDMA_512; 2196 sc->sc_rxcfg = RXCFG_MXDMA_512; 2197 } 2198 #endif /* DP83820 */ 2199 2200 sc->sc_txcfg |= TXCFG_ATP | 2201 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2202 sc->sc_tx_drain_thresh; 2203 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2204 2205 /* 2206 * Initialize the receive drain threshold if we have never 2207 * done so. 2208 */ 2209 if (sc->sc_rx_drain_thresh == 0) { 2210 /* 2211 * XXX This value should be tuned. This is set to the 2212 * maximum of 248 bytes, and we may be able to improve 2213 * performance by decreasing it (although we should never 2214 * set this value lower than 2; 14 bytes are required to 2215 * filter the packet). 2216 */ 2217 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2218 } 2219 2220 /* 2221 * Initialize the prototype RXCFG register. 2222 */ 2223 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2224 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2225 2226 #ifdef DP83820 2227 /* 2228 * Initialize the VLAN/IP receive control register. 2229 * We enable checksum computation on all incoming 2230 * packets, and do not reject packets w/ bad checksums. 2231 */ 2232 reg = 0; 2233 if (ifp->if_capenable & 2234 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2235 reg |= VRCR_IPEN; 2236 if (sc->sc_ethercom.ec_nvlans != 0) 2237 reg |= VRCR_VTDEN|VRCR_VTREN; 2238 bus_space_write_4(st, sh, SIP_VRCR, reg); 2239 2240 /* 2241 * Initialize the VLAN/IP transmit control register. 2242 * We enable outgoing checksum computation on a 2243 * per-packet basis. 2244 */ 2245 reg = 0; 2246 if (ifp->if_capenable & 2247 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2248 reg |= VTCR_PPCHK; 2249 if (sc->sc_ethercom.ec_nvlans != 0) 2250 reg |= VTCR_VPPTI; 2251 bus_space_write_4(st, sh, SIP_VTCR, reg); 2252 2253 /* 2254 * If we're using VLANs, initialize the VLAN data register. 2255 * To understand why we bswap the VLAN Ethertype, see section 2256 * 4.2.36 of the DP83820 manual. 2257 */ 2258 if (sc->sc_ethercom.ec_nvlans != 0) 2259 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2260 #endif /* DP83820 */ 2261 2262 /* 2263 * Give the transmit and receive rings to the chip. 2264 */ 2265 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2266 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2267 2268 /* 2269 * Initialize the interrupt mask. 2270 */ 2271 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2272 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2273 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2274 2275 /* Set up the receive filter. */ 2276 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2277 2278 /* 2279 * Set the current media. Do this after initializing the prototype 2280 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2281 * control. 2282 */ 2283 mii_mediachg(&sc->sc_mii); 2284 2285 /* 2286 * Enable interrupts. 2287 */ 2288 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2289 2290 /* 2291 * Start the transmit and receive processes. 2292 */ 2293 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2294 2295 /* 2296 * Start the one second MII clock. 2297 */ 2298 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2299 2300 /* 2301 * ...all done! 2302 */ 2303 ifp->if_flags |= IFF_RUNNING; 2304 ifp->if_flags &= ~IFF_OACTIVE; 2305 2306 out: 2307 if (error) 2308 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2309 return (error); 2310 } 2311 2312 /* 2313 * sip_drain: 2314 * 2315 * Drain the receive queue. 2316 */ 2317 void 2318 SIP_DECL(rxdrain)(struct sip_softc *sc) 2319 { 2320 struct sip_rxsoft *rxs; 2321 int i; 2322 2323 for (i = 0; i < SIP_NRXDESC; i++) { 2324 rxs = &sc->sc_rxsoft[i]; 2325 if (rxs->rxs_mbuf != NULL) { 2326 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2327 m_freem(rxs->rxs_mbuf); 2328 rxs->rxs_mbuf = NULL; 2329 } 2330 } 2331 } 2332 2333 /* 2334 * sip_stop: [ ifnet interface function ] 2335 * 2336 * Stop transmission on the interface. 2337 */ 2338 void 2339 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2340 { 2341 struct sip_softc *sc = ifp->if_softc; 2342 bus_space_tag_t st = sc->sc_st; 2343 bus_space_handle_t sh = sc->sc_sh; 2344 struct sip_txsoft *txs; 2345 u_int32_t cmdsts = 0; /* DEBUG */ 2346 2347 /* 2348 * Stop the one second clock. 2349 */ 2350 callout_stop(&sc->sc_tick_ch); 2351 2352 /* Down the MII. */ 2353 mii_down(&sc->sc_mii); 2354 2355 /* 2356 * Disable interrupts. 2357 */ 2358 bus_space_write_4(st, sh, SIP_IER, 0); 2359 2360 /* 2361 * Stop receiver and transmitter. 2362 */ 2363 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2364 2365 /* 2366 * Release any queued transmit buffers. 2367 */ 2368 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2369 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2370 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2371 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2372 CMDSTS_INTR) == 0) 2373 printf("%s: sip_stop: last descriptor does not " 2374 "have INTR bit set\n", sc->sc_dev.dv_xname); 2375 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 2376 #ifdef DIAGNOSTIC 2377 if (txs->txs_mbuf == NULL) { 2378 printf("%s: dirty txsoft with no mbuf chain\n", 2379 sc->sc_dev.dv_xname); 2380 panic("sip_stop"); 2381 } 2382 #endif 2383 cmdsts |= /* DEBUG */ 2384 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2385 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2386 m_freem(txs->txs_mbuf); 2387 txs->txs_mbuf = NULL; 2388 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2389 } 2390 2391 if (disable) 2392 SIP_DECL(rxdrain)(sc); 2393 2394 /* 2395 * Mark the interface down and cancel the watchdog timer. 2396 */ 2397 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2398 ifp->if_timer = 0; 2399 2400 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2401 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2402 printf("%s: sip_stop: no INTR bits set in dirty tx " 2403 "descriptors\n", sc->sc_dev.dv_xname); 2404 } 2405 2406 /* 2407 * sip_read_eeprom: 2408 * 2409 * Read data from the serial EEPROM. 2410 */ 2411 void 2412 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2413 u_int16_t *data) 2414 { 2415 bus_space_tag_t st = sc->sc_st; 2416 bus_space_handle_t sh = sc->sc_sh; 2417 u_int16_t reg; 2418 int i, x; 2419 2420 for (i = 0; i < wordcnt; i++) { 2421 /* Send CHIP SELECT. */ 2422 reg = EROMAR_EECS; 2423 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2424 2425 /* Shift in the READ opcode. */ 2426 for (x = 3; x > 0; x--) { 2427 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2428 reg |= EROMAR_EEDI; 2429 else 2430 reg &= ~EROMAR_EEDI; 2431 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2432 bus_space_write_4(st, sh, SIP_EROMAR, 2433 reg | EROMAR_EESK); 2434 delay(4); 2435 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2436 delay(4); 2437 } 2438 2439 /* Shift in address. */ 2440 for (x = 6; x > 0; x--) { 2441 if ((word + i) & (1 << (x - 1))) 2442 reg |= EROMAR_EEDI; 2443 else 2444 reg &= ~EROMAR_EEDI; 2445 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2446 bus_space_write_4(st, sh, SIP_EROMAR, 2447 reg | EROMAR_EESK); 2448 delay(4); 2449 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2450 delay(4); 2451 } 2452 2453 /* Shift out data. */ 2454 reg = EROMAR_EECS; 2455 data[i] = 0; 2456 for (x = 16; x > 0; x--) { 2457 bus_space_write_4(st, sh, SIP_EROMAR, 2458 reg | EROMAR_EESK); 2459 delay(4); 2460 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2461 data[i] |= (1 << (x - 1)); 2462 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2463 delay(4); 2464 } 2465 2466 /* Clear CHIP SELECT. */ 2467 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2468 delay(4); 2469 } 2470 } 2471 2472 /* 2473 * sip_add_rxbuf: 2474 * 2475 * Add a receive buffer to the indicated descriptor. 2476 */ 2477 int 2478 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2479 { 2480 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2481 struct mbuf *m; 2482 int error; 2483 2484 MGETHDR(m, M_DONTWAIT, MT_DATA); 2485 if (m == NULL) 2486 return (ENOBUFS); 2487 2488 MCLGET(m, M_DONTWAIT); 2489 if ((m->m_flags & M_EXT) == 0) { 2490 m_freem(m); 2491 return (ENOBUFS); 2492 } 2493 2494 #if defined(DP83820) 2495 m->m_len = SIP_RXBUF_LEN; 2496 #endif /* DP83820 */ 2497 2498 if (rxs->rxs_mbuf != NULL) 2499 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2500 2501 rxs->rxs_mbuf = m; 2502 2503 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2504 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2505 BUS_DMA_READ|BUS_DMA_NOWAIT); 2506 if (error) { 2507 printf("%s: can't load rx DMA map %d, error = %d\n", 2508 sc->sc_dev.dv_xname, idx, error); 2509 panic("sip_add_rxbuf"); /* XXX */ 2510 } 2511 2512 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2513 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2514 2515 SIP_INIT_RXDESC(sc, idx); 2516 2517 return (0); 2518 } 2519 2520 #if !defined(DP83820) 2521 /* 2522 * sip_sis900_set_filter: 2523 * 2524 * Set up the receive filter. 2525 */ 2526 void 2527 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2528 { 2529 bus_space_tag_t st = sc->sc_st; 2530 bus_space_handle_t sh = sc->sc_sh; 2531 struct ethercom *ec = &sc->sc_ethercom; 2532 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2533 struct ether_multi *enm; 2534 u_int8_t *cp; 2535 struct ether_multistep step; 2536 u_int32_t crc, mchash[16]; 2537 2538 /* 2539 * Initialize the prototype RFCR. 2540 */ 2541 sc->sc_rfcr = RFCR_RFEN; 2542 if (ifp->if_flags & IFF_BROADCAST) 2543 sc->sc_rfcr |= RFCR_AAB; 2544 if (ifp->if_flags & IFF_PROMISC) { 2545 sc->sc_rfcr |= RFCR_AAP; 2546 goto allmulti; 2547 } 2548 2549 /* 2550 * Set up the multicast address filter by passing all multicast 2551 * addresses through a CRC generator, and then using the high-order 2552 * 6 bits as an index into the 128 bit multicast hash table (only 2553 * the lower 16 bits of each 32 bit multicast hash register are 2554 * valid). The high order bits select the register, while the 2555 * rest of the bits select the bit within the register. 2556 */ 2557 2558 memset(mchash, 0, sizeof(mchash)); 2559 2560 ETHER_FIRST_MULTI(step, ec, enm); 2561 while (enm != NULL) { 2562 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2563 /* 2564 * We must listen to a range of multicast addresses. 2565 * For now, just accept all multicasts, rather than 2566 * trying to set only those filter bits needed to match 2567 * the range. (At this time, the only use of address 2568 * ranges is for IP multicast routing, for which the 2569 * range is big enough to require all bits set.) 2570 */ 2571 goto allmulti; 2572 } 2573 2574 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2575 2576 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2577 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2578 /* Just want the 8 most significant bits. */ 2579 crc >>= 24; 2580 } else { 2581 /* Just want the 7 most significant bits. */ 2582 crc >>= 25; 2583 } 2584 2585 /* Set the corresponding bit in the hash table. */ 2586 mchash[crc >> 4] |= 1 << (crc & 0xf); 2587 2588 ETHER_NEXT_MULTI(step, enm); 2589 } 2590 2591 ifp->if_flags &= ~IFF_ALLMULTI; 2592 goto setit; 2593 2594 allmulti: 2595 ifp->if_flags |= IFF_ALLMULTI; 2596 sc->sc_rfcr |= RFCR_AAM; 2597 2598 setit: 2599 #define FILTER_EMIT(addr, data) \ 2600 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2601 delay(1); \ 2602 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2603 delay(1) 2604 2605 /* 2606 * Disable receive filter, and program the node address. 2607 */ 2608 cp = LLADDR(ifp->if_sadl); 2609 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2610 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2611 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2612 2613 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2614 /* 2615 * Program the multicast hash table. 2616 */ 2617 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2618 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2619 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2620 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2621 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2622 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2623 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2624 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2625 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2626 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2627 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2628 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2629 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2630 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2631 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2632 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2633 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2634 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2635 } 2636 } 2637 #undef FILTER_EMIT 2638 2639 /* 2640 * Re-enable the receiver filter. 2641 */ 2642 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2643 } 2644 #endif /* ! DP83820 */ 2645 2646 /* 2647 * sip_dp83815_set_filter: 2648 * 2649 * Set up the receive filter. 2650 */ 2651 void 2652 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2653 { 2654 bus_space_tag_t st = sc->sc_st; 2655 bus_space_handle_t sh = sc->sc_sh; 2656 struct ethercom *ec = &sc->sc_ethercom; 2657 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2658 struct ether_multi *enm; 2659 u_int8_t *cp; 2660 struct ether_multistep step; 2661 u_int32_t crc, hash, slot, bit; 2662 #ifdef DP83820 2663 #define MCHASH_NWORDS 128 2664 #else 2665 #define MCHASH_NWORDS 32 2666 #endif /* DP83820 */ 2667 u_int16_t mchash[MCHASH_NWORDS]; 2668 int i; 2669 2670 /* 2671 * Initialize the prototype RFCR. 2672 * Enable the receive filter, and accept on 2673 * Perfect (destination address) Match 2674 * If IFF_BROADCAST, also accept all broadcast packets. 2675 * If IFF_PROMISC, accept all unicast packets (and later, set 2676 * IFF_ALLMULTI and accept all multicast, too). 2677 */ 2678 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2679 if (ifp->if_flags & IFF_BROADCAST) 2680 sc->sc_rfcr |= RFCR_AAB; 2681 if (ifp->if_flags & IFF_PROMISC) { 2682 sc->sc_rfcr |= RFCR_AAP; 2683 goto allmulti; 2684 } 2685 2686 #ifdef DP83820 2687 /* 2688 * Set up the DP83820 multicast address filter by passing all multicast 2689 * addresses through a CRC generator, and then using the high-order 2690 * 11 bits as an index into the 2048 bit multicast hash table. The 2691 * high-order 7 bits select the slot, while the low-order 4 bits 2692 * select the bit within the slot. Note that only the low 16-bits 2693 * of each filter word are used, and there are 128 filter words. 2694 */ 2695 #else 2696 /* 2697 * Set up the DP83815 multicast address filter by passing all multicast 2698 * addresses through a CRC generator, and then using the high-order 2699 * 9 bits as an index into the 512 bit multicast hash table. The 2700 * high-order 5 bits select the slot, while the low-order 4 bits 2701 * select the bit within the slot. Note that only the low 16-bits 2702 * of each filter word are used, and there are 32 filter words. 2703 */ 2704 #endif /* DP83820 */ 2705 2706 memset(mchash, 0, sizeof(mchash)); 2707 2708 ifp->if_flags &= ~IFF_ALLMULTI; 2709 ETHER_FIRST_MULTI(step, ec, enm); 2710 if (enm == NULL) 2711 goto setit; 2712 while (enm != NULL) { 2713 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2714 /* 2715 * We must listen to a range of multicast addresses. 2716 * For now, just accept all multicasts, rather than 2717 * trying to set only those filter bits needed to match 2718 * the range. (At this time, the only use of address 2719 * ranges is for IP multicast routing, for which the 2720 * range is big enough to require all bits set.) 2721 */ 2722 goto allmulti; 2723 } 2724 2725 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2726 2727 #ifdef DP83820 2728 /* Just want the 11 most significant bits. */ 2729 hash = crc >> 21; 2730 #else 2731 /* Just want the 9 most significant bits. */ 2732 hash = crc >> 23; 2733 #endif /* DP83820 */ 2734 2735 slot = hash >> 4; 2736 bit = hash & 0xf; 2737 2738 /* Set the corresponding bit in the hash table. */ 2739 mchash[slot] |= 1 << bit; 2740 2741 ETHER_NEXT_MULTI(step, enm); 2742 } 2743 sc->sc_rfcr |= RFCR_MHEN; 2744 goto setit; 2745 2746 allmulti: 2747 ifp->if_flags |= IFF_ALLMULTI; 2748 sc->sc_rfcr |= RFCR_AAM; 2749 2750 setit: 2751 #define FILTER_EMIT(addr, data) \ 2752 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2753 delay(1); \ 2754 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2755 delay(1) 2756 2757 /* 2758 * Disable receive filter, and program the node address. 2759 */ 2760 cp = LLADDR(ifp->if_sadl); 2761 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 2762 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 2763 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 2764 2765 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2766 /* 2767 * Program the multicast hash table. 2768 */ 2769 for (i = 0; i < MCHASH_NWORDS; i++) { 2770 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 2771 mchash[i]); 2772 } 2773 } 2774 #undef FILTER_EMIT 2775 #undef MCHASH_NWORDS 2776 2777 /* 2778 * Re-enable the receiver filter. 2779 */ 2780 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2781 } 2782 2783 #if defined(DP83820) 2784 /* 2785 * sip_dp83820_mii_readreg: [mii interface function] 2786 * 2787 * Read a PHY register on the MII of the DP83820. 2788 */ 2789 int 2790 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 2791 { 2792 2793 return (mii_bitbang_readreg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2794 phy, reg)); 2795 } 2796 2797 /* 2798 * sip_dp83820_mii_writereg: [mii interface function] 2799 * 2800 * Write a PHY register on the MII of the DP83820. 2801 */ 2802 void 2803 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 2804 { 2805 2806 mii_bitbang_writereg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2807 phy, reg, val); 2808 } 2809 2810 /* 2811 * sip_dp83815_mii_statchg: [mii interface function] 2812 * 2813 * Callback from MII layer when media changes. 2814 */ 2815 void 2816 SIP_DECL(dp83820_mii_statchg)(struct device *self) 2817 { 2818 struct sip_softc *sc = (struct sip_softc *) self; 2819 u_int32_t cfg; 2820 2821 /* 2822 * Update TXCFG for full-duplex operation. 2823 */ 2824 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2825 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2826 else 2827 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2828 2829 /* 2830 * Update RXCFG for full-duplex or loopback. 2831 */ 2832 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2833 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2834 sc->sc_rxcfg |= RXCFG_ATX; 2835 else 2836 sc->sc_rxcfg &= ~RXCFG_ATX; 2837 2838 /* 2839 * Update CFG for MII/GMII. 2840 */ 2841 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2842 cfg = sc->sc_cfg | CFG_MODE_1000; 2843 else 2844 cfg = sc->sc_cfg; 2845 2846 /* 2847 * XXX 802.3x flow control. 2848 */ 2849 2850 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 2851 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2852 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2853 } 2854 2855 /* 2856 * sip_dp83820_mii_bitbang_read: [mii bit-bang interface function] 2857 * 2858 * Read the MII serial port for the MII bit-bang module. 2859 */ 2860 u_int32_t 2861 SIP_DECL(dp83820_mii_bitbang_read)(struct device *self) 2862 { 2863 struct sip_softc *sc = (void *) self; 2864 2865 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 2866 } 2867 2868 /* 2869 * sip_dp83820_mii_bitbang_write: [mii big-bang interface function] 2870 * 2871 * Write the MII serial port for the MII bit-bang module. 2872 */ 2873 void 2874 SIP_DECL(dp83820_mii_bitbang_write)(struct device *self, u_int32_t val) 2875 { 2876 struct sip_softc *sc = (void *) self; 2877 2878 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 2879 } 2880 #else /* ! DP83820 */ 2881 /* 2882 * sip_sis900_mii_readreg: [mii interface function] 2883 * 2884 * Read a PHY register on the MII. 2885 */ 2886 int 2887 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 2888 { 2889 struct sip_softc *sc = (struct sip_softc *) self; 2890 u_int32_t enphy; 2891 2892 /* 2893 * The SiS 900 has only an internal PHY on the MII. Only allow 2894 * MII address 0. 2895 */ 2896 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 2897 sc->sc_rev < SIS_REV_635 && phy != 0) 2898 return (0); 2899 2900 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2901 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 2902 ENPHY_RWCMD | ENPHY_ACCESS); 2903 do { 2904 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2905 } while (enphy & ENPHY_ACCESS); 2906 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 2907 } 2908 2909 /* 2910 * sip_sis900_mii_writereg: [mii interface function] 2911 * 2912 * Write a PHY register on the MII. 2913 */ 2914 void 2915 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 2916 { 2917 struct sip_softc *sc = (struct sip_softc *) self; 2918 u_int32_t enphy; 2919 2920 /* 2921 * The SiS 900 has only an internal PHY on the MII. Only allow 2922 * MII address 0. 2923 */ 2924 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 2925 sc->sc_rev < SIS_REV_635 && phy != 0) 2926 return; 2927 2928 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2929 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 2930 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 2931 do { 2932 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2933 } while (enphy & ENPHY_ACCESS); 2934 } 2935 2936 /* 2937 * sip_sis900_mii_statchg: [mii interface function] 2938 * 2939 * Callback from MII layer when media changes. 2940 */ 2941 void 2942 SIP_DECL(sis900_mii_statchg)(struct device *self) 2943 { 2944 struct sip_softc *sc = (struct sip_softc *) self; 2945 u_int32_t flowctl; 2946 2947 /* 2948 * Update TXCFG for full-duplex operation. 2949 */ 2950 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2951 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2952 else 2953 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2954 2955 /* 2956 * Update RXCFG for full-duplex or loopback. 2957 */ 2958 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2959 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2960 sc->sc_rxcfg |= RXCFG_ATX; 2961 else 2962 sc->sc_rxcfg &= ~RXCFG_ATX; 2963 2964 /* 2965 * Update IMR for use of 802.3x flow control. 2966 */ 2967 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 2968 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 2969 flowctl = FLOWCTL_FLOWEN; 2970 } else { 2971 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 2972 flowctl = 0; 2973 } 2974 2975 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2976 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2977 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 2978 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 2979 } 2980 2981 /* 2982 * sip_dp83815_mii_readreg: [mii interface function] 2983 * 2984 * Read a PHY register on the MII. 2985 */ 2986 int 2987 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 2988 { 2989 struct sip_softc *sc = (struct sip_softc *) self; 2990 u_int32_t val; 2991 2992 /* 2993 * The DP83815 only has an internal PHY. Only allow 2994 * MII address 0. 2995 */ 2996 if (phy != 0) 2997 return (0); 2998 2999 /* 3000 * Apparently, after a reset, the DP83815 can take a while 3001 * to respond. During this recovery period, the BMSR returns 3002 * a value of 0. Catch this -- it's not supposed to happen 3003 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3004 * PHY to come back to life. 3005 * 3006 * This works out because the BMSR is the first register 3007 * read during the PHY probe process. 3008 */ 3009 do { 3010 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3011 } while (reg == MII_BMSR && val == 0); 3012 3013 return (val & 0xffff); 3014 } 3015 3016 /* 3017 * sip_dp83815_mii_writereg: [mii interface function] 3018 * 3019 * Write a PHY register to the MII. 3020 */ 3021 void 3022 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3023 { 3024 struct sip_softc *sc = (struct sip_softc *) self; 3025 3026 /* 3027 * The DP83815 only has an internal PHY. Only allow 3028 * MII address 0. 3029 */ 3030 if (phy != 0) 3031 return; 3032 3033 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3034 } 3035 3036 /* 3037 * sip_dp83815_mii_statchg: [mii interface function] 3038 * 3039 * Callback from MII layer when media changes. 3040 */ 3041 void 3042 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3043 { 3044 struct sip_softc *sc = (struct sip_softc *) self; 3045 3046 /* 3047 * Update TXCFG for full-duplex operation. 3048 */ 3049 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3050 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3051 else 3052 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3053 3054 /* 3055 * Update RXCFG for full-duplex or loopback. 3056 */ 3057 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3058 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3059 sc->sc_rxcfg |= RXCFG_ATX; 3060 else 3061 sc->sc_rxcfg &= ~RXCFG_ATX; 3062 3063 /* 3064 * XXX 802.3x flow control. 3065 */ 3066 3067 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3068 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3069 } 3070 #endif /* DP83820 */ 3071 3072 #if defined(DP83820) 3073 void 3074 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3075 const struct pci_attach_args *pa, u_int8_t *enaddr) 3076 { 3077 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3078 u_int8_t cksum, *e, match; 3079 int i; 3080 3081 /* 3082 * EEPROM data format for the DP83820 can be found in 3083 * the DP83820 manual, section 4.2.4. 3084 */ 3085 3086 SIP_DECL(read_eeprom)(sc, 0, 3087 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3088 3089 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3090 match = ~(match - 1); 3091 3092 cksum = 0x55; 3093 e = (u_int8_t *) eeprom_data; 3094 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3095 cksum += *e++; 3096 3097 if (cksum != match) 3098 printf("%s: Checksum (%x) mismatch (%x)", 3099 sc->sc_dev.dv_xname, cksum, match); 3100 3101 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3102 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3103 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3104 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3105 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3106 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3107 3108 /* Get the GPIOR bits. */ 3109 sc->sc_gpior = eeprom_data[0x04]; 3110 } 3111 #else /* ! DP83820 */ 3112 void 3113 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3114 const struct pci_attach_args *pa, u_int8_t *enaddr) 3115 { 3116 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3117 3118 switch (sc->sc_rev) { 3119 case SIS_REV_630S: 3120 case SIS_REV_630E: 3121 case SIS_REV_630EA1: 3122 case SIS_REV_630ET: 3123 case SIS_REV_635: 3124 /* 3125 * The MAC address for the on-board Ethernet of 3126 * the SiS 630 chipset is in the NVRAM. Kick 3127 * the chip into re-loading it from NVRAM, and 3128 * read the MAC address out of the filter registers. 3129 */ 3130 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3131 3132 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3133 RFCR_RFADDR_NODE0); 3134 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3135 0xffff; 3136 3137 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3138 RFCR_RFADDR_NODE2); 3139 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3140 0xffff; 3141 3142 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3143 RFCR_RFADDR_NODE4); 3144 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3145 0xffff; 3146 break; 3147 3148 default: 3149 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3150 sizeof(myea) / sizeof(myea[0]), myea); 3151 } 3152 3153 enaddr[0] = myea[0] & 0xff; 3154 enaddr[1] = myea[0] >> 8; 3155 enaddr[2] = myea[1] & 0xff; 3156 enaddr[3] = myea[1] >> 8; 3157 enaddr[4] = myea[2] & 0xff; 3158 enaddr[5] = myea[2] >> 8; 3159 } 3160 3161 /* Table and macro to bit-reverse an octet. */ 3162 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3163 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3164 3165 void 3166 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3167 const struct pci_attach_args *pa, u_int8_t *enaddr) 3168 { 3169 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3170 u_int8_t cksum, *e, match; 3171 int i; 3172 3173 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3174 sizeof(eeprom_data[0]), eeprom_data); 3175 3176 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3177 match = ~(match - 1); 3178 3179 cksum = 0x55; 3180 e = (u_int8_t *) eeprom_data; 3181 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3182 cksum += *e++; 3183 } 3184 if (cksum != match) { 3185 printf("%s: Checksum (%x) mismatch (%x)", 3186 sc->sc_dev.dv_xname, cksum, match); 3187 } 3188 3189 /* 3190 * Unrolled because it makes slightly more sense this way. 3191 * The DP83815 stores the MAC address in bit 0 of word 6 3192 * through bit 15 of word 8. 3193 */ 3194 ea = &eeprom_data[6]; 3195 enaddr[0] = ((*ea & 0x1) << 7); 3196 ea++; 3197 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3198 enaddr[1] = ((*ea & 0x1FE) >> 1); 3199 enaddr[2] = ((*ea & 0x1) << 7); 3200 ea++; 3201 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3202 enaddr[3] = ((*ea & 0x1FE) >> 1); 3203 enaddr[4] = ((*ea & 0x1) << 7); 3204 ea++; 3205 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3206 enaddr[5] = ((*ea & 0x1FE) >> 1); 3207 3208 /* 3209 * In case that's not weird enough, we also need to reverse 3210 * the bits in each byte. This all actually makes more sense 3211 * if you think about the EEPROM storage as an array of bits 3212 * being shifted into bytes, but that's not how we're looking 3213 * at it here... 3214 */ 3215 for (i = 0; i < 6 ;i++) 3216 enaddr[i] = bbr(enaddr[i]); 3217 } 3218 #endif /* DP83820 */ 3219 3220 /* 3221 * sip_mediastatus: [ifmedia interface function] 3222 * 3223 * Get the current interface media status. 3224 */ 3225 void 3226 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3227 { 3228 struct sip_softc *sc = ifp->if_softc; 3229 3230 mii_pollstat(&sc->sc_mii); 3231 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3232 ifmr->ifm_active = sc->sc_mii.mii_media_active; 3233 } 3234 3235 /* 3236 * sip_mediachange: [ifmedia interface function] 3237 * 3238 * Set hardware to newly-selected media. 3239 */ 3240 int 3241 SIP_DECL(mediachange)(struct ifnet *ifp) 3242 { 3243 struct sip_softc *sc = ifp->if_softc; 3244 3245 if (ifp->if_flags & IFF_UP) 3246 mii_mediachg(&sc->sc_mii); 3247 return (0); 3248 } 3249
Indexes created Tue Sep 30 11:09:46 GMT 2025