if_sip.c revision 1.52.4.6
1 /* $NetBSD: if_sip.c,v 1.52.4.6 2002/11/01 18:33:45 tron Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Support the 10-bit interface on the DP83820 (for fiber). 80 * 81 * - Reduce the Rx interrupt load. 82 */ 83 84 #include <sys/cdefs.h> 85 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.52.4.6 2002/11/01 18:33:45 tron Exp $"); 86 87 #include "bpfilter.h" 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/callout.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/ioctl.h> 97 #include <sys/errno.h> 98 #include <sys/device.h> 99 #include <sys/queue.h> 100 101 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 102 103 #include <net/if.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 #include <net/if_ether.h> 107 108 #if NBPFILTER > 0 109 #include <net/bpf.h> 110 #endif 111 112 #include <machine/bus.h> 113 #include <machine/intr.h> 114 #include <machine/endian.h> 115 116 #include <dev/mii/mii.h> 117 #include <dev/mii/miivar.h> 118 #ifdef DP83820 119 #include <dev/mii/mii_bitbang.h> 120 #endif /* DP83820 */ 121 122 #include <dev/pci/pcireg.h> 123 #include <dev/pci/pcivar.h> 124 #include <dev/pci/pcidevs.h> 125 126 #include <dev/pci/if_sipreg.h> 127 128 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 129 #define SIP_DECL(x) __CONCAT(gsip_,x) 130 #else /* SiS900 and DP83815 */ 131 #define SIP_DECL(x) __CONCAT(sip_,x) 132 #endif 133 134 #define SIP_STR(x) __STRING(SIP_DECL(x)) 135 136 /* 137 * Transmit descriptor list size. This is arbitrary, but allocate 138 * enough descriptors for 128 pending transmissions, and 8 segments 139 * per packet. This MUST work out to a power of 2. 140 */ 141 #define SIP_NTXSEGS 16 142 #define SIP_NTXSEGS_ALLOC 8 143 144 #define SIP_TXQUEUELEN 256 145 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 146 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 147 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 148 149 #if defined(DP83020) 150 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 151 #else 152 #define TX_DMAMAP_SIZE MCLBYTES 153 #endif 154 155 /* 156 * Receive descriptor list size. We have one Rx buffer per incoming 157 * packet, so this logic is a little simpler. 158 * 159 * Actually, on the DP83820, we allow the packet to consume more than 160 * one buffer, in order to support jumbo Ethernet frames. In that 161 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 162 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 163 * so we'd better be quick about handling receive interrupts. 164 */ 165 #if defined(DP83820) 166 #define SIP_NRXDESC 256 167 #else 168 #define SIP_NRXDESC 128 169 #endif /* DP83820 */ 170 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 171 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 172 173 /* 174 * Control structures are DMA'd to the SiS900 chip. We allocate them in 175 * a single clump that maps to a single DMA segment to make several things 176 * easier. 177 */ 178 struct sip_control_data { 179 /* 180 * The transmit descriptors. 181 */ 182 struct sip_desc scd_txdescs[SIP_NTXDESC]; 183 184 /* 185 * The receive descriptors. 186 */ 187 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 188 }; 189 190 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 191 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 192 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 193 194 /* 195 * Software state for transmit jobs. 196 */ 197 struct sip_txsoft { 198 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 199 bus_dmamap_t txs_dmamap; /* our DMA map */ 200 int txs_firstdesc; /* first descriptor in packet */ 201 int txs_lastdesc; /* last descriptor in packet */ 202 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 203 }; 204 205 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 206 207 /* 208 * Software state for receive jobs. 209 */ 210 struct sip_rxsoft { 211 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 212 bus_dmamap_t rxs_dmamap; /* our DMA map */ 213 }; 214 215 /* 216 * Software state per device. 217 */ 218 struct sip_softc { 219 struct device sc_dev; /* generic device information */ 220 bus_space_tag_t sc_st; /* bus space tag */ 221 bus_space_handle_t sc_sh; /* bus space handle */ 222 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 223 struct ethercom sc_ethercom; /* ethernet common data */ 224 void *sc_sdhook; /* shutdown hook */ 225 226 const struct sip_product *sc_model; /* which model are we? */ 227 int sc_rev; /* chip revision */ 228 229 void *sc_ih; /* interrupt cookie */ 230 231 struct mii_data sc_mii; /* MII/media information */ 232 233 struct callout sc_tick_ch; /* tick callout */ 234 235 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 236 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 237 238 /* 239 * Software state for transmit and receive descriptors. 240 */ 241 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 242 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 243 244 /* 245 * Control data structures. 246 */ 247 struct sip_control_data *sc_control_data; 248 #define sc_txdescs sc_control_data->scd_txdescs 249 #define sc_rxdescs sc_control_data->scd_rxdescs 250 251 #ifdef SIP_EVENT_COUNTERS 252 /* 253 * Event counters. 254 */ 255 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 256 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 257 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 258 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 259 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 260 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 261 #ifdef DP83820 262 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 263 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 264 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 265 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 266 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 267 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 268 #endif /* DP83820 */ 269 #endif /* SIP_EVENT_COUNTERS */ 270 271 u_int32_t sc_txcfg; /* prototype TXCFG register */ 272 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 273 u_int32_t sc_imr; /* prototype IMR register */ 274 u_int32_t sc_rfcr; /* prototype RFCR register */ 275 276 u_int32_t sc_cfg; /* prototype CFG register */ 277 278 #ifdef DP83820 279 u_int32_t sc_gpior; /* prototype GPIOR register */ 280 #endif /* DP83820 */ 281 282 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 283 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 284 285 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 286 287 int sc_flags; /* misc. flags; see below */ 288 289 int sc_txfree; /* number of free Tx descriptors */ 290 int sc_txnext; /* next ready Tx descriptor */ 291 int sc_txwin; /* Tx descriptors since last intr */ 292 293 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 294 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 295 296 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 297 #if defined(DP83820) 298 int sc_rxdiscard; 299 int sc_rxlen; 300 struct mbuf *sc_rxhead; 301 struct mbuf *sc_rxtail; 302 struct mbuf **sc_rxtailp; 303 #endif /* DP83820 */ 304 }; 305 306 /* sc_flags */ 307 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 308 309 #ifdef DP83820 310 #define SIP_RXCHAIN_RESET(sc) \ 311 do { \ 312 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 313 *(sc)->sc_rxtailp = NULL; \ 314 (sc)->sc_rxlen = 0; \ 315 } while (/*CONSTCOND*/0) 316 317 #define SIP_RXCHAIN_LINK(sc, m) \ 318 do { \ 319 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 320 (sc)->sc_rxtailp = &(m)->m_next; \ 321 } while (/*CONSTCOND*/0) 322 #endif /* DP83820 */ 323 324 #ifdef SIP_EVENT_COUNTERS 325 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 326 #else 327 #define SIP_EVCNT_INCR(ev) /* nothing */ 328 #endif 329 330 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 331 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 332 333 #define SIP_CDTXSYNC(sc, x, n, ops) \ 334 do { \ 335 int __x, __n; \ 336 \ 337 __x = (x); \ 338 __n = (n); \ 339 \ 340 /* If it will wrap around, sync to the end of the ring. */ \ 341 if ((__x + __n) > SIP_NTXDESC) { \ 342 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 343 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 344 (SIP_NTXDESC - __x), (ops)); \ 345 __n -= (SIP_NTXDESC - __x); \ 346 __x = 0; \ 347 } \ 348 \ 349 /* Now sync whatever is left. */ \ 350 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 351 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 352 } while (0) 353 354 #define SIP_CDRXSYNC(sc, x, ops) \ 355 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 356 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 357 358 #ifdef DP83820 359 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 360 #define SIP_RXBUF_LEN (MCLBYTES - 4) 361 #else 362 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 363 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 364 #endif 365 #define SIP_INIT_RXDESC(sc, x) \ 366 do { \ 367 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 368 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 369 \ 370 __sipd->sipd_link = \ 371 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 372 __sipd->sipd_bufptr = \ 373 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 374 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 375 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 376 SIP_INIT_RXDESC_EXTSTS \ 377 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 378 } while (0) 379 380 #define SIP_CHIP_VERS(sc, v, p, r) \ 381 ((sc)->sc_model->sip_vendor == (v) && \ 382 (sc)->sc_model->sip_product == (p) && \ 383 (sc)->sc_rev == (r)) 384 385 #define SIP_CHIP_MODEL(sc, v, p) \ 386 ((sc)->sc_model->sip_vendor == (v) && \ 387 (sc)->sc_model->sip_product == (p)) 388 389 #if !defined(DP83820) 390 #define SIP_SIS900_REV(sc, rev) \ 391 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 392 #endif 393 394 #define SIP_TIMEOUT 1000 395 396 void SIP_DECL(start)(struct ifnet *); 397 void SIP_DECL(watchdog)(struct ifnet *); 398 int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 399 int SIP_DECL(init)(struct ifnet *); 400 void SIP_DECL(stop)(struct ifnet *, int); 401 402 void SIP_DECL(shutdown)(void *); 403 404 void SIP_DECL(reset)(struct sip_softc *); 405 void SIP_DECL(rxdrain)(struct sip_softc *); 406 int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 407 void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, u_int16_t *); 408 void SIP_DECL(tick)(void *); 409 410 #if !defined(DP83820) 411 void SIP_DECL(sis900_set_filter)(struct sip_softc *); 412 #endif /* ! DP83820 */ 413 void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 414 415 #if defined(DP83820) 416 void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 417 const struct pci_attach_args *, u_int8_t *); 418 #else 419 void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 420 const struct pci_attach_args *, u_int8_t *); 421 void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 422 const struct pci_attach_args *, u_int8_t *); 423 #endif /* DP83820 */ 424 425 int SIP_DECL(intr)(void *); 426 void SIP_DECL(txintr)(struct sip_softc *); 427 void SIP_DECL(rxintr)(struct sip_softc *); 428 429 #if defined(DP83820) 430 int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 431 void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 432 void SIP_DECL(dp83820_mii_statchg)(struct device *); 433 #else 434 int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 435 void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 436 void SIP_DECL(sis900_mii_statchg)(struct device *); 437 438 int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 439 void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 440 void SIP_DECL(dp83815_mii_statchg)(struct device *); 441 #endif /* DP83820 */ 442 443 int SIP_DECL(mediachange)(struct ifnet *); 444 void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 445 446 int SIP_DECL(match)(struct device *, struct cfdata *, void *); 447 void SIP_DECL(attach)(struct device *, struct device *, void *); 448 449 int SIP_DECL(copy_small) = 0; 450 451 struct cfattach SIP_DECL(ca) = { 452 sizeof(struct sip_softc), SIP_DECL(match), SIP_DECL(attach), 453 }; 454 455 /* 456 * Descriptions of the variants of the SiS900. 457 */ 458 struct sip_variant { 459 int (*sipv_mii_readreg)(struct device *, int, int); 460 void (*sipv_mii_writereg)(struct device *, int, int, int); 461 void (*sipv_mii_statchg)(struct device *); 462 void (*sipv_set_filter)(struct sip_softc *); 463 void (*sipv_read_macaddr)(struct sip_softc *, 464 const struct pci_attach_args *, u_int8_t *); 465 }; 466 467 #if defined(DP83820) 468 u_int32_t SIP_DECL(dp83820_mii_bitbang_read)(struct device *); 469 void SIP_DECL(dp83820_mii_bitbang_write)(struct device *, u_int32_t); 470 471 const struct mii_bitbang_ops SIP_DECL(dp83820_mii_bitbang_ops) = { 472 SIP_DECL(dp83820_mii_bitbang_read), 473 SIP_DECL(dp83820_mii_bitbang_write), 474 { 475 EROMAR_MDIO, /* MII_BIT_MDO */ 476 EROMAR_MDIO, /* MII_BIT_MDI */ 477 EROMAR_MDC, /* MII_BIT_MDC */ 478 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 479 0, /* MII_BIT_DIR_PHY_HOST */ 480 } 481 }; 482 #endif /* DP83820 */ 483 484 #if defined(DP83820) 485 const struct sip_variant SIP_DECL(variant_dp83820) = { 486 SIP_DECL(dp83820_mii_readreg), 487 SIP_DECL(dp83820_mii_writereg), 488 SIP_DECL(dp83820_mii_statchg), 489 SIP_DECL(dp83815_set_filter), 490 SIP_DECL(dp83820_read_macaddr), 491 }; 492 #else 493 const struct sip_variant SIP_DECL(variant_sis900) = { 494 SIP_DECL(sis900_mii_readreg), 495 SIP_DECL(sis900_mii_writereg), 496 SIP_DECL(sis900_mii_statchg), 497 SIP_DECL(sis900_set_filter), 498 SIP_DECL(sis900_read_macaddr), 499 }; 500 501 const struct sip_variant SIP_DECL(variant_dp83815) = { 502 SIP_DECL(dp83815_mii_readreg), 503 SIP_DECL(dp83815_mii_writereg), 504 SIP_DECL(dp83815_mii_statchg), 505 SIP_DECL(dp83815_set_filter), 506 SIP_DECL(dp83815_read_macaddr), 507 }; 508 #endif /* DP83820 */ 509 510 /* 511 * Devices supported by this driver. 512 */ 513 const struct sip_product { 514 pci_vendor_id_t sip_vendor; 515 pci_product_id_t sip_product; 516 const char *sip_name; 517 const struct sip_variant *sip_variant; 518 } SIP_DECL(products)[] = { 519 #if defined(DP83820) 520 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 521 "NatSemi DP83820 Gigabit Ethernet", 522 &SIP_DECL(variant_dp83820) }, 523 #else 524 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 525 "SiS 900 10/100 Ethernet", 526 &SIP_DECL(variant_sis900) }, 527 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 528 "SiS 7016 10/100 Ethernet", 529 &SIP_DECL(variant_sis900) }, 530 531 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 532 "NatSemi DP83815 10/100 Ethernet", 533 &SIP_DECL(variant_dp83815) }, 534 #endif /* DP83820 */ 535 536 { 0, 0, 537 NULL, 538 NULL }, 539 }; 540 541 static const struct sip_product * 542 SIP_DECL(lookup)(const struct pci_attach_args *pa) 543 { 544 const struct sip_product *sip; 545 546 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 547 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 548 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 549 return (sip); 550 } 551 return (NULL); 552 } 553 554 #ifdef DP83820 555 /* 556 * I really hate stupid hardware vendors. There's a bit in the EEPROM 557 * which indicates if the card can do 64-bit data transfers. Unfortunately, 558 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 559 * which means we try to use 64-bit data transfers on those cards if we 560 * happen to be plugged into a 32-bit slot. 561 * 562 * What we do is use this table of cards known to be 64-bit cards. If 563 * you have a 64-bit card who's subsystem ID is not listed in this table, 564 * send the output of "pcictl dump ..." of the device to me so that your 565 * card will use the 64-bit data path when plugged into a 64-bit slot. 566 * 567 * -- Jason R. Thorpe <thorpej (at) netbsd.org> 568 * June 30, 2002 569 */ 570 static int 571 SIP_DECL(check_64bit)(const struct pci_attach_args *pa) 572 { 573 static const struct { 574 pci_vendor_id_t c64_vendor; 575 pci_product_id_t c64_product; 576 } card64[] = { 577 /* Asante GigaNIX */ 578 { 0x128a, 0x0002 }, 579 580 { 0, 0} 581 }; 582 pcireg_t subsys; 583 int i; 584 585 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 586 587 for (i = 0; card64[i].c64_vendor != 0; i++) { 588 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 589 PCI_PRODUCT(subsys) == card64[i].c64_product) 590 return (1); 591 } 592 593 return (0); 594 } 595 #endif /* DP83820 */ 596 597 int 598 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 599 { 600 struct pci_attach_args *pa = aux; 601 602 if (SIP_DECL(lookup)(pa) != NULL) 603 return (1); 604 605 return (0); 606 } 607 608 void 609 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 610 { 611 struct sip_softc *sc = (struct sip_softc *) self; 612 struct pci_attach_args *pa = aux; 613 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 614 pci_chipset_tag_t pc = pa->pa_pc; 615 pci_intr_handle_t ih; 616 const char *intrstr = NULL; 617 bus_space_tag_t iot, memt; 618 bus_space_handle_t ioh, memh; 619 bus_dma_segment_t seg; 620 int ioh_valid, memh_valid; 621 int i, rseg, error; 622 const struct sip_product *sip; 623 pcireg_t pmode; 624 u_int8_t enaddr[ETHER_ADDR_LEN]; 625 int pmreg; 626 #ifdef DP83820 627 pcireg_t memtype; 628 u_int32_t reg; 629 #endif /* DP83820 */ 630 631 callout_init(&sc->sc_tick_ch); 632 633 sip = SIP_DECL(lookup)(pa); 634 if (sip == NULL) { 635 printf("\n"); 636 panic(SIP_STR(attach) ": impossible"); 637 } 638 sc->sc_rev = PCI_REVISION(pa->pa_class); 639 640 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 641 642 sc->sc_model = sip; 643 644 /* 645 * XXX Work-around broken PXE firmware on some boards. 646 * 647 * The DP83815 shares an address decoder with the MEM BAR 648 * and the ROM BAR. Make sure the ROM BAR is disabled, 649 * so that memory mapped access works. 650 */ 651 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 652 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 653 ~PCI_MAPREG_ROM_ENABLE); 654 655 /* 656 * Map the device. 657 */ 658 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 659 PCI_MAPREG_TYPE_IO, 0, 660 &iot, &ioh, NULL, NULL) == 0); 661 #ifdef DP83820 662 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 663 switch (memtype) { 664 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 665 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 666 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 667 memtype, 0, &memt, &memh, NULL, NULL) == 0); 668 break; 669 default: 670 memh_valid = 0; 671 } 672 #else 673 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 674 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 675 &memt, &memh, NULL, NULL) == 0); 676 #endif /* DP83820 */ 677 678 if (memh_valid) { 679 sc->sc_st = memt; 680 sc->sc_sh = memh; 681 } else if (ioh_valid) { 682 sc->sc_st = iot; 683 sc->sc_sh = ioh; 684 } else { 685 printf("%s: unable to map device registers\n", 686 sc->sc_dev.dv_xname); 687 return; 688 } 689 690 sc->sc_dmat = pa->pa_dmat; 691 692 /* 693 * Make sure bus mastering is enabled. Also make sure 694 * Write/Invalidate is enabled if we're allowed to use it. 695 */ 696 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 697 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 698 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 699 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 700 pmreg | PCI_COMMAND_MASTER_ENABLE); 701 702 /* Get it out of power save mode if needed. */ 703 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 704 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 705 if (pmode == 3) { 706 /* 707 * The card has lost all configuration data in 708 * this state, so punt. 709 */ 710 printf("%s: unable to wake up from power state D3\n", 711 sc->sc_dev.dv_xname); 712 return; 713 } 714 if (pmode != 0) { 715 printf("%s: waking up from power state D%d\n", 716 sc->sc_dev.dv_xname, pmode); 717 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 718 } 719 } 720 721 /* 722 * Map and establish our interrupt. 723 */ 724 if (pci_intr_map(pa, &ih)) { 725 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 726 return; 727 } 728 intrstr = pci_intr_string(pc, ih); 729 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 730 if (sc->sc_ih == NULL) { 731 printf("%s: unable to establish interrupt", 732 sc->sc_dev.dv_xname); 733 if (intrstr != NULL) 734 printf(" at %s", intrstr); 735 printf("\n"); 736 return; 737 } 738 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 739 740 SIMPLEQ_INIT(&sc->sc_txfreeq); 741 SIMPLEQ_INIT(&sc->sc_txdirtyq); 742 743 /* 744 * Allocate the control data structures, and create and load the 745 * DMA map for it. 746 */ 747 if ((error = bus_dmamem_alloc(sc->sc_dmat, 748 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 749 0)) != 0) { 750 printf("%s: unable to allocate control data, error = %d\n", 751 sc->sc_dev.dv_xname, error); 752 goto fail_0; 753 } 754 755 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 756 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 757 BUS_DMA_COHERENT)) != 0) { 758 printf("%s: unable to map control data, error = %d\n", 759 sc->sc_dev.dv_xname, error); 760 goto fail_1; 761 } 762 763 if ((error = bus_dmamap_create(sc->sc_dmat, 764 sizeof(struct sip_control_data), 1, 765 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 766 printf("%s: unable to create control data DMA map, " 767 "error = %d\n", sc->sc_dev.dv_xname, error); 768 goto fail_2; 769 } 770 771 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 772 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 773 0)) != 0) { 774 printf("%s: unable to load control data DMA map, error = %d\n", 775 sc->sc_dev.dv_xname, error); 776 goto fail_3; 777 } 778 779 /* 780 * Create the transmit buffer DMA maps. 781 */ 782 for (i = 0; i < SIP_TXQUEUELEN; i++) { 783 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 784 SIP_NTXSEGS, MCLBYTES, 0, 0, 785 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 786 printf("%s: unable to create tx DMA map %d, " 787 "error = %d\n", sc->sc_dev.dv_xname, i, error); 788 goto fail_4; 789 } 790 } 791 792 /* 793 * Create the receive buffer DMA maps. 794 */ 795 for (i = 0; i < SIP_NRXDESC; i++) { 796 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 797 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 798 printf("%s: unable to create rx DMA map %d, " 799 "error = %d\n", sc->sc_dev.dv_xname, i, error); 800 goto fail_5; 801 } 802 sc->sc_rxsoft[i].rxs_mbuf = NULL; 803 } 804 805 /* 806 * Reset the chip to a known state. 807 */ 808 SIP_DECL(reset)(sc); 809 810 /* 811 * Read the Ethernet address from the EEPROM. This might 812 * also fetch other stuff from the EEPROM and stash it 813 * in the softc. 814 */ 815 sc->sc_cfg = 0; 816 #if !defined(DP83820) 817 if (SIP_SIS900_REV(sc,SIS_REV_635) || 818 SIP_SIS900_REV(sc,SIS_REV_900B)) 819 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 820 #endif 821 822 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 823 824 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 825 ether_sprintf(enaddr)); 826 827 /* 828 * Initialize the configuration register: aggressive PCI 829 * bus request algorithm, default backoff, default OW timer, 830 * default parity error detection. 831 * 832 * NOTE: "Big endian mode" is useless on the SiS900 and 833 * friends -- it affects packet data, not descriptors. 834 */ 835 #ifdef DP83820 836 /* 837 * Cause the chip to load configuration data from the EEPROM. 838 */ 839 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 840 for (i = 0; i < 10000; i++) { 841 delay(10); 842 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 843 PTSCR_EELOAD_EN) == 0) 844 break; 845 } 846 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 847 PTSCR_EELOAD_EN) { 848 printf("%s: timeout loading configuration from EEPROM\n", 849 sc->sc_dev.dv_xname); 850 return; 851 } 852 853 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 854 if (reg & CFG_PCI64_DET) { 855 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 856 /* 857 * Check to see if this card is 64-bit. If so, enable 64-bit 858 * data transfers. 859 * 860 * We can't use the DATA64_EN bit in the EEPROM, because 861 * vendors of 32-bit cards fail to clear that bit in many 862 * cases (yet the card still detects that it's in a 64-bit 863 * slot; go figure). 864 */ 865 if (SIP_DECL(check_64bit)(pa)) { 866 sc->sc_cfg |= CFG_DATA64_EN; 867 printf(", using 64-bit data transfers"); 868 } 869 printf("\n"); 870 } 871 872 /* 873 * XXX Need some PCI flags indicating support for 874 * XXX 64-bit addressing. 875 */ 876 #if 0 877 if (reg & CFG_M64ADDR) 878 sc->sc_cfg |= CFG_M64ADDR; 879 if (reg & CFG_T64ADDR) 880 sc->sc_cfg |= CFG_T64ADDR; 881 #endif 882 883 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 884 const char *sep = ""; 885 printf("%s: using ", sc->sc_dev.dv_xname); 886 if (reg & CFG_EXT_125) { 887 sc->sc_cfg |= CFG_EXT_125; 888 printf("%s125MHz clock", sep); 889 sep = ", "; 890 } 891 if (reg & CFG_TBI_EN) { 892 sc->sc_cfg |= CFG_TBI_EN; 893 printf("%sten-bit interface", sep); 894 sep = ", "; 895 } 896 printf("\n"); 897 } 898 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 899 (reg & CFG_MRM_DIS) != 0) 900 sc->sc_cfg |= CFG_MRM_DIS; 901 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 902 (reg & CFG_MWI_DIS) != 0) 903 sc->sc_cfg |= CFG_MWI_DIS; 904 905 /* 906 * Use the extended descriptor format on the DP83820. This 907 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 908 * checksumming. 909 */ 910 sc->sc_cfg |= CFG_EXTSTS_EN; 911 #endif /* DP83820 */ 912 913 /* 914 * Initialize our media structures and probe the MII. 915 */ 916 sc->sc_mii.mii_ifp = ifp; 917 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 918 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 919 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 920 ifmedia_init(&sc->sc_mii.mii_media, 0, SIP_DECL(mediachange), 921 SIP_DECL(mediastatus)); 922 #ifdef DP83820 923 if (sc->sc_cfg & CFG_TBI_EN) { 924 /* Using ten-bit interface. */ 925 printf("%s: TBI -- FIXME\n", sc->sc_dev.dv_xname); 926 } else { 927 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 928 MII_OFFSET_ANY, 0); 929 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 930 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 931 0, NULL); 932 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 933 } else 934 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 935 } 936 #else 937 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 938 MII_OFFSET_ANY, 0); 939 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 940 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 941 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 942 } else 943 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 944 #endif /* DP83820 */ 945 946 ifp = &sc->sc_ethercom.ec_if; 947 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 948 ifp->if_softc = sc; 949 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 950 ifp->if_ioctl = SIP_DECL(ioctl); 951 ifp->if_start = SIP_DECL(start); 952 ifp->if_watchdog = SIP_DECL(watchdog); 953 ifp->if_init = SIP_DECL(init); 954 ifp->if_stop = SIP_DECL(stop); 955 IFQ_SET_READY(&ifp->if_snd); 956 957 /* 958 * We can support 802.1Q VLAN-sized frames. 959 */ 960 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 961 962 #ifdef DP83820 963 /* 964 * And the DP83820 can do VLAN tagging in hardware, and 965 * support the jumbo Ethernet MTU. 966 */ 967 sc->sc_ethercom.ec_capabilities |= 968 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 969 970 /* 971 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 972 * in hardware. 973 */ 974 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 975 IFCAP_CSUM_UDPv4; 976 #endif /* DP83820 */ 977 978 /* 979 * Attach the interface. 980 */ 981 if_attach(ifp); 982 ether_ifattach(ifp, enaddr); 983 984 /* 985 * The number of bytes that must be available in 986 * the Tx FIFO before the bus master can DMA more 987 * data into the FIFO. 988 */ 989 sc->sc_tx_fill_thresh = 64 / 32; 990 991 /* 992 * Start at a drain threshold of 512 bytes. We will 993 * increase it if a DMA underrun occurs. 994 * 995 * XXX The minimum value of this variable should be 996 * tuned. We may be able to improve performance 997 * by starting with a lower value. That, however, 998 * may trash the first few outgoing packets if the 999 * PCI bus is saturated. 1000 */ 1001 sc->sc_tx_drain_thresh = 1504 / 32; 1002 1003 /* 1004 * Initialize the Rx FIFO drain threshold. 1005 * 1006 * This is in units of 8 bytes. 1007 * 1008 * We should never set this value lower than 2; 14 bytes are 1009 * required to filter the packet. 1010 */ 1011 sc->sc_rx_drain_thresh = 128 / 8; 1012 1013 #ifdef SIP_EVENT_COUNTERS 1014 /* 1015 * Attach event counters. 1016 */ 1017 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1018 NULL, sc->sc_dev.dv_xname, "txsstall"); 1019 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1020 NULL, sc->sc_dev.dv_xname, "txdstall"); 1021 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1022 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1023 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1024 NULL, sc->sc_dev.dv_xname, "txdintr"); 1025 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1026 NULL, sc->sc_dev.dv_xname, "txiintr"); 1027 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1028 NULL, sc->sc_dev.dv_xname, "rxintr"); 1029 #ifdef DP83820 1030 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1031 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1032 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1033 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1034 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1035 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1036 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1037 NULL, sc->sc_dev.dv_xname, "txipsum"); 1038 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1039 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1040 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1041 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1042 #endif /* DP83820 */ 1043 #endif /* SIP_EVENT_COUNTERS */ 1044 1045 /* 1046 * Make sure the interface is shutdown during reboot. 1047 */ 1048 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 1049 if (sc->sc_sdhook == NULL) 1050 printf("%s: WARNING: unable to establish shutdown hook\n", 1051 sc->sc_dev.dv_xname); 1052 return; 1053 1054 /* 1055 * Free any resources we've allocated during the failed attach 1056 * attempt. Do this in reverse order and fall through. 1057 */ 1058 fail_5: 1059 for (i = 0; i < SIP_NRXDESC; i++) { 1060 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1061 bus_dmamap_destroy(sc->sc_dmat, 1062 sc->sc_rxsoft[i].rxs_dmamap); 1063 } 1064 fail_4: 1065 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1066 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1067 bus_dmamap_destroy(sc->sc_dmat, 1068 sc->sc_txsoft[i].txs_dmamap); 1069 } 1070 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1071 fail_3: 1072 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1073 fail_2: 1074 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1075 sizeof(struct sip_control_data)); 1076 fail_1: 1077 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1078 fail_0: 1079 return; 1080 } 1081 1082 /* 1083 * sip_shutdown: 1084 * 1085 * Make sure the interface is stopped at reboot time. 1086 */ 1087 void 1088 SIP_DECL(shutdown)(void *arg) 1089 { 1090 struct sip_softc *sc = arg; 1091 1092 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1093 } 1094 1095 /* 1096 * sip_start: [ifnet interface function] 1097 * 1098 * Start packet transmission on the interface. 1099 */ 1100 void 1101 SIP_DECL(start)(struct ifnet *ifp) 1102 { 1103 struct sip_softc *sc = ifp->if_softc; 1104 struct mbuf *m0, *m; 1105 struct sip_txsoft *txs; 1106 bus_dmamap_t dmamap; 1107 int error, firsttx, nexttx, lasttx, ofree, seg; 1108 #ifdef DP83820 1109 u_int32_t extsts; 1110 #endif 1111 1112 /* 1113 * If we've been told to pause, don't transmit any more packets. 1114 */ 1115 if (sc->sc_flags & SIPF_PAUSED) 1116 ifp->if_flags |= IFF_OACTIVE; 1117 1118 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1119 return; 1120 1121 /* 1122 * Remember the previous number of free descriptors and 1123 * the first descriptor we'll use. 1124 */ 1125 ofree = sc->sc_txfree; 1126 firsttx = sc->sc_txnext; 1127 1128 /* 1129 * Loop through the send queue, setting up transmit descriptors 1130 * until we drain the queue, or use up all available transmit 1131 * descriptors. 1132 */ 1133 for (;;) { 1134 /* Get a work queue entry. */ 1135 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1136 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1137 break; 1138 } 1139 1140 /* 1141 * Grab a packet off the queue. 1142 */ 1143 IFQ_POLL(&ifp->if_snd, m0); 1144 if (m0 == NULL) 1145 break; 1146 #ifndef DP83820 1147 m = NULL; 1148 #endif 1149 1150 dmamap = txs->txs_dmamap; 1151 1152 #ifdef DP83820 1153 /* 1154 * Load the DMA map. If this fails, the packet either 1155 * didn't fit in the allotted number of segments, or we 1156 * were short on resources. For the too-many-segments 1157 * case, we simply report an error and drop the packet, 1158 * since we can't sanely copy a jumbo packet to a single 1159 * buffer. 1160 */ 1161 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1162 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1163 if (error) { 1164 if (error == EFBIG) { 1165 printf("%s: Tx packet consumes too many " 1166 "DMA segments, dropping...\n", 1167 sc->sc_dev.dv_xname); 1168 IFQ_DEQUEUE(&ifp->if_snd, m0); 1169 m_freem(m0); 1170 continue; 1171 } 1172 /* 1173 * Short on resources, just stop for now. 1174 */ 1175 break; 1176 } 1177 #else /* DP83820 */ 1178 /* 1179 * Load the DMA map. If this fails, the packet either 1180 * didn't fit in the alloted number of segments, or we 1181 * were short on resources. In this case, we'll copy 1182 * and try again. 1183 */ 1184 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1185 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1186 MGETHDR(m, M_DONTWAIT, MT_DATA); 1187 if (m == NULL) { 1188 printf("%s: unable to allocate Tx mbuf\n", 1189 sc->sc_dev.dv_xname); 1190 break; 1191 } 1192 if (m0->m_pkthdr.len > MHLEN) { 1193 MCLGET(m, M_DONTWAIT); 1194 if ((m->m_flags & M_EXT) == 0) { 1195 printf("%s: unable to allocate Tx " 1196 "cluster\n", sc->sc_dev.dv_xname); 1197 m_freem(m); 1198 break; 1199 } 1200 } 1201 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1202 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1203 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1204 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1205 if (error) { 1206 printf("%s: unable to load Tx buffer, " 1207 "error = %d\n", sc->sc_dev.dv_xname, error); 1208 break; 1209 } 1210 } 1211 #endif /* DP83820 */ 1212 1213 /* 1214 * Ensure we have enough descriptors free to describe 1215 * the packet. Note, we always reserve one descriptor 1216 * at the end of the ring as a termination point, to 1217 * prevent wrap-around. 1218 */ 1219 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1220 /* 1221 * Not enough free descriptors to transmit this 1222 * packet. We haven't committed anything yet, 1223 * so just unload the DMA map, put the packet 1224 * back on the queue, and punt. Notify the upper 1225 * layer that there are not more slots left. 1226 * 1227 * XXX We could allocate an mbuf and copy, but 1228 * XXX is it worth it? 1229 */ 1230 ifp->if_flags |= IFF_OACTIVE; 1231 bus_dmamap_unload(sc->sc_dmat, dmamap); 1232 #ifndef DP83820 1233 if (m != NULL) 1234 m_freem(m); 1235 #endif 1236 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1237 break; 1238 } 1239 1240 IFQ_DEQUEUE(&ifp->if_snd, m0); 1241 #ifndef DP83820 1242 if (m != NULL) { 1243 m_freem(m0); 1244 m0 = m; 1245 } 1246 #endif 1247 1248 /* 1249 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1250 */ 1251 1252 /* Sync the DMA map. */ 1253 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1254 BUS_DMASYNC_PREWRITE); 1255 1256 /* 1257 * Initialize the transmit descriptors. 1258 */ 1259 for (nexttx = sc->sc_txnext, seg = 0; 1260 seg < dmamap->dm_nsegs; 1261 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1262 /* 1263 * If this is the first descriptor we're 1264 * enqueueing, don't set the OWN bit just 1265 * yet. That could cause a race condition. 1266 * We'll do it below. 1267 */ 1268 sc->sc_txdescs[nexttx].sipd_bufptr = 1269 htole32(dmamap->dm_segs[seg].ds_addr); 1270 sc->sc_txdescs[nexttx].sipd_cmdsts = 1271 htole32((nexttx == firsttx ? 0 : CMDSTS_OWN) | 1272 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1273 #ifdef DP83820 1274 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1275 #endif /* DP83820 */ 1276 lasttx = nexttx; 1277 } 1278 1279 /* Clear the MORE bit on the last segment. */ 1280 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1281 1282 /* 1283 * If we're in the interrupt delay window, delay the 1284 * interrupt. 1285 */ 1286 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1287 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1288 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1289 htole32(CMDSTS_INTR); 1290 sc->sc_txwin = 0; 1291 } 1292 1293 #ifdef DP83820 1294 /* 1295 * If VLANs are enabled and the packet has a VLAN tag, set 1296 * up the descriptor to encapsulate the packet for us. 1297 * 1298 * This apparently has to be on the last descriptor of 1299 * the packet. 1300 */ 1301 if (sc->sc_ethercom.ec_nvlans != 0 && 1302 (m = m_aux_find(m0, AF_LINK, ETHERTYPE_VLAN)) != NULL) { 1303 sc->sc_txdescs[lasttx].sipd_extsts |= 1304 htole32(EXTSTS_VPKT | 1305 htons(*mtod(m, int *) & EXTSTS_VTCI)); 1306 } 1307 1308 /* 1309 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1310 * checksumming, set up the descriptor to do this work 1311 * for us. 1312 * 1313 * This apparently has to be on the first descriptor of 1314 * the packet. 1315 * 1316 * Byte-swap constants so the compiler can optimize. 1317 */ 1318 extsts = 0; 1319 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1320 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1321 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1322 extsts |= htole32(EXTSTS_IPPKT); 1323 } 1324 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1325 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1326 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1327 extsts |= htole32(EXTSTS_TCPPKT); 1328 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1329 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1330 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1331 extsts |= htole32(EXTSTS_UDPPKT); 1332 } 1333 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1334 #endif /* DP83820 */ 1335 1336 /* Sync the descriptors we're using. */ 1337 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1338 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1339 1340 /* 1341 * Store a pointer to the packet so we can free it later, 1342 * and remember what txdirty will be once the packet is 1343 * done. 1344 */ 1345 txs->txs_mbuf = m0; 1346 txs->txs_firstdesc = sc->sc_txnext; 1347 txs->txs_lastdesc = lasttx; 1348 1349 /* Advance the tx pointer. */ 1350 sc->sc_txfree -= dmamap->dm_nsegs; 1351 sc->sc_txnext = nexttx; 1352 1353 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs, txs_q); 1354 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1355 1356 #if NBPFILTER > 0 1357 /* 1358 * Pass the packet to any BPF listeners. 1359 */ 1360 if (ifp->if_bpf) 1361 bpf_mtap(ifp->if_bpf, m0); 1362 #endif /* NBPFILTER > 0 */ 1363 } 1364 1365 if (txs == NULL || sc->sc_txfree == 0) { 1366 /* No more slots left; notify upper layer. */ 1367 ifp->if_flags |= IFF_OACTIVE; 1368 } 1369 1370 if (sc->sc_txfree != ofree) { 1371 /* 1372 * The entire packet chain is set up. Give the 1373 * first descrptor to the chip now. 1374 */ 1375 sc->sc_txdescs[firsttx].sipd_cmdsts |= htole32(CMDSTS_OWN); 1376 SIP_CDTXSYNC(sc, firsttx, 1, 1377 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1378 1379 /* 1380 * Start the transmit process. Note, the manual says 1381 * that if there are no pending transmissions in the 1382 * chip's internal queue (indicated by TXE being clear), 1383 * then the driver software must set the TXDP to the 1384 * first descriptor to be transmitted. However, if we 1385 * do this, it causes serious performance degredation on 1386 * the DP83820 under load, not setting TXDP doesn't seem 1387 * to adversely affect the SiS 900 or DP83815. 1388 * 1389 * Well, I guess it wouldn't be the first time a manual 1390 * has lied -- and they could be speaking of the NULL- 1391 * terminated descriptor list case, rather than OWN- 1392 * terminated rings. 1393 */ 1394 #if 0 1395 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1396 CR_TXE) == 0) { 1397 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1398 SIP_CDTXADDR(sc, firsttx)); 1399 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1400 } 1401 #else 1402 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1403 #endif 1404 1405 /* Set a watchdog timer in case the chip flakes out. */ 1406 ifp->if_timer = 5; 1407 } 1408 } 1409 1410 /* 1411 * sip_watchdog: [ifnet interface function] 1412 * 1413 * Watchdog timer handler. 1414 */ 1415 void 1416 SIP_DECL(watchdog)(struct ifnet *ifp) 1417 { 1418 struct sip_softc *sc = ifp->if_softc; 1419 1420 /* 1421 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1422 * If we get a timeout, try and sweep up transmit descriptors. 1423 * If we manage to sweep them all up, ignore the lack of 1424 * interrupt. 1425 */ 1426 SIP_DECL(txintr)(sc); 1427 1428 if (sc->sc_txfree != SIP_NTXDESC) { 1429 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1430 ifp->if_oerrors++; 1431 1432 /* Reset the interface. */ 1433 (void) SIP_DECL(init)(ifp); 1434 } else if (ifp->if_flags & IFF_DEBUG) 1435 printf("%s: recovered from device timeout\n", 1436 sc->sc_dev.dv_xname); 1437 1438 /* Try to get more packets going. */ 1439 SIP_DECL(start)(ifp); 1440 } 1441 1442 /* 1443 * sip_ioctl: [ifnet interface function] 1444 * 1445 * Handle control requests from the operator. 1446 */ 1447 int 1448 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1449 { 1450 struct sip_softc *sc = ifp->if_softc; 1451 struct ifreq *ifr = (struct ifreq *)data; 1452 int s, error; 1453 1454 s = splnet(); 1455 1456 switch (cmd) { 1457 case SIOCSIFMEDIA: 1458 case SIOCGIFMEDIA: 1459 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1460 break; 1461 1462 default: 1463 error = ether_ioctl(ifp, cmd, data); 1464 if (error == ENETRESET) { 1465 /* 1466 * Multicast list has changed; set the hardware filter 1467 * accordingly. 1468 */ 1469 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1470 error = 0; 1471 } 1472 break; 1473 } 1474 1475 /* Try to get more packets going. */ 1476 SIP_DECL(start)(ifp); 1477 1478 splx(s); 1479 return (error); 1480 } 1481 1482 /* 1483 * sip_intr: 1484 * 1485 * Interrupt service routine. 1486 */ 1487 int 1488 SIP_DECL(intr)(void *arg) 1489 { 1490 struct sip_softc *sc = arg; 1491 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1492 u_int32_t isr; 1493 int handled = 0; 1494 1495 for (;;) { 1496 /* Reading clears interrupt. */ 1497 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1498 if ((isr & sc->sc_imr) == 0) 1499 break; 1500 1501 handled = 1; 1502 1503 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1504 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1505 1506 /* Grab any new packets. */ 1507 SIP_DECL(rxintr)(sc); 1508 1509 if (isr & ISR_RXORN) { 1510 printf("%s: receive FIFO overrun\n", 1511 sc->sc_dev.dv_xname); 1512 1513 /* XXX adjust rx_drain_thresh? */ 1514 } 1515 1516 if (isr & ISR_RXIDLE) { 1517 printf("%s: receive ring overrun\n", 1518 sc->sc_dev.dv_xname); 1519 1520 /* Get the receive process going again. */ 1521 bus_space_write_4(sc->sc_st, sc->sc_sh, 1522 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1523 bus_space_write_4(sc->sc_st, sc->sc_sh, 1524 SIP_CR, CR_RXE); 1525 } 1526 } 1527 1528 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1529 #ifdef SIP_EVENT_COUNTERS 1530 if (isr & ISR_TXDESC) 1531 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1532 else if (isr & ISR_TXIDLE) 1533 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1534 #endif 1535 1536 /* Sweep up transmit descriptors. */ 1537 SIP_DECL(txintr)(sc); 1538 1539 if (isr & ISR_TXURN) { 1540 u_int32_t thresh; 1541 1542 printf("%s: transmit FIFO underrun", 1543 sc->sc_dev.dv_xname); 1544 1545 thresh = sc->sc_tx_drain_thresh + 1; 1546 if (thresh <= TXCFG_DRTH && 1547 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1548 (sc->sc_tx_fill_thresh * 32))) { 1549 printf("; increasing Tx drain " 1550 "threshold to %u bytes\n", 1551 thresh * 32); 1552 sc->sc_tx_drain_thresh = thresh; 1553 (void) SIP_DECL(init)(ifp); 1554 } else { 1555 (void) SIP_DECL(init)(ifp); 1556 printf("\n"); 1557 } 1558 } 1559 } 1560 1561 #if !defined(DP83820) 1562 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1563 if (isr & ISR_PAUSE_ST) { 1564 sc->sc_flags |= SIPF_PAUSED; 1565 ifp->if_flags |= IFF_OACTIVE; 1566 } 1567 if (isr & ISR_PAUSE_END) { 1568 sc->sc_flags &= ~SIPF_PAUSED; 1569 ifp->if_flags &= ~IFF_OACTIVE; 1570 } 1571 } 1572 #endif /* ! DP83820 */ 1573 1574 if (isr & ISR_HIBERR) { 1575 #define PRINTERR(bit, str) \ 1576 if (isr & (bit)) \ 1577 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1578 PRINTERR(ISR_DPERR, "parity error"); 1579 PRINTERR(ISR_SSERR, "system error"); 1580 PRINTERR(ISR_RMABT, "master abort"); 1581 PRINTERR(ISR_RTABT, "target abort"); 1582 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1583 (void) SIP_DECL(init)(ifp); 1584 #undef PRINTERR 1585 } 1586 } 1587 1588 /* Try to get more packets going. */ 1589 SIP_DECL(start)(ifp); 1590 1591 return (handled); 1592 } 1593 1594 /* 1595 * sip_txintr: 1596 * 1597 * Helper; handle transmit interrupts. 1598 */ 1599 void 1600 SIP_DECL(txintr)(struct sip_softc *sc) 1601 { 1602 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1603 struct sip_txsoft *txs; 1604 u_int32_t cmdsts; 1605 1606 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1607 ifp->if_flags &= ~IFF_OACTIVE; 1608 1609 /* 1610 * Go through our Tx list and free mbufs for those 1611 * frames which have been transmitted. 1612 */ 1613 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1614 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1615 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1616 1617 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1618 if (cmdsts & CMDSTS_OWN) 1619 break; 1620 1621 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1622 1623 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1624 1625 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1626 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1627 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1628 m_freem(txs->txs_mbuf); 1629 txs->txs_mbuf = NULL; 1630 1631 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1632 1633 /* 1634 * Check for errors and collisions. 1635 */ 1636 if (cmdsts & 1637 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1638 ifp->if_oerrors++; 1639 if (cmdsts & CMDSTS_Tx_EC) 1640 ifp->if_collisions += 16; 1641 if (ifp->if_flags & IFF_DEBUG) { 1642 if (cmdsts & CMDSTS_Tx_ED) 1643 printf("%s: excessive deferral\n", 1644 sc->sc_dev.dv_xname); 1645 if (cmdsts & CMDSTS_Tx_EC) 1646 printf("%s: excessive collisions\n", 1647 sc->sc_dev.dv_xname); 1648 } 1649 } else { 1650 /* Packet was transmitted successfully. */ 1651 ifp->if_opackets++; 1652 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1653 } 1654 } 1655 1656 /* 1657 * If there are no more pending transmissions, cancel the watchdog 1658 * timer. 1659 */ 1660 if (txs == NULL) { 1661 ifp->if_timer = 0; 1662 sc->sc_txwin = 0; 1663 } 1664 } 1665 1666 #if defined(DP83820) 1667 /* 1668 * sip_rxintr: 1669 * 1670 * Helper; handle receive interrupts. 1671 */ 1672 void 1673 SIP_DECL(rxintr)(struct sip_softc *sc) 1674 { 1675 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1676 struct sip_rxsoft *rxs; 1677 struct mbuf *m, *tailm; 1678 u_int32_t cmdsts, extsts; 1679 int i, len; 1680 1681 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1682 rxs = &sc->sc_rxsoft[i]; 1683 1684 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1685 1686 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1687 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1688 1689 /* 1690 * NOTE: OWN is set if owned by _consumer_. We're the 1691 * consumer of the receive ring, so if the bit is clear, 1692 * we have processed all of the packets. 1693 */ 1694 if ((cmdsts & CMDSTS_OWN) == 0) { 1695 /* 1696 * We have processed all of the receive buffers. 1697 */ 1698 break; 1699 } 1700 1701 if (__predict_false(sc->sc_rxdiscard)) { 1702 SIP_INIT_RXDESC(sc, i); 1703 if ((cmdsts & CMDSTS_MORE) == 0) { 1704 /* Reset our state. */ 1705 sc->sc_rxdiscard = 0; 1706 } 1707 continue; 1708 } 1709 1710 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1711 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1712 1713 m = rxs->rxs_mbuf; 1714 1715 /* 1716 * Add a new receive buffer to the ring. 1717 */ 1718 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1719 /* 1720 * Failed, throw away what we've done so 1721 * far, and discard the rest of the packet. 1722 */ 1723 ifp->if_ierrors++; 1724 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1725 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1726 SIP_INIT_RXDESC(sc, i); 1727 if (cmdsts & CMDSTS_MORE) 1728 sc->sc_rxdiscard = 1; 1729 if (sc->sc_rxhead != NULL) 1730 m_freem(sc->sc_rxhead); 1731 SIP_RXCHAIN_RESET(sc); 1732 continue; 1733 } 1734 1735 SIP_RXCHAIN_LINK(sc, m); 1736 1737 /* 1738 * If this is not the end of the packet, keep 1739 * looking. 1740 */ 1741 if (cmdsts & CMDSTS_MORE) { 1742 sc->sc_rxlen += m->m_len; 1743 continue; 1744 } 1745 1746 /* 1747 * Okay, we have the entire packet now... 1748 */ 1749 *sc->sc_rxtailp = NULL; 1750 m = sc->sc_rxhead; 1751 tailm = sc->sc_rxtail; 1752 1753 SIP_RXCHAIN_RESET(sc); 1754 1755 /* 1756 * If an error occurred, update stats and drop the packet. 1757 */ 1758 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1759 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1760 ifp->if_ierrors++; 1761 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1762 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1763 /* Receive overrun handled elsewhere. */ 1764 printf("%s: receive descriptor error\n", 1765 sc->sc_dev.dv_xname); 1766 } 1767 #define PRINTERR(bit, str) \ 1768 if (cmdsts & (bit)) \ 1769 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1770 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1771 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1772 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1773 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1774 #undef PRINTERR 1775 m_freem(m); 1776 continue; 1777 } 1778 1779 /* 1780 * No errors. 1781 * 1782 * Note, the DP83820 includes the CRC with 1783 * every packet. 1784 */ 1785 len = CMDSTS_SIZE(cmdsts); 1786 tailm->m_len = len - sc->sc_rxlen; 1787 1788 /* 1789 * If the packet is small enough to fit in a 1790 * single header mbuf, allocate one and copy 1791 * the data into it. This greatly reduces 1792 * memory consumption when we receive lots 1793 * of small packets. 1794 */ 1795 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1796 struct mbuf *nm; 1797 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1798 if (nm == NULL) { 1799 ifp->if_ierrors++; 1800 m_freem(m); 1801 continue; 1802 } 1803 nm->m_data += 2; 1804 nm->m_pkthdr.len = nm->m_len = len; 1805 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1806 m_freem(m); 1807 m = nm; 1808 } 1809 #ifndef __NO_STRICT_ALIGNMENT 1810 else { 1811 /* 1812 * The DP83820's receive buffers must be 4-byte 1813 * aligned. But this means that the data after 1814 * the Ethernet header is misaligned. To compensate, 1815 * we have artificially shortened the buffer size 1816 * in the descriptor, and we do an overlapping copy 1817 * of the data two bytes further in (in the first 1818 * buffer of the chain only). 1819 */ 1820 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1821 m->m_len); 1822 m->m_data += 2; 1823 } 1824 #endif /* ! __NO_STRICT_ALIGNMENT */ 1825 1826 /* 1827 * If VLANs are enabled, VLAN packets have been unwrapped 1828 * for us. Associate the tag with the packet. 1829 */ 1830 if (sc->sc_ethercom.ec_nvlans != 0 && 1831 (extsts & EXTSTS_VPKT) != 0) { 1832 struct mbuf *vtag; 1833 1834 vtag = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 1835 if (vtag == NULL) { 1836 ifp->if_ierrors++; 1837 printf("%s: unable to allocate VLAN tag\n", 1838 sc->sc_dev.dv_xname); 1839 m_freem(m); 1840 continue; 1841 } 1842 1843 *mtod(vtag, int *) = ntohs(extsts & EXTSTS_VTCI); 1844 vtag->m_len = sizeof(int); 1845 } 1846 1847 /* 1848 * Set the incoming checksum information for the 1849 * packet. 1850 */ 1851 if ((extsts & EXTSTS_IPPKT) != 0) { 1852 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1853 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1854 if (extsts & EXTSTS_Rx_IPERR) 1855 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1856 if (extsts & EXTSTS_TCPPKT) { 1857 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1858 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1859 if (extsts & EXTSTS_Rx_TCPERR) 1860 m->m_pkthdr.csum_flags |= 1861 M_CSUM_TCP_UDP_BAD; 1862 } else if (extsts & EXTSTS_UDPPKT) { 1863 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1864 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1865 if (extsts & EXTSTS_Rx_UDPERR) 1866 m->m_pkthdr.csum_flags |= 1867 M_CSUM_TCP_UDP_BAD; 1868 } 1869 } 1870 1871 ifp->if_ipackets++; 1872 m->m_flags |= M_HASFCS; 1873 m->m_pkthdr.rcvif = ifp; 1874 m->m_pkthdr.len = len; 1875 1876 #if NBPFILTER > 0 1877 /* 1878 * Pass this up to any BPF listeners, but only 1879 * pass if up the stack if it's for us. 1880 */ 1881 if (ifp->if_bpf) 1882 bpf_mtap(ifp->if_bpf, m); 1883 #endif /* NBPFILTER > 0 */ 1884 1885 /* Pass it on. */ 1886 (*ifp->if_input)(ifp, m); 1887 } 1888 1889 /* Update the receive pointer. */ 1890 sc->sc_rxptr = i; 1891 } 1892 #else /* ! DP83820 */ 1893 /* 1894 * sip_rxintr: 1895 * 1896 * Helper; handle receive interrupts. 1897 */ 1898 void 1899 SIP_DECL(rxintr)(struct sip_softc *sc) 1900 { 1901 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1902 struct sip_rxsoft *rxs; 1903 struct mbuf *m; 1904 u_int32_t cmdsts; 1905 int i, len; 1906 1907 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1908 rxs = &sc->sc_rxsoft[i]; 1909 1910 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1911 1912 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1913 1914 /* 1915 * NOTE: OWN is set if owned by _consumer_. We're the 1916 * consumer of the receive ring, so if the bit is clear, 1917 * we have processed all of the packets. 1918 */ 1919 if ((cmdsts & CMDSTS_OWN) == 0) { 1920 /* 1921 * We have processed all of the receive buffers. 1922 */ 1923 break; 1924 } 1925 1926 /* 1927 * If any collisions were seen on the wire, count one. 1928 */ 1929 if (cmdsts & CMDSTS_Rx_COL) 1930 ifp->if_collisions++; 1931 1932 /* 1933 * If an error occurred, update stats, clear the status 1934 * word, and leave the packet buffer in place. It will 1935 * simply be reused the next time the ring comes around. 1936 */ 1937 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1938 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1939 ifp->if_ierrors++; 1940 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1941 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1942 /* Receive overrun handled elsewhere. */ 1943 printf("%s: receive descriptor error\n", 1944 sc->sc_dev.dv_xname); 1945 } 1946 #define PRINTERR(bit, str) \ 1947 if (cmdsts & (bit)) \ 1948 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1949 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1950 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1951 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1952 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1953 #undef PRINTERR 1954 SIP_INIT_RXDESC(sc, i); 1955 continue; 1956 } 1957 1958 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1959 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1960 1961 /* 1962 * No errors; receive the packet. Note, the SiS 900 1963 * includes the CRC with every packet. 1964 */ 1965 len = CMDSTS_SIZE(cmdsts); 1966 1967 #ifdef __NO_STRICT_ALIGNMENT 1968 /* 1969 * If the packet is small enough to fit in a 1970 * single header mbuf, allocate one and copy 1971 * the data into it. This greatly reduces 1972 * memory consumption when we receive lots 1973 * of small packets. 1974 * 1975 * Otherwise, we add a new buffer to the receive 1976 * chain. If this fails, we drop the packet and 1977 * recycle the old buffer. 1978 */ 1979 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 1980 MGETHDR(m, M_DONTWAIT, MT_DATA); 1981 if (m == NULL) 1982 goto dropit; 1983 memcpy(mtod(m, caddr_t), 1984 mtod(rxs->rxs_mbuf, caddr_t), len); 1985 SIP_INIT_RXDESC(sc, i); 1986 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1987 rxs->rxs_dmamap->dm_mapsize, 1988 BUS_DMASYNC_PREREAD); 1989 } else { 1990 m = rxs->rxs_mbuf; 1991 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1992 dropit: 1993 ifp->if_ierrors++; 1994 SIP_INIT_RXDESC(sc, i); 1995 bus_dmamap_sync(sc->sc_dmat, 1996 rxs->rxs_dmamap, 0, 1997 rxs->rxs_dmamap->dm_mapsize, 1998 BUS_DMASYNC_PREREAD); 1999 continue; 2000 } 2001 } 2002 #else 2003 /* 2004 * The SiS 900's receive buffers must be 4-byte aligned. 2005 * But this means that the data after the Ethernet header 2006 * is misaligned. We must allocate a new buffer and 2007 * copy the data, shifted forward 2 bytes. 2008 */ 2009 MGETHDR(m, M_DONTWAIT, MT_DATA); 2010 if (m == NULL) { 2011 dropit: 2012 ifp->if_ierrors++; 2013 SIP_INIT_RXDESC(sc, i); 2014 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2015 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2016 continue; 2017 } 2018 if (len > (MHLEN - 2)) { 2019 MCLGET(m, M_DONTWAIT); 2020 if ((m->m_flags & M_EXT) == 0) { 2021 m_freem(m); 2022 goto dropit; 2023 } 2024 } 2025 m->m_data += 2; 2026 2027 /* 2028 * Note that we use clusters for incoming frames, so the 2029 * buffer is virtually contiguous. 2030 */ 2031 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 2032 2033 /* Allow the receive descriptor to continue using its mbuf. */ 2034 SIP_INIT_RXDESC(sc, i); 2035 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2036 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2037 #endif /* __NO_STRICT_ALIGNMENT */ 2038 2039 ifp->if_ipackets++; 2040 m->m_flags |= M_HASFCS; 2041 m->m_pkthdr.rcvif = ifp; 2042 m->m_pkthdr.len = m->m_len = len; 2043 2044 #if NBPFILTER > 0 2045 /* 2046 * Pass this up to any BPF listeners, but only 2047 * pass if up the stack if it's for us. 2048 */ 2049 if (ifp->if_bpf) 2050 bpf_mtap(ifp->if_bpf, m); 2051 #endif /* NBPFILTER > 0 */ 2052 2053 /* Pass it on. */ 2054 (*ifp->if_input)(ifp, m); 2055 } 2056 2057 /* Update the receive pointer. */ 2058 sc->sc_rxptr = i; 2059 } 2060 #endif /* DP83820 */ 2061 2062 /* 2063 * sip_tick: 2064 * 2065 * One second timer, used to tick the MII. 2066 */ 2067 void 2068 SIP_DECL(tick)(void *arg) 2069 { 2070 struct sip_softc *sc = arg; 2071 int s; 2072 2073 s = splnet(); 2074 mii_tick(&sc->sc_mii); 2075 splx(s); 2076 2077 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2078 } 2079 2080 /* 2081 * sip_reset: 2082 * 2083 * Perform a soft reset on the SiS 900. 2084 */ 2085 void 2086 SIP_DECL(reset)(struct sip_softc *sc) 2087 { 2088 bus_space_tag_t st = sc->sc_st; 2089 bus_space_handle_t sh = sc->sc_sh; 2090 int i; 2091 2092 bus_space_write_4(st, sh, SIP_IER, 0); 2093 bus_space_write_4(st, sh, SIP_IMR, 0); 2094 bus_space_write_4(st, sh, SIP_RFCR, 0); 2095 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2096 2097 for (i = 0; i < SIP_TIMEOUT; i++) { 2098 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2099 break; 2100 delay(2); 2101 } 2102 2103 if (i == SIP_TIMEOUT) 2104 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2105 2106 delay(1000); 2107 2108 #ifdef DP83820 2109 /* 2110 * Set the general purpose I/O bits. Do it here in case we 2111 * need to have GPIO set up to talk to the media interface. 2112 */ 2113 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2114 delay(1000); 2115 #endif /* DP83820 */ 2116 } 2117 2118 /* 2119 * sip_init: [ ifnet interface function ] 2120 * 2121 * Initialize the interface. Must be called at splnet(). 2122 */ 2123 int 2124 SIP_DECL(init)(struct ifnet *ifp) 2125 { 2126 struct sip_softc *sc = ifp->if_softc; 2127 bus_space_tag_t st = sc->sc_st; 2128 bus_space_handle_t sh = sc->sc_sh; 2129 struct sip_txsoft *txs; 2130 struct sip_rxsoft *rxs; 2131 struct sip_desc *sipd; 2132 u_int32_t reg; 2133 int i, error = 0; 2134 2135 /* 2136 * Cancel any pending I/O. 2137 */ 2138 SIP_DECL(stop)(ifp, 0); 2139 2140 /* 2141 * Reset the chip to a known state. 2142 */ 2143 SIP_DECL(reset)(sc); 2144 2145 #if !defined(DP83820) 2146 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2147 /* 2148 * DP83815 manual, page 78: 2149 * 4.4 Recommended Registers Configuration 2150 * For optimum performance of the DP83815, version noted 2151 * as DP83815CVNG (SRR = 203h), the listed register 2152 * modifications must be followed in sequence... 2153 * 2154 * It's not clear if this should be 302h or 203h because that 2155 * chip name is listed as SRR 302h in the description of the 2156 * SRR register. However, my revision 302h DP83815 on the 2157 * Netgear FA311 purchased in 02/2001 needs these settings 2158 * to avoid tons of errors in AcceptPerfectMatch (non- 2159 * IFF_PROMISC) mode. I do not know if other revisions need 2160 * this set or not. [briggs -- 09 March 2001] 2161 * 2162 * Note that only the low-order 12 bits of 0xe4 are documented 2163 * and that this sets reserved bits in that register. 2164 */ 2165 reg = bus_space_read_4(st, sh, SIP_NS_SRR); 2166 if (reg == 0x302) { 2167 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2168 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2169 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2170 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2171 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2172 } 2173 } 2174 #endif /* ! DP83820 */ 2175 2176 /* 2177 * Initialize the transmit descriptor ring. 2178 */ 2179 for (i = 0; i < SIP_NTXDESC; i++) { 2180 sipd = &sc->sc_txdescs[i]; 2181 memset(sipd, 0, sizeof(struct sip_desc)); 2182 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2183 } 2184 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2185 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2186 sc->sc_txfree = SIP_NTXDESC; 2187 sc->sc_txnext = 0; 2188 sc->sc_txwin = 0; 2189 2190 /* 2191 * Initialize the transmit job descriptors. 2192 */ 2193 SIMPLEQ_INIT(&sc->sc_txfreeq); 2194 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2195 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2196 txs = &sc->sc_txsoft[i]; 2197 txs->txs_mbuf = NULL; 2198 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2199 } 2200 2201 /* 2202 * Initialize the receive descriptor and receive job 2203 * descriptor rings. 2204 */ 2205 for (i = 0; i < SIP_NRXDESC; i++) { 2206 rxs = &sc->sc_rxsoft[i]; 2207 if (rxs->rxs_mbuf == NULL) { 2208 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2209 printf("%s: unable to allocate or map rx " 2210 "buffer %d, error = %d\n", 2211 sc->sc_dev.dv_xname, i, error); 2212 /* 2213 * XXX Should attempt to run with fewer receive 2214 * XXX buffers instead of just failing. 2215 */ 2216 SIP_DECL(rxdrain)(sc); 2217 goto out; 2218 } 2219 } else 2220 SIP_INIT_RXDESC(sc, i); 2221 } 2222 sc->sc_rxptr = 0; 2223 #ifdef DP83820 2224 sc->sc_rxdiscard = 0; 2225 SIP_RXCHAIN_RESET(sc); 2226 #endif /* DP83820 */ 2227 2228 /* 2229 * Set the configuration register; it's already initialized 2230 * in sip_attach(). 2231 */ 2232 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2233 2234 /* 2235 * Initialize the prototype TXCFG register. 2236 */ 2237 #if defined(DP83820) 2238 sc->sc_txcfg = TXCFG_MXDMA_512; 2239 sc->sc_rxcfg = RXCFG_MXDMA_512; 2240 #else 2241 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2242 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2243 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & CFG_EDBMASTEN)) { 2244 sc->sc_txcfg = TXCFG_MXDMA_64; 2245 sc->sc_rxcfg = RXCFG_MXDMA_64; 2246 } else { 2247 sc->sc_txcfg = TXCFG_MXDMA_512; 2248 sc->sc_rxcfg = RXCFG_MXDMA_512; 2249 } 2250 #endif /* DP83820 */ 2251 2252 sc->sc_txcfg |= TXCFG_ATP | 2253 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2254 sc->sc_tx_drain_thresh; 2255 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2256 2257 /* 2258 * Initialize the receive drain threshold if we have never 2259 * done so. 2260 */ 2261 if (sc->sc_rx_drain_thresh == 0) { 2262 /* 2263 * XXX This value should be tuned. This is set to the 2264 * maximum of 248 bytes, and we may be able to improve 2265 * performance by decreasing it (although we should never 2266 * set this value lower than 2; 14 bytes are required to 2267 * filter the packet). 2268 */ 2269 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2270 } 2271 2272 /* 2273 * Initialize the prototype RXCFG register. 2274 */ 2275 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2276 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2277 2278 #ifdef DP83820 2279 /* 2280 * Initialize the VLAN/IP receive control register. 2281 * We enable checksum computation on all incoming 2282 * packets, and do not reject packets w/ bad checksums. 2283 */ 2284 reg = 0; 2285 if (ifp->if_capenable & 2286 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2287 reg |= VRCR_IPEN; 2288 if (sc->sc_ethercom.ec_nvlans != 0) 2289 reg |= VRCR_VTDEN|VRCR_VTREN; 2290 bus_space_write_4(st, sh, SIP_VRCR, reg); 2291 2292 /* 2293 * Initialize the VLAN/IP transmit control register. 2294 * We enable outgoing checksum computation on a 2295 * per-packet basis. 2296 */ 2297 reg = 0; 2298 if (ifp->if_capenable & 2299 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2300 reg |= VTCR_PPCHK; 2301 if (sc->sc_ethercom.ec_nvlans != 0) 2302 reg |= VTCR_VPPTI; 2303 bus_space_write_4(st, sh, SIP_VTCR, reg); 2304 2305 /* 2306 * If we're using VLANs, initialize the VLAN data register. 2307 * To understand why we bswap the VLAN Ethertype, see section 2308 * 4.2.36 of the DP83820 manual. 2309 */ 2310 if (sc->sc_ethercom.ec_nvlans != 0) 2311 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2312 #endif /* DP83820 */ 2313 2314 /* 2315 * Give the transmit and receive rings to the chip. 2316 */ 2317 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2318 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2319 2320 /* 2321 * Initialize the interrupt mask. 2322 */ 2323 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2324 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2325 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2326 2327 /* Set up the receive filter. */ 2328 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2329 2330 /* 2331 * Set the current media. Do this after initializing the prototype 2332 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2333 * control. 2334 */ 2335 mii_mediachg(&sc->sc_mii); 2336 2337 /* 2338 * Enable interrupts. 2339 */ 2340 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2341 2342 /* 2343 * Start the transmit and receive processes. 2344 */ 2345 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2346 2347 /* 2348 * Start the one second MII clock. 2349 */ 2350 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2351 2352 /* 2353 * ...all done! 2354 */ 2355 ifp->if_flags |= IFF_RUNNING; 2356 ifp->if_flags &= ~IFF_OACTIVE; 2357 2358 out: 2359 if (error) 2360 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2361 return (error); 2362 } 2363 2364 /* 2365 * sip_drain: 2366 * 2367 * Drain the receive queue. 2368 */ 2369 void 2370 SIP_DECL(rxdrain)(struct sip_softc *sc) 2371 { 2372 struct sip_rxsoft *rxs; 2373 int i; 2374 2375 for (i = 0; i < SIP_NRXDESC; i++) { 2376 rxs = &sc->sc_rxsoft[i]; 2377 if (rxs->rxs_mbuf != NULL) { 2378 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2379 m_freem(rxs->rxs_mbuf); 2380 rxs->rxs_mbuf = NULL; 2381 } 2382 } 2383 } 2384 2385 /* 2386 * sip_stop: [ ifnet interface function ] 2387 * 2388 * Stop transmission on the interface. 2389 */ 2390 void 2391 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2392 { 2393 struct sip_softc *sc = ifp->if_softc; 2394 bus_space_tag_t st = sc->sc_st; 2395 bus_space_handle_t sh = sc->sc_sh; 2396 struct sip_txsoft *txs; 2397 u_int32_t cmdsts = 0; /* DEBUG */ 2398 2399 /* 2400 * Stop the one second clock. 2401 */ 2402 callout_stop(&sc->sc_tick_ch); 2403 2404 /* Down the MII. */ 2405 mii_down(&sc->sc_mii); 2406 2407 /* 2408 * Disable interrupts. 2409 */ 2410 bus_space_write_4(st, sh, SIP_IER, 0); 2411 2412 /* 2413 * Stop receiver and transmitter. 2414 */ 2415 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2416 2417 /* 2418 * Release any queued transmit buffers. 2419 */ 2420 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2421 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2422 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2423 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2424 CMDSTS_INTR) == 0) 2425 printf("%s: sip_stop: last descriptor does not " 2426 "have INTR bit set\n", sc->sc_dev.dv_xname); 2427 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 2428 #ifdef DIAGNOSTIC 2429 if (txs->txs_mbuf == NULL) { 2430 printf("%s: dirty txsoft with no mbuf chain\n", 2431 sc->sc_dev.dv_xname); 2432 panic("sip_stop"); 2433 } 2434 #endif 2435 cmdsts |= /* DEBUG */ 2436 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2437 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2438 m_freem(txs->txs_mbuf); 2439 txs->txs_mbuf = NULL; 2440 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2441 } 2442 2443 if (disable) 2444 SIP_DECL(rxdrain)(sc); 2445 2446 /* 2447 * Mark the interface down and cancel the watchdog timer. 2448 */ 2449 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2450 ifp->if_timer = 0; 2451 2452 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2453 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2454 printf("%s: sip_stop: no INTR bits set in dirty tx " 2455 "descriptors\n", sc->sc_dev.dv_xname); 2456 } 2457 2458 /* 2459 * sip_read_eeprom: 2460 * 2461 * Read data from the serial EEPROM. 2462 */ 2463 void 2464 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2465 u_int16_t *data) 2466 { 2467 bus_space_tag_t st = sc->sc_st; 2468 bus_space_handle_t sh = sc->sc_sh; 2469 u_int16_t reg; 2470 int i, x; 2471 2472 for (i = 0; i < wordcnt; i++) { 2473 /* Send CHIP SELECT. */ 2474 reg = EROMAR_EECS; 2475 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2476 2477 /* Shift in the READ opcode. */ 2478 for (x = 3; x > 0; x--) { 2479 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2480 reg |= EROMAR_EEDI; 2481 else 2482 reg &= ~EROMAR_EEDI; 2483 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2484 bus_space_write_4(st, sh, SIP_EROMAR, 2485 reg | EROMAR_EESK); 2486 delay(4); 2487 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2488 delay(4); 2489 } 2490 2491 /* Shift in address. */ 2492 for (x = 6; x > 0; x--) { 2493 if ((word + i) & (1 << (x - 1))) 2494 reg |= EROMAR_EEDI; 2495 else 2496 reg &= ~EROMAR_EEDI; 2497 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2498 bus_space_write_4(st, sh, SIP_EROMAR, 2499 reg | EROMAR_EESK); 2500 delay(4); 2501 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2502 delay(4); 2503 } 2504 2505 /* Shift out data. */ 2506 reg = EROMAR_EECS; 2507 data[i] = 0; 2508 for (x = 16; x > 0; x--) { 2509 bus_space_write_4(st, sh, SIP_EROMAR, 2510 reg | EROMAR_EESK); 2511 delay(4); 2512 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2513 data[i] |= (1 << (x - 1)); 2514 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2515 delay(4); 2516 } 2517 2518 /* Clear CHIP SELECT. */ 2519 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2520 delay(4); 2521 } 2522 } 2523 2524 /* 2525 * sip_add_rxbuf: 2526 * 2527 * Add a receive buffer to the indicated descriptor. 2528 */ 2529 int 2530 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2531 { 2532 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2533 struct mbuf *m; 2534 int error; 2535 2536 MGETHDR(m, M_DONTWAIT, MT_DATA); 2537 if (m == NULL) 2538 return (ENOBUFS); 2539 2540 MCLGET(m, M_DONTWAIT); 2541 if ((m->m_flags & M_EXT) == 0) { 2542 m_freem(m); 2543 return (ENOBUFS); 2544 } 2545 2546 #if defined(DP83820) 2547 m->m_len = SIP_RXBUF_LEN; 2548 #endif /* DP83820 */ 2549 2550 if (rxs->rxs_mbuf != NULL) 2551 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2552 2553 rxs->rxs_mbuf = m; 2554 2555 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2556 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2557 BUS_DMA_READ|BUS_DMA_NOWAIT); 2558 if (error) { 2559 printf("%s: can't load rx DMA map %d, error = %d\n", 2560 sc->sc_dev.dv_xname, idx, error); 2561 panic("sip_add_rxbuf"); /* XXX */ 2562 } 2563 2564 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2565 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2566 2567 SIP_INIT_RXDESC(sc, idx); 2568 2569 return (0); 2570 } 2571 2572 #if !defined(DP83820) 2573 /* 2574 * sip_sis900_set_filter: 2575 * 2576 * Set up the receive filter. 2577 */ 2578 void 2579 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2580 { 2581 bus_space_tag_t st = sc->sc_st; 2582 bus_space_handle_t sh = sc->sc_sh; 2583 struct ethercom *ec = &sc->sc_ethercom; 2584 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2585 struct ether_multi *enm; 2586 u_int8_t *cp; 2587 struct ether_multistep step; 2588 u_int32_t crc, mchash[16]; 2589 2590 /* 2591 * Initialize the prototype RFCR. 2592 */ 2593 sc->sc_rfcr = RFCR_RFEN; 2594 if (ifp->if_flags & IFF_BROADCAST) 2595 sc->sc_rfcr |= RFCR_AAB; 2596 if (ifp->if_flags & IFF_PROMISC) { 2597 sc->sc_rfcr |= RFCR_AAP; 2598 goto allmulti; 2599 } 2600 2601 /* 2602 * Set up the multicast address filter by passing all multicast 2603 * addresses through a CRC generator, and then using the high-order 2604 * 6 bits as an index into the 128 bit multicast hash table (only 2605 * the lower 16 bits of each 32 bit multicast hash register are 2606 * valid). The high order bits select the register, while the 2607 * rest of the bits select the bit within the register. 2608 */ 2609 2610 memset(mchash, 0, sizeof(mchash)); 2611 2612 ETHER_FIRST_MULTI(step, ec, enm); 2613 while (enm != NULL) { 2614 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2615 /* 2616 * We must listen to a range of multicast addresses. 2617 * For now, just accept all multicasts, rather than 2618 * trying to set only those filter bits needed to match 2619 * the range. (At this time, the only use of address 2620 * ranges is for IP multicast routing, for which the 2621 * range is big enough to require all bits set.) 2622 */ 2623 goto allmulti; 2624 } 2625 2626 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2627 2628 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2629 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2630 /* Just want the 8 most significant bits. */ 2631 crc >>= 24; 2632 } else { 2633 /* Just want the 7 most significant bits. */ 2634 crc >>= 25; 2635 } 2636 2637 /* Set the corresponding bit in the hash table. */ 2638 mchash[crc >> 4] |= 1 << (crc & 0xf); 2639 2640 ETHER_NEXT_MULTI(step, enm); 2641 } 2642 2643 ifp->if_flags &= ~IFF_ALLMULTI; 2644 goto setit; 2645 2646 allmulti: 2647 ifp->if_flags |= IFF_ALLMULTI; 2648 sc->sc_rfcr |= RFCR_AAM; 2649 2650 setit: 2651 #define FILTER_EMIT(addr, data) \ 2652 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2653 delay(1); \ 2654 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2655 delay(1) 2656 2657 /* 2658 * Disable receive filter, and program the node address. 2659 */ 2660 cp = LLADDR(ifp->if_sadl); 2661 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2662 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2663 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2664 2665 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2666 /* 2667 * Program the multicast hash table. 2668 */ 2669 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2670 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2671 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2672 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2673 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2674 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2675 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2676 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2677 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2678 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2679 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2680 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2681 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2682 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2683 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2684 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2685 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2686 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2687 } 2688 } 2689 #undef FILTER_EMIT 2690 2691 /* 2692 * Re-enable the receiver filter. 2693 */ 2694 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2695 } 2696 #endif /* ! DP83820 */ 2697 2698 /* 2699 * sip_dp83815_set_filter: 2700 * 2701 * Set up the receive filter. 2702 */ 2703 void 2704 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2705 { 2706 bus_space_tag_t st = sc->sc_st; 2707 bus_space_handle_t sh = sc->sc_sh; 2708 struct ethercom *ec = &sc->sc_ethercom; 2709 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2710 struct ether_multi *enm; 2711 u_int8_t *cp; 2712 struct ether_multistep step; 2713 u_int32_t crc, hash, slot, bit; 2714 #ifdef DP83820 2715 #define MCHASH_NWORDS 128 2716 #else 2717 #define MCHASH_NWORDS 32 2718 #endif /* DP83820 */ 2719 u_int16_t mchash[MCHASH_NWORDS]; 2720 int i; 2721 2722 /* 2723 * Initialize the prototype RFCR. 2724 * Enable the receive filter, and accept on 2725 * Perfect (destination address) Match 2726 * If IFF_BROADCAST, also accept all broadcast packets. 2727 * If IFF_PROMISC, accept all unicast packets (and later, set 2728 * IFF_ALLMULTI and accept all multicast, too). 2729 */ 2730 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2731 if (ifp->if_flags & IFF_BROADCAST) 2732 sc->sc_rfcr |= RFCR_AAB; 2733 if (ifp->if_flags & IFF_PROMISC) { 2734 sc->sc_rfcr |= RFCR_AAP; 2735 goto allmulti; 2736 } 2737 2738 #ifdef DP83820 2739 /* 2740 * Set up the DP83820 multicast address filter by passing all multicast 2741 * addresses through a CRC generator, and then using the high-order 2742 * 11 bits as an index into the 2048 bit multicast hash table. The 2743 * high-order 7 bits select the slot, while the low-order 4 bits 2744 * select the bit within the slot. Note that only the low 16-bits 2745 * of each filter word are used, and there are 128 filter words. 2746 */ 2747 #else 2748 /* 2749 * Set up the DP83815 multicast address filter by passing all multicast 2750 * addresses through a CRC generator, and then using the high-order 2751 * 9 bits as an index into the 512 bit multicast hash table. The 2752 * high-order 5 bits select the slot, while the low-order 4 bits 2753 * select the bit within the slot. Note that only the low 16-bits 2754 * of each filter word are used, and there are 32 filter words. 2755 */ 2756 #endif /* DP83820 */ 2757 2758 memset(mchash, 0, sizeof(mchash)); 2759 2760 ifp->if_flags &= ~IFF_ALLMULTI; 2761 ETHER_FIRST_MULTI(step, ec, enm); 2762 if (enm == NULL) 2763 goto setit; 2764 while (enm != NULL) { 2765 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2766 /* 2767 * We must listen to a range of multicast addresses. 2768 * For now, just accept all multicasts, rather than 2769 * trying to set only those filter bits needed to match 2770 * the range. (At this time, the only use of address 2771 * ranges is for IP multicast routing, for which the 2772 * range is big enough to require all bits set.) 2773 */ 2774 goto allmulti; 2775 } 2776 2777 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2778 2779 #ifdef DP83820 2780 /* Just want the 11 most significant bits. */ 2781 hash = crc >> 21; 2782 #else 2783 /* Just want the 9 most significant bits. */ 2784 hash = crc >> 23; 2785 #endif /* DP83820 */ 2786 2787 slot = hash >> 4; 2788 bit = hash & 0xf; 2789 2790 /* Set the corresponding bit in the hash table. */ 2791 mchash[slot] |= 1 << bit; 2792 2793 ETHER_NEXT_MULTI(step, enm); 2794 } 2795 sc->sc_rfcr |= RFCR_MHEN; 2796 goto setit; 2797 2798 allmulti: 2799 ifp->if_flags |= IFF_ALLMULTI; 2800 sc->sc_rfcr |= RFCR_AAM; 2801 2802 setit: 2803 #define FILTER_EMIT(addr, data) \ 2804 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2805 delay(1); \ 2806 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2807 delay(1) 2808 2809 /* 2810 * Disable receive filter, and program the node address. 2811 */ 2812 cp = LLADDR(ifp->if_sadl); 2813 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 2814 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 2815 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 2816 2817 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2818 /* 2819 * Program the multicast hash table. 2820 */ 2821 for (i = 0; i < MCHASH_NWORDS; i++) { 2822 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 2823 mchash[i]); 2824 } 2825 } 2826 #undef FILTER_EMIT 2827 #undef MCHASH_NWORDS 2828 2829 /* 2830 * Re-enable the receiver filter. 2831 */ 2832 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2833 } 2834 2835 #if defined(DP83820) 2836 /* 2837 * sip_dp83820_mii_readreg: [mii interface function] 2838 * 2839 * Read a PHY register on the MII of the DP83820. 2840 */ 2841 int 2842 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 2843 { 2844 2845 return (mii_bitbang_readreg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2846 phy, reg)); 2847 } 2848 2849 /* 2850 * sip_dp83820_mii_writereg: [mii interface function] 2851 * 2852 * Write a PHY register on the MII of the DP83820. 2853 */ 2854 void 2855 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 2856 { 2857 2858 mii_bitbang_writereg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2859 phy, reg, val); 2860 } 2861 2862 /* 2863 * sip_dp83815_mii_statchg: [mii interface function] 2864 * 2865 * Callback from MII layer when media changes. 2866 */ 2867 void 2868 SIP_DECL(dp83820_mii_statchg)(struct device *self) 2869 { 2870 struct sip_softc *sc = (struct sip_softc *) self; 2871 u_int32_t cfg; 2872 2873 /* 2874 * Update TXCFG for full-duplex operation. 2875 */ 2876 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2877 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2878 else 2879 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2880 2881 /* 2882 * Update RXCFG for full-duplex or loopback. 2883 */ 2884 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2885 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2886 sc->sc_rxcfg |= RXCFG_ATX; 2887 else 2888 sc->sc_rxcfg &= ~RXCFG_ATX; 2889 2890 /* 2891 * Update CFG for MII/GMII. 2892 */ 2893 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2894 cfg = sc->sc_cfg | CFG_MODE_1000; 2895 else 2896 cfg = sc->sc_cfg; 2897 2898 /* 2899 * XXX 802.3x flow control. 2900 */ 2901 2902 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 2903 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2904 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2905 } 2906 2907 /* 2908 * sip_dp83820_mii_bitbang_read: [mii bit-bang interface function] 2909 * 2910 * Read the MII serial port for the MII bit-bang module. 2911 */ 2912 u_int32_t 2913 SIP_DECL(dp83820_mii_bitbang_read)(struct device *self) 2914 { 2915 struct sip_softc *sc = (void *) self; 2916 2917 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 2918 } 2919 2920 /* 2921 * sip_dp83820_mii_bitbang_write: [mii big-bang interface function] 2922 * 2923 * Write the MII serial port for the MII bit-bang module. 2924 */ 2925 void 2926 SIP_DECL(dp83820_mii_bitbang_write)(struct device *self, u_int32_t val) 2927 { 2928 struct sip_softc *sc = (void *) self; 2929 2930 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 2931 } 2932 #else /* ! DP83820 */ 2933 /* 2934 * sip_sis900_mii_readreg: [mii interface function] 2935 * 2936 * Read a PHY register on the MII. 2937 */ 2938 int 2939 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 2940 { 2941 struct sip_softc *sc = (struct sip_softc *) self; 2942 u_int32_t enphy; 2943 2944 /* 2945 * The SiS 900 has only an internal PHY on the MII. Only allow 2946 * MII address 0. 2947 */ 2948 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 2949 sc->sc_rev < SIS_REV_635 && phy != 0) 2950 return (0); 2951 2952 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2953 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 2954 ENPHY_RWCMD | ENPHY_ACCESS); 2955 do { 2956 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2957 } while (enphy & ENPHY_ACCESS); 2958 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 2959 } 2960 2961 /* 2962 * sip_sis900_mii_writereg: [mii interface function] 2963 * 2964 * Write a PHY register on the MII. 2965 */ 2966 void 2967 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 2968 { 2969 struct sip_softc *sc = (struct sip_softc *) self; 2970 u_int32_t enphy; 2971 2972 /* 2973 * The SiS 900 has only an internal PHY on the MII. Only allow 2974 * MII address 0. 2975 */ 2976 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 2977 sc->sc_rev < SIS_REV_635 && phy != 0) 2978 return; 2979 2980 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2981 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 2982 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 2983 do { 2984 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2985 } while (enphy & ENPHY_ACCESS); 2986 } 2987 2988 /* 2989 * sip_sis900_mii_statchg: [mii interface function] 2990 * 2991 * Callback from MII layer when media changes. 2992 */ 2993 void 2994 SIP_DECL(sis900_mii_statchg)(struct device *self) 2995 { 2996 struct sip_softc *sc = (struct sip_softc *) self; 2997 u_int32_t flowctl; 2998 2999 /* 3000 * Update TXCFG for full-duplex operation. 3001 */ 3002 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3003 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3004 else 3005 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3006 3007 /* 3008 * Update RXCFG for full-duplex or loopback. 3009 */ 3010 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3011 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3012 sc->sc_rxcfg |= RXCFG_ATX; 3013 else 3014 sc->sc_rxcfg &= ~RXCFG_ATX; 3015 3016 /* 3017 * Update IMR for use of 802.3x flow control. 3018 */ 3019 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 3020 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3021 flowctl = FLOWCTL_FLOWEN; 3022 } else { 3023 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3024 flowctl = 0; 3025 } 3026 3027 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3028 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3029 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3030 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3031 } 3032 3033 /* 3034 * sip_dp83815_mii_readreg: [mii interface function] 3035 * 3036 * Read a PHY register on the MII. 3037 */ 3038 int 3039 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 3040 { 3041 struct sip_softc *sc = (struct sip_softc *) self; 3042 u_int32_t val; 3043 3044 /* 3045 * The DP83815 only has an internal PHY. Only allow 3046 * MII address 0. 3047 */ 3048 if (phy != 0) 3049 return (0); 3050 3051 /* 3052 * Apparently, after a reset, the DP83815 can take a while 3053 * to respond. During this recovery period, the BMSR returns 3054 * a value of 0. Catch this -- it's not supposed to happen 3055 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3056 * PHY to come back to life. 3057 * 3058 * This works out because the BMSR is the first register 3059 * read during the PHY probe process. 3060 */ 3061 do { 3062 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3063 } while (reg == MII_BMSR && val == 0); 3064 3065 return (val & 0xffff); 3066 } 3067 3068 /* 3069 * sip_dp83815_mii_writereg: [mii interface function] 3070 * 3071 * Write a PHY register to the MII. 3072 */ 3073 void 3074 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3075 { 3076 struct sip_softc *sc = (struct sip_softc *) self; 3077 3078 /* 3079 * The DP83815 only has an internal PHY. Only allow 3080 * MII address 0. 3081 */ 3082 if (phy != 0) 3083 return; 3084 3085 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3086 } 3087 3088 /* 3089 * sip_dp83815_mii_statchg: [mii interface function] 3090 * 3091 * Callback from MII layer when media changes. 3092 */ 3093 void 3094 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3095 { 3096 struct sip_softc *sc = (struct sip_softc *) self; 3097 3098 /* 3099 * Update TXCFG for full-duplex operation. 3100 */ 3101 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3102 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3103 else 3104 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3105 3106 /* 3107 * Update RXCFG for full-duplex or loopback. 3108 */ 3109 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3110 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3111 sc->sc_rxcfg |= RXCFG_ATX; 3112 else 3113 sc->sc_rxcfg &= ~RXCFG_ATX; 3114 3115 /* 3116 * XXX 802.3x flow control. 3117 */ 3118 3119 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3120 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3121 } 3122 #endif /* DP83820 */ 3123 3124 #if defined(DP83820) 3125 void 3126 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3127 const struct pci_attach_args *pa, u_int8_t *enaddr) 3128 { 3129 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3130 u_int8_t cksum, *e, match; 3131 int i; 3132 3133 /* 3134 * EEPROM data format for the DP83820 can be found in 3135 * the DP83820 manual, section 4.2.4. 3136 */ 3137 3138 SIP_DECL(read_eeprom)(sc, 0, 3139 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3140 3141 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3142 match = ~(match - 1); 3143 3144 cksum = 0x55; 3145 e = (u_int8_t *) eeprom_data; 3146 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3147 cksum += *e++; 3148 3149 if (cksum != match) 3150 printf("%s: Checksum (%x) mismatch (%x)", 3151 sc->sc_dev.dv_xname, cksum, match); 3152 3153 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3154 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3155 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3156 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3157 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3158 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3159 3160 /* Get the GPIOR bits. */ 3161 sc->sc_gpior = eeprom_data[0x04]; 3162 } 3163 #else /* ! DP83820 */ 3164 void 3165 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3166 const struct pci_attach_args *pa, u_int8_t *enaddr) 3167 { 3168 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3169 3170 switch (sc->sc_rev) { 3171 case SIS_REV_630S: 3172 case SIS_REV_630E: 3173 case SIS_REV_630EA1: 3174 case SIS_REV_630ET: 3175 case SIS_REV_635: 3176 /* 3177 * The MAC address for the on-board Ethernet of 3178 * the SiS 630 chipset is in the NVRAM. Kick 3179 * the chip into re-loading it from NVRAM, and 3180 * read the MAC address out of the filter registers. 3181 */ 3182 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3183 3184 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3185 RFCR_RFADDR_NODE0); 3186 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3187 0xffff; 3188 3189 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3190 RFCR_RFADDR_NODE2); 3191 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3192 0xffff; 3193 3194 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3195 RFCR_RFADDR_NODE4); 3196 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3197 0xffff; 3198 break; 3199 3200 default: 3201 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3202 sizeof(myea) / sizeof(myea[0]), myea); 3203 } 3204 3205 enaddr[0] = myea[0] & 0xff; 3206 enaddr[1] = myea[0] >> 8; 3207 enaddr[2] = myea[1] & 0xff; 3208 enaddr[3] = myea[1] >> 8; 3209 enaddr[4] = myea[2] & 0xff; 3210 enaddr[5] = myea[2] >> 8; 3211 } 3212 3213 /* Table and macro to bit-reverse an octet. */ 3214 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3215 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3216 3217 void 3218 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3219 const struct pci_attach_args *pa, u_int8_t *enaddr) 3220 { 3221 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3222 u_int8_t cksum, *e, match; 3223 int i; 3224 3225 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3226 sizeof(eeprom_data[0]), eeprom_data); 3227 3228 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3229 match = ~(match - 1); 3230 3231 cksum = 0x55; 3232 e = (u_int8_t *) eeprom_data; 3233 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3234 cksum += *e++; 3235 } 3236 if (cksum != match) { 3237 printf("%s: Checksum (%x) mismatch (%x)", 3238 sc->sc_dev.dv_xname, cksum, match); 3239 } 3240 3241 /* 3242 * Unrolled because it makes slightly more sense this way. 3243 * The DP83815 stores the MAC address in bit 0 of word 6 3244 * through bit 15 of word 8. 3245 */ 3246 ea = &eeprom_data[6]; 3247 enaddr[0] = ((*ea & 0x1) << 7); 3248 ea++; 3249 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3250 enaddr[1] = ((*ea & 0x1FE) >> 1); 3251 enaddr[2] = ((*ea & 0x1) << 7); 3252 ea++; 3253 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3254 enaddr[3] = ((*ea & 0x1FE) >> 1); 3255 enaddr[4] = ((*ea & 0x1) << 7); 3256 ea++; 3257 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3258 enaddr[5] = ((*ea & 0x1FE) >> 1); 3259 3260 /* 3261 * In case that's not weird enough, we also need to reverse 3262 * the bits in each byte. This all actually makes more sense 3263 * if you think about the EEPROM storage as an array of bits 3264 * being shifted into bytes, but that's not how we're looking 3265 * at it here... 3266 */ 3267 for (i = 0; i < 6 ;i++) 3268 enaddr[i] = bbr(enaddr[i]); 3269 } 3270 #endif /* DP83820 */ 3271 3272 /* 3273 * sip_mediastatus: [ifmedia interface function] 3274 * 3275 * Get the current interface media status. 3276 */ 3277 void 3278 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3279 { 3280 struct sip_softc *sc = ifp->if_softc; 3281 3282 mii_pollstat(&sc->sc_mii); 3283 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3284 ifmr->ifm_active = sc->sc_mii.mii_media_active; 3285 } 3286 3287 /* 3288 * sip_mediachange: [ifmedia interface function] 3289 * 3290 * Set hardware to newly-selected media. 3291 */ 3292 int 3293 SIP_DECL(mediachange)(struct ifnet *ifp) 3294 { 3295 struct sip_softc *sc = ifp->if_softc; 3296 3297 if (ifp->if_flags & IFF_UP) 3298 mii_mediachg(&sc->sc_mii); 3299 return (0); 3300 } 3301
Indexes created Tue Sep 30 11:09:46 GMT 2025