if_sip.c revision 1.52.4.8
1 /* $NetBSD: if_sip.c,v 1.52.4.8 2003/06/15 12:42:45 tron Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Support the 10-bit interface on the DP83820 (for fiber). 80 * 81 * - Reduce the Rx interrupt load. 82 */ 83 84 #include <sys/cdefs.h> 85 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.52.4.8 2003/06/15 12:42:45 tron Exp $"); 86 87 #include "bpfilter.h" 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/callout.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/ioctl.h> 97 #include <sys/errno.h> 98 #include <sys/device.h> 99 #include <sys/queue.h> 100 101 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 102 103 #include <net/if.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 #include <net/if_ether.h> 107 108 #if NBPFILTER > 0 109 #include <net/bpf.h> 110 #endif 111 112 #include <machine/bus.h> 113 #include <machine/intr.h> 114 #include <machine/endian.h> 115 116 #include <dev/mii/mii.h> 117 #include <dev/mii/miivar.h> 118 #ifdef DP83820 119 #include <dev/mii/mii_bitbang.h> 120 #endif /* DP83820 */ 121 122 #include <dev/pci/pcireg.h> 123 #include <dev/pci/pcivar.h> 124 #include <dev/pci/pcidevs.h> 125 126 #include <dev/pci/if_sipreg.h> 127 128 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 129 #define SIP_DECL(x) __CONCAT(gsip_,x) 130 #else /* SiS900 and DP83815 */ 131 #define SIP_DECL(x) __CONCAT(sip_,x) 132 #endif 133 134 #define SIP_STR(x) __STRING(SIP_DECL(x)) 135 136 /* 137 * Transmit descriptor list size. This is arbitrary, but allocate 138 * enough descriptors for 128 pending transmissions, and 8 segments 139 * per packet. This MUST work out to a power of 2. 140 */ 141 #define SIP_NTXSEGS 16 142 #define SIP_NTXSEGS_ALLOC 8 143 144 #define SIP_TXQUEUELEN 256 145 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 146 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 147 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 148 149 #if defined(DP83020) 150 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 151 #else 152 #define TX_DMAMAP_SIZE MCLBYTES 153 #endif 154 155 /* 156 * Receive descriptor list size. We have one Rx buffer per incoming 157 * packet, so this logic is a little simpler. 158 * 159 * Actually, on the DP83820, we allow the packet to consume more than 160 * one buffer, in order to support jumbo Ethernet frames. In that 161 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 162 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 163 * so we'd better be quick about handling receive interrupts. 164 */ 165 #if defined(DP83820) 166 #define SIP_NRXDESC 256 167 #else 168 #define SIP_NRXDESC 128 169 #endif /* DP83820 */ 170 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 171 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 172 173 /* 174 * Control structures are DMA'd to the SiS900 chip. We allocate them in 175 * a single clump that maps to a single DMA segment to make several things 176 * easier. 177 */ 178 struct sip_control_data { 179 /* 180 * The transmit descriptors. 181 */ 182 struct sip_desc scd_txdescs[SIP_NTXDESC]; 183 184 /* 185 * The receive descriptors. 186 */ 187 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 188 }; 189 190 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 191 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 192 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 193 194 /* 195 * Software state for transmit jobs. 196 */ 197 struct sip_txsoft { 198 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 199 bus_dmamap_t txs_dmamap; /* our DMA map */ 200 int txs_firstdesc; /* first descriptor in packet */ 201 int txs_lastdesc; /* last descriptor in packet */ 202 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 203 }; 204 205 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 206 207 /* 208 * Software state for receive jobs. 209 */ 210 struct sip_rxsoft { 211 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 212 bus_dmamap_t rxs_dmamap; /* our DMA map */ 213 }; 214 215 /* 216 * Software state per device. 217 */ 218 struct sip_softc { 219 struct device sc_dev; /* generic device information */ 220 bus_space_tag_t sc_st; /* bus space tag */ 221 bus_space_handle_t sc_sh; /* bus space handle */ 222 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 223 struct ethercom sc_ethercom; /* ethernet common data */ 224 void *sc_sdhook; /* shutdown hook */ 225 226 const struct sip_product *sc_model; /* which model are we? */ 227 int sc_rev; /* chip revision */ 228 229 void *sc_ih; /* interrupt cookie */ 230 231 struct mii_data sc_mii; /* MII/media information */ 232 233 struct callout sc_tick_ch; /* tick callout */ 234 235 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 236 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 237 238 /* 239 * Software state for transmit and receive descriptors. 240 */ 241 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 242 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 243 244 /* 245 * Control data structures. 246 */ 247 struct sip_control_data *sc_control_data; 248 #define sc_txdescs sc_control_data->scd_txdescs 249 #define sc_rxdescs sc_control_data->scd_rxdescs 250 251 #ifdef SIP_EVENT_COUNTERS 252 /* 253 * Event counters. 254 */ 255 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 256 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 257 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 258 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 259 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 260 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 261 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 262 #ifdef DP83820 263 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 264 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 265 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 266 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 267 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 268 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 269 #endif /* DP83820 */ 270 #endif /* SIP_EVENT_COUNTERS */ 271 272 u_int32_t sc_txcfg; /* prototype TXCFG register */ 273 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 274 u_int32_t sc_imr; /* prototype IMR register */ 275 u_int32_t sc_rfcr; /* prototype RFCR register */ 276 277 u_int32_t sc_cfg; /* prototype CFG register */ 278 279 #ifdef DP83820 280 u_int32_t sc_gpior; /* prototype GPIOR register */ 281 #endif /* DP83820 */ 282 283 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 284 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 285 286 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 287 288 int sc_flags; /* misc. flags; see below */ 289 290 int sc_txfree; /* number of free Tx descriptors */ 291 int sc_txnext; /* next ready Tx descriptor */ 292 int sc_txwin; /* Tx descriptors since last intr */ 293 294 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 295 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 296 297 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 298 #if defined(DP83820) 299 int sc_rxdiscard; 300 int sc_rxlen; 301 struct mbuf *sc_rxhead; 302 struct mbuf *sc_rxtail; 303 struct mbuf **sc_rxtailp; 304 #endif /* DP83820 */ 305 }; 306 307 /* sc_flags */ 308 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 309 310 #ifdef DP83820 311 #define SIP_RXCHAIN_RESET(sc) \ 312 do { \ 313 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 314 *(sc)->sc_rxtailp = NULL; \ 315 (sc)->sc_rxlen = 0; \ 316 } while (/*CONSTCOND*/0) 317 318 #define SIP_RXCHAIN_LINK(sc, m) \ 319 do { \ 320 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 321 (sc)->sc_rxtailp = &(m)->m_next; \ 322 } while (/*CONSTCOND*/0) 323 #endif /* DP83820 */ 324 325 #ifdef SIP_EVENT_COUNTERS 326 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 327 #else 328 #define SIP_EVCNT_INCR(ev) /* nothing */ 329 #endif 330 331 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 332 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 333 334 #define SIP_CDTXSYNC(sc, x, n, ops) \ 335 do { \ 336 int __x, __n; \ 337 \ 338 __x = (x); \ 339 __n = (n); \ 340 \ 341 /* If it will wrap around, sync to the end of the ring. */ \ 342 if ((__x + __n) > SIP_NTXDESC) { \ 343 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 344 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 345 (SIP_NTXDESC - __x), (ops)); \ 346 __n -= (SIP_NTXDESC - __x); \ 347 __x = 0; \ 348 } \ 349 \ 350 /* Now sync whatever is left. */ \ 351 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 352 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 353 } while (0) 354 355 #define SIP_CDRXSYNC(sc, x, ops) \ 356 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 357 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 358 359 #ifdef DP83820 360 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 361 #define SIP_RXBUF_LEN (MCLBYTES - 4) 362 #else 363 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 364 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 365 #endif 366 #define SIP_INIT_RXDESC(sc, x) \ 367 do { \ 368 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 369 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 370 \ 371 __sipd->sipd_link = \ 372 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 373 __sipd->sipd_bufptr = \ 374 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 375 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 376 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 377 SIP_INIT_RXDESC_EXTSTS \ 378 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 379 } while (0) 380 381 #define SIP_CHIP_VERS(sc, v, p, r) \ 382 ((sc)->sc_model->sip_vendor == (v) && \ 383 (sc)->sc_model->sip_product == (p) && \ 384 (sc)->sc_rev == (r)) 385 386 #define SIP_CHIP_MODEL(sc, v, p) \ 387 ((sc)->sc_model->sip_vendor == (v) && \ 388 (sc)->sc_model->sip_product == (p)) 389 390 #if !defined(DP83820) 391 #define SIP_SIS900_REV(sc, rev) \ 392 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 393 #endif 394 395 #define SIP_TIMEOUT 1000 396 397 void SIP_DECL(start)(struct ifnet *); 398 void SIP_DECL(watchdog)(struct ifnet *); 399 int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 400 int SIP_DECL(init)(struct ifnet *); 401 void SIP_DECL(stop)(struct ifnet *, int); 402 403 void SIP_DECL(shutdown)(void *); 404 405 void SIP_DECL(reset)(struct sip_softc *); 406 void SIP_DECL(rxdrain)(struct sip_softc *); 407 int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 408 void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, u_int16_t *); 409 void SIP_DECL(tick)(void *); 410 411 #if !defined(DP83820) 412 void SIP_DECL(sis900_set_filter)(struct sip_softc *); 413 #endif /* ! DP83820 */ 414 void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 415 416 #if defined(DP83820) 417 void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 418 const struct pci_attach_args *, u_int8_t *); 419 #else 420 void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 421 const struct pci_attach_args *, u_int8_t *); 422 void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 423 const struct pci_attach_args *, u_int8_t *); 424 #endif /* DP83820 */ 425 426 int SIP_DECL(intr)(void *); 427 void SIP_DECL(txintr)(struct sip_softc *); 428 void SIP_DECL(rxintr)(struct sip_softc *); 429 430 #if defined(DP83820) 431 int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 432 void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 433 void SIP_DECL(dp83820_mii_statchg)(struct device *); 434 #else 435 int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 436 void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 437 void SIP_DECL(sis900_mii_statchg)(struct device *); 438 439 int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 440 void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 441 void SIP_DECL(dp83815_mii_statchg)(struct device *); 442 #endif /* DP83820 */ 443 444 int SIP_DECL(mediachange)(struct ifnet *); 445 void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 446 447 int SIP_DECL(match)(struct device *, struct cfdata *, void *); 448 void SIP_DECL(attach)(struct device *, struct device *, void *); 449 450 int SIP_DECL(copy_small) = 0; 451 452 struct cfattach SIP_DECL(ca) = { 453 sizeof(struct sip_softc), SIP_DECL(match), SIP_DECL(attach), 454 }; 455 456 /* 457 * Descriptions of the variants of the SiS900. 458 */ 459 struct sip_variant { 460 int (*sipv_mii_readreg)(struct device *, int, int); 461 void (*sipv_mii_writereg)(struct device *, int, int, int); 462 void (*sipv_mii_statchg)(struct device *); 463 void (*sipv_set_filter)(struct sip_softc *); 464 void (*sipv_read_macaddr)(struct sip_softc *, 465 const struct pci_attach_args *, u_int8_t *); 466 }; 467 468 #if defined(DP83820) 469 u_int32_t SIP_DECL(dp83820_mii_bitbang_read)(struct device *); 470 void SIP_DECL(dp83820_mii_bitbang_write)(struct device *, u_int32_t); 471 472 const struct mii_bitbang_ops SIP_DECL(dp83820_mii_bitbang_ops) = { 473 SIP_DECL(dp83820_mii_bitbang_read), 474 SIP_DECL(dp83820_mii_bitbang_write), 475 { 476 EROMAR_MDIO, /* MII_BIT_MDO */ 477 EROMAR_MDIO, /* MII_BIT_MDI */ 478 EROMAR_MDC, /* MII_BIT_MDC */ 479 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 480 0, /* MII_BIT_DIR_PHY_HOST */ 481 } 482 }; 483 #endif /* DP83820 */ 484 485 #if defined(DP83820) 486 const struct sip_variant SIP_DECL(variant_dp83820) = { 487 SIP_DECL(dp83820_mii_readreg), 488 SIP_DECL(dp83820_mii_writereg), 489 SIP_DECL(dp83820_mii_statchg), 490 SIP_DECL(dp83815_set_filter), 491 SIP_DECL(dp83820_read_macaddr), 492 }; 493 #else 494 const struct sip_variant SIP_DECL(variant_sis900) = { 495 SIP_DECL(sis900_mii_readreg), 496 SIP_DECL(sis900_mii_writereg), 497 SIP_DECL(sis900_mii_statchg), 498 SIP_DECL(sis900_set_filter), 499 SIP_DECL(sis900_read_macaddr), 500 }; 501 502 const struct sip_variant SIP_DECL(variant_dp83815) = { 503 SIP_DECL(dp83815_mii_readreg), 504 SIP_DECL(dp83815_mii_writereg), 505 SIP_DECL(dp83815_mii_statchg), 506 SIP_DECL(dp83815_set_filter), 507 SIP_DECL(dp83815_read_macaddr), 508 }; 509 #endif /* DP83820 */ 510 511 /* 512 * Devices supported by this driver. 513 */ 514 const struct sip_product { 515 pci_vendor_id_t sip_vendor; 516 pci_product_id_t sip_product; 517 const char *sip_name; 518 const struct sip_variant *sip_variant; 519 } SIP_DECL(products)[] = { 520 #if defined(DP83820) 521 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 522 "NatSemi DP83820 Gigabit Ethernet", 523 &SIP_DECL(variant_dp83820) }, 524 #else 525 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 526 "SiS 900 10/100 Ethernet", 527 &SIP_DECL(variant_sis900) }, 528 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 529 "SiS 7016 10/100 Ethernet", 530 &SIP_DECL(variant_sis900) }, 531 532 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 533 "NatSemi DP83815 10/100 Ethernet", 534 &SIP_DECL(variant_dp83815) }, 535 #endif /* DP83820 */ 536 537 { 0, 0, 538 NULL, 539 NULL }, 540 }; 541 542 static const struct sip_product * 543 SIP_DECL(lookup)(const struct pci_attach_args *pa) 544 { 545 const struct sip_product *sip; 546 547 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 548 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 549 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 550 return (sip); 551 } 552 return (NULL); 553 } 554 555 #ifdef DP83820 556 /* 557 * I really hate stupid hardware vendors. There's a bit in the EEPROM 558 * which indicates if the card can do 64-bit data transfers. Unfortunately, 559 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 560 * which means we try to use 64-bit data transfers on those cards if we 561 * happen to be plugged into a 32-bit slot. 562 * 563 * What we do is use this table of cards known to be 64-bit cards. If 564 * you have a 64-bit card who's subsystem ID is not listed in this table, 565 * send the output of "pcictl dump ..." of the device to me so that your 566 * card will use the 64-bit data path when plugged into a 64-bit slot. 567 * 568 * -- Jason R. Thorpe <thorpej (at) netbsd.org> 569 * June 30, 2002 570 */ 571 static int 572 SIP_DECL(check_64bit)(const struct pci_attach_args *pa) 573 { 574 static const struct { 575 pci_vendor_id_t c64_vendor; 576 pci_product_id_t c64_product; 577 } card64[] = { 578 /* Asante GigaNIX */ 579 { 0x128a, 0x0002 }, 580 581 { 0, 0} 582 }; 583 pcireg_t subsys; 584 int i; 585 586 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 587 588 for (i = 0; card64[i].c64_vendor != 0; i++) { 589 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 590 PCI_PRODUCT(subsys) == card64[i].c64_product) 591 return (1); 592 } 593 594 return (0); 595 } 596 #endif /* DP83820 */ 597 598 int 599 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 600 { 601 struct pci_attach_args *pa = aux; 602 603 if (SIP_DECL(lookup)(pa) != NULL) 604 return (1); 605 606 return (0); 607 } 608 609 void 610 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 611 { 612 struct sip_softc *sc = (struct sip_softc *) self; 613 struct pci_attach_args *pa = aux; 614 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 615 pci_chipset_tag_t pc = pa->pa_pc; 616 pci_intr_handle_t ih; 617 const char *intrstr = NULL; 618 bus_space_tag_t iot, memt; 619 bus_space_handle_t ioh, memh; 620 bus_dma_segment_t seg; 621 int ioh_valid, memh_valid; 622 int i, rseg, error; 623 const struct sip_product *sip; 624 pcireg_t pmode; 625 u_int8_t enaddr[ETHER_ADDR_LEN]; 626 int pmreg; 627 #ifdef DP83820 628 pcireg_t memtype; 629 u_int32_t reg; 630 #endif /* DP83820 */ 631 632 callout_init(&sc->sc_tick_ch); 633 634 sip = SIP_DECL(lookup)(pa); 635 if (sip == NULL) { 636 printf("\n"); 637 panic(SIP_STR(attach) ": impossible"); 638 } 639 sc->sc_rev = PCI_REVISION(pa->pa_class); 640 641 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 642 643 sc->sc_model = sip; 644 645 /* 646 * XXX Work-around broken PXE firmware on some boards. 647 * 648 * The DP83815 shares an address decoder with the MEM BAR 649 * and the ROM BAR. Make sure the ROM BAR is disabled, 650 * so that memory mapped access works. 651 */ 652 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 653 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 654 ~PCI_MAPREG_ROM_ENABLE); 655 656 /* 657 * Map the device. 658 */ 659 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 660 PCI_MAPREG_TYPE_IO, 0, 661 &iot, &ioh, NULL, NULL) == 0); 662 #ifdef DP83820 663 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 664 switch (memtype) { 665 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 666 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 667 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 668 memtype, 0, &memt, &memh, NULL, NULL) == 0); 669 break; 670 default: 671 memh_valid = 0; 672 } 673 #else 674 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 675 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 676 &memt, &memh, NULL, NULL) == 0); 677 #endif /* DP83820 */ 678 679 if (memh_valid) { 680 sc->sc_st = memt; 681 sc->sc_sh = memh; 682 } else if (ioh_valid) { 683 sc->sc_st = iot; 684 sc->sc_sh = ioh; 685 } else { 686 printf("%s: unable to map device registers\n", 687 sc->sc_dev.dv_xname); 688 return; 689 } 690 691 sc->sc_dmat = pa->pa_dmat; 692 693 /* 694 * Make sure bus mastering is enabled. Also make sure 695 * Write/Invalidate is enabled if we're allowed to use it. 696 */ 697 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 698 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 699 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 700 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 701 pmreg | PCI_COMMAND_MASTER_ENABLE); 702 703 /* Get it out of power save mode if needed. */ 704 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 705 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 706 if (pmode == 3) { 707 /* 708 * The card has lost all configuration data in 709 * this state, so punt. 710 */ 711 printf("%s: unable to wake up from power state D3\n", 712 sc->sc_dev.dv_xname); 713 return; 714 } 715 if (pmode != 0) { 716 printf("%s: waking up from power state D%d\n", 717 sc->sc_dev.dv_xname, pmode); 718 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 719 } 720 } 721 722 /* 723 * Map and establish our interrupt. 724 */ 725 if (pci_intr_map(pa, &ih)) { 726 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 727 return; 728 } 729 intrstr = pci_intr_string(pc, ih); 730 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 731 if (sc->sc_ih == NULL) { 732 printf("%s: unable to establish interrupt", 733 sc->sc_dev.dv_xname); 734 if (intrstr != NULL) 735 printf(" at %s", intrstr); 736 printf("\n"); 737 return; 738 } 739 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 740 741 SIMPLEQ_INIT(&sc->sc_txfreeq); 742 SIMPLEQ_INIT(&sc->sc_txdirtyq); 743 744 /* 745 * Allocate the control data structures, and create and load the 746 * DMA map for it. 747 */ 748 if ((error = bus_dmamem_alloc(sc->sc_dmat, 749 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 750 0)) != 0) { 751 printf("%s: unable to allocate control data, error = %d\n", 752 sc->sc_dev.dv_xname, error); 753 goto fail_0; 754 } 755 756 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 757 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 758 BUS_DMA_COHERENT)) != 0) { 759 printf("%s: unable to map control data, error = %d\n", 760 sc->sc_dev.dv_xname, error); 761 goto fail_1; 762 } 763 764 if ((error = bus_dmamap_create(sc->sc_dmat, 765 sizeof(struct sip_control_data), 1, 766 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 767 printf("%s: unable to create control data DMA map, " 768 "error = %d\n", sc->sc_dev.dv_xname, error); 769 goto fail_2; 770 } 771 772 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 773 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 774 0)) != 0) { 775 printf("%s: unable to load control data DMA map, error = %d\n", 776 sc->sc_dev.dv_xname, error); 777 goto fail_3; 778 } 779 780 /* 781 * Create the transmit buffer DMA maps. 782 */ 783 for (i = 0; i < SIP_TXQUEUELEN; i++) { 784 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 785 SIP_NTXSEGS, MCLBYTES, 0, 0, 786 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 787 printf("%s: unable to create tx DMA map %d, " 788 "error = %d\n", sc->sc_dev.dv_xname, i, error); 789 goto fail_4; 790 } 791 } 792 793 /* 794 * Create the receive buffer DMA maps. 795 */ 796 for (i = 0; i < SIP_NRXDESC; i++) { 797 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 798 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 799 printf("%s: unable to create rx DMA map %d, " 800 "error = %d\n", sc->sc_dev.dv_xname, i, error); 801 goto fail_5; 802 } 803 sc->sc_rxsoft[i].rxs_mbuf = NULL; 804 } 805 806 /* 807 * Reset the chip to a known state. 808 */ 809 SIP_DECL(reset)(sc); 810 811 /* 812 * Read the Ethernet address from the EEPROM. This might 813 * also fetch other stuff from the EEPROM and stash it 814 * in the softc. 815 */ 816 sc->sc_cfg = 0; 817 #if !defined(DP83820) 818 if (SIP_SIS900_REV(sc,SIS_REV_635) || 819 SIP_SIS900_REV(sc,SIS_REV_900B)) 820 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 821 #endif 822 823 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 824 825 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 826 ether_sprintf(enaddr)); 827 828 /* 829 * Initialize the configuration register: aggressive PCI 830 * bus request algorithm, default backoff, default OW timer, 831 * default parity error detection. 832 * 833 * NOTE: "Big endian mode" is useless on the SiS900 and 834 * friends -- it affects packet data, not descriptors. 835 */ 836 #ifdef DP83820 837 /* 838 * Cause the chip to load configuration data from the EEPROM. 839 */ 840 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 841 for (i = 0; i < 10000; i++) { 842 delay(10); 843 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 844 PTSCR_EELOAD_EN) == 0) 845 break; 846 } 847 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 848 PTSCR_EELOAD_EN) { 849 printf("%s: timeout loading configuration from EEPROM\n", 850 sc->sc_dev.dv_xname); 851 return; 852 } 853 854 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 855 if (reg & CFG_PCI64_DET) { 856 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 857 /* 858 * Check to see if this card is 64-bit. If so, enable 64-bit 859 * data transfers. 860 * 861 * We can't use the DATA64_EN bit in the EEPROM, because 862 * vendors of 32-bit cards fail to clear that bit in many 863 * cases (yet the card still detects that it's in a 64-bit 864 * slot; go figure). 865 */ 866 if (SIP_DECL(check_64bit)(pa)) { 867 sc->sc_cfg |= CFG_DATA64_EN; 868 printf(", using 64-bit data transfers"); 869 } 870 printf("\n"); 871 } 872 873 /* 874 * XXX Need some PCI flags indicating support for 875 * XXX 64-bit addressing. 876 */ 877 #if 0 878 if (reg & CFG_M64ADDR) 879 sc->sc_cfg |= CFG_M64ADDR; 880 if (reg & CFG_T64ADDR) 881 sc->sc_cfg |= CFG_T64ADDR; 882 #endif 883 884 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 885 const char *sep = ""; 886 printf("%s: using ", sc->sc_dev.dv_xname); 887 if (reg & CFG_EXT_125) { 888 sc->sc_cfg |= CFG_EXT_125; 889 printf("%s125MHz clock", sep); 890 sep = ", "; 891 } 892 if (reg & CFG_TBI_EN) { 893 sc->sc_cfg |= CFG_TBI_EN; 894 printf("%sten-bit interface", sep); 895 sep = ", "; 896 } 897 printf("\n"); 898 } 899 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 900 (reg & CFG_MRM_DIS) != 0) 901 sc->sc_cfg |= CFG_MRM_DIS; 902 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 903 (reg & CFG_MWI_DIS) != 0) 904 sc->sc_cfg |= CFG_MWI_DIS; 905 906 /* 907 * Use the extended descriptor format on the DP83820. This 908 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 909 * checksumming. 910 */ 911 sc->sc_cfg |= CFG_EXTSTS_EN; 912 #endif /* DP83820 */ 913 914 /* 915 * Initialize our media structures and probe the MII. 916 */ 917 sc->sc_mii.mii_ifp = ifp; 918 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 919 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 920 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 921 ifmedia_init(&sc->sc_mii.mii_media, 0, SIP_DECL(mediachange), 922 SIP_DECL(mediastatus)); 923 #ifdef DP83820 924 if (sc->sc_cfg & CFG_TBI_EN) { 925 /* Using ten-bit interface. */ 926 printf("%s: TBI -- FIXME\n", sc->sc_dev.dv_xname); 927 } else { 928 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 929 MII_OFFSET_ANY, 0); 930 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 931 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 932 0, NULL); 933 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 934 } else 935 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 936 } 937 #else 938 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 939 MII_OFFSET_ANY, 0); 940 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 941 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 942 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 943 } else 944 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 945 #endif /* DP83820 */ 946 947 ifp = &sc->sc_ethercom.ec_if; 948 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 949 ifp->if_softc = sc; 950 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 951 ifp->if_ioctl = SIP_DECL(ioctl); 952 ifp->if_start = SIP_DECL(start); 953 ifp->if_watchdog = SIP_DECL(watchdog); 954 ifp->if_init = SIP_DECL(init); 955 ifp->if_stop = SIP_DECL(stop); 956 IFQ_SET_READY(&ifp->if_snd); 957 958 /* 959 * We can support 802.1Q VLAN-sized frames. 960 */ 961 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 962 963 #ifdef DP83820 964 /* 965 * And the DP83820 can do VLAN tagging in hardware, and 966 * support the jumbo Ethernet MTU. 967 */ 968 sc->sc_ethercom.ec_capabilities |= 969 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 970 971 /* 972 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 973 * in hardware. 974 */ 975 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 976 IFCAP_CSUM_UDPv4; 977 #endif /* DP83820 */ 978 979 /* 980 * Attach the interface. 981 */ 982 if_attach(ifp); 983 ether_ifattach(ifp, enaddr); 984 985 /* 986 * The number of bytes that must be available in 987 * the Tx FIFO before the bus master can DMA more 988 * data into the FIFO. 989 */ 990 sc->sc_tx_fill_thresh = 64 / 32; 991 992 /* 993 * Start at a drain threshold of 512 bytes. We will 994 * increase it if a DMA underrun occurs. 995 * 996 * XXX The minimum value of this variable should be 997 * tuned. We may be able to improve performance 998 * by starting with a lower value. That, however, 999 * may trash the first few outgoing packets if the 1000 * PCI bus is saturated. 1001 */ 1002 sc->sc_tx_drain_thresh = 1504 / 32; 1003 1004 /* 1005 * Initialize the Rx FIFO drain threshold. 1006 * 1007 * This is in units of 8 bytes. 1008 * 1009 * We should never set this value lower than 2; 14 bytes are 1010 * required to filter the packet. 1011 */ 1012 sc->sc_rx_drain_thresh = 128 / 8; 1013 1014 #ifdef SIP_EVENT_COUNTERS 1015 /* 1016 * Attach event counters. 1017 */ 1018 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1019 NULL, sc->sc_dev.dv_xname, "txsstall"); 1020 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1021 NULL, sc->sc_dev.dv_xname, "txdstall"); 1022 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1023 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1024 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1025 NULL, sc->sc_dev.dv_xname, "txdintr"); 1026 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1027 NULL, sc->sc_dev.dv_xname, "txiintr"); 1028 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1029 NULL, sc->sc_dev.dv_xname, "rxintr"); 1030 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1031 NULL, sc->sc_dev.dv_xname, "hiberr"); 1032 #ifdef DP83820 1033 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1034 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1035 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1036 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1037 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1038 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1039 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1040 NULL, sc->sc_dev.dv_xname, "txipsum"); 1041 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1042 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1043 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1044 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1045 #endif /* DP83820 */ 1046 #endif /* SIP_EVENT_COUNTERS */ 1047 1048 /* 1049 * Make sure the interface is shutdown during reboot. 1050 */ 1051 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 1052 if (sc->sc_sdhook == NULL) 1053 printf("%s: WARNING: unable to establish shutdown hook\n", 1054 sc->sc_dev.dv_xname); 1055 return; 1056 1057 /* 1058 * Free any resources we've allocated during the failed attach 1059 * attempt. Do this in reverse order and fall through. 1060 */ 1061 fail_5: 1062 for (i = 0; i < SIP_NRXDESC; i++) { 1063 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1064 bus_dmamap_destroy(sc->sc_dmat, 1065 sc->sc_rxsoft[i].rxs_dmamap); 1066 } 1067 fail_4: 1068 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1069 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1070 bus_dmamap_destroy(sc->sc_dmat, 1071 sc->sc_txsoft[i].txs_dmamap); 1072 } 1073 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1074 fail_3: 1075 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1076 fail_2: 1077 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1078 sizeof(struct sip_control_data)); 1079 fail_1: 1080 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1081 fail_0: 1082 return; 1083 } 1084 1085 /* 1086 * sip_shutdown: 1087 * 1088 * Make sure the interface is stopped at reboot time. 1089 */ 1090 void 1091 SIP_DECL(shutdown)(void *arg) 1092 { 1093 struct sip_softc *sc = arg; 1094 1095 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1096 } 1097 1098 /* 1099 * sip_start: [ifnet interface function] 1100 * 1101 * Start packet transmission on the interface. 1102 */ 1103 void 1104 SIP_DECL(start)(struct ifnet *ifp) 1105 { 1106 struct sip_softc *sc = ifp->if_softc; 1107 struct mbuf *m0, *m; 1108 struct sip_txsoft *txs; 1109 bus_dmamap_t dmamap; 1110 int error, firsttx, nexttx, lasttx, ofree, seg; 1111 #ifdef DP83820 1112 u_int32_t extsts; 1113 #endif 1114 1115 /* 1116 * If we've been told to pause, don't transmit any more packets. 1117 */ 1118 if (sc->sc_flags & SIPF_PAUSED) 1119 ifp->if_flags |= IFF_OACTIVE; 1120 1121 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1122 return; 1123 1124 /* 1125 * Remember the previous number of free descriptors and 1126 * the first descriptor we'll use. 1127 */ 1128 ofree = sc->sc_txfree; 1129 firsttx = sc->sc_txnext; 1130 1131 /* 1132 * Loop through the send queue, setting up transmit descriptors 1133 * until we drain the queue, or use up all available transmit 1134 * descriptors. 1135 */ 1136 for (;;) { 1137 /* Get a work queue entry. */ 1138 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1139 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1140 break; 1141 } 1142 1143 /* 1144 * Grab a packet off the queue. 1145 */ 1146 IFQ_POLL(&ifp->if_snd, m0); 1147 if (m0 == NULL) 1148 break; 1149 #ifndef DP83820 1150 m = NULL; 1151 #endif 1152 1153 dmamap = txs->txs_dmamap; 1154 1155 #ifdef DP83820 1156 /* 1157 * Load the DMA map. If this fails, the packet either 1158 * didn't fit in the allotted number of segments, or we 1159 * were short on resources. For the too-many-segments 1160 * case, we simply report an error and drop the packet, 1161 * since we can't sanely copy a jumbo packet to a single 1162 * buffer. 1163 */ 1164 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1165 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1166 if (error) { 1167 if (error == EFBIG) { 1168 printf("%s: Tx packet consumes too many " 1169 "DMA segments, dropping...\n", 1170 sc->sc_dev.dv_xname); 1171 IFQ_DEQUEUE(&ifp->if_snd, m0); 1172 m_freem(m0); 1173 continue; 1174 } 1175 /* 1176 * Short on resources, just stop for now. 1177 */ 1178 break; 1179 } 1180 #else /* DP83820 */ 1181 /* 1182 * Load the DMA map. If this fails, the packet either 1183 * didn't fit in the alloted number of segments, or we 1184 * were short on resources. In this case, we'll copy 1185 * and try again. 1186 */ 1187 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1188 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1189 MGETHDR(m, M_DONTWAIT, MT_DATA); 1190 if (m == NULL) { 1191 printf("%s: unable to allocate Tx mbuf\n", 1192 sc->sc_dev.dv_xname); 1193 break; 1194 } 1195 if (m0->m_pkthdr.len > MHLEN) { 1196 MCLGET(m, M_DONTWAIT); 1197 if ((m->m_flags & M_EXT) == 0) { 1198 printf("%s: unable to allocate Tx " 1199 "cluster\n", sc->sc_dev.dv_xname); 1200 m_freem(m); 1201 break; 1202 } 1203 } 1204 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1205 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1206 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1207 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1208 if (error) { 1209 printf("%s: unable to load Tx buffer, " 1210 "error = %d\n", sc->sc_dev.dv_xname, error); 1211 break; 1212 } 1213 } 1214 #endif /* DP83820 */ 1215 1216 /* 1217 * Ensure we have enough descriptors free to describe 1218 * the packet. Note, we always reserve one descriptor 1219 * at the end of the ring as a termination point, to 1220 * prevent wrap-around. 1221 */ 1222 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1223 /* 1224 * Not enough free descriptors to transmit this 1225 * packet. We haven't committed anything yet, 1226 * so just unload the DMA map, put the packet 1227 * back on the queue, and punt. Notify the upper 1228 * layer that there are not more slots left. 1229 * 1230 * XXX We could allocate an mbuf and copy, but 1231 * XXX is it worth it? 1232 */ 1233 ifp->if_flags |= IFF_OACTIVE; 1234 bus_dmamap_unload(sc->sc_dmat, dmamap); 1235 #ifndef DP83820 1236 if (m != NULL) 1237 m_freem(m); 1238 #endif 1239 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1240 break; 1241 } 1242 1243 IFQ_DEQUEUE(&ifp->if_snd, m0); 1244 #ifndef DP83820 1245 if (m != NULL) { 1246 m_freem(m0); 1247 m0 = m; 1248 } 1249 #endif 1250 1251 /* 1252 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1253 */ 1254 1255 /* Sync the DMA map. */ 1256 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1257 BUS_DMASYNC_PREWRITE); 1258 1259 /* 1260 * Initialize the transmit descriptors. 1261 */ 1262 for (nexttx = sc->sc_txnext, seg = 0; 1263 seg < dmamap->dm_nsegs; 1264 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1265 /* 1266 * If this is the first descriptor we're 1267 * enqueueing, don't set the OWN bit just 1268 * yet. That could cause a race condition. 1269 * We'll do it below. 1270 */ 1271 sc->sc_txdescs[nexttx].sipd_bufptr = 1272 htole32(dmamap->dm_segs[seg].ds_addr); 1273 sc->sc_txdescs[nexttx].sipd_cmdsts = 1274 htole32((nexttx == firsttx ? 0 : CMDSTS_OWN) | 1275 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1276 #ifdef DP83820 1277 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1278 #endif /* DP83820 */ 1279 lasttx = nexttx; 1280 } 1281 1282 /* Clear the MORE bit on the last segment. */ 1283 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1284 1285 /* 1286 * If we're in the interrupt delay window, delay the 1287 * interrupt. 1288 */ 1289 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1290 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1291 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1292 htole32(CMDSTS_INTR); 1293 sc->sc_txwin = 0; 1294 } 1295 1296 #ifdef DP83820 1297 /* 1298 * If VLANs are enabled and the packet has a VLAN tag, set 1299 * up the descriptor to encapsulate the packet for us. 1300 * 1301 * This apparently has to be on the last descriptor of 1302 * the packet. 1303 */ 1304 if (sc->sc_ethercom.ec_nvlans != 0 && 1305 (m = m_aux_find(m0, AF_LINK, ETHERTYPE_VLAN)) != NULL) { 1306 sc->sc_txdescs[lasttx].sipd_extsts |= 1307 htole32(EXTSTS_VPKT | 1308 htons(*mtod(m, int *) & EXTSTS_VTCI)); 1309 } 1310 1311 /* 1312 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1313 * checksumming, set up the descriptor to do this work 1314 * for us. 1315 * 1316 * This apparently has to be on the first descriptor of 1317 * the packet. 1318 * 1319 * Byte-swap constants so the compiler can optimize. 1320 */ 1321 extsts = 0; 1322 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1323 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1324 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1325 extsts |= htole32(EXTSTS_IPPKT); 1326 } 1327 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1328 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1329 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1330 extsts |= htole32(EXTSTS_TCPPKT); 1331 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1332 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1333 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1334 extsts |= htole32(EXTSTS_UDPPKT); 1335 } 1336 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1337 #endif /* DP83820 */ 1338 1339 /* Sync the descriptors we're using. */ 1340 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1341 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1342 1343 /* 1344 * Store a pointer to the packet so we can free it later, 1345 * and remember what txdirty will be once the packet is 1346 * done. 1347 */ 1348 txs->txs_mbuf = m0; 1349 txs->txs_firstdesc = sc->sc_txnext; 1350 txs->txs_lastdesc = lasttx; 1351 1352 /* Advance the tx pointer. */ 1353 sc->sc_txfree -= dmamap->dm_nsegs; 1354 sc->sc_txnext = nexttx; 1355 1356 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs, txs_q); 1357 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1358 1359 #if NBPFILTER > 0 1360 /* 1361 * Pass the packet to any BPF listeners. 1362 */ 1363 if (ifp->if_bpf) 1364 bpf_mtap(ifp->if_bpf, m0); 1365 #endif /* NBPFILTER > 0 */ 1366 } 1367 1368 if (txs == NULL || sc->sc_txfree == 0) { 1369 /* No more slots left; notify upper layer. */ 1370 ifp->if_flags |= IFF_OACTIVE; 1371 } 1372 1373 if (sc->sc_txfree != ofree) { 1374 /* 1375 * The entire packet chain is set up. Give the 1376 * first descrptor to the chip now. 1377 */ 1378 sc->sc_txdescs[firsttx].sipd_cmdsts |= htole32(CMDSTS_OWN); 1379 SIP_CDTXSYNC(sc, firsttx, 1, 1380 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1381 1382 /* 1383 * Start the transmit process. Note, the manual says 1384 * that if there are no pending transmissions in the 1385 * chip's internal queue (indicated by TXE being clear), 1386 * then the driver software must set the TXDP to the 1387 * first descriptor to be transmitted. However, if we 1388 * do this, it causes serious performance degredation on 1389 * the DP83820 under load, not setting TXDP doesn't seem 1390 * to adversely affect the SiS 900 or DP83815. 1391 * 1392 * Well, I guess it wouldn't be the first time a manual 1393 * has lied -- and they could be speaking of the NULL- 1394 * terminated descriptor list case, rather than OWN- 1395 * terminated rings. 1396 */ 1397 #if 0 1398 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1399 CR_TXE) == 0) { 1400 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1401 SIP_CDTXADDR(sc, firsttx)); 1402 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1403 } 1404 #else 1405 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1406 #endif 1407 1408 /* Set a watchdog timer in case the chip flakes out. */ 1409 ifp->if_timer = 5; 1410 } 1411 } 1412 1413 /* 1414 * sip_watchdog: [ifnet interface function] 1415 * 1416 * Watchdog timer handler. 1417 */ 1418 void 1419 SIP_DECL(watchdog)(struct ifnet *ifp) 1420 { 1421 struct sip_softc *sc = ifp->if_softc; 1422 1423 /* 1424 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1425 * If we get a timeout, try and sweep up transmit descriptors. 1426 * If we manage to sweep them all up, ignore the lack of 1427 * interrupt. 1428 */ 1429 SIP_DECL(txintr)(sc); 1430 1431 if (sc->sc_txfree != SIP_NTXDESC) { 1432 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1433 ifp->if_oerrors++; 1434 1435 /* Reset the interface. */ 1436 (void) SIP_DECL(init)(ifp); 1437 } else if (ifp->if_flags & IFF_DEBUG) 1438 printf("%s: recovered from device timeout\n", 1439 sc->sc_dev.dv_xname); 1440 1441 /* Try to get more packets going. */ 1442 SIP_DECL(start)(ifp); 1443 } 1444 1445 /* 1446 * sip_ioctl: [ifnet interface function] 1447 * 1448 * Handle control requests from the operator. 1449 */ 1450 int 1451 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1452 { 1453 struct sip_softc *sc = ifp->if_softc; 1454 struct ifreq *ifr = (struct ifreq *)data; 1455 int s, error; 1456 1457 s = splnet(); 1458 1459 switch (cmd) { 1460 case SIOCSIFMEDIA: 1461 case SIOCGIFMEDIA: 1462 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1463 break; 1464 1465 default: 1466 error = ether_ioctl(ifp, cmd, data); 1467 if (error == ENETRESET) { 1468 /* 1469 * Multicast list has changed; set the hardware filter 1470 * accordingly. 1471 */ 1472 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1473 error = 0; 1474 } 1475 break; 1476 } 1477 1478 /* Try to get more packets going. */ 1479 SIP_DECL(start)(ifp); 1480 1481 splx(s); 1482 return (error); 1483 } 1484 1485 /* 1486 * sip_intr: 1487 * 1488 * Interrupt service routine. 1489 */ 1490 int 1491 SIP_DECL(intr)(void *arg) 1492 { 1493 struct sip_softc *sc = arg; 1494 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1495 u_int32_t isr; 1496 int handled = 0; 1497 1498 for (;;) { 1499 /* Reading clears interrupt. */ 1500 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1501 if ((isr & sc->sc_imr) == 0) 1502 break; 1503 1504 handled = 1; 1505 1506 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1507 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1508 1509 /* Grab any new packets. */ 1510 SIP_DECL(rxintr)(sc); 1511 1512 if (isr & ISR_RXORN) { 1513 printf("%s: receive FIFO overrun\n", 1514 sc->sc_dev.dv_xname); 1515 1516 /* XXX adjust rx_drain_thresh? */ 1517 } 1518 1519 if (isr & ISR_RXIDLE) { 1520 printf("%s: receive ring overrun\n", 1521 sc->sc_dev.dv_xname); 1522 1523 /* Get the receive process going again. */ 1524 bus_space_write_4(sc->sc_st, sc->sc_sh, 1525 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1526 bus_space_write_4(sc->sc_st, sc->sc_sh, 1527 SIP_CR, CR_RXE); 1528 } 1529 } 1530 1531 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1532 #ifdef SIP_EVENT_COUNTERS 1533 if (isr & ISR_TXDESC) 1534 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1535 else if (isr & ISR_TXIDLE) 1536 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1537 #endif 1538 1539 /* Sweep up transmit descriptors. */ 1540 SIP_DECL(txintr)(sc); 1541 1542 if (isr & ISR_TXURN) { 1543 u_int32_t thresh; 1544 1545 printf("%s: transmit FIFO underrun", 1546 sc->sc_dev.dv_xname); 1547 1548 thresh = sc->sc_tx_drain_thresh + 1; 1549 if (thresh <= TXCFG_DRTH && 1550 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1551 (sc->sc_tx_fill_thresh * 32))) { 1552 printf("; increasing Tx drain " 1553 "threshold to %u bytes\n", 1554 thresh * 32); 1555 sc->sc_tx_drain_thresh = thresh; 1556 (void) SIP_DECL(init)(ifp); 1557 } else { 1558 (void) SIP_DECL(init)(ifp); 1559 printf("\n"); 1560 } 1561 } 1562 } 1563 1564 #if !defined(DP83820) 1565 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1566 if (isr & ISR_PAUSE_ST) { 1567 sc->sc_flags |= SIPF_PAUSED; 1568 ifp->if_flags |= IFF_OACTIVE; 1569 } 1570 if (isr & ISR_PAUSE_END) { 1571 sc->sc_flags &= ~SIPF_PAUSED; 1572 ifp->if_flags &= ~IFF_OACTIVE; 1573 } 1574 } 1575 #endif /* ! DP83820 */ 1576 1577 if (isr & ISR_HIBERR) { 1578 int want_init = 0; 1579 1580 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1581 1582 #define PRINTERR(bit, str) \ 1583 do { \ 1584 if (isr & (bit)) { \ 1585 printf("%s: %s\n", \ 1586 sc->sc_dev.dv_xname, str); \ 1587 want_init = 1; \ 1588 } \ 1589 } while (/*CONSTCOND*/0) 1590 1591 PRINTERR(ISR_DPERR, "parity error"); 1592 PRINTERR(ISR_SSERR, "system error"); 1593 PRINTERR(ISR_RMABT, "master abort"); 1594 PRINTERR(ISR_RTABT, "target abort"); 1595 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1596 /* 1597 * Ignore: 1598 * Tx reset complete 1599 * Rx reset complete 1600 */ 1601 if (want_init) 1602 (void) SIP_DECL(init)(ifp); 1603 #undef PRINTERR 1604 } 1605 } 1606 1607 /* Try to get more packets going. */ 1608 SIP_DECL(start)(ifp); 1609 1610 return (handled); 1611 } 1612 1613 /* 1614 * sip_txintr: 1615 * 1616 * Helper; handle transmit interrupts. 1617 */ 1618 void 1619 SIP_DECL(txintr)(struct sip_softc *sc) 1620 { 1621 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1622 struct sip_txsoft *txs; 1623 u_int32_t cmdsts; 1624 1625 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1626 ifp->if_flags &= ~IFF_OACTIVE; 1627 1628 /* 1629 * Go through our Tx list and free mbufs for those 1630 * frames which have been transmitted. 1631 */ 1632 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1633 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1634 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1635 1636 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1637 if (cmdsts & CMDSTS_OWN) 1638 break; 1639 1640 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1641 1642 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1643 1644 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1645 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1646 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1647 m_freem(txs->txs_mbuf); 1648 txs->txs_mbuf = NULL; 1649 1650 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1651 1652 /* 1653 * Check for errors and collisions. 1654 */ 1655 if (cmdsts & 1656 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1657 ifp->if_oerrors++; 1658 if (cmdsts & CMDSTS_Tx_EC) 1659 ifp->if_collisions += 16; 1660 if (ifp->if_flags & IFF_DEBUG) { 1661 if (cmdsts & CMDSTS_Tx_ED) 1662 printf("%s: excessive deferral\n", 1663 sc->sc_dev.dv_xname); 1664 if (cmdsts & CMDSTS_Tx_EC) 1665 printf("%s: excessive collisions\n", 1666 sc->sc_dev.dv_xname); 1667 } 1668 } else { 1669 /* Packet was transmitted successfully. */ 1670 ifp->if_opackets++; 1671 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1672 } 1673 } 1674 1675 /* 1676 * If there are no more pending transmissions, cancel the watchdog 1677 * timer. 1678 */ 1679 if (txs == NULL) { 1680 ifp->if_timer = 0; 1681 sc->sc_txwin = 0; 1682 } 1683 } 1684 1685 #if defined(DP83820) 1686 /* 1687 * sip_rxintr: 1688 * 1689 * Helper; handle receive interrupts. 1690 */ 1691 void 1692 SIP_DECL(rxintr)(struct sip_softc *sc) 1693 { 1694 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1695 struct sip_rxsoft *rxs; 1696 struct mbuf *m, *tailm; 1697 u_int32_t cmdsts, extsts; 1698 int i, len; 1699 1700 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1701 rxs = &sc->sc_rxsoft[i]; 1702 1703 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1704 1705 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1706 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1707 1708 /* 1709 * NOTE: OWN is set if owned by _consumer_. We're the 1710 * consumer of the receive ring, so if the bit is clear, 1711 * we have processed all of the packets. 1712 */ 1713 if ((cmdsts & CMDSTS_OWN) == 0) { 1714 /* 1715 * We have processed all of the receive buffers. 1716 */ 1717 break; 1718 } 1719 1720 if (__predict_false(sc->sc_rxdiscard)) { 1721 SIP_INIT_RXDESC(sc, i); 1722 if ((cmdsts & CMDSTS_MORE) == 0) { 1723 /* Reset our state. */ 1724 sc->sc_rxdiscard = 0; 1725 } 1726 continue; 1727 } 1728 1729 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1730 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1731 1732 m = rxs->rxs_mbuf; 1733 1734 /* 1735 * Add a new receive buffer to the ring. 1736 */ 1737 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1738 /* 1739 * Failed, throw away what we've done so 1740 * far, and discard the rest of the packet. 1741 */ 1742 ifp->if_ierrors++; 1743 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1744 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1745 SIP_INIT_RXDESC(sc, i); 1746 if (cmdsts & CMDSTS_MORE) 1747 sc->sc_rxdiscard = 1; 1748 if (sc->sc_rxhead != NULL) 1749 m_freem(sc->sc_rxhead); 1750 SIP_RXCHAIN_RESET(sc); 1751 continue; 1752 } 1753 1754 SIP_RXCHAIN_LINK(sc, m); 1755 1756 /* 1757 * If this is not the end of the packet, keep 1758 * looking. 1759 */ 1760 if (cmdsts & CMDSTS_MORE) { 1761 sc->sc_rxlen += m->m_len; 1762 continue; 1763 } 1764 1765 /* 1766 * Okay, we have the entire packet now... 1767 */ 1768 *sc->sc_rxtailp = NULL; 1769 m = sc->sc_rxhead; 1770 tailm = sc->sc_rxtail; 1771 1772 SIP_RXCHAIN_RESET(sc); 1773 1774 /* 1775 * If an error occurred, update stats and drop the packet. 1776 */ 1777 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1778 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1779 ifp->if_ierrors++; 1780 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1781 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1782 /* Receive overrun handled elsewhere. */ 1783 printf("%s: receive descriptor error\n", 1784 sc->sc_dev.dv_xname); 1785 } 1786 #define PRINTERR(bit, str) \ 1787 if (cmdsts & (bit)) \ 1788 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1789 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1790 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1791 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1792 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1793 #undef PRINTERR 1794 m_freem(m); 1795 continue; 1796 } 1797 1798 /* 1799 * No errors. 1800 * 1801 * Note, the DP83820 includes the CRC with 1802 * every packet. 1803 */ 1804 len = CMDSTS_SIZE(cmdsts); 1805 tailm->m_len = len - sc->sc_rxlen; 1806 1807 /* 1808 * If the packet is small enough to fit in a 1809 * single header mbuf, allocate one and copy 1810 * the data into it. This greatly reduces 1811 * memory consumption when we receive lots 1812 * of small packets. 1813 */ 1814 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1815 struct mbuf *nm; 1816 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1817 if (nm == NULL) { 1818 ifp->if_ierrors++; 1819 m_freem(m); 1820 continue; 1821 } 1822 nm->m_data += 2; 1823 nm->m_pkthdr.len = nm->m_len = len; 1824 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1825 m_freem(m); 1826 m = nm; 1827 } 1828 #ifndef __NO_STRICT_ALIGNMENT 1829 else { 1830 /* 1831 * The DP83820's receive buffers must be 4-byte 1832 * aligned. But this means that the data after 1833 * the Ethernet header is misaligned. To compensate, 1834 * we have artificially shortened the buffer size 1835 * in the descriptor, and we do an overlapping copy 1836 * of the data two bytes further in (in the first 1837 * buffer of the chain only). 1838 */ 1839 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1840 m->m_len); 1841 m->m_data += 2; 1842 } 1843 #endif /* ! __NO_STRICT_ALIGNMENT */ 1844 1845 /* 1846 * If VLANs are enabled, VLAN packets have been unwrapped 1847 * for us. Associate the tag with the packet. 1848 */ 1849 if (sc->sc_ethercom.ec_nvlans != 0 && 1850 (extsts & EXTSTS_VPKT) != 0) { 1851 struct mbuf *vtag; 1852 1853 vtag = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 1854 if (vtag == NULL) { 1855 ifp->if_ierrors++; 1856 printf("%s: unable to allocate VLAN tag\n", 1857 sc->sc_dev.dv_xname); 1858 m_freem(m); 1859 continue; 1860 } 1861 1862 *mtod(vtag, int *) = ntohs(extsts & EXTSTS_VTCI); 1863 vtag->m_len = sizeof(int); 1864 } 1865 1866 /* 1867 * Set the incoming checksum information for the 1868 * packet. 1869 */ 1870 if ((extsts & EXTSTS_IPPKT) != 0) { 1871 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1872 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1873 if (extsts & EXTSTS_Rx_IPERR) 1874 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1875 if (extsts & EXTSTS_TCPPKT) { 1876 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1877 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1878 if (extsts & EXTSTS_Rx_TCPERR) 1879 m->m_pkthdr.csum_flags |= 1880 M_CSUM_TCP_UDP_BAD; 1881 } else if (extsts & EXTSTS_UDPPKT) { 1882 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1883 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1884 if (extsts & EXTSTS_Rx_UDPERR) 1885 m->m_pkthdr.csum_flags |= 1886 M_CSUM_TCP_UDP_BAD; 1887 } 1888 } 1889 1890 ifp->if_ipackets++; 1891 m->m_flags |= M_HASFCS; 1892 m->m_pkthdr.rcvif = ifp; 1893 m->m_pkthdr.len = len; 1894 1895 #if NBPFILTER > 0 1896 /* 1897 * Pass this up to any BPF listeners, but only 1898 * pass if up the stack if it's for us. 1899 */ 1900 if (ifp->if_bpf) 1901 bpf_mtap(ifp->if_bpf, m); 1902 #endif /* NBPFILTER > 0 */ 1903 1904 /* Pass it on. */ 1905 (*ifp->if_input)(ifp, m); 1906 } 1907 1908 /* Update the receive pointer. */ 1909 sc->sc_rxptr = i; 1910 } 1911 #else /* ! DP83820 */ 1912 /* 1913 * sip_rxintr: 1914 * 1915 * Helper; handle receive interrupts. 1916 */ 1917 void 1918 SIP_DECL(rxintr)(struct sip_softc *sc) 1919 { 1920 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1921 struct sip_rxsoft *rxs; 1922 struct mbuf *m; 1923 u_int32_t cmdsts; 1924 int i, len; 1925 1926 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1927 rxs = &sc->sc_rxsoft[i]; 1928 1929 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1930 1931 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1932 1933 /* 1934 * NOTE: OWN is set if owned by _consumer_. We're the 1935 * consumer of the receive ring, so if the bit is clear, 1936 * we have processed all of the packets. 1937 */ 1938 if ((cmdsts & CMDSTS_OWN) == 0) { 1939 /* 1940 * We have processed all of the receive buffers. 1941 */ 1942 break; 1943 } 1944 1945 /* 1946 * If any collisions were seen on the wire, count one. 1947 */ 1948 if (cmdsts & CMDSTS_Rx_COL) 1949 ifp->if_collisions++; 1950 1951 /* 1952 * If an error occurred, update stats, clear the status 1953 * word, and leave the packet buffer in place. It will 1954 * simply be reused the next time the ring comes around. 1955 */ 1956 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1957 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1958 ifp->if_ierrors++; 1959 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1960 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1961 /* Receive overrun handled elsewhere. */ 1962 printf("%s: receive descriptor error\n", 1963 sc->sc_dev.dv_xname); 1964 } 1965 #define PRINTERR(bit, str) \ 1966 if (cmdsts & (bit)) \ 1967 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1968 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1969 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1970 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1971 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1972 #undef PRINTERR 1973 SIP_INIT_RXDESC(sc, i); 1974 continue; 1975 } 1976 1977 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1978 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1979 1980 /* 1981 * No errors; receive the packet. Note, the SiS 900 1982 * includes the CRC with every packet. 1983 */ 1984 len = CMDSTS_SIZE(cmdsts); 1985 1986 #ifdef __NO_STRICT_ALIGNMENT 1987 /* 1988 * If the packet is small enough to fit in a 1989 * single header mbuf, allocate one and copy 1990 * the data into it. This greatly reduces 1991 * memory consumption when we receive lots 1992 * of small packets. 1993 * 1994 * Otherwise, we add a new buffer to the receive 1995 * chain. If this fails, we drop the packet and 1996 * recycle the old buffer. 1997 */ 1998 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 1999 MGETHDR(m, M_DONTWAIT, MT_DATA); 2000 if (m == NULL) 2001 goto dropit; 2002 memcpy(mtod(m, caddr_t), 2003 mtod(rxs->rxs_mbuf, caddr_t), len); 2004 SIP_INIT_RXDESC(sc, i); 2005 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2006 rxs->rxs_dmamap->dm_mapsize, 2007 BUS_DMASYNC_PREREAD); 2008 } else { 2009 m = rxs->rxs_mbuf; 2010 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 2011 dropit: 2012 ifp->if_ierrors++; 2013 SIP_INIT_RXDESC(sc, i); 2014 bus_dmamap_sync(sc->sc_dmat, 2015 rxs->rxs_dmamap, 0, 2016 rxs->rxs_dmamap->dm_mapsize, 2017 BUS_DMASYNC_PREREAD); 2018 continue; 2019 } 2020 } 2021 #else 2022 /* 2023 * The SiS 900's receive buffers must be 4-byte aligned. 2024 * But this means that the data after the Ethernet header 2025 * is misaligned. We must allocate a new buffer and 2026 * copy the data, shifted forward 2 bytes. 2027 */ 2028 MGETHDR(m, M_DONTWAIT, MT_DATA); 2029 if (m == NULL) { 2030 dropit: 2031 ifp->if_ierrors++; 2032 SIP_INIT_RXDESC(sc, i); 2033 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2034 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2035 continue; 2036 } 2037 if (len > (MHLEN - 2)) { 2038 MCLGET(m, M_DONTWAIT); 2039 if ((m->m_flags & M_EXT) == 0) { 2040 m_freem(m); 2041 goto dropit; 2042 } 2043 } 2044 m->m_data += 2; 2045 2046 /* 2047 * Note that we use clusters for incoming frames, so the 2048 * buffer is virtually contiguous. 2049 */ 2050 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 2051 2052 /* Allow the receive descriptor to continue using its mbuf. */ 2053 SIP_INIT_RXDESC(sc, i); 2054 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2055 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2056 #endif /* __NO_STRICT_ALIGNMENT */ 2057 2058 ifp->if_ipackets++; 2059 m->m_flags |= M_HASFCS; 2060 m->m_pkthdr.rcvif = ifp; 2061 m->m_pkthdr.len = m->m_len = len; 2062 2063 #if NBPFILTER > 0 2064 /* 2065 * Pass this up to any BPF listeners, but only 2066 * pass if up the stack if it's for us. 2067 */ 2068 if (ifp->if_bpf) 2069 bpf_mtap(ifp->if_bpf, m); 2070 #endif /* NBPFILTER > 0 */ 2071 2072 /* Pass it on. */ 2073 (*ifp->if_input)(ifp, m); 2074 } 2075 2076 /* Update the receive pointer. */ 2077 sc->sc_rxptr = i; 2078 } 2079 #endif /* DP83820 */ 2080 2081 /* 2082 * sip_tick: 2083 * 2084 * One second timer, used to tick the MII. 2085 */ 2086 void 2087 SIP_DECL(tick)(void *arg) 2088 { 2089 struct sip_softc *sc = arg; 2090 int s; 2091 2092 s = splnet(); 2093 mii_tick(&sc->sc_mii); 2094 splx(s); 2095 2096 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2097 } 2098 2099 /* 2100 * sip_reset: 2101 * 2102 * Perform a soft reset on the SiS 900. 2103 */ 2104 void 2105 SIP_DECL(reset)(struct sip_softc *sc) 2106 { 2107 bus_space_tag_t st = sc->sc_st; 2108 bus_space_handle_t sh = sc->sc_sh; 2109 int i; 2110 2111 bus_space_write_4(st, sh, SIP_IER, 0); 2112 bus_space_write_4(st, sh, SIP_IMR, 0); 2113 bus_space_write_4(st, sh, SIP_RFCR, 0); 2114 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2115 2116 for (i = 0; i < SIP_TIMEOUT; i++) { 2117 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2118 break; 2119 delay(2); 2120 } 2121 2122 if (i == SIP_TIMEOUT) 2123 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2124 2125 delay(1000); 2126 2127 #ifdef DP83820 2128 /* 2129 * Set the general purpose I/O bits. Do it here in case we 2130 * need to have GPIO set up to talk to the media interface. 2131 */ 2132 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2133 delay(1000); 2134 #endif /* DP83820 */ 2135 } 2136 2137 /* 2138 * sip_init: [ ifnet interface function ] 2139 * 2140 * Initialize the interface. Must be called at splnet(). 2141 */ 2142 int 2143 SIP_DECL(init)(struct ifnet *ifp) 2144 { 2145 struct sip_softc *sc = ifp->if_softc; 2146 bus_space_tag_t st = sc->sc_st; 2147 bus_space_handle_t sh = sc->sc_sh; 2148 struct sip_txsoft *txs; 2149 struct sip_rxsoft *rxs; 2150 struct sip_desc *sipd; 2151 #if defined(DP83820) 2152 u_int32_t reg; 2153 #endif 2154 int i, error = 0; 2155 2156 /* 2157 * Cancel any pending I/O. 2158 */ 2159 SIP_DECL(stop)(ifp, 0); 2160 2161 /* 2162 * Reset the chip to a known state. 2163 */ 2164 SIP_DECL(reset)(sc); 2165 2166 #if !defined(DP83820) 2167 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2168 /* 2169 * DP83815 manual, page 78: 2170 * 4.4 Recommended Registers Configuration 2171 * For optimum performance of the DP83815, version noted 2172 * as DP83815CVNG (SRR = 203h), the listed register 2173 * modifications must be followed in sequence... 2174 * 2175 * It's not clear if this should be 302h or 203h because that 2176 * chip name is listed as SRR 302h in the description of the 2177 * SRR register. However, my revision 302h DP83815 on the 2178 * Netgear FA311 purchased in 02/2001 needs these settings 2179 * to avoid tons of errors in AcceptPerfectMatch (non- 2180 * IFF_PROMISC) mode. I do not know if other revisions need 2181 * this set or not. [briggs -- 09 March 2001] 2182 * 2183 * Note that only the low-order 12 bits of 0xe4 are documented 2184 * and that this sets reserved bits in that register. 2185 */ 2186 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2187 2188 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2189 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2190 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2191 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2192 2193 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2194 } 2195 #endif /* ! DP83820 */ 2196 2197 /* 2198 * Initialize the transmit descriptor ring. 2199 */ 2200 for (i = 0; i < SIP_NTXDESC; i++) { 2201 sipd = &sc->sc_txdescs[i]; 2202 memset(sipd, 0, sizeof(struct sip_desc)); 2203 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2204 } 2205 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2206 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2207 sc->sc_txfree = SIP_NTXDESC; 2208 sc->sc_txnext = 0; 2209 sc->sc_txwin = 0; 2210 2211 /* 2212 * Initialize the transmit job descriptors. 2213 */ 2214 SIMPLEQ_INIT(&sc->sc_txfreeq); 2215 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2216 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2217 txs = &sc->sc_txsoft[i]; 2218 txs->txs_mbuf = NULL; 2219 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2220 } 2221 2222 /* 2223 * Initialize the receive descriptor and receive job 2224 * descriptor rings. 2225 */ 2226 for (i = 0; i < SIP_NRXDESC; i++) { 2227 rxs = &sc->sc_rxsoft[i]; 2228 if (rxs->rxs_mbuf == NULL) { 2229 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2230 printf("%s: unable to allocate or map rx " 2231 "buffer %d, error = %d\n", 2232 sc->sc_dev.dv_xname, i, error); 2233 /* 2234 * XXX Should attempt to run with fewer receive 2235 * XXX buffers instead of just failing. 2236 */ 2237 SIP_DECL(rxdrain)(sc); 2238 goto out; 2239 } 2240 } else 2241 SIP_INIT_RXDESC(sc, i); 2242 } 2243 sc->sc_rxptr = 0; 2244 #ifdef DP83820 2245 sc->sc_rxdiscard = 0; 2246 SIP_RXCHAIN_RESET(sc); 2247 #endif /* DP83820 */ 2248 2249 /* 2250 * Set the configuration register; it's already initialized 2251 * in sip_attach(). 2252 */ 2253 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2254 2255 /* 2256 * Initialize the prototype TXCFG register. 2257 */ 2258 #if defined(DP83820) 2259 sc->sc_txcfg = TXCFG_MXDMA_512; 2260 sc->sc_rxcfg = RXCFG_MXDMA_512; 2261 #else 2262 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2263 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2264 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & CFG_EDBMASTEN)) { 2265 sc->sc_txcfg = TXCFG_MXDMA_64; 2266 sc->sc_rxcfg = RXCFG_MXDMA_64; 2267 } else { 2268 sc->sc_txcfg = TXCFG_MXDMA_512; 2269 sc->sc_rxcfg = RXCFG_MXDMA_512; 2270 } 2271 #endif /* DP83820 */ 2272 2273 sc->sc_txcfg |= TXCFG_ATP | 2274 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2275 sc->sc_tx_drain_thresh; 2276 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2277 2278 /* 2279 * Initialize the receive drain threshold if we have never 2280 * done so. 2281 */ 2282 if (sc->sc_rx_drain_thresh == 0) { 2283 /* 2284 * XXX This value should be tuned. This is set to the 2285 * maximum of 248 bytes, and we may be able to improve 2286 * performance by decreasing it (although we should never 2287 * set this value lower than 2; 14 bytes are required to 2288 * filter the packet). 2289 */ 2290 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2291 } 2292 2293 /* 2294 * Initialize the prototype RXCFG register. 2295 */ 2296 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2297 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2298 2299 #ifdef DP83820 2300 /* 2301 * Initialize the VLAN/IP receive control register. 2302 * We enable checksum computation on all incoming 2303 * packets, and do not reject packets w/ bad checksums. 2304 */ 2305 reg = 0; 2306 if (ifp->if_capenable & 2307 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2308 reg |= VRCR_IPEN; 2309 if (sc->sc_ethercom.ec_nvlans != 0) 2310 reg |= VRCR_VTDEN|VRCR_VTREN; 2311 bus_space_write_4(st, sh, SIP_VRCR, reg); 2312 2313 /* 2314 * Initialize the VLAN/IP transmit control register. 2315 * We enable outgoing checksum computation on a 2316 * per-packet basis. 2317 */ 2318 reg = 0; 2319 if (ifp->if_capenable & 2320 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2321 reg |= VTCR_PPCHK; 2322 if (sc->sc_ethercom.ec_nvlans != 0) 2323 reg |= VTCR_VPPTI; 2324 bus_space_write_4(st, sh, SIP_VTCR, reg); 2325 2326 /* 2327 * If we're using VLANs, initialize the VLAN data register. 2328 * To understand why we bswap the VLAN Ethertype, see section 2329 * 4.2.36 of the DP83820 manual. 2330 */ 2331 if (sc->sc_ethercom.ec_nvlans != 0) 2332 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2333 #endif /* DP83820 */ 2334 2335 /* 2336 * Give the transmit and receive rings to the chip. 2337 */ 2338 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2339 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2340 2341 /* 2342 * Initialize the interrupt mask. 2343 */ 2344 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2345 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2346 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2347 2348 /* Set up the receive filter. */ 2349 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2350 2351 /* 2352 * Set the current media. Do this after initializing the prototype 2353 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2354 * control. 2355 */ 2356 mii_mediachg(&sc->sc_mii); 2357 2358 /* 2359 * Enable interrupts. 2360 */ 2361 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2362 2363 /* 2364 * Start the transmit and receive processes. 2365 */ 2366 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2367 2368 /* 2369 * Start the one second MII clock. 2370 */ 2371 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2372 2373 /* 2374 * ...all done! 2375 */ 2376 ifp->if_flags |= IFF_RUNNING; 2377 ifp->if_flags &= ~IFF_OACTIVE; 2378 2379 out: 2380 if (error) 2381 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2382 return (error); 2383 } 2384 2385 /* 2386 * sip_drain: 2387 * 2388 * Drain the receive queue. 2389 */ 2390 void 2391 SIP_DECL(rxdrain)(struct sip_softc *sc) 2392 { 2393 struct sip_rxsoft *rxs; 2394 int i; 2395 2396 for (i = 0; i < SIP_NRXDESC; i++) { 2397 rxs = &sc->sc_rxsoft[i]; 2398 if (rxs->rxs_mbuf != NULL) { 2399 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2400 m_freem(rxs->rxs_mbuf); 2401 rxs->rxs_mbuf = NULL; 2402 } 2403 } 2404 } 2405 2406 /* 2407 * sip_stop: [ ifnet interface function ] 2408 * 2409 * Stop transmission on the interface. 2410 */ 2411 void 2412 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2413 { 2414 struct sip_softc *sc = ifp->if_softc; 2415 bus_space_tag_t st = sc->sc_st; 2416 bus_space_handle_t sh = sc->sc_sh; 2417 struct sip_txsoft *txs; 2418 u_int32_t cmdsts = 0; /* DEBUG */ 2419 2420 /* 2421 * Stop the one second clock. 2422 */ 2423 callout_stop(&sc->sc_tick_ch); 2424 2425 /* Down the MII. */ 2426 mii_down(&sc->sc_mii); 2427 2428 /* 2429 * Disable interrupts. 2430 */ 2431 bus_space_write_4(st, sh, SIP_IER, 0); 2432 2433 /* 2434 * Stop receiver and transmitter. 2435 */ 2436 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2437 2438 /* 2439 * Release any queued transmit buffers. 2440 */ 2441 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2442 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2443 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2444 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2445 CMDSTS_INTR) == 0) 2446 printf("%s: sip_stop: last descriptor does not " 2447 "have INTR bit set\n", sc->sc_dev.dv_xname); 2448 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 2449 #ifdef DIAGNOSTIC 2450 if (txs->txs_mbuf == NULL) { 2451 printf("%s: dirty txsoft with no mbuf chain\n", 2452 sc->sc_dev.dv_xname); 2453 panic("sip_stop"); 2454 } 2455 #endif 2456 cmdsts |= /* DEBUG */ 2457 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2458 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2459 m_freem(txs->txs_mbuf); 2460 txs->txs_mbuf = NULL; 2461 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2462 } 2463 2464 if (disable) 2465 SIP_DECL(rxdrain)(sc); 2466 2467 /* 2468 * Mark the interface down and cancel the watchdog timer. 2469 */ 2470 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2471 ifp->if_timer = 0; 2472 2473 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2474 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2475 printf("%s: sip_stop: no INTR bits set in dirty tx " 2476 "descriptors\n", sc->sc_dev.dv_xname); 2477 } 2478 2479 /* 2480 * sip_read_eeprom: 2481 * 2482 * Read data from the serial EEPROM. 2483 */ 2484 void 2485 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2486 u_int16_t *data) 2487 { 2488 bus_space_tag_t st = sc->sc_st; 2489 bus_space_handle_t sh = sc->sc_sh; 2490 u_int16_t reg; 2491 int i, x; 2492 2493 for (i = 0; i < wordcnt; i++) { 2494 /* Send CHIP SELECT. */ 2495 reg = EROMAR_EECS; 2496 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2497 2498 /* Shift in the READ opcode. */ 2499 for (x = 3; x > 0; x--) { 2500 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2501 reg |= EROMAR_EEDI; 2502 else 2503 reg &= ~EROMAR_EEDI; 2504 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2505 bus_space_write_4(st, sh, SIP_EROMAR, 2506 reg | EROMAR_EESK); 2507 delay(4); 2508 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2509 delay(4); 2510 } 2511 2512 /* Shift in address. */ 2513 for (x = 6; x > 0; x--) { 2514 if ((word + i) & (1 << (x - 1))) 2515 reg |= EROMAR_EEDI; 2516 else 2517 reg &= ~EROMAR_EEDI; 2518 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2519 bus_space_write_4(st, sh, SIP_EROMAR, 2520 reg | EROMAR_EESK); 2521 delay(4); 2522 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2523 delay(4); 2524 } 2525 2526 /* Shift out data. */ 2527 reg = EROMAR_EECS; 2528 data[i] = 0; 2529 for (x = 16; x > 0; x--) { 2530 bus_space_write_4(st, sh, SIP_EROMAR, 2531 reg | EROMAR_EESK); 2532 delay(4); 2533 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2534 data[i] |= (1 << (x - 1)); 2535 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2536 delay(4); 2537 } 2538 2539 /* Clear CHIP SELECT. */ 2540 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2541 delay(4); 2542 } 2543 } 2544 2545 /* 2546 * sip_add_rxbuf: 2547 * 2548 * Add a receive buffer to the indicated descriptor. 2549 */ 2550 int 2551 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2552 { 2553 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2554 struct mbuf *m; 2555 int error; 2556 2557 MGETHDR(m, M_DONTWAIT, MT_DATA); 2558 if (m == NULL) 2559 return (ENOBUFS); 2560 2561 MCLGET(m, M_DONTWAIT); 2562 if ((m->m_flags & M_EXT) == 0) { 2563 m_freem(m); 2564 return (ENOBUFS); 2565 } 2566 2567 #if defined(DP83820) 2568 m->m_len = SIP_RXBUF_LEN; 2569 #endif /* DP83820 */ 2570 2571 if (rxs->rxs_mbuf != NULL) 2572 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2573 2574 rxs->rxs_mbuf = m; 2575 2576 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2577 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2578 BUS_DMA_READ|BUS_DMA_NOWAIT); 2579 if (error) { 2580 printf("%s: can't load rx DMA map %d, error = %d\n", 2581 sc->sc_dev.dv_xname, idx, error); 2582 panic("sip_add_rxbuf"); /* XXX */ 2583 } 2584 2585 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2586 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2587 2588 SIP_INIT_RXDESC(sc, idx); 2589 2590 return (0); 2591 } 2592 2593 #if !defined(DP83820) 2594 /* 2595 * sip_sis900_set_filter: 2596 * 2597 * Set up the receive filter. 2598 */ 2599 void 2600 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2601 { 2602 bus_space_tag_t st = sc->sc_st; 2603 bus_space_handle_t sh = sc->sc_sh; 2604 struct ethercom *ec = &sc->sc_ethercom; 2605 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2606 struct ether_multi *enm; 2607 u_int8_t *cp; 2608 struct ether_multistep step; 2609 u_int32_t crc, mchash[16]; 2610 2611 /* 2612 * Initialize the prototype RFCR. 2613 */ 2614 sc->sc_rfcr = RFCR_RFEN; 2615 if (ifp->if_flags & IFF_BROADCAST) 2616 sc->sc_rfcr |= RFCR_AAB; 2617 if (ifp->if_flags & IFF_PROMISC) { 2618 sc->sc_rfcr |= RFCR_AAP; 2619 goto allmulti; 2620 } 2621 2622 /* 2623 * Set up the multicast address filter by passing all multicast 2624 * addresses through a CRC generator, and then using the high-order 2625 * 6 bits as an index into the 128 bit multicast hash table (only 2626 * the lower 16 bits of each 32 bit multicast hash register are 2627 * valid). The high order bits select the register, while the 2628 * rest of the bits select the bit within the register. 2629 */ 2630 2631 memset(mchash, 0, sizeof(mchash)); 2632 2633 ETHER_FIRST_MULTI(step, ec, enm); 2634 while (enm != NULL) { 2635 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2636 /* 2637 * We must listen to a range of multicast addresses. 2638 * For now, just accept all multicasts, rather than 2639 * trying to set only those filter bits needed to match 2640 * the range. (At this time, the only use of address 2641 * ranges is for IP multicast routing, for which the 2642 * range is big enough to require all bits set.) 2643 */ 2644 goto allmulti; 2645 } 2646 2647 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2648 2649 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2650 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2651 /* Just want the 8 most significant bits. */ 2652 crc >>= 24; 2653 } else { 2654 /* Just want the 7 most significant bits. */ 2655 crc >>= 25; 2656 } 2657 2658 /* Set the corresponding bit in the hash table. */ 2659 mchash[crc >> 4] |= 1 << (crc & 0xf); 2660 2661 ETHER_NEXT_MULTI(step, enm); 2662 } 2663 2664 ifp->if_flags &= ~IFF_ALLMULTI; 2665 goto setit; 2666 2667 allmulti: 2668 ifp->if_flags |= IFF_ALLMULTI; 2669 sc->sc_rfcr |= RFCR_AAM; 2670 2671 setit: 2672 #define FILTER_EMIT(addr, data) \ 2673 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2674 delay(1); \ 2675 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2676 delay(1) 2677 2678 /* 2679 * Disable receive filter, and program the node address. 2680 */ 2681 cp = LLADDR(ifp->if_sadl); 2682 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2683 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2684 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2685 2686 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2687 /* 2688 * Program the multicast hash table. 2689 */ 2690 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2691 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2692 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2693 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2694 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2695 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2696 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2697 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2698 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2699 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2700 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2701 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2702 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2703 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2704 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2705 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2706 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2707 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2708 } 2709 } 2710 #undef FILTER_EMIT 2711 2712 /* 2713 * Re-enable the receiver filter. 2714 */ 2715 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2716 } 2717 #endif /* ! DP83820 */ 2718 2719 /* 2720 * sip_dp83815_set_filter: 2721 * 2722 * Set up the receive filter. 2723 */ 2724 void 2725 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2726 { 2727 bus_space_tag_t st = sc->sc_st; 2728 bus_space_handle_t sh = sc->sc_sh; 2729 struct ethercom *ec = &sc->sc_ethercom; 2730 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2731 struct ether_multi *enm; 2732 u_int8_t *cp; 2733 struct ether_multistep step; 2734 u_int32_t crc, hash, slot, bit; 2735 #ifdef DP83820 2736 #define MCHASH_NWORDS 128 2737 #else 2738 #define MCHASH_NWORDS 32 2739 #endif /* DP83820 */ 2740 u_int16_t mchash[MCHASH_NWORDS]; 2741 int i; 2742 2743 /* 2744 * Initialize the prototype RFCR. 2745 * Enable the receive filter, and accept on 2746 * Perfect (destination address) Match 2747 * If IFF_BROADCAST, also accept all broadcast packets. 2748 * If IFF_PROMISC, accept all unicast packets (and later, set 2749 * IFF_ALLMULTI and accept all multicast, too). 2750 */ 2751 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2752 if (ifp->if_flags & IFF_BROADCAST) 2753 sc->sc_rfcr |= RFCR_AAB; 2754 if (ifp->if_flags & IFF_PROMISC) { 2755 sc->sc_rfcr |= RFCR_AAP; 2756 goto allmulti; 2757 } 2758 2759 #ifdef DP83820 2760 /* 2761 * Set up the DP83820 multicast address filter by passing all multicast 2762 * addresses through a CRC generator, and then using the high-order 2763 * 11 bits as an index into the 2048 bit multicast hash table. The 2764 * high-order 7 bits select the slot, while the low-order 4 bits 2765 * select the bit within the slot. Note that only the low 16-bits 2766 * of each filter word are used, and there are 128 filter words. 2767 */ 2768 #else 2769 /* 2770 * Set up the DP83815 multicast address filter by passing all multicast 2771 * addresses through a CRC generator, and then using the high-order 2772 * 9 bits as an index into the 512 bit multicast hash table. The 2773 * high-order 5 bits select the slot, while the low-order 4 bits 2774 * select the bit within the slot. Note that only the low 16-bits 2775 * of each filter word are used, and there are 32 filter words. 2776 */ 2777 #endif /* DP83820 */ 2778 2779 memset(mchash, 0, sizeof(mchash)); 2780 2781 ifp->if_flags &= ~IFF_ALLMULTI; 2782 ETHER_FIRST_MULTI(step, ec, enm); 2783 if (enm == NULL) 2784 goto setit; 2785 while (enm != NULL) { 2786 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2787 /* 2788 * We must listen to a range of multicast addresses. 2789 * For now, just accept all multicasts, rather than 2790 * trying to set only those filter bits needed to match 2791 * the range. (At this time, the only use of address 2792 * ranges is for IP multicast routing, for which the 2793 * range is big enough to require all bits set.) 2794 */ 2795 goto allmulti; 2796 } 2797 2798 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2799 2800 #ifdef DP83820 2801 /* Just want the 11 most significant bits. */ 2802 hash = crc >> 21; 2803 #else 2804 /* Just want the 9 most significant bits. */ 2805 hash = crc >> 23; 2806 #endif /* DP83820 */ 2807 2808 slot = hash >> 4; 2809 bit = hash & 0xf; 2810 2811 /* Set the corresponding bit in the hash table. */ 2812 mchash[slot] |= 1 << bit; 2813 2814 ETHER_NEXT_MULTI(step, enm); 2815 } 2816 sc->sc_rfcr |= RFCR_MHEN; 2817 goto setit; 2818 2819 allmulti: 2820 ifp->if_flags |= IFF_ALLMULTI; 2821 sc->sc_rfcr |= RFCR_AAM; 2822 2823 setit: 2824 #define FILTER_EMIT(addr, data) \ 2825 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2826 delay(1); \ 2827 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2828 delay(1) 2829 2830 /* 2831 * Disable receive filter, and program the node address. 2832 */ 2833 cp = LLADDR(ifp->if_sadl); 2834 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 2835 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 2836 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 2837 2838 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2839 /* 2840 * Program the multicast hash table. 2841 */ 2842 for (i = 0; i < MCHASH_NWORDS; i++) { 2843 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 2844 mchash[i]); 2845 } 2846 } 2847 #undef FILTER_EMIT 2848 #undef MCHASH_NWORDS 2849 2850 /* 2851 * Re-enable the receiver filter. 2852 */ 2853 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2854 } 2855 2856 #if defined(DP83820) 2857 /* 2858 * sip_dp83820_mii_readreg: [mii interface function] 2859 * 2860 * Read a PHY register on the MII of the DP83820. 2861 */ 2862 int 2863 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 2864 { 2865 2866 return (mii_bitbang_readreg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2867 phy, reg)); 2868 } 2869 2870 /* 2871 * sip_dp83820_mii_writereg: [mii interface function] 2872 * 2873 * Write a PHY register on the MII of the DP83820. 2874 */ 2875 void 2876 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 2877 { 2878 2879 mii_bitbang_writereg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2880 phy, reg, val); 2881 } 2882 2883 /* 2884 * sip_dp83815_mii_statchg: [mii interface function] 2885 * 2886 * Callback from MII layer when media changes. 2887 */ 2888 void 2889 SIP_DECL(dp83820_mii_statchg)(struct device *self) 2890 { 2891 struct sip_softc *sc = (struct sip_softc *) self; 2892 u_int32_t cfg; 2893 2894 /* 2895 * Update TXCFG for full-duplex operation. 2896 */ 2897 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2898 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2899 else 2900 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2901 2902 /* 2903 * Update RXCFG for full-duplex or loopback. 2904 */ 2905 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2906 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2907 sc->sc_rxcfg |= RXCFG_ATX; 2908 else 2909 sc->sc_rxcfg &= ~RXCFG_ATX; 2910 2911 /* 2912 * Update CFG for MII/GMII. 2913 */ 2914 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2915 cfg = sc->sc_cfg | CFG_MODE_1000; 2916 else 2917 cfg = sc->sc_cfg; 2918 2919 /* 2920 * XXX 802.3x flow control. 2921 */ 2922 2923 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 2924 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2925 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2926 } 2927 2928 /* 2929 * sip_dp83820_mii_bitbang_read: [mii bit-bang interface function] 2930 * 2931 * Read the MII serial port for the MII bit-bang module. 2932 */ 2933 u_int32_t 2934 SIP_DECL(dp83820_mii_bitbang_read)(struct device *self) 2935 { 2936 struct sip_softc *sc = (void *) self; 2937 2938 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 2939 } 2940 2941 /* 2942 * sip_dp83820_mii_bitbang_write: [mii big-bang interface function] 2943 * 2944 * Write the MII serial port for the MII bit-bang module. 2945 */ 2946 void 2947 SIP_DECL(dp83820_mii_bitbang_write)(struct device *self, u_int32_t val) 2948 { 2949 struct sip_softc *sc = (void *) self; 2950 2951 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 2952 } 2953 #else /* ! DP83820 */ 2954 /* 2955 * sip_sis900_mii_readreg: [mii interface function] 2956 * 2957 * Read a PHY register on the MII. 2958 */ 2959 int 2960 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 2961 { 2962 struct sip_softc *sc = (struct sip_softc *) self; 2963 u_int32_t enphy; 2964 2965 /* 2966 * The SiS 900 has only an internal PHY on the MII. Only allow 2967 * MII address 0. 2968 */ 2969 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 2970 sc->sc_rev < SIS_REV_635 && phy != 0) 2971 return (0); 2972 2973 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2974 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 2975 ENPHY_RWCMD | ENPHY_ACCESS); 2976 do { 2977 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2978 } while (enphy & ENPHY_ACCESS); 2979 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 2980 } 2981 2982 /* 2983 * sip_sis900_mii_writereg: [mii interface function] 2984 * 2985 * Write a PHY register on the MII. 2986 */ 2987 void 2988 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 2989 { 2990 struct sip_softc *sc = (struct sip_softc *) self; 2991 u_int32_t enphy; 2992 2993 /* 2994 * The SiS 900 has only an internal PHY on the MII. Only allow 2995 * MII address 0. 2996 */ 2997 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 2998 sc->sc_rev < SIS_REV_635 && phy != 0) 2999 return; 3000 3001 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3002 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3003 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3004 do { 3005 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3006 } while (enphy & ENPHY_ACCESS); 3007 } 3008 3009 /* 3010 * sip_sis900_mii_statchg: [mii interface function] 3011 * 3012 * Callback from MII layer when media changes. 3013 */ 3014 void 3015 SIP_DECL(sis900_mii_statchg)(struct device *self) 3016 { 3017 struct sip_softc *sc = (struct sip_softc *) self; 3018 u_int32_t flowctl; 3019 3020 /* 3021 * Update TXCFG for full-duplex operation. 3022 */ 3023 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3024 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3025 else 3026 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3027 3028 /* 3029 * Update RXCFG for full-duplex or loopback. 3030 */ 3031 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3032 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3033 sc->sc_rxcfg |= RXCFG_ATX; 3034 else 3035 sc->sc_rxcfg &= ~RXCFG_ATX; 3036 3037 /* 3038 * Update IMR for use of 802.3x flow control. 3039 */ 3040 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 3041 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3042 flowctl = FLOWCTL_FLOWEN; 3043 } else { 3044 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3045 flowctl = 0; 3046 } 3047 3048 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3049 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3050 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3051 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3052 } 3053 3054 /* 3055 * sip_dp83815_mii_readreg: [mii interface function] 3056 * 3057 * Read a PHY register on the MII. 3058 */ 3059 int 3060 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 3061 { 3062 struct sip_softc *sc = (struct sip_softc *) self; 3063 u_int32_t val; 3064 3065 /* 3066 * The DP83815 only has an internal PHY. Only allow 3067 * MII address 0. 3068 */ 3069 if (phy != 0) 3070 return (0); 3071 3072 /* 3073 * Apparently, after a reset, the DP83815 can take a while 3074 * to respond. During this recovery period, the BMSR returns 3075 * a value of 0. Catch this -- it's not supposed to happen 3076 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3077 * PHY to come back to life. 3078 * 3079 * This works out because the BMSR is the first register 3080 * read during the PHY probe process. 3081 */ 3082 do { 3083 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3084 } while (reg == MII_BMSR && val == 0); 3085 3086 return (val & 0xffff); 3087 } 3088 3089 /* 3090 * sip_dp83815_mii_writereg: [mii interface function] 3091 * 3092 * Write a PHY register to the MII. 3093 */ 3094 void 3095 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3096 { 3097 struct sip_softc *sc = (struct sip_softc *) self; 3098 3099 /* 3100 * The DP83815 only has an internal PHY. Only allow 3101 * MII address 0. 3102 */ 3103 if (phy != 0) 3104 return; 3105 3106 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3107 } 3108 3109 /* 3110 * sip_dp83815_mii_statchg: [mii interface function] 3111 * 3112 * Callback from MII layer when media changes. 3113 */ 3114 void 3115 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3116 { 3117 struct sip_softc *sc = (struct sip_softc *) self; 3118 3119 /* 3120 * Update TXCFG for full-duplex operation. 3121 */ 3122 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3123 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3124 else 3125 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3126 3127 /* 3128 * Update RXCFG for full-duplex or loopback. 3129 */ 3130 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3131 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3132 sc->sc_rxcfg |= RXCFG_ATX; 3133 else 3134 sc->sc_rxcfg &= ~RXCFG_ATX; 3135 3136 /* 3137 * XXX 802.3x flow control. 3138 */ 3139 3140 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3141 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3142 3143 /* 3144 * Some DP83815s experience problems when used with short 3145 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3146 * sequence adjusts the DSP's signal attenuation to fix the 3147 * problem. 3148 */ 3149 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3150 uint32_t reg; 3151 3152 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3153 3154 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3155 reg &= 0x0fff; 3156 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3157 delay(100); 3158 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3159 reg &= 0x00ff; 3160 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3161 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3162 0x00e8); 3163 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3164 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3165 reg | 0x20); 3166 } 3167 3168 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3169 } 3170 } 3171 #endif /* DP83820 */ 3172 3173 #if defined(DP83820) 3174 void 3175 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3176 const struct pci_attach_args *pa, u_int8_t *enaddr) 3177 { 3178 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3179 u_int8_t cksum, *e, match; 3180 int i; 3181 3182 /* 3183 * EEPROM data format for the DP83820 can be found in 3184 * the DP83820 manual, section 4.2.4. 3185 */ 3186 3187 SIP_DECL(read_eeprom)(sc, 0, 3188 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3189 3190 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3191 match = ~(match - 1); 3192 3193 cksum = 0x55; 3194 e = (u_int8_t *) eeprom_data; 3195 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3196 cksum += *e++; 3197 3198 if (cksum != match) 3199 printf("%s: Checksum (%x) mismatch (%x)", 3200 sc->sc_dev.dv_xname, cksum, match); 3201 3202 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3203 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3204 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3205 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3206 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3207 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3208 3209 /* Get the GPIOR bits. */ 3210 sc->sc_gpior = eeprom_data[0x04]; 3211 } 3212 #else /* ! DP83820 */ 3213 void 3214 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3215 const struct pci_attach_args *pa, u_int8_t *enaddr) 3216 { 3217 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3218 3219 switch (sc->sc_rev) { 3220 case SIS_REV_630S: 3221 case SIS_REV_630E: 3222 case SIS_REV_630EA1: 3223 case SIS_REV_630ET: 3224 case SIS_REV_635: 3225 /* 3226 * The MAC address for the on-board Ethernet of 3227 * the SiS 630 chipset is in the NVRAM. Kick 3228 * the chip into re-loading it from NVRAM, and 3229 * read the MAC address out of the filter registers. 3230 */ 3231 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3232 3233 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3234 RFCR_RFADDR_NODE0); 3235 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3236 0xffff; 3237 3238 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3239 RFCR_RFADDR_NODE2); 3240 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3241 0xffff; 3242 3243 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3244 RFCR_RFADDR_NODE4); 3245 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3246 0xffff; 3247 break; 3248 3249 default: 3250 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3251 sizeof(myea) / sizeof(myea[0]), myea); 3252 } 3253 3254 enaddr[0] = myea[0] & 0xff; 3255 enaddr[1] = myea[0] >> 8; 3256 enaddr[2] = myea[1] & 0xff; 3257 enaddr[3] = myea[1] >> 8; 3258 enaddr[4] = myea[2] & 0xff; 3259 enaddr[5] = myea[2] >> 8; 3260 } 3261 3262 /* Table and macro to bit-reverse an octet. */ 3263 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3264 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3265 3266 void 3267 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3268 const struct pci_attach_args *pa, u_int8_t *enaddr) 3269 { 3270 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3271 u_int8_t cksum, *e, match; 3272 int i; 3273 3274 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3275 sizeof(eeprom_data[0]), eeprom_data); 3276 3277 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3278 match = ~(match - 1); 3279 3280 cksum = 0x55; 3281 e = (u_int8_t *) eeprom_data; 3282 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3283 cksum += *e++; 3284 } 3285 if (cksum != match) { 3286 printf("%s: Checksum (%x) mismatch (%x)", 3287 sc->sc_dev.dv_xname, cksum, match); 3288 } 3289 3290 /* 3291 * Unrolled because it makes slightly more sense this way. 3292 * The DP83815 stores the MAC address in bit 0 of word 6 3293 * through bit 15 of word 8. 3294 */ 3295 ea = &eeprom_data[6]; 3296 enaddr[0] = ((*ea & 0x1) << 7); 3297 ea++; 3298 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3299 enaddr[1] = ((*ea & 0x1FE) >> 1); 3300 enaddr[2] = ((*ea & 0x1) << 7); 3301 ea++; 3302 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3303 enaddr[3] = ((*ea & 0x1FE) >> 1); 3304 enaddr[4] = ((*ea & 0x1) << 7); 3305 ea++; 3306 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3307 enaddr[5] = ((*ea & 0x1FE) >> 1); 3308 3309 /* 3310 * In case that's not weird enough, we also need to reverse 3311 * the bits in each byte. This all actually makes more sense 3312 * if you think about the EEPROM storage as an array of bits 3313 * being shifted into bytes, but that's not how we're looking 3314 * at it here... 3315 */ 3316 for (i = 0; i < 6 ;i++) 3317 enaddr[i] = bbr(enaddr[i]); 3318 } 3319 #endif /* DP83820 */ 3320 3321 /* 3322 * sip_mediastatus: [ifmedia interface function] 3323 * 3324 * Get the current interface media status. 3325 */ 3326 void 3327 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3328 { 3329 struct sip_softc *sc = ifp->if_softc; 3330 3331 mii_pollstat(&sc->sc_mii); 3332 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3333 ifmr->ifm_active = sc->sc_mii.mii_media_active; 3334 } 3335 3336 /* 3337 * sip_mediachange: [ifmedia interface function] 3338 * 3339 * Set hardware to newly-selected media. 3340 */ 3341 int 3342 SIP_DECL(mediachange)(struct ifnet *ifp) 3343 { 3344 struct sip_softc *sc = ifp->if_softc; 3345 3346 if (ifp->if_flags & IFF_UP) 3347 mii_mediachg(&sc->sc_mii); 3348 return (0); 3349 } 3350
Indexes created Tue Sep 30 11:09:46 GMT 2025