if_sip.c revision 1.57
1 /* $NetBSD: if_sip.c,v 1.57 2002/06/30 19:11:40 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Support the 10-bit interface on the DP83820 (for fiber). 80 * 81 * - Reduce the interrupt load. 82 */ 83 84 #include <sys/cdefs.h> 85 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.57 2002/06/30 19:11:40 thorpej Exp $"); 86 87 #include "bpfilter.h" 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/callout.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/ioctl.h> 97 #include <sys/errno.h> 98 #include <sys/device.h> 99 #include <sys/queue.h> 100 101 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 102 103 #include <net/if.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 #include <net/if_ether.h> 107 108 #if NBPFILTER > 0 109 #include <net/bpf.h> 110 #endif 111 112 #include <machine/bus.h> 113 #include <machine/intr.h> 114 #include <machine/endian.h> 115 116 #include <dev/mii/mii.h> 117 #include <dev/mii/miivar.h> 118 #ifdef DP83820 119 #include <dev/mii/mii_bitbang.h> 120 #endif /* DP83820 */ 121 122 #include <dev/pci/pcireg.h> 123 #include <dev/pci/pcivar.h> 124 #include <dev/pci/pcidevs.h> 125 126 #include <dev/pci/if_sipreg.h> 127 128 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 129 #define SIP_DECL(x) __CONCAT(gsip_,x) 130 #else /* SiS900 and DP83815 */ 131 #define SIP_DECL(x) __CONCAT(sip_,x) 132 #endif 133 134 #define SIP_STR(x) __STRING(SIP_DECL(x)) 135 136 /* 137 * Transmit descriptor list size. This is arbitrary, but allocate 138 * enough descriptors for 128 pending transmissions, and 8 segments 139 * per packet. This MUST work out to a power of 2. 140 */ 141 #define SIP_NTXSEGS 16 142 #define SIP_NTXSEGS_ALLOC 8 143 144 #define SIP_TXQUEUELEN 256 145 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 146 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 147 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 148 149 #if defined(DP83020) 150 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 151 #else 152 #define TX_DMAMAP_SIZE MCLBYTES 153 #endif 154 155 /* 156 * Receive descriptor list size. We have one Rx buffer per incoming 157 * packet, so this logic is a little simpler. 158 * 159 * Actually, on the DP83820, we allow the packet to consume more than 160 * one buffer, in order to support jumbo Ethernet frames. In that 161 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 162 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 163 * so we'd better be quick about handling receive interrupts. 164 */ 165 #if defined(DP83820) 166 #define SIP_NRXDESC 256 167 #else 168 #define SIP_NRXDESC 128 169 #endif /* DP83820 */ 170 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 171 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 172 173 /* 174 * Control structures are DMA'd to the SiS900 chip. We allocate them in 175 * a single clump that maps to a single DMA segment to make several things 176 * easier. 177 */ 178 struct sip_control_data { 179 /* 180 * The transmit descriptors. 181 */ 182 struct sip_desc scd_txdescs[SIP_NTXDESC]; 183 184 /* 185 * The receive descriptors. 186 */ 187 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 188 }; 189 190 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 191 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 192 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 193 194 /* 195 * Software state for transmit jobs. 196 */ 197 struct sip_txsoft { 198 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 199 bus_dmamap_t txs_dmamap; /* our DMA map */ 200 int txs_firstdesc; /* first descriptor in packet */ 201 int txs_lastdesc; /* last descriptor in packet */ 202 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 203 }; 204 205 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 206 207 /* 208 * Software state for receive jobs. 209 */ 210 struct sip_rxsoft { 211 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 212 bus_dmamap_t rxs_dmamap; /* our DMA map */ 213 }; 214 215 /* 216 * Software state per device. 217 */ 218 struct sip_softc { 219 struct device sc_dev; /* generic device information */ 220 bus_space_tag_t sc_st; /* bus space tag */ 221 bus_space_handle_t sc_sh; /* bus space handle */ 222 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 223 struct ethercom sc_ethercom; /* ethernet common data */ 224 void *sc_sdhook; /* shutdown hook */ 225 226 const struct sip_product *sc_model; /* which model are we? */ 227 int sc_rev; /* chip revision */ 228 229 void *sc_ih; /* interrupt cookie */ 230 231 struct mii_data sc_mii; /* MII/media information */ 232 233 struct callout sc_tick_ch; /* tick callout */ 234 235 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 236 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 237 238 /* 239 * Software state for transmit and receive descriptors. 240 */ 241 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 242 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 243 244 /* 245 * Control data structures. 246 */ 247 struct sip_control_data *sc_control_data; 248 #define sc_txdescs sc_control_data->scd_txdescs 249 #define sc_rxdescs sc_control_data->scd_rxdescs 250 251 #ifdef SIP_EVENT_COUNTERS 252 /* 253 * Event counters. 254 */ 255 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 256 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 257 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 258 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 259 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 260 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 261 #ifdef DP83820 262 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 263 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 264 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 265 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 266 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 267 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 268 #endif /* DP83820 */ 269 #endif /* SIP_EVENT_COUNTERS */ 270 271 u_int32_t sc_txcfg; /* prototype TXCFG register */ 272 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 273 u_int32_t sc_imr; /* prototype IMR register */ 274 u_int32_t sc_rfcr; /* prototype RFCR register */ 275 276 u_int32_t sc_cfg; /* prototype CFG register */ 277 278 #ifdef DP83820 279 u_int32_t sc_gpior; /* prototype GPIOR register */ 280 #endif /* DP83820 */ 281 282 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 283 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 284 285 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 286 287 int sc_flags; /* misc. flags; see below */ 288 289 int sc_txfree; /* number of free Tx descriptors */ 290 int sc_txnext; /* next ready Tx descriptor */ 291 int sc_txwin; /* Tx descriptors since last intr */ 292 293 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 294 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 295 296 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 297 #if defined(DP83820) 298 int sc_rxdiscard; 299 int sc_rxlen; 300 struct mbuf *sc_rxhead; 301 struct mbuf *sc_rxtail; 302 struct mbuf **sc_rxtailp; 303 #endif /* DP83820 */ 304 }; 305 306 /* sc_flags */ 307 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 308 309 #ifdef DP83820 310 #define SIP_RXCHAIN_RESET(sc) \ 311 do { \ 312 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 313 *(sc)->sc_rxtailp = NULL; \ 314 (sc)->sc_rxlen = 0; \ 315 } while (/*CONSTCOND*/0) 316 317 #define SIP_RXCHAIN_LINK(sc, m) \ 318 do { \ 319 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 320 (sc)->sc_rxtailp = &(m)->m_next; \ 321 } while (/*CONSTCOND*/0) 322 #endif /* DP83820 */ 323 324 #ifdef SIP_EVENT_COUNTERS 325 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 326 #else 327 #define SIP_EVCNT_INCR(ev) /* nothing */ 328 #endif 329 330 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 331 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 332 333 #define SIP_CDTXSYNC(sc, x, n, ops) \ 334 do { \ 335 int __x, __n; \ 336 \ 337 __x = (x); \ 338 __n = (n); \ 339 \ 340 /* If it will wrap around, sync to the end of the ring. */ \ 341 if ((__x + __n) > SIP_NTXDESC) { \ 342 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 343 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 344 (SIP_NTXDESC - __x), (ops)); \ 345 __n -= (SIP_NTXDESC - __x); \ 346 __x = 0; \ 347 } \ 348 \ 349 /* Now sync whatever is left. */ \ 350 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 351 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 352 } while (0) 353 354 #define SIP_CDRXSYNC(sc, x, ops) \ 355 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 356 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 357 358 #ifdef DP83820 359 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 360 #define SIP_RXBUF_LEN (MCLBYTES - 4) 361 #else 362 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 363 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 364 #endif 365 #define SIP_INIT_RXDESC(sc, x) \ 366 do { \ 367 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 368 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 369 \ 370 __sipd->sipd_link = \ 371 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 372 __sipd->sipd_bufptr = \ 373 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 374 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 375 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 376 SIP_INIT_RXDESC_EXTSTS \ 377 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 378 } while (0) 379 380 #define SIP_CHIP_VERS(sc, v, p, r) \ 381 ((sc)->sc_model->sip_vendor == (v) && \ 382 (sc)->sc_model->sip_product == (p) && \ 383 (sc)->sc_rev == (r)) 384 385 #define SIP_CHIP_MODEL(sc, v, p) \ 386 ((sc)->sc_model->sip_vendor == (v) && \ 387 (sc)->sc_model->sip_product == (p)) 388 389 #if !defined(DP83820) 390 #define SIP_SIS900_REV(sc, rev) \ 391 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 392 #endif 393 394 #define SIP_TIMEOUT 1000 395 396 void SIP_DECL(start)(struct ifnet *); 397 void SIP_DECL(watchdog)(struct ifnet *); 398 int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 399 int SIP_DECL(init)(struct ifnet *); 400 void SIP_DECL(stop)(struct ifnet *, int); 401 402 void SIP_DECL(shutdown)(void *); 403 404 void SIP_DECL(reset)(struct sip_softc *); 405 void SIP_DECL(rxdrain)(struct sip_softc *); 406 int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 407 void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, u_int16_t *); 408 void SIP_DECL(tick)(void *); 409 410 #if !defined(DP83820) 411 void SIP_DECL(sis900_set_filter)(struct sip_softc *); 412 #endif /* ! DP83820 */ 413 void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 414 415 #if defined(DP83820) 416 void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 417 const struct pci_attach_args *, u_int8_t *); 418 #else 419 void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 420 const struct pci_attach_args *, u_int8_t *); 421 void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 422 const struct pci_attach_args *, u_int8_t *); 423 #endif /* DP83820 */ 424 425 int SIP_DECL(intr)(void *); 426 void SIP_DECL(txintr)(struct sip_softc *); 427 void SIP_DECL(rxintr)(struct sip_softc *); 428 429 #if defined(DP83820) 430 int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 431 void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 432 void SIP_DECL(dp83820_mii_statchg)(struct device *); 433 #else 434 int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 435 void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 436 void SIP_DECL(sis900_mii_statchg)(struct device *); 437 438 int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 439 void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 440 void SIP_DECL(dp83815_mii_statchg)(struct device *); 441 #endif /* DP83820 */ 442 443 int SIP_DECL(mediachange)(struct ifnet *); 444 void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 445 446 int SIP_DECL(match)(struct device *, struct cfdata *, void *); 447 void SIP_DECL(attach)(struct device *, struct device *, void *); 448 449 int SIP_DECL(copy_small) = 0; 450 451 struct cfattach SIP_DECL(ca) = { 452 sizeof(struct sip_softc), SIP_DECL(match), SIP_DECL(attach), 453 }; 454 455 /* 456 * Descriptions of the variants of the SiS900. 457 */ 458 struct sip_variant { 459 int (*sipv_mii_readreg)(struct device *, int, int); 460 void (*sipv_mii_writereg)(struct device *, int, int, int); 461 void (*sipv_mii_statchg)(struct device *); 462 void (*sipv_set_filter)(struct sip_softc *); 463 void (*sipv_read_macaddr)(struct sip_softc *, 464 const struct pci_attach_args *, u_int8_t *); 465 }; 466 467 #if defined(DP83820) 468 u_int32_t SIP_DECL(dp83820_mii_bitbang_read)(struct device *); 469 void SIP_DECL(dp83820_mii_bitbang_write)(struct device *, u_int32_t); 470 471 const struct mii_bitbang_ops SIP_DECL(dp83820_mii_bitbang_ops) = { 472 SIP_DECL(dp83820_mii_bitbang_read), 473 SIP_DECL(dp83820_mii_bitbang_write), 474 { 475 EROMAR_MDIO, /* MII_BIT_MDO */ 476 EROMAR_MDIO, /* MII_BIT_MDI */ 477 EROMAR_MDC, /* MII_BIT_MDC */ 478 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 479 0, /* MII_BIT_DIR_PHY_HOST */ 480 } 481 }; 482 #endif /* DP83820 */ 483 484 #if defined(DP83820) 485 const struct sip_variant SIP_DECL(variant_dp83820) = { 486 SIP_DECL(dp83820_mii_readreg), 487 SIP_DECL(dp83820_mii_writereg), 488 SIP_DECL(dp83820_mii_statchg), 489 SIP_DECL(dp83815_set_filter), 490 SIP_DECL(dp83820_read_macaddr), 491 }; 492 #else 493 const struct sip_variant SIP_DECL(variant_sis900) = { 494 SIP_DECL(sis900_mii_readreg), 495 SIP_DECL(sis900_mii_writereg), 496 SIP_DECL(sis900_mii_statchg), 497 SIP_DECL(sis900_set_filter), 498 SIP_DECL(sis900_read_macaddr), 499 }; 500 501 const struct sip_variant SIP_DECL(variant_dp83815) = { 502 SIP_DECL(dp83815_mii_readreg), 503 SIP_DECL(dp83815_mii_writereg), 504 SIP_DECL(dp83815_mii_statchg), 505 SIP_DECL(dp83815_set_filter), 506 SIP_DECL(dp83815_read_macaddr), 507 }; 508 #endif /* DP83820 */ 509 510 /* 511 * Devices supported by this driver. 512 */ 513 const struct sip_product { 514 pci_vendor_id_t sip_vendor; 515 pci_product_id_t sip_product; 516 const char *sip_name; 517 const struct sip_variant *sip_variant; 518 } SIP_DECL(products)[] = { 519 #if defined(DP83820) 520 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 521 "NatSemi DP83820 Gigabit Ethernet", 522 &SIP_DECL(variant_dp83820) }, 523 #else 524 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 525 "SiS 900 10/100 Ethernet", 526 &SIP_DECL(variant_sis900) }, 527 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 528 "SiS 7016 10/100 Ethernet", 529 &SIP_DECL(variant_sis900) }, 530 531 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 532 "NatSemi DP83815 10/100 Ethernet", 533 &SIP_DECL(variant_dp83815) }, 534 #endif /* DP83820 */ 535 536 { 0, 0, 537 NULL, 538 NULL }, 539 }; 540 541 static const struct sip_product * 542 SIP_DECL(lookup)(const struct pci_attach_args *pa) 543 { 544 const struct sip_product *sip; 545 546 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 547 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 548 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 549 return (sip); 550 } 551 return (NULL); 552 } 553 554 int 555 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 556 { 557 struct pci_attach_args *pa = aux; 558 559 if (SIP_DECL(lookup)(pa) != NULL) 560 return (1); 561 562 return (0); 563 } 564 565 void 566 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 567 { 568 struct sip_softc *sc = (struct sip_softc *) self; 569 struct pci_attach_args *pa = aux; 570 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 571 pci_chipset_tag_t pc = pa->pa_pc; 572 pci_intr_handle_t ih; 573 const char *intrstr = NULL; 574 bus_space_tag_t iot, memt; 575 bus_space_handle_t ioh, memh; 576 bus_dma_segment_t seg; 577 int ioh_valid, memh_valid; 578 int i, rseg, error; 579 const struct sip_product *sip; 580 pcireg_t pmode; 581 u_int8_t enaddr[ETHER_ADDR_LEN]; 582 int pmreg; 583 #ifdef DP83820 584 pcireg_t memtype; 585 u_int32_t reg; 586 #endif /* DP83820 */ 587 588 callout_init(&sc->sc_tick_ch); 589 590 sip = SIP_DECL(lookup)(pa); 591 if (sip == NULL) { 592 printf("\n"); 593 panic(SIP_STR(attach) ": impossible"); 594 } 595 sc->sc_rev = PCI_REVISION(pa->pa_class); 596 597 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 598 599 sc->sc_model = sip; 600 601 /* 602 * XXX Work-around broken PXE firmware on some boards. 603 * 604 * The DP83815 shares an address decoder with the MEM BAR 605 * and the ROM BAR. Make sure the ROM BAR is disabled, 606 * so that memory mapped access works. 607 */ 608 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 609 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 610 ~PCI_MAPREG_ROM_ENABLE); 611 612 /* 613 * Map the device. 614 */ 615 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 616 PCI_MAPREG_TYPE_IO, 0, 617 &iot, &ioh, NULL, NULL) == 0); 618 #ifdef DP83820 619 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 620 switch (memtype) { 621 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 622 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 623 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 624 memtype, 0, &memt, &memh, NULL, NULL) == 0); 625 break; 626 default: 627 memh_valid = 0; 628 } 629 #else 630 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 631 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 632 &memt, &memh, NULL, NULL) == 0); 633 #endif /* DP83820 */ 634 635 if (memh_valid) { 636 sc->sc_st = memt; 637 sc->sc_sh = memh; 638 } else if (ioh_valid) { 639 sc->sc_st = iot; 640 sc->sc_sh = ioh; 641 } else { 642 printf("%s: unable to map device registers\n", 643 sc->sc_dev.dv_xname); 644 return; 645 } 646 647 sc->sc_dmat = pa->pa_dmat; 648 649 /* 650 * Make sure bus mastering is enabled. Also make sure 651 * Write/Invalidate is enabled if we're allowed to use it. 652 */ 653 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 654 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 655 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 656 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 657 pmreg | PCI_COMMAND_MASTER_ENABLE); 658 659 /* Get it out of power save mode if needed. */ 660 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 661 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 662 if (pmode == 3) { 663 /* 664 * The card has lost all configuration data in 665 * this state, so punt. 666 */ 667 printf("%s: unable to wake up from power state D3\n", 668 sc->sc_dev.dv_xname); 669 return; 670 } 671 if (pmode != 0) { 672 printf("%s: waking up from power state D%d\n", 673 sc->sc_dev.dv_xname, pmode); 674 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 675 } 676 } 677 678 /* 679 * Map and establish our interrupt. 680 */ 681 if (pci_intr_map(pa, &ih)) { 682 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 683 return; 684 } 685 intrstr = pci_intr_string(pc, ih); 686 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 687 if (sc->sc_ih == NULL) { 688 printf("%s: unable to establish interrupt", 689 sc->sc_dev.dv_xname); 690 if (intrstr != NULL) 691 printf(" at %s", intrstr); 692 printf("\n"); 693 return; 694 } 695 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 696 697 SIMPLEQ_INIT(&sc->sc_txfreeq); 698 SIMPLEQ_INIT(&sc->sc_txdirtyq); 699 700 /* 701 * Allocate the control data structures, and create and load the 702 * DMA map for it. 703 */ 704 if ((error = bus_dmamem_alloc(sc->sc_dmat, 705 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 706 0)) != 0) { 707 printf("%s: unable to allocate control data, error = %d\n", 708 sc->sc_dev.dv_xname, error); 709 goto fail_0; 710 } 711 712 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 713 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 714 BUS_DMA_COHERENT)) != 0) { 715 printf("%s: unable to map control data, error = %d\n", 716 sc->sc_dev.dv_xname, error); 717 goto fail_1; 718 } 719 720 if ((error = bus_dmamap_create(sc->sc_dmat, 721 sizeof(struct sip_control_data), 1, 722 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 723 printf("%s: unable to create control data DMA map, " 724 "error = %d\n", sc->sc_dev.dv_xname, error); 725 goto fail_2; 726 } 727 728 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 729 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 730 0)) != 0) { 731 printf("%s: unable to load control data DMA map, error = %d\n", 732 sc->sc_dev.dv_xname, error); 733 goto fail_3; 734 } 735 736 /* 737 * Create the transmit buffer DMA maps. 738 */ 739 for (i = 0; i < SIP_TXQUEUELEN; i++) { 740 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 741 SIP_NTXSEGS, MCLBYTES, 0, 0, 742 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 743 printf("%s: unable to create tx DMA map %d, " 744 "error = %d\n", sc->sc_dev.dv_xname, i, error); 745 goto fail_4; 746 } 747 } 748 749 /* 750 * Create the receive buffer DMA maps. 751 */ 752 for (i = 0; i < SIP_NRXDESC; i++) { 753 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 754 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 755 printf("%s: unable to create rx DMA map %d, " 756 "error = %d\n", sc->sc_dev.dv_xname, i, error); 757 goto fail_5; 758 } 759 sc->sc_rxsoft[i].rxs_mbuf = NULL; 760 } 761 762 /* 763 * Reset the chip to a known state. 764 */ 765 SIP_DECL(reset)(sc); 766 767 /* 768 * Read the Ethernet address from the EEPROM. This might 769 * also fetch other stuff from the EEPROM and stash it 770 * in the softc. 771 */ 772 sc->sc_cfg = 0; 773 #if !defined(DP83820) 774 if (SIP_SIS900_REV(sc,SIS_REV_635) || 775 SIP_SIS900_REV(sc,SIS_REV_900B)) 776 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 777 #endif 778 779 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 780 781 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 782 ether_sprintf(enaddr)); 783 784 /* 785 * Initialize the configuration register: aggressive PCI 786 * bus request algorithm, default backoff, default OW timer, 787 * default parity error detection. 788 * 789 * NOTE: "Big endian mode" is useless on the SiS900 and 790 * friends -- it affects packet data, not descriptors. 791 */ 792 #ifdef DP83820 793 /* 794 * XXX Need some PCI flags indicating support for 795 * XXX 64-bit addressing. 796 */ 797 sc->sc_cfg &= ~(CFG_M64ADDR | CFG_T64ADDR); 798 799 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 800 if (reg & CFG_PCI64_DET) { 801 printf("%s: 64-bit PCI slot detected\n", sc->sc_dev.dv_xname); 802 if ((sc->sc_cfg & CFG_DATA64_EN) == 0) 803 printf("%s: 64-bit data transfers disabled in EEPROM\n", 804 sc->sc_dev.dv_xname); 805 } else 806 sc->sc_cfg &= ~CFG_DATA64_EN; 807 808 if (sc->sc_cfg & (CFG_TBI_EN|CFG_EXT_125)) { 809 const char *sep = ""; 810 printf("%s: using ", sc->sc_dev.dv_xname); 811 if (sc->sc_cfg & CFG_EXT_125) { 812 printf("%s125MHz clock", sep); 813 sep = ", "; 814 } 815 if (sc->sc_cfg & CFG_TBI_EN) { 816 printf("%sten-bit interface", sep); 817 sep = ", "; 818 } 819 printf("\n"); 820 } 821 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0) 822 sc->sc_cfg |= CFG_MRM_DIS; 823 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 824 sc->sc_cfg |= CFG_MWI_DIS; 825 826 /* 827 * Use the extended descriptor format on the DP83820. This 828 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 829 * checksumming. 830 */ 831 sc->sc_cfg |= CFG_EXTSTS_EN; 832 #endif /* DP83820 */ 833 834 /* 835 * Initialize our media structures and probe the MII. 836 */ 837 sc->sc_mii.mii_ifp = ifp; 838 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 839 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 840 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 841 ifmedia_init(&sc->sc_mii.mii_media, 0, SIP_DECL(mediachange), 842 SIP_DECL(mediastatus)); 843 #ifdef DP83820 844 if (sc->sc_cfg & CFG_TBI_EN) { 845 /* Using ten-bit interface. */ 846 printf("%s: TBI -- FIXME\n", sc->sc_dev.dv_xname); 847 } else { 848 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 849 MII_OFFSET_ANY, 0); 850 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 851 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 852 0, NULL); 853 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 854 } else 855 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 856 } 857 #else 858 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 859 MII_OFFSET_ANY, 0); 860 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 861 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 862 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 863 } else 864 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 865 #endif /* DP83820 */ 866 867 ifp = &sc->sc_ethercom.ec_if; 868 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 869 ifp->if_softc = sc; 870 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 871 ifp->if_ioctl = SIP_DECL(ioctl); 872 ifp->if_start = SIP_DECL(start); 873 ifp->if_watchdog = SIP_DECL(watchdog); 874 ifp->if_init = SIP_DECL(init); 875 ifp->if_stop = SIP_DECL(stop); 876 IFQ_SET_READY(&ifp->if_snd); 877 878 /* 879 * We can support 802.1Q VLAN-sized frames. 880 */ 881 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 882 883 #ifdef DP83820 884 /* 885 * And the DP83820 can do VLAN tagging in hardware, and 886 * support the jumbo Ethernet MTU. 887 */ 888 sc->sc_ethercom.ec_capabilities |= 889 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 890 891 /* 892 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 893 * in hardware. 894 */ 895 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 896 IFCAP_CSUM_UDPv4; 897 #endif /* DP83820 */ 898 899 /* 900 * Attach the interface. 901 */ 902 if_attach(ifp); 903 ether_ifattach(ifp, enaddr); 904 905 /* 906 * The number of bytes that must be available in 907 * the Tx FIFO before the bus master can DMA more 908 * data into the FIFO. 909 */ 910 sc->sc_tx_fill_thresh = 64 / 32; 911 912 /* 913 * Start at a drain threshold of 512 bytes. We will 914 * increase it if a DMA underrun occurs. 915 * 916 * XXX The minimum value of this variable should be 917 * tuned. We may be able to improve performance 918 * by starting with a lower value. That, however, 919 * may trash the first few outgoing packets if the 920 * PCI bus is saturated. 921 */ 922 sc->sc_tx_drain_thresh = 1504 / 32; 923 924 /* 925 * Initialize the Rx FIFO drain threshold. 926 * 927 * This is in units of 8 bytes. 928 * 929 * We should never set this value lower than 2; 14 bytes are 930 * required to filter the packet. 931 */ 932 sc->sc_rx_drain_thresh = 128 / 8; 933 934 #ifdef SIP_EVENT_COUNTERS 935 /* 936 * Attach event counters. 937 */ 938 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 939 NULL, sc->sc_dev.dv_xname, "txsstall"); 940 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 941 NULL, sc->sc_dev.dv_xname, "txdstall"); 942 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 943 NULL, sc->sc_dev.dv_xname, "txforceintr"); 944 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 945 NULL, sc->sc_dev.dv_xname, "txdintr"); 946 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 947 NULL, sc->sc_dev.dv_xname, "txiintr"); 948 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 949 NULL, sc->sc_dev.dv_xname, "rxintr"); 950 #ifdef DP83820 951 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 952 NULL, sc->sc_dev.dv_xname, "rxipsum"); 953 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 954 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 955 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 956 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 957 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 958 NULL, sc->sc_dev.dv_xname, "txipsum"); 959 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 960 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 961 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 962 NULL, sc->sc_dev.dv_xname, "txudpsum"); 963 #endif /* DP83820 */ 964 #endif /* SIP_EVENT_COUNTERS */ 965 966 /* 967 * Make sure the interface is shutdown during reboot. 968 */ 969 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 970 if (sc->sc_sdhook == NULL) 971 printf("%s: WARNING: unable to establish shutdown hook\n", 972 sc->sc_dev.dv_xname); 973 return; 974 975 /* 976 * Free any resources we've allocated during the failed attach 977 * attempt. Do this in reverse order and fall through. 978 */ 979 fail_5: 980 for (i = 0; i < SIP_NRXDESC; i++) { 981 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 982 bus_dmamap_destroy(sc->sc_dmat, 983 sc->sc_rxsoft[i].rxs_dmamap); 984 } 985 fail_4: 986 for (i = 0; i < SIP_TXQUEUELEN; i++) { 987 if (sc->sc_txsoft[i].txs_dmamap != NULL) 988 bus_dmamap_destroy(sc->sc_dmat, 989 sc->sc_txsoft[i].txs_dmamap); 990 } 991 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 992 fail_3: 993 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 994 fail_2: 995 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 996 sizeof(struct sip_control_data)); 997 fail_1: 998 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 999 fail_0: 1000 return; 1001 } 1002 1003 /* 1004 * sip_shutdown: 1005 * 1006 * Make sure the interface is stopped at reboot time. 1007 */ 1008 void 1009 SIP_DECL(shutdown)(void *arg) 1010 { 1011 struct sip_softc *sc = arg; 1012 1013 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1014 } 1015 1016 /* 1017 * sip_start: [ifnet interface function] 1018 * 1019 * Start packet transmission on the interface. 1020 */ 1021 void 1022 SIP_DECL(start)(struct ifnet *ifp) 1023 { 1024 struct sip_softc *sc = ifp->if_softc; 1025 struct mbuf *m0, *m; 1026 struct sip_txsoft *txs; 1027 bus_dmamap_t dmamap; 1028 int error, nexttx, lasttx, seg; 1029 int ofree = sc->sc_txfree; 1030 #if 0 1031 int firsttx = sc->sc_txnext; 1032 #endif 1033 #ifdef DP83820 1034 u_int32_t extsts; 1035 #endif 1036 1037 /* 1038 * If we've been told to pause, don't transmit any more packets. 1039 */ 1040 if (sc->sc_flags & SIPF_PAUSED) 1041 ifp->if_flags |= IFF_OACTIVE; 1042 1043 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1044 return; 1045 1046 /* 1047 * Loop through the send queue, setting up transmit descriptors 1048 * until we drain the queue, or use up all available transmit 1049 * descriptors. 1050 */ 1051 for (;;) { 1052 /* Get a work queue entry. */ 1053 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1054 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1055 break; 1056 } 1057 1058 /* 1059 * Grab a packet off the queue. 1060 */ 1061 IFQ_POLL(&ifp->if_snd, m0); 1062 if (m0 == NULL) 1063 break; 1064 #ifndef DP83820 1065 m = NULL; 1066 #endif 1067 1068 dmamap = txs->txs_dmamap; 1069 1070 #ifdef DP83820 1071 /* 1072 * Load the DMA map. If this fails, the packet either 1073 * didn't fit in the allotted number of segments, or we 1074 * were short on resources. For the too-many-segments 1075 * case, we simply report an error and drop the packet, 1076 * since we can't sanely copy a jumbo packet to a single 1077 * buffer. 1078 */ 1079 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1080 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1081 if (error) { 1082 if (error == EFBIG) { 1083 printf("%s: Tx packet consumes too many " 1084 "DMA segments, dropping...\n", 1085 sc->sc_dev.dv_xname); 1086 IFQ_DEQUEUE(&ifp->if_snd, m0); 1087 m_freem(m0); 1088 continue; 1089 } 1090 /* 1091 * Short on resources, just stop for now. 1092 */ 1093 break; 1094 } 1095 #else /* DP83820 */ 1096 /* 1097 * Load the DMA map. If this fails, the packet either 1098 * didn't fit in the alloted number of segments, or we 1099 * were short on resources. In this case, we'll copy 1100 * and try again. 1101 */ 1102 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1103 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1104 MGETHDR(m, M_DONTWAIT, MT_DATA); 1105 if (m == NULL) { 1106 printf("%s: unable to allocate Tx mbuf\n", 1107 sc->sc_dev.dv_xname); 1108 break; 1109 } 1110 if (m0->m_pkthdr.len > MHLEN) { 1111 MCLGET(m, M_DONTWAIT); 1112 if ((m->m_flags & M_EXT) == 0) { 1113 printf("%s: unable to allocate Tx " 1114 "cluster\n", sc->sc_dev.dv_xname); 1115 m_freem(m); 1116 break; 1117 } 1118 } 1119 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1120 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1121 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1122 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1123 if (error) { 1124 printf("%s: unable to load Tx buffer, " 1125 "error = %d\n", sc->sc_dev.dv_xname, error); 1126 break; 1127 } 1128 } 1129 #endif /* DP83820 */ 1130 1131 /* 1132 * Ensure we have enough descriptors free to describe 1133 * the packet. Note, we always reserve one descriptor 1134 * at the end of the ring as a termination point, to 1135 * prevent wrap-around. 1136 */ 1137 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1138 /* 1139 * Not enough free descriptors to transmit this 1140 * packet. We haven't committed anything yet, 1141 * so just unload the DMA map, put the packet 1142 * back on the queue, and punt. Notify the upper 1143 * layer that there are not more slots left. 1144 * 1145 * XXX We could allocate an mbuf and copy, but 1146 * XXX is it worth it? 1147 */ 1148 ifp->if_flags |= IFF_OACTIVE; 1149 bus_dmamap_unload(sc->sc_dmat, dmamap); 1150 #ifndef DP83820 1151 if (m != NULL) 1152 m_freem(m); 1153 #endif 1154 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1155 break; 1156 } 1157 1158 IFQ_DEQUEUE(&ifp->if_snd, m0); 1159 #ifndef DP83820 1160 if (m != NULL) { 1161 m_freem(m0); 1162 m0 = m; 1163 } 1164 #endif 1165 1166 /* 1167 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1168 */ 1169 1170 /* Sync the DMA map. */ 1171 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1172 BUS_DMASYNC_PREWRITE); 1173 1174 /* 1175 * Initialize the transmit descriptors. 1176 */ 1177 for (nexttx = sc->sc_txnext, seg = 0; 1178 seg < dmamap->dm_nsegs; 1179 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1180 /* 1181 * If this is the first descriptor we're 1182 * enqueueing, don't set the OWN bit just 1183 * yet. That could cause a race condition. 1184 * We'll do it below. 1185 */ 1186 sc->sc_txdescs[nexttx].sipd_bufptr = 1187 htole32(dmamap->dm_segs[seg].ds_addr); 1188 sc->sc_txdescs[nexttx].sipd_cmdsts = 1189 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1190 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1191 #ifdef DP83820 1192 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1193 #endif /* DP83820 */ 1194 lasttx = nexttx; 1195 } 1196 1197 /* Clear the MORE bit on the last segment. */ 1198 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1199 1200 /* 1201 * If we're in the interrupt delay window, delay the 1202 * interrupt. 1203 */ 1204 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1205 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1206 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1207 htole32(CMDSTS_INTR); 1208 sc->sc_txwin = 0; 1209 } 1210 1211 #ifdef DP83820 1212 /* 1213 * If VLANs are enabled and the packet has a VLAN tag, set 1214 * up the descriptor to encapsulate the packet for us. 1215 * 1216 * This apparently has to be on the last descriptor of 1217 * the packet. 1218 */ 1219 if (sc->sc_ethercom.ec_nvlans != 0 && 1220 (m = m_aux_find(m0, AF_LINK, ETHERTYPE_VLAN)) != NULL) { 1221 sc->sc_txdescs[lasttx].sipd_extsts |= 1222 htole32(EXTSTS_VPKT | 1223 htons(*mtod(m, int *) & EXTSTS_VTCI)); 1224 } 1225 1226 /* 1227 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1228 * checksumming, set up the descriptor to do this work 1229 * for us. 1230 * 1231 * This apparently has to be on the first descriptor of 1232 * the packet. 1233 * 1234 * Byte-swap constants so the compiler can optimize. 1235 */ 1236 extsts = 0; 1237 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1238 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1239 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1240 extsts |= htole32(EXTSTS_IPPKT); 1241 } 1242 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1243 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1244 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1245 extsts |= htole32(EXTSTS_TCPPKT); 1246 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1247 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1248 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1249 extsts |= htole32(EXTSTS_UDPPKT); 1250 } 1251 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1252 #endif /* DP83820 */ 1253 1254 /* Sync the descriptors we're using. */ 1255 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1256 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1257 1258 /* 1259 * The entire packet is set up. Give the first descrptor 1260 * to the chip now. 1261 */ 1262 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1263 htole32(CMDSTS_OWN); 1264 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1265 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1266 1267 /* 1268 * Store a pointer to the packet so we can free it later, 1269 * and remember what txdirty will be once the packet is 1270 * done. 1271 */ 1272 txs->txs_mbuf = m0; 1273 txs->txs_firstdesc = sc->sc_txnext; 1274 txs->txs_lastdesc = lasttx; 1275 1276 /* Advance the tx pointer. */ 1277 sc->sc_txfree -= dmamap->dm_nsegs; 1278 sc->sc_txnext = nexttx; 1279 1280 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1281 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1282 1283 #if NBPFILTER > 0 1284 /* 1285 * Pass the packet to any BPF listeners. 1286 */ 1287 if (ifp->if_bpf) 1288 bpf_mtap(ifp->if_bpf, m0); 1289 #endif /* NBPFILTER > 0 */ 1290 } 1291 1292 if (txs == NULL || sc->sc_txfree == 0) { 1293 /* No more slots left; notify upper layer. */ 1294 ifp->if_flags |= IFF_OACTIVE; 1295 } 1296 1297 if (sc->sc_txfree != ofree) { 1298 /* 1299 * Start the transmit process. Note, the manual says 1300 * that if there are no pending transmissions in the 1301 * chip's internal queue (indicated by TXE being clear), 1302 * then the driver software must set the TXDP to the 1303 * first descriptor to be transmitted. However, if we 1304 * do this, it causes serious performance degredation on 1305 * the DP83820 under load, not setting TXDP doesn't seem 1306 * to adversely affect the SiS 900 or DP83815. 1307 * 1308 * Well, I guess it wouldn't be the first time a manual 1309 * has lied -- and they could be speaking of the NULL- 1310 * terminated descriptor list case, rather than OWN- 1311 * terminated rings. 1312 */ 1313 #if 0 1314 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1315 CR_TXE) == 0) { 1316 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1317 SIP_CDTXADDR(sc, firsttx)); 1318 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1319 } 1320 #else 1321 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1322 #endif 1323 1324 /* Set a watchdog timer in case the chip flakes out. */ 1325 ifp->if_timer = 5; 1326 } 1327 } 1328 1329 /* 1330 * sip_watchdog: [ifnet interface function] 1331 * 1332 * Watchdog timer handler. 1333 */ 1334 void 1335 SIP_DECL(watchdog)(struct ifnet *ifp) 1336 { 1337 struct sip_softc *sc = ifp->if_softc; 1338 1339 /* 1340 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1341 * If we get a timeout, try and sweep up transmit descriptors. 1342 * If we manage to sweep them all up, ignore the lack of 1343 * interrupt. 1344 */ 1345 SIP_DECL(txintr)(sc); 1346 1347 if (sc->sc_txfree != SIP_NTXDESC) { 1348 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1349 ifp->if_oerrors++; 1350 1351 /* Reset the interface. */ 1352 (void) SIP_DECL(init)(ifp); 1353 } else if (ifp->if_flags & IFF_DEBUG) 1354 printf("%s: recovered from device timeout\n", 1355 sc->sc_dev.dv_xname); 1356 1357 /* Try to get more packets going. */ 1358 SIP_DECL(start)(ifp); 1359 } 1360 1361 /* 1362 * sip_ioctl: [ifnet interface function] 1363 * 1364 * Handle control requests from the operator. 1365 */ 1366 int 1367 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1368 { 1369 struct sip_softc *sc = ifp->if_softc; 1370 struct ifreq *ifr = (struct ifreq *)data; 1371 int s, error; 1372 1373 s = splnet(); 1374 1375 switch (cmd) { 1376 case SIOCSIFMEDIA: 1377 case SIOCGIFMEDIA: 1378 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1379 break; 1380 1381 default: 1382 error = ether_ioctl(ifp, cmd, data); 1383 if (error == ENETRESET) { 1384 /* 1385 * Multicast list has changed; set the hardware filter 1386 * accordingly. 1387 */ 1388 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1389 error = 0; 1390 } 1391 break; 1392 } 1393 1394 /* Try to get more packets going. */ 1395 SIP_DECL(start)(ifp); 1396 1397 splx(s); 1398 return (error); 1399 } 1400 1401 /* 1402 * sip_intr: 1403 * 1404 * Interrupt service routine. 1405 */ 1406 int 1407 SIP_DECL(intr)(void *arg) 1408 { 1409 struct sip_softc *sc = arg; 1410 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1411 u_int32_t isr; 1412 int handled = 0; 1413 1414 for (;;) { 1415 /* Reading clears interrupt. */ 1416 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1417 if ((isr & sc->sc_imr) == 0) 1418 break; 1419 1420 handled = 1; 1421 1422 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1423 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1424 1425 /* Grab any new packets. */ 1426 SIP_DECL(rxintr)(sc); 1427 1428 if (isr & ISR_RXORN) { 1429 printf("%s: receive FIFO overrun\n", 1430 sc->sc_dev.dv_xname); 1431 1432 /* XXX adjust rx_drain_thresh? */ 1433 } 1434 1435 if (isr & ISR_RXIDLE) { 1436 printf("%s: receive ring overrun\n", 1437 sc->sc_dev.dv_xname); 1438 1439 /* Get the receive process going again. */ 1440 bus_space_write_4(sc->sc_st, sc->sc_sh, 1441 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1442 bus_space_write_4(sc->sc_st, sc->sc_sh, 1443 SIP_CR, CR_RXE); 1444 } 1445 } 1446 1447 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1448 #ifdef SIP_EVENT_COUNTERS 1449 if (isr & ISR_TXDESC) 1450 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1451 else if (isr & ISR_TXIDLE) 1452 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1453 #endif 1454 1455 /* Sweep up transmit descriptors. */ 1456 SIP_DECL(txintr)(sc); 1457 1458 if (isr & ISR_TXURN) { 1459 u_int32_t thresh; 1460 1461 printf("%s: transmit FIFO underrun", 1462 sc->sc_dev.dv_xname); 1463 1464 thresh = sc->sc_tx_drain_thresh + 1; 1465 if (thresh <= TXCFG_DRTH && 1466 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1467 (sc->sc_tx_fill_thresh * 32))) { 1468 printf("; increasing Tx drain " 1469 "threshold to %u bytes\n", 1470 thresh * 32); 1471 sc->sc_tx_drain_thresh = thresh; 1472 (void) SIP_DECL(init)(ifp); 1473 } else { 1474 (void) SIP_DECL(init)(ifp); 1475 printf("\n"); 1476 } 1477 } 1478 } 1479 1480 #if !defined(DP83820) 1481 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1482 if (isr & ISR_PAUSE_ST) { 1483 sc->sc_flags |= SIPF_PAUSED; 1484 ifp->if_flags |= IFF_OACTIVE; 1485 } 1486 if (isr & ISR_PAUSE_END) { 1487 sc->sc_flags &= ~SIPF_PAUSED; 1488 ifp->if_flags &= ~IFF_OACTIVE; 1489 } 1490 } 1491 #endif /* ! DP83820 */ 1492 1493 if (isr & ISR_HIBERR) { 1494 #define PRINTERR(bit, str) \ 1495 if (isr & (bit)) \ 1496 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1497 PRINTERR(ISR_DPERR, "parity error"); 1498 PRINTERR(ISR_SSERR, "system error"); 1499 PRINTERR(ISR_RMABT, "master abort"); 1500 PRINTERR(ISR_RTABT, "target abort"); 1501 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1502 (void) SIP_DECL(init)(ifp); 1503 #undef PRINTERR 1504 } 1505 } 1506 1507 /* Try to get more packets going. */ 1508 SIP_DECL(start)(ifp); 1509 1510 return (handled); 1511 } 1512 1513 /* 1514 * sip_txintr: 1515 * 1516 * Helper; handle transmit interrupts. 1517 */ 1518 void 1519 SIP_DECL(txintr)(struct sip_softc *sc) 1520 { 1521 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1522 struct sip_txsoft *txs; 1523 u_int32_t cmdsts; 1524 1525 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1526 ifp->if_flags &= ~IFF_OACTIVE; 1527 1528 /* 1529 * Go through our Tx list and free mbufs for those 1530 * frames which have been transmitted. 1531 */ 1532 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1533 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1534 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1535 1536 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1537 if (cmdsts & CMDSTS_OWN) 1538 break; 1539 1540 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1541 1542 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1543 1544 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1545 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1546 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1547 m_freem(txs->txs_mbuf); 1548 txs->txs_mbuf = NULL; 1549 1550 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1551 1552 /* 1553 * Check for errors and collisions. 1554 */ 1555 if (cmdsts & 1556 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1557 ifp->if_oerrors++; 1558 if (cmdsts & CMDSTS_Tx_EC) 1559 ifp->if_collisions += 16; 1560 if (ifp->if_flags & IFF_DEBUG) { 1561 if (cmdsts & CMDSTS_Tx_ED) 1562 printf("%s: excessive deferral\n", 1563 sc->sc_dev.dv_xname); 1564 if (cmdsts & CMDSTS_Tx_EC) 1565 printf("%s: excessive collisions\n", 1566 sc->sc_dev.dv_xname); 1567 } 1568 } else { 1569 /* Packet was transmitted successfully. */ 1570 ifp->if_opackets++; 1571 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1572 } 1573 } 1574 1575 /* 1576 * If there are no more pending transmissions, cancel the watchdog 1577 * timer. 1578 */ 1579 if (txs == NULL) { 1580 ifp->if_timer = 0; 1581 sc->sc_txwin = 0; 1582 } 1583 } 1584 1585 #if defined(DP83820) 1586 /* 1587 * sip_rxintr: 1588 * 1589 * Helper; handle receive interrupts. 1590 */ 1591 void 1592 SIP_DECL(rxintr)(struct sip_softc *sc) 1593 { 1594 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1595 struct sip_rxsoft *rxs; 1596 struct mbuf *m, *tailm; 1597 u_int32_t cmdsts, extsts; 1598 int i, len; 1599 1600 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1601 rxs = &sc->sc_rxsoft[i]; 1602 1603 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1604 1605 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1606 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1607 1608 /* 1609 * NOTE: OWN is set if owned by _consumer_. We're the 1610 * consumer of the receive ring, so if the bit is clear, 1611 * we have processed all of the packets. 1612 */ 1613 if ((cmdsts & CMDSTS_OWN) == 0) { 1614 /* 1615 * We have processed all of the receive buffers. 1616 */ 1617 break; 1618 } 1619 1620 if (__predict_false(sc->sc_rxdiscard)) { 1621 SIP_INIT_RXDESC(sc, i); 1622 if ((cmdsts & CMDSTS_MORE) == 0) { 1623 /* Reset our state. */ 1624 sc->sc_rxdiscard = 0; 1625 } 1626 continue; 1627 } 1628 1629 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1630 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1631 1632 m = rxs->rxs_mbuf; 1633 1634 /* 1635 * Add a new receive buffer to the ring. 1636 */ 1637 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1638 /* 1639 * Failed, throw away what we've done so 1640 * far, and discard the rest of the packet. 1641 */ 1642 ifp->if_ierrors++; 1643 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1644 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1645 SIP_INIT_RXDESC(sc, i); 1646 if (cmdsts & CMDSTS_MORE) 1647 sc->sc_rxdiscard = 1; 1648 if (sc->sc_rxhead != NULL) 1649 m_freem(sc->sc_rxhead); 1650 SIP_RXCHAIN_RESET(sc); 1651 continue; 1652 } 1653 1654 SIP_RXCHAIN_LINK(sc, m); 1655 1656 /* 1657 * If this is not the end of the packet, keep 1658 * looking. 1659 */ 1660 if (cmdsts & CMDSTS_MORE) { 1661 sc->sc_rxlen += m->m_len; 1662 continue; 1663 } 1664 1665 /* 1666 * Okay, we have the entire packet now... 1667 */ 1668 *sc->sc_rxtailp = NULL; 1669 m = sc->sc_rxhead; 1670 tailm = sc->sc_rxtail; 1671 1672 SIP_RXCHAIN_RESET(sc); 1673 1674 /* 1675 * If an error occurred, update stats and drop the packet. 1676 */ 1677 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1678 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1679 ifp->if_ierrors++; 1680 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1681 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1682 /* Receive overrun handled elsewhere. */ 1683 printf("%s: receive descriptor error\n", 1684 sc->sc_dev.dv_xname); 1685 } 1686 #define PRINTERR(bit, str) \ 1687 if (cmdsts & (bit)) \ 1688 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1689 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1690 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1691 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1692 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1693 #undef PRINTERR 1694 m_freem(m); 1695 continue; 1696 } 1697 1698 /* 1699 * No errors. 1700 * 1701 * Note, the DP83820 includes the CRC with 1702 * every packet. 1703 */ 1704 len = CMDSTS_SIZE(cmdsts); 1705 tailm->m_len = len - sc->sc_rxlen; 1706 1707 /* 1708 * If the packet is small enough to fit in a 1709 * single header mbuf, allocate one and copy 1710 * the data into it. This greatly reduces 1711 * memory consumption when we receive lots 1712 * of small packets. 1713 */ 1714 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1715 struct mbuf *nm; 1716 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1717 if (nm == NULL) { 1718 ifp->if_ierrors++; 1719 m_freem(m); 1720 continue; 1721 } 1722 nm->m_data += 2; 1723 nm->m_pkthdr.len = nm->m_len = len; 1724 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1725 m_freem(m); 1726 m = nm; 1727 } 1728 #ifndef __NO_STRICT_ALIGNMENT 1729 else { 1730 /* 1731 * The DP83820's receive buffers must be 4-byte 1732 * aligned. But this means that the data after 1733 * the Ethernet header is misaligned. To compensate, 1734 * we have artificially shortened the buffer size 1735 * in the descriptor, and we do an overlapping copy 1736 * of the data two bytes further in (in the first 1737 * buffer of the chain only). 1738 */ 1739 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1740 m->m_len); 1741 m->m_data += 2; 1742 } 1743 #endif /* ! __NO_STRICT_ALIGNMENT */ 1744 1745 /* 1746 * If VLANs are enabled, VLAN packets have been unwrapped 1747 * for us. Associate the tag with the packet. 1748 */ 1749 if (sc->sc_ethercom.ec_nvlans != 0 && 1750 (extsts & EXTSTS_VPKT) != 0) { 1751 struct mbuf *vtag; 1752 1753 vtag = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 1754 if (vtag == NULL) { 1755 ifp->if_ierrors++; 1756 printf("%s: unable to allocate VLAN tag\n", 1757 sc->sc_dev.dv_xname); 1758 m_freem(m); 1759 continue; 1760 } 1761 1762 *mtod(vtag, int *) = ntohs(extsts & EXTSTS_VTCI); 1763 vtag->m_len = sizeof(int); 1764 } 1765 1766 /* 1767 * Set the incoming checksum information for the 1768 * packet. 1769 */ 1770 if ((extsts & EXTSTS_IPPKT) != 0) { 1771 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1772 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1773 if (extsts & EXTSTS_Rx_IPERR) 1774 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1775 if (extsts & EXTSTS_TCPPKT) { 1776 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1777 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1778 if (extsts & EXTSTS_Rx_TCPERR) 1779 m->m_pkthdr.csum_flags |= 1780 M_CSUM_TCP_UDP_BAD; 1781 } else if (extsts & EXTSTS_UDPPKT) { 1782 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1783 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1784 if (extsts & EXTSTS_Rx_UDPERR) 1785 m->m_pkthdr.csum_flags |= 1786 M_CSUM_TCP_UDP_BAD; 1787 } 1788 } 1789 1790 ifp->if_ipackets++; 1791 m->m_flags |= M_HASFCS; 1792 m->m_pkthdr.rcvif = ifp; 1793 m->m_pkthdr.len = len; 1794 1795 #if NBPFILTER > 0 1796 /* 1797 * Pass this up to any BPF listeners, but only 1798 * pass if up the stack if it's for us. 1799 */ 1800 if (ifp->if_bpf) 1801 bpf_mtap(ifp->if_bpf, m); 1802 #endif /* NBPFILTER > 0 */ 1803 1804 /* Pass it on. */ 1805 (*ifp->if_input)(ifp, m); 1806 } 1807 1808 /* Update the receive pointer. */ 1809 sc->sc_rxptr = i; 1810 } 1811 #else /* ! DP83820 */ 1812 /* 1813 * sip_rxintr: 1814 * 1815 * Helper; handle receive interrupts. 1816 */ 1817 void 1818 SIP_DECL(rxintr)(struct sip_softc *sc) 1819 { 1820 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1821 struct sip_rxsoft *rxs; 1822 struct mbuf *m; 1823 u_int32_t cmdsts; 1824 int i, len; 1825 1826 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1827 rxs = &sc->sc_rxsoft[i]; 1828 1829 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1830 1831 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1832 1833 /* 1834 * NOTE: OWN is set if owned by _consumer_. We're the 1835 * consumer of the receive ring, so if the bit is clear, 1836 * we have processed all of the packets. 1837 */ 1838 if ((cmdsts & CMDSTS_OWN) == 0) { 1839 /* 1840 * We have processed all of the receive buffers. 1841 */ 1842 break; 1843 } 1844 1845 /* 1846 * If any collisions were seen on the wire, count one. 1847 */ 1848 if (cmdsts & CMDSTS_Rx_COL) 1849 ifp->if_collisions++; 1850 1851 /* 1852 * If an error occurred, update stats, clear the status 1853 * word, and leave the packet buffer in place. It will 1854 * simply be reused the next time the ring comes around. 1855 */ 1856 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1857 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1858 ifp->if_ierrors++; 1859 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1860 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1861 /* Receive overrun handled elsewhere. */ 1862 printf("%s: receive descriptor error\n", 1863 sc->sc_dev.dv_xname); 1864 } 1865 #define PRINTERR(bit, str) \ 1866 if (cmdsts & (bit)) \ 1867 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1868 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1869 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1870 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1871 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1872 #undef PRINTERR 1873 SIP_INIT_RXDESC(sc, i); 1874 continue; 1875 } 1876 1877 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1878 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1879 1880 /* 1881 * No errors; receive the packet. Note, the SiS 900 1882 * includes the CRC with every packet. 1883 */ 1884 len = CMDSTS_SIZE(cmdsts); 1885 1886 #ifdef __NO_STRICT_ALIGNMENT 1887 /* 1888 * If the packet is small enough to fit in a 1889 * single header mbuf, allocate one and copy 1890 * the data into it. This greatly reduces 1891 * memory consumption when we receive lots 1892 * of small packets. 1893 * 1894 * Otherwise, we add a new buffer to the receive 1895 * chain. If this fails, we drop the packet and 1896 * recycle the old buffer. 1897 */ 1898 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 1899 MGETHDR(m, M_DONTWAIT, MT_DATA); 1900 if (m == NULL) 1901 goto dropit; 1902 memcpy(mtod(m, caddr_t), 1903 mtod(rxs->rxs_mbuf, caddr_t), len); 1904 SIP_INIT_RXDESC(sc, i); 1905 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1906 rxs->rxs_dmamap->dm_mapsize, 1907 BUS_DMASYNC_PREREAD); 1908 } else { 1909 m = rxs->rxs_mbuf; 1910 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1911 dropit: 1912 ifp->if_ierrors++; 1913 SIP_INIT_RXDESC(sc, i); 1914 bus_dmamap_sync(sc->sc_dmat, 1915 rxs->rxs_dmamap, 0, 1916 rxs->rxs_dmamap->dm_mapsize, 1917 BUS_DMASYNC_PREREAD); 1918 continue; 1919 } 1920 } 1921 #else 1922 /* 1923 * The SiS 900's receive buffers must be 4-byte aligned. 1924 * But this means that the data after the Ethernet header 1925 * is misaligned. We must allocate a new buffer and 1926 * copy the data, shifted forward 2 bytes. 1927 */ 1928 MGETHDR(m, M_DONTWAIT, MT_DATA); 1929 if (m == NULL) { 1930 dropit: 1931 ifp->if_ierrors++; 1932 SIP_INIT_RXDESC(sc, i); 1933 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1934 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1935 continue; 1936 } 1937 if (len > (MHLEN - 2)) { 1938 MCLGET(m, M_DONTWAIT); 1939 if ((m->m_flags & M_EXT) == 0) { 1940 m_freem(m); 1941 goto dropit; 1942 } 1943 } 1944 m->m_data += 2; 1945 1946 /* 1947 * Note that we use clusters for incoming frames, so the 1948 * buffer is virtually contiguous. 1949 */ 1950 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 1951 1952 /* Allow the receive descriptor to continue using its mbuf. */ 1953 SIP_INIT_RXDESC(sc, i); 1954 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1955 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1956 #endif /* __NO_STRICT_ALIGNMENT */ 1957 1958 ifp->if_ipackets++; 1959 m->m_flags |= M_HASFCS; 1960 m->m_pkthdr.rcvif = ifp; 1961 m->m_pkthdr.len = m->m_len = len; 1962 1963 #if NBPFILTER > 0 1964 /* 1965 * Pass this up to any BPF listeners, but only 1966 * pass if up the stack if it's for us. 1967 */ 1968 if (ifp->if_bpf) 1969 bpf_mtap(ifp->if_bpf, m); 1970 #endif /* NBPFILTER > 0 */ 1971 1972 /* Pass it on. */ 1973 (*ifp->if_input)(ifp, m); 1974 } 1975 1976 /* Update the receive pointer. */ 1977 sc->sc_rxptr = i; 1978 } 1979 #endif /* DP83820 */ 1980 1981 /* 1982 * sip_tick: 1983 * 1984 * One second timer, used to tick the MII. 1985 */ 1986 void 1987 SIP_DECL(tick)(void *arg) 1988 { 1989 struct sip_softc *sc = arg; 1990 int s; 1991 1992 s = splnet(); 1993 mii_tick(&sc->sc_mii); 1994 splx(s); 1995 1996 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 1997 } 1998 1999 /* 2000 * sip_reset: 2001 * 2002 * Perform a soft reset on the SiS 900. 2003 */ 2004 void 2005 SIP_DECL(reset)(struct sip_softc *sc) 2006 { 2007 bus_space_tag_t st = sc->sc_st; 2008 bus_space_handle_t sh = sc->sc_sh; 2009 int i; 2010 2011 bus_space_write_4(st, sh, SIP_IER, 0); 2012 bus_space_write_4(st, sh, SIP_IMR, 0); 2013 bus_space_write_4(st, sh, SIP_RFCR, 0); 2014 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2015 2016 for (i = 0; i < SIP_TIMEOUT; i++) { 2017 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2018 break; 2019 delay(2); 2020 } 2021 2022 if (i == SIP_TIMEOUT) 2023 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2024 2025 delay(1000); 2026 2027 #ifdef DP83820 2028 /* 2029 * Set the general purpose I/O bits. Do it here in case we 2030 * need to have GPIO set up to talk to the media interface. 2031 */ 2032 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2033 delay(1000); 2034 #endif /* DP83820 */ 2035 } 2036 2037 /* 2038 * sip_init: [ ifnet interface function ] 2039 * 2040 * Initialize the interface. Must be called at splnet(). 2041 */ 2042 int 2043 SIP_DECL(init)(struct ifnet *ifp) 2044 { 2045 struct sip_softc *sc = ifp->if_softc; 2046 bus_space_tag_t st = sc->sc_st; 2047 bus_space_handle_t sh = sc->sc_sh; 2048 struct sip_txsoft *txs; 2049 struct sip_rxsoft *rxs; 2050 struct sip_desc *sipd; 2051 u_int32_t reg; 2052 int i, error = 0; 2053 2054 /* 2055 * Cancel any pending I/O. 2056 */ 2057 SIP_DECL(stop)(ifp, 0); 2058 2059 /* 2060 * Reset the chip to a known state. 2061 */ 2062 SIP_DECL(reset)(sc); 2063 2064 #if !defined(DP83820) 2065 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2066 /* 2067 * DP83815 manual, page 78: 2068 * 4.4 Recommended Registers Configuration 2069 * For optimum performance of the DP83815, version noted 2070 * as DP83815CVNG (SRR = 203h), the listed register 2071 * modifications must be followed in sequence... 2072 * 2073 * It's not clear if this should be 302h or 203h because that 2074 * chip name is listed as SRR 302h in the description of the 2075 * SRR register. However, my revision 302h DP83815 on the 2076 * Netgear FA311 purchased in 02/2001 needs these settings 2077 * to avoid tons of errors in AcceptPerfectMatch (non- 2078 * IFF_PROMISC) mode. I do not know if other revisions need 2079 * this set or not. [briggs -- 09 March 2001] 2080 * 2081 * Note that only the low-order 12 bits of 0xe4 are documented 2082 * and that this sets reserved bits in that register. 2083 */ 2084 reg = bus_space_read_4(st, sh, SIP_NS_SRR); 2085 if (reg == 0x302) { 2086 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2087 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2088 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2089 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2090 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2091 } 2092 } 2093 #endif /* ! DP83820 */ 2094 2095 /* 2096 * Initialize the transmit descriptor ring. 2097 */ 2098 for (i = 0; i < SIP_NTXDESC; i++) { 2099 sipd = &sc->sc_txdescs[i]; 2100 memset(sipd, 0, sizeof(struct sip_desc)); 2101 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2102 } 2103 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2104 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2105 sc->sc_txfree = SIP_NTXDESC; 2106 sc->sc_txnext = 0; 2107 sc->sc_txwin = 0; 2108 2109 /* 2110 * Initialize the transmit job descriptors. 2111 */ 2112 SIMPLEQ_INIT(&sc->sc_txfreeq); 2113 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2114 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2115 txs = &sc->sc_txsoft[i]; 2116 txs->txs_mbuf = NULL; 2117 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2118 } 2119 2120 /* 2121 * Initialize the receive descriptor and receive job 2122 * descriptor rings. 2123 */ 2124 for (i = 0; i < SIP_NRXDESC; i++) { 2125 rxs = &sc->sc_rxsoft[i]; 2126 if (rxs->rxs_mbuf == NULL) { 2127 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2128 printf("%s: unable to allocate or map rx " 2129 "buffer %d, error = %d\n", 2130 sc->sc_dev.dv_xname, i, error); 2131 /* 2132 * XXX Should attempt to run with fewer receive 2133 * XXX buffers instead of just failing. 2134 */ 2135 SIP_DECL(rxdrain)(sc); 2136 goto out; 2137 } 2138 } else 2139 SIP_INIT_RXDESC(sc, i); 2140 } 2141 sc->sc_rxptr = 0; 2142 #ifdef DP83820 2143 sc->sc_rxdiscard = 0; 2144 SIP_RXCHAIN_RESET(sc); 2145 #endif /* DP83820 */ 2146 2147 /* 2148 * Set the configuration register; it's already initialized 2149 * in sip_attach(). 2150 */ 2151 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2152 2153 /* 2154 * Initialize the prototype TXCFG register. 2155 */ 2156 #if defined(DP83820) 2157 sc->sc_txcfg = TXCFG_MXDMA_512; 2158 sc->sc_rxcfg = RXCFG_MXDMA_512; 2159 #else 2160 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2161 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2162 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & CFG_EDBMASTEN)) { 2163 sc->sc_txcfg = TXCFG_MXDMA_64; 2164 sc->sc_rxcfg = RXCFG_MXDMA_64; 2165 } else { 2166 sc->sc_txcfg = TXCFG_MXDMA_512; 2167 sc->sc_rxcfg = RXCFG_MXDMA_512; 2168 } 2169 #endif /* DP83820 */ 2170 2171 sc->sc_txcfg |= TXCFG_ATP | 2172 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2173 sc->sc_tx_drain_thresh; 2174 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2175 2176 /* 2177 * Initialize the receive drain threshold if we have never 2178 * done so. 2179 */ 2180 if (sc->sc_rx_drain_thresh == 0) { 2181 /* 2182 * XXX This value should be tuned. This is set to the 2183 * maximum of 248 bytes, and we may be able to improve 2184 * performance by decreasing it (although we should never 2185 * set this value lower than 2; 14 bytes are required to 2186 * filter the packet). 2187 */ 2188 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2189 } 2190 2191 /* 2192 * Initialize the prototype RXCFG register. 2193 */ 2194 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2195 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2196 2197 #ifdef DP83820 2198 /* 2199 * Initialize the VLAN/IP receive control register. 2200 * We enable checksum computation on all incoming 2201 * packets, and do not reject packets w/ bad checksums. 2202 */ 2203 reg = 0; 2204 if (ifp->if_capenable & 2205 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2206 reg |= VRCR_IPEN; 2207 if (sc->sc_ethercom.ec_nvlans != 0) 2208 reg |= VRCR_VTDEN|VRCR_VTREN; 2209 bus_space_write_4(st, sh, SIP_VRCR, reg); 2210 2211 /* 2212 * Initialize the VLAN/IP transmit control register. 2213 * We enable outgoing checksum computation on a 2214 * per-packet basis. 2215 */ 2216 reg = 0; 2217 if (ifp->if_capenable & 2218 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2219 reg |= VTCR_PPCHK; 2220 if (sc->sc_ethercom.ec_nvlans != 0) 2221 reg |= VTCR_VPPTI; 2222 bus_space_write_4(st, sh, SIP_VTCR, reg); 2223 2224 /* 2225 * If we're using VLANs, initialize the VLAN data register. 2226 * To understand why we bswap the VLAN Ethertype, see section 2227 * 4.2.36 of the DP83820 manual. 2228 */ 2229 if (sc->sc_ethercom.ec_nvlans != 0) 2230 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2231 #endif /* DP83820 */ 2232 2233 /* 2234 * Give the transmit and receive rings to the chip. 2235 */ 2236 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2237 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2238 2239 /* 2240 * Initialize the interrupt mask. 2241 */ 2242 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2243 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2244 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2245 2246 /* Set up the receive filter. */ 2247 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2248 2249 /* 2250 * Set the current media. Do this after initializing the prototype 2251 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2252 * control. 2253 */ 2254 mii_mediachg(&sc->sc_mii); 2255 2256 /* 2257 * Enable interrupts. 2258 */ 2259 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2260 2261 /* 2262 * Start the transmit and receive processes. 2263 */ 2264 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2265 2266 /* 2267 * Start the one second MII clock. 2268 */ 2269 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2270 2271 /* 2272 * ...all done! 2273 */ 2274 ifp->if_flags |= IFF_RUNNING; 2275 ifp->if_flags &= ~IFF_OACTIVE; 2276 2277 out: 2278 if (error) 2279 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2280 return (error); 2281 } 2282 2283 /* 2284 * sip_drain: 2285 * 2286 * Drain the receive queue. 2287 */ 2288 void 2289 SIP_DECL(rxdrain)(struct sip_softc *sc) 2290 { 2291 struct sip_rxsoft *rxs; 2292 int i; 2293 2294 for (i = 0; i < SIP_NRXDESC; i++) { 2295 rxs = &sc->sc_rxsoft[i]; 2296 if (rxs->rxs_mbuf != NULL) { 2297 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2298 m_freem(rxs->rxs_mbuf); 2299 rxs->rxs_mbuf = NULL; 2300 } 2301 } 2302 } 2303 2304 /* 2305 * sip_stop: [ ifnet interface function ] 2306 * 2307 * Stop transmission on the interface. 2308 */ 2309 void 2310 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2311 { 2312 struct sip_softc *sc = ifp->if_softc; 2313 bus_space_tag_t st = sc->sc_st; 2314 bus_space_handle_t sh = sc->sc_sh; 2315 struct sip_txsoft *txs; 2316 u_int32_t cmdsts = 0; /* DEBUG */ 2317 2318 /* 2319 * Stop the one second clock. 2320 */ 2321 callout_stop(&sc->sc_tick_ch); 2322 2323 /* Down the MII. */ 2324 mii_down(&sc->sc_mii); 2325 2326 /* 2327 * Disable interrupts. 2328 */ 2329 bus_space_write_4(st, sh, SIP_IER, 0); 2330 2331 /* 2332 * Stop receiver and transmitter. 2333 */ 2334 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2335 2336 /* 2337 * Release any queued transmit buffers. 2338 */ 2339 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2340 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2341 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2342 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2343 CMDSTS_INTR) == 0) 2344 printf("%s: sip_stop: last descriptor does not " 2345 "have INTR bit set\n", sc->sc_dev.dv_xname); 2346 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2347 #ifdef DIAGNOSTIC 2348 if (txs->txs_mbuf == NULL) { 2349 printf("%s: dirty txsoft with no mbuf chain\n", 2350 sc->sc_dev.dv_xname); 2351 panic("sip_stop"); 2352 } 2353 #endif 2354 cmdsts |= /* DEBUG */ 2355 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2356 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2357 m_freem(txs->txs_mbuf); 2358 txs->txs_mbuf = NULL; 2359 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2360 } 2361 2362 if (disable) 2363 SIP_DECL(rxdrain)(sc); 2364 2365 /* 2366 * Mark the interface down and cancel the watchdog timer. 2367 */ 2368 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2369 ifp->if_timer = 0; 2370 2371 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2372 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2373 printf("%s: sip_stop: no INTR bits set in dirty tx " 2374 "descriptors\n", sc->sc_dev.dv_xname); 2375 } 2376 2377 /* 2378 * sip_read_eeprom: 2379 * 2380 * Read data from the serial EEPROM. 2381 */ 2382 void 2383 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2384 u_int16_t *data) 2385 { 2386 bus_space_tag_t st = sc->sc_st; 2387 bus_space_handle_t sh = sc->sc_sh; 2388 u_int16_t reg; 2389 int i, x; 2390 2391 for (i = 0; i < wordcnt; i++) { 2392 /* Send CHIP SELECT. */ 2393 reg = EROMAR_EECS; 2394 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2395 2396 /* Shift in the READ opcode. */ 2397 for (x = 3; x > 0; x--) { 2398 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2399 reg |= EROMAR_EEDI; 2400 else 2401 reg &= ~EROMAR_EEDI; 2402 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2403 bus_space_write_4(st, sh, SIP_EROMAR, 2404 reg | EROMAR_EESK); 2405 delay(4); 2406 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2407 delay(4); 2408 } 2409 2410 /* Shift in address. */ 2411 for (x = 6; x > 0; x--) { 2412 if ((word + i) & (1 << (x - 1))) 2413 reg |= EROMAR_EEDI; 2414 else 2415 reg &= ~EROMAR_EEDI; 2416 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2417 bus_space_write_4(st, sh, SIP_EROMAR, 2418 reg | EROMAR_EESK); 2419 delay(4); 2420 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2421 delay(4); 2422 } 2423 2424 /* Shift out data. */ 2425 reg = EROMAR_EECS; 2426 data[i] = 0; 2427 for (x = 16; x > 0; x--) { 2428 bus_space_write_4(st, sh, SIP_EROMAR, 2429 reg | EROMAR_EESK); 2430 delay(4); 2431 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2432 data[i] |= (1 << (x - 1)); 2433 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2434 delay(4); 2435 } 2436 2437 /* Clear CHIP SELECT. */ 2438 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2439 delay(4); 2440 } 2441 } 2442 2443 /* 2444 * sip_add_rxbuf: 2445 * 2446 * Add a receive buffer to the indicated descriptor. 2447 */ 2448 int 2449 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2450 { 2451 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2452 struct mbuf *m; 2453 int error; 2454 2455 MGETHDR(m, M_DONTWAIT, MT_DATA); 2456 if (m == NULL) 2457 return (ENOBUFS); 2458 2459 MCLGET(m, M_DONTWAIT); 2460 if ((m->m_flags & M_EXT) == 0) { 2461 m_freem(m); 2462 return (ENOBUFS); 2463 } 2464 2465 #if defined(DP83820) 2466 m->m_len = SIP_RXBUF_LEN; 2467 #endif /* DP83820 */ 2468 2469 if (rxs->rxs_mbuf != NULL) 2470 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2471 2472 rxs->rxs_mbuf = m; 2473 2474 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2475 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2476 BUS_DMA_READ|BUS_DMA_NOWAIT); 2477 if (error) { 2478 printf("%s: can't load rx DMA map %d, error = %d\n", 2479 sc->sc_dev.dv_xname, idx, error); 2480 panic("sip_add_rxbuf"); /* XXX */ 2481 } 2482 2483 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2484 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2485 2486 SIP_INIT_RXDESC(sc, idx); 2487 2488 return (0); 2489 } 2490 2491 #if !defined(DP83820) 2492 /* 2493 * sip_sis900_set_filter: 2494 * 2495 * Set up the receive filter. 2496 */ 2497 void 2498 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2499 { 2500 bus_space_tag_t st = sc->sc_st; 2501 bus_space_handle_t sh = sc->sc_sh; 2502 struct ethercom *ec = &sc->sc_ethercom; 2503 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2504 struct ether_multi *enm; 2505 u_int8_t *cp; 2506 struct ether_multistep step; 2507 u_int32_t crc, mchash[16]; 2508 2509 /* 2510 * Initialize the prototype RFCR. 2511 */ 2512 sc->sc_rfcr = RFCR_RFEN; 2513 if (ifp->if_flags & IFF_BROADCAST) 2514 sc->sc_rfcr |= RFCR_AAB; 2515 if (ifp->if_flags & IFF_PROMISC) { 2516 sc->sc_rfcr |= RFCR_AAP; 2517 goto allmulti; 2518 } 2519 2520 /* 2521 * Set up the multicast address filter by passing all multicast 2522 * addresses through a CRC generator, and then using the high-order 2523 * 6 bits as an index into the 128 bit multicast hash table (only 2524 * the lower 16 bits of each 32 bit multicast hash register are 2525 * valid). The high order bits select the register, while the 2526 * rest of the bits select the bit within the register. 2527 */ 2528 2529 memset(mchash, 0, sizeof(mchash)); 2530 2531 ETHER_FIRST_MULTI(step, ec, enm); 2532 while (enm != NULL) { 2533 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2534 /* 2535 * We must listen to a range of multicast addresses. 2536 * For now, just accept all multicasts, rather than 2537 * trying to set only those filter bits needed to match 2538 * the range. (At this time, the only use of address 2539 * ranges is for IP multicast routing, for which the 2540 * range is big enough to require all bits set.) 2541 */ 2542 goto allmulti; 2543 } 2544 2545 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2546 2547 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2548 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2549 /* Just want the 8 most significant bits. */ 2550 crc >>= 24; 2551 } else { 2552 /* Just want the 7 most significant bits. */ 2553 crc >>= 25; 2554 } 2555 2556 /* Set the corresponding bit in the hash table. */ 2557 mchash[crc >> 4] |= 1 << (crc & 0xf); 2558 2559 ETHER_NEXT_MULTI(step, enm); 2560 } 2561 2562 ifp->if_flags &= ~IFF_ALLMULTI; 2563 goto setit; 2564 2565 allmulti: 2566 ifp->if_flags |= IFF_ALLMULTI; 2567 sc->sc_rfcr |= RFCR_AAM; 2568 2569 setit: 2570 #define FILTER_EMIT(addr, data) \ 2571 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2572 delay(1); \ 2573 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2574 delay(1) 2575 2576 /* 2577 * Disable receive filter, and program the node address. 2578 */ 2579 cp = LLADDR(ifp->if_sadl); 2580 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2581 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2582 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2583 2584 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2585 /* 2586 * Program the multicast hash table. 2587 */ 2588 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2589 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2590 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2591 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2592 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2593 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2594 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2595 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2596 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2597 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2598 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2599 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2600 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2601 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2602 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2603 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2604 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2605 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2606 } 2607 } 2608 #undef FILTER_EMIT 2609 2610 /* 2611 * Re-enable the receiver filter. 2612 */ 2613 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2614 } 2615 #endif /* ! DP83820 */ 2616 2617 /* 2618 * sip_dp83815_set_filter: 2619 * 2620 * Set up the receive filter. 2621 */ 2622 void 2623 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2624 { 2625 bus_space_tag_t st = sc->sc_st; 2626 bus_space_handle_t sh = sc->sc_sh; 2627 struct ethercom *ec = &sc->sc_ethercom; 2628 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2629 struct ether_multi *enm; 2630 u_int8_t *cp; 2631 struct ether_multistep step; 2632 u_int32_t crc, hash, slot, bit; 2633 #ifdef DP83820 2634 #define MCHASH_NWORDS 128 2635 #else 2636 #define MCHASH_NWORDS 32 2637 #endif /* DP83820 */ 2638 u_int16_t mchash[MCHASH_NWORDS]; 2639 int i; 2640 2641 /* 2642 * Initialize the prototype RFCR. 2643 * Enable the receive filter, and accept on 2644 * Perfect (destination address) Match 2645 * If IFF_BROADCAST, also accept all broadcast packets. 2646 * If IFF_PROMISC, accept all unicast packets (and later, set 2647 * IFF_ALLMULTI and accept all multicast, too). 2648 */ 2649 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2650 if (ifp->if_flags & IFF_BROADCAST) 2651 sc->sc_rfcr |= RFCR_AAB; 2652 if (ifp->if_flags & IFF_PROMISC) { 2653 sc->sc_rfcr |= RFCR_AAP; 2654 goto allmulti; 2655 } 2656 2657 #ifdef DP83820 2658 /* 2659 * Set up the DP83820 multicast address filter by passing all multicast 2660 * addresses through a CRC generator, and then using the high-order 2661 * 11 bits as an index into the 2048 bit multicast hash table. The 2662 * high-order 7 bits select the slot, while the low-order 4 bits 2663 * select the bit within the slot. Note that only the low 16-bits 2664 * of each filter word are used, and there are 128 filter words. 2665 */ 2666 #else 2667 /* 2668 * Set up the DP83815 multicast address filter by passing all multicast 2669 * addresses through a CRC generator, and then using the high-order 2670 * 9 bits as an index into the 512 bit multicast hash table. The 2671 * high-order 5 bits select the slot, while the low-order 4 bits 2672 * select the bit within the slot. Note that only the low 16-bits 2673 * of each filter word are used, and there are 32 filter words. 2674 */ 2675 #endif /* DP83820 */ 2676 2677 memset(mchash, 0, sizeof(mchash)); 2678 2679 ifp->if_flags &= ~IFF_ALLMULTI; 2680 ETHER_FIRST_MULTI(step, ec, enm); 2681 if (enm == NULL) 2682 goto setit; 2683 while (enm != NULL) { 2684 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2685 /* 2686 * We must listen to a range of multicast addresses. 2687 * For now, just accept all multicasts, rather than 2688 * trying to set only those filter bits needed to match 2689 * the range. (At this time, the only use of address 2690 * ranges is for IP multicast routing, for which the 2691 * range is big enough to require all bits set.) 2692 */ 2693 goto allmulti; 2694 } 2695 2696 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2697 2698 #ifdef DP83820 2699 /* Just want the 11 most significant bits. */ 2700 hash = crc >> 21; 2701 #else 2702 /* Just want the 9 most significant bits. */ 2703 hash = crc >> 23; 2704 #endif /* DP83820 */ 2705 2706 slot = hash >> 4; 2707 bit = hash & 0xf; 2708 2709 /* Set the corresponding bit in the hash table. */ 2710 mchash[slot] |= 1 << bit; 2711 2712 ETHER_NEXT_MULTI(step, enm); 2713 } 2714 sc->sc_rfcr |= RFCR_MHEN; 2715 goto setit; 2716 2717 allmulti: 2718 ifp->if_flags |= IFF_ALLMULTI; 2719 sc->sc_rfcr |= RFCR_AAM; 2720 2721 setit: 2722 #define FILTER_EMIT(addr, data) \ 2723 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2724 delay(1); \ 2725 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2726 delay(1) 2727 2728 /* 2729 * Disable receive filter, and program the node address. 2730 */ 2731 cp = LLADDR(ifp->if_sadl); 2732 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 2733 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 2734 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 2735 2736 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2737 /* 2738 * Program the multicast hash table. 2739 */ 2740 for (i = 0; i < MCHASH_NWORDS; i++) { 2741 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 2742 mchash[i]); 2743 } 2744 } 2745 #undef FILTER_EMIT 2746 #undef MCHASH_NWORDS 2747 2748 /* 2749 * Re-enable the receiver filter. 2750 */ 2751 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2752 } 2753 2754 #if defined(DP83820) 2755 /* 2756 * sip_dp83820_mii_readreg: [mii interface function] 2757 * 2758 * Read a PHY register on the MII of the DP83820. 2759 */ 2760 int 2761 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 2762 { 2763 2764 return (mii_bitbang_readreg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2765 phy, reg)); 2766 } 2767 2768 /* 2769 * sip_dp83820_mii_writereg: [mii interface function] 2770 * 2771 * Write a PHY register on the MII of the DP83820. 2772 */ 2773 void 2774 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 2775 { 2776 2777 mii_bitbang_writereg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2778 phy, reg, val); 2779 } 2780 2781 /* 2782 * sip_dp83815_mii_statchg: [mii interface function] 2783 * 2784 * Callback from MII layer when media changes. 2785 */ 2786 void 2787 SIP_DECL(dp83820_mii_statchg)(struct device *self) 2788 { 2789 struct sip_softc *sc = (struct sip_softc *) self; 2790 u_int32_t cfg; 2791 2792 /* 2793 * Update TXCFG for full-duplex operation. 2794 */ 2795 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2796 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2797 else 2798 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2799 2800 /* 2801 * Update RXCFG for full-duplex or loopback. 2802 */ 2803 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2804 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2805 sc->sc_rxcfg |= RXCFG_ATX; 2806 else 2807 sc->sc_rxcfg &= ~RXCFG_ATX; 2808 2809 /* 2810 * Update CFG for MII/GMII. 2811 */ 2812 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2813 cfg = sc->sc_cfg | CFG_MODE_1000; 2814 else 2815 cfg = sc->sc_cfg; 2816 2817 /* 2818 * XXX 802.3x flow control. 2819 */ 2820 2821 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 2822 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2823 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2824 } 2825 2826 /* 2827 * sip_dp83820_mii_bitbang_read: [mii bit-bang interface function] 2828 * 2829 * Read the MII serial port for the MII bit-bang module. 2830 */ 2831 u_int32_t 2832 SIP_DECL(dp83820_mii_bitbang_read)(struct device *self) 2833 { 2834 struct sip_softc *sc = (void *) self; 2835 2836 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 2837 } 2838 2839 /* 2840 * sip_dp83820_mii_bitbang_write: [mii big-bang interface function] 2841 * 2842 * Write the MII serial port for the MII bit-bang module. 2843 */ 2844 void 2845 SIP_DECL(dp83820_mii_bitbang_write)(struct device *self, u_int32_t val) 2846 { 2847 struct sip_softc *sc = (void *) self; 2848 2849 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 2850 } 2851 #else /* ! DP83820 */ 2852 /* 2853 * sip_sis900_mii_readreg: [mii interface function] 2854 * 2855 * Read a PHY register on the MII. 2856 */ 2857 int 2858 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 2859 { 2860 struct sip_softc *sc = (struct sip_softc *) self; 2861 u_int32_t enphy; 2862 2863 /* 2864 * The SiS 900 has only an internal PHY on the MII. Only allow 2865 * MII address 0. 2866 */ 2867 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 2868 sc->sc_rev < SIS_REV_635 && phy != 0) 2869 return (0); 2870 2871 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2872 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 2873 ENPHY_RWCMD | ENPHY_ACCESS); 2874 do { 2875 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2876 } while (enphy & ENPHY_ACCESS); 2877 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 2878 } 2879 2880 /* 2881 * sip_sis900_mii_writereg: [mii interface function] 2882 * 2883 * Write a PHY register on the MII. 2884 */ 2885 void 2886 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 2887 { 2888 struct sip_softc *sc = (struct sip_softc *) self; 2889 u_int32_t enphy; 2890 2891 /* 2892 * The SiS 900 has only an internal PHY on the MII. Only allow 2893 * MII address 0. 2894 */ 2895 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 2896 sc->sc_rev < SIS_REV_635 && phy != 0) 2897 return; 2898 2899 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2900 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 2901 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 2902 do { 2903 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2904 } while (enphy & ENPHY_ACCESS); 2905 } 2906 2907 /* 2908 * sip_sis900_mii_statchg: [mii interface function] 2909 * 2910 * Callback from MII layer when media changes. 2911 */ 2912 void 2913 SIP_DECL(sis900_mii_statchg)(struct device *self) 2914 { 2915 struct sip_softc *sc = (struct sip_softc *) self; 2916 u_int32_t flowctl; 2917 2918 /* 2919 * Update TXCFG for full-duplex operation. 2920 */ 2921 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2922 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2923 else 2924 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2925 2926 /* 2927 * Update RXCFG for full-duplex or loopback. 2928 */ 2929 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2930 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2931 sc->sc_rxcfg |= RXCFG_ATX; 2932 else 2933 sc->sc_rxcfg &= ~RXCFG_ATX; 2934 2935 /* 2936 * Update IMR for use of 802.3x flow control. 2937 */ 2938 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 2939 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 2940 flowctl = FLOWCTL_FLOWEN; 2941 } else { 2942 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 2943 flowctl = 0; 2944 } 2945 2946 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2947 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2948 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 2949 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 2950 } 2951 2952 /* 2953 * sip_dp83815_mii_readreg: [mii interface function] 2954 * 2955 * Read a PHY register on the MII. 2956 */ 2957 int 2958 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 2959 { 2960 struct sip_softc *sc = (struct sip_softc *) self; 2961 u_int32_t val; 2962 2963 /* 2964 * The DP83815 only has an internal PHY. Only allow 2965 * MII address 0. 2966 */ 2967 if (phy != 0) 2968 return (0); 2969 2970 /* 2971 * Apparently, after a reset, the DP83815 can take a while 2972 * to respond. During this recovery period, the BMSR returns 2973 * a value of 0. Catch this -- it's not supposed to happen 2974 * (the BMSR has some hardcoded-to-1 bits), and wait for the 2975 * PHY to come back to life. 2976 * 2977 * This works out because the BMSR is the first register 2978 * read during the PHY probe process. 2979 */ 2980 do { 2981 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 2982 } while (reg == MII_BMSR && val == 0); 2983 2984 return (val & 0xffff); 2985 } 2986 2987 /* 2988 * sip_dp83815_mii_writereg: [mii interface function] 2989 * 2990 * Write a PHY register to the MII. 2991 */ 2992 void 2993 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 2994 { 2995 struct sip_softc *sc = (struct sip_softc *) self; 2996 2997 /* 2998 * The DP83815 only has an internal PHY. Only allow 2999 * MII address 0. 3000 */ 3001 if (phy != 0) 3002 return; 3003 3004 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3005 } 3006 3007 /* 3008 * sip_dp83815_mii_statchg: [mii interface function] 3009 * 3010 * Callback from MII layer when media changes. 3011 */ 3012 void 3013 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3014 { 3015 struct sip_softc *sc = (struct sip_softc *) self; 3016 3017 /* 3018 * Update TXCFG for full-duplex operation. 3019 */ 3020 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3021 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3022 else 3023 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3024 3025 /* 3026 * Update RXCFG for full-duplex or loopback. 3027 */ 3028 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3029 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3030 sc->sc_rxcfg |= RXCFG_ATX; 3031 else 3032 sc->sc_rxcfg &= ~RXCFG_ATX; 3033 3034 /* 3035 * XXX 802.3x flow control. 3036 */ 3037 3038 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3039 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3040 } 3041 #endif /* DP83820 */ 3042 3043 #if defined(DP83820) 3044 void 3045 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3046 const struct pci_attach_args *pa, u_int8_t *enaddr) 3047 { 3048 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3049 u_int8_t cksum, *e, match; 3050 int i; 3051 3052 /* 3053 * EEPROM data format for the DP83820 can be found in 3054 * the DP83820 manual, section 4.2.4. 3055 */ 3056 3057 SIP_DECL(read_eeprom)(sc, 0, 3058 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3059 3060 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3061 match = ~(match - 1); 3062 3063 cksum = 0x55; 3064 e = (u_int8_t *) eeprom_data; 3065 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3066 cksum += *e++; 3067 3068 if (cksum != match) 3069 printf("%s: Checksum (%x) mismatch (%x)", 3070 sc->sc_dev.dv_xname, cksum, match); 3071 3072 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3073 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3074 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3075 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3076 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3077 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3078 3079 /* Get the GPIOR bits. */ 3080 sc->sc_gpior = eeprom_data[0x04]; 3081 3082 /* Get various CFG related bits. */ 3083 if (eeprom_data[0x05] & DP83820_CONFIG2_CFG_EXT_125) 3084 sc->sc_cfg |= CFG_EXT_125; 3085 if (eeprom_data[0x05] & DP83820_CONFIG2_CFG_M64ADDR) 3086 sc->sc_cfg |= CFG_M64ADDR; 3087 if (eeprom_data[0x05] & DP83820_CONFIG2_CFG_DATA64_EN) 3088 sc->sc_cfg |= CFG_DATA64_EN; 3089 if (eeprom_data[0x05] & DP83820_CONFIG2_CFG_T64ADDR) 3090 sc->sc_cfg |= CFG_T64ADDR; 3091 if (eeprom_data[0x05] & DP83820_CONFIG2_CFG_TBI_EN) 3092 sc->sc_cfg |= CFG_TBI_EN; 3093 } 3094 #else /* ! DP83820 */ 3095 void 3096 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3097 const struct pci_attach_args *pa, u_int8_t *enaddr) 3098 { 3099 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3100 3101 switch (sc->sc_rev) { 3102 case SIS_REV_630S: 3103 case SIS_REV_630E: 3104 case SIS_REV_630EA1: 3105 case SIS_REV_630ET: 3106 case SIS_REV_635: 3107 /* 3108 * The MAC address for the on-board Ethernet of 3109 * the SiS 630 chipset is in the NVRAM. Kick 3110 * the chip into re-loading it from NVRAM, and 3111 * read the MAC address out of the filter registers. 3112 */ 3113 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3114 3115 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3116 RFCR_RFADDR_NODE0); 3117 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3118 0xffff; 3119 3120 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3121 RFCR_RFADDR_NODE2); 3122 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3123 0xffff; 3124 3125 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3126 RFCR_RFADDR_NODE4); 3127 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3128 0xffff; 3129 break; 3130 3131 default: 3132 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3133 sizeof(myea) / sizeof(myea[0]), myea); 3134 } 3135 3136 enaddr[0] = myea[0] & 0xff; 3137 enaddr[1] = myea[0] >> 8; 3138 enaddr[2] = myea[1] & 0xff; 3139 enaddr[3] = myea[1] >> 8; 3140 enaddr[4] = myea[2] & 0xff; 3141 enaddr[5] = myea[2] >> 8; 3142 } 3143 3144 /* Table and macro to bit-reverse an octet. */ 3145 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3146 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3147 3148 void 3149 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3150 const struct pci_attach_args *pa, u_int8_t *enaddr) 3151 { 3152 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3153 u_int8_t cksum, *e, match; 3154 int i; 3155 3156 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3157 sizeof(eeprom_data[0]), eeprom_data); 3158 3159 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3160 match = ~(match - 1); 3161 3162 cksum = 0x55; 3163 e = (u_int8_t *) eeprom_data; 3164 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3165 cksum += *e++; 3166 } 3167 if (cksum != match) { 3168 printf("%s: Checksum (%x) mismatch (%x)", 3169 sc->sc_dev.dv_xname, cksum, match); 3170 } 3171 3172 /* 3173 * Unrolled because it makes slightly more sense this way. 3174 * The DP83815 stores the MAC address in bit 0 of word 6 3175 * through bit 15 of word 8. 3176 */ 3177 ea = &eeprom_data[6]; 3178 enaddr[0] = ((*ea & 0x1) << 7); 3179 ea++; 3180 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3181 enaddr[1] = ((*ea & 0x1FE) >> 1); 3182 enaddr[2] = ((*ea & 0x1) << 7); 3183 ea++; 3184 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3185 enaddr[3] = ((*ea & 0x1FE) >> 1); 3186 enaddr[4] = ((*ea & 0x1) << 7); 3187 ea++; 3188 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3189 enaddr[5] = ((*ea & 0x1FE) >> 1); 3190 3191 /* 3192 * In case that's not weird enough, we also need to reverse 3193 * the bits in each byte. This all actually makes more sense 3194 * if you think about the EEPROM storage as an array of bits 3195 * being shifted into bytes, but that's not how we're looking 3196 * at it here... 3197 */ 3198 for (i = 0; i < 6 ;i++) 3199 enaddr[i] = bbr(enaddr[i]); 3200 } 3201 #endif /* DP83820 */ 3202 3203 /* 3204 * sip_mediastatus: [ifmedia interface function] 3205 * 3206 * Get the current interface media status. 3207 */ 3208 void 3209 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3210 { 3211 struct sip_softc *sc = ifp->if_softc; 3212 3213 mii_pollstat(&sc->sc_mii); 3214 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3215 ifmr->ifm_active = sc->sc_mii.mii_media_active; 3216 } 3217 3218 /* 3219 * sip_mediachange: [ifmedia interface function] 3220 * 3221 * Set hardware to newly-selected media. 3222 */ 3223 int 3224 SIP_DECL(mediachange)(struct ifnet *ifp) 3225 { 3226 struct sip_softc *sc = ifp->if_softc; 3227 3228 if (ifp->if_flags & IFF_UP) 3229 mii_mediachg(&sc->sc_mii); 3230 return (0); 3231 } 3232
Indexes created Tue Sep 30 11:09:46 GMT 2025