if_sip.c revision 1.59
1 /* $NetBSD: if_sip.c,v 1.59 2002/06/30 20:04:43 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Support the 10-bit interface on the DP83820 (for fiber). 80 * 81 * - Reduce the Rx interrupt load. 82 */ 83 84 #include <sys/cdefs.h> 85 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.59 2002/06/30 20:04:43 thorpej Exp $"); 86 87 #include "bpfilter.h" 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/callout.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/ioctl.h> 97 #include <sys/errno.h> 98 #include <sys/device.h> 99 #include <sys/queue.h> 100 101 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 102 103 #include <net/if.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 #include <net/if_ether.h> 107 108 #if NBPFILTER > 0 109 #include <net/bpf.h> 110 #endif 111 112 #include <machine/bus.h> 113 #include <machine/intr.h> 114 #include <machine/endian.h> 115 116 #include <dev/mii/mii.h> 117 #include <dev/mii/miivar.h> 118 #ifdef DP83820 119 #include <dev/mii/mii_bitbang.h> 120 #endif /* DP83820 */ 121 122 #include <dev/pci/pcireg.h> 123 #include <dev/pci/pcivar.h> 124 #include <dev/pci/pcidevs.h> 125 126 #include <dev/pci/if_sipreg.h> 127 128 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 129 #define SIP_DECL(x) __CONCAT(gsip_,x) 130 #else /* SiS900 and DP83815 */ 131 #define SIP_DECL(x) __CONCAT(sip_,x) 132 #endif 133 134 #define SIP_STR(x) __STRING(SIP_DECL(x)) 135 136 /* 137 * Transmit descriptor list size. This is arbitrary, but allocate 138 * enough descriptors for 128 pending transmissions, and 8 segments 139 * per packet. This MUST work out to a power of 2. 140 */ 141 #define SIP_NTXSEGS 16 142 #define SIP_NTXSEGS_ALLOC 8 143 144 #define SIP_TXQUEUELEN 256 145 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 146 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 147 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 148 149 #if defined(DP83020) 150 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 151 #else 152 #define TX_DMAMAP_SIZE MCLBYTES 153 #endif 154 155 /* 156 * Receive descriptor list size. We have one Rx buffer per incoming 157 * packet, so this logic is a little simpler. 158 * 159 * Actually, on the DP83820, we allow the packet to consume more than 160 * one buffer, in order to support jumbo Ethernet frames. In that 161 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 162 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 163 * so we'd better be quick about handling receive interrupts. 164 */ 165 #if defined(DP83820) 166 #define SIP_NRXDESC 256 167 #else 168 #define SIP_NRXDESC 128 169 #endif /* DP83820 */ 170 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 171 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 172 173 /* 174 * Control structures are DMA'd to the SiS900 chip. We allocate them in 175 * a single clump that maps to a single DMA segment to make several things 176 * easier. 177 */ 178 struct sip_control_data { 179 /* 180 * The transmit descriptors. 181 */ 182 struct sip_desc scd_txdescs[SIP_NTXDESC]; 183 184 /* 185 * The receive descriptors. 186 */ 187 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 188 }; 189 190 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 191 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 192 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 193 194 /* 195 * Software state for transmit jobs. 196 */ 197 struct sip_txsoft { 198 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 199 bus_dmamap_t txs_dmamap; /* our DMA map */ 200 int txs_firstdesc; /* first descriptor in packet */ 201 int txs_lastdesc; /* last descriptor in packet */ 202 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 203 }; 204 205 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 206 207 /* 208 * Software state for receive jobs. 209 */ 210 struct sip_rxsoft { 211 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 212 bus_dmamap_t rxs_dmamap; /* our DMA map */ 213 }; 214 215 /* 216 * Software state per device. 217 */ 218 struct sip_softc { 219 struct device sc_dev; /* generic device information */ 220 bus_space_tag_t sc_st; /* bus space tag */ 221 bus_space_handle_t sc_sh; /* bus space handle */ 222 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 223 struct ethercom sc_ethercom; /* ethernet common data */ 224 void *sc_sdhook; /* shutdown hook */ 225 226 const struct sip_product *sc_model; /* which model are we? */ 227 int sc_rev; /* chip revision */ 228 229 void *sc_ih; /* interrupt cookie */ 230 231 struct mii_data sc_mii; /* MII/media information */ 232 233 struct callout sc_tick_ch; /* tick callout */ 234 235 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 236 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 237 238 /* 239 * Software state for transmit and receive descriptors. 240 */ 241 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 242 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 243 244 /* 245 * Control data structures. 246 */ 247 struct sip_control_data *sc_control_data; 248 #define sc_txdescs sc_control_data->scd_txdescs 249 #define sc_rxdescs sc_control_data->scd_rxdescs 250 251 #ifdef SIP_EVENT_COUNTERS 252 /* 253 * Event counters. 254 */ 255 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 256 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 257 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 258 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 259 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 260 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 261 #ifdef DP83820 262 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 263 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 264 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 265 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 266 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 267 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 268 #endif /* DP83820 */ 269 #endif /* SIP_EVENT_COUNTERS */ 270 271 u_int32_t sc_txcfg; /* prototype TXCFG register */ 272 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 273 u_int32_t sc_imr; /* prototype IMR register */ 274 u_int32_t sc_rfcr; /* prototype RFCR register */ 275 276 u_int32_t sc_cfg; /* prototype CFG register */ 277 278 #ifdef DP83820 279 u_int32_t sc_gpior; /* prototype GPIOR register */ 280 #endif /* DP83820 */ 281 282 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 283 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 284 285 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 286 287 int sc_flags; /* misc. flags; see below */ 288 289 int sc_txfree; /* number of free Tx descriptors */ 290 int sc_txnext; /* next ready Tx descriptor */ 291 int sc_txwin; /* Tx descriptors since last intr */ 292 293 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 294 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 295 296 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 297 #if defined(DP83820) 298 int sc_rxdiscard; 299 int sc_rxlen; 300 struct mbuf *sc_rxhead; 301 struct mbuf *sc_rxtail; 302 struct mbuf **sc_rxtailp; 303 #endif /* DP83820 */ 304 }; 305 306 /* sc_flags */ 307 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 308 309 #ifdef DP83820 310 #define SIP_RXCHAIN_RESET(sc) \ 311 do { \ 312 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 313 *(sc)->sc_rxtailp = NULL; \ 314 (sc)->sc_rxlen = 0; \ 315 } while (/*CONSTCOND*/0) 316 317 #define SIP_RXCHAIN_LINK(sc, m) \ 318 do { \ 319 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 320 (sc)->sc_rxtailp = &(m)->m_next; \ 321 } while (/*CONSTCOND*/0) 322 #endif /* DP83820 */ 323 324 #ifdef SIP_EVENT_COUNTERS 325 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 326 #else 327 #define SIP_EVCNT_INCR(ev) /* nothing */ 328 #endif 329 330 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 331 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 332 333 #define SIP_CDTXSYNC(sc, x, n, ops) \ 334 do { \ 335 int __x, __n; \ 336 \ 337 __x = (x); \ 338 __n = (n); \ 339 \ 340 /* If it will wrap around, sync to the end of the ring. */ \ 341 if ((__x + __n) > SIP_NTXDESC) { \ 342 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 343 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 344 (SIP_NTXDESC - __x), (ops)); \ 345 __n -= (SIP_NTXDESC - __x); \ 346 __x = 0; \ 347 } \ 348 \ 349 /* Now sync whatever is left. */ \ 350 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 351 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 352 } while (0) 353 354 #define SIP_CDRXSYNC(sc, x, ops) \ 355 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 356 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 357 358 #ifdef DP83820 359 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 360 #define SIP_RXBUF_LEN (MCLBYTES - 4) 361 #else 362 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 363 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 364 #endif 365 #define SIP_INIT_RXDESC(sc, x) \ 366 do { \ 367 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 368 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 369 \ 370 __sipd->sipd_link = \ 371 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 372 __sipd->sipd_bufptr = \ 373 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 374 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 375 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 376 SIP_INIT_RXDESC_EXTSTS \ 377 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 378 } while (0) 379 380 #define SIP_CHIP_VERS(sc, v, p, r) \ 381 ((sc)->sc_model->sip_vendor == (v) && \ 382 (sc)->sc_model->sip_product == (p) && \ 383 (sc)->sc_rev == (r)) 384 385 #define SIP_CHIP_MODEL(sc, v, p) \ 386 ((sc)->sc_model->sip_vendor == (v) && \ 387 (sc)->sc_model->sip_product == (p)) 388 389 #if !defined(DP83820) 390 #define SIP_SIS900_REV(sc, rev) \ 391 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 392 #endif 393 394 #define SIP_TIMEOUT 1000 395 396 void SIP_DECL(start)(struct ifnet *); 397 void SIP_DECL(watchdog)(struct ifnet *); 398 int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 399 int SIP_DECL(init)(struct ifnet *); 400 void SIP_DECL(stop)(struct ifnet *, int); 401 402 void SIP_DECL(shutdown)(void *); 403 404 void SIP_DECL(reset)(struct sip_softc *); 405 void SIP_DECL(rxdrain)(struct sip_softc *); 406 int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 407 void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, u_int16_t *); 408 void SIP_DECL(tick)(void *); 409 410 #if !defined(DP83820) 411 void SIP_DECL(sis900_set_filter)(struct sip_softc *); 412 #endif /* ! DP83820 */ 413 void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 414 415 #if defined(DP83820) 416 void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 417 const struct pci_attach_args *, u_int8_t *); 418 #else 419 void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 420 const struct pci_attach_args *, u_int8_t *); 421 void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 422 const struct pci_attach_args *, u_int8_t *); 423 #endif /* DP83820 */ 424 425 int SIP_DECL(intr)(void *); 426 void SIP_DECL(txintr)(struct sip_softc *); 427 void SIP_DECL(rxintr)(struct sip_softc *); 428 429 #if defined(DP83820) 430 int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 431 void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 432 void SIP_DECL(dp83820_mii_statchg)(struct device *); 433 #else 434 int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 435 void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 436 void SIP_DECL(sis900_mii_statchg)(struct device *); 437 438 int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 439 void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 440 void SIP_DECL(dp83815_mii_statchg)(struct device *); 441 #endif /* DP83820 */ 442 443 int SIP_DECL(mediachange)(struct ifnet *); 444 void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 445 446 int SIP_DECL(match)(struct device *, struct cfdata *, void *); 447 void SIP_DECL(attach)(struct device *, struct device *, void *); 448 449 int SIP_DECL(copy_small) = 0; 450 451 struct cfattach SIP_DECL(ca) = { 452 sizeof(struct sip_softc), SIP_DECL(match), SIP_DECL(attach), 453 }; 454 455 /* 456 * Descriptions of the variants of the SiS900. 457 */ 458 struct sip_variant { 459 int (*sipv_mii_readreg)(struct device *, int, int); 460 void (*sipv_mii_writereg)(struct device *, int, int, int); 461 void (*sipv_mii_statchg)(struct device *); 462 void (*sipv_set_filter)(struct sip_softc *); 463 void (*sipv_read_macaddr)(struct sip_softc *, 464 const struct pci_attach_args *, u_int8_t *); 465 }; 466 467 #if defined(DP83820) 468 u_int32_t SIP_DECL(dp83820_mii_bitbang_read)(struct device *); 469 void SIP_DECL(dp83820_mii_bitbang_write)(struct device *, u_int32_t); 470 471 const struct mii_bitbang_ops SIP_DECL(dp83820_mii_bitbang_ops) = { 472 SIP_DECL(dp83820_mii_bitbang_read), 473 SIP_DECL(dp83820_mii_bitbang_write), 474 { 475 EROMAR_MDIO, /* MII_BIT_MDO */ 476 EROMAR_MDIO, /* MII_BIT_MDI */ 477 EROMAR_MDC, /* MII_BIT_MDC */ 478 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 479 0, /* MII_BIT_DIR_PHY_HOST */ 480 } 481 }; 482 #endif /* DP83820 */ 483 484 #if defined(DP83820) 485 const struct sip_variant SIP_DECL(variant_dp83820) = { 486 SIP_DECL(dp83820_mii_readreg), 487 SIP_DECL(dp83820_mii_writereg), 488 SIP_DECL(dp83820_mii_statchg), 489 SIP_DECL(dp83815_set_filter), 490 SIP_DECL(dp83820_read_macaddr), 491 }; 492 #else 493 const struct sip_variant SIP_DECL(variant_sis900) = { 494 SIP_DECL(sis900_mii_readreg), 495 SIP_DECL(sis900_mii_writereg), 496 SIP_DECL(sis900_mii_statchg), 497 SIP_DECL(sis900_set_filter), 498 SIP_DECL(sis900_read_macaddr), 499 }; 500 501 const struct sip_variant SIP_DECL(variant_dp83815) = { 502 SIP_DECL(dp83815_mii_readreg), 503 SIP_DECL(dp83815_mii_writereg), 504 SIP_DECL(dp83815_mii_statchg), 505 SIP_DECL(dp83815_set_filter), 506 SIP_DECL(dp83815_read_macaddr), 507 }; 508 #endif /* DP83820 */ 509 510 /* 511 * Devices supported by this driver. 512 */ 513 const struct sip_product { 514 pci_vendor_id_t sip_vendor; 515 pci_product_id_t sip_product; 516 const char *sip_name; 517 const struct sip_variant *sip_variant; 518 } SIP_DECL(products)[] = { 519 #if defined(DP83820) 520 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 521 "NatSemi DP83820 Gigabit Ethernet", 522 &SIP_DECL(variant_dp83820) }, 523 #else 524 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 525 "SiS 900 10/100 Ethernet", 526 &SIP_DECL(variant_sis900) }, 527 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 528 "SiS 7016 10/100 Ethernet", 529 &SIP_DECL(variant_sis900) }, 530 531 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 532 "NatSemi DP83815 10/100 Ethernet", 533 &SIP_DECL(variant_dp83815) }, 534 #endif /* DP83820 */ 535 536 { 0, 0, 537 NULL, 538 NULL }, 539 }; 540 541 static const struct sip_product * 542 SIP_DECL(lookup)(const struct pci_attach_args *pa) 543 { 544 const struct sip_product *sip; 545 546 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 547 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 548 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 549 return (sip); 550 } 551 return (NULL); 552 } 553 554 int 555 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 556 { 557 struct pci_attach_args *pa = aux; 558 559 if (SIP_DECL(lookup)(pa) != NULL) 560 return (1); 561 562 return (0); 563 } 564 565 void 566 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 567 { 568 struct sip_softc *sc = (struct sip_softc *) self; 569 struct pci_attach_args *pa = aux; 570 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 571 pci_chipset_tag_t pc = pa->pa_pc; 572 pci_intr_handle_t ih; 573 const char *intrstr = NULL; 574 bus_space_tag_t iot, memt; 575 bus_space_handle_t ioh, memh; 576 bus_dma_segment_t seg; 577 int ioh_valid, memh_valid; 578 int i, rseg, error; 579 const struct sip_product *sip; 580 pcireg_t pmode; 581 u_int8_t enaddr[ETHER_ADDR_LEN]; 582 int pmreg; 583 #ifdef DP83820 584 pcireg_t memtype; 585 u_int32_t reg; 586 #endif /* DP83820 */ 587 588 callout_init(&sc->sc_tick_ch); 589 590 sip = SIP_DECL(lookup)(pa); 591 if (sip == NULL) { 592 printf("\n"); 593 panic(SIP_STR(attach) ": impossible"); 594 } 595 sc->sc_rev = PCI_REVISION(pa->pa_class); 596 597 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 598 599 sc->sc_model = sip; 600 601 /* 602 * XXX Work-around broken PXE firmware on some boards. 603 * 604 * The DP83815 shares an address decoder with the MEM BAR 605 * and the ROM BAR. Make sure the ROM BAR is disabled, 606 * so that memory mapped access works. 607 */ 608 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 609 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 610 ~PCI_MAPREG_ROM_ENABLE); 611 612 /* 613 * Map the device. 614 */ 615 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 616 PCI_MAPREG_TYPE_IO, 0, 617 &iot, &ioh, NULL, NULL) == 0); 618 #ifdef DP83820 619 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 620 switch (memtype) { 621 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 622 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 623 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 624 memtype, 0, &memt, &memh, NULL, NULL) == 0); 625 break; 626 default: 627 memh_valid = 0; 628 } 629 #else 630 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 631 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 632 &memt, &memh, NULL, NULL) == 0); 633 #endif /* DP83820 */ 634 635 if (memh_valid) { 636 sc->sc_st = memt; 637 sc->sc_sh = memh; 638 } else if (ioh_valid) { 639 sc->sc_st = iot; 640 sc->sc_sh = ioh; 641 } else { 642 printf("%s: unable to map device registers\n", 643 sc->sc_dev.dv_xname); 644 return; 645 } 646 647 sc->sc_dmat = pa->pa_dmat; 648 649 /* 650 * Make sure bus mastering is enabled. Also make sure 651 * Write/Invalidate is enabled if we're allowed to use it. 652 */ 653 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 654 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 655 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 656 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 657 pmreg | PCI_COMMAND_MASTER_ENABLE); 658 659 /* Get it out of power save mode if needed. */ 660 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 661 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 662 if (pmode == 3) { 663 /* 664 * The card has lost all configuration data in 665 * this state, so punt. 666 */ 667 printf("%s: unable to wake up from power state D3\n", 668 sc->sc_dev.dv_xname); 669 return; 670 } 671 if (pmode != 0) { 672 printf("%s: waking up from power state D%d\n", 673 sc->sc_dev.dv_xname, pmode); 674 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 675 } 676 } 677 678 /* 679 * Map and establish our interrupt. 680 */ 681 if (pci_intr_map(pa, &ih)) { 682 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 683 return; 684 } 685 intrstr = pci_intr_string(pc, ih); 686 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 687 if (sc->sc_ih == NULL) { 688 printf("%s: unable to establish interrupt", 689 sc->sc_dev.dv_xname); 690 if (intrstr != NULL) 691 printf(" at %s", intrstr); 692 printf("\n"); 693 return; 694 } 695 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 696 697 SIMPLEQ_INIT(&sc->sc_txfreeq); 698 SIMPLEQ_INIT(&sc->sc_txdirtyq); 699 700 /* 701 * Allocate the control data structures, and create and load the 702 * DMA map for it. 703 */ 704 if ((error = bus_dmamem_alloc(sc->sc_dmat, 705 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 706 0)) != 0) { 707 printf("%s: unable to allocate control data, error = %d\n", 708 sc->sc_dev.dv_xname, error); 709 goto fail_0; 710 } 711 712 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 713 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 714 BUS_DMA_COHERENT)) != 0) { 715 printf("%s: unable to map control data, error = %d\n", 716 sc->sc_dev.dv_xname, error); 717 goto fail_1; 718 } 719 720 if ((error = bus_dmamap_create(sc->sc_dmat, 721 sizeof(struct sip_control_data), 1, 722 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 723 printf("%s: unable to create control data DMA map, " 724 "error = %d\n", sc->sc_dev.dv_xname, error); 725 goto fail_2; 726 } 727 728 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 729 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 730 0)) != 0) { 731 printf("%s: unable to load control data DMA map, error = %d\n", 732 sc->sc_dev.dv_xname, error); 733 goto fail_3; 734 } 735 736 /* 737 * Create the transmit buffer DMA maps. 738 */ 739 for (i = 0; i < SIP_TXQUEUELEN; i++) { 740 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 741 SIP_NTXSEGS, MCLBYTES, 0, 0, 742 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 743 printf("%s: unable to create tx DMA map %d, " 744 "error = %d\n", sc->sc_dev.dv_xname, i, error); 745 goto fail_4; 746 } 747 } 748 749 /* 750 * Create the receive buffer DMA maps. 751 */ 752 for (i = 0; i < SIP_NRXDESC; i++) { 753 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 754 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 755 printf("%s: unable to create rx DMA map %d, " 756 "error = %d\n", sc->sc_dev.dv_xname, i, error); 757 goto fail_5; 758 } 759 sc->sc_rxsoft[i].rxs_mbuf = NULL; 760 } 761 762 /* 763 * Reset the chip to a known state. 764 */ 765 SIP_DECL(reset)(sc); 766 767 /* 768 * Read the Ethernet address from the EEPROM. This might 769 * also fetch other stuff from the EEPROM and stash it 770 * in the softc. 771 */ 772 sc->sc_cfg = 0; 773 #if !defined(DP83820) 774 if (SIP_SIS900_REV(sc,SIS_REV_635) || 775 SIP_SIS900_REV(sc,SIS_REV_900B)) 776 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 777 #endif 778 779 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 780 781 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 782 ether_sprintf(enaddr)); 783 784 /* 785 * Initialize the configuration register: aggressive PCI 786 * bus request algorithm, default backoff, default OW timer, 787 * default parity error detection. 788 * 789 * NOTE: "Big endian mode" is useless on the SiS900 and 790 * friends -- it affects packet data, not descriptors. 791 */ 792 #ifdef DP83820 793 /* 794 * Cause the chip to load configuration data from the EEPROM. 795 */ 796 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 797 for (i = 0; i < 10000; i++) { 798 delay(10); 799 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 800 PTSCR_EELOAD_EN) == 0) 801 break; 802 } 803 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 804 PTSCR_EELOAD_EN) { 805 printf("%s: timeout loading configuration from EEPROM\n", 806 sc->sc_dev.dv_xname); 807 return; 808 } 809 810 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 811 if (reg & CFG_PCI64_DET) { 812 printf("%s: 64-bit PCI slot detected\n", sc->sc_dev.dv_xname); 813 if (reg & CFG_DATA64_EN) 814 sc->sc_cfg |= CFG_DATA64_EN; 815 else 816 printf("%s: 64-bit data transfers disabled in EEPROM\n", 817 sc->sc_dev.dv_xname); 818 } 819 820 /* 821 * XXX Need some PCI flags indicating support for 822 * XXX 64-bit addressing. 823 */ 824 #if 0 825 if (reg & CFG_M64ADDR) 826 sc->sc_cfg |= CFG_M64ADDR; 827 if (reg & CFG_T64ADDR) 828 sc->sc_cfg |= CFG_T64ADDR; 829 #endif 830 831 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 832 const char *sep = ""; 833 printf("%s: using ", sc->sc_dev.dv_xname); 834 if (reg & CFG_EXT_125) { 835 sc->sc_cfg |= CFG_EXT_125; 836 printf("%s125MHz clock", sep); 837 sep = ", "; 838 } 839 if (reg & CFG_TBI_EN) { 840 sc->sc_cfg |= CFG_TBI_EN; 841 printf("%sten-bit interface", sep); 842 sep = ", "; 843 } 844 printf("\n"); 845 } 846 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 847 (reg & CFG_MRM_DIS) != 0) 848 sc->sc_cfg |= CFG_MRM_DIS; 849 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 850 (reg & CFG_MWI_DIS) != 0) 851 sc->sc_cfg |= CFG_MWI_DIS; 852 853 /* 854 * Use the extended descriptor format on the DP83820. This 855 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 856 * checksumming. 857 */ 858 sc->sc_cfg |= CFG_EXTSTS_EN; 859 #endif /* DP83820 */ 860 861 /* 862 * Initialize our media structures and probe the MII. 863 */ 864 sc->sc_mii.mii_ifp = ifp; 865 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 866 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 867 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 868 ifmedia_init(&sc->sc_mii.mii_media, 0, SIP_DECL(mediachange), 869 SIP_DECL(mediastatus)); 870 #ifdef DP83820 871 if (sc->sc_cfg & CFG_TBI_EN) { 872 /* Using ten-bit interface. */ 873 printf("%s: TBI -- FIXME\n", sc->sc_dev.dv_xname); 874 } else { 875 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 876 MII_OFFSET_ANY, 0); 877 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 878 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 879 0, NULL); 880 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 881 } else 882 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 883 } 884 #else 885 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 886 MII_OFFSET_ANY, 0); 887 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 888 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 889 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 890 } else 891 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 892 #endif /* DP83820 */ 893 894 ifp = &sc->sc_ethercom.ec_if; 895 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 896 ifp->if_softc = sc; 897 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 898 ifp->if_ioctl = SIP_DECL(ioctl); 899 ifp->if_start = SIP_DECL(start); 900 ifp->if_watchdog = SIP_DECL(watchdog); 901 ifp->if_init = SIP_DECL(init); 902 ifp->if_stop = SIP_DECL(stop); 903 IFQ_SET_READY(&ifp->if_snd); 904 905 /* 906 * We can support 802.1Q VLAN-sized frames. 907 */ 908 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 909 910 #ifdef DP83820 911 /* 912 * And the DP83820 can do VLAN tagging in hardware, and 913 * support the jumbo Ethernet MTU. 914 */ 915 sc->sc_ethercom.ec_capabilities |= 916 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 917 918 /* 919 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 920 * in hardware. 921 */ 922 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 923 IFCAP_CSUM_UDPv4; 924 #endif /* DP83820 */ 925 926 /* 927 * Attach the interface. 928 */ 929 if_attach(ifp); 930 ether_ifattach(ifp, enaddr); 931 932 /* 933 * The number of bytes that must be available in 934 * the Tx FIFO before the bus master can DMA more 935 * data into the FIFO. 936 */ 937 sc->sc_tx_fill_thresh = 64 / 32; 938 939 /* 940 * Start at a drain threshold of 512 bytes. We will 941 * increase it if a DMA underrun occurs. 942 * 943 * XXX The minimum value of this variable should be 944 * tuned. We may be able to improve performance 945 * by starting with a lower value. That, however, 946 * may trash the first few outgoing packets if the 947 * PCI bus is saturated. 948 */ 949 sc->sc_tx_drain_thresh = 1504 / 32; 950 951 /* 952 * Initialize the Rx FIFO drain threshold. 953 * 954 * This is in units of 8 bytes. 955 * 956 * We should never set this value lower than 2; 14 bytes are 957 * required to filter the packet. 958 */ 959 sc->sc_rx_drain_thresh = 128 / 8; 960 961 #ifdef SIP_EVENT_COUNTERS 962 /* 963 * Attach event counters. 964 */ 965 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 966 NULL, sc->sc_dev.dv_xname, "txsstall"); 967 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 968 NULL, sc->sc_dev.dv_xname, "txdstall"); 969 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 970 NULL, sc->sc_dev.dv_xname, "txforceintr"); 971 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 972 NULL, sc->sc_dev.dv_xname, "txdintr"); 973 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 974 NULL, sc->sc_dev.dv_xname, "txiintr"); 975 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 976 NULL, sc->sc_dev.dv_xname, "rxintr"); 977 #ifdef DP83820 978 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 979 NULL, sc->sc_dev.dv_xname, "rxipsum"); 980 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 981 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 982 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 983 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 984 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 985 NULL, sc->sc_dev.dv_xname, "txipsum"); 986 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 987 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 988 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 989 NULL, sc->sc_dev.dv_xname, "txudpsum"); 990 #endif /* DP83820 */ 991 #endif /* SIP_EVENT_COUNTERS */ 992 993 /* 994 * Make sure the interface is shutdown during reboot. 995 */ 996 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 997 if (sc->sc_sdhook == NULL) 998 printf("%s: WARNING: unable to establish shutdown hook\n", 999 sc->sc_dev.dv_xname); 1000 return; 1001 1002 /* 1003 * Free any resources we've allocated during the failed attach 1004 * attempt. Do this in reverse order and fall through. 1005 */ 1006 fail_5: 1007 for (i = 0; i < SIP_NRXDESC; i++) { 1008 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1009 bus_dmamap_destroy(sc->sc_dmat, 1010 sc->sc_rxsoft[i].rxs_dmamap); 1011 } 1012 fail_4: 1013 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1014 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1015 bus_dmamap_destroy(sc->sc_dmat, 1016 sc->sc_txsoft[i].txs_dmamap); 1017 } 1018 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1019 fail_3: 1020 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1021 fail_2: 1022 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1023 sizeof(struct sip_control_data)); 1024 fail_1: 1025 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1026 fail_0: 1027 return; 1028 } 1029 1030 /* 1031 * sip_shutdown: 1032 * 1033 * Make sure the interface is stopped at reboot time. 1034 */ 1035 void 1036 SIP_DECL(shutdown)(void *arg) 1037 { 1038 struct sip_softc *sc = arg; 1039 1040 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1041 } 1042 1043 /* 1044 * sip_start: [ifnet interface function] 1045 * 1046 * Start packet transmission on the interface. 1047 */ 1048 void 1049 SIP_DECL(start)(struct ifnet *ifp) 1050 { 1051 struct sip_softc *sc = ifp->if_softc; 1052 struct mbuf *m0, *m; 1053 struct sip_txsoft *txs; 1054 bus_dmamap_t dmamap; 1055 int error, nexttx, lasttx, seg; 1056 int ofree = sc->sc_txfree; 1057 #if 0 1058 int firsttx = sc->sc_txnext; 1059 #endif 1060 #ifdef DP83820 1061 u_int32_t extsts; 1062 #endif 1063 1064 /* 1065 * If we've been told to pause, don't transmit any more packets. 1066 */ 1067 if (sc->sc_flags & SIPF_PAUSED) 1068 ifp->if_flags |= IFF_OACTIVE; 1069 1070 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1071 return; 1072 1073 /* 1074 * Loop through the send queue, setting up transmit descriptors 1075 * until we drain the queue, or use up all available transmit 1076 * descriptors. 1077 */ 1078 for (;;) { 1079 /* Get a work queue entry. */ 1080 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1081 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1082 break; 1083 } 1084 1085 /* 1086 * Grab a packet off the queue. 1087 */ 1088 IFQ_POLL(&ifp->if_snd, m0); 1089 if (m0 == NULL) 1090 break; 1091 #ifndef DP83820 1092 m = NULL; 1093 #endif 1094 1095 dmamap = txs->txs_dmamap; 1096 1097 #ifdef DP83820 1098 /* 1099 * Load the DMA map. If this fails, the packet either 1100 * didn't fit in the allotted number of segments, or we 1101 * were short on resources. For the too-many-segments 1102 * case, we simply report an error and drop the packet, 1103 * since we can't sanely copy a jumbo packet to a single 1104 * buffer. 1105 */ 1106 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1107 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1108 if (error) { 1109 if (error == EFBIG) { 1110 printf("%s: Tx packet consumes too many " 1111 "DMA segments, dropping...\n", 1112 sc->sc_dev.dv_xname); 1113 IFQ_DEQUEUE(&ifp->if_snd, m0); 1114 m_freem(m0); 1115 continue; 1116 } 1117 /* 1118 * Short on resources, just stop for now. 1119 */ 1120 break; 1121 } 1122 #else /* DP83820 */ 1123 /* 1124 * Load the DMA map. If this fails, the packet either 1125 * didn't fit in the alloted number of segments, or we 1126 * were short on resources. In this case, we'll copy 1127 * and try again. 1128 */ 1129 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1130 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1131 MGETHDR(m, M_DONTWAIT, MT_DATA); 1132 if (m == NULL) { 1133 printf("%s: unable to allocate Tx mbuf\n", 1134 sc->sc_dev.dv_xname); 1135 break; 1136 } 1137 if (m0->m_pkthdr.len > MHLEN) { 1138 MCLGET(m, M_DONTWAIT); 1139 if ((m->m_flags & M_EXT) == 0) { 1140 printf("%s: unable to allocate Tx " 1141 "cluster\n", sc->sc_dev.dv_xname); 1142 m_freem(m); 1143 break; 1144 } 1145 } 1146 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1147 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1148 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1149 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1150 if (error) { 1151 printf("%s: unable to load Tx buffer, " 1152 "error = %d\n", sc->sc_dev.dv_xname, error); 1153 break; 1154 } 1155 } 1156 #endif /* DP83820 */ 1157 1158 /* 1159 * Ensure we have enough descriptors free to describe 1160 * the packet. Note, we always reserve one descriptor 1161 * at the end of the ring as a termination point, to 1162 * prevent wrap-around. 1163 */ 1164 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1165 /* 1166 * Not enough free descriptors to transmit this 1167 * packet. We haven't committed anything yet, 1168 * so just unload the DMA map, put the packet 1169 * back on the queue, and punt. Notify the upper 1170 * layer that there are not more slots left. 1171 * 1172 * XXX We could allocate an mbuf and copy, but 1173 * XXX is it worth it? 1174 */ 1175 ifp->if_flags |= IFF_OACTIVE; 1176 bus_dmamap_unload(sc->sc_dmat, dmamap); 1177 #ifndef DP83820 1178 if (m != NULL) 1179 m_freem(m); 1180 #endif 1181 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1182 break; 1183 } 1184 1185 IFQ_DEQUEUE(&ifp->if_snd, m0); 1186 #ifndef DP83820 1187 if (m != NULL) { 1188 m_freem(m0); 1189 m0 = m; 1190 } 1191 #endif 1192 1193 /* 1194 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1195 */ 1196 1197 /* Sync the DMA map. */ 1198 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1199 BUS_DMASYNC_PREWRITE); 1200 1201 /* 1202 * Initialize the transmit descriptors. 1203 */ 1204 for (nexttx = sc->sc_txnext, seg = 0; 1205 seg < dmamap->dm_nsegs; 1206 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1207 /* 1208 * If this is the first descriptor we're 1209 * enqueueing, don't set the OWN bit just 1210 * yet. That could cause a race condition. 1211 * We'll do it below. 1212 */ 1213 sc->sc_txdescs[nexttx].sipd_bufptr = 1214 htole32(dmamap->dm_segs[seg].ds_addr); 1215 sc->sc_txdescs[nexttx].sipd_cmdsts = 1216 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1217 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1218 #ifdef DP83820 1219 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1220 #endif /* DP83820 */ 1221 lasttx = nexttx; 1222 } 1223 1224 /* Clear the MORE bit on the last segment. */ 1225 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1226 1227 /* 1228 * If we're in the interrupt delay window, delay the 1229 * interrupt. 1230 */ 1231 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1232 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1233 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1234 htole32(CMDSTS_INTR); 1235 sc->sc_txwin = 0; 1236 } 1237 1238 #ifdef DP83820 1239 /* 1240 * If VLANs are enabled and the packet has a VLAN tag, set 1241 * up the descriptor to encapsulate the packet for us. 1242 * 1243 * This apparently has to be on the last descriptor of 1244 * the packet. 1245 */ 1246 if (sc->sc_ethercom.ec_nvlans != 0 && 1247 (m = m_aux_find(m0, AF_LINK, ETHERTYPE_VLAN)) != NULL) { 1248 sc->sc_txdescs[lasttx].sipd_extsts |= 1249 htole32(EXTSTS_VPKT | 1250 htons(*mtod(m, int *) & EXTSTS_VTCI)); 1251 } 1252 1253 /* 1254 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1255 * checksumming, set up the descriptor to do this work 1256 * for us. 1257 * 1258 * This apparently has to be on the first descriptor of 1259 * the packet. 1260 * 1261 * Byte-swap constants so the compiler can optimize. 1262 */ 1263 extsts = 0; 1264 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1265 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1266 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1267 extsts |= htole32(EXTSTS_IPPKT); 1268 } 1269 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1270 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1271 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1272 extsts |= htole32(EXTSTS_TCPPKT); 1273 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1274 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1275 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1276 extsts |= htole32(EXTSTS_UDPPKT); 1277 } 1278 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1279 #endif /* DP83820 */ 1280 1281 /* Sync the descriptors we're using. */ 1282 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1283 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1284 1285 /* 1286 * The entire packet is set up. Give the first descrptor 1287 * to the chip now. 1288 */ 1289 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1290 htole32(CMDSTS_OWN); 1291 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1292 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1293 1294 /* 1295 * Store a pointer to the packet so we can free it later, 1296 * and remember what txdirty will be once the packet is 1297 * done. 1298 */ 1299 txs->txs_mbuf = m0; 1300 txs->txs_firstdesc = sc->sc_txnext; 1301 txs->txs_lastdesc = lasttx; 1302 1303 /* Advance the tx pointer. */ 1304 sc->sc_txfree -= dmamap->dm_nsegs; 1305 sc->sc_txnext = nexttx; 1306 1307 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1308 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1309 1310 #if NBPFILTER > 0 1311 /* 1312 * Pass the packet to any BPF listeners. 1313 */ 1314 if (ifp->if_bpf) 1315 bpf_mtap(ifp->if_bpf, m0); 1316 #endif /* NBPFILTER > 0 */ 1317 } 1318 1319 if (txs == NULL || sc->sc_txfree == 0) { 1320 /* No more slots left; notify upper layer. */ 1321 ifp->if_flags |= IFF_OACTIVE; 1322 } 1323 1324 if (sc->sc_txfree != ofree) { 1325 /* 1326 * Start the transmit process. Note, the manual says 1327 * that if there are no pending transmissions in the 1328 * chip's internal queue (indicated by TXE being clear), 1329 * then the driver software must set the TXDP to the 1330 * first descriptor to be transmitted. However, if we 1331 * do this, it causes serious performance degredation on 1332 * the DP83820 under load, not setting TXDP doesn't seem 1333 * to adversely affect the SiS 900 or DP83815. 1334 * 1335 * Well, I guess it wouldn't be the first time a manual 1336 * has lied -- and they could be speaking of the NULL- 1337 * terminated descriptor list case, rather than OWN- 1338 * terminated rings. 1339 */ 1340 #if 0 1341 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1342 CR_TXE) == 0) { 1343 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1344 SIP_CDTXADDR(sc, firsttx)); 1345 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1346 } 1347 #else 1348 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1349 #endif 1350 1351 /* Set a watchdog timer in case the chip flakes out. */ 1352 ifp->if_timer = 5; 1353 } 1354 } 1355 1356 /* 1357 * sip_watchdog: [ifnet interface function] 1358 * 1359 * Watchdog timer handler. 1360 */ 1361 void 1362 SIP_DECL(watchdog)(struct ifnet *ifp) 1363 { 1364 struct sip_softc *sc = ifp->if_softc; 1365 1366 /* 1367 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1368 * If we get a timeout, try and sweep up transmit descriptors. 1369 * If we manage to sweep them all up, ignore the lack of 1370 * interrupt. 1371 */ 1372 SIP_DECL(txintr)(sc); 1373 1374 if (sc->sc_txfree != SIP_NTXDESC) { 1375 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1376 ifp->if_oerrors++; 1377 1378 /* Reset the interface. */ 1379 (void) SIP_DECL(init)(ifp); 1380 } else if (ifp->if_flags & IFF_DEBUG) 1381 printf("%s: recovered from device timeout\n", 1382 sc->sc_dev.dv_xname); 1383 1384 /* Try to get more packets going. */ 1385 SIP_DECL(start)(ifp); 1386 } 1387 1388 /* 1389 * sip_ioctl: [ifnet interface function] 1390 * 1391 * Handle control requests from the operator. 1392 */ 1393 int 1394 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1395 { 1396 struct sip_softc *sc = ifp->if_softc; 1397 struct ifreq *ifr = (struct ifreq *)data; 1398 int s, error; 1399 1400 s = splnet(); 1401 1402 switch (cmd) { 1403 case SIOCSIFMEDIA: 1404 case SIOCGIFMEDIA: 1405 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1406 break; 1407 1408 default: 1409 error = ether_ioctl(ifp, cmd, data); 1410 if (error == ENETRESET) { 1411 /* 1412 * Multicast list has changed; set the hardware filter 1413 * accordingly. 1414 */ 1415 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1416 error = 0; 1417 } 1418 break; 1419 } 1420 1421 /* Try to get more packets going. */ 1422 SIP_DECL(start)(ifp); 1423 1424 splx(s); 1425 return (error); 1426 } 1427 1428 /* 1429 * sip_intr: 1430 * 1431 * Interrupt service routine. 1432 */ 1433 int 1434 SIP_DECL(intr)(void *arg) 1435 { 1436 struct sip_softc *sc = arg; 1437 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1438 u_int32_t isr; 1439 int handled = 0; 1440 1441 for (;;) { 1442 /* Reading clears interrupt. */ 1443 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1444 if ((isr & sc->sc_imr) == 0) 1445 break; 1446 1447 handled = 1; 1448 1449 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1450 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1451 1452 /* Grab any new packets. */ 1453 SIP_DECL(rxintr)(sc); 1454 1455 if (isr & ISR_RXORN) { 1456 printf("%s: receive FIFO overrun\n", 1457 sc->sc_dev.dv_xname); 1458 1459 /* XXX adjust rx_drain_thresh? */ 1460 } 1461 1462 if (isr & ISR_RXIDLE) { 1463 printf("%s: receive ring overrun\n", 1464 sc->sc_dev.dv_xname); 1465 1466 /* Get the receive process going again. */ 1467 bus_space_write_4(sc->sc_st, sc->sc_sh, 1468 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1469 bus_space_write_4(sc->sc_st, sc->sc_sh, 1470 SIP_CR, CR_RXE); 1471 } 1472 } 1473 1474 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1475 #ifdef SIP_EVENT_COUNTERS 1476 if (isr & ISR_TXDESC) 1477 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1478 else if (isr & ISR_TXIDLE) 1479 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1480 #endif 1481 1482 /* Sweep up transmit descriptors. */ 1483 SIP_DECL(txintr)(sc); 1484 1485 if (isr & ISR_TXURN) { 1486 u_int32_t thresh; 1487 1488 printf("%s: transmit FIFO underrun", 1489 sc->sc_dev.dv_xname); 1490 1491 thresh = sc->sc_tx_drain_thresh + 1; 1492 if (thresh <= TXCFG_DRTH && 1493 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1494 (sc->sc_tx_fill_thresh * 32))) { 1495 printf("; increasing Tx drain " 1496 "threshold to %u bytes\n", 1497 thresh * 32); 1498 sc->sc_tx_drain_thresh = thresh; 1499 (void) SIP_DECL(init)(ifp); 1500 } else { 1501 (void) SIP_DECL(init)(ifp); 1502 printf("\n"); 1503 } 1504 } 1505 } 1506 1507 #if !defined(DP83820) 1508 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1509 if (isr & ISR_PAUSE_ST) { 1510 sc->sc_flags |= SIPF_PAUSED; 1511 ifp->if_flags |= IFF_OACTIVE; 1512 } 1513 if (isr & ISR_PAUSE_END) { 1514 sc->sc_flags &= ~SIPF_PAUSED; 1515 ifp->if_flags &= ~IFF_OACTIVE; 1516 } 1517 } 1518 #endif /* ! DP83820 */ 1519 1520 if (isr & ISR_HIBERR) { 1521 #define PRINTERR(bit, str) \ 1522 if (isr & (bit)) \ 1523 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1524 PRINTERR(ISR_DPERR, "parity error"); 1525 PRINTERR(ISR_SSERR, "system error"); 1526 PRINTERR(ISR_RMABT, "master abort"); 1527 PRINTERR(ISR_RTABT, "target abort"); 1528 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1529 (void) SIP_DECL(init)(ifp); 1530 #undef PRINTERR 1531 } 1532 } 1533 1534 /* Try to get more packets going. */ 1535 SIP_DECL(start)(ifp); 1536 1537 return (handled); 1538 } 1539 1540 /* 1541 * sip_txintr: 1542 * 1543 * Helper; handle transmit interrupts. 1544 */ 1545 void 1546 SIP_DECL(txintr)(struct sip_softc *sc) 1547 { 1548 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1549 struct sip_txsoft *txs; 1550 u_int32_t cmdsts; 1551 1552 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1553 ifp->if_flags &= ~IFF_OACTIVE; 1554 1555 /* 1556 * Go through our Tx list and free mbufs for those 1557 * frames which have been transmitted. 1558 */ 1559 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1560 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1561 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1562 1563 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1564 if (cmdsts & CMDSTS_OWN) 1565 break; 1566 1567 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1568 1569 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1570 1571 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1572 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1573 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1574 m_freem(txs->txs_mbuf); 1575 txs->txs_mbuf = NULL; 1576 1577 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1578 1579 /* 1580 * Check for errors and collisions. 1581 */ 1582 if (cmdsts & 1583 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1584 ifp->if_oerrors++; 1585 if (cmdsts & CMDSTS_Tx_EC) 1586 ifp->if_collisions += 16; 1587 if (ifp->if_flags & IFF_DEBUG) { 1588 if (cmdsts & CMDSTS_Tx_ED) 1589 printf("%s: excessive deferral\n", 1590 sc->sc_dev.dv_xname); 1591 if (cmdsts & CMDSTS_Tx_EC) 1592 printf("%s: excessive collisions\n", 1593 sc->sc_dev.dv_xname); 1594 } 1595 } else { 1596 /* Packet was transmitted successfully. */ 1597 ifp->if_opackets++; 1598 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1599 } 1600 } 1601 1602 /* 1603 * If there are no more pending transmissions, cancel the watchdog 1604 * timer. 1605 */ 1606 if (txs == NULL) { 1607 ifp->if_timer = 0; 1608 sc->sc_txwin = 0; 1609 } 1610 } 1611 1612 #if defined(DP83820) 1613 /* 1614 * sip_rxintr: 1615 * 1616 * Helper; handle receive interrupts. 1617 */ 1618 void 1619 SIP_DECL(rxintr)(struct sip_softc *sc) 1620 { 1621 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1622 struct sip_rxsoft *rxs; 1623 struct mbuf *m, *tailm; 1624 u_int32_t cmdsts, extsts; 1625 int i, len; 1626 1627 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1628 rxs = &sc->sc_rxsoft[i]; 1629 1630 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1631 1632 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1633 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1634 1635 /* 1636 * NOTE: OWN is set if owned by _consumer_. We're the 1637 * consumer of the receive ring, so if the bit is clear, 1638 * we have processed all of the packets. 1639 */ 1640 if ((cmdsts & CMDSTS_OWN) == 0) { 1641 /* 1642 * We have processed all of the receive buffers. 1643 */ 1644 break; 1645 } 1646 1647 if (__predict_false(sc->sc_rxdiscard)) { 1648 SIP_INIT_RXDESC(sc, i); 1649 if ((cmdsts & CMDSTS_MORE) == 0) { 1650 /* Reset our state. */ 1651 sc->sc_rxdiscard = 0; 1652 } 1653 continue; 1654 } 1655 1656 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1657 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1658 1659 m = rxs->rxs_mbuf; 1660 1661 /* 1662 * Add a new receive buffer to the ring. 1663 */ 1664 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1665 /* 1666 * Failed, throw away what we've done so 1667 * far, and discard the rest of the packet. 1668 */ 1669 ifp->if_ierrors++; 1670 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1671 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1672 SIP_INIT_RXDESC(sc, i); 1673 if (cmdsts & CMDSTS_MORE) 1674 sc->sc_rxdiscard = 1; 1675 if (sc->sc_rxhead != NULL) 1676 m_freem(sc->sc_rxhead); 1677 SIP_RXCHAIN_RESET(sc); 1678 continue; 1679 } 1680 1681 SIP_RXCHAIN_LINK(sc, m); 1682 1683 /* 1684 * If this is not the end of the packet, keep 1685 * looking. 1686 */ 1687 if (cmdsts & CMDSTS_MORE) { 1688 sc->sc_rxlen += m->m_len; 1689 continue; 1690 } 1691 1692 /* 1693 * Okay, we have the entire packet now... 1694 */ 1695 *sc->sc_rxtailp = NULL; 1696 m = sc->sc_rxhead; 1697 tailm = sc->sc_rxtail; 1698 1699 SIP_RXCHAIN_RESET(sc); 1700 1701 /* 1702 * If an error occurred, update stats and drop the packet. 1703 */ 1704 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1705 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1706 ifp->if_ierrors++; 1707 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1708 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1709 /* Receive overrun handled elsewhere. */ 1710 printf("%s: receive descriptor error\n", 1711 sc->sc_dev.dv_xname); 1712 } 1713 #define PRINTERR(bit, str) \ 1714 if (cmdsts & (bit)) \ 1715 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1716 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1717 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1718 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1719 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1720 #undef PRINTERR 1721 m_freem(m); 1722 continue; 1723 } 1724 1725 /* 1726 * No errors. 1727 * 1728 * Note, the DP83820 includes the CRC with 1729 * every packet. 1730 */ 1731 len = CMDSTS_SIZE(cmdsts); 1732 tailm->m_len = len - sc->sc_rxlen; 1733 1734 /* 1735 * If the packet is small enough to fit in a 1736 * single header mbuf, allocate one and copy 1737 * the data into it. This greatly reduces 1738 * memory consumption when we receive lots 1739 * of small packets. 1740 */ 1741 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1742 struct mbuf *nm; 1743 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1744 if (nm == NULL) { 1745 ifp->if_ierrors++; 1746 m_freem(m); 1747 continue; 1748 } 1749 nm->m_data += 2; 1750 nm->m_pkthdr.len = nm->m_len = len; 1751 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1752 m_freem(m); 1753 m = nm; 1754 } 1755 #ifndef __NO_STRICT_ALIGNMENT 1756 else { 1757 /* 1758 * The DP83820's receive buffers must be 4-byte 1759 * aligned. But this means that the data after 1760 * the Ethernet header is misaligned. To compensate, 1761 * we have artificially shortened the buffer size 1762 * in the descriptor, and we do an overlapping copy 1763 * of the data two bytes further in (in the first 1764 * buffer of the chain only). 1765 */ 1766 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1767 m->m_len); 1768 m->m_data += 2; 1769 } 1770 #endif /* ! __NO_STRICT_ALIGNMENT */ 1771 1772 /* 1773 * If VLANs are enabled, VLAN packets have been unwrapped 1774 * for us. Associate the tag with the packet. 1775 */ 1776 if (sc->sc_ethercom.ec_nvlans != 0 && 1777 (extsts & EXTSTS_VPKT) != 0) { 1778 struct mbuf *vtag; 1779 1780 vtag = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 1781 if (vtag == NULL) { 1782 ifp->if_ierrors++; 1783 printf("%s: unable to allocate VLAN tag\n", 1784 sc->sc_dev.dv_xname); 1785 m_freem(m); 1786 continue; 1787 } 1788 1789 *mtod(vtag, int *) = ntohs(extsts & EXTSTS_VTCI); 1790 vtag->m_len = sizeof(int); 1791 } 1792 1793 /* 1794 * Set the incoming checksum information for the 1795 * packet. 1796 */ 1797 if ((extsts & EXTSTS_IPPKT) != 0) { 1798 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1799 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1800 if (extsts & EXTSTS_Rx_IPERR) 1801 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1802 if (extsts & EXTSTS_TCPPKT) { 1803 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1804 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1805 if (extsts & EXTSTS_Rx_TCPERR) 1806 m->m_pkthdr.csum_flags |= 1807 M_CSUM_TCP_UDP_BAD; 1808 } else if (extsts & EXTSTS_UDPPKT) { 1809 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1810 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1811 if (extsts & EXTSTS_Rx_UDPERR) 1812 m->m_pkthdr.csum_flags |= 1813 M_CSUM_TCP_UDP_BAD; 1814 } 1815 } 1816 1817 ifp->if_ipackets++; 1818 m->m_flags |= M_HASFCS; 1819 m->m_pkthdr.rcvif = ifp; 1820 m->m_pkthdr.len = len; 1821 1822 #if NBPFILTER > 0 1823 /* 1824 * Pass this up to any BPF listeners, but only 1825 * pass if up the stack if it's for us. 1826 */ 1827 if (ifp->if_bpf) 1828 bpf_mtap(ifp->if_bpf, m); 1829 #endif /* NBPFILTER > 0 */ 1830 1831 /* Pass it on. */ 1832 (*ifp->if_input)(ifp, m); 1833 } 1834 1835 /* Update the receive pointer. */ 1836 sc->sc_rxptr = i; 1837 } 1838 #else /* ! DP83820 */ 1839 /* 1840 * sip_rxintr: 1841 * 1842 * Helper; handle receive interrupts. 1843 */ 1844 void 1845 SIP_DECL(rxintr)(struct sip_softc *sc) 1846 { 1847 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1848 struct sip_rxsoft *rxs; 1849 struct mbuf *m; 1850 u_int32_t cmdsts; 1851 int i, len; 1852 1853 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1854 rxs = &sc->sc_rxsoft[i]; 1855 1856 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1857 1858 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1859 1860 /* 1861 * NOTE: OWN is set if owned by _consumer_. We're the 1862 * consumer of the receive ring, so if the bit is clear, 1863 * we have processed all of the packets. 1864 */ 1865 if ((cmdsts & CMDSTS_OWN) == 0) { 1866 /* 1867 * We have processed all of the receive buffers. 1868 */ 1869 break; 1870 } 1871 1872 /* 1873 * If any collisions were seen on the wire, count one. 1874 */ 1875 if (cmdsts & CMDSTS_Rx_COL) 1876 ifp->if_collisions++; 1877 1878 /* 1879 * If an error occurred, update stats, clear the status 1880 * word, and leave the packet buffer in place. It will 1881 * simply be reused the next time the ring comes around. 1882 */ 1883 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1884 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1885 ifp->if_ierrors++; 1886 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1887 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1888 /* Receive overrun handled elsewhere. */ 1889 printf("%s: receive descriptor error\n", 1890 sc->sc_dev.dv_xname); 1891 } 1892 #define PRINTERR(bit, str) \ 1893 if (cmdsts & (bit)) \ 1894 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1895 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1896 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1897 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1898 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1899 #undef PRINTERR 1900 SIP_INIT_RXDESC(sc, i); 1901 continue; 1902 } 1903 1904 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1905 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1906 1907 /* 1908 * No errors; receive the packet. Note, the SiS 900 1909 * includes the CRC with every packet. 1910 */ 1911 len = CMDSTS_SIZE(cmdsts); 1912 1913 #ifdef __NO_STRICT_ALIGNMENT 1914 /* 1915 * If the packet is small enough to fit in a 1916 * single header mbuf, allocate one and copy 1917 * the data into it. This greatly reduces 1918 * memory consumption when we receive lots 1919 * of small packets. 1920 * 1921 * Otherwise, we add a new buffer to the receive 1922 * chain. If this fails, we drop the packet and 1923 * recycle the old buffer. 1924 */ 1925 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 1926 MGETHDR(m, M_DONTWAIT, MT_DATA); 1927 if (m == NULL) 1928 goto dropit; 1929 memcpy(mtod(m, caddr_t), 1930 mtod(rxs->rxs_mbuf, caddr_t), len); 1931 SIP_INIT_RXDESC(sc, i); 1932 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1933 rxs->rxs_dmamap->dm_mapsize, 1934 BUS_DMASYNC_PREREAD); 1935 } else { 1936 m = rxs->rxs_mbuf; 1937 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1938 dropit: 1939 ifp->if_ierrors++; 1940 SIP_INIT_RXDESC(sc, i); 1941 bus_dmamap_sync(sc->sc_dmat, 1942 rxs->rxs_dmamap, 0, 1943 rxs->rxs_dmamap->dm_mapsize, 1944 BUS_DMASYNC_PREREAD); 1945 continue; 1946 } 1947 } 1948 #else 1949 /* 1950 * The SiS 900's receive buffers must be 4-byte aligned. 1951 * But this means that the data after the Ethernet header 1952 * is misaligned. We must allocate a new buffer and 1953 * copy the data, shifted forward 2 bytes. 1954 */ 1955 MGETHDR(m, M_DONTWAIT, MT_DATA); 1956 if (m == NULL) { 1957 dropit: 1958 ifp->if_ierrors++; 1959 SIP_INIT_RXDESC(sc, i); 1960 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1961 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1962 continue; 1963 } 1964 if (len > (MHLEN - 2)) { 1965 MCLGET(m, M_DONTWAIT); 1966 if ((m->m_flags & M_EXT) == 0) { 1967 m_freem(m); 1968 goto dropit; 1969 } 1970 } 1971 m->m_data += 2; 1972 1973 /* 1974 * Note that we use clusters for incoming frames, so the 1975 * buffer is virtually contiguous. 1976 */ 1977 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 1978 1979 /* Allow the receive descriptor to continue using its mbuf. */ 1980 SIP_INIT_RXDESC(sc, i); 1981 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1982 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1983 #endif /* __NO_STRICT_ALIGNMENT */ 1984 1985 ifp->if_ipackets++; 1986 m->m_flags |= M_HASFCS; 1987 m->m_pkthdr.rcvif = ifp; 1988 m->m_pkthdr.len = m->m_len = len; 1989 1990 #if NBPFILTER > 0 1991 /* 1992 * Pass this up to any BPF listeners, but only 1993 * pass if up the stack if it's for us. 1994 */ 1995 if (ifp->if_bpf) 1996 bpf_mtap(ifp->if_bpf, m); 1997 #endif /* NBPFILTER > 0 */ 1998 1999 /* Pass it on. */ 2000 (*ifp->if_input)(ifp, m); 2001 } 2002 2003 /* Update the receive pointer. */ 2004 sc->sc_rxptr = i; 2005 } 2006 #endif /* DP83820 */ 2007 2008 /* 2009 * sip_tick: 2010 * 2011 * One second timer, used to tick the MII. 2012 */ 2013 void 2014 SIP_DECL(tick)(void *arg) 2015 { 2016 struct sip_softc *sc = arg; 2017 int s; 2018 2019 s = splnet(); 2020 mii_tick(&sc->sc_mii); 2021 splx(s); 2022 2023 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2024 } 2025 2026 /* 2027 * sip_reset: 2028 * 2029 * Perform a soft reset on the SiS 900. 2030 */ 2031 void 2032 SIP_DECL(reset)(struct sip_softc *sc) 2033 { 2034 bus_space_tag_t st = sc->sc_st; 2035 bus_space_handle_t sh = sc->sc_sh; 2036 int i; 2037 2038 bus_space_write_4(st, sh, SIP_IER, 0); 2039 bus_space_write_4(st, sh, SIP_IMR, 0); 2040 bus_space_write_4(st, sh, SIP_RFCR, 0); 2041 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2042 2043 for (i = 0; i < SIP_TIMEOUT; i++) { 2044 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2045 break; 2046 delay(2); 2047 } 2048 2049 if (i == SIP_TIMEOUT) 2050 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2051 2052 delay(1000); 2053 2054 #ifdef DP83820 2055 /* 2056 * Set the general purpose I/O bits. Do it here in case we 2057 * need to have GPIO set up to talk to the media interface. 2058 */ 2059 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2060 delay(1000); 2061 #endif /* DP83820 */ 2062 } 2063 2064 /* 2065 * sip_init: [ ifnet interface function ] 2066 * 2067 * Initialize the interface. Must be called at splnet(). 2068 */ 2069 int 2070 SIP_DECL(init)(struct ifnet *ifp) 2071 { 2072 struct sip_softc *sc = ifp->if_softc; 2073 bus_space_tag_t st = sc->sc_st; 2074 bus_space_handle_t sh = sc->sc_sh; 2075 struct sip_txsoft *txs; 2076 struct sip_rxsoft *rxs; 2077 struct sip_desc *sipd; 2078 u_int32_t reg; 2079 int i, error = 0; 2080 2081 /* 2082 * Cancel any pending I/O. 2083 */ 2084 SIP_DECL(stop)(ifp, 0); 2085 2086 /* 2087 * Reset the chip to a known state. 2088 */ 2089 SIP_DECL(reset)(sc); 2090 2091 #if !defined(DP83820) 2092 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2093 /* 2094 * DP83815 manual, page 78: 2095 * 4.4 Recommended Registers Configuration 2096 * For optimum performance of the DP83815, version noted 2097 * as DP83815CVNG (SRR = 203h), the listed register 2098 * modifications must be followed in sequence... 2099 * 2100 * It's not clear if this should be 302h or 203h because that 2101 * chip name is listed as SRR 302h in the description of the 2102 * SRR register. However, my revision 302h DP83815 on the 2103 * Netgear FA311 purchased in 02/2001 needs these settings 2104 * to avoid tons of errors in AcceptPerfectMatch (non- 2105 * IFF_PROMISC) mode. I do not know if other revisions need 2106 * this set or not. [briggs -- 09 March 2001] 2107 * 2108 * Note that only the low-order 12 bits of 0xe4 are documented 2109 * and that this sets reserved bits in that register. 2110 */ 2111 reg = bus_space_read_4(st, sh, SIP_NS_SRR); 2112 if (reg == 0x302) { 2113 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2114 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2115 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2116 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2117 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2118 } 2119 } 2120 #endif /* ! DP83820 */ 2121 2122 /* 2123 * Initialize the transmit descriptor ring. 2124 */ 2125 for (i = 0; i < SIP_NTXDESC; i++) { 2126 sipd = &sc->sc_txdescs[i]; 2127 memset(sipd, 0, sizeof(struct sip_desc)); 2128 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2129 } 2130 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2131 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2132 sc->sc_txfree = SIP_NTXDESC; 2133 sc->sc_txnext = 0; 2134 sc->sc_txwin = 0; 2135 2136 /* 2137 * Initialize the transmit job descriptors. 2138 */ 2139 SIMPLEQ_INIT(&sc->sc_txfreeq); 2140 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2141 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2142 txs = &sc->sc_txsoft[i]; 2143 txs->txs_mbuf = NULL; 2144 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2145 } 2146 2147 /* 2148 * Initialize the receive descriptor and receive job 2149 * descriptor rings. 2150 */ 2151 for (i = 0; i < SIP_NRXDESC; i++) { 2152 rxs = &sc->sc_rxsoft[i]; 2153 if (rxs->rxs_mbuf == NULL) { 2154 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2155 printf("%s: unable to allocate or map rx " 2156 "buffer %d, error = %d\n", 2157 sc->sc_dev.dv_xname, i, error); 2158 /* 2159 * XXX Should attempt to run with fewer receive 2160 * XXX buffers instead of just failing. 2161 */ 2162 SIP_DECL(rxdrain)(sc); 2163 goto out; 2164 } 2165 } else 2166 SIP_INIT_RXDESC(sc, i); 2167 } 2168 sc->sc_rxptr = 0; 2169 #ifdef DP83820 2170 sc->sc_rxdiscard = 0; 2171 SIP_RXCHAIN_RESET(sc); 2172 #endif /* DP83820 */ 2173 2174 /* 2175 * Set the configuration register; it's already initialized 2176 * in sip_attach(). 2177 */ 2178 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2179 2180 /* 2181 * Initialize the prototype TXCFG register. 2182 */ 2183 #if defined(DP83820) 2184 sc->sc_txcfg = TXCFG_MXDMA_512; 2185 sc->sc_rxcfg = RXCFG_MXDMA_512; 2186 #else 2187 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2188 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2189 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & CFG_EDBMASTEN)) { 2190 sc->sc_txcfg = TXCFG_MXDMA_64; 2191 sc->sc_rxcfg = RXCFG_MXDMA_64; 2192 } else { 2193 sc->sc_txcfg = TXCFG_MXDMA_512; 2194 sc->sc_rxcfg = RXCFG_MXDMA_512; 2195 } 2196 #endif /* DP83820 */ 2197 2198 sc->sc_txcfg |= TXCFG_ATP | 2199 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2200 sc->sc_tx_drain_thresh; 2201 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2202 2203 /* 2204 * Initialize the receive drain threshold if we have never 2205 * done so. 2206 */ 2207 if (sc->sc_rx_drain_thresh == 0) { 2208 /* 2209 * XXX This value should be tuned. This is set to the 2210 * maximum of 248 bytes, and we may be able to improve 2211 * performance by decreasing it (although we should never 2212 * set this value lower than 2; 14 bytes are required to 2213 * filter the packet). 2214 */ 2215 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2216 } 2217 2218 /* 2219 * Initialize the prototype RXCFG register. 2220 */ 2221 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2222 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2223 2224 #ifdef DP83820 2225 /* 2226 * Initialize the VLAN/IP receive control register. 2227 * We enable checksum computation on all incoming 2228 * packets, and do not reject packets w/ bad checksums. 2229 */ 2230 reg = 0; 2231 if (ifp->if_capenable & 2232 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2233 reg |= VRCR_IPEN; 2234 if (sc->sc_ethercom.ec_nvlans != 0) 2235 reg |= VRCR_VTDEN|VRCR_VTREN; 2236 bus_space_write_4(st, sh, SIP_VRCR, reg); 2237 2238 /* 2239 * Initialize the VLAN/IP transmit control register. 2240 * We enable outgoing checksum computation on a 2241 * per-packet basis. 2242 */ 2243 reg = 0; 2244 if (ifp->if_capenable & 2245 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2246 reg |= VTCR_PPCHK; 2247 if (sc->sc_ethercom.ec_nvlans != 0) 2248 reg |= VTCR_VPPTI; 2249 bus_space_write_4(st, sh, SIP_VTCR, reg); 2250 2251 /* 2252 * If we're using VLANs, initialize the VLAN data register. 2253 * To understand why we bswap the VLAN Ethertype, see section 2254 * 4.2.36 of the DP83820 manual. 2255 */ 2256 if (sc->sc_ethercom.ec_nvlans != 0) 2257 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2258 #endif /* DP83820 */ 2259 2260 /* 2261 * Give the transmit and receive rings to the chip. 2262 */ 2263 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2264 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2265 2266 /* 2267 * Initialize the interrupt mask. 2268 */ 2269 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2270 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2271 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2272 2273 /* Set up the receive filter. */ 2274 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2275 2276 /* 2277 * Set the current media. Do this after initializing the prototype 2278 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2279 * control. 2280 */ 2281 mii_mediachg(&sc->sc_mii); 2282 2283 /* 2284 * Enable interrupts. 2285 */ 2286 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2287 2288 /* 2289 * Start the transmit and receive processes. 2290 */ 2291 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2292 2293 /* 2294 * Start the one second MII clock. 2295 */ 2296 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2297 2298 /* 2299 * ...all done! 2300 */ 2301 ifp->if_flags |= IFF_RUNNING; 2302 ifp->if_flags &= ~IFF_OACTIVE; 2303 2304 out: 2305 if (error) 2306 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2307 return (error); 2308 } 2309 2310 /* 2311 * sip_drain: 2312 * 2313 * Drain the receive queue. 2314 */ 2315 void 2316 SIP_DECL(rxdrain)(struct sip_softc *sc) 2317 { 2318 struct sip_rxsoft *rxs; 2319 int i; 2320 2321 for (i = 0; i < SIP_NRXDESC; i++) { 2322 rxs = &sc->sc_rxsoft[i]; 2323 if (rxs->rxs_mbuf != NULL) { 2324 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2325 m_freem(rxs->rxs_mbuf); 2326 rxs->rxs_mbuf = NULL; 2327 } 2328 } 2329 } 2330 2331 /* 2332 * sip_stop: [ ifnet interface function ] 2333 * 2334 * Stop transmission on the interface. 2335 */ 2336 void 2337 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2338 { 2339 struct sip_softc *sc = ifp->if_softc; 2340 bus_space_tag_t st = sc->sc_st; 2341 bus_space_handle_t sh = sc->sc_sh; 2342 struct sip_txsoft *txs; 2343 u_int32_t cmdsts = 0; /* DEBUG */ 2344 2345 /* 2346 * Stop the one second clock. 2347 */ 2348 callout_stop(&sc->sc_tick_ch); 2349 2350 /* Down the MII. */ 2351 mii_down(&sc->sc_mii); 2352 2353 /* 2354 * Disable interrupts. 2355 */ 2356 bus_space_write_4(st, sh, SIP_IER, 0); 2357 2358 /* 2359 * Stop receiver and transmitter. 2360 */ 2361 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2362 2363 /* 2364 * Release any queued transmit buffers. 2365 */ 2366 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2367 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2368 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2369 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2370 CMDSTS_INTR) == 0) 2371 printf("%s: sip_stop: last descriptor does not " 2372 "have INTR bit set\n", sc->sc_dev.dv_xname); 2373 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2374 #ifdef DIAGNOSTIC 2375 if (txs->txs_mbuf == NULL) { 2376 printf("%s: dirty txsoft with no mbuf chain\n", 2377 sc->sc_dev.dv_xname); 2378 panic("sip_stop"); 2379 } 2380 #endif 2381 cmdsts |= /* DEBUG */ 2382 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2383 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2384 m_freem(txs->txs_mbuf); 2385 txs->txs_mbuf = NULL; 2386 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2387 } 2388 2389 if (disable) 2390 SIP_DECL(rxdrain)(sc); 2391 2392 /* 2393 * Mark the interface down and cancel the watchdog timer. 2394 */ 2395 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2396 ifp->if_timer = 0; 2397 2398 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2399 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2400 printf("%s: sip_stop: no INTR bits set in dirty tx " 2401 "descriptors\n", sc->sc_dev.dv_xname); 2402 } 2403 2404 /* 2405 * sip_read_eeprom: 2406 * 2407 * Read data from the serial EEPROM. 2408 */ 2409 void 2410 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2411 u_int16_t *data) 2412 { 2413 bus_space_tag_t st = sc->sc_st; 2414 bus_space_handle_t sh = sc->sc_sh; 2415 u_int16_t reg; 2416 int i, x; 2417 2418 for (i = 0; i < wordcnt; i++) { 2419 /* Send CHIP SELECT. */ 2420 reg = EROMAR_EECS; 2421 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2422 2423 /* Shift in the READ opcode. */ 2424 for (x = 3; x > 0; x--) { 2425 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2426 reg |= EROMAR_EEDI; 2427 else 2428 reg &= ~EROMAR_EEDI; 2429 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2430 bus_space_write_4(st, sh, SIP_EROMAR, 2431 reg | EROMAR_EESK); 2432 delay(4); 2433 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2434 delay(4); 2435 } 2436 2437 /* Shift in address. */ 2438 for (x = 6; x > 0; x--) { 2439 if ((word + i) & (1 << (x - 1))) 2440 reg |= EROMAR_EEDI; 2441 else 2442 reg &= ~EROMAR_EEDI; 2443 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2444 bus_space_write_4(st, sh, SIP_EROMAR, 2445 reg | EROMAR_EESK); 2446 delay(4); 2447 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2448 delay(4); 2449 } 2450 2451 /* Shift out data. */ 2452 reg = EROMAR_EECS; 2453 data[i] = 0; 2454 for (x = 16; x > 0; x--) { 2455 bus_space_write_4(st, sh, SIP_EROMAR, 2456 reg | EROMAR_EESK); 2457 delay(4); 2458 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2459 data[i] |= (1 << (x - 1)); 2460 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2461 delay(4); 2462 } 2463 2464 /* Clear CHIP SELECT. */ 2465 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2466 delay(4); 2467 } 2468 } 2469 2470 /* 2471 * sip_add_rxbuf: 2472 * 2473 * Add a receive buffer to the indicated descriptor. 2474 */ 2475 int 2476 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2477 { 2478 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2479 struct mbuf *m; 2480 int error; 2481 2482 MGETHDR(m, M_DONTWAIT, MT_DATA); 2483 if (m == NULL) 2484 return (ENOBUFS); 2485 2486 MCLGET(m, M_DONTWAIT); 2487 if ((m->m_flags & M_EXT) == 0) { 2488 m_freem(m); 2489 return (ENOBUFS); 2490 } 2491 2492 #if defined(DP83820) 2493 m->m_len = SIP_RXBUF_LEN; 2494 #endif /* DP83820 */ 2495 2496 if (rxs->rxs_mbuf != NULL) 2497 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2498 2499 rxs->rxs_mbuf = m; 2500 2501 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2502 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2503 BUS_DMA_READ|BUS_DMA_NOWAIT); 2504 if (error) { 2505 printf("%s: can't load rx DMA map %d, error = %d\n", 2506 sc->sc_dev.dv_xname, idx, error); 2507 panic("sip_add_rxbuf"); /* XXX */ 2508 } 2509 2510 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2511 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2512 2513 SIP_INIT_RXDESC(sc, idx); 2514 2515 return (0); 2516 } 2517 2518 #if !defined(DP83820) 2519 /* 2520 * sip_sis900_set_filter: 2521 * 2522 * Set up the receive filter. 2523 */ 2524 void 2525 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2526 { 2527 bus_space_tag_t st = sc->sc_st; 2528 bus_space_handle_t sh = sc->sc_sh; 2529 struct ethercom *ec = &sc->sc_ethercom; 2530 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2531 struct ether_multi *enm; 2532 u_int8_t *cp; 2533 struct ether_multistep step; 2534 u_int32_t crc, mchash[16]; 2535 2536 /* 2537 * Initialize the prototype RFCR. 2538 */ 2539 sc->sc_rfcr = RFCR_RFEN; 2540 if (ifp->if_flags & IFF_BROADCAST) 2541 sc->sc_rfcr |= RFCR_AAB; 2542 if (ifp->if_flags & IFF_PROMISC) { 2543 sc->sc_rfcr |= RFCR_AAP; 2544 goto allmulti; 2545 } 2546 2547 /* 2548 * Set up the multicast address filter by passing all multicast 2549 * addresses through a CRC generator, and then using the high-order 2550 * 6 bits as an index into the 128 bit multicast hash table (only 2551 * the lower 16 bits of each 32 bit multicast hash register are 2552 * valid). The high order bits select the register, while the 2553 * rest of the bits select the bit within the register. 2554 */ 2555 2556 memset(mchash, 0, sizeof(mchash)); 2557 2558 ETHER_FIRST_MULTI(step, ec, enm); 2559 while (enm != NULL) { 2560 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2561 /* 2562 * We must listen to a range of multicast addresses. 2563 * For now, just accept all multicasts, rather than 2564 * trying to set only those filter bits needed to match 2565 * the range. (At this time, the only use of address 2566 * ranges is for IP multicast routing, for which the 2567 * range is big enough to require all bits set.) 2568 */ 2569 goto allmulti; 2570 } 2571 2572 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2573 2574 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2575 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2576 /* Just want the 8 most significant bits. */ 2577 crc >>= 24; 2578 } else { 2579 /* Just want the 7 most significant bits. */ 2580 crc >>= 25; 2581 } 2582 2583 /* Set the corresponding bit in the hash table. */ 2584 mchash[crc >> 4] |= 1 << (crc & 0xf); 2585 2586 ETHER_NEXT_MULTI(step, enm); 2587 } 2588 2589 ifp->if_flags &= ~IFF_ALLMULTI; 2590 goto setit; 2591 2592 allmulti: 2593 ifp->if_flags |= IFF_ALLMULTI; 2594 sc->sc_rfcr |= RFCR_AAM; 2595 2596 setit: 2597 #define FILTER_EMIT(addr, data) \ 2598 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2599 delay(1); \ 2600 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2601 delay(1) 2602 2603 /* 2604 * Disable receive filter, and program the node address. 2605 */ 2606 cp = LLADDR(ifp->if_sadl); 2607 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2608 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2609 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2610 2611 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2612 /* 2613 * Program the multicast hash table. 2614 */ 2615 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2616 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2617 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2618 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2619 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2620 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2621 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2622 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2623 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2624 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2625 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2626 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2627 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2628 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2629 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2630 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2631 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2632 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2633 } 2634 } 2635 #undef FILTER_EMIT 2636 2637 /* 2638 * Re-enable the receiver filter. 2639 */ 2640 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2641 } 2642 #endif /* ! DP83820 */ 2643 2644 /* 2645 * sip_dp83815_set_filter: 2646 * 2647 * Set up the receive filter. 2648 */ 2649 void 2650 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2651 { 2652 bus_space_tag_t st = sc->sc_st; 2653 bus_space_handle_t sh = sc->sc_sh; 2654 struct ethercom *ec = &sc->sc_ethercom; 2655 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2656 struct ether_multi *enm; 2657 u_int8_t *cp; 2658 struct ether_multistep step; 2659 u_int32_t crc, hash, slot, bit; 2660 #ifdef DP83820 2661 #define MCHASH_NWORDS 128 2662 #else 2663 #define MCHASH_NWORDS 32 2664 #endif /* DP83820 */ 2665 u_int16_t mchash[MCHASH_NWORDS]; 2666 int i; 2667 2668 /* 2669 * Initialize the prototype RFCR. 2670 * Enable the receive filter, and accept on 2671 * Perfect (destination address) Match 2672 * If IFF_BROADCAST, also accept all broadcast packets. 2673 * If IFF_PROMISC, accept all unicast packets (and later, set 2674 * IFF_ALLMULTI and accept all multicast, too). 2675 */ 2676 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2677 if (ifp->if_flags & IFF_BROADCAST) 2678 sc->sc_rfcr |= RFCR_AAB; 2679 if (ifp->if_flags & IFF_PROMISC) { 2680 sc->sc_rfcr |= RFCR_AAP; 2681 goto allmulti; 2682 } 2683 2684 #ifdef DP83820 2685 /* 2686 * Set up the DP83820 multicast address filter by passing all multicast 2687 * addresses through a CRC generator, and then using the high-order 2688 * 11 bits as an index into the 2048 bit multicast hash table. The 2689 * high-order 7 bits select the slot, while the low-order 4 bits 2690 * select the bit within the slot. Note that only the low 16-bits 2691 * of each filter word are used, and there are 128 filter words. 2692 */ 2693 #else 2694 /* 2695 * Set up the DP83815 multicast address filter by passing all multicast 2696 * addresses through a CRC generator, and then using the high-order 2697 * 9 bits as an index into the 512 bit multicast hash table. The 2698 * high-order 5 bits select the slot, while the low-order 4 bits 2699 * select the bit within the slot. Note that only the low 16-bits 2700 * of each filter word are used, and there are 32 filter words. 2701 */ 2702 #endif /* DP83820 */ 2703 2704 memset(mchash, 0, sizeof(mchash)); 2705 2706 ifp->if_flags &= ~IFF_ALLMULTI; 2707 ETHER_FIRST_MULTI(step, ec, enm); 2708 if (enm == NULL) 2709 goto setit; 2710 while (enm != NULL) { 2711 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2712 /* 2713 * We must listen to a range of multicast addresses. 2714 * For now, just accept all multicasts, rather than 2715 * trying to set only those filter bits needed to match 2716 * the range. (At this time, the only use of address 2717 * ranges is for IP multicast routing, for which the 2718 * range is big enough to require all bits set.) 2719 */ 2720 goto allmulti; 2721 } 2722 2723 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2724 2725 #ifdef DP83820 2726 /* Just want the 11 most significant bits. */ 2727 hash = crc >> 21; 2728 #else 2729 /* Just want the 9 most significant bits. */ 2730 hash = crc >> 23; 2731 #endif /* DP83820 */ 2732 2733 slot = hash >> 4; 2734 bit = hash & 0xf; 2735 2736 /* Set the corresponding bit in the hash table. */ 2737 mchash[slot] |= 1 << bit; 2738 2739 ETHER_NEXT_MULTI(step, enm); 2740 } 2741 sc->sc_rfcr |= RFCR_MHEN; 2742 goto setit; 2743 2744 allmulti: 2745 ifp->if_flags |= IFF_ALLMULTI; 2746 sc->sc_rfcr |= RFCR_AAM; 2747 2748 setit: 2749 #define FILTER_EMIT(addr, data) \ 2750 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2751 delay(1); \ 2752 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2753 delay(1) 2754 2755 /* 2756 * Disable receive filter, and program the node address. 2757 */ 2758 cp = LLADDR(ifp->if_sadl); 2759 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 2760 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 2761 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 2762 2763 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2764 /* 2765 * Program the multicast hash table. 2766 */ 2767 for (i = 0; i < MCHASH_NWORDS; i++) { 2768 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 2769 mchash[i]); 2770 } 2771 } 2772 #undef FILTER_EMIT 2773 #undef MCHASH_NWORDS 2774 2775 /* 2776 * Re-enable the receiver filter. 2777 */ 2778 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2779 } 2780 2781 #if defined(DP83820) 2782 /* 2783 * sip_dp83820_mii_readreg: [mii interface function] 2784 * 2785 * Read a PHY register on the MII of the DP83820. 2786 */ 2787 int 2788 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 2789 { 2790 2791 return (mii_bitbang_readreg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2792 phy, reg)); 2793 } 2794 2795 /* 2796 * sip_dp83820_mii_writereg: [mii interface function] 2797 * 2798 * Write a PHY register on the MII of the DP83820. 2799 */ 2800 void 2801 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 2802 { 2803 2804 mii_bitbang_writereg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2805 phy, reg, val); 2806 } 2807 2808 /* 2809 * sip_dp83815_mii_statchg: [mii interface function] 2810 * 2811 * Callback from MII layer when media changes. 2812 */ 2813 void 2814 SIP_DECL(dp83820_mii_statchg)(struct device *self) 2815 { 2816 struct sip_softc *sc = (struct sip_softc *) self; 2817 u_int32_t cfg; 2818 2819 /* 2820 * Update TXCFG for full-duplex operation. 2821 */ 2822 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2823 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2824 else 2825 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2826 2827 /* 2828 * Update RXCFG for full-duplex or loopback. 2829 */ 2830 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2831 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2832 sc->sc_rxcfg |= RXCFG_ATX; 2833 else 2834 sc->sc_rxcfg &= ~RXCFG_ATX; 2835 2836 /* 2837 * Update CFG for MII/GMII. 2838 */ 2839 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2840 cfg = sc->sc_cfg | CFG_MODE_1000; 2841 else 2842 cfg = sc->sc_cfg; 2843 2844 /* 2845 * XXX 802.3x flow control. 2846 */ 2847 2848 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 2849 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2850 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2851 } 2852 2853 /* 2854 * sip_dp83820_mii_bitbang_read: [mii bit-bang interface function] 2855 * 2856 * Read the MII serial port for the MII bit-bang module. 2857 */ 2858 u_int32_t 2859 SIP_DECL(dp83820_mii_bitbang_read)(struct device *self) 2860 { 2861 struct sip_softc *sc = (void *) self; 2862 2863 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 2864 } 2865 2866 /* 2867 * sip_dp83820_mii_bitbang_write: [mii big-bang interface function] 2868 * 2869 * Write the MII serial port for the MII bit-bang module. 2870 */ 2871 void 2872 SIP_DECL(dp83820_mii_bitbang_write)(struct device *self, u_int32_t val) 2873 { 2874 struct sip_softc *sc = (void *) self; 2875 2876 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 2877 } 2878 #else /* ! DP83820 */ 2879 /* 2880 * sip_sis900_mii_readreg: [mii interface function] 2881 * 2882 * Read a PHY register on the MII. 2883 */ 2884 int 2885 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 2886 { 2887 struct sip_softc *sc = (struct sip_softc *) self; 2888 u_int32_t enphy; 2889 2890 /* 2891 * The SiS 900 has only an internal PHY on the MII. Only allow 2892 * MII address 0. 2893 */ 2894 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 2895 sc->sc_rev < SIS_REV_635 && phy != 0) 2896 return (0); 2897 2898 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2899 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 2900 ENPHY_RWCMD | ENPHY_ACCESS); 2901 do { 2902 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2903 } while (enphy & ENPHY_ACCESS); 2904 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 2905 } 2906 2907 /* 2908 * sip_sis900_mii_writereg: [mii interface function] 2909 * 2910 * Write a PHY register on the MII. 2911 */ 2912 void 2913 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 2914 { 2915 struct sip_softc *sc = (struct sip_softc *) self; 2916 u_int32_t enphy; 2917 2918 /* 2919 * The SiS 900 has only an internal PHY on the MII. Only allow 2920 * MII address 0. 2921 */ 2922 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 2923 sc->sc_rev < SIS_REV_635 && phy != 0) 2924 return; 2925 2926 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2927 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 2928 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 2929 do { 2930 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2931 } while (enphy & ENPHY_ACCESS); 2932 } 2933 2934 /* 2935 * sip_sis900_mii_statchg: [mii interface function] 2936 * 2937 * Callback from MII layer when media changes. 2938 */ 2939 void 2940 SIP_DECL(sis900_mii_statchg)(struct device *self) 2941 { 2942 struct sip_softc *sc = (struct sip_softc *) self; 2943 u_int32_t flowctl; 2944 2945 /* 2946 * Update TXCFG for full-duplex operation. 2947 */ 2948 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2949 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2950 else 2951 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2952 2953 /* 2954 * Update RXCFG for full-duplex or loopback. 2955 */ 2956 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2957 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2958 sc->sc_rxcfg |= RXCFG_ATX; 2959 else 2960 sc->sc_rxcfg &= ~RXCFG_ATX; 2961 2962 /* 2963 * Update IMR for use of 802.3x flow control. 2964 */ 2965 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 2966 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 2967 flowctl = FLOWCTL_FLOWEN; 2968 } else { 2969 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 2970 flowctl = 0; 2971 } 2972 2973 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2974 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2975 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 2976 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 2977 } 2978 2979 /* 2980 * sip_dp83815_mii_readreg: [mii interface function] 2981 * 2982 * Read a PHY register on the MII. 2983 */ 2984 int 2985 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 2986 { 2987 struct sip_softc *sc = (struct sip_softc *) self; 2988 u_int32_t val; 2989 2990 /* 2991 * The DP83815 only has an internal PHY. Only allow 2992 * MII address 0. 2993 */ 2994 if (phy != 0) 2995 return (0); 2996 2997 /* 2998 * Apparently, after a reset, the DP83815 can take a while 2999 * to respond. During this recovery period, the BMSR returns 3000 * a value of 0. Catch this -- it's not supposed to happen 3001 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3002 * PHY to come back to life. 3003 * 3004 * This works out because the BMSR is the first register 3005 * read during the PHY probe process. 3006 */ 3007 do { 3008 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3009 } while (reg == MII_BMSR && val == 0); 3010 3011 return (val & 0xffff); 3012 } 3013 3014 /* 3015 * sip_dp83815_mii_writereg: [mii interface function] 3016 * 3017 * Write a PHY register to the MII. 3018 */ 3019 void 3020 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3021 { 3022 struct sip_softc *sc = (struct sip_softc *) self; 3023 3024 /* 3025 * The DP83815 only has an internal PHY. Only allow 3026 * MII address 0. 3027 */ 3028 if (phy != 0) 3029 return; 3030 3031 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3032 } 3033 3034 /* 3035 * sip_dp83815_mii_statchg: [mii interface function] 3036 * 3037 * Callback from MII layer when media changes. 3038 */ 3039 void 3040 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3041 { 3042 struct sip_softc *sc = (struct sip_softc *) self; 3043 3044 /* 3045 * Update TXCFG for full-duplex operation. 3046 */ 3047 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3048 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3049 else 3050 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3051 3052 /* 3053 * Update RXCFG for full-duplex or loopback. 3054 */ 3055 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3056 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3057 sc->sc_rxcfg |= RXCFG_ATX; 3058 else 3059 sc->sc_rxcfg &= ~RXCFG_ATX; 3060 3061 /* 3062 * XXX 802.3x flow control. 3063 */ 3064 3065 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3066 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3067 } 3068 #endif /* DP83820 */ 3069 3070 #if defined(DP83820) 3071 void 3072 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3073 const struct pci_attach_args *pa, u_int8_t *enaddr) 3074 { 3075 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3076 u_int8_t cksum, *e, match; 3077 int i; 3078 3079 /* 3080 * EEPROM data format for the DP83820 can be found in 3081 * the DP83820 manual, section 4.2.4. 3082 */ 3083 3084 SIP_DECL(read_eeprom)(sc, 0, 3085 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3086 3087 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3088 match = ~(match - 1); 3089 3090 cksum = 0x55; 3091 e = (u_int8_t *) eeprom_data; 3092 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3093 cksum += *e++; 3094 3095 if (cksum != match) 3096 printf("%s: Checksum (%x) mismatch (%x)", 3097 sc->sc_dev.dv_xname, cksum, match); 3098 3099 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3100 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3101 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3102 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3103 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3104 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3105 3106 /* Get the GPIOR bits. */ 3107 sc->sc_gpior = eeprom_data[0x04]; 3108 } 3109 #else /* ! DP83820 */ 3110 void 3111 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3112 const struct pci_attach_args *pa, u_int8_t *enaddr) 3113 { 3114 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3115 3116 switch (sc->sc_rev) { 3117 case SIS_REV_630S: 3118 case SIS_REV_630E: 3119 case SIS_REV_630EA1: 3120 case SIS_REV_630ET: 3121 case SIS_REV_635: 3122 /* 3123 * The MAC address for the on-board Ethernet of 3124 * the SiS 630 chipset is in the NVRAM. Kick 3125 * the chip into re-loading it from NVRAM, and 3126 * read the MAC address out of the filter registers. 3127 */ 3128 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3129 3130 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3131 RFCR_RFADDR_NODE0); 3132 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3133 0xffff; 3134 3135 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3136 RFCR_RFADDR_NODE2); 3137 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3138 0xffff; 3139 3140 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3141 RFCR_RFADDR_NODE4); 3142 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3143 0xffff; 3144 break; 3145 3146 default: 3147 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3148 sizeof(myea) / sizeof(myea[0]), myea); 3149 } 3150 3151 enaddr[0] = myea[0] & 0xff; 3152 enaddr[1] = myea[0] >> 8; 3153 enaddr[2] = myea[1] & 0xff; 3154 enaddr[3] = myea[1] >> 8; 3155 enaddr[4] = myea[2] & 0xff; 3156 enaddr[5] = myea[2] >> 8; 3157 } 3158 3159 /* Table and macro to bit-reverse an octet. */ 3160 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3161 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3162 3163 void 3164 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3165 const struct pci_attach_args *pa, u_int8_t *enaddr) 3166 { 3167 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3168 u_int8_t cksum, *e, match; 3169 int i; 3170 3171 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3172 sizeof(eeprom_data[0]), eeprom_data); 3173 3174 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3175 match = ~(match - 1); 3176 3177 cksum = 0x55; 3178 e = (u_int8_t *) eeprom_data; 3179 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3180 cksum += *e++; 3181 } 3182 if (cksum != match) { 3183 printf("%s: Checksum (%x) mismatch (%x)", 3184 sc->sc_dev.dv_xname, cksum, match); 3185 } 3186 3187 /* 3188 * Unrolled because it makes slightly more sense this way. 3189 * The DP83815 stores the MAC address in bit 0 of word 6 3190 * through bit 15 of word 8. 3191 */ 3192 ea = &eeprom_data[6]; 3193 enaddr[0] = ((*ea & 0x1) << 7); 3194 ea++; 3195 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3196 enaddr[1] = ((*ea & 0x1FE) >> 1); 3197 enaddr[2] = ((*ea & 0x1) << 7); 3198 ea++; 3199 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3200 enaddr[3] = ((*ea & 0x1FE) >> 1); 3201 enaddr[4] = ((*ea & 0x1) << 7); 3202 ea++; 3203 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3204 enaddr[5] = ((*ea & 0x1FE) >> 1); 3205 3206 /* 3207 * In case that's not weird enough, we also need to reverse 3208 * the bits in each byte. This all actually makes more sense 3209 * if you think about the EEPROM storage as an array of bits 3210 * being shifted into bytes, but that's not how we're looking 3211 * at it here... 3212 */ 3213 for (i = 0; i < 6 ;i++) 3214 enaddr[i] = bbr(enaddr[i]); 3215 } 3216 #endif /* DP83820 */ 3217 3218 /* 3219 * sip_mediastatus: [ifmedia interface function] 3220 * 3221 * Get the current interface media status. 3222 */ 3223 void 3224 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3225 { 3226 struct sip_softc *sc = ifp->if_softc; 3227 3228 mii_pollstat(&sc->sc_mii); 3229 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3230 ifmr->ifm_active = sc->sc_mii.mii_media_active; 3231 } 3232 3233 /* 3234 * sip_mediachange: [ifmedia interface function] 3235 * 3236 * Set hardware to newly-selected media. 3237 */ 3238 int 3239 SIP_DECL(mediachange)(struct ifnet *ifp) 3240 { 3241 struct sip_softc *sc = ifp->if_softc; 3242 3243 if (ifp->if_flags & IFF_UP) 3244 mii_mediachg(&sc->sc_mii); 3245 return (0); 3246 } 3247
Indexes created Mon Sep 22 21:09:42 GMT 2025