if_sip.c revision 1.60
1 /* $NetBSD: if_sip.c,v 1.60 2002/06/30 20:36:06 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Support the 10-bit interface on the DP83820 (for fiber). 80 * 81 * - Reduce the Rx interrupt load. 82 */ 83 84 #include <sys/cdefs.h> 85 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.60 2002/06/30 20:36:06 thorpej Exp $"); 86 87 #include "bpfilter.h" 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/callout.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/ioctl.h> 97 #include <sys/errno.h> 98 #include <sys/device.h> 99 #include <sys/queue.h> 100 101 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 102 103 #include <net/if.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 #include <net/if_ether.h> 107 108 #if NBPFILTER > 0 109 #include <net/bpf.h> 110 #endif 111 112 #include <machine/bus.h> 113 #include <machine/intr.h> 114 #include <machine/endian.h> 115 116 #include <dev/mii/mii.h> 117 #include <dev/mii/miivar.h> 118 #ifdef DP83820 119 #include <dev/mii/mii_bitbang.h> 120 #endif /* DP83820 */ 121 122 #include <dev/pci/pcireg.h> 123 #include <dev/pci/pcivar.h> 124 #include <dev/pci/pcidevs.h> 125 126 #include <dev/pci/if_sipreg.h> 127 128 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 129 #define SIP_DECL(x) __CONCAT(gsip_,x) 130 #else /* SiS900 and DP83815 */ 131 #define SIP_DECL(x) __CONCAT(sip_,x) 132 #endif 133 134 #define SIP_STR(x) __STRING(SIP_DECL(x)) 135 136 /* 137 * Transmit descriptor list size. This is arbitrary, but allocate 138 * enough descriptors for 128 pending transmissions, and 8 segments 139 * per packet. This MUST work out to a power of 2. 140 */ 141 #define SIP_NTXSEGS 16 142 #define SIP_NTXSEGS_ALLOC 8 143 144 #define SIP_TXQUEUELEN 256 145 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 146 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 147 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 148 149 #if defined(DP83020) 150 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 151 #else 152 #define TX_DMAMAP_SIZE MCLBYTES 153 #endif 154 155 /* 156 * Receive descriptor list size. We have one Rx buffer per incoming 157 * packet, so this logic is a little simpler. 158 * 159 * Actually, on the DP83820, we allow the packet to consume more than 160 * one buffer, in order to support jumbo Ethernet frames. In that 161 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 162 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 163 * so we'd better be quick about handling receive interrupts. 164 */ 165 #if defined(DP83820) 166 #define SIP_NRXDESC 256 167 #else 168 #define SIP_NRXDESC 128 169 #endif /* DP83820 */ 170 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 171 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 172 173 /* 174 * Control structures are DMA'd to the SiS900 chip. We allocate them in 175 * a single clump that maps to a single DMA segment to make several things 176 * easier. 177 */ 178 struct sip_control_data { 179 /* 180 * The transmit descriptors. 181 */ 182 struct sip_desc scd_txdescs[SIP_NTXDESC]; 183 184 /* 185 * The receive descriptors. 186 */ 187 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 188 }; 189 190 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 191 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 192 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 193 194 /* 195 * Software state for transmit jobs. 196 */ 197 struct sip_txsoft { 198 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 199 bus_dmamap_t txs_dmamap; /* our DMA map */ 200 int txs_firstdesc; /* first descriptor in packet */ 201 int txs_lastdesc; /* last descriptor in packet */ 202 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 203 }; 204 205 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 206 207 /* 208 * Software state for receive jobs. 209 */ 210 struct sip_rxsoft { 211 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 212 bus_dmamap_t rxs_dmamap; /* our DMA map */ 213 }; 214 215 /* 216 * Software state per device. 217 */ 218 struct sip_softc { 219 struct device sc_dev; /* generic device information */ 220 bus_space_tag_t sc_st; /* bus space tag */ 221 bus_space_handle_t sc_sh; /* bus space handle */ 222 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 223 struct ethercom sc_ethercom; /* ethernet common data */ 224 void *sc_sdhook; /* shutdown hook */ 225 226 const struct sip_product *sc_model; /* which model are we? */ 227 int sc_rev; /* chip revision */ 228 229 void *sc_ih; /* interrupt cookie */ 230 231 struct mii_data sc_mii; /* MII/media information */ 232 233 struct callout sc_tick_ch; /* tick callout */ 234 235 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 236 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 237 238 /* 239 * Software state for transmit and receive descriptors. 240 */ 241 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 242 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 243 244 /* 245 * Control data structures. 246 */ 247 struct sip_control_data *sc_control_data; 248 #define sc_txdescs sc_control_data->scd_txdescs 249 #define sc_rxdescs sc_control_data->scd_rxdescs 250 251 #ifdef SIP_EVENT_COUNTERS 252 /* 253 * Event counters. 254 */ 255 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 256 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 257 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 258 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 259 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 260 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 261 #ifdef DP83820 262 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 263 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 264 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 265 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 266 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 267 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 268 #endif /* DP83820 */ 269 #endif /* SIP_EVENT_COUNTERS */ 270 271 u_int32_t sc_txcfg; /* prototype TXCFG register */ 272 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 273 u_int32_t sc_imr; /* prototype IMR register */ 274 u_int32_t sc_rfcr; /* prototype RFCR register */ 275 276 u_int32_t sc_cfg; /* prototype CFG register */ 277 278 #ifdef DP83820 279 u_int32_t sc_gpior; /* prototype GPIOR register */ 280 #endif /* DP83820 */ 281 282 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 283 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 284 285 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 286 287 int sc_flags; /* misc. flags; see below */ 288 289 int sc_txfree; /* number of free Tx descriptors */ 290 int sc_txnext; /* next ready Tx descriptor */ 291 int sc_txwin; /* Tx descriptors since last intr */ 292 293 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 294 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 295 296 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 297 #if defined(DP83820) 298 int sc_rxdiscard; 299 int sc_rxlen; 300 struct mbuf *sc_rxhead; 301 struct mbuf *sc_rxtail; 302 struct mbuf **sc_rxtailp; 303 #endif /* DP83820 */ 304 }; 305 306 /* sc_flags */ 307 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 308 309 #ifdef DP83820 310 #define SIP_RXCHAIN_RESET(sc) \ 311 do { \ 312 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 313 *(sc)->sc_rxtailp = NULL; \ 314 (sc)->sc_rxlen = 0; \ 315 } while (/*CONSTCOND*/0) 316 317 #define SIP_RXCHAIN_LINK(sc, m) \ 318 do { \ 319 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 320 (sc)->sc_rxtailp = &(m)->m_next; \ 321 } while (/*CONSTCOND*/0) 322 #endif /* DP83820 */ 323 324 #ifdef SIP_EVENT_COUNTERS 325 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 326 #else 327 #define SIP_EVCNT_INCR(ev) /* nothing */ 328 #endif 329 330 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 331 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 332 333 #define SIP_CDTXSYNC(sc, x, n, ops) \ 334 do { \ 335 int __x, __n; \ 336 \ 337 __x = (x); \ 338 __n = (n); \ 339 \ 340 /* If it will wrap around, sync to the end of the ring. */ \ 341 if ((__x + __n) > SIP_NTXDESC) { \ 342 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 343 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 344 (SIP_NTXDESC - __x), (ops)); \ 345 __n -= (SIP_NTXDESC - __x); \ 346 __x = 0; \ 347 } \ 348 \ 349 /* Now sync whatever is left. */ \ 350 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 351 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 352 } while (0) 353 354 #define SIP_CDRXSYNC(sc, x, ops) \ 355 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 356 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 357 358 #ifdef DP83820 359 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 360 #define SIP_RXBUF_LEN (MCLBYTES - 4) 361 #else 362 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 363 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 364 #endif 365 #define SIP_INIT_RXDESC(sc, x) \ 366 do { \ 367 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 368 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 369 \ 370 __sipd->sipd_link = \ 371 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 372 __sipd->sipd_bufptr = \ 373 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 374 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 375 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 376 SIP_INIT_RXDESC_EXTSTS \ 377 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 378 } while (0) 379 380 #define SIP_CHIP_VERS(sc, v, p, r) \ 381 ((sc)->sc_model->sip_vendor == (v) && \ 382 (sc)->sc_model->sip_product == (p) && \ 383 (sc)->sc_rev == (r)) 384 385 #define SIP_CHIP_MODEL(sc, v, p) \ 386 ((sc)->sc_model->sip_vendor == (v) && \ 387 (sc)->sc_model->sip_product == (p)) 388 389 #if !defined(DP83820) 390 #define SIP_SIS900_REV(sc, rev) \ 391 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 392 #endif 393 394 #define SIP_TIMEOUT 1000 395 396 void SIP_DECL(start)(struct ifnet *); 397 void SIP_DECL(watchdog)(struct ifnet *); 398 int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 399 int SIP_DECL(init)(struct ifnet *); 400 void SIP_DECL(stop)(struct ifnet *, int); 401 402 void SIP_DECL(shutdown)(void *); 403 404 void SIP_DECL(reset)(struct sip_softc *); 405 void SIP_DECL(rxdrain)(struct sip_softc *); 406 int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 407 void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, u_int16_t *); 408 void SIP_DECL(tick)(void *); 409 410 #if !defined(DP83820) 411 void SIP_DECL(sis900_set_filter)(struct sip_softc *); 412 #endif /* ! DP83820 */ 413 void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 414 415 #if defined(DP83820) 416 void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 417 const struct pci_attach_args *, u_int8_t *); 418 #else 419 void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 420 const struct pci_attach_args *, u_int8_t *); 421 void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 422 const struct pci_attach_args *, u_int8_t *); 423 #endif /* DP83820 */ 424 425 int SIP_DECL(intr)(void *); 426 void SIP_DECL(txintr)(struct sip_softc *); 427 void SIP_DECL(rxintr)(struct sip_softc *); 428 429 #if defined(DP83820) 430 int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 431 void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 432 void SIP_DECL(dp83820_mii_statchg)(struct device *); 433 #else 434 int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 435 void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 436 void SIP_DECL(sis900_mii_statchg)(struct device *); 437 438 int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 439 void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 440 void SIP_DECL(dp83815_mii_statchg)(struct device *); 441 #endif /* DP83820 */ 442 443 int SIP_DECL(mediachange)(struct ifnet *); 444 void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 445 446 int SIP_DECL(match)(struct device *, struct cfdata *, void *); 447 void SIP_DECL(attach)(struct device *, struct device *, void *); 448 449 int SIP_DECL(copy_small) = 0; 450 451 struct cfattach SIP_DECL(ca) = { 452 sizeof(struct sip_softc), SIP_DECL(match), SIP_DECL(attach), 453 }; 454 455 /* 456 * Descriptions of the variants of the SiS900. 457 */ 458 struct sip_variant { 459 int (*sipv_mii_readreg)(struct device *, int, int); 460 void (*sipv_mii_writereg)(struct device *, int, int, int); 461 void (*sipv_mii_statchg)(struct device *); 462 void (*sipv_set_filter)(struct sip_softc *); 463 void (*sipv_read_macaddr)(struct sip_softc *, 464 const struct pci_attach_args *, u_int8_t *); 465 }; 466 467 #if defined(DP83820) 468 u_int32_t SIP_DECL(dp83820_mii_bitbang_read)(struct device *); 469 void SIP_DECL(dp83820_mii_bitbang_write)(struct device *, u_int32_t); 470 471 const struct mii_bitbang_ops SIP_DECL(dp83820_mii_bitbang_ops) = { 472 SIP_DECL(dp83820_mii_bitbang_read), 473 SIP_DECL(dp83820_mii_bitbang_write), 474 { 475 EROMAR_MDIO, /* MII_BIT_MDO */ 476 EROMAR_MDIO, /* MII_BIT_MDI */ 477 EROMAR_MDC, /* MII_BIT_MDC */ 478 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 479 0, /* MII_BIT_DIR_PHY_HOST */ 480 } 481 }; 482 #endif /* DP83820 */ 483 484 #if defined(DP83820) 485 const struct sip_variant SIP_DECL(variant_dp83820) = { 486 SIP_DECL(dp83820_mii_readreg), 487 SIP_DECL(dp83820_mii_writereg), 488 SIP_DECL(dp83820_mii_statchg), 489 SIP_DECL(dp83815_set_filter), 490 SIP_DECL(dp83820_read_macaddr), 491 }; 492 #else 493 const struct sip_variant SIP_DECL(variant_sis900) = { 494 SIP_DECL(sis900_mii_readreg), 495 SIP_DECL(sis900_mii_writereg), 496 SIP_DECL(sis900_mii_statchg), 497 SIP_DECL(sis900_set_filter), 498 SIP_DECL(sis900_read_macaddr), 499 }; 500 501 const struct sip_variant SIP_DECL(variant_dp83815) = { 502 SIP_DECL(dp83815_mii_readreg), 503 SIP_DECL(dp83815_mii_writereg), 504 SIP_DECL(dp83815_mii_statchg), 505 SIP_DECL(dp83815_set_filter), 506 SIP_DECL(dp83815_read_macaddr), 507 }; 508 #endif /* DP83820 */ 509 510 /* 511 * Devices supported by this driver. 512 */ 513 const struct sip_product { 514 pci_vendor_id_t sip_vendor; 515 pci_product_id_t sip_product; 516 const char *sip_name; 517 const struct sip_variant *sip_variant; 518 } SIP_DECL(products)[] = { 519 #if defined(DP83820) 520 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 521 "NatSemi DP83820 Gigabit Ethernet", 522 &SIP_DECL(variant_dp83820) }, 523 #else 524 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 525 "SiS 900 10/100 Ethernet", 526 &SIP_DECL(variant_sis900) }, 527 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 528 "SiS 7016 10/100 Ethernet", 529 &SIP_DECL(variant_sis900) }, 530 531 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 532 "NatSemi DP83815 10/100 Ethernet", 533 &SIP_DECL(variant_dp83815) }, 534 #endif /* DP83820 */ 535 536 { 0, 0, 537 NULL, 538 NULL }, 539 }; 540 541 static const struct sip_product * 542 SIP_DECL(lookup)(const struct pci_attach_args *pa) 543 { 544 const struct sip_product *sip; 545 546 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 547 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 548 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 549 return (sip); 550 } 551 return (NULL); 552 } 553 554 #ifdef DP83820 555 /* 556 * I really hate stupid hardware vendors. There's a bit in the EEPROM 557 * which indicates if the card can do 64-bit data transfers. Unfortunately, 558 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 559 * which means we try to use 64-bit data transfers on those cards if we 560 * happen to be plugged into a 32-bit slot. 561 * 562 * What we do is use this table of cards known to be 64-bit cards. If 563 * you have a 64-bit card who's subsystem ID is not listed in this table, 564 * send the output of "pcictl dump ..." of the device to me so that your 565 * card will use the 64-bit data path when plugged into a 64-bit slot. 566 * 567 * -- Jason R. Thorpe <thorpej (at) netbsd.org> 568 * June 30, 2002 569 */ 570 static int 571 SIP_DECL(check_64bit)(const struct pci_attach_args *pa) 572 { 573 static const struct { 574 pci_vendor_id_t c64_vendor; 575 pci_product_id_t c64_product; 576 } card64[] = { 577 /* Asante GigaNIX */ 578 { 0x128a, 0x0002 }, 579 580 { 0, 0} 581 }; 582 pcireg_t subsys; 583 int i; 584 585 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 586 587 for (i = 0; card64[i].c64_vendor != 0; i++) { 588 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 589 PCI_PRODUCT(subsys) == card64[i].c64_product) 590 return (1); 591 } 592 593 return (0); 594 } 595 #endif /* DP83820 */ 596 597 int 598 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 599 { 600 struct pci_attach_args *pa = aux; 601 602 if (SIP_DECL(lookup)(pa) != NULL) 603 return (1); 604 605 return (0); 606 } 607 608 void 609 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 610 { 611 struct sip_softc *sc = (struct sip_softc *) self; 612 struct pci_attach_args *pa = aux; 613 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 614 pci_chipset_tag_t pc = pa->pa_pc; 615 pci_intr_handle_t ih; 616 const char *intrstr = NULL; 617 bus_space_tag_t iot, memt; 618 bus_space_handle_t ioh, memh; 619 bus_dma_segment_t seg; 620 int ioh_valid, memh_valid; 621 int i, rseg, error; 622 const struct sip_product *sip; 623 pcireg_t pmode; 624 u_int8_t enaddr[ETHER_ADDR_LEN]; 625 int pmreg; 626 #ifdef DP83820 627 pcireg_t memtype; 628 u_int32_t reg; 629 #endif /* DP83820 */ 630 631 callout_init(&sc->sc_tick_ch); 632 633 sip = SIP_DECL(lookup)(pa); 634 if (sip == NULL) { 635 printf("\n"); 636 panic(SIP_STR(attach) ": impossible"); 637 } 638 sc->sc_rev = PCI_REVISION(pa->pa_class); 639 640 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 641 642 sc->sc_model = sip; 643 644 /* 645 * XXX Work-around broken PXE firmware on some boards. 646 * 647 * The DP83815 shares an address decoder with the MEM BAR 648 * and the ROM BAR. Make sure the ROM BAR is disabled, 649 * so that memory mapped access works. 650 */ 651 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 652 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 653 ~PCI_MAPREG_ROM_ENABLE); 654 655 /* 656 * Map the device. 657 */ 658 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 659 PCI_MAPREG_TYPE_IO, 0, 660 &iot, &ioh, NULL, NULL) == 0); 661 #ifdef DP83820 662 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 663 switch (memtype) { 664 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 665 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 666 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 667 memtype, 0, &memt, &memh, NULL, NULL) == 0); 668 break; 669 default: 670 memh_valid = 0; 671 } 672 #else 673 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 674 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 675 &memt, &memh, NULL, NULL) == 0); 676 #endif /* DP83820 */ 677 678 if (memh_valid) { 679 sc->sc_st = memt; 680 sc->sc_sh = memh; 681 } else if (ioh_valid) { 682 sc->sc_st = iot; 683 sc->sc_sh = ioh; 684 } else { 685 printf("%s: unable to map device registers\n", 686 sc->sc_dev.dv_xname); 687 return; 688 } 689 690 sc->sc_dmat = pa->pa_dmat; 691 692 /* 693 * Make sure bus mastering is enabled. Also make sure 694 * Write/Invalidate is enabled if we're allowed to use it. 695 */ 696 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 697 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 698 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 699 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 700 pmreg | PCI_COMMAND_MASTER_ENABLE); 701 702 /* Get it out of power save mode if needed. */ 703 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 704 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 705 if (pmode == 3) { 706 /* 707 * The card has lost all configuration data in 708 * this state, so punt. 709 */ 710 printf("%s: unable to wake up from power state D3\n", 711 sc->sc_dev.dv_xname); 712 return; 713 } 714 if (pmode != 0) { 715 printf("%s: waking up from power state D%d\n", 716 sc->sc_dev.dv_xname, pmode); 717 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 718 } 719 } 720 721 /* 722 * Map and establish our interrupt. 723 */ 724 if (pci_intr_map(pa, &ih)) { 725 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 726 return; 727 } 728 intrstr = pci_intr_string(pc, ih); 729 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 730 if (sc->sc_ih == NULL) { 731 printf("%s: unable to establish interrupt", 732 sc->sc_dev.dv_xname); 733 if (intrstr != NULL) 734 printf(" at %s", intrstr); 735 printf("\n"); 736 return; 737 } 738 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 739 740 SIMPLEQ_INIT(&sc->sc_txfreeq); 741 SIMPLEQ_INIT(&sc->sc_txdirtyq); 742 743 /* 744 * Allocate the control data structures, and create and load the 745 * DMA map for it. 746 */ 747 if ((error = bus_dmamem_alloc(sc->sc_dmat, 748 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 749 0)) != 0) { 750 printf("%s: unable to allocate control data, error = %d\n", 751 sc->sc_dev.dv_xname, error); 752 goto fail_0; 753 } 754 755 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 756 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 757 BUS_DMA_COHERENT)) != 0) { 758 printf("%s: unable to map control data, error = %d\n", 759 sc->sc_dev.dv_xname, error); 760 goto fail_1; 761 } 762 763 if ((error = bus_dmamap_create(sc->sc_dmat, 764 sizeof(struct sip_control_data), 1, 765 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 766 printf("%s: unable to create control data DMA map, " 767 "error = %d\n", sc->sc_dev.dv_xname, error); 768 goto fail_2; 769 } 770 771 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 772 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 773 0)) != 0) { 774 printf("%s: unable to load control data DMA map, error = %d\n", 775 sc->sc_dev.dv_xname, error); 776 goto fail_3; 777 } 778 779 /* 780 * Create the transmit buffer DMA maps. 781 */ 782 for (i = 0; i < SIP_TXQUEUELEN; i++) { 783 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 784 SIP_NTXSEGS, MCLBYTES, 0, 0, 785 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 786 printf("%s: unable to create tx DMA map %d, " 787 "error = %d\n", sc->sc_dev.dv_xname, i, error); 788 goto fail_4; 789 } 790 } 791 792 /* 793 * Create the receive buffer DMA maps. 794 */ 795 for (i = 0; i < SIP_NRXDESC; i++) { 796 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 797 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 798 printf("%s: unable to create rx DMA map %d, " 799 "error = %d\n", sc->sc_dev.dv_xname, i, error); 800 goto fail_5; 801 } 802 sc->sc_rxsoft[i].rxs_mbuf = NULL; 803 } 804 805 /* 806 * Reset the chip to a known state. 807 */ 808 SIP_DECL(reset)(sc); 809 810 /* 811 * Read the Ethernet address from the EEPROM. This might 812 * also fetch other stuff from the EEPROM and stash it 813 * in the softc. 814 */ 815 sc->sc_cfg = 0; 816 #if !defined(DP83820) 817 if (SIP_SIS900_REV(sc,SIS_REV_635) || 818 SIP_SIS900_REV(sc,SIS_REV_900B)) 819 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 820 #endif 821 822 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 823 824 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 825 ether_sprintf(enaddr)); 826 827 /* 828 * Initialize the configuration register: aggressive PCI 829 * bus request algorithm, default backoff, default OW timer, 830 * default parity error detection. 831 * 832 * NOTE: "Big endian mode" is useless on the SiS900 and 833 * friends -- it affects packet data, not descriptors. 834 */ 835 #ifdef DP83820 836 /* 837 * Cause the chip to load configuration data from the EEPROM. 838 */ 839 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 840 for (i = 0; i < 10000; i++) { 841 delay(10); 842 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 843 PTSCR_EELOAD_EN) == 0) 844 break; 845 } 846 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 847 PTSCR_EELOAD_EN) { 848 printf("%s: timeout loading configuration from EEPROM\n", 849 sc->sc_dev.dv_xname); 850 return; 851 } 852 853 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 854 if (reg & CFG_PCI64_DET) { 855 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 856 /* 857 * Check to see if this card is 64-bit. If so, enable 64-bit 858 * data transfers. 859 * 860 * We can't use the DATA64_EN bit in the EEPROM, because 861 * vendors of 32-bit cards fail to clear that bit in many 862 * cases (yet the card still detects that it's in a 64-bit 863 * slot; go figure). 864 */ 865 if (SIP_DECL(check_64bit)(pa)) { 866 sc->sc_cfg |= CFG_DATA64_EN; 867 printf(", using 64-bit data transfers"); 868 } 869 printf("\n"); 870 } 871 872 /* 873 * XXX Need some PCI flags indicating support for 874 * XXX 64-bit addressing. 875 */ 876 #if 0 877 if (reg & CFG_M64ADDR) 878 sc->sc_cfg |= CFG_M64ADDR; 879 if (reg & CFG_T64ADDR) 880 sc->sc_cfg |= CFG_T64ADDR; 881 #endif 882 883 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 884 const char *sep = ""; 885 printf("%s: using ", sc->sc_dev.dv_xname); 886 if (reg & CFG_EXT_125) { 887 sc->sc_cfg |= CFG_EXT_125; 888 printf("%s125MHz clock", sep); 889 sep = ", "; 890 } 891 if (reg & CFG_TBI_EN) { 892 sc->sc_cfg |= CFG_TBI_EN; 893 printf("%sten-bit interface", sep); 894 sep = ", "; 895 } 896 printf("\n"); 897 } 898 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 899 (reg & CFG_MRM_DIS) != 0) 900 sc->sc_cfg |= CFG_MRM_DIS; 901 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 902 (reg & CFG_MWI_DIS) != 0) 903 sc->sc_cfg |= CFG_MWI_DIS; 904 905 /* 906 * Use the extended descriptor format on the DP83820. This 907 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 908 * checksumming. 909 */ 910 sc->sc_cfg |= CFG_EXTSTS_EN; 911 #endif /* DP83820 */ 912 913 /* 914 * Initialize our media structures and probe the MII. 915 */ 916 sc->sc_mii.mii_ifp = ifp; 917 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 918 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 919 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 920 ifmedia_init(&sc->sc_mii.mii_media, 0, SIP_DECL(mediachange), 921 SIP_DECL(mediastatus)); 922 #ifdef DP83820 923 if (sc->sc_cfg & CFG_TBI_EN) { 924 /* Using ten-bit interface. */ 925 printf("%s: TBI -- FIXME\n", sc->sc_dev.dv_xname); 926 } else { 927 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 928 MII_OFFSET_ANY, 0); 929 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 930 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 931 0, NULL); 932 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 933 } else 934 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 935 } 936 #else 937 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 938 MII_OFFSET_ANY, 0); 939 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 940 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 941 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 942 } else 943 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 944 #endif /* DP83820 */ 945 946 ifp = &sc->sc_ethercom.ec_if; 947 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 948 ifp->if_softc = sc; 949 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 950 ifp->if_ioctl = SIP_DECL(ioctl); 951 ifp->if_start = SIP_DECL(start); 952 ifp->if_watchdog = SIP_DECL(watchdog); 953 ifp->if_init = SIP_DECL(init); 954 ifp->if_stop = SIP_DECL(stop); 955 IFQ_SET_READY(&ifp->if_snd); 956 957 /* 958 * We can support 802.1Q VLAN-sized frames. 959 */ 960 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 961 962 #ifdef DP83820 963 /* 964 * And the DP83820 can do VLAN tagging in hardware, and 965 * support the jumbo Ethernet MTU. 966 */ 967 sc->sc_ethercom.ec_capabilities |= 968 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 969 970 /* 971 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 972 * in hardware. 973 */ 974 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 975 IFCAP_CSUM_UDPv4; 976 #endif /* DP83820 */ 977 978 /* 979 * Attach the interface. 980 */ 981 if_attach(ifp); 982 ether_ifattach(ifp, enaddr); 983 984 /* 985 * The number of bytes that must be available in 986 * the Tx FIFO before the bus master can DMA more 987 * data into the FIFO. 988 */ 989 sc->sc_tx_fill_thresh = 64 / 32; 990 991 /* 992 * Start at a drain threshold of 512 bytes. We will 993 * increase it if a DMA underrun occurs. 994 * 995 * XXX The minimum value of this variable should be 996 * tuned. We may be able to improve performance 997 * by starting with a lower value. That, however, 998 * may trash the first few outgoing packets if the 999 * PCI bus is saturated. 1000 */ 1001 sc->sc_tx_drain_thresh = 1504 / 32; 1002 1003 /* 1004 * Initialize the Rx FIFO drain threshold. 1005 * 1006 * This is in units of 8 bytes. 1007 * 1008 * We should never set this value lower than 2; 14 bytes are 1009 * required to filter the packet. 1010 */ 1011 sc->sc_rx_drain_thresh = 128 / 8; 1012 1013 #ifdef SIP_EVENT_COUNTERS 1014 /* 1015 * Attach event counters. 1016 */ 1017 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1018 NULL, sc->sc_dev.dv_xname, "txsstall"); 1019 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1020 NULL, sc->sc_dev.dv_xname, "txdstall"); 1021 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1022 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1023 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1024 NULL, sc->sc_dev.dv_xname, "txdintr"); 1025 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1026 NULL, sc->sc_dev.dv_xname, "txiintr"); 1027 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1028 NULL, sc->sc_dev.dv_xname, "rxintr"); 1029 #ifdef DP83820 1030 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1031 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1032 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1033 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1034 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1035 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1036 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1037 NULL, sc->sc_dev.dv_xname, "txipsum"); 1038 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1039 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1040 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1041 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1042 #endif /* DP83820 */ 1043 #endif /* SIP_EVENT_COUNTERS */ 1044 1045 /* 1046 * Make sure the interface is shutdown during reboot. 1047 */ 1048 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 1049 if (sc->sc_sdhook == NULL) 1050 printf("%s: WARNING: unable to establish shutdown hook\n", 1051 sc->sc_dev.dv_xname); 1052 return; 1053 1054 /* 1055 * Free any resources we've allocated during the failed attach 1056 * attempt. Do this in reverse order and fall through. 1057 */ 1058 fail_5: 1059 for (i = 0; i < SIP_NRXDESC; i++) { 1060 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1061 bus_dmamap_destroy(sc->sc_dmat, 1062 sc->sc_rxsoft[i].rxs_dmamap); 1063 } 1064 fail_4: 1065 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1066 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1067 bus_dmamap_destroy(sc->sc_dmat, 1068 sc->sc_txsoft[i].txs_dmamap); 1069 } 1070 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1071 fail_3: 1072 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1073 fail_2: 1074 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1075 sizeof(struct sip_control_data)); 1076 fail_1: 1077 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1078 fail_0: 1079 return; 1080 } 1081 1082 /* 1083 * sip_shutdown: 1084 * 1085 * Make sure the interface is stopped at reboot time. 1086 */ 1087 void 1088 SIP_DECL(shutdown)(void *arg) 1089 { 1090 struct sip_softc *sc = arg; 1091 1092 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1093 } 1094 1095 /* 1096 * sip_start: [ifnet interface function] 1097 * 1098 * Start packet transmission on the interface. 1099 */ 1100 void 1101 SIP_DECL(start)(struct ifnet *ifp) 1102 { 1103 struct sip_softc *sc = ifp->if_softc; 1104 struct mbuf *m0, *m; 1105 struct sip_txsoft *txs; 1106 bus_dmamap_t dmamap; 1107 int error, nexttx, lasttx, seg; 1108 int ofree = sc->sc_txfree; 1109 #if 0 1110 int firsttx = sc->sc_txnext; 1111 #endif 1112 #ifdef DP83820 1113 u_int32_t extsts; 1114 #endif 1115 1116 /* 1117 * If we've been told to pause, don't transmit any more packets. 1118 */ 1119 if (sc->sc_flags & SIPF_PAUSED) 1120 ifp->if_flags |= IFF_OACTIVE; 1121 1122 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1123 return; 1124 1125 /* 1126 * Loop through the send queue, setting up transmit descriptors 1127 * until we drain the queue, or use up all available transmit 1128 * descriptors. 1129 */ 1130 for (;;) { 1131 /* Get a work queue entry. */ 1132 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1133 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1134 break; 1135 } 1136 1137 /* 1138 * Grab a packet off the queue. 1139 */ 1140 IFQ_POLL(&ifp->if_snd, m0); 1141 if (m0 == NULL) 1142 break; 1143 #ifndef DP83820 1144 m = NULL; 1145 #endif 1146 1147 dmamap = txs->txs_dmamap; 1148 1149 #ifdef DP83820 1150 /* 1151 * Load the DMA map. If this fails, the packet either 1152 * didn't fit in the allotted number of segments, or we 1153 * were short on resources. For the too-many-segments 1154 * case, we simply report an error and drop the packet, 1155 * since we can't sanely copy a jumbo packet to a single 1156 * buffer. 1157 */ 1158 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1159 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1160 if (error) { 1161 if (error == EFBIG) { 1162 printf("%s: Tx packet consumes too many " 1163 "DMA segments, dropping...\n", 1164 sc->sc_dev.dv_xname); 1165 IFQ_DEQUEUE(&ifp->if_snd, m0); 1166 m_freem(m0); 1167 continue; 1168 } 1169 /* 1170 * Short on resources, just stop for now. 1171 */ 1172 break; 1173 } 1174 #else /* DP83820 */ 1175 /* 1176 * Load the DMA map. If this fails, the packet either 1177 * didn't fit in the alloted number of segments, or we 1178 * were short on resources. In this case, we'll copy 1179 * and try again. 1180 */ 1181 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1182 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1183 MGETHDR(m, M_DONTWAIT, MT_DATA); 1184 if (m == NULL) { 1185 printf("%s: unable to allocate Tx mbuf\n", 1186 sc->sc_dev.dv_xname); 1187 break; 1188 } 1189 if (m0->m_pkthdr.len > MHLEN) { 1190 MCLGET(m, M_DONTWAIT); 1191 if ((m->m_flags & M_EXT) == 0) { 1192 printf("%s: unable to allocate Tx " 1193 "cluster\n", sc->sc_dev.dv_xname); 1194 m_freem(m); 1195 break; 1196 } 1197 } 1198 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1199 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1200 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1201 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1202 if (error) { 1203 printf("%s: unable to load Tx buffer, " 1204 "error = %d\n", sc->sc_dev.dv_xname, error); 1205 break; 1206 } 1207 } 1208 #endif /* DP83820 */ 1209 1210 /* 1211 * Ensure we have enough descriptors free to describe 1212 * the packet. Note, we always reserve one descriptor 1213 * at the end of the ring as a termination point, to 1214 * prevent wrap-around. 1215 */ 1216 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1217 /* 1218 * Not enough free descriptors to transmit this 1219 * packet. We haven't committed anything yet, 1220 * so just unload the DMA map, put the packet 1221 * back on the queue, and punt. Notify the upper 1222 * layer that there are not more slots left. 1223 * 1224 * XXX We could allocate an mbuf and copy, but 1225 * XXX is it worth it? 1226 */ 1227 ifp->if_flags |= IFF_OACTIVE; 1228 bus_dmamap_unload(sc->sc_dmat, dmamap); 1229 #ifndef DP83820 1230 if (m != NULL) 1231 m_freem(m); 1232 #endif 1233 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1234 break; 1235 } 1236 1237 IFQ_DEQUEUE(&ifp->if_snd, m0); 1238 #ifndef DP83820 1239 if (m != NULL) { 1240 m_freem(m0); 1241 m0 = m; 1242 } 1243 #endif 1244 1245 /* 1246 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1247 */ 1248 1249 /* Sync the DMA map. */ 1250 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1251 BUS_DMASYNC_PREWRITE); 1252 1253 /* 1254 * Initialize the transmit descriptors. 1255 */ 1256 for (nexttx = sc->sc_txnext, seg = 0; 1257 seg < dmamap->dm_nsegs; 1258 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1259 /* 1260 * If this is the first descriptor we're 1261 * enqueueing, don't set the OWN bit just 1262 * yet. That could cause a race condition. 1263 * We'll do it below. 1264 */ 1265 sc->sc_txdescs[nexttx].sipd_bufptr = 1266 htole32(dmamap->dm_segs[seg].ds_addr); 1267 sc->sc_txdescs[nexttx].sipd_cmdsts = 1268 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1269 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1270 #ifdef DP83820 1271 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1272 #endif /* DP83820 */ 1273 lasttx = nexttx; 1274 } 1275 1276 /* Clear the MORE bit on the last segment. */ 1277 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1278 1279 /* 1280 * If we're in the interrupt delay window, delay the 1281 * interrupt. 1282 */ 1283 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1284 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1285 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1286 htole32(CMDSTS_INTR); 1287 sc->sc_txwin = 0; 1288 } 1289 1290 #ifdef DP83820 1291 /* 1292 * If VLANs are enabled and the packet has a VLAN tag, set 1293 * up the descriptor to encapsulate the packet for us. 1294 * 1295 * This apparently has to be on the last descriptor of 1296 * the packet. 1297 */ 1298 if (sc->sc_ethercom.ec_nvlans != 0 && 1299 (m = m_aux_find(m0, AF_LINK, ETHERTYPE_VLAN)) != NULL) { 1300 sc->sc_txdescs[lasttx].sipd_extsts |= 1301 htole32(EXTSTS_VPKT | 1302 htons(*mtod(m, int *) & EXTSTS_VTCI)); 1303 } 1304 1305 /* 1306 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1307 * checksumming, set up the descriptor to do this work 1308 * for us. 1309 * 1310 * This apparently has to be on the first descriptor of 1311 * the packet. 1312 * 1313 * Byte-swap constants so the compiler can optimize. 1314 */ 1315 extsts = 0; 1316 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1317 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1318 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1319 extsts |= htole32(EXTSTS_IPPKT); 1320 } 1321 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1322 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1323 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1324 extsts |= htole32(EXTSTS_TCPPKT); 1325 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1326 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1327 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1328 extsts |= htole32(EXTSTS_UDPPKT); 1329 } 1330 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1331 #endif /* DP83820 */ 1332 1333 /* Sync the descriptors we're using. */ 1334 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1335 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1336 1337 /* 1338 * The entire packet is set up. Give the first descrptor 1339 * to the chip now. 1340 */ 1341 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1342 htole32(CMDSTS_OWN); 1343 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1344 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1345 1346 /* 1347 * Store a pointer to the packet so we can free it later, 1348 * and remember what txdirty will be once the packet is 1349 * done. 1350 */ 1351 txs->txs_mbuf = m0; 1352 txs->txs_firstdesc = sc->sc_txnext; 1353 txs->txs_lastdesc = lasttx; 1354 1355 /* Advance the tx pointer. */ 1356 sc->sc_txfree -= dmamap->dm_nsegs; 1357 sc->sc_txnext = nexttx; 1358 1359 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1360 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1361 1362 #if NBPFILTER > 0 1363 /* 1364 * Pass the packet to any BPF listeners. 1365 */ 1366 if (ifp->if_bpf) 1367 bpf_mtap(ifp->if_bpf, m0); 1368 #endif /* NBPFILTER > 0 */ 1369 } 1370 1371 if (txs == NULL || sc->sc_txfree == 0) { 1372 /* No more slots left; notify upper layer. */ 1373 ifp->if_flags |= IFF_OACTIVE; 1374 } 1375 1376 if (sc->sc_txfree != ofree) { 1377 /* 1378 * Start the transmit process. Note, the manual says 1379 * that if there are no pending transmissions in the 1380 * chip's internal queue (indicated by TXE being clear), 1381 * then the driver software must set the TXDP to the 1382 * first descriptor to be transmitted. However, if we 1383 * do this, it causes serious performance degredation on 1384 * the DP83820 under load, not setting TXDP doesn't seem 1385 * to adversely affect the SiS 900 or DP83815. 1386 * 1387 * Well, I guess it wouldn't be the first time a manual 1388 * has lied -- and they could be speaking of the NULL- 1389 * terminated descriptor list case, rather than OWN- 1390 * terminated rings. 1391 */ 1392 #if 0 1393 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1394 CR_TXE) == 0) { 1395 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1396 SIP_CDTXADDR(sc, firsttx)); 1397 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1398 } 1399 #else 1400 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1401 #endif 1402 1403 /* Set a watchdog timer in case the chip flakes out. */ 1404 ifp->if_timer = 5; 1405 } 1406 } 1407 1408 /* 1409 * sip_watchdog: [ifnet interface function] 1410 * 1411 * Watchdog timer handler. 1412 */ 1413 void 1414 SIP_DECL(watchdog)(struct ifnet *ifp) 1415 { 1416 struct sip_softc *sc = ifp->if_softc; 1417 1418 /* 1419 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1420 * If we get a timeout, try and sweep up transmit descriptors. 1421 * If we manage to sweep them all up, ignore the lack of 1422 * interrupt. 1423 */ 1424 SIP_DECL(txintr)(sc); 1425 1426 if (sc->sc_txfree != SIP_NTXDESC) { 1427 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1428 ifp->if_oerrors++; 1429 1430 /* Reset the interface. */ 1431 (void) SIP_DECL(init)(ifp); 1432 } else if (ifp->if_flags & IFF_DEBUG) 1433 printf("%s: recovered from device timeout\n", 1434 sc->sc_dev.dv_xname); 1435 1436 /* Try to get more packets going. */ 1437 SIP_DECL(start)(ifp); 1438 } 1439 1440 /* 1441 * sip_ioctl: [ifnet interface function] 1442 * 1443 * Handle control requests from the operator. 1444 */ 1445 int 1446 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1447 { 1448 struct sip_softc *sc = ifp->if_softc; 1449 struct ifreq *ifr = (struct ifreq *)data; 1450 int s, error; 1451 1452 s = splnet(); 1453 1454 switch (cmd) { 1455 case SIOCSIFMEDIA: 1456 case SIOCGIFMEDIA: 1457 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1458 break; 1459 1460 default: 1461 error = ether_ioctl(ifp, cmd, data); 1462 if (error == ENETRESET) { 1463 /* 1464 * Multicast list has changed; set the hardware filter 1465 * accordingly. 1466 */ 1467 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1468 error = 0; 1469 } 1470 break; 1471 } 1472 1473 /* Try to get more packets going. */ 1474 SIP_DECL(start)(ifp); 1475 1476 splx(s); 1477 return (error); 1478 } 1479 1480 /* 1481 * sip_intr: 1482 * 1483 * Interrupt service routine. 1484 */ 1485 int 1486 SIP_DECL(intr)(void *arg) 1487 { 1488 struct sip_softc *sc = arg; 1489 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1490 u_int32_t isr; 1491 int handled = 0; 1492 1493 for (;;) { 1494 /* Reading clears interrupt. */ 1495 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1496 if ((isr & sc->sc_imr) == 0) 1497 break; 1498 1499 handled = 1; 1500 1501 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1502 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1503 1504 /* Grab any new packets. */ 1505 SIP_DECL(rxintr)(sc); 1506 1507 if (isr & ISR_RXORN) { 1508 printf("%s: receive FIFO overrun\n", 1509 sc->sc_dev.dv_xname); 1510 1511 /* XXX adjust rx_drain_thresh? */ 1512 } 1513 1514 if (isr & ISR_RXIDLE) { 1515 printf("%s: receive ring overrun\n", 1516 sc->sc_dev.dv_xname); 1517 1518 /* Get the receive process going again. */ 1519 bus_space_write_4(sc->sc_st, sc->sc_sh, 1520 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1521 bus_space_write_4(sc->sc_st, sc->sc_sh, 1522 SIP_CR, CR_RXE); 1523 } 1524 } 1525 1526 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1527 #ifdef SIP_EVENT_COUNTERS 1528 if (isr & ISR_TXDESC) 1529 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1530 else if (isr & ISR_TXIDLE) 1531 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1532 #endif 1533 1534 /* Sweep up transmit descriptors. */ 1535 SIP_DECL(txintr)(sc); 1536 1537 if (isr & ISR_TXURN) { 1538 u_int32_t thresh; 1539 1540 printf("%s: transmit FIFO underrun", 1541 sc->sc_dev.dv_xname); 1542 1543 thresh = sc->sc_tx_drain_thresh + 1; 1544 if (thresh <= TXCFG_DRTH && 1545 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1546 (sc->sc_tx_fill_thresh * 32))) { 1547 printf("; increasing Tx drain " 1548 "threshold to %u bytes\n", 1549 thresh * 32); 1550 sc->sc_tx_drain_thresh = thresh; 1551 (void) SIP_DECL(init)(ifp); 1552 } else { 1553 (void) SIP_DECL(init)(ifp); 1554 printf("\n"); 1555 } 1556 } 1557 } 1558 1559 #if !defined(DP83820) 1560 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1561 if (isr & ISR_PAUSE_ST) { 1562 sc->sc_flags |= SIPF_PAUSED; 1563 ifp->if_flags |= IFF_OACTIVE; 1564 } 1565 if (isr & ISR_PAUSE_END) { 1566 sc->sc_flags &= ~SIPF_PAUSED; 1567 ifp->if_flags &= ~IFF_OACTIVE; 1568 } 1569 } 1570 #endif /* ! DP83820 */ 1571 1572 if (isr & ISR_HIBERR) { 1573 #define PRINTERR(bit, str) \ 1574 if (isr & (bit)) \ 1575 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1576 PRINTERR(ISR_DPERR, "parity error"); 1577 PRINTERR(ISR_SSERR, "system error"); 1578 PRINTERR(ISR_RMABT, "master abort"); 1579 PRINTERR(ISR_RTABT, "target abort"); 1580 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1581 (void) SIP_DECL(init)(ifp); 1582 #undef PRINTERR 1583 } 1584 } 1585 1586 /* Try to get more packets going. */ 1587 SIP_DECL(start)(ifp); 1588 1589 return (handled); 1590 } 1591 1592 /* 1593 * sip_txintr: 1594 * 1595 * Helper; handle transmit interrupts. 1596 */ 1597 void 1598 SIP_DECL(txintr)(struct sip_softc *sc) 1599 { 1600 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1601 struct sip_txsoft *txs; 1602 u_int32_t cmdsts; 1603 1604 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1605 ifp->if_flags &= ~IFF_OACTIVE; 1606 1607 /* 1608 * Go through our Tx list and free mbufs for those 1609 * frames which have been transmitted. 1610 */ 1611 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1612 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1613 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1614 1615 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1616 if (cmdsts & CMDSTS_OWN) 1617 break; 1618 1619 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1620 1621 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1622 1623 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1624 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1625 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1626 m_freem(txs->txs_mbuf); 1627 txs->txs_mbuf = NULL; 1628 1629 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1630 1631 /* 1632 * Check for errors and collisions. 1633 */ 1634 if (cmdsts & 1635 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1636 ifp->if_oerrors++; 1637 if (cmdsts & CMDSTS_Tx_EC) 1638 ifp->if_collisions += 16; 1639 if (ifp->if_flags & IFF_DEBUG) { 1640 if (cmdsts & CMDSTS_Tx_ED) 1641 printf("%s: excessive deferral\n", 1642 sc->sc_dev.dv_xname); 1643 if (cmdsts & CMDSTS_Tx_EC) 1644 printf("%s: excessive collisions\n", 1645 sc->sc_dev.dv_xname); 1646 } 1647 } else { 1648 /* Packet was transmitted successfully. */ 1649 ifp->if_opackets++; 1650 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1651 } 1652 } 1653 1654 /* 1655 * If there are no more pending transmissions, cancel the watchdog 1656 * timer. 1657 */ 1658 if (txs == NULL) { 1659 ifp->if_timer = 0; 1660 sc->sc_txwin = 0; 1661 } 1662 } 1663 1664 #if defined(DP83820) 1665 /* 1666 * sip_rxintr: 1667 * 1668 * Helper; handle receive interrupts. 1669 */ 1670 void 1671 SIP_DECL(rxintr)(struct sip_softc *sc) 1672 { 1673 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1674 struct sip_rxsoft *rxs; 1675 struct mbuf *m, *tailm; 1676 u_int32_t cmdsts, extsts; 1677 int i, len; 1678 1679 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1680 rxs = &sc->sc_rxsoft[i]; 1681 1682 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1683 1684 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1685 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1686 1687 /* 1688 * NOTE: OWN is set if owned by _consumer_. We're the 1689 * consumer of the receive ring, so if the bit is clear, 1690 * we have processed all of the packets. 1691 */ 1692 if ((cmdsts & CMDSTS_OWN) == 0) { 1693 /* 1694 * We have processed all of the receive buffers. 1695 */ 1696 break; 1697 } 1698 1699 if (__predict_false(sc->sc_rxdiscard)) { 1700 SIP_INIT_RXDESC(sc, i); 1701 if ((cmdsts & CMDSTS_MORE) == 0) { 1702 /* Reset our state. */ 1703 sc->sc_rxdiscard = 0; 1704 } 1705 continue; 1706 } 1707 1708 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1709 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1710 1711 m = rxs->rxs_mbuf; 1712 1713 /* 1714 * Add a new receive buffer to the ring. 1715 */ 1716 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1717 /* 1718 * Failed, throw away what we've done so 1719 * far, and discard the rest of the packet. 1720 */ 1721 ifp->if_ierrors++; 1722 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1723 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1724 SIP_INIT_RXDESC(sc, i); 1725 if (cmdsts & CMDSTS_MORE) 1726 sc->sc_rxdiscard = 1; 1727 if (sc->sc_rxhead != NULL) 1728 m_freem(sc->sc_rxhead); 1729 SIP_RXCHAIN_RESET(sc); 1730 continue; 1731 } 1732 1733 SIP_RXCHAIN_LINK(sc, m); 1734 1735 /* 1736 * If this is not the end of the packet, keep 1737 * looking. 1738 */ 1739 if (cmdsts & CMDSTS_MORE) { 1740 sc->sc_rxlen += m->m_len; 1741 continue; 1742 } 1743 1744 /* 1745 * Okay, we have the entire packet now... 1746 */ 1747 *sc->sc_rxtailp = NULL; 1748 m = sc->sc_rxhead; 1749 tailm = sc->sc_rxtail; 1750 1751 SIP_RXCHAIN_RESET(sc); 1752 1753 /* 1754 * If an error occurred, update stats and drop the packet. 1755 */ 1756 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1757 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1758 ifp->if_ierrors++; 1759 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1760 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1761 /* Receive overrun handled elsewhere. */ 1762 printf("%s: receive descriptor error\n", 1763 sc->sc_dev.dv_xname); 1764 } 1765 #define PRINTERR(bit, str) \ 1766 if (cmdsts & (bit)) \ 1767 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1768 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1769 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1770 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1771 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1772 #undef PRINTERR 1773 m_freem(m); 1774 continue; 1775 } 1776 1777 /* 1778 * No errors. 1779 * 1780 * Note, the DP83820 includes the CRC with 1781 * every packet. 1782 */ 1783 len = CMDSTS_SIZE(cmdsts); 1784 tailm->m_len = len - sc->sc_rxlen; 1785 1786 /* 1787 * If the packet is small enough to fit in a 1788 * single header mbuf, allocate one and copy 1789 * the data into it. This greatly reduces 1790 * memory consumption when we receive lots 1791 * of small packets. 1792 */ 1793 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1794 struct mbuf *nm; 1795 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1796 if (nm == NULL) { 1797 ifp->if_ierrors++; 1798 m_freem(m); 1799 continue; 1800 } 1801 nm->m_data += 2; 1802 nm->m_pkthdr.len = nm->m_len = len; 1803 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1804 m_freem(m); 1805 m = nm; 1806 } 1807 #ifndef __NO_STRICT_ALIGNMENT 1808 else { 1809 /* 1810 * The DP83820's receive buffers must be 4-byte 1811 * aligned. But this means that the data after 1812 * the Ethernet header is misaligned. To compensate, 1813 * we have artificially shortened the buffer size 1814 * in the descriptor, and we do an overlapping copy 1815 * of the data two bytes further in (in the first 1816 * buffer of the chain only). 1817 */ 1818 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1819 m->m_len); 1820 m->m_data += 2; 1821 } 1822 #endif /* ! __NO_STRICT_ALIGNMENT */ 1823 1824 /* 1825 * If VLANs are enabled, VLAN packets have been unwrapped 1826 * for us. Associate the tag with the packet. 1827 */ 1828 if (sc->sc_ethercom.ec_nvlans != 0 && 1829 (extsts & EXTSTS_VPKT) != 0) { 1830 struct mbuf *vtag; 1831 1832 vtag = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 1833 if (vtag == NULL) { 1834 ifp->if_ierrors++; 1835 printf("%s: unable to allocate VLAN tag\n", 1836 sc->sc_dev.dv_xname); 1837 m_freem(m); 1838 continue; 1839 } 1840 1841 *mtod(vtag, int *) = ntohs(extsts & EXTSTS_VTCI); 1842 vtag->m_len = sizeof(int); 1843 } 1844 1845 /* 1846 * Set the incoming checksum information for the 1847 * packet. 1848 */ 1849 if ((extsts & EXTSTS_IPPKT) != 0) { 1850 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1851 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1852 if (extsts & EXTSTS_Rx_IPERR) 1853 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1854 if (extsts & EXTSTS_TCPPKT) { 1855 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1856 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1857 if (extsts & EXTSTS_Rx_TCPERR) 1858 m->m_pkthdr.csum_flags |= 1859 M_CSUM_TCP_UDP_BAD; 1860 } else if (extsts & EXTSTS_UDPPKT) { 1861 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1862 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1863 if (extsts & EXTSTS_Rx_UDPERR) 1864 m->m_pkthdr.csum_flags |= 1865 M_CSUM_TCP_UDP_BAD; 1866 } 1867 } 1868 1869 ifp->if_ipackets++; 1870 m->m_flags |= M_HASFCS; 1871 m->m_pkthdr.rcvif = ifp; 1872 m->m_pkthdr.len = len; 1873 1874 #if NBPFILTER > 0 1875 /* 1876 * Pass this up to any BPF listeners, but only 1877 * pass if up the stack if it's for us. 1878 */ 1879 if (ifp->if_bpf) 1880 bpf_mtap(ifp->if_bpf, m); 1881 #endif /* NBPFILTER > 0 */ 1882 1883 /* Pass it on. */ 1884 (*ifp->if_input)(ifp, m); 1885 } 1886 1887 /* Update the receive pointer. */ 1888 sc->sc_rxptr = i; 1889 } 1890 #else /* ! DP83820 */ 1891 /* 1892 * sip_rxintr: 1893 * 1894 * Helper; handle receive interrupts. 1895 */ 1896 void 1897 SIP_DECL(rxintr)(struct sip_softc *sc) 1898 { 1899 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1900 struct sip_rxsoft *rxs; 1901 struct mbuf *m; 1902 u_int32_t cmdsts; 1903 int i, len; 1904 1905 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1906 rxs = &sc->sc_rxsoft[i]; 1907 1908 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1909 1910 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1911 1912 /* 1913 * NOTE: OWN is set if owned by _consumer_. We're the 1914 * consumer of the receive ring, so if the bit is clear, 1915 * we have processed all of the packets. 1916 */ 1917 if ((cmdsts & CMDSTS_OWN) == 0) { 1918 /* 1919 * We have processed all of the receive buffers. 1920 */ 1921 break; 1922 } 1923 1924 /* 1925 * If any collisions were seen on the wire, count one. 1926 */ 1927 if (cmdsts & CMDSTS_Rx_COL) 1928 ifp->if_collisions++; 1929 1930 /* 1931 * If an error occurred, update stats, clear the status 1932 * word, and leave the packet buffer in place. It will 1933 * simply be reused the next time the ring comes around. 1934 */ 1935 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1936 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1937 ifp->if_ierrors++; 1938 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1939 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1940 /* Receive overrun handled elsewhere. */ 1941 printf("%s: receive descriptor error\n", 1942 sc->sc_dev.dv_xname); 1943 } 1944 #define PRINTERR(bit, str) \ 1945 if (cmdsts & (bit)) \ 1946 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1947 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1948 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1949 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1950 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1951 #undef PRINTERR 1952 SIP_INIT_RXDESC(sc, i); 1953 continue; 1954 } 1955 1956 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1957 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1958 1959 /* 1960 * No errors; receive the packet. Note, the SiS 900 1961 * includes the CRC with every packet. 1962 */ 1963 len = CMDSTS_SIZE(cmdsts); 1964 1965 #ifdef __NO_STRICT_ALIGNMENT 1966 /* 1967 * If the packet is small enough to fit in a 1968 * single header mbuf, allocate one and copy 1969 * the data into it. This greatly reduces 1970 * memory consumption when we receive lots 1971 * of small packets. 1972 * 1973 * Otherwise, we add a new buffer to the receive 1974 * chain. If this fails, we drop the packet and 1975 * recycle the old buffer. 1976 */ 1977 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 1978 MGETHDR(m, M_DONTWAIT, MT_DATA); 1979 if (m == NULL) 1980 goto dropit; 1981 memcpy(mtod(m, caddr_t), 1982 mtod(rxs->rxs_mbuf, caddr_t), len); 1983 SIP_INIT_RXDESC(sc, i); 1984 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1985 rxs->rxs_dmamap->dm_mapsize, 1986 BUS_DMASYNC_PREREAD); 1987 } else { 1988 m = rxs->rxs_mbuf; 1989 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1990 dropit: 1991 ifp->if_ierrors++; 1992 SIP_INIT_RXDESC(sc, i); 1993 bus_dmamap_sync(sc->sc_dmat, 1994 rxs->rxs_dmamap, 0, 1995 rxs->rxs_dmamap->dm_mapsize, 1996 BUS_DMASYNC_PREREAD); 1997 continue; 1998 } 1999 } 2000 #else 2001 /* 2002 * The SiS 900's receive buffers must be 4-byte aligned. 2003 * But this means that the data after the Ethernet header 2004 * is misaligned. We must allocate a new buffer and 2005 * copy the data, shifted forward 2 bytes. 2006 */ 2007 MGETHDR(m, M_DONTWAIT, MT_DATA); 2008 if (m == NULL) { 2009 dropit: 2010 ifp->if_ierrors++; 2011 SIP_INIT_RXDESC(sc, i); 2012 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2013 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2014 continue; 2015 } 2016 if (len > (MHLEN - 2)) { 2017 MCLGET(m, M_DONTWAIT); 2018 if ((m->m_flags & M_EXT) == 0) { 2019 m_freem(m); 2020 goto dropit; 2021 } 2022 } 2023 m->m_data += 2; 2024 2025 /* 2026 * Note that we use clusters for incoming frames, so the 2027 * buffer is virtually contiguous. 2028 */ 2029 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 2030 2031 /* Allow the receive descriptor to continue using its mbuf. */ 2032 SIP_INIT_RXDESC(sc, i); 2033 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2034 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2035 #endif /* __NO_STRICT_ALIGNMENT */ 2036 2037 ifp->if_ipackets++; 2038 m->m_flags |= M_HASFCS; 2039 m->m_pkthdr.rcvif = ifp; 2040 m->m_pkthdr.len = m->m_len = len; 2041 2042 #if NBPFILTER > 0 2043 /* 2044 * Pass this up to any BPF listeners, but only 2045 * pass if up the stack if it's for us. 2046 */ 2047 if (ifp->if_bpf) 2048 bpf_mtap(ifp->if_bpf, m); 2049 #endif /* NBPFILTER > 0 */ 2050 2051 /* Pass it on. */ 2052 (*ifp->if_input)(ifp, m); 2053 } 2054 2055 /* Update the receive pointer. */ 2056 sc->sc_rxptr = i; 2057 } 2058 #endif /* DP83820 */ 2059 2060 /* 2061 * sip_tick: 2062 * 2063 * One second timer, used to tick the MII. 2064 */ 2065 void 2066 SIP_DECL(tick)(void *arg) 2067 { 2068 struct sip_softc *sc = arg; 2069 int s; 2070 2071 s = splnet(); 2072 mii_tick(&sc->sc_mii); 2073 splx(s); 2074 2075 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2076 } 2077 2078 /* 2079 * sip_reset: 2080 * 2081 * Perform a soft reset on the SiS 900. 2082 */ 2083 void 2084 SIP_DECL(reset)(struct sip_softc *sc) 2085 { 2086 bus_space_tag_t st = sc->sc_st; 2087 bus_space_handle_t sh = sc->sc_sh; 2088 int i; 2089 2090 bus_space_write_4(st, sh, SIP_IER, 0); 2091 bus_space_write_4(st, sh, SIP_IMR, 0); 2092 bus_space_write_4(st, sh, SIP_RFCR, 0); 2093 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2094 2095 for (i = 0; i < SIP_TIMEOUT; i++) { 2096 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2097 break; 2098 delay(2); 2099 } 2100 2101 if (i == SIP_TIMEOUT) 2102 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2103 2104 delay(1000); 2105 2106 #ifdef DP83820 2107 /* 2108 * Set the general purpose I/O bits. Do it here in case we 2109 * need to have GPIO set up to talk to the media interface. 2110 */ 2111 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2112 delay(1000); 2113 #endif /* DP83820 */ 2114 } 2115 2116 /* 2117 * sip_init: [ ifnet interface function ] 2118 * 2119 * Initialize the interface. Must be called at splnet(). 2120 */ 2121 int 2122 SIP_DECL(init)(struct ifnet *ifp) 2123 { 2124 struct sip_softc *sc = ifp->if_softc; 2125 bus_space_tag_t st = sc->sc_st; 2126 bus_space_handle_t sh = sc->sc_sh; 2127 struct sip_txsoft *txs; 2128 struct sip_rxsoft *rxs; 2129 struct sip_desc *sipd; 2130 u_int32_t reg; 2131 int i, error = 0; 2132 2133 /* 2134 * Cancel any pending I/O. 2135 */ 2136 SIP_DECL(stop)(ifp, 0); 2137 2138 /* 2139 * Reset the chip to a known state. 2140 */ 2141 SIP_DECL(reset)(sc); 2142 2143 #if !defined(DP83820) 2144 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2145 /* 2146 * DP83815 manual, page 78: 2147 * 4.4 Recommended Registers Configuration 2148 * For optimum performance of the DP83815, version noted 2149 * as DP83815CVNG (SRR = 203h), the listed register 2150 * modifications must be followed in sequence... 2151 * 2152 * It's not clear if this should be 302h or 203h because that 2153 * chip name is listed as SRR 302h in the description of the 2154 * SRR register. However, my revision 302h DP83815 on the 2155 * Netgear FA311 purchased in 02/2001 needs these settings 2156 * to avoid tons of errors in AcceptPerfectMatch (non- 2157 * IFF_PROMISC) mode. I do not know if other revisions need 2158 * this set or not. [briggs -- 09 March 2001] 2159 * 2160 * Note that only the low-order 12 bits of 0xe4 are documented 2161 * and that this sets reserved bits in that register. 2162 */ 2163 reg = bus_space_read_4(st, sh, SIP_NS_SRR); 2164 if (reg == 0x302) { 2165 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2166 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2167 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2168 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2169 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2170 } 2171 } 2172 #endif /* ! DP83820 */ 2173 2174 /* 2175 * Initialize the transmit descriptor ring. 2176 */ 2177 for (i = 0; i < SIP_NTXDESC; i++) { 2178 sipd = &sc->sc_txdescs[i]; 2179 memset(sipd, 0, sizeof(struct sip_desc)); 2180 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2181 } 2182 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2183 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2184 sc->sc_txfree = SIP_NTXDESC; 2185 sc->sc_txnext = 0; 2186 sc->sc_txwin = 0; 2187 2188 /* 2189 * Initialize the transmit job descriptors. 2190 */ 2191 SIMPLEQ_INIT(&sc->sc_txfreeq); 2192 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2193 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2194 txs = &sc->sc_txsoft[i]; 2195 txs->txs_mbuf = NULL; 2196 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2197 } 2198 2199 /* 2200 * Initialize the receive descriptor and receive job 2201 * descriptor rings. 2202 */ 2203 for (i = 0; i < SIP_NRXDESC; i++) { 2204 rxs = &sc->sc_rxsoft[i]; 2205 if (rxs->rxs_mbuf == NULL) { 2206 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2207 printf("%s: unable to allocate or map rx " 2208 "buffer %d, error = %d\n", 2209 sc->sc_dev.dv_xname, i, error); 2210 /* 2211 * XXX Should attempt to run with fewer receive 2212 * XXX buffers instead of just failing. 2213 */ 2214 SIP_DECL(rxdrain)(sc); 2215 goto out; 2216 } 2217 } else 2218 SIP_INIT_RXDESC(sc, i); 2219 } 2220 sc->sc_rxptr = 0; 2221 #ifdef DP83820 2222 sc->sc_rxdiscard = 0; 2223 SIP_RXCHAIN_RESET(sc); 2224 #endif /* DP83820 */ 2225 2226 /* 2227 * Set the configuration register; it's already initialized 2228 * in sip_attach(). 2229 */ 2230 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2231 2232 /* 2233 * Initialize the prototype TXCFG register. 2234 */ 2235 #if defined(DP83820) 2236 sc->sc_txcfg = TXCFG_MXDMA_512; 2237 sc->sc_rxcfg = RXCFG_MXDMA_512; 2238 #else 2239 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2240 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2241 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & CFG_EDBMASTEN)) { 2242 sc->sc_txcfg = TXCFG_MXDMA_64; 2243 sc->sc_rxcfg = RXCFG_MXDMA_64; 2244 } else { 2245 sc->sc_txcfg = TXCFG_MXDMA_512; 2246 sc->sc_rxcfg = RXCFG_MXDMA_512; 2247 } 2248 #endif /* DP83820 */ 2249 2250 sc->sc_txcfg |= TXCFG_ATP | 2251 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2252 sc->sc_tx_drain_thresh; 2253 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2254 2255 /* 2256 * Initialize the receive drain threshold if we have never 2257 * done so. 2258 */ 2259 if (sc->sc_rx_drain_thresh == 0) { 2260 /* 2261 * XXX This value should be tuned. This is set to the 2262 * maximum of 248 bytes, and we may be able to improve 2263 * performance by decreasing it (although we should never 2264 * set this value lower than 2; 14 bytes are required to 2265 * filter the packet). 2266 */ 2267 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2268 } 2269 2270 /* 2271 * Initialize the prototype RXCFG register. 2272 */ 2273 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2274 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2275 2276 #ifdef DP83820 2277 /* 2278 * Initialize the VLAN/IP receive control register. 2279 * We enable checksum computation on all incoming 2280 * packets, and do not reject packets w/ bad checksums. 2281 */ 2282 reg = 0; 2283 if (ifp->if_capenable & 2284 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2285 reg |= VRCR_IPEN; 2286 if (sc->sc_ethercom.ec_nvlans != 0) 2287 reg |= VRCR_VTDEN|VRCR_VTREN; 2288 bus_space_write_4(st, sh, SIP_VRCR, reg); 2289 2290 /* 2291 * Initialize the VLAN/IP transmit control register. 2292 * We enable outgoing checksum computation on a 2293 * per-packet basis. 2294 */ 2295 reg = 0; 2296 if (ifp->if_capenable & 2297 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2298 reg |= VTCR_PPCHK; 2299 if (sc->sc_ethercom.ec_nvlans != 0) 2300 reg |= VTCR_VPPTI; 2301 bus_space_write_4(st, sh, SIP_VTCR, reg); 2302 2303 /* 2304 * If we're using VLANs, initialize the VLAN data register. 2305 * To understand why we bswap the VLAN Ethertype, see section 2306 * 4.2.36 of the DP83820 manual. 2307 */ 2308 if (sc->sc_ethercom.ec_nvlans != 0) 2309 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2310 #endif /* DP83820 */ 2311 2312 /* 2313 * Give the transmit and receive rings to the chip. 2314 */ 2315 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2316 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2317 2318 /* 2319 * Initialize the interrupt mask. 2320 */ 2321 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2322 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2323 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2324 2325 /* Set up the receive filter. */ 2326 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2327 2328 /* 2329 * Set the current media. Do this after initializing the prototype 2330 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2331 * control. 2332 */ 2333 mii_mediachg(&sc->sc_mii); 2334 2335 /* 2336 * Enable interrupts. 2337 */ 2338 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2339 2340 /* 2341 * Start the transmit and receive processes. 2342 */ 2343 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2344 2345 /* 2346 * Start the one second MII clock. 2347 */ 2348 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2349 2350 /* 2351 * ...all done! 2352 */ 2353 ifp->if_flags |= IFF_RUNNING; 2354 ifp->if_flags &= ~IFF_OACTIVE; 2355 2356 out: 2357 if (error) 2358 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2359 return (error); 2360 } 2361 2362 /* 2363 * sip_drain: 2364 * 2365 * Drain the receive queue. 2366 */ 2367 void 2368 SIP_DECL(rxdrain)(struct sip_softc *sc) 2369 { 2370 struct sip_rxsoft *rxs; 2371 int i; 2372 2373 for (i = 0; i < SIP_NRXDESC; i++) { 2374 rxs = &sc->sc_rxsoft[i]; 2375 if (rxs->rxs_mbuf != NULL) { 2376 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2377 m_freem(rxs->rxs_mbuf); 2378 rxs->rxs_mbuf = NULL; 2379 } 2380 } 2381 } 2382 2383 /* 2384 * sip_stop: [ ifnet interface function ] 2385 * 2386 * Stop transmission on the interface. 2387 */ 2388 void 2389 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2390 { 2391 struct sip_softc *sc = ifp->if_softc; 2392 bus_space_tag_t st = sc->sc_st; 2393 bus_space_handle_t sh = sc->sc_sh; 2394 struct sip_txsoft *txs; 2395 u_int32_t cmdsts = 0; /* DEBUG */ 2396 2397 /* 2398 * Stop the one second clock. 2399 */ 2400 callout_stop(&sc->sc_tick_ch); 2401 2402 /* Down the MII. */ 2403 mii_down(&sc->sc_mii); 2404 2405 /* 2406 * Disable interrupts. 2407 */ 2408 bus_space_write_4(st, sh, SIP_IER, 0); 2409 2410 /* 2411 * Stop receiver and transmitter. 2412 */ 2413 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2414 2415 /* 2416 * Release any queued transmit buffers. 2417 */ 2418 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2419 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2420 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2421 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2422 CMDSTS_INTR) == 0) 2423 printf("%s: sip_stop: last descriptor does not " 2424 "have INTR bit set\n", sc->sc_dev.dv_xname); 2425 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2426 #ifdef DIAGNOSTIC 2427 if (txs->txs_mbuf == NULL) { 2428 printf("%s: dirty txsoft with no mbuf chain\n", 2429 sc->sc_dev.dv_xname); 2430 panic("sip_stop"); 2431 } 2432 #endif 2433 cmdsts |= /* DEBUG */ 2434 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2435 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2436 m_freem(txs->txs_mbuf); 2437 txs->txs_mbuf = NULL; 2438 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2439 } 2440 2441 if (disable) 2442 SIP_DECL(rxdrain)(sc); 2443 2444 /* 2445 * Mark the interface down and cancel the watchdog timer. 2446 */ 2447 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2448 ifp->if_timer = 0; 2449 2450 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2451 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2452 printf("%s: sip_stop: no INTR bits set in dirty tx " 2453 "descriptors\n", sc->sc_dev.dv_xname); 2454 } 2455 2456 /* 2457 * sip_read_eeprom: 2458 * 2459 * Read data from the serial EEPROM. 2460 */ 2461 void 2462 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2463 u_int16_t *data) 2464 { 2465 bus_space_tag_t st = sc->sc_st; 2466 bus_space_handle_t sh = sc->sc_sh; 2467 u_int16_t reg; 2468 int i, x; 2469 2470 for (i = 0; i < wordcnt; i++) { 2471 /* Send CHIP SELECT. */ 2472 reg = EROMAR_EECS; 2473 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2474 2475 /* Shift in the READ opcode. */ 2476 for (x = 3; x > 0; x--) { 2477 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2478 reg |= EROMAR_EEDI; 2479 else 2480 reg &= ~EROMAR_EEDI; 2481 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2482 bus_space_write_4(st, sh, SIP_EROMAR, 2483 reg | EROMAR_EESK); 2484 delay(4); 2485 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2486 delay(4); 2487 } 2488 2489 /* Shift in address. */ 2490 for (x = 6; x > 0; x--) { 2491 if ((word + i) & (1 << (x - 1))) 2492 reg |= EROMAR_EEDI; 2493 else 2494 reg &= ~EROMAR_EEDI; 2495 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2496 bus_space_write_4(st, sh, SIP_EROMAR, 2497 reg | EROMAR_EESK); 2498 delay(4); 2499 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2500 delay(4); 2501 } 2502 2503 /* Shift out data. */ 2504 reg = EROMAR_EECS; 2505 data[i] = 0; 2506 for (x = 16; x > 0; x--) { 2507 bus_space_write_4(st, sh, SIP_EROMAR, 2508 reg | EROMAR_EESK); 2509 delay(4); 2510 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2511 data[i] |= (1 << (x - 1)); 2512 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2513 delay(4); 2514 } 2515 2516 /* Clear CHIP SELECT. */ 2517 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2518 delay(4); 2519 } 2520 } 2521 2522 /* 2523 * sip_add_rxbuf: 2524 * 2525 * Add a receive buffer to the indicated descriptor. 2526 */ 2527 int 2528 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2529 { 2530 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2531 struct mbuf *m; 2532 int error; 2533 2534 MGETHDR(m, M_DONTWAIT, MT_DATA); 2535 if (m == NULL) 2536 return (ENOBUFS); 2537 2538 MCLGET(m, M_DONTWAIT); 2539 if ((m->m_flags & M_EXT) == 0) { 2540 m_freem(m); 2541 return (ENOBUFS); 2542 } 2543 2544 #if defined(DP83820) 2545 m->m_len = SIP_RXBUF_LEN; 2546 #endif /* DP83820 */ 2547 2548 if (rxs->rxs_mbuf != NULL) 2549 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2550 2551 rxs->rxs_mbuf = m; 2552 2553 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2554 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2555 BUS_DMA_READ|BUS_DMA_NOWAIT); 2556 if (error) { 2557 printf("%s: can't load rx DMA map %d, error = %d\n", 2558 sc->sc_dev.dv_xname, idx, error); 2559 panic("sip_add_rxbuf"); /* XXX */ 2560 } 2561 2562 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2563 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2564 2565 SIP_INIT_RXDESC(sc, idx); 2566 2567 return (0); 2568 } 2569 2570 #if !defined(DP83820) 2571 /* 2572 * sip_sis900_set_filter: 2573 * 2574 * Set up the receive filter. 2575 */ 2576 void 2577 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2578 { 2579 bus_space_tag_t st = sc->sc_st; 2580 bus_space_handle_t sh = sc->sc_sh; 2581 struct ethercom *ec = &sc->sc_ethercom; 2582 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2583 struct ether_multi *enm; 2584 u_int8_t *cp; 2585 struct ether_multistep step; 2586 u_int32_t crc, mchash[16]; 2587 2588 /* 2589 * Initialize the prototype RFCR. 2590 */ 2591 sc->sc_rfcr = RFCR_RFEN; 2592 if (ifp->if_flags & IFF_BROADCAST) 2593 sc->sc_rfcr |= RFCR_AAB; 2594 if (ifp->if_flags & IFF_PROMISC) { 2595 sc->sc_rfcr |= RFCR_AAP; 2596 goto allmulti; 2597 } 2598 2599 /* 2600 * Set up the multicast address filter by passing all multicast 2601 * addresses through a CRC generator, and then using the high-order 2602 * 6 bits as an index into the 128 bit multicast hash table (only 2603 * the lower 16 bits of each 32 bit multicast hash register are 2604 * valid). The high order bits select the register, while the 2605 * rest of the bits select the bit within the register. 2606 */ 2607 2608 memset(mchash, 0, sizeof(mchash)); 2609 2610 ETHER_FIRST_MULTI(step, ec, enm); 2611 while (enm != NULL) { 2612 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2613 /* 2614 * We must listen to a range of multicast addresses. 2615 * For now, just accept all multicasts, rather than 2616 * trying to set only those filter bits needed to match 2617 * the range. (At this time, the only use of address 2618 * ranges is for IP multicast routing, for which the 2619 * range is big enough to require all bits set.) 2620 */ 2621 goto allmulti; 2622 } 2623 2624 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2625 2626 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2627 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2628 /* Just want the 8 most significant bits. */ 2629 crc >>= 24; 2630 } else { 2631 /* Just want the 7 most significant bits. */ 2632 crc >>= 25; 2633 } 2634 2635 /* Set the corresponding bit in the hash table. */ 2636 mchash[crc >> 4] |= 1 << (crc & 0xf); 2637 2638 ETHER_NEXT_MULTI(step, enm); 2639 } 2640 2641 ifp->if_flags &= ~IFF_ALLMULTI; 2642 goto setit; 2643 2644 allmulti: 2645 ifp->if_flags |= IFF_ALLMULTI; 2646 sc->sc_rfcr |= RFCR_AAM; 2647 2648 setit: 2649 #define FILTER_EMIT(addr, data) \ 2650 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2651 delay(1); \ 2652 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2653 delay(1) 2654 2655 /* 2656 * Disable receive filter, and program the node address. 2657 */ 2658 cp = LLADDR(ifp->if_sadl); 2659 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2660 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2661 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2662 2663 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2664 /* 2665 * Program the multicast hash table. 2666 */ 2667 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2668 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2669 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2670 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2671 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2672 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2673 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2674 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2675 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2676 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2677 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2678 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2679 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2680 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2681 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2682 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2683 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2684 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2685 } 2686 } 2687 #undef FILTER_EMIT 2688 2689 /* 2690 * Re-enable the receiver filter. 2691 */ 2692 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2693 } 2694 #endif /* ! DP83820 */ 2695 2696 /* 2697 * sip_dp83815_set_filter: 2698 * 2699 * Set up the receive filter. 2700 */ 2701 void 2702 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2703 { 2704 bus_space_tag_t st = sc->sc_st; 2705 bus_space_handle_t sh = sc->sc_sh; 2706 struct ethercom *ec = &sc->sc_ethercom; 2707 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2708 struct ether_multi *enm; 2709 u_int8_t *cp; 2710 struct ether_multistep step; 2711 u_int32_t crc, hash, slot, bit; 2712 #ifdef DP83820 2713 #define MCHASH_NWORDS 128 2714 #else 2715 #define MCHASH_NWORDS 32 2716 #endif /* DP83820 */ 2717 u_int16_t mchash[MCHASH_NWORDS]; 2718 int i; 2719 2720 /* 2721 * Initialize the prototype RFCR. 2722 * Enable the receive filter, and accept on 2723 * Perfect (destination address) Match 2724 * If IFF_BROADCAST, also accept all broadcast packets. 2725 * If IFF_PROMISC, accept all unicast packets (and later, set 2726 * IFF_ALLMULTI and accept all multicast, too). 2727 */ 2728 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2729 if (ifp->if_flags & IFF_BROADCAST) 2730 sc->sc_rfcr |= RFCR_AAB; 2731 if (ifp->if_flags & IFF_PROMISC) { 2732 sc->sc_rfcr |= RFCR_AAP; 2733 goto allmulti; 2734 } 2735 2736 #ifdef DP83820 2737 /* 2738 * Set up the DP83820 multicast address filter by passing all multicast 2739 * addresses through a CRC generator, and then using the high-order 2740 * 11 bits as an index into the 2048 bit multicast hash table. The 2741 * high-order 7 bits select the slot, while the low-order 4 bits 2742 * select the bit within the slot. Note that only the low 16-bits 2743 * of each filter word are used, and there are 128 filter words. 2744 */ 2745 #else 2746 /* 2747 * Set up the DP83815 multicast address filter by passing all multicast 2748 * addresses through a CRC generator, and then using the high-order 2749 * 9 bits as an index into the 512 bit multicast hash table. The 2750 * high-order 5 bits select the slot, while the low-order 4 bits 2751 * select the bit within the slot. Note that only the low 16-bits 2752 * of each filter word are used, and there are 32 filter words. 2753 */ 2754 #endif /* DP83820 */ 2755 2756 memset(mchash, 0, sizeof(mchash)); 2757 2758 ifp->if_flags &= ~IFF_ALLMULTI; 2759 ETHER_FIRST_MULTI(step, ec, enm); 2760 if (enm == NULL) 2761 goto setit; 2762 while (enm != NULL) { 2763 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2764 /* 2765 * We must listen to a range of multicast addresses. 2766 * For now, just accept all multicasts, rather than 2767 * trying to set only those filter bits needed to match 2768 * the range. (At this time, the only use of address 2769 * ranges is for IP multicast routing, for which the 2770 * range is big enough to require all bits set.) 2771 */ 2772 goto allmulti; 2773 } 2774 2775 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2776 2777 #ifdef DP83820 2778 /* Just want the 11 most significant bits. */ 2779 hash = crc >> 21; 2780 #else 2781 /* Just want the 9 most significant bits. */ 2782 hash = crc >> 23; 2783 #endif /* DP83820 */ 2784 2785 slot = hash >> 4; 2786 bit = hash & 0xf; 2787 2788 /* Set the corresponding bit in the hash table. */ 2789 mchash[slot] |= 1 << bit; 2790 2791 ETHER_NEXT_MULTI(step, enm); 2792 } 2793 sc->sc_rfcr |= RFCR_MHEN; 2794 goto setit; 2795 2796 allmulti: 2797 ifp->if_flags |= IFF_ALLMULTI; 2798 sc->sc_rfcr |= RFCR_AAM; 2799 2800 setit: 2801 #define FILTER_EMIT(addr, data) \ 2802 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2803 delay(1); \ 2804 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2805 delay(1) 2806 2807 /* 2808 * Disable receive filter, and program the node address. 2809 */ 2810 cp = LLADDR(ifp->if_sadl); 2811 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 2812 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 2813 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 2814 2815 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2816 /* 2817 * Program the multicast hash table. 2818 */ 2819 for (i = 0; i < MCHASH_NWORDS; i++) { 2820 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 2821 mchash[i]); 2822 } 2823 } 2824 #undef FILTER_EMIT 2825 #undef MCHASH_NWORDS 2826 2827 /* 2828 * Re-enable the receiver filter. 2829 */ 2830 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2831 } 2832 2833 #if defined(DP83820) 2834 /* 2835 * sip_dp83820_mii_readreg: [mii interface function] 2836 * 2837 * Read a PHY register on the MII of the DP83820. 2838 */ 2839 int 2840 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 2841 { 2842 2843 return (mii_bitbang_readreg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2844 phy, reg)); 2845 } 2846 2847 /* 2848 * sip_dp83820_mii_writereg: [mii interface function] 2849 * 2850 * Write a PHY register on the MII of the DP83820. 2851 */ 2852 void 2853 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 2854 { 2855 2856 mii_bitbang_writereg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2857 phy, reg, val); 2858 } 2859 2860 /* 2861 * sip_dp83815_mii_statchg: [mii interface function] 2862 * 2863 * Callback from MII layer when media changes. 2864 */ 2865 void 2866 SIP_DECL(dp83820_mii_statchg)(struct device *self) 2867 { 2868 struct sip_softc *sc = (struct sip_softc *) self; 2869 u_int32_t cfg; 2870 2871 /* 2872 * Update TXCFG for full-duplex operation. 2873 */ 2874 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2875 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2876 else 2877 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2878 2879 /* 2880 * Update RXCFG for full-duplex or loopback. 2881 */ 2882 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2883 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2884 sc->sc_rxcfg |= RXCFG_ATX; 2885 else 2886 sc->sc_rxcfg &= ~RXCFG_ATX; 2887 2888 /* 2889 * Update CFG for MII/GMII. 2890 */ 2891 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2892 cfg = sc->sc_cfg | CFG_MODE_1000; 2893 else 2894 cfg = sc->sc_cfg; 2895 2896 /* 2897 * XXX 802.3x flow control. 2898 */ 2899 2900 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 2901 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2902 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2903 } 2904 2905 /* 2906 * sip_dp83820_mii_bitbang_read: [mii bit-bang interface function] 2907 * 2908 * Read the MII serial port for the MII bit-bang module. 2909 */ 2910 u_int32_t 2911 SIP_DECL(dp83820_mii_bitbang_read)(struct device *self) 2912 { 2913 struct sip_softc *sc = (void *) self; 2914 2915 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 2916 } 2917 2918 /* 2919 * sip_dp83820_mii_bitbang_write: [mii big-bang interface function] 2920 * 2921 * Write the MII serial port for the MII bit-bang module. 2922 */ 2923 void 2924 SIP_DECL(dp83820_mii_bitbang_write)(struct device *self, u_int32_t val) 2925 { 2926 struct sip_softc *sc = (void *) self; 2927 2928 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 2929 } 2930 #else /* ! DP83820 */ 2931 /* 2932 * sip_sis900_mii_readreg: [mii interface function] 2933 * 2934 * Read a PHY register on the MII. 2935 */ 2936 int 2937 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 2938 { 2939 struct sip_softc *sc = (struct sip_softc *) self; 2940 u_int32_t enphy; 2941 2942 /* 2943 * The SiS 900 has only an internal PHY on the MII. Only allow 2944 * MII address 0. 2945 */ 2946 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 2947 sc->sc_rev < SIS_REV_635 && phy != 0) 2948 return (0); 2949 2950 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2951 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 2952 ENPHY_RWCMD | ENPHY_ACCESS); 2953 do { 2954 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2955 } while (enphy & ENPHY_ACCESS); 2956 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 2957 } 2958 2959 /* 2960 * sip_sis900_mii_writereg: [mii interface function] 2961 * 2962 * Write a PHY register on the MII. 2963 */ 2964 void 2965 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 2966 { 2967 struct sip_softc *sc = (struct sip_softc *) self; 2968 u_int32_t enphy; 2969 2970 /* 2971 * The SiS 900 has only an internal PHY on the MII. Only allow 2972 * MII address 0. 2973 */ 2974 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 2975 sc->sc_rev < SIS_REV_635 && phy != 0) 2976 return; 2977 2978 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 2979 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 2980 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 2981 do { 2982 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 2983 } while (enphy & ENPHY_ACCESS); 2984 } 2985 2986 /* 2987 * sip_sis900_mii_statchg: [mii interface function] 2988 * 2989 * Callback from MII layer when media changes. 2990 */ 2991 void 2992 SIP_DECL(sis900_mii_statchg)(struct device *self) 2993 { 2994 struct sip_softc *sc = (struct sip_softc *) self; 2995 u_int32_t flowctl; 2996 2997 /* 2998 * Update TXCFG for full-duplex operation. 2999 */ 3000 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3001 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3002 else 3003 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3004 3005 /* 3006 * Update RXCFG for full-duplex or loopback. 3007 */ 3008 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3009 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3010 sc->sc_rxcfg |= RXCFG_ATX; 3011 else 3012 sc->sc_rxcfg &= ~RXCFG_ATX; 3013 3014 /* 3015 * Update IMR for use of 802.3x flow control. 3016 */ 3017 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 3018 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3019 flowctl = FLOWCTL_FLOWEN; 3020 } else { 3021 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3022 flowctl = 0; 3023 } 3024 3025 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3026 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3027 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3028 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3029 } 3030 3031 /* 3032 * sip_dp83815_mii_readreg: [mii interface function] 3033 * 3034 * Read a PHY register on the MII. 3035 */ 3036 int 3037 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 3038 { 3039 struct sip_softc *sc = (struct sip_softc *) self; 3040 u_int32_t val; 3041 3042 /* 3043 * The DP83815 only has an internal PHY. Only allow 3044 * MII address 0. 3045 */ 3046 if (phy != 0) 3047 return (0); 3048 3049 /* 3050 * Apparently, after a reset, the DP83815 can take a while 3051 * to respond. During this recovery period, the BMSR returns 3052 * a value of 0. Catch this -- it's not supposed to happen 3053 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3054 * PHY to come back to life. 3055 * 3056 * This works out because the BMSR is the first register 3057 * read during the PHY probe process. 3058 */ 3059 do { 3060 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3061 } while (reg == MII_BMSR && val == 0); 3062 3063 return (val & 0xffff); 3064 } 3065 3066 /* 3067 * sip_dp83815_mii_writereg: [mii interface function] 3068 * 3069 * Write a PHY register to the MII. 3070 */ 3071 void 3072 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3073 { 3074 struct sip_softc *sc = (struct sip_softc *) self; 3075 3076 /* 3077 * The DP83815 only has an internal PHY. Only allow 3078 * MII address 0. 3079 */ 3080 if (phy != 0) 3081 return; 3082 3083 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3084 } 3085 3086 /* 3087 * sip_dp83815_mii_statchg: [mii interface function] 3088 * 3089 * Callback from MII layer when media changes. 3090 */ 3091 void 3092 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3093 { 3094 struct sip_softc *sc = (struct sip_softc *) self; 3095 3096 /* 3097 * Update TXCFG for full-duplex operation. 3098 */ 3099 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3100 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3101 else 3102 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3103 3104 /* 3105 * Update RXCFG for full-duplex or loopback. 3106 */ 3107 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3108 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3109 sc->sc_rxcfg |= RXCFG_ATX; 3110 else 3111 sc->sc_rxcfg &= ~RXCFG_ATX; 3112 3113 /* 3114 * XXX 802.3x flow control. 3115 */ 3116 3117 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3118 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3119 } 3120 #endif /* DP83820 */ 3121 3122 #if defined(DP83820) 3123 void 3124 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3125 const struct pci_attach_args *pa, u_int8_t *enaddr) 3126 { 3127 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3128 u_int8_t cksum, *e, match; 3129 int i; 3130 3131 /* 3132 * EEPROM data format for the DP83820 can be found in 3133 * the DP83820 manual, section 4.2.4. 3134 */ 3135 3136 SIP_DECL(read_eeprom)(sc, 0, 3137 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3138 3139 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3140 match = ~(match - 1); 3141 3142 cksum = 0x55; 3143 e = (u_int8_t *) eeprom_data; 3144 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3145 cksum += *e++; 3146 3147 if (cksum != match) 3148 printf("%s: Checksum (%x) mismatch (%x)", 3149 sc->sc_dev.dv_xname, cksum, match); 3150 3151 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3152 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3153 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3154 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3155 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3156 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3157 3158 /* Get the GPIOR bits. */ 3159 sc->sc_gpior = eeprom_data[0x04]; 3160 } 3161 #else /* ! DP83820 */ 3162 void 3163 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3164 const struct pci_attach_args *pa, u_int8_t *enaddr) 3165 { 3166 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3167 3168 switch (sc->sc_rev) { 3169 case SIS_REV_630S: 3170 case SIS_REV_630E: 3171 case SIS_REV_630EA1: 3172 case SIS_REV_630ET: 3173 case SIS_REV_635: 3174 /* 3175 * The MAC address for the on-board Ethernet of 3176 * the SiS 630 chipset is in the NVRAM. Kick 3177 * the chip into re-loading it from NVRAM, and 3178 * read the MAC address out of the filter registers. 3179 */ 3180 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3181 3182 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3183 RFCR_RFADDR_NODE0); 3184 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3185 0xffff; 3186 3187 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3188 RFCR_RFADDR_NODE2); 3189 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3190 0xffff; 3191 3192 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3193 RFCR_RFADDR_NODE4); 3194 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3195 0xffff; 3196 break; 3197 3198 default: 3199 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3200 sizeof(myea) / sizeof(myea[0]), myea); 3201 } 3202 3203 enaddr[0] = myea[0] & 0xff; 3204 enaddr[1] = myea[0] >> 8; 3205 enaddr[2] = myea[1] & 0xff; 3206 enaddr[3] = myea[1] >> 8; 3207 enaddr[4] = myea[2] & 0xff; 3208 enaddr[5] = myea[2] >> 8; 3209 } 3210 3211 /* Table and macro to bit-reverse an octet. */ 3212 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3213 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3214 3215 void 3216 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3217 const struct pci_attach_args *pa, u_int8_t *enaddr) 3218 { 3219 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3220 u_int8_t cksum, *e, match; 3221 int i; 3222 3223 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3224 sizeof(eeprom_data[0]), eeprom_data); 3225 3226 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3227 match = ~(match - 1); 3228 3229 cksum = 0x55; 3230 e = (u_int8_t *) eeprom_data; 3231 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3232 cksum += *e++; 3233 } 3234 if (cksum != match) { 3235 printf("%s: Checksum (%x) mismatch (%x)", 3236 sc->sc_dev.dv_xname, cksum, match); 3237 } 3238 3239 /* 3240 * Unrolled because it makes slightly more sense this way. 3241 * The DP83815 stores the MAC address in bit 0 of word 6 3242 * through bit 15 of word 8. 3243 */ 3244 ea = &eeprom_data[6]; 3245 enaddr[0] = ((*ea & 0x1) << 7); 3246 ea++; 3247 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3248 enaddr[1] = ((*ea & 0x1FE) >> 1); 3249 enaddr[2] = ((*ea & 0x1) << 7); 3250 ea++; 3251 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3252 enaddr[3] = ((*ea & 0x1FE) >> 1); 3253 enaddr[4] = ((*ea & 0x1) << 7); 3254 ea++; 3255 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3256 enaddr[5] = ((*ea & 0x1FE) >> 1); 3257 3258 /* 3259 * In case that's not weird enough, we also need to reverse 3260 * the bits in each byte. This all actually makes more sense 3261 * if you think about the EEPROM storage as an array of bits 3262 * being shifted into bytes, but that's not how we're looking 3263 * at it here... 3264 */ 3265 for (i = 0; i < 6 ;i++) 3266 enaddr[i] = bbr(enaddr[i]); 3267 } 3268 #endif /* DP83820 */ 3269 3270 /* 3271 * sip_mediastatus: [ifmedia interface function] 3272 * 3273 * Get the current interface media status. 3274 */ 3275 void 3276 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3277 { 3278 struct sip_softc *sc = ifp->if_softc; 3279 3280 mii_pollstat(&sc->sc_mii); 3281 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3282 ifmr->ifm_active = sc->sc_mii.mii_media_active; 3283 } 3284 3285 /* 3286 * sip_mediachange: [ifmedia interface function] 3287 * 3288 * Set hardware to newly-selected media. 3289 */ 3290 int 3291 SIP_DECL(mediachange)(struct ifnet *ifp) 3292 { 3293 struct sip_softc *sc = ifp->if_softc; 3294 3295 if (ifp->if_flags & IFF_UP) 3296 mii_mediachg(&sc->sc_mii); 3297 return (0); 3298 } 3299
Indexes created Tue Sep 30 11:09:46 GMT 2025