if_sip.c revision 1.65
1 /* $NetBSD: if_sip.c,v 1.65 2002/08/20 00:35:46 itojun Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.65 2002/08/20 00:35:46 itojun Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <machine/bus.h> 116 #include <machine/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #ifdef DP83820 122 #include <dev/mii/mii_bitbang.h> 123 #endif /* DP83820 */ 124 125 #include <dev/pci/pcireg.h> 126 #include <dev/pci/pcivar.h> 127 #include <dev/pci/pcidevs.h> 128 129 #include <dev/pci/if_sipreg.h> 130 131 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 132 #define SIP_DECL(x) __CONCAT(gsip_,x) 133 #else /* SiS900 and DP83815 */ 134 #define SIP_DECL(x) __CONCAT(sip_,x) 135 #endif 136 137 #define SIP_STR(x) __STRING(SIP_DECL(x)) 138 139 /* 140 * Transmit descriptor list size. This is arbitrary, but allocate 141 * enough descriptors for 128 pending transmissions, and 8 segments 142 * per packet. This MUST work out to a power of 2. 143 */ 144 #define SIP_NTXSEGS 16 145 #define SIP_NTXSEGS_ALLOC 8 146 147 #define SIP_TXQUEUELEN 256 148 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 149 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 150 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 151 152 #if defined(DP83020) 153 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 154 #else 155 #define TX_DMAMAP_SIZE MCLBYTES 156 #endif 157 158 /* 159 * Receive descriptor list size. We have one Rx buffer per incoming 160 * packet, so this logic is a little simpler. 161 * 162 * Actually, on the DP83820, we allow the packet to consume more than 163 * one buffer, in order to support jumbo Ethernet frames. In that 164 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 165 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 166 * so we'd better be quick about handling receive interrupts. 167 */ 168 #if defined(DP83820) 169 #define SIP_NRXDESC 256 170 #else 171 #define SIP_NRXDESC 128 172 #endif /* DP83820 */ 173 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 174 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 175 176 /* 177 * Control structures are DMA'd to the SiS900 chip. We allocate them in 178 * a single clump that maps to a single DMA segment to make several things 179 * easier. 180 */ 181 struct sip_control_data { 182 /* 183 * The transmit descriptors. 184 */ 185 struct sip_desc scd_txdescs[SIP_NTXDESC]; 186 187 /* 188 * The receive descriptors. 189 */ 190 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 191 }; 192 193 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 194 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 195 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 196 197 /* 198 * Software state for transmit jobs. 199 */ 200 struct sip_txsoft { 201 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 202 bus_dmamap_t txs_dmamap; /* our DMA map */ 203 int txs_firstdesc; /* first descriptor in packet */ 204 int txs_lastdesc; /* last descriptor in packet */ 205 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 206 }; 207 208 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 209 210 /* 211 * Software state for receive jobs. 212 */ 213 struct sip_rxsoft { 214 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 215 bus_dmamap_t rxs_dmamap; /* our DMA map */ 216 }; 217 218 /* 219 * Software state per device. 220 */ 221 struct sip_softc { 222 struct device sc_dev; /* generic device information */ 223 bus_space_tag_t sc_st; /* bus space tag */ 224 bus_space_handle_t sc_sh; /* bus space handle */ 225 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 226 struct ethercom sc_ethercom; /* ethernet common data */ 227 void *sc_sdhook; /* shutdown hook */ 228 229 const struct sip_product *sc_model; /* which model are we? */ 230 int sc_rev; /* chip revision */ 231 232 void *sc_ih; /* interrupt cookie */ 233 234 struct mii_data sc_mii; /* MII/media information */ 235 236 struct callout sc_tick_ch; /* tick callout */ 237 238 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 239 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 240 241 /* 242 * Software state for transmit and receive descriptors. 243 */ 244 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 245 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 246 247 /* 248 * Control data structures. 249 */ 250 struct sip_control_data *sc_control_data; 251 #define sc_txdescs sc_control_data->scd_txdescs 252 #define sc_rxdescs sc_control_data->scd_rxdescs 253 254 #ifdef SIP_EVENT_COUNTERS 255 /* 256 * Event counters. 257 */ 258 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 259 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 260 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 261 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 262 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 263 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 264 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 265 #ifdef DP83820 266 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 267 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 268 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 269 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 270 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 271 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 272 #endif /* DP83820 */ 273 #endif /* SIP_EVENT_COUNTERS */ 274 275 u_int32_t sc_txcfg; /* prototype TXCFG register */ 276 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 277 u_int32_t sc_imr; /* prototype IMR register */ 278 u_int32_t sc_rfcr; /* prototype RFCR register */ 279 280 u_int32_t sc_cfg; /* prototype CFG register */ 281 282 #ifdef DP83820 283 u_int32_t sc_gpior; /* prototype GPIOR register */ 284 #endif /* DP83820 */ 285 286 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 287 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 288 289 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 290 291 int sc_flags; /* misc. flags; see below */ 292 293 int sc_txfree; /* number of free Tx descriptors */ 294 int sc_txnext; /* next ready Tx descriptor */ 295 int sc_txwin; /* Tx descriptors since last intr */ 296 297 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 298 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 299 300 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 301 #if defined(DP83820) 302 int sc_rxdiscard; 303 int sc_rxlen; 304 struct mbuf *sc_rxhead; 305 struct mbuf *sc_rxtail; 306 struct mbuf **sc_rxtailp; 307 #endif /* DP83820 */ 308 309 #if NRND > 0 310 rndsource_element_t rnd_source; /* random source */ 311 #endif 312 }; 313 314 /* sc_flags */ 315 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 316 317 #ifdef DP83820 318 #define SIP_RXCHAIN_RESET(sc) \ 319 do { \ 320 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 321 *(sc)->sc_rxtailp = NULL; \ 322 (sc)->sc_rxlen = 0; \ 323 } while (/*CONSTCOND*/0) 324 325 #define SIP_RXCHAIN_LINK(sc, m) \ 326 do { \ 327 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 328 (sc)->sc_rxtailp = &(m)->m_next; \ 329 } while (/*CONSTCOND*/0) 330 #endif /* DP83820 */ 331 332 #ifdef SIP_EVENT_COUNTERS 333 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 334 #else 335 #define SIP_EVCNT_INCR(ev) /* nothing */ 336 #endif 337 338 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 339 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 340 341 #define SIP_CDTXSYNC(sc, x, n, ops) \ 342 do { \ 343 int __x, __n; \ 344 \ 345 __x = (x); \ 346 __n = (n); \ 347 \ 348 /* If it will wrap around, sync to the end of the ring. */ \ 349 if ((__x + __n) > SIP_NTXDESC) { \ 350 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 351 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 352 (SIP_NTXDESC - __x), (ops)); \ 353 __n -= (SIP_NTXDESC - __x); \ 354 __x = 0; \ 355 } \ 356 \ 357 /* Now sync whatever is left. */ \ 358 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 359 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 360 } while (0) 361 362 #define SIP_CDRXSYNC(sc, x, ops) \ 363 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 364 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 365 366 #ifdef DP83820 367 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 368 #define SIP_RXBUF_LEN (MCLBYTES - 4) 369 #else 370 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 371 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 372 #endif 373 #define SIP_INIT_RXDESC(sc, x) \ 374 do { \ 375 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 376 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 377 \ 378 __sipd->sipd_link = \ 379 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 380 __sipd->sipd_bufptr = \ 381 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 382 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 383 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 384 SIP_INIT_RXDESC_EXTSTS \ 385 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 386 } while (0) 387 388 #define SIP_CHIP_VERS(sc, v, p, r) \ 389 ((sc)->sc_model->sip_vendor == (v) && \ 390 (sc)->sc_model->sip_product == (p) && \ 391 (sc)->sc_rev == (r)) 392 393 #define SIP_CHIP_MODEL(sc, v, p) \ 394 ((sc)->sc_model->sip_vendor == (v) && \ 395 (sc)->sc_model->sip_product == (p)) 396 397 #if !defined(DP83820) 398 #define SIP_SIS900_REV(sc, rev) \ 399 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 400 #endif 401 402 #define SIP_TIMEOUT 1000 403 404 void SIP_DECL(start)(struct ifnet *); 405 void SIP_DECL(watchdog)(struct ifnet *); 406 int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 407 int SIP_DECL(init)(struct ifnet *); 408 void SIP_DECL(stop)(struct ifnet *, int); 409 410 void SIP_DECL(shutdown)(void *); 411 412 void SIP_DECL(reset)(struct sip_softc *); 413 void SIP_DECL(rxdrain)(struct sip_softc *); 414 int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 415 void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, u_int16_t *); 416 void SIP_DECL(tick)(void *); 417 418 #if !defined(DP83820) 419 void SIP_DECL(sis900_set_filter)(struct sip_softc *); 420 #endif /* ! DP83820 */ 421 void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 422 423 #if defined(DP83820) 424 void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 425 const struct pci_attach_args *, u_int8_t *); 426 #else 427 void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 428 const struct pci_attach_args *, u_int8_t *); 429 void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 430 const struct pci_attach_args *, u_int8_t *); 431 #endif /* DP83820 */ 432 433 int SIP_DECL(intr)(void *); 434 void SIP_DECL(txintr)(struct sip_softc *); 435 void SIP_DECL(rxintr)(struct sip_softc *); 436 437 #if defined(DP83820) 438 int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 439 void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 440 void SIP_DECL(dp83820_mii_statchg)(struct device *); 441 #else 442 int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 443 void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 444 void SIP_DECL(sis900_mii_statchg)(struct device *); 445 446 int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 447 void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 448 void SIP_DECL(dp83815_mii_statchg)(struct device *); 449 #endif /* DP83820 */ 450 451 int SIP_DECL(mediachange)(struct ifnet *); 452 void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 453 454 int SIP_DECL(match)(struct device *, struct cfdata *, void *); 455 void SIP_DECL(attach)(struct device *, struct device *, void *); 456 457 int SIP_DECL(copy_small) = 0; 458 459 struct cfattach SIP_DECL(ca) = { 460 sizeof(struct sip_softc), SIP_DECL(match), SIP_DECL(attach), 461 }; 462 463 /* 464 * Descriptions of the variants of the SiS900. 465 */ 466 struct sip_variant { 467 int (*sipv_mii_readreg)(struct device *, int, int); 468 void (*sipv_mii_writereg)(struct device *, int, int, int); 469 void (*sipv_mii_statchg)(struct device *); 470 void (*sipv_set_filter)(struct sip_softc *); 471 void (*sipv_read_macaddr)(struct sip_softc *, 472 const struct pci_attach_args *, u_int8_t *); 473 }; 474 475 #if defined(DP83820) 476 u_int32_t SIP_DECL(dp83820_mii_bitbang_read)(struct device *); 477 void SIP_DECL(dp83820_mii_bitbang_write)(struct device *, u_int32_t); 478 479 const struct mii_bitbang_ops SIP_DECL(dp83820_mii_bitbang_ops) = { 480 SIP_DECL(dp83820_mii_bitbang_read), 481 SIP_DECL(dp83820_mii_bitbang_write), 482 { 483 EROMAR_MDIO, /* MII_BIT_MDO */ 484 EROMAR_MDIO, /* MII_BIT_MDI */ 485 EROMAR_MDC, /* MII_BIT_MDC */ 486 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 487 0, /* MII_BIT_DIR_PHY_HOST */ 488 } 489 }; 490 #endif /* DP83820 */ 491 492 #if defined(DP83820) 493 const struct sip_variant SIP_DECL(variant_dp83820) = { 494 SIP_DECL(dp83820_mii_readreg), 495 SIP_DECL(dp83820_mii_writereg), 496 SIP_DECL(dp83820_mii_statchg), 497 SIP_DECL(dp83815_set_filter), 498 SIP_DECL(dp83820_read_macaddr), 499 }; 500 #else 501 const struct sip_variant SIP_DECL(variant_sis900) = { 502 SIP_DECL(sis900_mii_readreg), 503 SIP_DECL(sis900_mii_writereg), 504 SIP_DECL(sis900_mii_statchg), 505 SIP_DECL(sis900_set_filter), 506 SIP_DECL(sis900_read_macaddr), 507 }; 508 509 const struct sip_variant SIP_DECL(variant_dp83815) = { 510 SIP_DECL(dp83815_mii_readreg), 511 SIP_DECL(dp83815_mii_writereg), 512 SIP_DECL(dp83815_mii_statchg), 513 SIP_DECL(dp83815_set_filter), 514 SIP_DECL(dp83815_read_macaddr), 515 }; 516 #endif /* DP83820 */ 517 518 /* 519 * Devices supported by this driver. 520 */ 521 const struct sip_product { 522 pci_vendor_id_t sip_vendor; 523 pci_product_id_t sip_product; 524 const char *sip_name; 525 const struct sip_variant *sip_variant; 526 } SIP_DECL(products)[] = { 527 #if defined(DP83820) 528 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 529 "NatSemi DP83820 Gigabit Ethernet", 530 &SIP_DECL(variant_dp83820) }, 531 #else 532 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 533 "SiS 900 10/100 Ethernet", 534 &SIP_DECL(variant_sis900) }, 535 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 536 "SiS 7016 10/100 Ethernet", 537 &SIP_DECL(variant_sis900) }, 538 539 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 540 "NatSemi DP83815 10/100 Ethernet", 541 &SIP_DECL(variant_dp83815) }, 542 #endif /* DP83820 */ 543 544 { 0, 0, 545 NULL, 546 NULL }, 547 }; 548 549 static const struct sip_product * 550 SIP_DECL(lookup)(const struct pci_attach_args *pa) 551 { 552 const struct sip_product *sip; 553 554 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 555 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 556 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 557 return (sip); 558 } 559 return (NULL); 560 } 561 562 #ifdef DP83820 563 /* 564 * I really hate stupid hardware vendors. There's a bit in the EEPROM 565 * which indicates if the card can do 64-bit data transfers. Unfortunately, 566 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 567 * which means we try to use 64-bit data transfers on those cards if we 568 * happen to be plugged into a 32-bit slot. 569 * 570 * What we do is use this table of cards known to be 64-bit cards. If 571 * you have a 64-bit card who's subsystem ID is not listed in this table, 572 * send the output of "pcictl dump ..." of the device to me so that your 573 * card will use the 64-bit data path when plugged into a 64-bit slot. 574 * 575 * -- Jason R. Thorpe <thorpej (at) netbsd.org> 576 * June 30, 2002 577 */ 578 static int 579 SIP_DECL(check_64bit)(const struct pci_attach_args *pa) 580 { 581 static const struct { 582 pci_vendor_id_t c64_vendor; 583 pci_product_id_t c64_product; 584 } card64[] = { 585 /* Asante GigaNIX */ 586 { 0x128a, 0x0002 }, 587 588 /* Accton EN1407-T, Planex GN-1000TE */ 589 { 0x1113, 0x1407 }, 590 591 { 0, 0} 592 }; 593 pcireg_t subsys; 594 int i; 595 596 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 597 598 for (i = 0; card64[i].c64_vendor != 0; i++) { 599 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 600 PCI_PRODUCT(subsys) == card64[i].c64_product) 601 return (1); 602 } 603 604 return (0); 605 } 606 #endif /* DP83820 */ 607 608 int 609 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 610 { 611 struct pci_attach_args *pa = aux; 612 613 if (SIP_DECL(lookup)(pa) != NULL) 614 return (1); 615 616 return (0); 617 } 618 619 void 620 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 621 { 622 struct sip_softc *sc = (struct sip_softc *) self; 623 struct pci_attach_args *pa = aux; 624 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 625 pci_chipset_tag_t pc = pa->pa_pc; 626 pci_intr_handle_t ih; 627 const char *intrstr = NULL; 628 bus_space_tag_t iot, memt; 629 bus_space_handle_t ioh, memh; 630 bus_dma_segment_t seg; 631 int ioh_valid, memh_valid; 632 int i, rseg, error; 633 const struct sip_product *sip; 634 pcireg_t pmode; 635 u_int8_t enaddr[ETHER_ADDR_LEN]; 636 int pmreg; 637 #ifdef DP83820 638 pcireg_t memtype; 639 u_int32_t reg; 640 #endif /* DP83820 */ 641 642 callout_init(&sc->sc_tick_ch); 643 644 sip = SIP_DECL(lookup)(pa); 645 if (sip == NULL) { 646 printf("\n"); 647 panic(SIP_STR(attach) ": impossible"); 648 } 649 sc->sc_rev = PCI_REVISION(pa->pa_class); 650 651 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 652 653 sc->sc_model = sip; 654 655 /* 656 * XXX Work-around broken PXE firmware on some boards. 657 * 658 * The DP83815 shares an address decoder with the MEM BAR 659 * and the ROM BAR. Make sure the ROM BAR is disabled, 660 * so that memory mapped access works. 661 */ 662 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 663 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 664 ~PCI_MAPREG_ROM_ENABLE); 665 666 /* 667 * Map the device. 668 */ 669 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 670 PCI_MAPREG_TYPE_IO, 0, 671 &iot, &ioh, NULL, NULL) == 0); 672 #ifdef DP83820 673 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 674 switch (memtype) { 675 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 676 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 677 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 678 memtype, 0, &memt, &memh, NULL, NULL) == 0); 679 break; 680 default: 681 memh_valid = 0; 682 } 683 #else 684 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 685 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 686 &memt, &memh, NULL, NULL) == 0); 687 #endif /* DP83820 */ 688 689 if (memh_valid) { 690 sc->sc_st = memt; 691 sc->sc_sh = memh; 692 } else if (ioh_valid) { 693 sc->sc_st = iot; 694 sc->sc_sh = ioh; 695 } else { 696 printf("%s: unable to map device registers\n", 697 sc->sc_dev.dv_xname); 698 return; 699 } 700 701 sc->sc_dmat = pa->pa_dmat; 702 703 /* 704 * Make sure bus mastering is enabled. Also make sure 705 * Write/Invalidate is enabled if we're allowed to use it. 706 */ 707 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 708 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 709 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 710 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 711 pmreg | PCI_COMMAND_MASTER_ENABLE); 712 713 /* Get it out of power save mode if needed. */ 714 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 715 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 716 if (pmode == 3) { 717 /* 718 * The card has lost all configuration data in 719 * this state, so punt. 720 */ 721 printf("%s: unable to wake up from power state D3\n", 722 sc->sc_dev.dv_xname); 723 return; 724 } 725 if (pmode != 0) { 726 printf("%s: waking up from power state D%d\n", 727 sc->sc_dev.dv_xname, pmode); 728 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 729 } 730 } 731 732 /* 733 * Map and establish our interrupt. 734 */ 735 if (pci_intr_map(pa, &ih)) { 736 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 737 return; 738 } 739 intrstr = pci_intr_string(pc, ih); 740 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 741 if (sc->sc_ih == NULL) { 742 printf("%s: unable to establish interrupt", 743 sc->sc_dev.dv_xname); 744 if (intrstr != NULL) 745 printf(" at %s", intrstr); 746 printf("\n"); 747 return; 748 } 749 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 750 751 SIMPLEQ_INIT(&sc->sc_txfreeq); 752 SIMPLEQ_INIT(&sc->sc_txdirtyq); 753 754 /* 755 * Allocate the control data structures, and create and load the 756 * DMA map for it. 757 */ 758 if ((error = bus_dmamem_alloc(sc->sc_dmat, 759 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 760 0)) != 0) { 761 printf("%s: unable to allocate control data, error = %d\n", 762 sc->sc_dev.dv_xname, error); 763 goto fail_0; 764 } 765 766 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 767 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 768 BUS_DMA_COHERENT)) != 0) { 769 printf("%s: unable to map control data, error = %d\n", 770 sc->sc_dev.dv_xname, error); 771 goto fail_1; 772 } 773 774 if ((error = bus_dmamap_create(sc->sc_dmat, 775 sizeof(struct sip_control_data), 1, 776 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 777 printf("%s: unable to create control data DMA map, " 778 "error = %d\n", sc->sc_dev.dv_xname, error); 779 goto fail_2; 780 } 781 782 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 783 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 784 0)) != 0) { 785 printf("%s: unable to load control data DMA map, error = %d\n", 786 sc->sc_dev.dv_xname, error); 787 goto fail_3; 788 } 789 790 /* 791 * Create the transmit buffer DMA maps. 792 */ 793 for (i = 0; i < SIP_TXQUEUELEN; i++) { 794 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 795 SIP_NTXSEGS, MCLBYTES, 0, 0, 796 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 797 printf("%s: unable to create tx DMA map %d, " 798 "error = %d\n", sc->sc_dev.dv_xname, i, error); 799 goto fail_4; 800 } 801 } 802 803 /* 804 * Create the receive buffer DMA maps. 805 */ 806 for (i = 0; i < SIP_NRXDESC; i++) { 807 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 808 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 809 printf("%s: unable to create rx DMA map %d, " 810 "error = %d\n", sc->sc_dev.dv_xname, i, error); 811 goto fail_5; 812 } 813 sc->sc_rxsoft[i].rxs_mbuf = NULL; 814 } 815 816 /* 817 * Reset the chip to a known state. 818 */ 819 SIP_DECL(reset)(sc); 820 821 /* 822 * Read the Ethernet address from the EEPROM. This might 823 * also fetch other stuff from the EEPROM and stash it 824 * in the softc. 825 */ 826 sc->sc_cfg = 0; 827 #if !defined(DP83820) 828 if (SIP_SIS900_REV(sc,SIS_REV_635) || 829 SIP_SIS900_REV(sc,SIS_REV_900B)) 830 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 831 #endif 832 833 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 834 835 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 836 ether_sprintf(enaddr)); 837 838 /* 839 * Initialize the configuration register: aggressive PCI 840 * bus request algorithm, default backoff, default OW timer, 841 * default parity error detection. 842 * 843 * NOTE: "Big endian mode" is useless on the SiS900 and 844 * friends -- it affects packet data, not descriptors. 845 */ 846 #ifdef DP83820 847 /* 848 * Cause the chip to load configuration data from the EEPROM. 849 */ 850 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 851 for (i = 0; i < 10000; i++) { 852 delay(10); 853 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 854 PTSCR_EELOAD_EN) == 0) 855 break; 856 } 857 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 858 PTSCR_EELOAD_EN) { 859 printf("%s: timeout loading configuration from EEPROM\n", 860 sc->sc_dev.dv_xname); 861 return; 862 } 863 864 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 865 if (reg & CFG_PCI64_DET) { 866 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 867 /* 868 * Check to see if this card is 64-bit. If so, enable 64-bit 869 * data transfers. 870 * 871 * We can't use the DATA64_EN bit in the EEPROM, because 872 * vendors of 32-bit cards fail to clear that bit in many 873 * cases (yet the card still detects that it's in a 64-bit 874 * slot; go figure). 875 */ 876 if (SIP_DECL(check_64bit)(pa)) { 877 sc->sc_cfg |= CFG_DATA64_EN; 878 printf(", using 64-bit data transfers"); 879 } 880 printf("\n"); 881 } 882 883 /* 884 * XXX Need some PCI flags indicating support for 885 * XXX 64-bit addressing. 886 */ 887 #if 0 888 if (reg & CFG_M64ADDR) 889 sc->sc_cfg |= CFG_M64ADDR; 890 if (reg & CFG_T64ADDR) 891 sc->sc_cfg |= CFG_T64ADDR; 892 #endif 893 894 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 895 const char *sep = ""; 896 printf("%s: using ", sc->sc_dev.dv_xname); 897 if (reg & CFG_EXT_125) { 898 sc->sc_cfg |= CFG_EXT_125; 899 printf("%s125MHz clock", sep); 900 sep = ", "; 901 } 902 if (reg & CFG_TBI_EN) { 903 sc->sc_cfg |= CFG_TBI_EN; 904 printf("%sten-bit interface", sep); 905 sep = ", "; 906 } 907 printf("\n"); 908 } 909 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 910 (reg & CFG_MRM_DIS) != 0) 911 sc->sc_cfg |= CFG_MRM_DIS; 912 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 913 (reg & CFG_MWI_DIS) != 0) 914 sc->sc_cfg |= CFG_MWI_DIS; 915 916 /* 917 * Use the extended descriptor format on the DP83820. This 918 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 919 * checksumming. 920 */ 921 sc->sc_cfg |= CFG_EXTSTS_EN; 922 #endif /* DP83820 */ 923 924 /* 925 * Initialize our media structures and probe the MII. 926 */ 927 sc->sc_mii.mii_ifp = ifp; 928 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 929 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 930 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 931 ifmedia_init(&sc->sc_mii.mii_media, 0, SIP_DECL(mediachange), 932 SIP_DECL(mediastatus)); 933 934 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 935 MII_OFFSET_ANY, 0); 936 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 937 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 938 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 939 } else 940 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 941 942 ifp = &sc->sc_ethercom.ec_if; 943 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 944 ifp->if_softc = sc; 945 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 946 ifp->if_ioctl = SIP_DECL(ioctl); 947 ifp->if_start = SIP_DECL(start); 948 ifp->if_watchdog = SIP_DECL(watchdog); 949 ifp->if_init = SIP_DECL(init); 950 ifp->if_stop = SIP_DECL(stop); 951 IFQ_SET_READY(&ifp->if_snd); 952 953 /* 954 * We can support 802.1Q VLAN-sized frames. 955 */ 956 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 957 958 #ifdef DP83820 959 /* 960 * And the DP83820 can do VLAN tagging in hardware, and 961 * support the jumbo Ethernet MTU. 962 */ 963 sc->sc_ethercom.ec_capabilities |= 964 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 965 966 /* 967 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 968 * in hardware. 969 */ 970 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 971 IFCAP_CSUM_UDPv4; 972 #endif /* DP83820 */ 973 974 /* 975 * Attach the interface. 976 */ 977 if_attach(ifp); 978 ether_ifattach(ifp, enaddr); 979 #if NRND > 0 980 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 981 RND_TYPE_NET, 0); 982 #endif 983 984 /* 985 * The number of bytes that must be available in 986 * the Tx FIFO before the bus master can DMA more 987 * data into the FIFO. 988 */ 989 sc->sc_tx_fill_thresh = 64 / 32; 990 991 /* 992 * Start at a drain threshold of 512 bytes. We will 993 * increase it if a DMA underrun occurs. 994 * 995 * XXX The minimum value of this variable should be 996 * tuned. We may be able to improve performance 997 * by starting with a lower value. That, however, 998 * may trash the first few outgoing packets if the 999 * PCI bus is saturated. 1000 */ 1001 sc->sc_tx_drain_thresh = 1504 / 32; 1002 1003 /* 1004 * Initialize the Rx FIFO drain threshold. 1005 * 1006 * This is in units of 8 bytes. 1007 * 1008 * We should never set this value lower than 2; 14 bytes are 1009 * required to filter the packet. 1010 */ 1011 sc->sc_rx_drain_thresh = 128 / 8; 1012 1013 #ifdef SIP_EVENT_COUNTERS 1014 /* 1015 * Attach event counters. 1016 */ 1017 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1018 NULL, sc->sc_dev.dv_xname, "txsstall"); 1019 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1020 NULL, sc->sc_dev.dv_xname, "txdstall"); 1021 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1022 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1023 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1024 NULL, sc->sc_dev.dv_xname, "txdintr"); 1025 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1026 NULL, sc->sc_dev.dv_xname, "txiintr"); 1027 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1028 NULL, sc->sc_dev.dv_xname, "rxintr"); 1029 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1030 NULL, sc->sc_dev.dv_xname, "hiberr"); 1031 #ifdef DP83820 1032 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1033 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1034 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1035 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1036 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1037 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1038 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1039 NULL, sc->sc_dev.dv_xname, "txipsum"); 1040 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1041 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1042 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1043 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1044 #endif /* DP83820 */ 1045 #endif /* SIP_EVENT_COUNTERS */ 1046 1047 /* 1048 * Make sure the interface is shutdown during reboot. 1049 */ 1050 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 1051 if (sc->sc_sdhook == NULL) 1052 printf("%s: WARNING: unable to establish shutdown hook\n", 1053 sc->sc_dev.dv_xname); 1054 return; 1055 1056 /* 1057 * Free any resources we've allocated during the failed attach 1058 * attempt. Do this in reverse order and fall through. 1059 */ 1060 fail_5: 1061 for (i = 0; i < SIP_NRXDESC; i++) { 1062 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1063 bus_dmamap_destroy(sc->sc_dmat, 1064 sc->sc_rxsoft[i].rxs_dmamap); 1065 } 1066 fail_4: 1067 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1068 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1069 bus_dmamap_destroy(sc->sc_dmat, 1070 sc->sc_txsoft[i].txs_dmamap); 1071 } 1072 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1073 fail_3: 1074 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1075 fail_2: 1076 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1077 sizeof(struct sip_control_data)); 1078 fail_1: 1079 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1080 fail_0: 1081 return; 1082 } 1083 1084 /* 1085 * sip_shutdown: 1086 * 1087 * Make sure the interface is stopped at reboot time. 1088 */ 1089 void 1090 SIP_DECL(shutdown)(void *arg) 1091 { 1092 struct sip_softc *sc = arg; 1093 1094 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1095 } 1096 1097 /* 1098 * sip_start: [ifnet interface function] 1099 * 1100 * Start packet transmission on the interface. 1101 */ 1102 void 1103 SIP_DECL(start)(struct ifnet *ifp) 1104 { 1105 struct sip_softc *sc = ifp->if_softc; 1106 struct mbuf *m0, *m; 1107 struct sip_txsoft *txs; 1108 bus_dmamap_t dmamap; 1109 int error, nexttx, lasttx, seg; 1110 int ofree = sc->sc_txfree; 1111 #if 0 1112 int firsttx = sc->sc_txnext; 1113 #endif 1114 #ifdef DP83820 1115 u_int32_t extsts; 1116 #endif 1117 1118 /* 1119 * If we've been told to pause, don't transmit any more packets. 1120 */ 1121 if (sc->sc_flags & SIPF_PAUSED) 1122 ifp->if_flags |= IFF_OACTIVE; 1123 1124 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1125 return; 1126 1127 /* 1128 * Loop through the send queue, setting up transmit descriptors 1129 * until we drain the queue, or use up all available transmit 1130 * descriptors. 1131 */ 1132 for (;;) { 1133 /* Get a work queue entry. */ 1134 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1135 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1136 break; 1137 } 1138 1139 /* 1140 * Grab a packet off the queue. 1141 */ 1142 IFQ_POLL(&ifp->if_snd, m0); 1143 if (m0 == NULL) 1144 break; 1145 #ifndef DP83820 1146 m = NULL; 1147 #endif 1148 1149 dmamap = txs->txs_dmamap; 1150 1151 #ifdef DP83820 1152 /* 1153 * Load the DMA map. If this fails, the packet either 1154 * didn't fit in the allotted number of segments, or we 1155 * were short on resources. For the too-many-segments 1156 * case, we simply report an error and drop the packet, 1157 * since we can't sanely copy a jumbo packet to a single 1158 * buffer. 1159 */ 1160 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1161 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1162 if (error) { 1163 if (error == EFBIG) { 1164 printf("%s: Tx packet consumes too many " 1165 "DMA segments, dropping...\n", 1166 sc->sc_dev.dv_xname); 1167 IFQ_DEQUEUE(&ifp->if_snd, m0); 1168 m_freem(m0); 1169 continue; 1170 } 1171 /* 1172 * Short on resources, just stop for now. 1173 */ 1174 break; 1175 } 1176 #else /* DP83820 */ 1177 /* 1178 * Load the DMA map. If this fails, the packet either 1179 * didn't fit in the alloted number of segments, or we 1180 * were short on resources. In this case, we'll copy 1181 * and try again. 1182 */ 1183 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1184 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1185 MGETHDR(m, M_DONTWAIT, MT_DATA); 1186 if (m == NULL) { 1187 printf("%s: unable to allocate Tx mbuf\n", 1188 sc->sc_dev.dv_xname); 1189 break; 1190 } 1191 if (m0->m_pkthdr.len > MHLEN) { 1192 MCLGET(m, M_DONTWAIT); 1193 if ((m->m_flags & M_EXT) == 0) { 1194 printf("%s: unable to allocate Tx " 1195 "cluster\n", sc->sc_dev.dv_xname); 1196 m_freem(m); 1197 break; 1198 } 1199 } 1200 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1201 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1202 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1203 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1204 if (error) { 1205 printf("%s: unable to load Tx buffer, " 1206 "error = %d\n", sc->sc_dev.dv_xname, error); 1207 break; 1208 } 1209 } 1210 #endif /* DP83820 */ 1211 1212 /* 1213 * Ensure we have enough descriptors free to describe 1214 * the packet. Note, we always reserve one descriptor 1215 * at the end of the ring as a termination point, to 1216 * prevent wrap-around. 1217 */ 1218 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1219 /* 1220 * Not enough free descriptors to transmit this 1221 * packet. We haven't committed anything yet, 1222 * so just unload the DMA map, put the packet 1223 * back on the queue, and punt. Notify the upper 1224 * layer that there are not more slots left. 1225 * 1226 * XXX We could allocate an mbuf and copy, but 1227 * XXX is it worth it? 1228 */ 1229 ifp->if_flags |= IFF_OACTIVE; 1230 bus_dmamap_unload(sc->sc_dmat, dmamap); 1231 #ifndef DP83820 1232 if (m != NULL) 1233 m_freem(m); 1234 #endif 1235 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1236 break; 1237 } 1238 1239 IFQ_DEQUEUE(&ifp->if_snd, m0); 1240 #ifndef DP83820 1241 if (m != NULL) { 1242 m_freem(m0); 1243 m0 = m; 1244 } 1245 #endif 1246 1247 /* 1248 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1249 */ 1250 1251 /* Sync the DMA map. */ 1252 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1253 BUS_DMASYNC_PREWRITE); 1254 1255 /* 1256 * Initialize the transmit descriptors. 1257 */ 1258 for (nexttx = sc->sc_txnext, seg = 0; 1259 seg < dmamap->dm_nsegs; 1260 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1261 /* 1262 * If this is the first descriptor we're 1263 * enqueueing, don't set the OWN bit just 1264 * yet. That could cause a race condition. 1265 * We'll do it below. 1266 */ 1267 sc->sc_txdescs[nexttx].sipd_bufptr = 1268 htole32(dmamap->dm_segs[seg].ds_addr); 1269 sc->sc_txdescs[nexttx].sipd_cmdsts = 1270 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1271 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1272 #ifdef DP83820 1273 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1274 #endif /* DP83820 */ 1275 lasttx = nexttx; 1276 } 1277 1278 /* Clear the MORE bit on the last segment. */ 1279 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1280 1281 /* 1282 * If we're in the interrupt delay window, delay the 1283 * interrupt. 1284 */ 1285 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1286 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1287 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1288 htole32(CMDSTS_INTR); 1289 sc->sc_txwin = 0; 1290 } 1291 1292 #ifdef DP83820 1293 /* 1294 * If VLANs are enabled and the packet has a VLAN tag, set 1295 * up the descriptor to encapsulate the packet for us. 1296 * 1297 * This apparently has to be on the last descriptor of 1298 * the packet. 1299 */ 1300 if (sc->sc_ethercom.ec_nvlans != 0 && 1301 (m = m_aux_find(m0, AF_LINK, ETHERTYPE_VLAN)) != NULL) { 1302 sc->sc_txdescs[lasttx].sipd_extsts |= 1303 htole32(EXTSTS_VPKT | 1304 htons(*mtod(m, int *) & EXTSTS_VTCI)); 1305 } 1306 1307 /* 1308 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1309 * checksumming, set up the descriptor to do this work 1310 * for us. 1311 * 1312 * This apparently has to be on the first descriptor of 1313 * the packet. 1314 * 1315 * Byte-swap constants so the compiler can optimize. 1316 */ 1317 extsts = 0; 1318 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1319 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1320 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1321 extsts |= htole32(EXTSTS_IPPKT); 1322 } 1323 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1324 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1325 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1326 extsts |= htole32(EXTSTS_TCPPKT); 1327 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1328 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1329 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1330 extsts |= htole32(EXTSTS_UDPPKT); 1331 } 1332 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1333 #endif /* DP83820 */ 1334 1335 /* Sync the descriptors we're using. */ 1336 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1337 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1338 1339 /* 1340 * The entire packet is set up. Give the first descrptor 1341 * to the chip now. 1342 */ 1343 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1344 htole32(CMDSTS_OWN); 1345 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1346 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1347 1348 /* 1349 * Store a pointer to the packet so we can free it later, 1350 * and remember what txdirty will be once the packet is 1351 * done. 1352 */ 1353 txs->txs_mbuf = m0; 1354 txs->txs_firstdesc = sc->sc_txnext; 1355 txs->txs_lastdesc = lasttx; 1356 1357 /* Advance the tx pointer. */ 1358 sc->sc_txfree -= dmamap->dm_nsegs; 1359 sc->sc_txnext = nexttx; 1360 1361 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1362 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1363 1364 #if NBPFILTER > 0 1365 /* 1366 * Pass the packet to any BPF listeners. 1367 */ 1368 if (ifp->if_bpf) 1369 bpf_mtap(ifp->if_bpf, m0); 1370 #endif /* NBPFILTER > 0 */ 1371 } 1372 1373 if (txs == NULL || sc->sc_txfree == 0) { 1374 /* No more slots left; notify upper layer. */ 1375 ifp->if_flags |= IFF_OACTIVE; 1376 } 1377 1378 if (sc->sc_txfree != ofree) { 1379 /* 1380 * Start the transmit process. Note, the manual says 1381 * that if there are no pending transmissions in the 1382 * chip's internal queue (indicated by TXE being clear), 1383 * then the driver software must set the TXDP to the 1384 * first descriptor to be transmitted. However, if we 1385 * do this, it causes serious performance degredation on 1386 * the DP83820 under load, not setting TXDP doesn't seem 1387 * to adversely affect the SiS 900 or DP83815. 1388 * 1389 * Well, I guess it wouldn't be the first time a manual 1390 * has lied -- and they could be speaking of the NULL- 1391 * terminated descriptor list case, rather than OWN- 1392 * terminated rings. 1393 */ 1394 #if 0 1395 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1396 CR_TXE) == 0) { 1397 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1398 SIP_CDTXADDR(sc, firsttx)); 1399 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1400 } 1401 #else 1402 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1403 #endif 1404 1405 /* Set a watchdog timer in case the chip flakes out. */ 1406 ifp->if_timer = 5; 1407 } 1408 } 1409 1410 /* 1411 * sip_watchdog: [ifnet interface function] 1412 * 1413 * Watchdog timer handler. 1414 */ 1415 void 1416 SIP_DECL(watchdog)(struct ifnet *ifp) 1417 { 1418 struct sip_softc *sc = ifp->if_softc; 1419 1420 /* 1421 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1422 * If we get a timeout, try and sweep up transmit descriptors. 1423 * If we manage to sweep them all up, ignore the lack of 1424 * interrupt. 1425 */ 1426 SIP_DECL(txintr)(sc); 1427 1428 if (sc->sc_txfree != SIP_NTXDESC) { 1429 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1430 ifp->if_oerrors++; 1431 1432 /* Reset the interface. */ 1433 (void) SIP_DECL(init)(ifp); 1434 } else if (ifp->if_flags & IFF_DEBUG) 1435 printf("%s: recovered from device timeout\n", 1436 sc->sc_dev.dv_xname); 1437 1438 /* Try to get more packets going. */ 1439 SIP_DECL(start)(ifp); 1440 } 1441 1442 /* 1443 * sip_ioctl: [ifnet interface function] 1444 * 1445 * Handle control requests from the operator. 1446 */ 1447 int 1448 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1449 { 1450 struct sip_softc *sc = ifp->if_softc; 1451 struct ifreq *ifr = (struct ifreq *)data; 1452 int s, error; 1453 1454 s = splnet(); 1455 1456 switch (cmd) { 1457 case SIOCSIFMEDIA: 1458 case SIOCGIFMEDIA: 1459 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1460 break; 1461 1462 default: 1463 error = ether_ioctl(ifp, cmd, data); 1464 if (error == ENETRESET) { 1465 /* 1466 * Multicast list has changed; set the hardware filter 1467 * accordingly. 1468 */ 1469 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1470 error = 0; 1471 } 1472 break; 1473 } 1474 1475 /* Try to get more packets going. */ 1476 SIP_DECL(start)(ifp); 1477 1478 splx(s); 1479 return (error); 1480 } 1481 1482 /* 1483 * sip_intr: 1484 * 1485 * Interrupt service routine. 1486 */ 1487 int 1488 SIP_DECL(intr)(void *arg) 1489 { 1490 struct sip_softc *sc = arg; 1491 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1492 u_int32_t isr; 1493 int handled = 0; 1494 1495 for (;;) { 1496 /* Reading clears interrupt. */ 1497 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1498 if ((isr & sc->sc_imr) == 0) 1499 break; 1500 1501 #if NRND > 0 1502 rnd_add_uint32(&sc->rnd_source, isr); 1503 #endif 1504 1505 handled = 1; 1506 1507 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1508 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1509 1510 /* Grab any new packets. */ 1511 SIP_DECL(rxintr)(sc); 1512 1513 if (isr & ISR_RXORN) { 1514 printf("%s: receive FIFO overrun\n", 1515 sc->sc_dev.dv_xname); 1516 1517 /* XXX adjust rx_drain_thresh? */ 1518 } 1519 1520 if (isr & ISR_RXIDLE) { 1521 printf("%s: receive ring overrun\n", 1522 sc->sc_dev.dv_xname); 1523 1524 /* Get the receive process going again. */ 1525 bus_space_write_4(sc->sc_st, sc->sc_sh, 1526 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1527 bus_space_write_4(sc->sc_st, sc->sc_sh, 1528 SIP_CR, CR_RXE); 1529 } 1530 } 1531 1532 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1533 #ifdef SIP_EVENT_COUNTERS 1534 if (isr & ISR_TXDESC) 1535 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1536 else if (isr & ISR_TXIDLE) 1537 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1538 #endif 1539 1540 /* Sweep up transmit descriptors. */ 1541 SIP_DECL(txintr)(sc); 1542 1543 if (isr & ISR_TXURN) { 1544 u_int32_t thresh; 1545 1546 printf("%s: transmit FIFO underrun", 1547 sc->sc_dev.dv_xname); 1548 1549 thresh = sc->sc_tx_drain_thresh + 1; 1550 if (thresh <= TXCFG_DRTH && 1551 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1552 (sc->sc_tx_fill_thresh * 32))) { 1553 printf("; increasing Tx drain " 1554 "threshold to %u bytes\n", 1555 thresh * 32); 1556 sc->sc_tx_drain_thresh = thresh; 1557 (void) SIP_DECL(init)(ifp); 1558 } else { 1559 (void) SIP_DECL(init)(ifp); 1560 printf("\n"); 1561 } 1562 } 1563 } 1564 1565 #if !defined(DP83820) 1566 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1567 if (isr & ISR_PAUSE_ST) { 1568 sc->sc_flags |= SIPF_PAUSED; 1569 ifp->if_flags |= IFF_OACTIVE; 1570 } 1571 if (isr & ISR_PAUSE_END) { 1572 sc->sc_flags &= ~SIPF_PAUSED; 1573 ifp->if_flags &= ~IFF_OACTIVE; 1574 } 1575 } 1576 #endif /* ! DP83820 */ 1577 1578 if (isr & ISR_HIBERR) { 1579 int want_init = 0; 1580 1581 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1582 1583 #define PRINTERR(bit, str) \ 1584 do { \ 1585 if (isr & (bit)) { \ 1586 printf("%s: %s\n", \ 1587 sc->sc_dev.dv_xname, str); \ 1588 want_init = 1; \ 1589 } \ 1590 } while (/*CONSTCOND*/0) 1591 1592 PRINTERR(ISR_DPERR, "parity error"); 1593 PRINTERR(ISR_SSERR, "system error"); 1594 PRINTERR(ISR_RMABT, "master abort"); 1595 PRINTERR(ISR_RTABT, "target abort"); 1596 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1597 /* 1598 * Ignore: 1599 * Tx reset complete 1600 * Rx reset complete 1601 */ 1602 if (want_init) 1603 (void) SIP_DECL(init)(ifp); 1604 #undef PRINTERR 1605 } 1606 } 1607 1608 /* Try to get more packets going. */ 1609 SIP_DECL(start)(ifp); 1610 1611 return (handled); 1612 } 1613 1614 /* 1615 * sip_txintr: 1616 * 1617 * Helper; handle transmit interrupts. 1618 */ 1619 void 1620 SIP_DECL(txintr)(struct sip_softc *sc) 1621 { 1622 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1623 struct sip_txsoft *txs; 1624 u_int32_t cmdsts; 1625 1626 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1627 ifp->if_flags &= ~IFF_OACTIVE; 1628 1629 /* 1630 * Go through our Tx list and free mbufs for those 1631 * frames which have been transmitted. 1632 */ 1633 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1634 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1635 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1636 1637 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1638 if (cmdsts & CMDSTS_OWN) 1639 break; 1640 1641 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1642 1643 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1644 1645 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1646 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1647 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1648 m_freem(txs->txs_mbuf); 1649 txs->txs_mbuf = NULL; 1650 1651 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1652 1653 /* 1654 * Check for errors and collisions. 1655 */ 1656 if (cmdsts & 1657 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1658 ifp->if_oerrors++; 1659 if (cmdsts & CMDSTS_Tx_EC) 1660 ifp->if_collisions += 16; 1661 if (ifp->if_flags & IFF_DEBUG) { 1662 if (cmdsts & CMDSTS_Tx_ED) 1663 printf("%s: excessive deferral\n", 1664 sc->sc_dev.dv_xname); 1665 if (cmdsts & CMDSTS_Tx_EC) 1666 printf("%s: excessive collisions\n", 1667 sc->sc_dev.dv_xname); 1668 } 1669 } else { 1670 /* Packet was transmitted successfully. */ 1671 ifp->if_opackets++; 1672 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1673 } 1674 } 1675 1676 /* 1677 * If there are no more pending transmissions, cancel the watchdog 1678 * timer. 1679 */ 1680 if (txs == NULL) { 1681 ifp->if_timer = 0; 1682 sc->sc_txwin = 0; 1683 } 1684 } 1685 1686 #if defined(DP83820) 1687 /* 1688 * sip_rxintr: 1689 * 1690 * Helper; handle receive interrupts. 1691 */ 1692 void 1693 SIP_DECL(rxintr)(struct sip_softc *sc) 1694 { 1695 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1696 struct sip_rxsoft *rxs; 1697 struct mbuf *m, *tailm; 1698 u_int32_t cmdsts, extsts; 1699 int i, len; 1700 1701 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1702 rxs = &sc->sc_rxsoft[i]; 1703 1704 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1705 1706 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1707 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1708 1709 /* 1710 * NOTE: OWN is set if owned by _consumer_. We're the 1711 * consumer of the receive ring, so if the bit is clear, 1712 * we have processed all of the packets. 1713 */ 1714 if ((cmdsts & CMDSTS_OWN) == 0) { 1715 /* 1716 * We have processed all of the receive buffers. 1717 */ 1718 break; 1719 } 1720 1721 if (__predict_false(sc->sc_rxdiscard)) { 1722 SIP_INIT_RXDESC(sc, i); 1723 if ((cmdsts & CMDSTS_MORE) == 0) { 1724 /* Reset our state. */ 1725 sc->sc_rxdiscard = 0; 1726 } 1727 continue; 1728 } 1729 1730 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1731 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1732 1733 m = rxs->rxs_mbuf; 1734 1735 /* 1736 * Add a new receive buffer to the ring. 1737 */ 1738 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1739 /* 1740 * Failed, throw away what we've done so 1741 * far, and discard the rest of the packet. 1742 */ 1743 ifp->if_ierrors++; 1744 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1745 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1746 SIP_INIT_RXDESC(sc, i); 1747 if (cmdsts & CMDSTS_MORE) 1748 sc->sc_rxdiscard = 1; 1749 if (sc->sc_rxhead != NULL) 1750 m_freem(sc->sc_rxhead); 1751 SIP_RXCHAIN_RESET(sc); 1752 continue; 1753 } 1754 1755 SIP_RXCHAIN_LINK(sc, m); 1756 1757 /* 1758 * If this is not the end of the packet, keep 1759 * looking. 1760 */ 1761 if (cmdsts & CMDSTS_MORE) { 1762 sc->sc_rxlen += m->m_len; 1763 continue; 1764 } 1765 1766 /* 1767 * Okay, we have the entire packet now... 1768 */ 1769 *sc->sc_rxtailp = NULL; 1770 m = sc->sc_rxhead; 1771 tailm = sc->sc_rxtail; 1772 1773 SIP_RXCHAIN_RESET(sc); 1774 1775 /* 1776 * If an error occurred, update stats and drop the packet. 1777 */ 1778 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1779 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1780 ifp->if_ierrors++; 1781 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1782 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1783 /* Receive overrun handled elsewhere. */ 1784 printf("%s: receive descriptor error\n", 1785 sc->sc_dev.dv_xname); 1786 } 1787 #define PRINTERR(bit, str) \ 1788 if (cmdsts & (bit)) \ 1789 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1790 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1791 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1792 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1793 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1794 #undef PRINTERR 1795 m_freem(m); 1796 continue; 1797 } 1798 1799 /* 1800 * No errors. 1801 * 1802 * Note, the DP83820 includes the CRC with 1803 * every packet. 1804 */ 1805 len = CMDSTS_SIZE(cmdsts); 1806 tailm->m_len = len - sc->sc_rxlen; 1807 1808 /* 1809 * If the packet is small enough to fit in a 1810 * single header mbuf, allocate one and copy 1811 * the data into it. This greatly reduces 1812 * memory consumption when we receive lots 1813 * of small packets. 1814 */ 1815 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1816 struct mbuf *nm; 1817 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1818 if (nm == NULL) { 1819 ifp->if_ierrors++; 1820 m_freem(m); 1821 continue; 1822 } 1823 nm->m_data += 2; 1824 nm->m_pkthdr.len = nm->m_len = len; 1825 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1826 m_freem(m); 1827 m = nm; 1828 } 1829 #ifndef __NO_STRICT_ALIGNMENT 1830 else { 1831 /* 1832 * The DP83820's receive buffers must be 4-byte 1833 * aligned. But this means that the data after 1834 * the Ethernet header is misaligned. To compensate, 1835 * we have artificially shortened the buffer size 1836 * in the descriptor, and we do an overlapping copy 1837 * of the data two bytes further in (in the first 1838 * buffer of the chain only). 1839 */ 1840 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1841 m->m_len); 1842 m->m_data += 2; 1843 } 1844 #endif /* ! __NO_STRICT_ALIGNMENT */ 1845 1846 /* 1847 * If VLANs are enabled, VLAN packets have been unwrapped 1848 * for us. Associate the tag with the packet. 1849 */ 1850 if (sc->sc_ethercom.ec_nvlans != 0 && 1851 (extsts & EXTSTS_VPKT) != 0) { 1852 struct mbuf *vtag; 1853 1854 vtag = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 1855 if (vtag == NULL) { 1856 ifp->if_ierrors++; 1857 printf("%s: unable to allocate VLAN tag\n", 1858 sc->sc_dev.dv_xname); 1859 m_freem(m); 1860 continue; 1861 } 1862 1863 *mtod(vtag, int *) = ntohs(extsts & EXTSTS_VTCI); 1864 vtag->m_len = sizeof(int); 1865 } 1866 1867 /* 1868 * Set the incoming checksum information for the 1869 * packet. 1870 */ 1871 if ((extsts & EXTSTS_IPPKT) != 0) { 1872 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1873 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1874 if (extsts & EXTSTS_Rx_IPERR) 1875 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1876 if (extsts & EXTSTS_TCPPKT) { 1877 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1878 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1879 if (extsts & EXTSTS_Rx_TCPERR) 1880 m->m_pkthdr.csum_flags |= 1881 M_CSUM_TCP_UDP_BAD; 1882 } else if (extsts & EXTSTS_UDPPKT) { 1883 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1884 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1885 if (extsts & EXTSTS_Rx_UDPERR) 1886 m->m_pkthdr.csum_flags |= 1887 M_CSUM_TCP_UDP_BAD; 1888 } 1889 } 1890 1891 ifp->if_ipackets++; 1892 m->m_flags |= M_HASFCS; 1893 m->m_pkthdr.rcvif = ifp; 1894 m->m_pkthdr.len = len; 1895 1896 #if NBPFILTER > 0 1897 /* 1898 * Pass this up to any BPF listeners, but only 1899 * pass if up the stack if it's for us. 1900 */ 1901 if (ifp->if_bpf) 1902 bpf_mtap(ifp->if_bpf, m); 1903 #endif /* NBPFILTER > 0 */ 1904 1905 /* Pass it on. */ 1906 (*ifp->if_input)(ifp, m); 1907 } 1908 1909 /* Update the receive pointer. */ 1910 sc->sc_rxptr = i; 1911 } 1912 #else /* ! DP83820 */ 1913 /* 1914 * sip_rxintr: 1915 * 1916 * Helper; handle receive interrupts. 1917 */ 1918 void 1919 SIP_DECL(rxintr)(struct sip_softc *sc) 1920 { 1921 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1922 struct sip_rxsoft *rxs; 1923 struct mbuf *m; 1924 u_int32_t cmdsts; 1925 int i, len; 1926 1927 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1928 rxs = &sc->sc_rxsoft[i]; 1929 1930 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1931 1932 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1933 1934 /* 1935 * NOTE: OWN is set if owned by _consumer_. We're the 1936 * consumer of the receive ring, so if the bit is clear, 1937 * we have processed all of the packets. 1938 */ 1939 if ((cmdsts & CMDSTS_OWN) == 0) { 1940 /* 1941 * We have processed all of the receive buffers. 1942 */ 1943 break; 1944 } 1945 1946 /* 1947 * If any collisions were seen on the wire, count one. 1948 */ 1949 if (cmdsts & CMDSTS_Rx_COL) 1950 ifp->if_collisions++; 1951 1952 /* 1953 * If an error occurred, update stats, clear the status 1954 * word, and leave the packet buffer in place. It will 1955 * simply be reused the next time the ring comes around. 1956 */ 1957 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1958 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1959 ifp->if_ierrors++; 1960 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1961 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1962 /* Receive overrun handled elsewhere. */ 1963 printf("%s: receive descriptor error\n", 1964 sc->sc_dev.dv_xname); 1965 } 1966 #define PRINTERR(bit, str) \ 1967 if (cmdsts & (bit)) \ 1968 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1969 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1970 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1971 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1972 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1973 #undef PRINTERR 1974 SIP_INIT_RXDESC(sc, i); 1975 continue; 1976 } 1977 1978 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1979 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1980 1981 /* 1982 * No errors; receive the packet. Note, the SiS 900 1983 * includes the CRC with every packet. 1984 */ 1985 len = CMDSTS_SIZE(cmdsts); 1986 1987 #ifdef __NO_STRICT_ALIGNMENT 1988 /* 1989 * If the packet is small enough to fit in a 1990 * single header mbuf, allocate one and copy 1991 * the data into it. This greatly reduces 1992 * memory consumption when we receive lots 1993 * of small packets. 1994 * 1995 * Otherwise, we add a new buffer to the receive 1996 * chain. If this fails, we drop the packet and 1997 * recycle the old buffer. 1998 */ 1999 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 2000 MGETHDR(m, M_DONTWAIT, MT_DATA); 2001 if (m == NULL) 2002 goto dropit; 2003 memcpy(mtod(m, caddr_t), 2004 mtod(rxs->rxs_mbuf, caddr_t), len); 2005 SIP_INIT_RXDESC(sc, i); 2006 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2007 rxs->rxs_dmamap->dm_mapsize, 2008 BUS_DMASYNC_PREREAD); 2009 } else { 2010 m = rxs->rxs_mbuf; 2011 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 2012 dropit: 2013 ifp->if_ierrors++; 2014 SIP_INIT_RXDESC(sc, i); 2015 bus_dmamap_sync(sc->sc_dmat, 2016 rxs->rxs_dmamap, 0, 2017 rxs->rxs_dmamap->dm_mapsize, 2018 BUS_DMASYNC_PREREAD); 2019 continue; 2020 } 2021 } 2022 #else 2023 /* 2024 * The SiS 900's receive buffers must be 4-byte aligned. 2025 * But this means that the data after the Ethernet header 2026 * is misaligned. We must allocate a new buffer and 2027 * copy the data, shifted forward 2 bytes. 2028 */ 2029 MGETHDR(m, M_DONTWAIT, MT_DATA); 2030 if (m == NULL) { 2031 dropit: 2032 ifp->if_ierrors++; 2033 SIP_INIT_RXDESC(sc, i); 2034 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2035 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2036 continue; 2037 } 2038 if (len > (MHLEN - 2)) { 2039 MCLGET(m, M_DONTWAIT); 2040 if ((m->m_flags & M_EXT) == 0) { 2041 m_freem(m); 2042 goto dropit; 2043 } 2044 } 2045 m->m_data += 2; 2046 2047 /* 2048 * Note that we use clusters for incoming frames, so the 2049 * buffer is virtually contiguous. 2050 */ 2051 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 2052 2053 /* Allow the receive descriptor to continue using its mbuf. */ 2054 SIP_INIT_RXDESC(sc, i); 2055 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2056 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2057 #endif /* __NO_STRICT_ALIGNMENT */ 2058 2059 ifp->if_ipackets++; 2060 m->m_flags |= M_HASFCS; 2061 m->m_pkthdr.rcvif = ifp; 2062 m->m_pkthdr.len = m->m_len = len; 2063 2064 #if NBPFILTER > 0 2065 /* 2066 * Pass this up to any BPF listeners, but only 2067 * pass if up the stack if it's for us. 2068 */ 2069 if (ifp->if_bpf) 2070 bpf_mtap(ifp->if_bpf, m); 2071 #endif /* NBPFILTER > 0 */ 2072 2073 /* Pass it on. */ 2074 (*ifp->if_input)(ifp, m); 2075 } 2076 2077 /* Update the receive pointer. */ 2078 sc->sc_rxptr = i; 2079 } 2080 #endif /* DP83820 */ 2081 2082 /* 2083 * sip_tick: 2084 * 2085 * One second timer, used to tick the MII. 2086 */ 2087 void 2088 SIP_DECL(tick)(void *arg) 2089 { 2090 struct sip_softc *sc = arg; 2091 int s; 2092 2093 s = splnet(); 2094 mii_tick(&sc->sc_mii); 2095 splx(s); 2096 2097 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2098 } 2099 2100 /* 2101 * sip_reset: 2102 * 2103 * Perform a soft reset on the SiS 900. 2104 */ 2105 void 2106 SIP_DECL(reset)(struct sip_softc *sc) 2107 { 2108 bus_space_tag_t st = sc->sc_st; 2109 bus_space_handle_t sh = sc->sc_sh; 2110 int i; 2111 2112 bus_space_write_4(st, sh, SIP_IER, 0); 2113 bus_space_write_4(st, sh, SIP_IMR, 0); 2114 bus_space_write_4(st, sh, SIP_RFCR, 0); 2115 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2116 2117 for (i = 0; i < SIP_TIMEOUT; i++) { 2118 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2119 break; 2120 delay(2); 2121 } 2122 2123 if (i == SIP_TIMEOUT) 2124 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2125 2126 delay(1000); 2127 2128 #ifdef DP83820 2129 /* 2130 * Set the general purpose I/O bits. Do it here in case we 2131 * need to have GPIO set up to talk to the media interface. 2132 */ 2133 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2134 delay(1000); 2135 #endif /* DP83820 */ 2136 } 2137 2138 /* 2139 * sip_init: [ ifnet interface function ] 2140 * 2141 * Initialize the interface. Must be called at splnet(). 2142 */ 2143 int 2144 SIP_DECL(init)(struct ifnet *ifp) 2145 { 2146 struct sip_softc *sc = ifp->if_softc; 2147 bus_space_tag_t st = sc->sc_st; 2148 bus_space_handle_t sh = sc->sc_sh; 2149 struct sip_txsoft *txs; 2150 struct sip_rxsoft *rxs; 2151 struct sip_desc *sipd; 2152 u_int32_t reg; 2153 int i, error = 0; 2154 2155 /* 2156 * Cancel any pending I/O. 2157 */ 2158 SIP_DECL(stop)(ifp, 0); 2159 2160 /* 2161 * Reset the chip to a known state. 2162 */ 2163 SIP_DECL(reset)(sc); 2164 2165 #if !defined(DP83820) 2166 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2167 /* 2168 * DP83815 manual, page 78: 2169 * 4.4 Recommended Registers Configuration 2170 * For optimum performance of the DP83815, version noted 2171 * as DP83815CVNG (SRR = 203h), the listed register 2172 * modifications must be followed in sequence... 2173 * 2174 * It's not clear if this should be 302h or 203h because that 2175 * chip name is listed as SRR 302h in the description of the 2176 * SRR register. However, my revision 302h DP83815 on the 2177 * Netgear FA311 purchased in 02/2001 needs these settings 2178 * to avoid tons of errors in AcceptPerfectMatch (non- 2179 * IFF_PROMISC) mode. I do not know if other revisions need 2180 * this set or not. [briggs -- 09 March 2001] 2181 * 2182 * Note that only the low-order 12 bits of 0xe4 are documented 2183 * and that this sets reserved bits in that register. 2184 */ 2185 reg = bus_space_read_4(st, sh, SIP_NS_SRR); 2186 if (reg == 0x302) { 2187 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2188 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2189 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2190 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2191 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2192 } 2193 } 2194 #endif /* ! DP83820 */ 2195 2196 /* 2197 * Initialize the transmit descriptor ring. 2198 */ 2199 for (i = 0; i < SIP_NTXDESC; i++) { 2200 sipd = &sc->sc_txdescs[i]; 2201 memset(sipd, 0, sizeof(struct sip_desc)); 2202 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2203 } 2204 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2205 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2206 sc->sc_txfree = SIP_NTXDESC; 2207 sc->sc_txnext = 0; 2208 sc->sc_txwin = 0; 2209 2210 /* 2211 * Initialize the transmit job descriptors. 2212 */ 2213 SIMPLEQ_INIT(&sc->sc_txfreeq); 2214 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2215 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2216 txs = &sc->sc_txsoft[i]; 2217 txs->txs_mbuf = NULL; 2218 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2219 } 2220 2221 /* 2222 * Initialize the receive descriptor and receive job 2223 * descriptor rings. 2224 */ 2225 for (i = 0; i < SIP_NRXDESC; i++) { 2226 rxs = &sc->sc_rxsoft[i]; 2227 if (rxs->rxs_mbuf == NULL) { 2228 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2229 printf("%s: unable to allocate or map rx " 2230 "buffer %d, error = %d\n", 2231 sc->sc_dev.dv_xname, i, error); 2232 /* 2233 * XXX Should attempt to run with fewer receive 2234 * XXX buffers instead of just failing. 2235 */ 2236 SIP_DECL(rxdrain)(sc); 2237 goto out; 2238 } 2239 } else 2240 SIP_INIT_RXDESC(sc, i); 2241 } 2242 sc->sc_rxptr = 0; 2243 #ifdef DP83820 2244 sc->sc_rxdiscard = 0; 2245 SIP_RXCHAIN_RESET(sc); 2246 #endif /* DP83820 */ 2247 2248 /* 2249 * Set the configuration register; it's already initialized 2250 * in sip_attach(). 2251 */ 2252 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2253 2254 /* 2255 * Initialize the prototype TXCFG register. 2256 */ 2257 #if defined(DP83820) 2258 sc->sc_txcfg = TXCFG_MXDMA_512; 2259 sc->sc_rxcfg = RXCFG_MXDMA_512; 2260 #else 2261 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2262 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2263 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & CFG_EDBMASTEN)) { 2264 sc->sc_txcfg = TXCFG_MXDMA_64; 2265 sc->sc_rxcfg = RXCFG_MXDMA_64; 2266 } else { 2267 sc->sc_txcfg = TXCFG_MXDMA_512; 2268 sc->sc_rxcfg = RXCFG_MXDMA_512; 2269 } 2270 #endif /* DP83820 */ 2271 2272 sc->sc_txcfg |= TXCFG_ATP | 2273 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2274 sc->sc_tx_drain_thresh; 2275 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2276 2277 /* 2278 * Initialize the receive drain threshold if we have never 2279 * done so. 2280 */ 2281 if (sc->sc_rx_drain_thresh == 0) { 2282 /* 2283 * XXX This value should be tuned. This is set to the 2284 * maximum of 248 bytes, and we may be able to improve 2285 * performance by decreasing it (although we should never 2286 * set this value lower than 2; 14 bytes are required to 2287 * filter the packet). 2288 */ 2289 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2290 } 2291 2292 /* 2293 * Initialize the prototype RXCFG register. 2294 */ 2295 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2296 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2297 2298 #ifdef DP83820 2299 /* 2300 * Initialize the VLAN/IP receive control register. 2301 * We enable checksum computation on all incoming 2302 * packets, and do not reject packets w/ bad checksums. 2303 */ 2304 reg = 0; 2305 if (ifp->if_capenable & 2306 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2307 reg |= VRCR_IPEN; 2308 if (sc->sc_ethercom.ec_nvlans != 0) 2309 reg |= VRCR_VTDEN|VRCR_VTREN; 2310 bus_space_write_4(st, sh, SIP_VRCR, reg); 2311 2312 /* 2313 * Initialize the VLAN/IP transmit control register. 2314 * We enable outgoing checksum computation on a 2315 * per-packet basis. 2316 */ 2317 reg = 0; 2318 if (ifp->if_capenable & 2319 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2320 reg |= VTCR_PPCHK; 2321 if (sc->sc_ethercom.ec_nvlans != 0) 2322 reg |= VTCR_VPPTI; 2323 bus_space_write_4(st, sh, SIP_VTCR, reg); 2324 2325 /* 2326 * If we're using VLANs, initialize the VLAN data register. 2327 * To understand why we bswap the VLAN Ethertype, see section 2328 * 4.2.36 of the DP83820 manual. 2329 */ 2330 if (sc->sc_ethercom.ec_nvlans != 0) 2331 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2332 #endif /* DP83820 */ 2333 2334 /* 2335 * Give the transmit and receive rings to the chip. 2336 */ 2337 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2338 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2339 2340 /* 2341 * Initialize the interrupt mask. 2342 */ 2343 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2344 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2345 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2346 2347 /* Set up the receive filter. */ 2348 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2349 2350 /* 2351 * Set the current media. Do this after initializing the prototype 2352 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2353 * control. 2354 */ 2355 mii_mediachg(&sc->sc_mii); 2356 2357 /* 2358 * Enable interrupts. 2359 */ 2360 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2361 2362 /* 2363 * Start the transmit and receive processes. 2364 */ 2365 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2366 2367 /* 2368 * Start the one second MII clock. 2369 */ 2370 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2371 2372 /* 2373 * ...all done! 2374 */ 2375 ifp->if_flags |= IFF_RUNNING; 2376 ifp->if_flags &= ~IFF_OACTIVE; 2377 2378 out: 2379 if (error) 2380 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2381 return (error); 2382 } 2383 2384 /* 2385 * sip_drain: 2386 * 2387 * Drain the receive queue. 2388 */ 2389 void 2390 SIP_DECL(rxdrain)(struct sip_softc *sc) 2391 { 2392 struct sip_rxsoft *rxs; 2393 int i; 2394 2395 for (i = 0; i < SIP_NRXDESC; i++) { 2396 rxs = &sc->sc_rxsoft[i]; 2397 if (rxs->rxs_mbuf != NULL) { 2398 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2399 m_freem(rxs->rxs_mbuf); 2400 rxs->rxs_mbuf = NULL; 2401 } 2402 } 2403 } 2404 2405 /* 2406 * sip_stop: [ ifnet interface function ] 2407 * 2408 * Stop transmission on the interface. 2409 */ 2410 void 2411 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2412 { 2413 struct sip_softc *sc = ifp->if_softc; 2414 bus_space_tag_t st = sc->sc_st; 2415 bus_space_handle_t sh = sc->sc_sh; 2416 struct sip_txsoft *txs; 2417 u_int32_t cmdsts = 0; /* DEBUG */ 2418 2419 /* 2420 * Stop the one second clock. 2421 */ 2422 callout_stop(&sc->sc_tick_ch); 2423 2424 /* Down the MII. */ 2425 mii_down(&sc->sc_mii); 2426 2427 /* 2428 * Disable interrupts. 2429 */ 2430 bus_space_write_4(st, sh, SIP_IER, 0); 2431 2432 /* 2433 * Stop receiver and transmitter. 2434 */ 2435 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2436 2437 /* 2438 * Release any queued transmit buffers. 2439 */ 2440 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2441 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2442 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2443 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2444 CMDSTS_INTR) == 0) 2445 printf("%s: sip_stop: last descriptor does not " 2446 "have INTR bit set\n", sc->sc_dev.dv_xname); 2447 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2448 #ifdef DIAGNOSTIC 2449 if (txs->txs_mbuf == NULL) { 2450 printf("%s: dirty txsoft with no mbuf chain\n", 2451 sc->sc_dev.dv_xname); 2452 panic("sip_stop"); 2453 } 2454 #endif 2455 cmdsts |= /* DEBUG */ 2456 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2457 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2458 m_freem(txs->txs_mbuf); 2459 txs->txs_mbuf = NULL; 2460 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2461 } 2462 2463 if (disable) 2464 SIP_DECL(rxdrain)(sc); 2465 2466 /* 2467 * Mark the interface down and cancel the watchdog timer. 2468 */ 2469 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2470 ifp->if_timer = 0; 2471 2472 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2473 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2474 printf("%s: sip_stop: no INTR bits set in dirty tx " 2475 "descriptors\n", sc->sc_dev.dv_xname); 2476 } 2477 2478 /* 2479 * sip_read_eeprom: 2480 * 2481 * Read data from the serial EEPROM. 2482 */ 2483 void 2484 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2485 u_int16_t *data) 2486 { 2487 bus_space_tag_t st = sc->sc_st; 2488 bus_space_handle_t sh = sc->sc_sh; 2489 u_int16_t reg; 2490 int i, x; 2491 2492 for (i = 0; i < wordcnt; i++) { 2493 /* Send CHIP SELECT. */ 2494 reg = EROMAR_EECS; 2495 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2496 2497 /* Shift in the READ opcode. */ 2498 for (x = 3; x > 0; x--) { 2499 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2500 reg |= EROMAR_EEDI; 2501 else 2502 reg &= ~EROMAR_EEDI; 2503 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2504 bus_space_write_4(st, sh, SIP_EROMAR, 2505 reg | EROMAR_EESK); 2506 delay(4); 2507 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2508 delay(4); 2509 } 2510 2511 /* Shift in address. */ 2512 for (x = 6; x > 0; x--) { 2513 if ((word + i) & (1 << (x - 1))) 2514 reg |= EROMAR_EEDI; 2515 else 2516 reg &= ~EROMAR_EEDI; 2517 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2518 bus_space_write_4(st, sh, SIP_EROMAR, 2519 reg | EROMAR_EESK); 2520 delay(4); 2521 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2522 delay(4); 2523 } 2524 2525 /* Shift out data. */ 2526 reg = EROMAR_EECS; 2527 data[i] = 0; 2528 for (x = 16; x > 0; x--) { 2529 bus_space_write_4(st, sh, SIP_EROMAR, 2530 reg | EROMAR_EESK); 2531 delay(4); 2532 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2533 data[i] |= (1 << (x - 1)); 2534 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2535 delay(4); 2536 } 2537 2538 /* Clear CHIP SELECT. */ 2539 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2540 delay(4); 2541 } 2542 } 2543 2544 /* 2545 * sip_add_rxbuf: 2546 * 2547 * Add a receive buffer to the indicated descriptor. 2548 */ 2549 int 2550 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2551 { 2552 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2553 struct mbuf *m; 2554 int error; 2555 2556 MGETHDR(m, M_DONTWAIT, MT_DATA); 2557 if (m == NULL) 2558 return (ENOBUFS); 2559 2560 MCLGET(m, M_DONTWAIT); 2561 if ((m->m_flags & M_EXT) == 0) { 2562 m_freem(m); 2563 return (ENOBUFS); 2564 } 2565 2566 #if defined(DP83820) 2567 m->m_len = SIP_RXBUF_LEN; 2568 #endif /* DP83820 */ 2569 2570 if (rxs->rxs_mbuf != NULL) 2571 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2572 2573 rxs->rxs_mbuf = m; 2574 2575 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2576 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2577 BUS_DMA_READ|BUS_DMA_NOWAIT); 2578 if (error) { 2579 printf("%s: can't load rx DMA map %d, error = %d\n", 2580 sc->sc_dev.dv_xname, idx, error); 2581 panic("sip_add_rxbuf"); /* XXX */ 2582 } 2583 2584 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2585 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2586 2587 SIP_INIT_RXDESC(sc, idx); 2588 2589 return (0); 2590 } 2591 2592 #if !defined(DP83820) 2593 /* 2594 * sip_sis900_set_filter: 2595 * 2596 * Set up the receive filter. 2597 */ 2598 void 2599 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2600 { 2601 bus_space_tag_t st = sc->sc_st; 2602 bus_space_handle_t sh = sc->sc_sh; 2603 struct ethercom *ec = &sc->sc_ethercom; 2604 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2605 struct ether_multi *enm; 2606 u_int8_t *cp; 2607 struct ether_multistep step; 2608 u_int32_t crc, mchash[16]; 2609 2610 /* 2611 * Initialize the prototype RFCR. 2612 */ 2613 sc->sc_rfcr = RFCR_RFEN; 2614 if (ifp->if_flags & IFF_BROADCAST) 2615 sc->sc_rfcr |= RFCR_AAB; 2616 if (ifp->if_flags & IFF_PROMISC) { 2617 sc->sc_rfcr |= RFCR_AAP; 2618 goto allmulti; 2619 } 2620 2621 /* 2622 * Set up the multicast address filter by passing all multicast 2623 * addresses through a CRC generator, and then using the high-order 2624 * 6 bits as an index into the 128 bit multicast hash table (only 2625 * the lower 16 bits of each 32 bit multicast hash register are 2626 * valid). The high order bits select the register, while the 2627 * rest of the bits select the bit within the register. 2628 */ 2629 2630 memset(mchash, 0, sizeof(mchash)); 2631 2632 ETHER_FIRST_MULTI(step, ec, enm); 2633 while (enm != NULL) { 2634 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2635 /* 2636 * We must listen to a range of multicast addresses. 2637 * For now, just accept all multicasts, rather than 2638 * trying to set only those filter bits needed to match 2639 * the range. (At this time, the only use of address 2640 * ranges is for IP multicast routing, for which the 2641 * range is big enough to require all bits set.) 2642 */ 2643 goto allmulti; 2644 } 2645 2646 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2647 2648 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2649 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2650 /* Just want the 8 most significant bits. */ 2651 crc >>= 24; 2652 } else { 2653 /* Just want the 7 most significant bits. */ 2654 crc >>= 25; 2655 } 2656 2657 /* Set the corresponding bit in the hash table. */ 2658 mchash[crc >> 4] |= 1 << (crc & 0xf); 2659 2660 ETHER_NEXT_MULTI(step, enm); 2661 } 2662 2663 ifp->if_flags &= ~IFF_ALLMULTI; 2664 goto setit; 2665 2666 allmulti: 2667 ifp->if_flags |= IFF_ALLMULTI; 2668 sc->sc_rfcr |= RFCR_AAM; 2669 2670 setit: 2671 #define FILTER_EMIT(addr, data) \ 2672 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2673 delay(1); \ 2674 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2675 delay(1) 2676 2677 /* 2678 * Disable receive filter, and program the node address. 2679 */ 2680 cp = LLADDR(ifp->if_sadl); 2681 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2682 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2683 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2684 2685 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2686 /* 2687 * Program the multicast hash table. 2688 */ 2689 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2690 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2691 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2692 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2693 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2694 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2695 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2696 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2697 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2698 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2699 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2700 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2701 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2702 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2703 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2704 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2705 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2706 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2707 } 2708 } 2709 #undef FILTER_EMIT 2710 2711 /* 2712 * Re-enable the receiver filter. 2713 */ 2714 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2715 } 2716 #endif /* ! DP83820 */ 2717 2718 /* 2719 * sip_dp83815_set_filter: 2720 * 2721 * Set up the receive filter. 2722 */ 2723 void 2724 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2725 { 2726 bus_space_tag_t st = sc->sc_st; 2727 bus_space_handle_t sh = sc->sc_sh; 2728 struct ethercom *ec = &sc->sc_ethercom; 2729 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2730 struct ether_multi *enm; 2731 u_int8_t *cp; 2732 struct ether_multistep step; 2733 u_int32_t crc, hash, slot, bit; 2734 #ifdef DP83820 2735 #define MCHASH_NWORDS 128 2736 #else 2737 #define MCHASH_NWORDS 32 2738 #endif /* DP83820 */ 2739 u_int16_t mchash[MCHASH_NWORDS]; 2740 int i; 2741 2742 /* 2743 * Initialize the prototype RFCR. 2744 * Enable the receive filter, and accept on 2745 * Perfect (destination address) Match 2746 * If IFF_BROADCAST, also accept all broadcast packets. 2747 * If IFF_PROMISC, accept all unicast packets (and later, set 2748 * IFF_ALLMULTI and accept all multicast, too). 2749 */ 2750 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2751 if (ifp->if_flags & IFF_BROADCAST) 2752 sc->sc_rfcr |= RFCR_AAB; 2753 if (ifp->if_flags & IFF_PROMISC) { 2754 sc->sc_rfcr |= RFCR_AAP; 2755 goto allmulti; 2756 } 2757 2758 #ifdef DP83820 2759 /* 2760 * Set up the DP83820 multicast address filter by passing all multicast 2761 * addresses through a CRC generator, and then using the high-order 2762 * 11 bits as an index into the 2048 bit multicast hash table. The 2763 * high-order 7 bits select the slot, while the low-order 4 bits 2764 * select the bit within the slot. Note that only the low 16-bits 2765 * of each filter word are used, and there are 128 filter words. 2766 */ 2767 #else 2768 /* 2769 * Set up the DP83815 multicast address filter by passing all multicast 2770 * addresses through a CRC generator, and then using the high-order 2771 * 9 bits as an index into the 512 bit multicast hash table. The 2772 * high-order 5 bits select the slot, while the low-order 4 bits 2773 * select the bit within the slot. Note that only the low 16-bits 2774 * of each filter word are used, and there are 32 filter words. 2775 */ 2776 #endif /* DP83820 */ 2777 2778 memset(mchash, 0, sizeof(mchash)); 2779 2780 ifp->if_flags &= ~IFF_ALLMULTI; 2781 ETHER_FIRST_MULTI(step, ec, enm); 2782 if (enm == NULL) 2783 goto setit; 2784 while (enm != NULL) { 2785 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2786 /* 2787 * We must listen to a range of multicast addresses. 2788 * For now, just accept all multicasts, rather than 2789 * trying to set only those filter bits needed to match 2790 * the range. (At this time, the only use of address 2791 * ranges is for IP multicast routing, for which the 2792 * range is big enough to require all bits set.) 2793 */ 2794 goto allmulti; 2795 } 2796 2797 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2798 2799 #ifdef DP83820 2800 /* Just want the 11 most significant bits. */ 2801 hash = crc >> 21; 2802 #else 2803 /* Just want the 9 most significant bits. */ 2804 hash = crc >> 23; 2805 #endif /* DP83820 */ 2806 2807 slot = hash >> 4; 2808 bit = hash & 0xf; 2809 2810 /* Set the corresponding bit in the hash table. */ 2811 mchash[slot] |= 1 << bit; 2812 2813 ETHER_NEXT_MULTI(step, enm); 2814 } 2815 sc->sc_rfcr |= RFCR_MHEN; 2816 goto setit; 2817 2818 allmulti: 2819 ifp->if_flags |= IFF_ALLMULTI; 2820 sc->sc_rfcr |= RFCR_AAM; 2821 2822 setit: 2823 #define FILTER_EMIT(addr, data) \ 2824 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2825 delay(1); \ 2826 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2827 delay(1) 2828 2829 /* 2830 * Disable receive filter, and program the node address. 2831 */ 2832 cp = LLADDR(ifp->if_sadl); 2833 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 2834 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 2835 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 2836 2837 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2838 /* 2839 * Program the multicast hash table. 2840 */ 2841 for (i = 0; i < MCHASH_NWORDS; i++) { 2842 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 2843 mchash[i]); 2844 } 2845 } 2846 #undef FILTER_EMIT 2847 #undef MCHASH_NWORDS 2848 2849 /* 2850 * Re-enable the receiver filter. 2851 */ 2852 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2853 } 2854 2855 #if defined(DP83820) 2856 /* 2857 * sip_dp83820_mii_readreg: [mii interface function] 2858 * 2859 * Read a PHY register on the MII of the DP83820. 2860 */ 2861 int 2862 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 2863 { 2864 struct sip_softc *sc = (void *) self; 2865 2866 if (sc->sc_cfg & CFG_TBI_EN) { 2867 bus_addr_t tbireg; 2868 int rv; 2869 2870 if (phy != 0) 2871 return (0); 2872 2873 switch (reg) { 2874 case MII_BMCR: tbireg = SIP_TBICR; break; 2875 case MII_BMSR: tbireg = SIP_TBISR; break; 2876 case MII_ANAR: tbireg = SIP_TANAR; break; 2877 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 2878 case MII_ANER: tbireg = SIP_TANER; break; 2879 case MII_EXTSR: 2880 /* 2881 * Don't even bother reading the TESR register. 2882 * The manual documents that the device has 2883 * 1000baseX full/half capability, but the 2884 * register itself seems read back 0 on some 2885 * boards. Just hard-code the result. 2886 */ 2887 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 2888 2889 default: 2890 return (0); 2891 } 2892 2893 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 2894 if (tbireg == SIP_TBISR) { 2895 /* LINK and ACOMP are switched! */ 2896 int val = rv; 2897 2898 rv = 0; 2899 if (val & TBISR_MR_LINK_STATUS) 2900 rv |= BMSR_LINK; 2901 if (val & TBISR_MR_AN_COMPLETE) 2902 rv |= BMSR_ACOMP; 2903 2904 /* 2905 * The manual claims this register reads back 0 2906 * on hard and soft reset. But we want to let 2907 * the gentbi driver know that we support auto- 2908 * negotiation, so hard-code this bit in the 2909 * result. 2910 */ 2911 rv |= BMSR_ANEG | BMSR_EXTCAP; 2912 } 2913 2914 return (rv); 2915 } 2916 2917 return (mii_bitbang_readreg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2918 phy, reg)); 2919 } 2920 2921 /* 2922 * sip_dp83820_mii_writereg: [mii interface function] 2923 * 2924 * Write a PHY register on the MII of the DP83820. 2925 */ 2926 void 2927 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 2928 { 2929 struct sip_softc *sc = (void *) self; 2930 2931 if (sc->sc_cfg & CFG_TBI_EN) { 2932 bus_addr_t tbireg; 2933 2934 if (phy != 0) 2935 return; 2936 2937 switch (reg) { 2938 case MII_BMCR: tbireg = SIP_TBICR; break; 2939 case MII_ANAR: tbireg = SIP_TANAR; break; 2940 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 2941 default: 2942 return; 2943 } 2944 2945 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 2946 return; 2947 } 2948 2949 mii_bitbang_writereg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2950 phy, reg, val); 2951 } 2952 2953 /* 2954 * sip_dp83815_mii_statchg: [mii interface function] 2955 * 2956 * Callback from MII layer when media changes. 2957 */ 2958 void 2959 SIP_DECL(dp83820_mii_statchg)(struct device *self) 2960 { 2961 struct sip_softc *sc = (struct sip_softc *) self; 2962 u_int32_t cfg; 2963 2964 /* 2965 * Update TXCFG for full-duplex operation. 2966 */ 2967 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2968 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2969 else 2970 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2971 2972 /* 2973 * Update RXCFG for full-duplex or loopback. 2974 */ 2975 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2976 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2977 sc->sc_rxcfg |= RXCFG_ATX; 2978 else 2979 sc->sc_rxcfg &= ~RXCFG_ATX; 2980 2981 /* 2982 * Update CFG for MII/GMII. 2983 */ 2984 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2985 cfg = sc->sc_cfg | CFG_MODE_1000; 2986 else 2987 cfg = sc->sc_cfg; 2988 2989 /* 2990 * XXX 802.3x flow control. 2991 */ 2992 2993 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 2994 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2995 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 2996 } 2997 2998 /* 2999 * sip_dp83820_mii_bitbang_read: [mii bit-bang interface function] 3000 * 3001 * Read the MII serial port for the MII bit-bang module. 3002 */ 3003 u_int32_t 3004 SIP_DECL(dp83820_mii_bitbang_read)(struct device *self) 3005 { 3006 struct sip_softc *sc = (void *) self; 3007 3008 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3009 } 3010 3011 /* 3012 * sip_dp83820_mii_bitbang_write: [mii big-bang interface function] 3013 * 3014 * Write the MII serial port for the MII bit-bang module. 3015 */ 3016 void 3017 SIP_DECL(dp83820_mii_bitbang_write)(struct device *self, u_int32_t val) 3018 { 3019 struct sip_softc *sc = (void *) self; 3020 3021 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3022 } 3023 #else /* ! DP83820 */ 3024 /* 3025 * sip_sis900_mii_readreg: [mii interface function] 3026 * 3027 * Read a PHY register on the MII. 3028 */ 3029 int 3030 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 3031 { 3032 struct sip_softc *sc = (struct sip_softc *) self; 3033 u_int32_t enphy; 3034 3035 /* 3036 * The SiS 900 has only an internal PHY on the MII. Only allow 3037 * MII address 0. 3038 */ 3039 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 3040 sc->sc_rev < SIS_REV_635 && phy != 0) 3041 return (0); 3042 3043 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3044 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3045 ENPHY_RWCMD | ENPHY_ACCESS); 3046 do { 3047 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3048 } while (enphy & ENPHY_ACCESS); 3049 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3050 } 3051 3052 /* 3053 * sip_sis900_mii_writereg: [mii interface function] 3054 * 3055 * Write a PHY register on the MII. 3056 */ 3057 void 3058 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 3059 { 3060 struct sip_softc *sc = (struct sip_softc *) self; 3061 u_int32_t enphy; 3062 3063 /* 3064 * The SiS 900 has only an internal PHY on the MII. Only allow 3065 * MII address 0. 3066 */ 3067 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 3068 sc->sc_rev < SIS_REV_635 && phy != 0) 3069 return; 3070 3071 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3072 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3073 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3074 do { 3075 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3076 } while (enphy & ENPHY_ACCESS); 3077 } 3078 3079 /* 3080 * sip_sis900_mii_statchg: [mii interface function] 3081 * 3082 * Callback from MII layer when media changes. 3083 */ 3084 void 3085 SIP_DECL(sis900_mii_statchg)(struct device *self) 3086 { 3087 struct sip_softc *sc = (struct sip_softc *) self; 3088 u_int32_t flowctl; 3089 3090 /* 3091 * Update TXCFG for full-duplex operation. 3092 */ 3093 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3094 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3095 else 3096 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3097 3098 /* 3099 * Update RXCFG for full-duplex or loopback. 3100 */ 3101 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3102 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3103 sc->sc_rxcfg |= RXCFG_ATX; 3104 else 3105 sc->sc_rxcfg &= ~RXCFG_ATX; 3106 3107 /* 3108 * Update IMR for use of 802.3x flow control. 3109 */ 3110 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 3111 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3112 flowctl = FLOWCTL_FLOWEN; 3113 } else { 3114 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3115 flowctl = 0; 3116 } 3117 3118 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3119 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3120 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3121 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3122 } 3123 3124 /* 3125 * sip_dp83815_mii_readreg: [mii interface function] 3126 * 3127 * Read a PHY register on the MII. 3128 */ 3129 int 3130 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 3131 { 3132 struct sip_softc *sc = (struct sip_softc *) self; 3133 u_int32_t val; 3134 3135 /* 3136 * The DP83815 only has an internal PHY. Only allow 3137 * MII address 0. 3138 */ 3139 if (phy != 0) 3140 return (0); 3141 3142 /* 3143 * Apparently, after a reset, the DP83815 can take a while 3144 * to respond. During this recovery period, the BMSR returns 3145 * a value of 0. Catch this -- it's not supposed to happen 3146 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3147 * PHY to come back to life. 3148 * 3149 * This works out because the BMSR is the first register 3150 * read during the PHY probe process. 3151 */ 3152 do { 3153 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3154 } while (reg == MII_BMSR && val == 0); 3155 3156 return (val & 0xffff); 3157 } 3158 3159 /* 3160 * sip_dp83815_mii_writereg: [mii interface function] 3161 * 3162 * Write a PHY register to the MII. 3163 */ 3164 void 3165 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3166 { 3167 struct sip_softc *sc = (struct sip_softc *) self; 3168 3169 /* 3170 * The DP83815 only has an internal PHY. Only allow 3171 * MII address 0. 3172 */ 3173 if (phy != 0) 3174 return; 3175 3176 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3177 } 3178 3179 /* 3180 * sip_dp83815_mii_statchg: [mii interface function] 3181 * 3182 * Callback from MII layer when media changes. 3183 */ 3184 void 3185 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3186 { 3187 struct sip_softc *sc = (struct sip_softc *) self; 3188 3189 /* 3190 * Update TXCFG for full-duplex operation. 3191 */ 3192 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3193 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3194 else 3195 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3196 3197 /* 3198 * Update RXCFG for full-duplex or loopback. 3199 */ 3200 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3201 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3202 sc->sc_rxcfg |= RXCFG_ATX; 3203 else 3204 sc->sc_rxcfg &= ~RXCFG_ATX; 3205 3206 /* 3207 * XXX 802.3x flow control. 3208 */ 3209 3210 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3211 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3212 } 3213 #endif /* DP83820 */ 3214 3215 #if defined(DP83820) 3216 void 3217 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3218 const struct pci_attach_args *pa, u_int8_t *enaddr) 3219 { 3220 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3221 u_int8_t cksum, *e, match; 3222 int i; 3223 3224 /* 3225 * EEPROM data format for the DP83820 can be found in 3226 * the DP83820 manual, section 4.2.4. 3227 */ 3228 3229 SIP_DECL(read_eeprom)(sc, 0, 3230 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3231 3232 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3233 match = ~(match - 1); 3234 3235 cksum = 0x55; 3236 e = (u_int8_t *) eeprom_data; 3237 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3238 cksum += *e++; 3239 3240 if (cksum != match) 3241 printf("%s: Checksum (%x) mismatch (%x)", 3242 sc->sc_dev.dv_xname, cksum, match); 3243 3244 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3245 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3246 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3247 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3248 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3249 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3250 3251 /* Get the GPIOR bits. */ 3252 sc->sc_gpior = eeprom_data[0x04]; 3253 } 3254 #else /* ! DP83820 */ 3255 void 3256 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3257 const struct pci_attach_args *pa, u_int8_t *enaddr) 3258 { 3259 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3260 3261 switch (sc->sc_rev) { 3262 case SIS_REV_630S: 3263 case SIS_REV_630E: 3264 case SIS_REV_630EA1: 3265 case SIS_REV_630ET: 3266 case SIS_REV_635: 3267 /* 3268 * The MAC address for the on-board Ethernet of 3269 * the SiS 630 chipset is in the NVRAM. Kick 3270 * the chip into re-loading it from NVRAM, and 3271 * read the MAC address out of the filter registers. 3272 */ 3273 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3274 3275 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3276 RFCR_RFADDR_NODE0); 3277 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3278 0xffff; 3279 3280 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3281 RFCR_RFADDR_NODE2); 3282 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3283 0xffff; 3284 3285 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3286 RFCR_RFADDR_NODE4); 3287 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3288 0xffff; 3289 break; 3290 3291 default: 3292 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3293 sizeof(myea) / sizeof(myea[0]), myea); 3294 } 3295 3296 enaddr[0] = myea[0] & 0xff; 3297 enaddr[1] = myea[0] >> 8; 3298 enaddr[2] = myea[1] & 0xff; 3299 enaddr[3] = myea[1] >> 8; 3300 enaddr[4] = myea[2] & 0xff; 3301 enaddr[5] = myea[2] >> 8; 3302 } 3303 3304 /* Table and macro to bit-reverse an octet. */ 3305 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3306 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3307 3308 void 3309 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3310 const struct pci_attach_args *pa, u_int8_t *enaddr) 3311 { 3312 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3313 u_int8_t cksum, *e, match; 3314 int i; 3315 3316 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3317 sizeof(eeprom_data[0]), eeprom_data); 3318 3319 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3320 match = ~(match - 1); 3321 3322 cksum = 0x55; 3323 e = (u_int8_t *) eeprom_data; 3324 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3325 cksum += *e++; 3326 } 3327 if (cksum != match) { 3328 printf("%s: Checksum (%x) mismatch (%x)", 3329 sc->sc_dev.dv_xname, cksum, match); 3330 } 3331 3332 /* 3333 * Unrolled because it makes slightly more sense this way. 3334 * The DP83815 stores the MAC address in bit 0 of word 6 3335 * through bit 15 of word 8. 3336 */ 3337 ea = &eeprom_data[6]; 3338 enaddr[0] = ((*ea & 0x1) << 7); 3339 ea++; 3340 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3341 enaddr[1] = ((*ea & 0x1FE) >> 1); 3342 enaddr[2] = ((*ea & 0x1) << 7); 3343 ea++; 3344 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3345 enaddr[3] = ((*ea & 0x1FE) >> 1); 3346 enaddr[4] = ((*ea & 0x1) << 7); 3347 ea++; 3348 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3349 enaddr[5] = ((*ea & 0x1FE) >> 1); 3350 3351 /* 3352 * In case that's not weird enough, we also need to reverse 3353 * the bits in each byte. This all actually makes more sense 3354 * if you think about the EEPROM storage as an array of bits 3355 * being shifted into bytes, but that's not how we're looking 3356 * at it here... 3357 */ 3358 for (i = 0; i < 6 ;i++) 3359 enaddr[i] = bbr(enaddr[i]); 3360 } 3361 #endif /* DP83820 */ 3362 3363 /* 3364 * sip_mediastatus: [ifmedia interface function] 3365 * 3366 * Get the current interface media status. 3367 */ 3368 void 3369 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3370 { 3371 struct sip_softc *sc = ifp->if_softc; 3372 3373 mii_pollstat(&sc->sc_mii); 3374 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3375 ifmr->ifm_active = sc->sc_mii.mii_media_active; 3376 } 3377 3378 /* 3379 * sip_mediachange: [ifmedia interface function] 3380 * 3381 * Set hardware to newly-selected media. 3382 */ 3383 int 3384 SIP_DECL(mediachange)(struct ifnet *ifp) 3385 { 3386 struct sip_softc *sc = ifp->if_softc; 3387 3388 if (ifp->if_flags & IFF_UP) 3389 mii_mediachg(&sc->sc_mii); 3390 return (0); 3391 } 3392
Indexes created Tue Sep 30 11:09:46 GMT 2025