if_sip.c revision 1.68
1 /* $NetBSD: if_sip.c,v 1.68 2002/08/26 07:38:34 itojun Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.68 2002/08/26 07:38:34 itojun Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <machine/bus.h> 116 #include <machine/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #ifdef DP83820 122 #include <dev/mii/mii_bitbang.h> 123 #endif /* DP83820 */ 124 125 #include <dev/pci/pcireg.h> 126 #include <dev/pci/pcivar.h> 127 #include <dev/pci/pcidevs.h> 128 129 #include <dev/pci/if_sipreg.h> 130 131 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 132 #define SIP_DECL(x) __CONCAT(gsip_,x) 133 #else /* SiS900 and DP83815 */ 134 #define SIP_DECL(x) __CONCAT(sip_,x) 135 #endif 136 137 #define SIP_STR(x) __STRING(SIP_DECL(x)) 138 139 /* 140 * Transmit descriptor list size. This is arbitrary, but allocate 141 * enough descriptors for 128 pending transmissions, and 8 segments 142 * per packet. This MUST work out to a power of 2. 143 */ 144 #define SIP_NTXSEGS 16 145 #define SIP_NTXSEGS_ALLOC 8 146 147 #define SIP_TXQUEUELEN 256 148 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 149 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 150 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 151 152 #if defined(DP83020) 153 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 154 #else 155 #define TX_DMAMAP_SIZE MCLBYTES 156 #endif 157 158 /* 159 * Receive descriptor list size. We have one Rx buffer per incoming 160 * packet, so this logic is a little simpler. 161 * 162 * Actually, on the DP83820, we allow the packet to consume more than 163 * one buffer, in order to support jumbo Ethernet frames. In that 164 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 165 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 166 * so we'd better be quick about handling receive interrupts. 167 */ 168 #if defined(DP83820) 169 #define SIP_NRXDESC 256 170 #else 171 #define SIP_NRXDESC 128 172 #endif /* DP83820 */ 173 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 174 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 175 176 /* 177 * Control structures are DMA'd to the SiS900 chip. We allocate them in 178 * a single clump that maps to a single DMA segment to make several things 179 * easier. 180 */ 181 struct sip_control_data { 182 /* 183 * The transmit descriptors. 184 */ 185 struct sip_desc scd_txdescs[SIP_NTXDESC]; 186 187 /* 188 * The receive descriptors. 189 */ 190 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 191 }; 192 193 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 194 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 195 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 196 197 /* 198 * Software state for transmit jobs. 199 */ 200 struct sip_txsoft { 201 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 202 bus_dmamap_t txs_dmamap; /* our DMA map */ 203 int txs_firstdesc; /* first descriptor in packet */ 204 int txs_lastdesc; /* last descriptor in packet */ 205 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 206 }; 207 208 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 209 210 /* 211 * Software state for receive jobs. 212 */ 213 struct sip_rxsoft { 214 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 215 bus_dmamap_t rxs_dmamap; /* our DMA map */ 216 }; 217 218 /* 219 * Software state per device. 220 */ 221 struct sip_softc { 222 struct device sc_dev; /* generic device information */ 223 bus_space_tag_t sc_st; /* bus space tag */ 224 bus_space_handle_t sc_sh; /* bus space handle */ 225 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 226 struct ethercom sc_ethercom; /* ethernet common data */ 227 void *sc_sdhook; /* shutdown hook */ 228 229 const struct sip_product *sc_model; /* which model are we? */ 230 int sc_rev; /* chip revision */ 231 232 void *sc_ih; /* interrupt cookie */ 233 234 struct mii_data sc_mii; /* MII/media information */ 235 236 struct callout sc_tick_ch; /* tick callout */ 237 238 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 239 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 240 241 /* 242 * Software state for transmit and receive descriptors. 243 */ 244 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 245 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 246 247 /* 248 * Control data structures. 249 */ 250 struct sip_control_data *sc_control_data; 251 #define sc_txdescs sc_control_data->scd_txdescs 252 #define sc_rxdescs sc_control_data->scd_rxdescs 253 254 #ifdef SIP_EVENT_COUNTERS 255 /* 256 * Event counters. 257 */ 258 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 259 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 260 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 261 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 262 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 263 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 264 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 265 #ifdef DP83820 266 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 267 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 268 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 269 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 270 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 271 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 272 #endif /* DP83820 */ 273 #endif /* SIP_EVENT_COUNTERS */ 274 275 u_int32_t sc_txcfg; /* prototype TXCFG register */ 276 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 277 u_int32_t sc_imr; /* prototype IMR register */ 278 u_int32_t sc_rfcr; /* prototype RFCR register */ 279 280 u_int32_t sc_cfg; /* prototype CFG register */ 281 282 #ifdef DP83820 283 u_int32_t sc_gpior; /* prototype GPIOR register */ 284 #endif /* DP83820 */ 285 286 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 287 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 288 289 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 290 291 int sc_flags; /* misc. flags; see below */ 292 293 int sc_txfree; /* number of free Tx descriptors */ 294 int sc_txnext; /* next ready Tx descriptor */ 295 int sc_txwin; /* Tx descriptors since last intr */ 296 297 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 298 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 299 300 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 301 #if defined(DP83820) 302 int sc_rxdiscard; 303 int sc_rxlen; 304 struct mbuf *sc_rxhead; 305 struct mbuf *sc_rxtail; 306 struct mbuf **sc_rxtailp; 307 #endif /* DP83820 */ 308 309 #if NRND > 0 310 rndsource_element_t rnd_source; /* random source */ 311 #endif 312 }; 313 314 /* sc_flags */ 315 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 316 317 #ifdef DP83820 318 #define SIP_RXCHAIN_RESET(sc) \ 319 do { \ 320 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 321 *(sc)->sc_rxtailp = NULL; \ 322 (sc)->sc_rxlen = 0; \ 323 } while (/*CONSTCOND*/0) 324 325 #define SIP_RXCHAIN_LINK(sc, m) \ 326 do { \ 327 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 328 (sc)->sc_rxtailp = &(m)->m_next; \ 329 } while (/*CONSTCOND*/0) 330 #endif /* DP83820 */ 331 332 #ifdef SIP_EVENT_COUNTERS 333 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 334 #else 335 #define SIP_EVCNT_INCR(ev) /* nothing */ 336 #endif 337 338 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 339 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 340 341 #define SIP_CDTXSYNC(sc, x, n, ops) \ 342 do { \ 343 int __x, __n; \ 344 \ 345 __x = (x); \ 346 __n = (n); \ 347 \ 348 /* If it will wrap around, sync to the end of the ring. */ \ 349 if ((__x + __n) > SIP_NTXDESC) { \ 350 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 351 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 352 (SIP_NTXDESC - __x), (ops)); \ 353 __n -= (SIP_NTXDESC - __x); \ 354 __x = 0; \ 355 } \ 356 \ 357 /* Now sync whatever is left. */ \ 358 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 359 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 360 } while (0) 361 362 #define SIP_CDRXSYNC(sc, x, ops) \ 363 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 364 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 365 366 #ifdef DP83820 367 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 368 #define SIP_RXBUF_LEN (MCLBYTES - 4) 369 #else 370 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 371 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 372 #endif 373 #define SIP_INIT_RXDESC(sc, x) \ 374 do { \ 375 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 376 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 377 \ 378 __sipd->sipd_link = \ 379 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 380 __sipd->sipd_bufptr = \ 381 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 382 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 383 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 384 SIP_INIT_RXDESC_EXTSTS \ 385 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 386 } while (0) 387 388 #define SIP_CHIP_VERS(sc, v, p, r) \ 389 ((sc)->sc_model->sip_vendor == (v) && \ 390 (sc)->sc_model->sip_product == (p) && \ 391 (sc)->sc_rev == (r)) 392 393 #define SIP_CHIP_MODEL(sc, v, p) \ 394 ((sc)->sc_model->sip_vendor == (v) && \ 395 (sc)->sc_model->sip_product == (p)) 396 397 #if !defined(DP83820) 398 #define SIP_SIS900_REV(sc, rev) \ 399 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 400 #endif 401 402 #define SIP_TIMEOUT 1000 403 404 void SIP_DECL(start)(struct ifnet *); 405 void SIP_DECL(watchdog)(struct ifnet *); 406 int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 407 int SIP_DECL(init)(struct ifnet *); 408 void SIP_DECL(stop)(struct ifnet *, int); 409 410 void SIP_DECL(shutdown)(void *); 411 412 void SIP_DECL(reset)(struct sip_softc *); 413 void SIP_DECL(rxdrain)(struct sip_softc *); 414 int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 415 void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, u_int16_t *); 416 void SIP_DECL(tick)(void *); 417 418 #if !defined(DP83820) 419 void SIP_DECL(sis900_set_filter)(struct sip_softc *); 420 #endif /* ! DP83820 */ 421 void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 422 423 #if defined(DP83820) 424 void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 425 const struct pci_attach_args *, u_int8_t *); 426 #else 427 void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 428 const struct pci_attach_args *, u_int8_t *); 429 void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 430 const struct pci_attach_args *, u_int8_t *); 431 #endif /* DP83820 */ 432 433 int SIP_DECL(intr)(void *); 434 void SIP_DECL(txintr)(struct sip_softc *); 435 void SIP_DECL(rxintr)(struct sip_softc *); 436 437 #if defined(DP83820) 438 int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 439 void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 440 void SIP_DECL(dp83820_mii_statchg)(struct device *); 441 #else 442 int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 443 void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 444 void SIP_DECL(sis900_mii_statchg)(struct device *); 445 446 int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 447 void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 448 void SIP_DECL(dp83815_mii_statchg)(struct device *); 449 #endif /* DP83820 */ 450 451 int SIP_DECL(mediachange)(struct ifnet *); 452 void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 453 454 int SIP_DECL(match)(struct device *, struct cfdata *, void *); 455 void SIP_DECL(attach)(struct device *, struct device *, void *); 456 457 int SIP_DECL(copy_small) = 0; 458 459 struct cfattach SIP_DECL(ca) = { 460 sizeof(struct sip_softc), SIP_DECL(match), SIP_DECL(attach), 461 }; 462 463 /* 464 * Descriptions of the variants of the SiS900. 465 */ 466 struct sip_variant { 467 int (*sipv_mii_readreg)(struct device *, int, int); 468 void (*sipv_mii_writereg)(struct device *, int, int, int); 469 void (*sipv_mii_statchg)(struct device *); 470 void (*sipv_set_filter)(struct sip_softc *); 471 void (*sipv_read_macaddr)(struct sip_softc *, 472 const struct pci_attach_args *, u_int8_t *); 473 }; 474 475 #if defined(DP83820) 476 u_int32_t SIP_DECL(dp83820_mii_bitbang_read)(struct device *); 477 void SIP_DECL(dp83820_mii_bitbang_write)(struct device *, u_int32_t); 478 479 const struct mii_bitbang_ops SIP_DECL(dp83820_mii_bitbang_ops) = { 480 SIP_DECL(dp83820_mii_bitbang_read), 481 SIP_DECL(dp83820_mii_bitbang_write), 482 { 483 EROMAR_MDIO, /* MII_BIT_MDO */ 484 EROMAR_MDIO, /* MII_BIT_MDI */ 485 EROMAR_MDC, /* MII_BIT_MDC */ 486 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 487 0, /* MII_BIT_DIR_PHY_HOST */ 488 } 489 }; 490 #endif /* DP83820 */ 491 492 #if defined(DP83820) 493 const struct sip_variant SIP_DECL(variant_dp83820) = { 494 SIP_DECL(dp83820_mii_readreg), 495 SIP_DECL(dp83820_mii_writereg), 496 SIP_DECL(dp83820_mii_statchg), 497 SIP_DECL(dp83815_set_filter), 498 SIP_DECL(dp83820_read_macaddr), 499 }; 500 #else 501 const struct sip_variant SIP_DECL(variant_sis900) = { 502 SIP_DECL(sis900_mii_readreg), 503 SIP_DECL(sis900_mii_writereg), 504 SIP_DECL(sis900_mii_statchg), 505 SIP_DECL(sis900_set_filter), 506 SIP_DECL(sis900_read_macaddr), 507 }; 508 509 const struct sip_variant SIP_DECL(variant_dp83815) = { 510 SIP_DECL(dp83815_mii_readreg), 511 SIP_DECL(dp83815_mii_writereg), 512 SIP_DECL(dp83815_mii_statchg), 513 SIP_DECL(dp83815_set_filter), 514 SIP_DECL(dp83815_read_macaddr), 515 }; 516 #endif /* DP83820 */ 517 518 /* 519 * Devices supported by this driver. 520 */ 521 const struct sip_product { 522 pci_vendor_id_t sip_vendor; 523 pci_product_id_t sip_product; 524 const char *sip_name; 525 const struct sip_variant *sip_variant; 526 } SIP_DECL(products)[] = { 527 #if defined(DP83820) 528 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 529 "NatSemi DP83820 Gigabit Ethernet", 530 &SIP_DECL(variant_dp83820) }, 531 #else 532 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 533 "SiS 900 10/100 Ethernet", 534 &SIP_DECL(variant_sis900) }, 535 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 536 "SiS 7016 10/100 Ethernet", 537 &SIP_DECL(variant_sis900) }, 538 539 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 540 "NatSemi DP83815 10/100 Ethernet", 541 &SIP_DECL(variant_dp83815) }, 542 #endif /* DP83820 */ 543 544 { 0, 0, 545 NULL, 546 NULL }, 547 }; 548 549 static const struct sip_product * 550 SIP_DECL(lookup)(const struct pci_attach_args *pa) 551 { 552 const struct sip_product *sip; 553 554 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 555 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 556 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 557 return (sip); 558 } 559 return (NULL); 560 } 561 562 #ifdef DP83820 563 /* 564 * I really hate stupid hardware vendors. There's a bit in the EEPROM 565 * which indicates if the card can do 64-bit data transfers. Unfortunately, 566 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 567 * which means we try to use 64-bit data transfers on those cards if we 568 * happen to be plugged into a 32-bit slot. 569 * 570 * What we do is use this table of cards known to be 64-bit cards. If 571 * you have a 64-bit card who's subsystem ID is not listed in this table, 572 * send the output of "pcictl dump ..." of the device to me so that your 573 * card will use the 64-bit data path when plugged into a 64-bit slot. 574 * 575 * -- Jason R. Thorpe <thorpej (at) netbsd.org> 576 * June 30, 2002 577 */ 578 static int 579 SIP_DECL(check_64bit)(const struct pci_attach_args *pa) 580 { 581 static const struct { 582 pci_vendor_id_t c64_vendor; 583 pci_product_id_t c64_product; 584 } card64[] = { 585 /* Asante GigaNIX */ 586 { 0x128a, 0x0002 }, 587 588 /* Accton EN1407-T, Planex GN-1000TE */ 589 { 0x1113, 0x1407 }, 590 591 { 0, 0} 592 }; 593 pcireg_t subsys; 594 int i; 595 596 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 597 598 for (i = 0; card64[i].c64_vendor != 0; i++) { 599 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 600 PCI_PRODUCT(subsys) == card64[i].c64_product) 601 return (1); 602 } 603 604 return (0); 605 } 606 #endif /* DP83820 */ 607 608 int 609 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 610 { 611 struct pci_attach_args *pa = aux; 612 613 if (SIP_DECL(lookup)(pa) != NULL) 614 return (1); 615 616 return (0); 617 } 618 619 void 620 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 621 { 622 struct sip_softc *sc = (struct sip_softc *) self; 623 struct pci_attach_args *pa = aux; 624 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 625 pci_chipset_tag_t pc = pa->pa_pc; 626 pci_intr_handle_t ih; 627 const char *intrstr = NULL; 628 bus_space_tag_t iot, memt; 629 bus_space_handle_t ioh, memh; 630 bus_dma_segment_t seg; 631 int ioh_valid, memh_valid; 632 int i, rseg, error; 633 const struct sip_product *sip; 634 pcireg_t pmode; 635 u_int8_t enaddr[ETHER_ADDR_LEN]; 636 int pmreg; 637 #ifdef DP83820 638 pcireg_t memtype; 639 u_int32_t reg; 640 #endif /* DP83820 */ 641 642 callout_init(&sc->sc_tick_ch); 643 644 sip = SIP_DECL(lookup)(pa); 645 if (sip == NULL) { 646 printf("\n"); 647 panic(SIP_STR(attach) ": impossible"); 648 } 649 sc->sc_rev = PCI_REVISION(pa->pa_class); 650 651 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 652 653 sc->sc_model = sip; 654 655 /* 656 * XXX Work-around broken PXE firmware on some boards. 657 * 658 * The DP83815 shares an address decoder with the MEM BAR 659 * and the ROM BAR. Make sure the ROM BAR is disabled, 660 * so that memory mapped access works. 661 */ 662 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 663 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 664 ~PCI_MAPREG_ROM_ENABLE); 665 666 /* 667 * Map the device. 668 */ 669 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 670 PCI_MAPREG_TYPE_IO, 0, 671 &iot, &ioh, NULL, NULL) == 0); 672 #ifdef DP83820 673 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 674 switch (memtype) { 675 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 676 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 677 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 678 memtype, 0, &memt, &memh, NULL, NULL) == 0); 679 break; 680 default: 681 memh_valid = 0; 682 } 683 #else 684 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 685 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 686 &memt, &memh, NULL, NULL) == 0); 687 #endif /* DP83820 */ 688 689 if (memh_valid) { 690 sc->sc_st = memt; 691 sc->sc_sh = memh; 692 } else if (ioh_valid) { 693 sc->sc_st = iot; 694 sc->sc_sh = ioh; 695 } else { 696 printf("%s: unable to map device registers\n", 697 sc->sc_dev.dv_xname); 698 return; 699 } 700 701 sc->sc_dmat = pa->pa_dmat; 702 703 /* 704 * Make sure bus mastering is enabled. Also make sure 705 * Write/Invalidate is enabled if we're allowed to use it. 706 */ 707 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 708 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 709 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 710 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 711 pmreg | PCI_COMMAND_MASTER_ENABLE); 712 713 /* Get it out of power save mode if needed. */ 714 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 715 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 716 if (pmode == 3) { 717 /* 718 * The card has lost all configuration data in 719 * this state, so punt. 720 */ 721 printf("%s: unable to wake up from power state D3\n", 722 sc->sc_dev.dv_xname); 723 return; 724 } 725 if (pmode != 0) { 726 printf("%s: waking up from power state D%d\n", 727 sc->sc_dev.dv_xname, pmode); 728 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 729 } 730 } 731 732 /* 733 * Map and establish our interrupt. 734 */ 735 if (pci_intr_map(pa, &ih)) { 736 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 737 return; 738 } 739 intrstr = pci_intr_string(pc, ih); 740 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 741 if (sc->sc_ih == NULL) { 742 printf("%s: unable to establish interrupt", 743 sc->sc_dev.dv_xname); 744 if (intrstr != NULL) 745 printf(" at %s", intrstr); 746 printf("\n"); 747 return; 748 } 749 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 750 751 SIMPLEQ_INIT(&sc->sc_txfreeq); 752 SIMPLEQ_INIT(&sc->sc_txdirtyq); 753 754 /* 755 * Allocate the control data structures, and create and load the 756 * DMA map for it. 757 */ 758 if ((error = bus_dmamem_alloc(sc->sc_dmat, 759 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 760 0)) != 0) { 761 printf("%s: unable to allocate control data, error = %d\n", 762 sc->sc_dev.dv_xname, error); 763 goto fail_0; 764 } 765 766 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 767 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 768 BUS_DMA_COHERENT)) != 0) { 769 printf("%s: unable to map control data, error = %d\n", 770 sc->sc_dev.dv_xname, error); 771 goto fail_1; 772 } 773 774 if ((error = bus_dmamap_create(sc->sc_dmat, 775 sizeof(struct sip_control_data), 1, 776 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 777 printf("%s: unable to create control data DMA map, " 778 "error = %d\n", sc->sc_dev.dv_xname, error); 779 goto fail_2; 780 } 781 782 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 783 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 784 0)) != 0) { 785 printf("%s: unable to load control data DMA map, error = %d\n", 786 sc->sc_dev.dv_xname, error); 787 goto fail_3; 788 } 789 790 /* 791 * Create the transmit buffer DMA maps. 792 */ 793 for (i = 0; i < SIP_TXQUEUELEN; i++) { 794 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 795 SIP_NTXSEGS, MCLBYTES, 0, 0, 796 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 797 printf("%s: unable to create tx DMA map %d, " 798 "error = %d\n", sc->sc_dev.dv_xname, i, error); 799 goto fail_4; 800 } 801 } 802 803 /* 804 * Create the receive buffer DMA maps. 805 */ 806 for (i = 0; i < SIP_NRXDESC; i++) { 807 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 808 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 809 printf("%s: unable to create rx DMA map %d, " 810 "error = %d\n", sc->sc_dev.dv_xname, i, error); 811 goto fail_5; 812 } 813 sc->sc_rxsoft[i].rxs_mbuf = NULL; 814 } 815 816 /* 817 * Reset the chip to a known state. 818 */ 819 SIP_DECL(reset)(sc); 820 821 /* 822 * Read the Ethernet address from the EEPROM. This might 823 * also fetch other stuff from the EEPROM and stash it 824 * in the softc. 825 */ 826 sc->sc_cfg = 0; 827 #if !defined(DP83820) 828 if (SIP_SIS900_REV(sc,SIS_REV_635) || 829 SIP_SIS900_REV(sc,SIS_REV_900B)) 830 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 831 #endif 832 833 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 834 835 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 836 ether_sprintf(enaddr)); 837 838 /* 839 * Initialize the configuration register: aggressive PCI 840 * bus request algorithm, default backoff, default OW timer, 841 * default parity error detection. 842 * 843 * NOTE: "Big endian mode" is useless on the SiS900 and 844 * friends -- it affects packet data, not descriptors. 845 */ 846 #ifdef DP83820 847 /* 848 * Cause the chip to load configuration data from the EEPROM. 849 */ 850 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 851 for (i = 0; i < 10000; i++) { 852 delay(10); 853 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 854 PTSCR_EELOAD_EN) == 0) 855 break; 856 } 857 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 858 PTSCR_EELOAD_EN) { 859 printf("%s: timeout loading configuration from EEPROM\n", 860 sc->sc_dev.dv_xname); 861 return; 862 } 863 864 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 865 if (reg & CFG_PCI64_DET) { 866 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 867 /* 868 * Check to see if this card is 64-bit. If so, enable 64-bit 869 * data transfers. 870 * 871 * We can't use the DATA64_EN bit in the EEPROM, because 872 * vendors of 32-bit cards fail to clear that bit in many 873 * cases (yet the card still detects that it's in a 64-bit 874 * slot; go figure). 875 */ 876 if (SIP_DECL(check_64bit)(pa)) { 877 sc->sc_cfg |= CFG_DATA64_EN; 878 printf(", using 64-bit data transfers"); 879 } 880 printf("\n"); 881 } 882 883 /* 884 * XXX Need some PCI flags indicating support for 885 * XXX 64-bit addressing. 886 */ 887 #if 0 888 if (reg & CFG_M64ADDR) 889 sc->sc_cfg |= CFG_M64ADDR; 890 if (reg & CFG_T64ADDR) 891 sc->sc_cfg |= CFG_T64ADDR; 892 #endif 893 894 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 895 const char *sep = ""; 896 printf("%s: using ", sc->sc_dev.dv_xname); 897 if (reg & CFG_EXT_125) { 898 sc->sc_cfg |= CFG_EXT_125; 899 printf("%s125MHz clock", sep); 900 sep = ", "; 901 } 902 if (reg & CFG_TBI_EN) { 903 sc->sc_cfg |= CFG_TBI_EN; 904 printf("%sten-bit interface", sep); 905 sep = ", "; 906 } 907 printf("\n"); 908 } 909 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 910 (reg & CFG_MRM_DIS) != 0) 911 sc->sc_cfg |= CFG_MRM_DIS; 912 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 913 (reg & CFG_MWI_DIS) != 0) 914 sc->sc_cfg |= CFG_MWI_DIS; 915 916 /* 917 * Use the extended descriptor format on the DP83820. This 918 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 919 * checksumming. 920 */ 921 sc->sc_cfg |= CFG_EXTSTS_EN; 922 #endif /* DP83820 */ 923 924 /* 925 * Initialize our media structures and probe the MII. 926 */ 927 sc->sc_mii.mii_ifp = ifp; 928 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 929 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 930 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 931 ifmedia_init(&sc->sc_mii.mii_media, 0, SIP_DECL(mediachange), 932 SIP_DECL(mediastatus)); 933 934 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 935 MII_OFFSET_ANY, 0); 936 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 937 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 938 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 939 } else 940 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 941 942 ifp = &sc->sc_ethercom.ec_if; 943 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 944 ifp->if_softc = sc; 945 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 946 ifp->if_ioctl = SIP_DECL(ioctl); 947 ifp->if_start = SIP_DECL(start); 948 ifp->if_watchdog = SIP_DECL(watchdog); 949 ifp->if_init = SIP_DECL(init); 950 ifp->if_stop = SIP_DECL(stop); 951 IFQ_SET_READY(&ifp->if_snd); 952 953 /* 954 * We can support 802.1Q VLAN-sized frames. 955 */ 956 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 957 958 #ifdef DP83820 959 /* 960 * And the DP83820 can do VLAN tagging in hardware, and 961 * support the jumbo Ethernet MTU. 962 */ 963 sc->sc_ethercom.ec_capabilities |= 964 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 965 966 /* 967 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 968 * in hardware. 969 */ 970 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 971 IFCAP_CSUM_UDPv4; 972 #endif /* DP83820 */ 973 974 /* 975 * Attach the interface. 976 */ 977 if_attach(ifp); 978 ether_ifattach(ifp, enaddr); 979 #if NRND > 0 980 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 981 RND_TYPE_NET, 0); 982 #endif 983 984 /* 985 * The number of bytes that must be available in 986 * the Tx FIFO before the bus master can DMA more 987 * data into the FIFO. 988 */ 989 sc->sc_tx_fill_thresh = 64 / 32; 990 991 /* 992 * Start at a drain threshold of 512 bytes. We will 993 * increase it if a DMA underrun occurs. 994 * 995 * XXX The minimum value of this variable should be 996 * tuned. We may be able to improve performance 997 * by starting with a lower value. That, however, 998 * may trash the first few outgoing packets if the 999 * PCI bus is saturated. 1000 */ 1001 sc->sc_tx_drain_thresh = 1504 / 32; 1002 1003 /* 1004 * Initialize the Rx FIFO drain threshold. 1005 * 1006 * This is in units of 8 bytes. 1007 * 1008 * We should never set this value lower than 2; 14 bytes are 1009 * required to filter the packet. 1010 */ 1011 sc->sc_rx_drain_thresh = 128 / 8; 1012 1013 #ifdef SIP_EVENT_COUNTERS 1014 /* 1015 * Attach event counters. 1016 */ 1017 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1018 NULL, sc->sc_dev.dv_xname, "txsstall"); 1019 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1020 NULL, sc->sc_dev.dv_xname, "txdstall"); 1021 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1022 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1023 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1024 NULL, sc->sc_dev.dv_xname, "txdintr"); 1025 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1026 NULL, sc->sc_dev.dv_xname, "txiintr"); 1027 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1028 NULL, sc->sc_dev.dv_xname, "rxintr"); 1029 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1030 NULL, sc->sc_dev.dv_xname, "hiberr"); 1031 #ifdef DP83820 1032 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1033 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1034 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1035 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1036 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1037 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1038 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1039 NULL, sc->sc_dev.dv_xname, "txipsum"); 1040 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1041 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1042 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1043 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1044 #endif /* DP83820 */ 1045 #endif /* SIP_EVENT_COUNTERS */ 1046 1047 /* 1048 * Make sure the interface is shutdown during reboot. 1049 */ 1050 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 1051 if (sc->sc_sdhook == NULL) 1052 printf("%s: WARNING: unable to establish shutdown hook\n", 1053 sc->sc_dev.dv_xname); 1054 return; 1055 1056 /* 1057 * Free any resources we've allocated during the failed attach 1058 * attempt. Do this in reverse order and fall through. 1059 */ 1060 fail_5: 1061 for (i = 0; i < SIP_NRXDESC; i++) { 1062 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1063 bus_dmamap_destroy(sc->sc_dmat, 1064 sc->sc_rxsoft[i].rxs_dmamap); 1065 } 1066 fail_4: 1067 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1068 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1069 bus_dmamap_destroy(sc->sc_dmat, 1070 sc->sc_txsoft[i].txs_dmamap); 1071 } 1072 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1073 fail_3: 1074 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1075 fail_2: 1076 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1077 sizeof(struct sip_control_data)); 1078 fail_1: 1079 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1080 fail_0: 1081 return; 1082 } 1083 1084 /* 1085 * sip_shutdown: 1086 * 1087 * Make sure the interface is stopped at reboot time. 1088 */ 1089 void 1090 SIP_DECL(shutdown)(void *arg) 1091 { 1092 struct sip_softc *sc = arg; 1093 1094 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1095 } 1096 1097 /* 1098 * sip_start: [ifnet interface function] 1099 * 1100 * Start packet transmission on the interface. 1101 */ 1102 void 1103 SIP_DECL(start)(struct ifnet *ifp) 1104 { 1105 struct sip_softc *sc = ifp->if_softc; 1106 struct mbuf *m0, *m; 1107 struct sip_txsoft *txs; 1108 bus_dmamap_t dmamap; 1109 int error, nexttx, lasttx, seg; 1110 int ofree = sc->sc_txfree; 1111 #if 0 1112 int firsttx = sc->sc_txnext; 1113 #endif 1114 #ifdef DP83820 1115 u_int32_t extsts; 1116 #endif 1117 1118 /* 1119 * If we've been told to pause, don't transmit any more packets. 1120 */ 1121 if (sc->sc_flags & SIPF_PAUSED) 1122 ifp->if_flags |= IFF_OACTIVE; 1123 1124 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1125 return; 1126 1127 /* 1128 * Loop through the send queue, setting up transmit descriptors 1129 * until we drain the queue, or use up all available transmit 1130 * descriptors. 1131 */ 1132 for (;;) { 1133 /* Get a work queue entry. */ 1134 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1135 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1136 break; 1137 } 1138 1139 /* 1140 * Grab a packet off the queue. 1141 */ 1142 IFQ_POLL(&ifp->if_snd, m0); 1143 if (m0 == NULL) 1144 break; 1145 #ifndef DP83820 1146 m = NULL; 1147 #endif 1148 1149 dmamap = txs->txs_dmamap; 1150 1151 #ifdef DP83820 1152 /* 1153 * Load the DMA map. If this fails, the packet either 1154 * didn't fit in the allotted number of segments, or we 1155 * were short on resources. For the too-many-segments 1156 * case, we simply report an error and drop the packet, 1157 * since we can't sanely copy a jumbo packet to a single 1158 * buffer. 1159 */ 1160 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1161 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1162 if (error) { 1163 if (error == EFBIG) { 1164 printf("%s: Tx packet consumes too many " 1165 "DMA segments, dropping...\n", 1166 sc->sc_dev.dv_xname); 1167 IFQ_DEQUEUE(&ifp->if_snd, m0); 1168 m_freem(m0); 1169 continue; 1170 } 1171 /* 1172 * Short on resources, just stop for now. 1173 */ 1174 break; 1175 } 1176 #else /* DP83820 */ 1177 /* 1178 * Load the DMA map. If this fails, the packet either 1179 * didn't fit in the alloted number of segments, or we 1180 * were short on resources. In this case, we'll copy 1181 * and try again. 1182 */ 1183 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1184 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1185 MGETHDR(m, M_DONTWAIT, MT_DATA); 1186 if (m == NULL) { 1187 printf("%s: unable to allocate Tx mbuf\n", 1188 sc->sc_dev.dv_xname); 1189 break; 1190 } 1191 if (m0->m_pkthdr.len > MHLEN) { 1192 MCLGET(m, M_DONTWAIT); 1193 if ((m->m_flags & M_EXT) == 0) { 1194 printf("%s: unable to allocate Tx " 1195 "cluster\n", sc->sc_dev.dv_xname); 1196 m_freem(m); 1197 break; 1198 } 1199 } 1200 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1201 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1202 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1203 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1204 if (error) { 1205 printf("%s: unable to load Tx buffer, " 1206 "error = %d\n", sc->sc_dev.dv_xname, error); 1207 break; 1208 } 1209 } 1210 #endif /* DP83820 */ 1211 1212 /* 1213 * Ensure we have enough descriptors free to describe 1214 * the packet. Note, we always reserve one descriptor 1215 * at the end of the ring as a termination point, to 1216 * prevent wrap-around. 1217 */ 1218 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1219 /* 1220 * Not enough free descriptors to transmit this 1221 * packet. We haven't committed anything yet, 1222 * so just unload the DMA map, put the packet 1223 * back on the queue, and punt. Notify the upper 1224 * layer that there are not more slots left. 1225 * 1226 * XXX We could allocate an mbuf and copy, but 1227 * XXX is it worth it? 1228 */ 1229 ifp->if_flags |= IFF_OACTIVE; 1230 bus_dmamap_unload(sc->sc_dmat, dmamap); 1231 #ifndef DP83820 1232 if (m != NULL) 1233 m_freem(m); 1234 #endif 1235 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1236 break; 1237 } 1238 1239 IFQ_DEQUEUE(&ifp->if_snd, m0); 1240 #ifndef DP83820 1241 if (m != NULL) { 1242 m_freem(m0); 1243 m0 = m; 1244 } 1245 #endif 1246 1247 /* 1248 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1249 */ 1250 1251 /* Sync the DMA map. */ 1252 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1253 BUS_DMASYNC_PREWRITE); 1254 1255 /* 1256 * Initialize the transmit descriptors. 1257 */ 1258 for (nexttx = sc->sc_txnext, seg = 0; 1259 seg < dmamap->dm_nsegs; 1260 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1261 /* 1262 * If this is the first descriptor we're 1263 * enqueueing, don't set the OWN bit just 1264 * yet. That could cause a race condition. 1265 * We'll do it below. 1266 */ 1267 sc->sc_txdescs[nexttx].sipd_bufptr = 1268 htole32(dmamap->dm_segs[seg].ds_addr); 1269 sc->sc_txdescs[nexttx].sipd_cmdsts = 1270 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1271 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1272 #ifdef DP83820 1273 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1274 #endif /* DP83820 */ 1275 lasttx = nexttx; 1276 } 1277 1278 /* Clear the MORE bit on the last segment. */ 1279 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1280 1281 /* 1282 * If we're in the interrupt delay window, delay the 1283 * interrupt. 1284 */ 1285 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1286 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1287 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1288 htole32(CMDSTS_INTR); 1289 sc->sc_txwin = 0; 1290 } 1291 1292 #ifdef DP83820 1293 /* 1294 * If VLANs are enabled and the packet has a VLAN tag, set 1295 * up the descriptor to encapsulate the packet for us. 1296 * 1297 * This apparently has to be on the last descriptor of 1298 * the packet. 1299 */ 1300 if (sc->sc_ethercom.ec_nvlans != 0 && 1301 (m = m_aux_find(m0, AF_LINK, ETHERTYPE_VLAN)) != NULL) { 1302 sc->sc_txdescs[lasttx].sipd_extsts |= 1303 htole32(EXTSTS_VPKT | 1304 htons(*mtod(m, int *) & EXTSTS_VTCI)); 1305 } 1306 1307 /* 1308 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1309 * checksumming, set up the descriptor to do this work 1310 * for us. 1311 * 1312 * This apparently has to be on the first descriptor of 1313 * the packet. 1314 * 1315 * Byte-swap constants so the compiler can optimize. 1316 */ 1317 extsts = 0; 1318 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1319 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1320 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1321 extsts |= htole32(EXTSTS_IPPKT); 1322 } 1323 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1324 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1325 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1326 extsts |= htole32(EXTSTS_TCPPKT); 1327 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1328 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1329 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1330 extsts |= htole32(EXTSTS_UDPPKT); 1331 } 1332 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1333 #endif /* DP83820 */ 1334 1335 /* Sync the descriptors we're using. */ 1336 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1337 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1338 1339 /* 1340 * The entire packet is set up. Give the first descrptor 1341 * to the chip now. 1342 */ 1343 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1344 htole32(CMDSTS_OWN); 1345 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1346 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1347 1348 /* 1349 * Store a pointer to the packet so we can free it later, 1350 * and remember what txdirty will be once the packet is 1351 * done. 1352 */ 1353 txs->txs_mbuf = m0; 1354 txs->txs_firstdesc = sc->sc_txnext; 1355 txs->txs_lastdesc = lasttx; 1356 1357 /* Advance the tx pointer. */ 1358 sc->sc_txfree -= dmamap->dm_nsegs; 1359 sc->sc_txnext = nexttx; 1360 1361 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1362 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1363 1364 #if NBPFILTER > 0 1365 /* 1366 * Pass the packet to any BPF listeners. 1367 */ 1368 if (ifp->if_bpf) 1369 bpf_mtap(ifp->if_bpf, m0); 1370 #endif /* NBPFILTER > 0 */ 1371 } 1372 1373 if (txs == NULL || sc->sc_txfree == 0) { 1374 /* No more slots left; notify upper layer. */ 1375 ifp->if_flags |= IFF_OACTIVE; 1376 } 1377 1378 if (sc->sc_txfree != ofree) { 1379 /* 1380 * Start the transmit process. Note, the manual says 1381 * that if there are no pending transmissions in the 1382 * chip's internal queue (indicated by TXE being clear), 1383 * then the driver software must set the TXDP to the 1384 * first descriptor to be transmitted. However, if we 1385 * do this, it causes serious performance degredation on 1386 * the DP83820 under load, not setting TXDP doesn't seem 1387 * to adversely affect the SiS 900 or DP83815. 1388 * 1389 * Well, I guess it wouldn't be the first time a manual 1390 * has lied -- and they could be speaking of the NULL- 1391 * terminated descriptor list case, rather than OWN- 1392 * terminated rings. 1393 */ 1394 #if 0 1395 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1396 CR_TXE) == 0) { 1397 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1398 SIP_CDTXADDR(sc, firsttx)); 1399 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1400 } 1401 #else 1402 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1403 #endif 1404 1405 /* Set a watchdog timer in case the chip flakes out. */ 1406 ifp->if_timer = 5; 1407 } 1408 } 1409 1410 /* 1411 * sip_watchdog: [ifnet interface function] 1412 * 1413 * Watchdog timer handler. 1414 */ 1415 void 1416 SIP_DECL(watchdog)(struct ifnet *ifp) 1417 { 1418 struct sip_softc *sc = ifp->if_softc; 1419 1420 /* 1421 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1422 * If we get a timeout, try and sweep up transmit descriptors. 1423 * If we manage to sweep them all up, ignore the lack of 1424 * interrupt. 1425 */ 1426 SIP_DECL(txintr)(sc); 1427 1428 if (sc->sc_txfree != SIP_NTXDESC) { 1429 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1430 ifp->if_oerrors++; 1431 1432 /* Reset the interface. */ 1433 (void) SIP_DECL(init)(ifp); 1434 } else if (ifp->if_flags & IFF_DEBUG) 1435 printf("%s: recovered from device timeout\n", 1436 sc->sc_dev.dv_xname); 1437 1438 /* Try to get more packets going. */ 1439 SIP_DECL(start)(ifp); 1440 } 1441 1442 /* 1443 * sip_ioctl: [ifnet interface function] 1444 * 1445 * Handle control requests from the operator. 1446 */ 1447 int 1448 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1449 { 1450 struct sip_softc *sc = ifp->if_softc; 1451 struct ifreq *ifr = (struct ifreq *)data; 1452 int s, error; 1453 1454 s = splnet(); 1455 1456 switch (cmd) { 1457 case SIOCSIFMEDIA: 1458 case SIOCGIFMEDIA: 1459 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1460 break; 1461 1462 default: 1463 error = ether_ioctl(ifp, cmd, data); 1464 if (error == ENETRESET) { 1465 /* 1466 * Multicast list has changed; set the hardware filter 1467 * accordingly. 1468 */ 1469 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1470 error = 0; 1471 } 1472 break; 1473 } 1474 1475 /* Try to get more packets going. */ 1476 SIP_DECL(start)(ifp); 1477 1478 splx(s); 1479 return (error); 1480 } 1481 1482 /* 1483 * sip_intr: 1484 * 1485 * Interrupt service routine. 1486 */ 1487 int 1488 SIP_DECL(intr)(void *arg) 1489 { 1490 struct sip_softc *sc = arg; 1491 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1492 u_int32_t isr; 1493 int handled = 0; 1494 1495 for (;;) { 1496 /* Reading clears interrupt. */ 1497 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1498 if ((isr & sc->sc_imr) == 0) 1499 break; 1500 1501 #if NRND > 0 1502 if (RND_ENABLED(&sc->rnd_source)) 1503 rnd_add_uint32(&sc->rnd_source, isr); 1504 #endif 1505 1506 handled = 1; 1507 1508 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1509 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1510 1511 /* Grab any new packets. */ 1512 SIP_DECL(rxintr)(sc); 1513 1514 if (isr & ISR_RXORN) { 1515 printf("%s: receive FIFO overrun\n", 1516 sc->sc_dev.dv_xname); 1517 1518 /* XXX adjust rx_drain_thresh? */ 1519 } 1520 1521 if (isr & ISR_RXIDLE) { 1522 printf("%s: receive ring overrun\n", 1523 sc->sc_dev.dv_xname); 1524 1525 /* Get the receive process going again. */ 1526 bus_space_write_4(sc->sc_st, sc->sc_sh, 1527 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1528 bus_space_write_4(sc->sc_st, sc->sc_sh, 1529 SIP_CR, CR_RXE); 1530 } 1531 } 1532 1533 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1534 #ifdef SIP_EVENT_COUNTERS 1535 if (isr & ISR_TXDESC) 1536 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1537 else if (isr & ISR_TXIDLE) 1538 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1539 #endif 1540 1541 /* Sweep up transmit descriptors. */ 1542 SIP_DECL(txintr)(sc); 1543 1544 if (isr & ISR_TXURN) { 1545 u_int32_t thresh; 1546 1547 printf("%s: transmit FIFO underrun", 1548 sc->sc_dev.dv_xname); 1549 1550 thresh = sc->sc_tx_drain_thresh + 1; 1551 if (thresh <= TXCFG_DRTH && 1552 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1553 (sc->sc_tx_fill_thresh * 32))) { 1554 printf("; increasing Tx drain " 1555 "threshold to %u bytes\n", 1556 thresh * 32); 1557 sc->sc_tx_drain_thresh = thresh; 1558 (void) SIP_DECL(init)(ifp); 1559 } else { 1560 (void) SIP_DECL(init)(ifp); 1561 printf("\n"); 1562 } 1563 } 1564 } 1565 1566 #if !defined(DP83820) 1567 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1568 if (isr & ISR_PAUSE_ST) { 1569 sc->sc_flags |= SIPF_PAUSED; 1570 ifp->if_flags |= IFF_OACTIVE; 1571 } 1572 if (isr & ISR_PAUSE_END) { 1573 sc->sc_flags &= ~SIPF_PAUSED; 1574 ifp->if_flags &= ~IFF_OACTIVE; 1575 } 1576 } 1577 #endif /* ! DP83820 */ 1578 1579 if (isr & ISR_HIBERR) { 1580 int want_init = 0; 1581 1582 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1583 1584 #define PRINTERR(bit, str) \ 1585 do { \ 1586 if ((isr & (bit)) != 0) { \ 1587 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1588 printf("%s: %s\n", \ 1589 sc->sc_dev.dv_xname, str); \ 1590 want_init = 1; \ 1591 } \ 1592 } while (/*CONSTCOND*/0) 1593 1594 PRINTERR(ISR_DPERR, "parity error"); 1595 PRINTERR(ISR_SSERR, "system error"); 1596 PRINTERR(ISR_RMABT, "master abort"); 1597 PRINTERR(ISR_RTABT, "target abort"); 1598 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1599 /* 1600 * Ignore: 1601 * Tx reset complete 1602 * Rx reset complete 1603 */ 1604 if (want_init) 1605 (void) SIP_DECL(init)(ifp); 1606 #undef PRINTERR 1607 } 1608 } 1609 1610 /* Try to get more packets going. */ 1611 SIP_DECL(start)(ifp); 1612 1613 return (handled); 1614 } 1615 1616 /* 1617 * sip_txintr: 1618 * 1619 * Helper; handle transmit interrupts. 1620 */ 1621 void 1622 SIP_DECL(txintr)(struct sip_softc *sc) 1623 { 1624 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1625 struct sip_txsoft *txs; 1626 u_int32_t cmdsts; 1627 1628 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1629 ifp->if_flags &= ~IFF_OACTIVE; 1630 1631 /* 1632 * Go through our Tx list and free mbufs for those 1633 * frames which have been transmitted. 1634 */ 1635 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1636 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1637 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1638 1639 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1640 if (cmdsts & CMDSTS_OWN) 1641 break; 1642 1643 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1644 1645 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1646 1647 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1648 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1649 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1650 m_freem(txs->txs_mbuf); 1651 txs->txs_mbuf = NULL; 1652 1653 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1654 1655 /* 1656 * Check for errors and collisions. 1657 */ 1658 if (cmdsts & 1659 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1660 ifp->if_oerrors++; 1661 if (cmdsts & CMDSTS_Tx_EC) 1662 ifp->if_collisions += 16; 1663 if (ifp->if_flags & IFF_DEBUG) { 1664 if (cmdsts & CMDSTS_Tx_ED) 1665 printf("%s: excessive deferral\n", 1666 sc->sc_dev.dv_xname); 1667 if (cmdsts & CMDSTS_Tx_EC) 1668 printf("%s: excessive collisions\n", 1669 sc->sc_dev.dv_xname); 1670 } 1671 } else { 1672 /* Packet was transmitted successfully. */ 1673 ifp->if_opackets++; 1674 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1675 } 1676 } 1677 1678 /* 1679 * If there are no more pending transmissions, cancel the watchdog 1680 * timer. 1681 */ 1682 if (txs == NULL) { 1683 ifp->if_timer = 0; 1684 sc->sc_txwin = 0; 1685 } 1686 } 1687 1688 #if defined(DP83820) 1689 /* 1690 * sip_rxintr: 1691 * 1692 * Helper; handle receive interrupts. 1693 */ 1694 void 1695 SIP_DECL(rxintr)(struct sip_softc *sc) 1696 { 1697 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1698 struct sip_rxsoft *rxs; 1699 struct mbuf *m, *tailm; 1700 u_int32_t cmdsts, extsts; 1701 int i, len; 1702 1703 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1704 rxs = &sc->sc_rxsoft[i]; 1705 1706 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1707 1708 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1709 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1710 1711 /* 1712 * NOTE: OWN is set if owned by _consumer_. We're the 1713 * consumer of the receive ring, so if the bit is clear, 1714 * we have processed all of the packets. 1715 */ 1716 if ((cmdsts & CMDSTS_OWN) == 0) { 1717 /* 1718 * We have processed all of the receive buffers. 1719 */ 1720 break; 1721 } 1722 1723 if (__predict_false(sc->sc_rxdiscard)) { 1724 SIP_INIT_RXDESC(sc, i); 1725 if ((cmdsts & CMDSTS_MORE) == 0) { 1726 /* Reset our state. */ 1727 sc->sc_rxdiscard = 0; 1728 } 1729 continue; 1730 } 1731 1732 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1733 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1734 1735 m = rxs->rxs_mbuf; 1736 1737 /* 1738 * Add a new receive buffer to the ring. 1739 */ 1740 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1741 /* 1742 * Failed, throw away what we've done so 1743 * far, and discard the rest of the packet. 1744 */ 1745 ifp->if_ierrors++; 1746 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1747 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1748 SIP_INIT_RXDESC(sc, i); 1749 if (cmdsts & CMDSTS_MORE) 1750 sc->sc_rxdiscard = 1; 1751 if (sc->sc_rxhead != NULL) 1752 m_freem(sc->sc_rxhead); 1753 SIP_RXCHAIN_RESET(sc); 1754 continue; 1755 } 1756 1757 SIP_RXCHAIN_LINK(sc, m); 1758 1759 /* 1760 * If this is not the end of the packet, keep 1761 * looking. 1762 */ 1763 if (cmdsts & CMDSTS_MORE) { 1764 sc->sc_rxlen += m->m_len; 1765 continue; 1766 } 1767 1768 /* 1769 * Okay, we have the entire packet now... 1770 */ 1771 *sc->sc_rxtailp = NULL; 1772 m = sc->sc_rxhead; 1773 tailm = sc->sc_rxtail; 1774 1775 SIP_RXCHAIN_RESET(sc); 1776 1777 /* 1778 * If an error occurred, update stats and drop the packet. 1779 */ 1780 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1781 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1782 ifp->if_ierrors++; 1783 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1784 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1785 /* Receive overrun handled elsewhere. */ 1786 printf("%s: receive descriptor error\n", 1787 sc->sc_dev.dv_xname); 1788 } 1789 #define PRINTERR(bit, str) \ 1790 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1791 (cmdsts & (bit)) != 0) \ 1792 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1793 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1794 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1795 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1796 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1797 #undef PRINTERR 1798 m_freem(m); 1799 continue; 1800 } 1801 1802 /* 1803 * No errors. 1804 * 1805 * Note, the DP83820 includes the CRC with 1806 * every packet. 1807 */ 1808 len = CMDSTS_SIZE(cmdsts); 1809 tailm->m_len = len - sc->sc_rxlen; 1810 1811 /* 1812 * If the packet is small enough to fit in a 1813 * single header mbuf, allocate one and copy 1814 * the data into it. This greatly reduces 1815 * memory consumption when we receive lots 1816 * of small packets. 1817 */ 1818 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1819 struct mbuf *nm; 1820 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1821 if (nm == NULL) { 1822 ifp->if_ierrors++; 1823 m_freem(m); 1824 continue; 1825 } 1826 nm->m_data += 2; 1827 nm->m_pkthdr.len = nm->m_len = len; 1828 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1829 m_freem(m); 1830 m = nm; 1831 } 1832 #ifndef __NO_STRICT_ALIGNMENT 1833 else { 1834 /* 1835 * The DP83820's receive buffers must be 4-byte 1836 * aligned. But this means that the data after 1837 * the Ethernet header is misaligned. To compensate, 1838 * we have artificially shortened the buffer size 1839 * in the descriptor, and we do an overlapping copy 1840 * of the data two bytes further in (in the first 1841 * buffer of the chain only). 1842 */ 1843 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1844 m->m_len); 1845 m->m_data += 2; 1846 } 1847 #endif /* ! __NO_STRICT_ALIGNMENT */ 1848 1849 /* 1850 * If VLANs are enabled, VLAN packets have been unwrapped 1851 * for us. Associate the tag with the packet. 1852 */ 1853 if (sc->sc_ethercom.ec_nvlans != 0 && 1854 (extsts & EXTSTS_VPKT) != 0) { 1855 struct mbuf *vtag; 1856 1857 vtag = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 1858 if (vtag == NULL) { 1859 ifp->if_ierrors++; 1860 printf("%s: unable to allocate VLAN tag\n", 1861 sc->sc_dev.dv_xname); 1862 m_freem(m); 1863 continue; 1864 } 1865 1866 *mtod(vtag, int *) = ntohs(extsts & EXTSTS_VTCI); 1867 vtag->m_len = sizeof(int); 1868 } 1869 1870 /* 1871 * Set the incoming checksum information for the 1872 * packet. 1873 */ 1874 if ((extsts & EXTSTS_IPPKT) != 0) { 1875 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1876 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1877 if (extsts & EXTSTS_Rx_IPERR) 1878 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1879 if (extsts & EXTSTS_TCPPKT) { 1880 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1881 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1882 if (extsts & EXTSTS_Rx_TCPERR) 1883 m->m_pkthdr.csum_flags |= 1884 M_CSUM_TCP_UDP_BAD; 1885 } else if (extsts & EXTSTS_UDPPKT) { 1886 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1887 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1888 if (extsts & EXTSTS_Rx_UDPERR) 1889 m->m_pkthdr.csum_flags |= 1890 M_CSUM_TCP_UDP_BAD; 1891 } 1892 } 1893 1894 ifp->if_ipackets++; 1895 m->m_flags |= M_HASFCS; 1896 m->m_pkthdr.rcvif = ifp; 1897 m->m_pkthdr.len = len; 1898 1899 #if NBPFILTER > 0 1900 /* 1901 * Pass this up to any BPF listeners, but only 1902 * pass if up the stack if it's for us. 1903 */ 1904 if (ifp->if_bpf) 1905 bpf_mtap(ifp->if_bpf, m); 1906 #endif /* NBPFILTER > 0 */ 1907 1908 /* Pass it on. */ 1909 (*ifp->if_input)(ifp, m); 1910 } 1911 1912 /* Update the receive pointer. */ 1913 sc->sc_rxptr = i; 1914 } 1915 #else /* ! DP83820 */ 1916 /* 1917 * sip_rxintr: 1918 * 1919 * Helper; handle receive interrupts. 1920 */ 1921 void 1922 SIP_DECL(rxintr)(struct sip_softc *sc) 1923 { 1924 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1925 struct sip_rxsoft *rxs; 1926 struct mbuf *m; 1927 u_int32_t cmdsts; 1928 int i, len; 1929 1930 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1931 rxs = &sc->sc_rxsoft[i]; 1932 1933 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1934 1935 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1936 1937 /* 1938 * NOTE: OWN is set if owned by _consumer_. We're the 1939 * consumer of the receive ring, so if the bit is clear, 1940 * we have processed all of the packets. 1941 */ 1942 if ((cmdsts & CMDSTS_OWN) == 0) { 1943 /* 1944 * We have processed all of the receive buffers. 1945 */ 1946 break; 1947 } 1948 1949 /* 1950 * If any collisions were seen on the wire, count one. 1951 */ 1952 if (cmdsts & CMDSTS_Rx_COL) 1953 ifp->if_collisions++; 1954 1955 /* 1956 * If an error occurred, update stats, clear the status 1957 * word, and leave the packet buffer in place. It will 1958 * simply be reused the next time the ring comes around. 1959 */ 1960 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1961 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1962 ifp->if_ierrors++; 1963 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1964 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1965 /* Receive overrun handled elsewhere. */ 1966 printf("%s: receive descriptor error\n", 1967 sc->sc_dev.dv_xname); 1968 } 1969 #define PRINTERR(bit, str) \ 1970 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1971 (cmdsts & (bit)) != 0) \ 1972 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1973 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1974 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1975 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1976 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1977 #undef PRINTERR 1978 SIP_INIT_RXDESC(sc, i); 1979 continue; 1980 } 1981 1982 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1983 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1984 1985 /* 1986 * No errors; receive the packet. Note, the SiS 900 1987 * includes the CRC with every packet. 1988 */ 1989 len = CMDSTS_SIZE(cmdsts); 1990 1991 #ifdef __NO_STRICT_ALIGNMENT 1992 /* 1993 * If the packet is small enough to fit in a 1994 * single header mbuf, allocate one and copy 1995 * the data into it. This greatly reduces 1996 * memory consumption when we receive lots 1997 * of small packets. 1998 * 1999 * Otherwise, we add a new buffer to the receive 2000 * chain. If this fails, we drop the packet and 2001 * recycle the old buffer. 2002 */ 2003 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 2004 MGETHDR(m, M_DONTWAIT, MT_DATA); 2005 if (m == NULL) 2006 goto dropit; 2007 memcpy(mtod(m, caddr_t), 2008 mtod(rxs->rxs_mbuf, caddr_t), len); 2009 SIP_INIT_RXDESC(sc, i); 2010 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2011 rxs->rxs_dmamap->dm_mapsize, 2012 BUS_DMASYNC_PREREAD); 2013 } else { 2014 m = rxs->rxs_mbuf; 2015 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 2016 dropit: 2017 ifp->if_ierrors++; 2018 SIP_INIT_RXDESC(sc, i); 2019 bus_dmamap_sync(sc->sc_dmat, 2020 rxs->rxs_dmamap, 0, 2021 rxs->rxs_dmamap->dm_mapsize, 2022 BUS_DMASYNC_PREREAD); 2023 continue; 2024 } 2025 } 2026 #else 2027 /* 2028 * The SiS 900's receive buffers must be 4-byte aligned. 2029 * But this means that the data after the Ethernet header 2030 * is misaligned. We must allocate a new buffer and 2031 * copy the data, shifted forward 2 bytes. 2032 */ 2033 MGETHDR(m, M_DONTWAIT, MT_DATA); 2034 if (m == NULL) { 2035 dropit: 2036 ifp->if_ierrors++; 2037 SIP_INIT_RXDESC(sc, i); 2038 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2039 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2040 continue; 2041 } 2042 if (len > (MHLEN - 2)) { 2043 MCLGET(m, M_DONTWAIT); 2044 if ((m->m_flags & M_EXT) == 0) { 2045 m_freem(m); 2046 goto dropit; 2047 } 2048 } 2049 m->m_data += 2; 2050 2051 /* 2052 * Note that we use clusters for incoming frames, so the 2053 * buffer is virtually contiguous. 2054 */ 2055 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 2056 2057 /* Allow the receive descriptor to continue using its mbuf. */ 2058 SIP_INIT_RXDESC(sc, i); 2059 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2060 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2061 #endif /* __NO_STRICT_ALIGNMENT */ 2062 2063 ifp->if_ipackets++; 2064 m->m_flags |= M_HASFCS; 2065 m->m_pkthdr.rcvif = ifp; 2066 m->m_pkthdr.len = m->m_len = len; 2067 2068 #if NBPFILTER > 0 2069 /* 2070 * Pass this up to any BPF listeners, but only 2071 * pass if up the stack if it's for us. 2072 */ 2073 if (ifp->if_bpf) 2074 bpf_mtap(ifp->if_bpf, m); 2075 #endif /* NBPFILTER > 0 */ 2076 2077 /* Pass it on. */ 2078 (*ifp->if_input)(ifp, m); 2079 } 2080 2081 /* Update the receive pointer. */ 2082 sc->sc_rxptr = i; 2083 } 2084 #endif /* DP83820 */ 2085 2086 /* 2087 * sip_tick: 2088 * 2089 * One second timer, used to tick the MII. 2090 */ 2091 void 2092 SIP_DECL(tick)(void *arg) 2093 { 2094 struct sip_softc *sc = arg; 2095 int s; 2096 2097 s = splnet(); 2098 mii_tick(&sc->sc_mii); 2099 splx(s); 2100 2101 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2102 } 2103 2104 /* 2105 * sip_reset: 2106 * 2107 * Perform a soft reset on the SiS 900. 2108 */ 2109 void 2110 SIP_DECL(reset)(struct sip_softc *sc) 2111 { 2112 bus_space_tag_t st = sc->sc_st; 2113 bus_space_handle_t sh = sc->sc_sh; 2114 int i; 2115 2116 bus_space_write_4(st, sh, SIP_IER, 0); 2117 bus_space_write_4(st, sh, SIP_IMR, 0); 2118 bus_space_write_4(st, sh, SIP_RFCR, 0); 2119 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2120 2121 for (i = 0; i < SIP_TIMEOUT; i++) { 2122 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2123 break; 2124 delay(2); 2125 } 2126 2127 if (i == SIP_TIMEOUT) 2128 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2129 2130 delay(1000); 2131 2132 #ifdef DP83820 2133 /* 2134 * Set the general purpose I/O bits. Do it here in case we 2135 * need to have GPIO set up to talk to the media interface. 2136 */ 2137 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2138 delay(1000); 2139 #endif /* DP83820 */ 2140 } 2141 2142 /* 2143 * sip_init: [ ifnet interface function ] 2144 * 2145 * Initialize the interface. Must be called at splnet(). 2146 */ 2147 int 2148 SIP_DECL(init)(struct ifnet *ifp) 2149 { 2150 struct sip_softc *sc = ifp->if_softc; 2151 bus_space_tag_t st = sc->sc_st; 2152 bus_space_handle_t sh = sc->sc_sh; 2153 struct sip_txsoft *txs; 2154 struct sip_rxsoft *rxs; 2155 struct sip_desc *sipd; 2156 u_int32_t reg; 2157 int i, error = 0; 2158 2159 /* 2160 * Cancel any pending I/O. 2161 */ 2162 SIP_DECL(stop)(ifp, 0); 2163 2164 /* 2165 * Reset the chip to a known state. 2166 */ 2167 SIP_DECL(reset)(sc); 2168 2169 #if !defined(DP83820) 2170 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2171 /* 2172 * DP83815 manual, page 78: 2173 * 4.4 Recommended Registers Configuration 2174 * For optimum performance of the DP83815, version noted 2175 * as DP83815CVNG (SRR = 203h), the listed register 2176 * modifications must be followed in sequence... 2177 * 2178 * It's not clear if this should be 302h or 203h because that 2179 * chip name is listed as SRR 302h in the description of the 2180 * SRR register. However, my revision 302h DP83815 on the 2181 * Netgear FA311 purchased in 02/2001 needs these settings 2182 * to avoid tons of errors in AcceptPerfectMatch (non- 2183 * IFF_PROMISC) mode. I do not know if other revisions need 2184 * this set or not. [briggs -- 09 March 2001] 2185 * 2186 * Note that only the low-order 12 bits of 0xe4 are documented 2187 * and that this sets reserved bits in that register. 2188 */ 2189 reg = bus_space_read_4(st, sh, SIP_NS_SRR); 2190 if (reg == 0x302) { 2191 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2192 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2193 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2194 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2195 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2196 } 2197 } 2198 #endif /* ! DP83820 */ 2199 2200 /* 2201 * Initialize the transmit descriptor ring. 2202 */ 2203 for (i = 0; i < SIP_NTXDESC; i++) { 2204 sipd = &sc->sc_txdescs[i]; 2205 memset(sipd, 0, sizeof(struct sip_desc)); 2206 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2207 } 2208 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2209 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2210 sc->sc_txfree = SIP_NTXDESC; 2211 sc->sc_txnext = 0; 2212 sc->sc_txwin = 0; 2213 2214 /* 2215 * Initialize the transmit job descriptors. 2216 */ 2217 SIMPLEQ_INIT(&sc->sc_txfreeq); 2218 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2219 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2220 txs = &sc->sc_txsoft[i]; 2221 txs->txs_mbuf = NULL; 2222 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2223 } 2224 2225 /* 2226 * Initialize the receive descriptor and receive job 2227 * descriptor rings. 2228 */ 2229 for (i = 0; i < SIP_NRXDESC; i++) { 2230 rxs = &sc->sc_rxsoft[i]; 2231 if (rxs->rxs_mbuf == NULL) { 2232 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2233 printf("%s: unable to allocate or map rx " 2234 "buffer %d, error = %d\n", 2235 sc->sc_dev.dv_xname, i, error); 2236 /* 2237 * XXX Should attempt to run with fewer receive 2238 * XXX buffers instead of just failing. 2239 */ 2240 SIP_DECL(rxdrain)(sc); 2241 goto out; 2242 } 2243 } else 2244 SIP_INIT_RXDESC(sc, i); 2245 } 2246 sc->sc_rxptr = 0; 2247 #ifdef DP83820 2248 sc->sc_rxdiscard = 0; 2249 SIP_RXCHAIN_RESET(sc); 2250 #endif /* DP83820 */ 2251 2252 /* 2253 * Set the configuration register; it's already initialized 2254 * in sip_attach(). 2255 */ 2256 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2257 2258 /* 2259 * Initialize the prototype TXCFG register. 2260 */ 2261 #if defined(DP83820) 2262 sc->sc_txcfg = TXCFG_MXDMA_512; 2263 sc->sc_rxcfg = RXCFG_MXDMA_512; 2264 #else 2265 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2266 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2267 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & CFG_EDBMASTEN)) { 2268 sc->sc_txcfg = TXCFG_MXDMA_64; 2269 sc->sc_rxcfg = RXCFG_MXDMA_64; 2270 } else { 2271 sc->sc_txcfg = TXCFG_MXDMA_512; 2272 sc->sc_rxcfg = RXCFG_MXDMA_512; 2273 } 2274 #endif /* DP83820 */ 2275 2276 sc->sc_txcfg |= TXCFG_ATP | 2277 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2278 sc->sc_tx_drain_thresh; 2279 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2280 2281 /* 2282 * Initialize the receive drain threshold if we have never 2283 * done so. 2284 */ 2285 if (sc->sc_rx_drain_thresh == 0) { 2286 /* 2287 * XXX This value should be tuned. This is set to the 2288 * maximum of 248 bytes, and we may be able to improve 2289 * performance by decreasing it (although we should never 2290 * set this value lower than 2; 14 bytes are required to 2291 * filter the packet). 2292 */ 2293 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2294 } 2295 2296 /* 2297 * Initialize the prototype RXCFG register. 2298 */ 2299 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2300 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2301 2302 #ifdef DP83820 2303 /* 2304 * Initialize the VLAN/IP receive control register. 2305 * We enable checksum computation on all incoming 2306 * packets, and do not reject packets w/ bad checksums. 2307 */ 2308 reg = 0; 2309 if (ifp->if_capenable & 2310 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2311 reg |= VRCR_IPEN; 2312 if (sc->sc_ethercom.ec_nvlans != 0) 2313 reg |= VRCR_VTDEN|VRCR_VTREN; 2314 bus_space_write_4(st, sh, SIP_VRCR, reg); 2315 2316 /* 2317 * Initialize the VLAN/IP transmit control register. 2318 * We enable outgoing checksum computation on a 2319 * per-packet basis. 2320 */ 2321 reg = 0; 2322 if (ifp->if_capenable & 2323 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2324 reg |= VTCR_PPCHK; 2325 if (sc->sc_ethercom.ec_nvlans != 0) 2326 reg |= VTCR_VPPTI; 2327 bus_space_write_4(st, sh, SIP_VTCR, reg); 2328 2329 /* 2330 * If we're using VLANs, initialize the VLAN data register. 2331 * To understand why we bswap the VLAN Ethertype, see section 2332 * 4.2.36 of the DP83820 manual. 2333 */ 2334 if (sc->sc_ethercom.ec_nvlans != 0) 2335 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2336 #endif /* DP83820 */ 2337 2338 /* 2339 * Give the transmit and receive rings to the chip. 2340 */ 2341 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2342 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2343 2344 /* 2345 * Initialize the interrupt mask. 2346 */ 2347 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2348 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2349 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2350 2351 /* Set up the receive filter. */ 2352 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2353 2354 /* 2355 * Set the current media. Do this after initializing the prototype 2356 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2357 * control. 2358 */ 2359 mii_mediachg(&sc->sc_mii); 2360 2361 /* 2362 * Enable interrupts. 2363 */ 2364 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2365 2366 /* 2367 * Start the transmit and receive processes. 2368 */ 2369 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2370 2371 /* 2372 * Start the one second MII clock. 2373 */ 2374 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2375 2376 /* 2377 * ...all done! 2378 */ 2379 ifp->if_flags |= IFF_RUNNING; 2380 ifp->if_flags &= ~IFF_OACTIVE; 2381 2382 out: 2383 if (error) 2384 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2385 return (error); 2386 } 2387 2388 /* 2389 * sip_drain: 2390 * 2391 * Drain the receive queue. 2392 */ 2393 void 2394 SIP_DECL(rxdrain)(struct sip_softc *sc) 2395 { 2396 struct sip_rxsoft *rxs; 2397 int i; 2398 2399 for (i = 0; i < SIP_NRXDESC; i++) { 2400 rxs = &sc->sc_rxsoft[i]; 2401 if (rxs->rxs_mbuf != NULL) { 2402 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2403 m_freem(rxs->rxs_mbuf); 2404 rxs->rxs_mbuf = NULL; 2405 } 2406 } 2407 } 2408 2409 /* 2410 * sip_stop: [ ifnet interface function ] 2411 * 2412 * Stop transmission on the interface. 2413 */ 2414 void 2415 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2416 { 2417 struct sip_softc *sc = ifp->if_softc; 2418 bus_space_tag_t st = sc->sc_st; 2419 bus_space_handle_t sh = sc->sc_sh; 2420 struct sip_txsoft *txs; 2421 u_int32_t cmdsts = 0; /* DEBUG */ 2422 2423 /* 2424 * Stop the one second clock. 2425 */ 2426 callout_stop(&sc->sc_tick_ch); 2427 2428 /* Down the MII. */ 2429 mii_down(&sc->sc_mii); 2430 2431 /* 2432 * Disable interrupts. 2433 */ 2434 bus_space_write_4(st, sh, SIP_IER, 0); 2435 2436 /* 2437 * Stop receiver and transmitter. 2438 */ 2439 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2440 2441 /* 2442 * Release any queued transmit buffers. 2443 */ 2444 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2445 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2446 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2447 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2448 CMDSTS_INTR) == 0) 2449 printf("%s: sip_stop: last descriptor does not " 2450 "have INTR bit set\n", sc->sc_dev.dv_xname); 2451 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2452 #ifdef DIAGNOSTIC 2453 if (txs->txs_mbuf == NULL) { 2454 printf("%s: dirty txsoft with no mbuf chain\n", 2455 sc->sc_dev.dv_xname); 2456 panic("sip_stop"); 2457 } 2458 #endif 2459 cmdsts |= /* DEBUG */ 2460 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2461 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2462 m_freem(txs->txs_mbuf); 2463 txs->txs_mbuf = NULL; 2464 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2465 } 2466 2467 if (disable) 2468 SIP_DECL(rxdrain)(sc); 2469 2470 /* 2471 * Mark the interface down and cancel the watchdog timer. 2472 */ 2473 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2474 ifp->if_timer = 0; 2475 2476 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2477 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2478 printf("%s: sip_stop: no INTR bits set in dirty tx " 2479 "descriptors\n", sc->sc_dev.dv_xname); 2480 } 2481 2482 /* 2483 * sip_read_eeprom: 2484 * 2485 * Read data from the serial EEPROM. 2486 */ 2487 void 2488 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2489 u_int16_t *data) 2490 { 2491 bus_space_tag_t st = sc->sc_st; 2492 bus_space_handle_t sh = sc->sc_sh; 2493 u_int16_t reg; 2494 int i, x; 2495 2496 for (i = 0; i < wordcnt; i++) { 2497 /* Send CHIP SELECT. */ 2498 reg = EROMAR_EECS; 2499 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2500 2501 /* Shift in the READ opcode. */ 2502 for (x = 3; x > 0; x--) { 2503 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2504 reg |= EROMAR_EEDI; 2505 else 2506 reg &= ~EROMAR_EEDI; 2507 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2508 bus_space_write_4(st, sh, SIP_EROMAR, 2509 reg | EROMAR_EESK); 2510 delay(4); 2511 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2512 delay(4); 2513 } 2514 2515 /* Shift in address. */ 2516 for (x = 6; x > 0; x--) { 2517 if ((word + i) & (1 << (x - 1))) 2518 reg |= EROMAR_EEDI; 2519 else 2520 reg &= ~EROMAR_EEDI; 2521 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2522 bus_space_write_4(st, sh, SIP_EROMAR, 2523 reg | EROMAR_EESK); 2524 delay(4); 2525 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2526 delay(4); 2527 } 2528 2529 /* Shift out data. */ 2530 reg = EROMAR_EECS; 2531 data[i] = 0; 2532 for (x = 16; x > 0; x--) { 2533 bus_space_write_4(st, sh, SIP_EROMAR, 2534 reg | EROMAR_EESK); 2535 delay(4); 2536 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2537 data[i] |= (1 << (x - 1)); 2538 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2539 delay(4); 2540 } 2541 2542 /* Clear CHIP SELECT. */ 2543 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2544 delay(4); 2545 } 2546 } 2547 2548 /* 2549 * sip_add_rxbuf: 2550 * 2551 * Add a receive buffer to the indicated descriptor. 2552 */ 2553 int 2554 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2555 { 2556 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2557 struct mbuf *m; 2558 int error; 2559 2560 MGETHDR(m, M_DONTWAIT, MT_DATA); 2561 if (m == NULL) 2562 return (ENOBUFS); 2563 2564 MCLGET(m, M_DONTWAIT); 2565 if ((m->m_flags & M_EXT) == 0) { 2566 m_freem(m); 2567 return (ENOBUFS); 2568 } 2569 2570 #if defined(DP83820) 2571 m->m_len = SIP_RXBUF_LEN; 2572 #endif /* DP83820 */ 2573 2574 if (rxs->rxs_mbuf != NULL) 2575 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2576 2577 rxs->rxs_mbuf = m; 2578 2579 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2580 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2581 BUS_DMA_READ|BUS_DMA_NOWAIT); 2582 if (error) { 2583 printf("%s: can't load rx DMA map %d, error = %d\n", 2584 sc->sc_dev.dv_xname, idx, error); 2585 panic("sip_add_rxbuf"); /* XXX */ 2586 } 2587 2588 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2589 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2590 2591 SIP_INIT_RXDESC(sc, idx); 2592 2593 return (0); 2594 } 2595 2596 #if !defined(DP83820) 2597 /* 2598 * sip_sis900_set_filter: 2599 * 2600 * Set up the receive filter. 2601 */ 2602 void 2603 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2604 { 2605 bus_space_tag_t st = sc->sc_st; 2606 bus_space_handle_t sh = sc->sc_sh; 2607 struct ethercom *ec = &sc->sc_ethercom; 2608 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2609 struct ether_multi *enm; 2610 u_int8_t *cp; 2611 struct ether_multistep step; 2612 u_int32_t crc, mchash[16]; 2613 2614 /* 2615 * Initialize the prototype RFCR. 2616 */ 2617 sc->sc_rfcr = RFCR_RFEN; 2618 if (ifp->if_flags & IFF_BROADCAST) 2619 sc->sc_rfcr |= RFCR_AAB; 2620 if (ifp->if_flags & IFF_PROMISC) { 2621 sc->sc_rfcr |= RFCR_AAP; 2622 goto allmulti; 2623 } 2624 2625 /* 2626 * Set up the multicast address filter by passing all multicast 2627 * addresses through a CRC generator, and then using the high-order 2628 * 6 bits as an index into the 128 bit multicast hash table (only 2629 * the lower 16 bits of each 32 bit multicast hash register are 2630 * valid). The high order bits select the register, while the 2631 * rest of the bits select the bit within the register. 2632 */ 2633 2634 memset(mchash, 0, sizeof(mchash)); 2635 2636 ETHER_FIRST_MULTI(step, ec, enm); 2637 while (enm != NULL) { 2638 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2639 /* 2640 * We must listen to a range of multicast addresses. 2641 * For now, just accept all multicasts, rather than 2642 * trying to set only those filter bits needed to match 2643 * the range. (At this time, the only use of address 2644 * ranges is for IP multicast routing, for which the 2645 * range is big enough to require all bits set.) 2646 */ 2647 goto allmulti; 2648 } 2649 2650 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2651 2652 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2653 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2654 /* Just want the 8 most significant bits. */ 2655 crc >>= 24; 2656 } else { 2657 /* Just want the 7 most significant bits. */ 2658 crc >>= 25; 2659 } 2660 2661 /* Set the corresponding bit in the hash table. */ 2662 mchash[crc >> 4] |= 1 << (crc & 0xf); 2663 2664 ETHER_NEXT_MULTI(step, enm); 2665 } 2666 2667 ifp->if_flags &= ~IFF_ALLMULTI; 2668 goto setit; 2669 2670 allmulti: 2671 ifp->if_flags |= IFF_ALLMULTI; 2672 sc->sc_rfcr |= RFCR_AAM; 2673 2674 setit: 2675 #define FILTER_EMIT(addr, data) \ 2676 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2677 delay(1); \ 2678 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2679 delay(1) 2680 2681 /* 2682 * Disable receive filter, and program the node address. 2683 */ 2684 cp = LLADDR(ifp->if_sadl); 2685 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2686 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2687 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2688 2689 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2690 /* 2691 * Program the multicast hash table. 2692 */ 2693 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2694 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2695 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2696 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2697 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2698 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2699 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2700 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2701 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2702 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2703 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2704 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2705 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2706 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2707 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2708 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2709 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2710 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2711 } 2712 } 2713 #undef FILTER_EMIT 2714 2715 /* 2716 * Re-enable the receiver filter. 2717 */ 2718 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2719 } 2720 #endif /* ! DP83820 */ 2721 2722 /* 2723 * sip_dp83815_set_filter: 2724 * 2725 * Set up the receive filter. 2726 */ 2727 void 2728 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2729 { 2730 bus_space_tag_t st = sc->sc_st; 2731 bus_space_handle_t sh = sc->sc_sh; 2732 struct ethercom *ec = &sc->sc_ethercom; 2733 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2734 struct ether_multi *enm; 2735 u_int8_t *cp; 2736 struct ether_multistep step; 2737 u_int32_t crc, hash, slot, bit; 2738 #ifdef DP83820 2739 #define MCHASH_NWORDS 128 2740 #else 2741 #define MCHASH_NWORDS 32 2742 #endif /* DP83820 */ 2743 u_int16_t mchash[MCHASH_NWORDS]; 2744 int i; 2745 2746 /* 2747 * Initialize the prototype RFCR. 2748 * Enable the receive filter, and accept on 2749 * Perfect (destination address) Match 2750 * If IFF_BROADCAST, also accept all broadcast packets. 2751 * If IFF_PROMISC, accept all unicast packets (and later, set 2752 * IFF_ALLMULTI and accept all multicast, too). 2753 */ 2754 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2755 if (ifp->if_flags & IFF_BROADCAST) 2756 sc->sc_rfcr |= RFCR_AAB; 2757 if (ifp->if_flags & IFF_PROMISC) { 2758 sc->sc_rfcr |= RFCR_AAP; 2759 goto allmulti; 2760 } 2761 2762 #ifdef DP83820 2763 /* 2764 * Set up the DP83820 multicast address filter by passing all multicast 2765 * addresses through a CRC generator, and then using the high-order 2766 * 11 bits as an index into the 2048 bit multicast hash table. The 2767 * high-order 7 bits select the slot, while the low-order 4 bits 2768 * select the bit within the slot. Note that only the low 16-bits 2769 * of each filter word are used, and there are 128 filter words. 2770 */ 2771 #else 2772 /* 2773 * Set up the DP83815 multicast address filter by passing all multicast 2774 * addresses through a CRC generator, and then using the high-order 2775 * 9 bits as an index into the 512 bit multicast hash table. The 2776 * high-order 5 bits select the slot, while the low-order 4 bits 2777 * select the bit within the slot. Note that only the low 16-bits 2778 * of each filter word are used, and there are 32 filter words. 2779 */ 2780 #endif /* DP83820 */ 2781 2782 memset(mchash, 0, sizeof(mchash)); 2783 2784 ifp->if_flags &= ~IFF_ALLMULTI; 2785 ETHER_FIRST_MULTI(step, ec, enm); 2786 if (enm == NULL) 2787 goto setit; 2788 while (enm != NULL) { 2789 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2790 /* 2791 * We must listen to a range of multicast addresses. 2792 * For now, just accept all multicasts, rather than 2793 * trying to set only those filter bits needed to match 2794 * the range. (At this time, the only use of address 2795 * ranges is for IP multicast routing, for which the 2796 * range is big enough to require all bits set.) 2797 */ 2798 goto allmulti; 2799 } 2800 2801 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2802 2803 #ifdef DP83820 2804 /* Just want the 11 most significant bits. */ 2805 hash = crc >> 21; 2806 #else 2807 /* Just want the 9 most significant bits. */ 2808 hash = crc >> 23; 2809 #endif /* DP83820 */ 2810 2811 slot = hash >> 4; 2812 bit = hash & 0xf; 2813 2814 /* Set the corresponding bit in the hash table. */ 2815 mchash[slot] |= 1 << bit; 2816 2817 ETHER_NEXT_MULTI(step, enm); 2818 } 2819 sc->sc_rfcr |= RFCR_MHEN; 2820 goto setit; 2821 2822 allmulti: 2823 ifp->if_flags |= IFF_ALLMULTI; 2824 sc->sc_rfcr |= RFCR_AAM; 2825 2826 setit: 2827 #define FILTER_EMIT(addr, data) \ 2828 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2829 delay(1); \ 2830 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2831 delay(1) 2832 2833 /* 2834 * Disable receive filter, and program the node address. 2835 */ 2836 cp = LLADDR(ifp->if_sadl); 2837 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 2838 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 2839 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 2840 2841 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2842 /* 2843 * Program the multicast hash table. 2844 */ 2845 for (i = 0; i < MCHASH_NWORDS; i++) { 2846 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 2847 mchash[i]); 2848 } 2849 } 2850 #undef FILTER_EMIT 2851 #undef MCHASH_NWORDS 2852 2853 /* 2854 * Re-enable the receiver filter. 2855 */ 2856 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2857 } 2858 2859 #if defined(DP83820) 2860 /* 2861 * sip_dp83820_mii_readreg: [mii interface function] 2862 * 2863 * Read a PHY register on the MII of the DP83820. 2864 */ 2865 int 2866 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 2867 { 2868 struct sip_softc *sc = (void *) self; 2869 2870 if (sc->sc_cfg & CFG_TBI_EN) { 2871 bus_addr_t tbireg; 2872 int rv; 2873 2874 if (phy != 0) 2875 return (0); 2876 2877 switch (reg) { 2878 case MII_BMCR: tbireg = SIP_TBICR; break; 2879 case MII_BMSR: tbireg = SIP_TBISR; break; 2880 case MII_ANAR: tbireg = SIP_TANAR; break; 2881 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 2882 case MII_ANER: tbireg = SIP_TANER; break; 2883 case MII_EXTSR: 2884 /* 2885 * Don't even bother reading the TESR register. 2886 * The manual documents that the device has 2887 * 1000baseX full/half capability, but the 2888 * register itself seems read back 0 on some 2889 * boards. Just hard-code the result. 2890 */ 2891 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 2892 2893 default: 2894 return (0); 2895 } 2896 2897 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 2898 if (tbireg == SIP_TBISR) { 2899 /* LINK and ACOMP are switched! */ 2900 int val = rv; 2901 2902 rv = 0; 2903 if (val & TBISR_MR_LINK_STATUS) 2904 rv |= BMSR_LINK; 2905 if (val & TBISR_MR_AN_COMPLETE) 2906 rv |= BMSR_ACOMP; 2907 2908 /* 2909 * The manual claims this register reads back 0 2910 * on hard and soft reset. But we want to let 2911 * the gentbi driver know that we support auto- 2912 * negotiation, so hard-code this bit in the 2913 * result. 2914 */ 2915 rv |= BMSR_ANEG | BMSR_EXTCAP; 2916 } 2917 2918 return (rv); 2919 } 2920 2921 return (mii_bitbang_readreg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2922 phy, reg)); 2923 } 2924 2925 /* 2926 * sip_dp83820_mii_writereg: [mii interface function] 2927 * 2928 * Write a PHY register on the MII of the DP83820. 2929 */ 2930 void 2931 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 2932 { 2933 struct sip_softc *sc = (void *) self; 2934 2935 if (sc->sc_cfg & CFG_TBI_EN) { 2936 bus_addr_t tbireg; 2937 2938 if (phy != 0) 2939 return; 2940 2941 switch (reg) { 2942 case MII_BMCR: tbireg = SIP_TBICR; break; 2943 case MII_ANAR: tbireg = SIP_TANAR; break; 2944 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 2945 default: 2946 return; 2947 } 2948 2949 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 2950 return; 2951 } 2952 2953 mii_bitbang_writereg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2954 phy, reg, val); 2955 } 2956 2957 /* 2958 * sip_dp83815_mii_statchg: [mii interface function] 2959 * 2960 * Callback from MII layer when media changes. 2961 */ 2962 void 2963 SIP_DECL(dp83820_mii_statchg)(struct device *self) 2964 { 2965 struct sip_softc *sc = (struct sip_softc *) self; 2966 u_int32_t cfg; 2967 2968 /* 2969 * Update TXCFG for full-duplex operation. 2970 */ 2971 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2972 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2973 else 2974 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 2975 2976 /* 2977 * Update RXCFG for full-duplex or loopback. 2978 */ 2979 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 2980 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 2981 sc->sc_rxcfg |= RXCFG_ATX; 2982 else 2983 sc->sc_rxcfg &= ~RXCFG_ATX; 2984 2985 /* 2986 * Update CFG for MII/GMII. 2987 */ 2988 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2989 cfg = sc->sc_cfg | CFG_MODE_1000; 2990 else 2991 cfg = sc->sc_cfg; 2992 2993 /* 2994 * XXX 802.3x flow control. 2995 */ 2996 2997 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 2998 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 2999 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3000 } 3001 3002 /* 3003 * sip_dp83820_mii_bitbang_read: [mii bit-bang interface function] 3004 * 3005 * Read the MII serial port for the MII bit-bang module. 3006 */ 3007 u_int32_t 3008 SIP_DECL(dp83820_mii_bitbang_read)(struct device *self) 3009 { 3010 struct sip_softc *sc = (void *) self; 3011 3012 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3013 } 3014 3015 /* 3016 * sip_dp83820_mii_bitbang_write: [mii big-bang interface function] 3017 * 3018 * Write the MII serial port for the MII bit-bang module. 3019 */ 3020 void 3021 SIP_DECL(dp83820_mii_bitbang_write)(struct device *self, u_int32_t val) 3022 { 3023 struct sip_softc *sc = (void *) self; 3024 3025 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3026 } 3027 #else /* ! DP83820 */ 3028 /* 3029 * sip_sis900_mii_readreg: [mii interface function] 3030 * 3031 * Read a PHY register on the MII. 3032 */ 3033 int 3034 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 3035 { 3036 struct sip_softc *sc = (struct sip_softc *) self; 3037 u_int32_t enphy; 3038 3039 /* 3040 * The SiS 900 has only an internal PHY on the MII. Only allow 3041 * MII address 0. 3042 */ 3043 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 3044 sc->sc_rev < SIS_REV_635 && phy != 0) 3045 return (0); 3046 3047 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3048 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3049 ENPHY_RWCMD | ENPHY_ACCESS); 3050 do { 3051 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3052 } while (enphy & ENPHY_ACCESS); 3053 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3054 } 3055 3056 /* 3057 * sip_sis900_mii_writereg: [mii interface function] 3058 * 3059 * Write a PHY register on the MII. 3060 */ 3061 void 3062 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 3063 { 3064 struct sip_softc *sc = (struct sip_softc *) self; 3065 u_int32_t enphy; 3066 3067 /* 3068 * The SiS 900 has only an internal PHY on the MII. Only allow 3069 * MII address 0. 3070 */ 3071 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 3072 sc->sc_rev < SIS_REV_635 && phy != 0) 3073 return; 3074 3075 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3076 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3077 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3078 do { 3079 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3080 } while (enphy & ENPHY_ACCESS); 3081 } 3082 3083 /* 3084 * sip_sis900_mii_statchg: [mii interface function] 3085 * 3086 * Callback from MII layer when media changes. 3087 */ 3088 void 3089 SIP_DECL(sis900_mii_statchg)(struct device *self) 3090 { 3091 struct sip_softc *sc = (struct sip_softc *) self; 3092 u_int32_t flowctl; 3093 3094 /* 3095 * Update TXCFG for full-duplex operation. 3096 */ 3097 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3098 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3099 else 3100 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3101 3102 /* 3103 * Update RXCFG for full-duplex or loopback. 3104 */ 3105 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3106 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3107 sc->sc_rxcfg |= RXCFG_ATX; 3108 else 3109 sc->sc_rxcfg &= ~RXCFG_ATX; 3110 3111 /* 3112 * Update IMR for use of 802.3x flow control. 3113 */ 3114 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 3115 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3116 flowctl = FLOWCTL_FLOWEN; 3117 } else { 3118 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3119 flowctl = 0; 3120 } 3121 3122 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3123 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3124 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3125 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3126 } 3127 3128 /* 3129 * sip_dp83815_mii_readreg: [mii interface function] 3130 * 3131 * Read a PHY register on the MII. 3132 */ 3133 int 3134 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 3135 { 3136 struct sip_softc *sc = (struct sip_softc *) self; 3137 u_int32_t val; 3138 3139 /* 3140 * The DP83815 only has an internal PHY. Only allow 3141 * MII address 0. 3142 */ 3143 if (phy != 0) 3144 return (0); 3145 3146 /* 3147 * Apparently, after a reset, the DP83815 can take a while 3148 * to respond. During this recovery period, the BMSR returns 3149 * a value of 0. Catch this -- it's not supposed to happen 3150 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3151 * PHY to come back to life. 3152 * 3153 * This works out because the BMSR is the first register 3154 * read during the PHY probe process. 3155 */ 3156 do { 3157 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3158 } while (reg == MII_BMSR && val == 0); 3159 3160 return (val & 0xffff); 3161 } 3162 3163 /* 3164 * sip_dp83815_mii_writereg: [mii interface function] 3165 * 3166 * Write a PHY register to the MII. 3167 */ 3168 void 3169 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3170 { 3171 struct sip_softc *sc = (struct sip_softc *) self; 3172 3173 /* 3174 * The DP83815 only has an internal PHY. Only allow 3175 * MII address 0. 3176 */ 3177 if (phy != 0) 3178 return; 3179 3180 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3181 } 3182 3183 /* 3184 * sip_dp83815_mii_statchg: [mii interface function] 3185 * 3186 * Callback from MII layer when media changes. 3187 */ 3188 void 3189 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3190 { 3191 struct sip_softc *sc = (struct sip_softc *) self; 3192 3193 /* 3194 * Update TXCFG for full-duplex operation. 3195 */ 3196 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3197 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3198 else 3199 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3200 3201 /* 3202 * Update RXCFG for full-duplex or loopback. 3203 */ 3204 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3205 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3206 sc->sc_rxcfg |= RXCFG_ATX; 3207 else 3208 sc->sc_rxcfg &= ~RXCFG_ATX; 3209 3210 /* 3211 * XXX 802.3x flow control. 3212 */ 3213 3214 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3215 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3216 } 3217 #endif /* DP83820 */ 3218 3219 #if defined(DP83820) 3220 void 3221 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3222 const struct pci_attach_args *pa, u_int8_t *enaddr) 3223 { 3224 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3225 u_int8_t cksum, *e, match; 3226 int i; 3227 3228 /* 3229 * EEPROM data format for the DP83820 can be found in 3230 * the DP83820 manual, section 4.2.4. 3231 */ 3232 3233 SIP_DECL(read_eeprom)(sc, 0, 3234 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3235 3236 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3237 match = ~(match - 1); 3238 3239 cksum = 0x55; 3240 e = (u_int8_t *) eeprom_data; 3241 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3242 cksum += *e++; 3243 3244 if (cksum != match) 3245 printf("%s: Checksum (%x) mismatch (%x)", 3246 sc->sc_dev.dv_xname, cksum, match); 3247 3248 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3249 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3250 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3251 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3252 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3253 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3254 3255 /* Get the GPIOR bits. */ 3256 sc->sc_gpior = eeprom_data[0x04]; 3257 } 3258 #else /* ! DP83820 */ 3259 void 3260 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3261 const struct pci_attach_args *pa, u_int8_t *enaddr) 3262 { 3263 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3264 3265 switch (sc->sc_rev) { 3266 case SIS_REV_630S: 3267 case SIS_REV_630E: 3268 case SIS_REV_630EA1: 3269 case SIS_REV_630ET: 3270 case SIS_REV_635: 3271 /* 3272 * The MAC address for the on-board Ethernet of 3273 * the SiS 630 chipset is in the NVRAM. Kick 3274 * the chip into re-loading it from NVRAM, and 3275 * read the MAC address out of the filter registers. 3276 */ 3277 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3278 3279 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3280 RFCR_RFADDR_NODE0); 3281 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3282 0xffff; 3283 3284 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3285 RFCR_RFADDR_NODE2); 3286 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3287 0xffff; 3288 3289 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3290 RFCR_RFADDR_NODE4); 3291 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3292 0xffff; 3293 break; 3294 3295 default: 3296 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3297 sizeof(myea) / sizeof(myea[0]), myea); 3298 } 3299 3300 enaddr[0] = myea[0] & 0xff; 3301 enaddr[1] = myea[0] >> 8; 3302 enaddr[2] = myea[1] & 0xff; 3303 enaddr[3] = myea[1] >> 8; 3304 enaddr[4] = myea[2] & 0xff; 3305 enaddr[5] = myea[2] >> 8; 3306 } 3307 3308 /* Table and macro to bit-reverse an octet. */ 3309 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3310 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3311 3312 void 3313 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3314 const struct pci_attach_args *pa, u_int8_t *enaddr) 3315 { 3316 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3317 u_int8_t cksum, *e, match; 3318 int i; 3319 3320 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3321 sizeof(eeprom_data[0]), eeprom_data); 3322 3323 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3324 match = ~(match - 1); 3325 3326 cksum = 0x55; 3327 e = (u_int8_t *) eeprom_data; 3328 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3329 cksum += *e++; 3330 } 3331 if (cksum != match) { 3332 printf("%s: Checksum (%x) mismatch (%x)", 3333 sc->sc_dev.dv_xname, cksum, match); 3334 } 3335 3336 /* 3337 * Unrolled because it makes slightly more sense this way. 3338 * The DP83815 stores the MAC address in bit 0 of word 6 3339 * through bit 15 of word 8. 3340 */ 3341 ea = &eeprom_data[6]; 3342 enaddr[0] = ((*ea & 0x1) << 7); 3343 ea++; 3344 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3345 enaddr[1] = ((*ea & 0x1FE) >> 1); 3346 enaddr[2] = ((*ea & 0x1) << 7); 3347 ea++; 3348 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3349 enaddr[3] = ((*ea & 0x1FE) >> 1); 3350 enaddr[4] = ((*ea & 0x1) << 7); 3351 ea++; 3352 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3353 enaddr[5] = ((*ea & 0x1FE) >> 1); 3354 3355 /* 3356 * In case that's not weird enough, we also need to reverse 3357 * the bits in each byte. This all actually makes more sense 3358 * if you think about the EEPROM storage as an array of bits 3359 * being shifted into bytes, but that's not how we're looking 3360 * at it here... 3361 */ 3362 for (i = 0; i < 6 ;i++) 3363 enaddr[i] = bbr(enaddr[i]); 3364 } 3365 #endif /* DP83820 */ 3366 3367 /* 3368 * sip_mediastatus: [ifmedia interface function] 3369 * 3370 * Get the current interface media status. 3371 */ 3372 void 3373 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3374 { 3375 struct sip_softc *sc = ifp->if_softc; 3376 3377 mii_pollstat(&sc->sc_mii); 3378 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3379 ifmr->ifm_active = sc->sc_mii.mii_media_active; 3380 } 3381 3382 /* 3383 * sip_mediachange: [ifmedia interface function] 3384 * 3385 * Set hardware to newly-selected media. 3386 */ 3387 int 3388 SIP_DECL(mediachange)(struct ifnet *ifp) 3389 { 3390 struct sip_softc *sc = ifp->if_softc; 3391 3392 if (ifp->if_flags & IFF_UP) 3393 mii_mediachg(&sc->sc_mii); 3394 return (0); 3395 } 3396
Indexes created Tue Sep 30 11:09:46 GMT 2025