if_sip.c revision 1.78.2.1
1 /* $NetBSD: if_sip.c,v 1.78.2.1 2004/08/03 10:49:08 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.78.2.1 2004/08/03 10:49:08 skrll Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <machine/bus.h> 116 #include <machine/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/mii_bitbang.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/pci/if_sipreg.h> 128 129 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 130 #define SIP_DECL(x) __CONCAT(gsip_,x) 131 #else /* SiS900 and DP83815 */ 132 #define SIP_DECL(x) __CONCAT(sip_,x) 133 #endif 134 135 #define SIP_STR(x) __STRING(SIP_DECL(x)) 136 137 /* 138 * Transmit descriptor list size. This is arbitrary, but allocate 139 * enough descriptors for 128 pending transmissions, and 8 segments 140 * per packet (64 for DP83820 for jumbo frames). 141 * 142 * This MUST work out to a power of 2. 143 */ 144 #ifdef DP83820 145 #define SIP_NTXSEGS 64 146 #define SIP_NTXSEGS_ALLOC 16 147 #else 148 #define SIP_NTXSEGS 16 149 #define SIP_NTXSEGS_ALLOC 8 150 #endif 151 152 #define SIP_TXQUEUELEN 256 153 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 154 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 155 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 156 157 #if defined(DP83820) 158 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 159 #else 160 #define TX_DMAMAP_SIZE MCLBYTES 161 #endif 162 163 /* 164 * Receive descriptor list size. We have one Rx buffer per incoming 165 * packet, so this logic is a little simpler. 166 * 167 * Actually, on the DP83820, we allow the packet to consume more than 168 * one buffer, in order to support jumbo Ethernet frames. In that 169 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 170 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 171 * so we'd better be quick about handling receive interrupts. 172 */ 173 #if defined(DP83820) 174 #define SIP_NRXDESC 256 175 #else 176 #define SIP_NRXDESC 128 177 #endif /* DP83820 */ 178 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 179 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 180 181 /* 182 * Control structures are DMA'd to the SiS900 chip. We allocate them in 183 * a single clump that maps to a single DMA segment to make several things 184 * easier. 185 */ 186 struct sip_control_data { 187 /* 188 * The transmit descriptors. 189 */ 190 struct sip_desc scd_txdescs[SIP_NTXDESC]; 191 192 /* 193 * The receive descriptors. 194 */ 195 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 196 }; 197 198 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 199 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 200 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 201 202 /* 203 * Software state for transmit jobs. 204 */ 205 struct sip_txsoft { 206 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 207 bus_dmamap_t txs_dmamap; /* our DMA map */ 208 int txs_firstdesc; /* first descriptor in packet */ 209 int txs_lastdesc; /* last descriptor in packet */ 210 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 211 }; 212 213 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 214 215 /* 216 * Software state for receive jobs. 217 */ 218 struct sip_rxsoft { 219 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 220 bus_dmamap_t rxs_dmamap; /* our DMA map */ 221 }; 222 223 /* 224 * Software state per device. 225 */ 226 struct sip_softc { 227 struct device sc_dev; /* generic device information */ 228 bus_space_tag_t sc_st; /* bus space tag */ 229 bus_space_handle_t sc_sh; /* bus space handle */ 230 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 231 struct ethercom sc_ethercom; /* ethernet common data */ 232 void *sc_sdhook; /* shutdown hook */ 233 234 const struct sip_product *sc_model; /* which model are we? */ 235 int sc_rev; /* chip revision */ 236 237 void *sc_ih; /* interrupt cookie */ 238 239 struct mii_data sc_mii; /* MII/media information */ 240 241 struct callout sc_tick_ch; /* tick callout */ 242 243 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 244 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 245 246 /* 247 * Software state for transmit and receive descriptors. 248 */ 249 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 250 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 251 252 /* 253 * Control data structures. 254 */ 255 struct sip_control_data *sc_control_data; 256 #define sc_txdescs sc_control_data->scd_txdescs 257 #define sc_rxdescs sc_control_data->scd_rxdescs 258 259 #ifdef SIP_EVENT_COUNTERS 260 /* 261 * Event counters. 262 */ 263 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 264 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 265 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 266 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 267 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 268 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 269 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 270 struct evcnt sc_ev_rxpause; /* PAUSE received */ 271 #ifdef DP83820 272 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 273 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 274 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 275 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 276 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 277 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 278 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 279 #endif /* DP83820 */ 280 #endif /* SIP_EVENT_COUNTERS */ 281 282 u_int32_t sc_txcfg; /* prototype TXCFG register */ 283 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 284 u_int32_t sc_imr; /* prototype IMR register */ 285 u_int32_t sc_rfcr; /* prototype RFCR register */ 286 287 u_int32_t sc_cfg; /* prototype CFG register */ 288 289 #ifdef DP83820 290 u_int32_t sc_gpior; /* prototype GPIOR register */ 291 #endif /* DP83820 */ 292 293 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 294 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 295 296 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 297 298 int sc_flowflags; /* 802.3x flow control flags */ 299 #ifdef DP83820 300 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 301 #else 302 int sc_paused; /* paused indication */ 303 #endif 304 305 int sc_txfree; /* number of free Tx descriptors */ 306 int sc_txnext; /* next ready Tx descriptor */ 307 int sc_txwin; /* Tx descriptors since last intr */ 308 309 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 310 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 311 312 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 313 #if defined(DP83820) 314 int sc_rxdiscard; 315 int sc_rxlen; 316 struct mbuf *sc_rxhead; 317 struct mbuf *sc_rxtail; 318 struct mbuf **sc_rxtailp; 319 #endif /* DP83820 */ 320 321 #if NRND > 0 322 rndsource_element_t rnd_source; /* random source */ 323 #endif 324 }; 325 326 #ifdef DP83820 327 #define SIP_RXCHAIN_RESET(sc) \ 328 do { \ 329 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 330 *(sc)->sc_rxtailp = NULL; \ 331 (sc)->sc_rxlen = 0; \ 332 } while (/*CONSTCOND*/0) 333 334 #define SIP_RXCHAIN_LINK(sc, m) \ 335 do { \ 336 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 337 (sc)->sc_rxtailp = &(m)->m_next; \ 338 } while (/*CONSTCOND*/0) 339 #endif /* DP83820 */ 340 341 #ifdef SIP_EVENT_COUNTERS 342 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 343 #else 344 #define SIP_EVCNT_INCR(ev) /* nothing */ 345 #endif 346 347 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 348 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 349 350 #define SIP_CDTXSYNC(sc, x, n, ops) \ 351 do { \ 352 int __x, __n; \ 353 \ 354 __x = (x); \ 355 __n = (n); \ 356 \ 357 /* If it will wrap around, sync to the end of the ring. */ \ 358 if ((__x + __n) > SIP_NTXDESC) { \ 359 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 360 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 361 (SIP_NTXDESC - __x), (ops)); \ 362 __n -= (SIP_NTXDESC - __x); \ 363 __x = 0; \ 364 } \ 365 \ 366 /* Now sync whatever is left. */ \ 367 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 368 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 369 } while (0) 370 371 #define SIP_CDRXSYNC(sc, x, ops) \ 372 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 373 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 374 375 #ifdef DP83820 376 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 377 #define SIP_RXBUF_LEN (MCLBYTES - 8) 378 #else 379 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 380 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 381 #endif 382 #define SIP_INIT_RXDESC(sc, x) \ 383 do { \ 384 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 385 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 386 \ 387 __sipd->sipd_link = \ 388 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 389 __sipd->sipd_bufptr = \ 390 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 391 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 392 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 393 SIP_INIT_RXDESC_EXTSTS \ 394 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 395 } while (0) 396 397 #define SIP_CHIP_VERS(sc, v, p, r) \ 398 ((sc)->sc_model->sip_vendor == (v) && \ 399 (sc)->sc_model->sip_product == (p) && \ 400 (sc)->sc_rev == (r)) 401 402 #define SIP_CHIP_MODEL(sc, v, p) \ 403 ((sc)->sc_model->sip_vendor == (v) && \ 404 (sc)->sc_model->sip_product == (p)) 405 406 #if !defined(DP83820) 407 #define SIP_SIS900_REV(sc, rev) \ 408 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 409 #endif 410 411 #define SIP_TIMEOUT 1000 412 413 void SIP_DECL(start)(struct ifnet *); 414 void SIP_DECL(watchdog)(struct ifnet *); 415 int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 416 int SIP_DECL(init)(struct ifnet *); 417 void SIP_DECL(stop)(struct ifnet *, int); 418 419 void SIP_DECL(shutdown)(void *); 420 421 void SIP_DECL(reset)(struct sip_softc *); 422 void SIP_DECL(rxdrain)(struct sip_softc *); 423 int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 424 void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, u_int16_t *); 425 void SIP_DECL(tick)(void *); 426 427 #if !defined(DP83820) 428 void SIP_DECL(sis900_set_filter)(struct sip_softc *); 429 #endif /* ! DP83820 */ 430 void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 431 432 #if defined(DP83820) 433 void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 434 const struct pci_attach_args *, u_int8_t *); 435 #else 436 static void SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc); 437 void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 438 const struct pci_attach_args *, u_int8_t *); 439 void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 440 const struct pci_attach_args *, u_int8_t *); 441 #endif /* DP83820 */ 442 443 int SIP_DECL(intr)(void *); 444 void SIP_DECL(txintr)(struct sip_softc *); 445 void SIP_DECL(rxintr)(struct sip_softc *); 446 447 #if defined(DP83820) 448 int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 449 void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 450 void SIP_DECL(dp83820_mii_statchg)(struct device *); 451 #else 452 int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 453 void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 454 void SIP_DECL(sis900_mii_statchg)(struct device *); 455 456 int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 457 void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 458 void SIP_DECL(dp83815_mii_statchg)(struct device *); 459 #endif /* DP83820 */ 460 461 int SIP_DECL(mediachange)(struct ifnet *); 462 void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 463 464 int SIP_DECL(match)(struct device *, struct cfdata *, void *); 465 void SIP_DECL(attach)(struct device *, struct device *, void *); 466 467 int SIP_DECL(copy_small) = 0; 468 469 #ifdef DP83820 470 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 471 gsip_match, gsip_attach, NULL, NULL); 472 #else 473 CFATTACH_DECL(sip, sizeof(struct sip_softc), 474 sip_match, sip_attach, NULL, NULL); 475 #endif 476 477 /* 478 * Descriptions of the variants of the SiS900. 479 */ 480 struct sip_variant { 481 int (*sipv_mii_readreg)(struct device *, int, int); 482 void (*sipv_mii_writereg)(struct device *, int, int, int); 483 void (*sipv_mii_statchg)(struct device *); 484 void (*sipv_set_filter)(struct sip_softc *); 485 void (*sipv_read_macaddr)(struct sip_softc *, 486 const struct pci_attach_args *, u_int8_t *); 487 }; 488 489 u_int32_t SIP_DECL(mii_bitbang_read)(struct device *); 490 void SIP_DECL(mii_bitbang_write)(struct device *, u_int32_t); 491 492 const struct mii_bitbang_ops SIP_DECL(mii_bitbang_ops) = { 493 SIP_DECL(mii_bitbang_read), 494 SIP_DECL(mii_bitbang_write), 495 { 496 EROMAR_MDIO, /* MII_BIT_MDO */ 497 EROMAR_MDIO, /* MII_BIT_MDI */ 498 EROMAR_MDC, /* MII_BIT_MDC */ 499 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 500 0, /* MII_BIT_DIR_PHY_HOST */ 501 } 502 }; 503 504 #if defined(DP83820) 505 const struct sip_variant SIP_DECL(variant_dp83820) = { 506 SIP_DECL(dp83820_mii_readreg), 507 SIP_DECL(dp83820_mii_writereg), 508 SIP_DECL(dp83820_mii_statchg), 509 SIP_DECL(dp83815_set_filter), 510 SIP_DECL(dp83820_read_macaddr), 511 }; 512 #else 513 const struct sip_variant SIP_DECL(variant_sis900) = { 514 SIP_DECL(sis900_mii_readreg), 515 SIP_DECL(sis900_mii_writereg), 516 SIP_DECL(sis900_mii_statchg), 517 SIP_DECL(sis900_set_filter), 518 SIP_DECL(sis900_read_macaddr), 519 }; 520 521 const struct sip_variant SIP_DECL(variant_dp83815) = { 522 SIP_DECL(dp83815_mii_readreg), 523 SIP_DECL(dp83815_mii_writereg), 524 SIP_DECL(dp83815_mii_statchg), 525 SIP_DECL(dp83815_set_filter), 526 SIP_DECL(dp83815_read_macaddr), 527 }; 528 #endif /* DP83820 */ 529 530 /* 531 * Devices supported by this driver. 532 */ 533 const struct sip_product { 534 pci_vendor_id_t sip_vendor; 535 pci_product_id_t sip_product; 536 const char *sip_name; 537 const struct sip_variant *sip_variant; 538 } SIP_DECL(products)[] = { 539 #if defined(DP83820) 540 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 541 "NatSemi DP83820 Gigabit Ethernet", 542 &SIP_DECL(variant_dp83820) }, 543 #else 544 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 545 "SiS 900 10/100 Ethernet", 546 &SIP_DECL(variant_sis900) }, 547 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 548 "SiS 7016 10/100 Ethernet", 549 &SIP_DECL(variant_sis900) }, 550 551 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 552 "NatSemi DP83815 10/100 Ethernet", 553 &SIP_DECL(variant_dp83815) }, 554 #endif /* DP83820 */ 555 556 { 0, 0, 557 NULL, 558 NULL }, 559 }; 560 561 static const struct sip_product * 562 SIP_DECL(lookup)(const struct pci_attach_args *pa) 563 { 564 const struct sip_product *sip; 565 566 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 567 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 568 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 569 return (sip); 570 } 571 return (NULL); 572 } 573 574 #ifdef DP83820 575 /* 576 * I really hate stupid hardware vendors. There's a bit in the EEPROM 577 * which indicates if the card can do 64-bit data transfers. Unfortunately, 578 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 579 * which means we try to use 64-bit data transfers on those cards if we 580 * happen to be plugged into a 32-bit slot. 581 * 582 * What we do is use this table of cards known to be 64-bit cards. If 583 * you have a 64-bit card who's subsystem ID is not listed in this table, 584 * send the output of "pcictl dump ..." of the device to me so that your 585 * card will use the 64-bit data path when plugged into a 64-bit slot. 586 * 587 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 588 * June 30, 2002 589 */ 590 static int 591 SIP_DECL(check_64bit)(const struct pci_attach_args *pa) 592 { 593 static const struct { 594 pci_vendor_id_t c64_vendor; 595 pci_product_id_t c64_product; 596 } card64[] = { 597 /* Asante GigaNIX */ 598 { 0x128a, 0x0002 }, 599 600 /* Accton EN1407-T, Planex GN-1000TE */ 601 { 0x1113, 0x1407 }, 602 603 /* Netgear GA-621 */ 604 { 0x1385, 0x621a }, 605 606 /* SMC EZ Card */ 607 { 0x10b8, 0x9462 }, 608 609 { 0, 0} 610 }; 611 pcireg_t subsys; 612 int i; 613 614 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 615 616 for (i = 0; card64[i].c64_vendor != 0; i++) { 617 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 618 PCI_PRODUCT(subsys) == card64[i].c64_product) 619 return (1); 620 } 621 622 return (0); 623 } 624 #endif /* DP83820 */ 625 626 int 627 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 628 { 629 struct pci_attach_args *pa = aux; 630 631 if (SIP_DECL(lookup)(pa) != NULL) 632 return (1); 633 634 return (0); 635 } 636 637 void 638 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 639 { 640 struct sip_softc *sc = (struct sip_softc *) self; 641 struct pci_attach_args *pa = aux; 642 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 643 pci_chipset_tag_t pc = pa->pa_pc; 644 pci_intr_handle_t ih; 645 const char *intrstr = NULL; 646 bus_space_tag_t iot, memt; 647 bus_space_handle_t ioh, memh; 648 bus_dma_segment_t seg; 649 int ioh_valid, memh_valid; 650 int i, rseg, error; 651 const struct sip_product *sip; 652 pcireg_t pmode; 653 u_int8_t enaddr[ETHER_ADDR_LEN]; 654 int pmreg; 655 #ifdef DP83820 656 pcireg_t memtype; 657 u_int32_t reg; 658 #endif /* DP83820 */ 659 660 callout_init(&sc->sc_tick_ch); 661 662 sip = SIP_DECL(lookup)(pa); 663 if (sip == NULL) { 664 printf("\n"); 665 panic(SIP_STR(attach) ": impossible"); 666 } 667 sc->sc_rev = PCI_REVISION(pa->pa_class); 668 669 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 670 671 sc->sc_model = sip; 672 673 /* 674 * XXX Work-around broken PXE firmware on some boards. 675 * 676 * The DP83815 shares an address decoder with the MEM BAR 677 * and the ROM BAR. Make sure the ROM BAR is disabled, 678 * so that memory mapped access works. 679 */ 680 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 681 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 682 ~PCI_MAPREG_ROM_ENABLE); 683 684 /* 685 * Map the device. 686 */ 687 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 688 PCI_MAPREG_TYPE_IO, 0, 689 &iot, &ioh, NULL, NULL) == 0); 690 #ifdef DP83820 691 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 692 switch (memtype) { 693 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 694 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 695 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 696 memtype, 0, &memt, &memh, NULL, NULL) == 0); 697 break; 698 default: 699 memh_valid = 0; 700 } 701 #else 702 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 703 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 704 &memt, &memh, NULL, NULL) == 0); 705 #endif /* DP83820 */ 706 707 if (memh_valid) { 708 sc->sc_st = memt; 709 sc->sc_sh = memh; 710 } else if (ioh_valid) { 711 sc->sc_st = iot; 712 sc->sc_sh = ioh; 713 } else { 714 printf("%s: unable to map device registers\n", 715 sc->sc_dev.dv_xname); 716 return; 717 } 718 719 sc->sc_dmat = pa->pa_dmat; 720 721 /* 722 * Make sure bus mastering is enabled. Also make sure 723 * Write/Invalidate is enabled if we're allowed to use it. 724 */ 725 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 726 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 727 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 728 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 729 pmreg | PCI_COMMAND_MASTER_ENABLE); 730 731 /* Get it out of power save mode if needed. */ 732 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 733 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 734 PCI_PMCSR_STATE_MASK; 735 if (pmode == PCI_PMCSR_STATE_D3) { 736 /* 737 * The card has lost all configuration data in 738 * this state, so punt. 739 */ 740 printf("%s: unable to wake up from power state D3\n", 741 sc->sc_dev.dv_xname); 742 return; 743 } 744 if (pmode != PCI_PMCSR_STATE_D0) { 745 printf("%s: waking up from power state D%d\n", 746 sc->sc_dev.dv_xname, pmode); 747 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 748 PCI_PMCSR_STATE_D0); 749 } 750 } 751 752 /* 753 * Map and establish our interrupt. 754 */ 755 if (pci_intr_map(pa, &ih)) { 756 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 757 return; 758 } 759 intrstr = pci_intr_string(pc, ih); 760 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 761 if (sc->sc_ih == NULL) { 762 printf("%s: unable to establish interrupt", 763 sc->sc_dev.dv_xname); 764 if (intrstr != NULL) 765 printf(" at %s", intrstr); 766 printf("\n"); 767 return; 768 } 769 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 770 771 SIMPLEQ_INIT(&sc->sc_txfreeq); 772 SIMPLEQ_INIT(&sc->sc_txdirtyq); 773 774 /* 775 * Allocate the control data structures, and create and load the 776 * DMA map for it. 777 */ 778 if ((error = bus_dmamem_alloc(sc->sc_dmat, 779 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 780 0)) != 0) { 781 printf("%s: unable to allocate control data, error = %d\n", 782 sc->sc_dev.dv_xname, error); 783 goto fail_0; 784 } 785 786 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 787 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 788 BUS_DMA_COHERENT)) != 0) { 789 printf("%s: unable to map control data, error = %d\n", 790 sc->sc_dev.dv_xname, error); 791 goto fail_1; 792 } 793 794 if ((error = bus_dmamap_create(sc->sc_dmat, 795 sizeof(struct sip_control_data), 1, 796 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 797 printf("%s: unable to create control data DMA map, " 798 "error = %d\n", sc->sc_dev.dv_xname, error); 799 goto fail_2; 800 } 801 802 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 803 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 804 0)) != 0) { 805 printf("%s: unable to load control data DMA map, error = %d\n", 806 sc->sc_dev.dv_xname, error); 807 goto fail_3; 808 } 809 810 /* 811 * Create the transmit buffer DMA maps. 812 */ 813 for (i = 0; i < SIP_TXQUEUELEN; i++) { 814 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 815 SIP_NTXSEGS, MCLBYTES, 0, 0, 816 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 817 printf("%s: unable to create tx DMA map %d, " 818 "error = %d\n", sc->sc_dev.dv_xname, i, error); 819 goto fail_4; 820 } 821 } 822 823 /* 824 * Create the receive buffer DMA maps. 825 */ 826 for (i = 0; i < SIP_NRXDESC; i++) { 827 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 828 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 829 printf("%s: unable to create rx DMA map %d, " 830 "error = %d\n", sc->sc_dev.dv_xname, i, error); 831 goto fail_5; 832 } 833 sc->sc_rxsoft[i].rxs_mbuf = NULL; 834 } 835 836 /* 837 * Reset the chip to a known state. 838 */ 839 SIP_DECL(reset)(sc); 840 841 /* 842 * Read the Ethernet address from the EEPROM. This might 843 * also fetch other stuff from the EEPROM and stash it 844 * in the softc. 845 */ 846 sc->sc_cfg = 0; 847 #if !defined(DP83820) 848 if (SIP_SIS900_REV(sc,SIS_REV_635) || 849 SIP_SIS900_REV(sc,SIS_REV_900B)) 850 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 851 852 if (SIP_SIS900_REV(sc,SIS_REV_635) || 853 SIP_SIS900_REV(sc,SIS_REV_960) || 854 SIP_SIS900_REV(sc,SIS_REV_900B)) 855 sc->sc_cfg |= (bus_space_read_4(sc->sc_st, sc->sc_sh, 856 SIP_CFG) & CFG_EDBMASTEN); 857 #endif 858 859 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 860 861 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 862 ether_sprintf(enaddr)); 863 864 /* 865 * Initialize the configuration register: aggressive PCI 866 * bus request algorithm, default backoff, default OW timer, 867 * default parity error detection. 868 * 869 * NOTE: "Big endian mode" is useless on the SiS900 and 870 * friends -- it affects packet data, not descriptors. 871 */ 872 #ifdef DP83820 873 /* 874 * Cause the chip to load configuration data from the EEPROM. 875 */ 876 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 877 for (i = 0; i < 10000; i++) { 878 delay(10); 879 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 880 PTSCR_EELOAD_EN) == 0) 881 break; 882 } 883 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 884 PTSCR_EELOAD_EN) { 885 printf("%s: timeout loading configuration from EEPROM\n", 886 sc->sc_dev.dv_xname); 887 return; 888 } 889 890 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 891 892 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 893 if (reg & CFG_PCI64_DET) { 894 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 895 /* 896 * Check to see if this card is 64-bit. If so, enable 64-bit 897 * data transfers. 898 * 899 * We can't use the DATA64_EN bit in the EEPROM, because 900 * vendors of 32-bit cards fail to clear that bit in many 901 * cases (yet the card still detects that it's in a 64-bit 902 * slot; go figure). 903 */ 904 if (SIP_DECL(check_64bit)(pa)) { 905 sc->sc_cfg |= CFG_DATA64_EN; 906 printf(", using 64-bit data transfers"); 907 } 908 printf("\n"); 909 } 910 911 /* 912 * XXX Need some PCI flags indicating support for 913 * XXX 64-bit addressing. 914 */ 915 #if 0 916 if (reg & CFG_M64ADDR) 917 sc->sc_cfg |= CFG_M64ADDR; 918 if (reg & CFG_T64ADDR) 919 sc->sc_cfg |= CFG_T64ADDR; 920 #endif 921 922 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 923 const char *sep = ""; 924 printf("%s: using ", sc->sc_dev.dv_xname); 925 if (reg & CFG_EXT_125) { 926 sc->sc_cfg |= CFG_EXT_125; 927 printf("%s125MHz clock", sep); 928 sep = ", "; 929 } 930 if (reg & CFG_TBI_EN) { 931 sc->sc_cfg |= CFG_TBI_EN; 932 printf("%sten-bit interface", sep); 933 sep = ", "; 934 } 935 printf("\n"); 936 } 937 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 938 (reg & CFG_MRM_DIS) != 0) 939 sc->sc_cfg |= CFG_MRM_DIS; 940 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 941 (reg & CFG_MWI_DIS) != 0) 942 sc->sc_cfg |= CFG_MWI_DIS; 943 944 /* 945 * Use the extended descriptor format on the DP83820. This 946 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 947 * checksumming. 948 */ 949 sc->sc_cfg |= CFG_EXTSTS_EN; 950 #endif /* DP83820 */ 951 952 /* 953 * Initialize our media structures and probe the MII. 954 */ 955 sc->sc_mii.mii_ifp = ifp; 956 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 957 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 958 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 959 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, SIP_DECL(mediachange), 960 SIP_DECL(mediastatus)); 961 962 /* 963 * XXX We cannot handle flow control on the DP83815. 964 */ 965 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 966 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 967 MII_OFFSET_ANY, 0); 968 else 969 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 970 MII_OFFSET_ANY, MIIF_DOPAUSE); 971 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 972 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 973 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 974 } else 975 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 976 977 ifp = &sc->sc_ethercom.ec_if; 978 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 979 ifp->if_softc = sc; 980 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 981 ifp->if_ioctl = SIP_DECL(ioctl); 982 ifp->if_start = SIP_DECL(start); 983 ifp->if_watchdog = SIP_DECL(watchdog); 984 ifp->if_init = SIP_DECL(init); 985 ifp->if_stop = SIP_DECL(stop); 986 IFQ_SET_READY(&ifp->if_snd); 987 988 /* 989 * We can support 802.1Q VLAN-sized frames. 990 */ 991 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 992 993 #ifdef DP83820 994 /* 995 * And the DP83820 can do VLAN tagging in hardware, and 996 * support the jumbo Ethernet MTU. 997 */ 998 sc->sc_ethercom.ec_capabilities |= 999 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1000 1001 /* 1002 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1003 * in hardware. 1004 */ 1005 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 1006 IFCAP_CSUM_UDPv4; 1007 #endif /* DP83820 */ 1008 1009 /* 1010 * Attach the interface. 1011 */ 1012 if_attach(ifp); 1013 ether_ifattach(ifp, enaddr); 1014 #if NRND > 0 1015 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1016 RND_TYPE_NET, 0); 1017 #endif 1018 1019 /* 1020 * The number of bytes that must be available in 1021 * the Tx FIFO before the bus master can DMA more 1022 * data into the FIFO. 1023 */ 1024 sc->sc_tx_fill_thresh = 64 / 32; 1025 1026 /* 1027 * Start at a drain threshold of 512 bytes. We will 1028 * increase it if a DMA underrun occurs. 1029 * 1030 * XXX The minimum value of this variable should be 1031 * tuned. We may be able to improve performance 1032 * by starting with a lower value. That, however, 1033 * may trash the first few outgoing packets if the 1034 * PCI bus is saturated. 1035 */ 1036 #ifdef DP83820 1037 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1038 #else 1039 sc->sc_tx_drain_thresh = 1504 / 32; 1040 #endif 1041 1042 /* 1043 * Initialize the Rx FIFO drain threshold. 1044 * 1045 * This is in units of 8 bytes. 1046 * 1047 * We should never set this value lower than 2; 14 bytes are 1048 * required to filter the packet. 1049 */ 1050 sc->sc_rx_drain_thresh = 128 / 8; 1051 1052 #ifdef SIP_EVENT_COUNTERS 1053 /* 1054 * Attach event counters. 1055 */ 1056 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1057 NULL, sc->sc_dev.dv_xname, "txsstall"); 1058 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1059 NULL, sc->sc_dev.dv_xname, "txdstall"); 1060 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1061 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1062 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1063 NULL, sc->sc_dev.dv_xname, "txdintr"); 1064 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1065 NULL, sc->sc_dev.dv_xname, "txiintr"); 1066 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1067 NULL, sc->sc_dev.dv_xname, "rxintr"); 1068 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1069 NULL, sc->sc_dev.dv_xname, "hiberr"); 1070 #ifndef DP83820 1071 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1072 NULL, sc->sc_dev.dv_xname, "rxpause"); 1073 #endif /* !DP83820 */ 1074 #ifdef DP83820 1075 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1076 NULL, sc->sc_dev.dv_xname, "rxpause"); 1077 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1078 NULL, sc->sc_dev.dv_xname, "txpause"); 1079 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1080 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1081 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1082 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1083 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1084 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1085 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1086 NULL, sc->sc_dev.dv_xname, "txipsum"); 1087 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1088 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1089 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1090 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1091 #endif /* DP83820 */ 1092 #endif /* SIP_EVENT_COUNTERS */ 1093 1094 /* 1095 * Make sure the interface is shutdown during reboot. 1096 */ 1097 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 1098 if (sc->sc_sdhook == NULL) 1099 printf("%s: WARNING: unable to establish shutdown hook\n", 1100 sc->sc_dev.dv_xname); 1101 return; 1102 1103 /* 1104 * Free any resources we've allocated during the failed attach 1105 * attempt. Do this in reverse order and fall through. 1106 */ 1107 fail_5: 1108 for (i = 0; i < SIP_NRXDESC; i++) { 1109 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1110 bus_dmamap_destroy(sc->sc_dmat, 1111 sc->sc_rxsoft[i].rxs_dmamap); 1112 } 1113 fail_4: 1114 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1115 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1116 bus_dmamap_destroy(sc->sc_dmat, 1117 sc->sc_txsoft[i].txs_dmamap); 1118 } 1119 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1120 fail_3: 1121 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1122 fail_2: 1123 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1124 sizeof(struct sip_control_data)); 1125 fail_1: 1126 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1127 fail_0: 1128 return; 1129 } 1130 1131 /* 1132 * sip_shutdown: 1133 * 1134 * Make sure the interface is stopped at reboot time. 1135 */ 1136 void 1137 SIP_DECL(shutdown)(void *arg) 1138 { 1139 struct sip_softc *sc = arg; 1140 1141 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1142 } 1143 1144 /* 1145 * sip_start: [ifnet interface function] 1146 * 1147 * Start packet transmission on the interface. 1148 */ 1149 void 1150 SIP_DECL(start)(struct ifnet *ifp) 1151 { 1152 struct sip_softc *sc = ifp->if_softc; 1153 struct mbuf *m0; 1154 #ifndef DP83820 1155 struct mbuf *m; 1156 #endif 1157 struct sip_txsoft *txs; 1158 bus_dmamap_t dmamap; 1159 int error, nexttx, lasttx, seg; 1160 int ofree = sc->sc_txfree; 1161 #if 0 1162 int firsttx = sc->sc_txnext; 1163 #endif 1164 #ifdef DP83820 1165 struct m_tag *mtag; 1166 u_int32_t extsts; 1167 #endif 1168 1169 #ifndef DP83820 1170 /* 1171 * If we've been told to pause, don't transmit any more packets. 1172 */ 1173 if (sc->sc_paused) 1174 ifp->if_flags |= IFF_OACTIVE; 1175 #endif 1176 1177 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1178 return; 1179 1180 /* 1181 * Loop through the send queue, setting up transmit descriptors 1182 * until we drain the queue, or use up all available transmit 1183 * descriptors. 1184 */ 1185 for (;;) { 1186 /* Get a work queue entry. */ 1187 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1188 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1189 break; 1190 } 1191 1192 /* 1193 * Grab a packet off the queue. 1194 */ 1195 IFQ_POLL(&ifp->if_snd, m0); 1196 if (m0 == NULL) 1197 break; 1198 #ifndef DP83820 1199 m = NULL; 1200 #endif 1201 1202 dmamap = txs->txs_dmamap; 1203 1204 #ifdef DP83820 1205 /* 1206 * Load the DMA map. If this fails, the packet either 1207 * didn't fit in the allotted number of segments, or we 1208 * were short on resources. For the too-many-segments 1209 * case, we simply report an error and drop the packet, 1210 * since we can't sanely copy a jumbo packet to a single 1211 * buffer. 1212 */ 1213 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1214 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1215 if (error) { 1216 if (error == EFBIG) { 1217 printf("%s: Tx packet consumes too many " 1218 "DMA segments, dropping...\n", 1219 sc->sc_dev.dv_xname); 1220 IFQ_DEQUEUE(&ifp->if_snd, m0); 1221 m_freem(m0); 1222 continue; 1223 } 1224 /* 1225 * Short on resources, just stop for now. 1226 */ 1227 break; 1228 } 1229 #else /* DP83820 */ 1230 /* 1231 * Load the DMA map. If this fails, the packet either 1232 * didn't fit in the alloted number of segments, or we 1233 * were short on resources. In this case, we'll copy 1234 * and try again. 1235 */ 1236 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1237 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1238 MGETHDR(m, M_DONTWAIT, MT_DATA); 1239 if (m == NULL) { 1240 printf("%s: unable to allocate Tx mbuf\n", 1241 sc->sc_dev.dv_xname); 1242 break; 1243 } 1244 if (m0->m_pkthdr.len > MHLEN) { 1245 MCLGET(m, M_DONTWAIT); 1246 if ((m->m_flags & M_EXT) == 0) { 1247 printf("%s: unable to allocate Tx " 1248 "cluster\n", sc->sc_dev.dv_xname); 1249 m_freem(m); 1250 break; 1251 } 1252 } 1253 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1254 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1255 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1256 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1257 if (error) { 1258 printf("%s: unable to load Tx buffer, " 1259 "error = %d\n", sc->sc_dev.dv_xname, error); 1260 break; 1261 } 1262 } 1263 #endif /* DP83820 */ 1264 1265 /* 1266 * Ensure we have enough descriptors free to describe 1267 * the packet. Note, we always reserve one descriptor 1268 * at the end of the ring as a termination point, to 1269 * prevent wrap-around. 1270 */ 1271 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1272 /* 1273 * Not enough free descriptors to transmit this 1274 * packet. We haven't committed anything yet, 1275 * so just unload the DMA map, put the packet 1276 * back on the queue, and punt. Notify the upper 1277 * layer that there are not more slots left. 1278 * 1279 * XXX We could allocate an mbuf and copy, but 1280 * XXX is it worth it? 1281 */ 1282 ifp->if_flags |= IFF_OACTIVE; 1283 bus_dmamap_unload(sc->sc_dmat, dmamap); 1284 #ifndef DP83820 1285 if (m != NULL) 1286 m_freem(m); 1287 #endif 1288 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1289 break; 1290 } 1291 1292 IFQ_DEQUEUE(&ifp->if_snd, m0); 1293 #ifndef DP83820 1294 if (m != NULL) { 1295 m_freem(m0); 1296 m0 = m; 1297 } 1298 #endif 1299 1300 /* 1301 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1302 */ 1303 1304 /* Sync the DMA map. */ 1305 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1306 BUS_DMASYNC_PREWRITE); 1307 1308 /* 1309 * Initialize the transmit descriptors. 1310 */ 1311 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1312 seg < dmamap->dm_nsegs; 1313 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1314 /* 1315 * If this is the first descriptor we're 1316 * enqueueing, don't set the OWN bit just 1317 * yet. That could cause a race condition. 1318 * We'll do it below. 1319 */ 1320 sc->sc_txdescs[nexttx].sipd_bufptr = 1321 htole32(dmamap->dm_segs[seg].ds_addr); 1322 sc->sc_txdescs[nexttx].sipd_cmdsts = 1323 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1324 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1325 #ifdef DP83820 1326 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1327 #endif /* DP83820 */ 1328 lasttx = nexttx; 1329 } 1330 1331 /* Clear the MORE bit on the last segment. */ 1332 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1333 1334 /* 1335 * If we're in the interrupt delay window, delay the 1336 * interrupt. 1337 */ 1338 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1339 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1340 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1341 htole32(CMDSTS_INTR); 1342 sc->sc_txwin = 0; 1343 } 1344 1345 #ifdef DP83820 1346 /* 1347 * If VLANs are enabled and the packet has a VLAN tag, set 1348 * up the descriptor to encapsulate the packet for us. 1349 * 1350 * This apparently has to be on the last descriptor of 1351 * the packet. 1352 */ 1353 if (sc->sc_ethercom.ec_nvlans != 0 && 1354 (mtag = m_tag_find(m0, PACKET_TAG_VLAN, NULL)) != NULL) { 1355 sc->sc_txdescs[lasttx].sipd_extsts |= 1356 htole32(EXTSTS_VPKT | 1357 (*(u_int *)(mtag + 1) & EXTSTS_VTCI)); 1358 } 1359 1360 /* 1361 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1362 * checksumming, set up the descriptor to do this work 1363 * for us. 1364 * 1365 * This apparently has to be on the first descriptor of 1366 * the packet. 1367 * 1368 * Byte-swap constants so the compiler can optimize. 1369 */ 1370 extsts = 0; 1371 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1372 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1373 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1374 extsts |= htole32(EXTSTS_IPPKT); 1375 } 1376 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1377 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1378 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1379 extsts |= htole32(EXTSTS_TCPPKT); 1380 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1381 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1382 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1383 extsts |= htole32(EXTSTS_UDPPKT); 1384 } 1385 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1386 #endif /* DP83820 */ 1387 1388 /* Sync the descriptors we're using. */ 1389 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1390 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1391 1392 /* 1393 * The entire packet is set up. Give the first descrptor 1394 * to the chip now. 1395 */ 1396 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1397 htole32(CMDSTS_OWN); 1398 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1399 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1400 1401 /* 1402 * Store a pointer to the packet so we can free it later, 1403 * and remember what txdirty will be once the packet is 1404 * done. 1405 */ 1406 txs->txs_mbuf = m0; 1407 txs->txs_firstdesc = sc->sc_txnext; 1408 txs->txs_lastdesc = lasttx; 1409 1410 /* Advance the tx pointer. */ 1411 sc->sc_txfree -= dmamap->dm_nsegs; 1412 sc->sc_txnext = nexttx; 1413 1414 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1415 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1416 1417 #if NBPFILTER > 0 1418 /* 1419 * Pass the packet to any BPF listeners. 1420 */ 1421 if (ifp->if_bpf) 1422 bpf_mtap(ifp->if_bpf, m0); 1423 #endif /* NBPFILTER > 0 */ 1424 } 1425 1426 if (txs == NULL || sc->sc_txfree == 0) { 1427 /* No more slots left; notify upper layer. */ 1428 ifp->if_flags |= IFF_OACTIVE; 1429 } 1430 1431 if (sc->sc_txfree != ofree) { 1432 /* 1433 * Start the transmit process. Note, the manual says 1434 * that if there are no pending transmissions in the 1435 * chip's internal queue (indicated by TXE being clear), 1436 * then the driver software must set the TXDP to the 1437 * first descriptor to be transmitted. However, if we 1438 * do this, it causes serious performance degredation on 1439 * the DP83820 under load, not setting TXDP doesn't seem 1440 * to adversely affect the SiS 900 or DP83815. 1441 * 1442 * Well, I guess it wouldn't be the first time a manual 1443 * has lied -- and they could be speaking of the NULL- 1444 * terminated descriptor list case, rather than OWN- 1445 * terminated rings. 1446 */ 1447 #if 0 1448 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1449 CR_TXE) == 0) { 1450 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1451 SIP_CDTXADDR(sc, firsttx)); 1452 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1453 } 1454 #else 1455 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1456 #endif 1457 1458 /* Set a watchdog timer in case the chip flakes out. */ 1459 #ifdef DP83820 1460 /* Gigabit autonegotiation takes 5 seconds. */ 1461 ifp->if_timer = 10; 1462 #else 1463 ifp->if_timer = 5; 1464 #endif 1465 } 1466 } 1467 1468 /* 1469 * sip_watchdog: [ifnet interface function] 1470 * 1471 * Watchdog timer handler. 1472 */ 1473 void 1474 SIP_DECL(watchdog)(struct ifnet *ifp) 1475 { 1476 struct sip_softc *sc = ifp->if_softc; 1477 1478 /* 1479 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1480 * If we get a timeout, try and sweep up transmit descriptors. 1481 * If we manage to sweep them all up, ignore the lack of 1482 * interrupt. 1483 */ 1484 SIP_DECL(txintr)(sc); 1485 1486 if (sc->sc_txfree != SIP_NTXDESC) { 1487 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1488 ifp->if_oerrors++; 1489 1490 /* Reset the interface. */ 1491 (void) SIP_DECL(init)(ifp); 1492 } else if (ifp->if_flags & IFF_DEBUG) 1493 printf("%s: recovered from device timeout\n", 1494 sc->sc_dev.dv_xname); 1495 1496 /* Try to get more packets going. */ 1497 SIP_DECL(start)(ifp); 1498 } 1499 1500 /* 1501 * sip_ioctl: [ifnet interface function] 1502 * 1503 * Handle control requests from the operator. 1504 */ 1505 int 1506 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1507 { 1508 struct sip_softc *sc = ifp->if_softc; 1509 struct ifreq *ifr = (struct ifreq *)data; 1510 int s, error; 1511 1512 s = splnet(); 1513 1514 switch (cmd) { 1515 case SIOCSIFMEDIA: 1516 /* Flow control requires full-duplex mode. */ 1517 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1518 (ifr->ifr_media & IFM_FDX) == 0) 1519 ifr->ifr_media &= ~IFM_ETH_FMASK; 1520 #ifdef DP83820 1521 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1522 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1523 /* We can do both TXPAUSE and RXPAUSE. */ 1524 ifr->ifr_media |= 1525 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1526 } 1527 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1528 } 1529 #else 1530 /* XXX */ 1531 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1532 ifr->ifr_media &= ~IFM_ETH_FMASK; 1533 1534 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1535 if (ifr->ifr_media & IFM_FLOW) { 1536 /* 1537 * Both TXPAUSE and RXPAUSE must be set. 1538 * (SiS900 and DP83815 don't have PAUSE_ASYM 1539 * feature.) 1540 * 1541 * XXX Can SiS900 and DP83815 send PAUSE? 1542 */ 1543 ifr->ifr_media |= 1544 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1545 } 1546 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1547 } 1548 #endif 1549 /* FALLTHROUGH */ 1550 case SIOCGIFMEDIA: 1551 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1552 break; 1553 1554 default: 1555 error = ether_ioctl(ifp, cmd, data); 1556 if (error == ENETRESET) { 1557 /* 1558 * Multicast list has changed; set the hardware filter 1559 * accordingly. 1560 */ 1561 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1562 error = 0; 1563 } 1564 break; 1565 } 1566 1567 /* Try to get more packets going. */ 1568 SIP_DECL(start)(ifp); 1569 1570 splx(s); 1571 return (error); 1572 } 1573 1574 /* 1575 * sip_intr: 1576 * 1577 * Interrupt service routine. 1578 */ 1579 int 1580 SIP_DECL(intr)(void *arg) 1581 { 1582 struct sip_softc *sc = arg; 1583 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1584 u_int32_t isr; 1585 int handled = 0; 1586 1587 /* Disable interrupts. */ 1588 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1589 1590 for (;;) { 1591 /* Reading clears interrupt. */ 1592 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1593 if ((isr & sc->sc_imr) == 0) 1594 break; 1595 1596 #if NRND > 0 1597 if (RND_ENABLED(&sc->rnd_source)) 1598 rnd_add_uint32(&sc->rnd_source, isr); 1599 #endif 1600 1601 handled = 1; 1602 1603 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1604 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1605 1606 /* Grab any new packets. */ 1607 SIP_DECL(rxintr)(sc); 1608 1609 if (isr & ISR_RXORN) { 1610 printf("%s: receive FIFO overrun\n", 1611 sc->sc_dev.dv_xname); 1612 1613 /* XXX adjust rx_drain_thresh? */ 1614 } 1615 1616 if (isr & ISR_RXIDLE) { 1617 printf("%s: receive ring overrun\n", 1618 sc->sc_dev.dv_xname); 1619 1620 /* Get the receive process going again. */ 1621 bus_space_write_4(sc->sc_st, sc->sc_sh, 1622 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1623 bus_space_write_4(sc->sc_st, sc->sc_sh, 1624 SIP_CR, CR_RXE); 1625 } 1626 } 1627 1628 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1629 #ifdef SIP_EVENT_COUNTERS 1630 if (isr & ISR_TXDESC) 1631 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1632 else if (isr & ISR_TXIDLE) 1633 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1634 #endif 1635 1636 /* Sweep up transmit descriptors. */ 1637 SIP_DECL(txintr)(sc); 1638 1639 if (isr & ISR_TXURN) { 1640 u_int32_t thresh; 1641 1642 printf("%s: transmit FIFO underrun", 1643 sc->sc_dev.dv_xname); 1644 1645 thresh = sc->sc_tx_drain_thresh + 1; 1646 if (thresh <= TXCFG_DRTH && 1647 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1648 (sc->sc_tx_fill_thresh * 32))) { 1649 printf("; increasing Tx drain " 1650 "threshold to %u bytes\n", 1651 thresh * 32); 1652 sc->sc_tx_drain_thresh = thresh; 1653 (void) SIP_DECL(init)(ifp); 1654 } else { 1655 (void) SIP_DECL(init)(ifp); 1656 printf("\n"); 1657 } 1658 } 1659 } 1660 1661 #if !defined(DP83820) 1662 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1663 if (isr & ISR_PAUSE_ST) { 1664 sc->sc_paused = 1; 1665 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1666 ifp->if_flags |= IFF_OACTIVE; 1667 } 1668 if (isr & ISR_PAUSE_END) { 1669 sc->sc_paused = 0; 1670 ifp->if_flags &= ~IFF_OACTIVE; 1671 } 1672 } 1673 #endif /* ! DP83820 */ 1674 1675 if (isr & ISR_HIBERR) { 1676 int want_init = 0; 1677 1678 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1679 1680 #define PRINTERR(bit, str) \ 1681 do { \ 1682 if ((isr & (bit)) != 0) { \ 1683 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1684 printf("%s: %s\n", \ 1685 sc->sc_dev.dv_xname, str); \ 1686 want_init = 1; \ 1687 } \ 1688 } while (/*CONSTCOND*/0) 1689 1690 PRINTERR(ISR_DPERR, "parity error"); 1691 PRINTERR(ISR_SSERR, "system error"); 1692 PRINTERR(ISR_RMABT, "master abort"); 1693 PRINTERR(ISR_RTABT, "target abort"); 1694 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1695 /* 1696 * Ignore: 1697 * Tx reset complete 1698 * Rx reset complete 1699 */ 1700 if (want_init) 1701 (void) SIP_DECL(init)(ifp); 1702 #undef PRINTERR 1703 } 1704 } 1705 1706 /* Re-enable interrupts. */ 1707 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1708 1709 /* Try to get more packets going. */ 1710 SIP_DECL(start)(ifp); 1711 1712 return (handled); 1713 } 1714 1715 /* 1716 * sip_txintr: 1717 * 1718 * Helper; handle transmit interrupts. 1719 */ 1720 void 1721 SIP_DECL(txintr)(struct sip_softc *sc) 1722 { 1723 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1724 struct sip_txsoft *txs; 1725 u_int32_t cmdsts; 1726 1727 #ifndef DP83820 1728 if (sc->sc_paused == 0) 1729 #endif 1730 ifp->if_flags &= ~IFF_OACTIVE; 1731 1732 /* 1733 * Go through our Tx list and free mbufs for those 1734 * frames which have been transmitted. 1735 */ 1736 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1737 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1738 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1739 1740 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1741 if (cmdsts & CMDSTS_OWN) 1742 break; 1743 1744 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1745 1746 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1747 1748 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1749 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1750 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1751 m_freem(txs->txs_mbuf); 1752 txs->txs_mbuf = NULL; 1753 1754 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1755 1756 /* 1757 * Check for errors and collisions. 1758 */ 1759 if (cmdsts & 1760 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1761 ifp->if_oerrors++; 1762 if (cmdsts & CMDSTS_Tx_EC) 1763 ifp->if_collisions += 16; 1764 if (ifp->if_flags & IFF_DEBUG) { 1765 if (cmdsts & CMDSTS_Tx_ED) 1766 printf("%s: excessive deferral\n", 1767 sc->sc_dev.dv_xname); 1768 if (cmdsts & CMDSTS_Tx_EC) 1769 printf("%s: excessive collisions\n", 1770 sc->sc_dev.dv_xname); 1771 } 1772 } else { 1773 /* Packet was transmitted successfully. */ 1774 ifp->if_opackets++; 1775 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1776 } 1777 } 1778 1779 /* 1780 * If there are no more pending transmissions, cancel the watchdog 1781 * timer. 1782 */ 1783 if (txs == NULL) { 1784 ifp->if_timer = 0; 1785 sc->sc_txwin = 0; 1786 } 1787 } 1788 1789 #if defined(DP83820) 1790 /* 1791 * sip_rxintr: 1792 * 1793 * Helper; handle receive interrupts. 1794 */ 1795 void 1796 SIP_DECL(rxintr)(struct sip_softc *sc) 1797 { 1798 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1799 struct sip_rxsoft *rxs; 1800 struct mbuf *m, *tailm; 1801 u_int32_t cmdsts, extsts; 1802 int i, len, frame_len; 1803 1804 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1805 rxs = &sc->sc_rxsoft[i]; 1806 1807 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1808 1809 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1810 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1811 1812 /* 1813 * NOTE: OWN is set if owned by _consumer_. We're the 1814 * consumer of the receive ring, so if the bit is clear, 1815 * we have processed all of the packets. 1816 */ 1817 if ((cmdsts & CMDSTS_OWN) == 0) { 1818 /* 1819 * We have processed all of the receive buffers. 1820 */ 1821 break; 1822 } 1823 1824 if (__predict_false(sc->sc_rxdiscard)) { 1825 SIP_INIT_RXDESC(sc, i); 1826 if ((cmdsts & CMDSTS_MORE) == 0) { 1827 /* Reset our state. */ 1828 sc->sc_rxdiscard = 0; 1829 } 1830 continue; 1831 } 1832 1833 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1834 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1835 1836 m = rxs->rxs_mbuf; 1837 1838 /* 1839 * Add a new receive buffer to the ring. 1840 */ 1841 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1842 /* 1843 * Failed, throw away what we've done so 1844 * far, and discard the rest of the packet. 1845 */ 1846 ifp->if_ierrors++; 1847 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1848 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1849 SIP_INIT_RXDESC(sc, i); 1850 if (cmdsts & CMDSTS_MORE) 1851 sc->sc_rxdiscard = 1; 1852 if (sc->sc_rxhead != NULL) 1853 m_freem(sc->sc_rxhead); 1854 SIP_RXCHAIN_RESET(sc); 1855 continue; 1856 } 1857 1858 SIP_RXCHAIN_LINK(sc, m); 1859 1860 /* 1861 * If this is not the end of the packet, keep 1862 * looking. 1863 */ 1864 if (cmdsts & CMDSTS_MORE) { 1865 sc->sc_rxlen += m->m_len; 1866 continue; 1867 } 1868 1869 /* 1870 * Okay, we have the entire packet now... 1871 */ 1872 *sc->sc_rxtailp = NULL; 1873 m = sc->sc_rxhead; 1874 tailm = sc->sc_rxtail; 1875 frame_len = sc->sc_rxlen; 1876 1877 SIP_RXCHAIN_RESET(sc); 1878 1879 /* 1880 * If an error occurred, update stats and drop the packet. 1881 */ 1882 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1883 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1884 ifp->if_ierrors++; 1885 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1886 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1887 /* Receive overrun handled elsewhere. */ 1888 printf("%s: receive descriptor error\n", 1889 sc->sc_dev.dv_xname); 1890 } 1891 #define PRINTERR(bit, str) \ 1892 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1893 (cmdsts & (bit)) != 0) \ 1894 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1895 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1896 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1897 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1898 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1899 #undef PRINTERR 1900 m_freem(m); 1901 continue; 1902 } 1903 1904 /* 1905 * No errors. 1906 * 1907 * Note, the DP83820 includes the CRC with 1908 * every packet. 1909 */ 1910 len = CMDSTS_SIZE(cmdsts); 1911 frame_len += len; 1912 tailm->m_len = len; 1913 1914 /* 1915 * If the packet is small enough to fit in a 1916 * single header mbuf, allocate one and copy 1917 * the data into it. This greatly reduces 1918 * memory consumption when we receive lots 1919 * of small packets. 1920 */ 1921 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1922 struct mbuf *nm; 1923 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1924 if (nm == NULL) { 1925 ifp->if_ierrors++; 1926 m_freem(m); 1927 continue; 1928 } 1929 nm->m_data += 2; 1930 nm->m_pkthdr.len = nm->m_len = len; 1931 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1932 m_freem(m); 1933 m = nm; 1934 } 1935 #ifndef __NO_STRICT_ALIGNMENT 1936 else { 1937 /* 1938 * The DP83820's receive buffers must be 4-byte 1939 * aligned. But this means that the data after 1940 * the Ethernet header is misaligned. To compensate, 1941 * we have artificially shortened the buffer size 1942 * in the descriptor, and we do an overlapping copy 1943 * of the data two bytes further in (in the first 1944 * buffer of the chain only). 1945 */ 1946 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1947 m->m_len); 1948 m->m_data += 2; 1949 } 1950 #endif /* ! __NO_STRICT_ALIGNMENT */ 1951 1952 /* 1953 * If VLANs are enabled, VLAN packets have been unwrapped 1954 * for us. Associate the tag with the packet. 1955 */ 1956 if (sc->sc_ethercom.ec_nvlans != 0 && 1957 (extsts & EXTSTS_VPKT) != 0) { 1958 struct m_tag *vtag; 1959 1960 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 1961 M_NOWAIT); 1962 if (vtag == NULL) { 1963 ifp->if_ierrors++; 1964 printf("%s: unable to allocate VLAN tag\n", 1965 sc->sc_dev.dv_xname); 1966 m_freem(m); 1967 continue; 1968 } 1969 1970 *(u_int *)(vtag + 1) = ntohs(extsts & EXTSTS_VTCI); 1971 } 1972 1973 /* 1974 * Set the incoming checksum information for the 1975 * packet. 1976 */ 1977 if ((extsts & EXTSTS_IPPKT) != 0) { 1978 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1979 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1980 if (extsts & EXTSTS_Rx_IPERR) 1981 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1982 if (extsts & EXTSTS_TCPPKT) { 1983 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1984 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1985 if (extsts & EXTSTS_Rx_TCPERR) 1986 m->m_pkthdr.csum_flags |= 1987 M_CSUM_TCP_UDP_BAD; 1988 } else if (extsts & EXTSTS_UDPPKT) { 1989 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1990 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1991 if (extsts & EXTSTS_Rx_UDPERR) 1992 m->m_pkthdr.csum_flags |= 1993 M_CSUM_TCP_UDP_BAD; 1994 } 1995 } 1996 1997 ifp->if_ipackets++; 1998 m->m_flags |= M_HASFCS; 1999 m->m_pkthdr.rcvif = ifp; 2000 m->m_pkthdr.len = frame_len; 2001 2002 #if NBPFILTER > 0 2003 /* 2004 * Pass this up to any BPF listeners, but only 2005 * pass if up the stack if it's for us. 2006 */ 2007 if (ifp->if_bpf) 2008 bpf_mtap(ifp->if_bpf, m); 2009 #endif /* NBPFILTER > 0 */ 2010 2011 /* Pass it on. */ 2012 (*ifp->if_input)(ifp, m); 2013 } 2014 2015 /* Update the receive pointer. */ 2016 sc->sc_rxptr = i; 2017 } 2018 #else /* ! DP83820 */ 2019 /* 2020 * sip_rxintr: 2021 * 2022 * Helper; handle receive interrupts. 2023 */ 2024 void 2025 SIP_DECL(rxintr)(struct sip_softc *sc) 2026 { 2027 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2028 struct sip_rxsoft *rxs; 2029 struct mbuf *m; 2030 u_int32_t cmdsts; 2031 int i, len; 2032 2033 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 2034 rxs = &sc->sc_rxsoft[i]; 2035 2036 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2037 2038 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 2039 2040 /* 2041 * NOTE: OWN is set if owned by _consumer_. We're the 2042 * consumer of the receive ring, so if the bit is clear, 2043 * we have processed all of the packets. 2044 */ 2045 if ((cmdsts & CMDSTS_OWN) == 0) { 2046 /* 2047 * We have processed all of the receive buffers. 2048 */ 2049 break; 2050 } 2051 2052 /* 2053 * If any collisions were seen on the wire, count one. 2054 */ 2055 if (cmdsts & CMDSTS_Rx_COL) 2056 ifp->if_collisions++; 2057 2058 /* 2059 * If an error occurred, update stats, clear the status 2060 * word, and leave the packet buffer in place. It will 2061 * simply be reused the next time the ring comes around. 2062 */ 2063 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2064 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2065 ifp->if_ierrors++; 2066 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2067 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2068 /* Receive overrun handled elsewhere. */ 2069 printf("%s: receive descriptor error\n", 2070 sc->sc_dev.dv_xname); 2071 } 2072 #define PRINTERR(bit, str) \ 2073 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2074 (cmdsts & (bit)) != 0) \ 2075 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 2076 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2077 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2078 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2079 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2080 #undef PRINTERR 2081 SIP_INIT_RXDESC(sc, i); 2082 continue; 2083 } 2084 2085 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2086 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2087 2088 /* 2089 * No errors; receive the packet. Note, the SiS 900 2090 * includes the CRC with every packet. 2091 */ 2092 len = CMDSTS_SIZE(cmdsts); 2093 2094 #ifdef __NO_STRICT_ALIGNMENT 2095 /* 2096 * If the packet is small enough to fit in a 2097 * single header mbuf, allocate one and copy 2098 * the data into it. This greatly reduces 2099 * memory consumption when we receive lots 2100 * of small packets. 2101 * 2102 * Otherwise, we add a new buffer to the receive 2103 * chain. If this fails, we drop the packet and 2104 * recycle the old buffer. 2105 */ 2106 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 2107 MGETHDR(m, M_DONTWAIT, MT_DATA); 2108 if (m == NULL) 2109 goto dropit; 2110 memcpy(mtod(m, caddr_t), 2111 mtod(rxs->rxs_mbuf, caddr_t), len); 2112 SIP_INIT_RXDESC(sc, i); 2113 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2114 rxs->rxs_dmamap->dm_mapsize, 2115 BUS_DMASYNC_PREREAD); 2116 } else { 2117 m = rxs->rxs_mbuf; 2118 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 2119 dropit: 2120 ifp->if_ierrors++; 2121 SIP_INIT_RXDESC(sc, i); 2122 bus_dmamap_sync(sc->sc_dmat, 2123 rxs->rxs_dmamap, 0, 2124 rxs->rxs_dmamap->dm_mapsize, 2125 BUS_DMASYNC_PREREAD); 2126 continue; 2127 } 2128 } 2129 #else 2130 /* 2131 * The SiS 900's receive buffers must be 4-byte aligned. 2132 * But this means that the data after the Ethernet header 2133 * is misaligned. We must allocate a new buffer and 2134 * copy the data, shifted forward 2 bytes. 2135 */ 2136 MGETHDR(m, M_DONTWAIT, MT_DATA); 2137 if (m == NULL) { 2138 dropit: 2139 ifp->if_ierrors++; 2140 SIP_INIT_RXDESC(sc, i); 2141 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2142 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2143 continue; 2144 } 2145 if (len > (MHLEN - 2)) { 2146 MCLGET(m, M_DONTWAIT); 2147 if ((m->m_flags & M_EXT) == 0) { 2148 m_freem(m); 2149 goto dropit; 2150 } 2151 } 2152 m->m_data += 2; 2153 2154 /* 2155 * Note that we use clusters for incoming frames, so the 2156 * buffer is virtually contiguous. 2157 */ 2158 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 2159 2160 /* Allow the receive descriptor to continue using its mbuf. */ 2161 SIP_INIT_RXDESC(sc, i); 2162 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2163 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2164 #endif /* __NO_STRICT_ALIGNMENT */ 2165 2166 ifp->if_ipackets++; 2167 m->m_flags |= M_HASFCS; 2168 m->m_pkthdr.rcvif = ifp; 2169 m->m_pkthdr.len = m->m_len = len; 2170 2171 #if NBPFILTER > 0 2172 /* 2173 * Pass this up to any BPF listeners, but only 2174 * pass if up the stack if it's for us. 2175 */ 2176 if (ifp->if_bpf) 2177 bpf_mtap(ifp->if_bpf, m); 2178 #endif /* NBPFILTER > 0 */ 2179 2180 /* Pass it on. */ 2181 (*ifp->if_input)(ifp, m); 2182 } 2183 2184 /* Update the receive pointer. */ 2185 sc->sc_rxptr = i; 2186 } 2187 #endif /* DP83820 */ 2188 2189 /* 2190 * sip_tick: 2191 * 2192 * One second timer, used to tick the MII. 2193 */ 2194 void 2195 SIP_DECL(tick)(void *arg) 2196 { 2197 struct sip_softc *sc = arg; 2198 int s; 2199 2200 s = splnet(); 2201 #ifdef DP83820 2202 #ifdef SIP_EVENT_COUNTERS 2203 /* Read PAUSE related counts from MIB registers. */ 2204 sc->sc_ev_rxpause.ev_count += 2205 bus_space_read_4(sc->sc_st, sc->sc_sh, 2206 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2207 sc->sc_ev_txpause.ev_count += 2208 bus_space_read_4(sc->sc_st, sc->sc_sh, 2209 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2210 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2211 #endif /* SIP_EVENT_COUNTERS */ 2212 #endif /* DP83820 */ 2213 mii_tick(&sc->sc_mii); 2214 splx(s); 2215 2216 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2217 } 2218 2219 /* 2220 * sip_reset: 2221 * 2222 * Perform a soft reset on the SiS 900. 2223 */ 2224 void 2225 SIP_DECL(reset)(struct sip_softc *sc) 2226 { 2227 bus_space_tag_t st = sc->sc_st; 2228 bus_space_handle_t sh = sc->sc_sh; 2229 int i; 2230 2231 bus_space_write_4(st, sh, SIP_IER, 0); 2232 bus_space_write_4(st, sh, SIP_IMR, 0); 2233 bus_space_write_4(st, sh, SIP_RFCR, 0); 2234 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2235 2236 for (i = 0; i < SIP_TIMEOUT; i++) { 2237 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2238 break; 2239 delay(2); 2240 } 2241 2242 if (i == SIP_TIMEOUT) 2243 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2244 2245 delay(1000); 2246 2247 #ifdef DP83820 2248 /* 2249 * Set the general purpose I/O bits. Do it here in case we 2250 * need to have GPIO set up to talk to the media interface. 2251 */ 2252 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2253 delay(1000); 2254 #endif /* DP83820 */ 2255 } 2256 2257 /* 2258 * sip_init: [ ifnet interface function ] 2259 * 2260 * Initialize the interface. Must be called at splnet(). 2261 */ 2262 int 2263 SIP_DECL(init)(struct ifnet *ifp) 2264 { 2265 struct sip_softc *sc = ifp->if_softc; 2266 bus_space_tag_t st = sc->sc_st; 2267 bus_space_handle_t sh = sc->sc_sh; 2268 struct sip_txsoft *txs; 2269 struct sip_rxsoft *rxs; 2270 struct sip_desc *sipd; 2271 #if defined(DP83820) 2272 u_int32_t reg; 2273 #endif 2274 int i, error = 0; 2275 2276 /* 2277 * Cancel any pending I/O. 2278 */ 2279 SIP_DECL(stop)(ifp, 0); 2280 2281 /* 2282 * Reset the chip to a known state. 2283 */ 2284 SIP_DECL(reset)(sc); 2285 2286 #if !defined(DP83820) 2287 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2288 /* 2289 * DP83815 manual, page 78: 2290 * 4.4 Recommended Registers Configuration 2291 * For optimum performance of the DP83815, version noted 2292 * as DP83815CVNG (SRR = 203h), the listed register 2293 * modifications must be followed in sequence... 2294 * 2295 * It's not clear if this should be 302h or 203h because that 2296 * chip name is listed as SRR 302h in the description of the 2297 * SRR register. However, my revision 302h DP83815 on the 2298 * Netgear FA311 purchased in 02/2001 needs these settings 2299 * to avoid tons of errors in AcceptPerfectMatch (non- 2300 * IFF_PROMISC) mode. I do not know if other revisions need 2301 * this set or not. [briggs -- 09 March 2001] 2302 * 2303 * Note that only the low-order 12 bits of 0xe4 are documented 2304 * and that this sets reserved bits in that register. 2305 */ 2306 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2307 2308 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2309 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2310 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2311 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2312 2313 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2314 } 2315 #endif /* ! DP83820 */ 2316 2317 /* 2318 * Initialize the transmit descriptor ring. 2319 */ 2320 for (i = 0; i < SIP_NTXDESC; i++) { 2321 sipd = &sc->sc_txdescs[i]; 2322 memset(sipd, 0, sizeof(struct sip_desc)); 2323 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2324 } 2325 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2326 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2327 sc->sc_txfree = SIP_NTXDESC; 2328 sc->sc_txnext = 0; 2329 sc->sc_txwin = 0; 2330 2331 /* 2332 * Initialize the transmit job descriptors. 2333 */ 2334 SIMPLEQ_INIT(&sc->sc_txfreeq); 2335 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2336 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2337 txs = &sc->sc_txsoft[i]; 2338 txs->txs_mbuf = NULL; 2339 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2340 } 2341 2342 /* 2343 * Initialize the receive descriptor and receive job 2344 * descriptor rings. 2345 */ 2346 for (i = 0; i < SIP_NRXDESC; i++) { 2347 rxs = &sc->sc_rxsoft[i]; 2348 if (rxs->rxs_mbuf == NULL) { 2349 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2350 printf("%s: unable to allocate or map rx " 2351 "buffer %d, error = %d\n", 2352 sc->sc_dev.dv_xname, i, error); 2353 /* 2354 * XXX Should attempt to run with fewer receive 2355 * XXX buffers instead of just failing. 2356 */ 2357 SIP_DECL(rxdrain)(sc); 2358 goto out; 2359 } 2360 } else 2361 SIP_INIT_RXDESC(sc, i); 2362 } 2363 sc->sc_rxptr = 0; 2364 #ifdef DP83820 2365 sc->sc_rxdiscard = 0; 2366 SIP_RXCHAIN_RESET(sc); 2367 #endif /* DP83820 */ 2368 2369 /* 2370 * Set the configuration register; it's already initialized 2371 * in sip_attach(). 2372 */ 2373 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2374 2375 /* 2376 * Initialize the prototype TXCFG register. 2377 */ 2378 #if defined(DP83820) 2379 sc->sc_txcfg = TXCFG_MXDMA_512; 2380 sc->sc_rxcfg = RXCFG_MXDMA_512; 2381 #else 2382 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2383 SIP_SIS900_REV(sc, SIS_REV_960) || 2384 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2385 (sc->sc_cfg & CFG_EDBMASTEN)) { 2386 sc->sc_txcfg = TXCFG_MXDMA_64; 2387 sc->sc_rxcfg = RXCFG_MXDMA_64; 2388 } else { 2389 sc->sc_txcfg = TXCFG_MXDMA_512; 2390 sc->sc_rxcfg = RXCFG_MXDMA_512; 2391 } 2392 #endif /* DP83820 */ 2393 2394 sc->sc_txcfg |= TXCFG_ATP | 2395 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2396 sc->sc_tx_drain_thresh; 2397 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2398 2399 /* 2400 * Initialize the receive drain threshold if we have never 2401 * done so. 2402 */ 2403 if (sc->sc_rx_drain_thresh == 0) { 2404 /* 2405 * XXX This value should be tuned. This is set to the 2406 * maximum of 248 bytes, and we may be able to improve 2407 * performance by decreasing it (although we should never 2408 * set this value lower than 2; 14 bytes are required to 2409 * filter the packet). 2410 */ 2411 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2412 } 2413 2414 /* 2415 * Initialize the prototype RXCFG register. 2416 */ 2417 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2418 #ifdef DP83820 2419 /* 2420 * Accept long packets (including FCS) so we can handle 2421 * 802.1q-tagged frames and jumbo frames properly. 2422 */ 2423 if (ifp->if_mtu > ETHERMTU || 2424 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2425 sc->sc_rxcfg |= RXCFG_ALP; 2426 2427 /* 2428 * Checksum offloading is disabled if the user selects an MTU 2429 * larger than 8109. (FreeBSD says 8152, but there is emperical 2430 * evidence that >8109 does not work on some boards, such as the 2431 * Planex GN-1000TE). 2432 */ 2433 if (ifp->if_mtu > 8109 && 2434 (ifp->if_capenable & 2435 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4))) { 2436 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2437 "disabled.\n", sc->sc_dev.dv_xname); 2438 ifp->if_capenable &= ~(IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4| 2439 IFCAP_CSUM_UDPv4); 2440 ifp->if_csum_flags_tx = 0; 2441 ifp->if_csum_flags_rx = 0; 2442 } 2443 #else 2444 /* 2445 * Accept packets >1518 bytes (including FCS) so we can handle 2446 * 802.1q-tagged frames properly. 2447 */ 2448 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2449 sc->sc_rxcfg |= RXCFG_ALP; 2450 #endif 2451 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2452 2453 #ifdef DP83820 2454 /* 2455 * Initialize the VLAN/IP receive control register. 2456 * We enable checksum computation on all incoming 2457 * packets, and do not reject packets w/ bad checksums. 2458 */ 2459 reg = 0; 2460 if (ifp->if_capenable & 2461 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2462 reg |= VRCR_IPEN; 2463 if (sc->sc_ethercom.ec_nvlans != 0) 2464 reg |= VRCR_VTDEN|VRCR_VTREN; 2465 bus_space_write_4(st, sh, SIP_VRCR, reg); 2466 2467 /* 2468 * Initialize the VLAN/IP transmit control register. 2469 * We enable outgoing checksum computation on a 2470 * per-packet basis. 2471 */ 2472 reg = 0; 2473 if (ifp->if_capenable & 2474 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2475 reg |= VTCR_PPCHK; 2476 if (sc->sc_ethercom.ec_nvlans != 0) 2477 reg |= VTCR_VPPTI; 2478 bus_space_write_4(st, sh, SIP_VTCR, reg); 2479 2480 /* 2481 * If we're using VLANs, initialize the VLAN data register. 2482 * To understand why we bswap the VLAN Ethertype, see section 2483 * 4.2.36 of the DP83820 manual. 2484 */ 2485 if (sc->sc_ethercom.ec_nvlans != 0) 2486 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2487 #endif /* DP83820 */ 2488 2489 /* 2490 * Give the transmit and receive rings to the chip. 2491 */ 2492 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2493 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2494 2495 /* 2496 * Initialize the interrupt mask. 2497 */ 2498 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2499 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2500 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2501 2502 /* Set up the receive filter. */ 2503 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2504 2505 #ifdef DP83820 2506 /* 2507 * Tune sc_rx_flow_thresh. 2508 * XXX "More than 8KB" is too short for jumbo frames. 2509 * XXX TODO: Threshold value should be user-settable. 2510 */ 2511 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2512 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2513 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2514 #endif 2515 2516 /* 2517 * Set the current media. Do this after initializing the prototype 2518 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2519 * control. 2520 */ 2521 mii_mediachg(&sc->sc_mii); 2522 2523 #ifdef DP83820 2524 /* 2525 * Set the interrupt hold-off timer to 100us. 2526 */ 2527 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2528 #endif 2529 2530 /* 2531 * Enable interrupts. 2532 */ 2533 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2534 2535 /* 2536 * Start the transmit and receive processes. 2537 */ 2538 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2539 2540 /* 2541 * Start the one second MII clock. 2542 */ 2543 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2544 2545 /* 2546 * ...all done! 2547 */ 2548 ifp->if_flags |= IFF_RUNNING; 2549 ifp->if_flags &= ~IFF_OACTIVE; 2550 2551 out: 2552 if (error) 2553 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2554 return (error); 2555 } 2556 2557 /* 2558 * sip_drain: 2559 * 2560 * Drain the receive queue. 2561 */ 2562 void 2563 SIP_DECL(rxdrain)(struct sip_softc *sc) 2564 { 2565 struct sip_rxsoft *rxs; 2566 int i; 2567 2568 for (i = 0; i < SIP_NRXDESC; i++) { 2569 rxs = &sc->sc_rxsoft[i]; 2570 if (rxs->rxs_mbuf != NULL) { 2571 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2572 m_freem(rxs->rxs_mbuf); 2573 rxs->rxs_mbuf = NULL; 2574 } 2575 } 2576 } 2577 2578 /* 2579 * sip_stop: [ ifnet interface function ] 2580 * 2581 * Stop transmission on the interface. 2582 */ 2583 void 2584 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2585 { 2586 struct sip_softc *sc = ifp->if_softc; 2587 bus_space_tag_t st = sc->sc_st; 2588 bus_space_handle_t sh = sc->sc_sh; 2589 struct sip_txsoft *txs; 2590 u_int32_t cmdsts = 0; /* DEBUG */ 2591 2592 /* 2593 * Stop the one second clock. 2594 */ 2595 callout_stop(&sc->sc_tick_ch); 2596 2597 /* Down the MII. */ 2598 mii_down(&sc->sc_mii); 2599 2600 /* 2601 * Disable interrupts. 2602 */ 2603 bus_space_write_4(st, sh, SIP_IER, 0); 2604 2605 /* 2606 * Stop receiver and transmitter. 2607 */ 2608 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2609 2610 /* 2611 * Release any queued transmit buffers. 2612 */ 2613 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2614 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2615 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2616 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2617 CMDSTS_INTR) == 0) 2618 printf("%s: sip_stop: last descriptor does not " 2619 "have INTR bit set\n", sc->sc_dev.dv_xname); 2620 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2621 #ifdef DIAGNOSTIC 2622 if (txs->txs_mbuf == NULL) { 2623 printf("%s: dirty txsoft with no mbuf chain\n", 2624 sc->sc_dev.dv_xname); 2625 panic("sip_stop"); 2626 } 2627 #endif 2628 cmdsts |= /* DEBUG */ 2629 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2630 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2631 m_freem(txs->txs_mbuf); 2632 txs->txs_mbuf = NULL; 2633 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2634 } 2635 2636 if (disable) 2637 SIP_DECL(rxdrain)(sc); 2638 2639 /* 2640 * Mark the interface down and cancel the watchdog timer. 2641 */ 2642 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2643 ifp->if_timer = 0; 2644 2645 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2646 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2647 printf("%s: sip_stop: no INTR bits set in dirty tx " 2648 "descriptors\n", sc->sc_dev.dv_xname); 2649 } 2650 2651 /* 2652 * sip_read_eeprom: 2653 * 2654 * Read data from the serial EEPROM. 2655 */ 2656 void 2657 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2658 u_int16_t *data) 2659 { 2660 bus_space_tag_t st = sc->sc_st; 2661 bus_space_handle_t sh = sc->sc_sh; 2662 u_int16_t reg; 2663 int i, x; 2664 2665 for (i = 0; i < wordcnt; i++) { 2666 /* Send CHIP SELECT. */ 2667 reg = EROMAR_EECS; 2668 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2669 2670 /* Shift in the READ opcode. */ 2671 for (x = 3; x > 0; x--) { 2672 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2673 reg |= EROMAR_EEDI; 2674 else 2675 reg &= ~EROMAR_EEDI; 2676 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2677 bus_space_write_4(st, sh, SIP_EROMAR, 2678 reg | EROMAR_EESK); 2679 delay(4); 2680 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2681 delay(4); 2682 } 2683 2684 /* Shift in address. */ 2685 for (x = 6; x > 0; x--) { 2686 if ((word + i) & (1 << (x - 1))) 2687 reg |= EROMAR_EEDI; 2688 else 2689 reg &= ~EROMAR_EEDI; 2690 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2691 bus_space_write_4(st, sh, SIP_EROMAR, 2692 reg | EROMAR_EESK); 2693 delay(4); 2694 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2695 delay(4); 2696 } 2697 2698 /* Shift out data. */ 2699 reg = EROMAR_EECS; 2700 data[i] = 0; 2701 for (x = 16; x > 0; x--) { 2702 bus_space_write_4(st, sh, SIP_EROMAR, 2703 reg | EROMAR_EESK); 2704 delay(4); 2705 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2706 data[i] |= (1 << (x - 1)); 2707 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2708 delay(4); 2709 } 2710 2711 /* Clear CHIP SELECT. */ 2712 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2713 delay(4); 2714 } 2715 } 2716 2717 /* 2718 * sip_add_rxbuf: 2719 * 2720 * Add a receive buffer to the indicated descriptor. 2721 */ 2722 int 2723 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2724 { 2725 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2726 struct mbuf *m; 2727 int error; 2728 2729 MGETHDR(m, M_DONTWAIT, MT_DATA); 2730 if (m == NULL) 2731 return (ENOBUFS); 2732 2733 MCLGET(m, M_DONTWAIT); 2734 if ((m->m_flags & M_EXT) == 0) { 2735 m_freem(m); 2736 return (ENOBUFS); 2737 } 2738 2739 #if defined(DP83820) 2740 m->m_len = SIP_RXBUF_LEN; 2741 #endif /* DP83820 */ 2742 2743 if (rxs->rxs_mbuf != NULL) 2744 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2745 2746 rxs->rxs_mbuf = m; 2747 2748 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2749 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2750 BUS_DMA_READ|BUS_DMA_NOWAIT); 2751 if (error) { 2752 printf("%s: can't load rx DMA map %d, error = %d\n", 2753 sc->sc_dev.dv_xname, idx, error); 2754 panic("sip_add_rxbuf"); /* XXX */ 2755 } 2756 2757 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2758 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2759 2760 SIP_INIT_RXDESC(sc, idx); 2761 2762 return (0); 2763 } 2764 2765 #if !defined(DP83820) 2766 /* 2767 * sip_sis900_set_filter: 2768 * 2769 * Set up the receive filter. 2770 */ 2771 void 2772 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2773 { 2774 bus_space_tag_t st = sc->sc_st; 2775 bus_space_handle_t sh = sc->sc_sh; 2776 struct ethercom *ec = &sc->sc_ethercom; 2777 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2778 struct ether_multi *enm; 2779 u_int8_t *cp; 2780 struct ether_multistep step; 2781 u_int32_t crc, mchash[16]; 2782 2783 /* 2784 * Initialize the prototype RFCR. 2785 */ 2786 sc->sc_rfcr = RFCR_RFEN; 2787 if (ifp->if_flags & IFF_BROADCAST) 2788 sc->sc_rfcr |= RFCR_AAB; 2789 if (ifp->if_flags & IFF_PROMISC) { 2790 sc->sc_rfcr |= RFCR_AAP; 2791 goto allmulti; 2792 } 2793 2794 /* 2795 * Set up the multicast address filter by passing all multicast 2796 * addresses through a CRC generator, and then using the high-order 2797 * 6 bits as an index into the 128 bit multicast hash table (only 2798 * the lower 16 bits of each 32 bit multicast hash register are 2799 * valid). The high order bits select the register, while the 2800 * rest of the bits select the bit within the register. 2801 */ 2802 2803 memset(mchash, 0, sizeof(mchash)); 2804 2805 /* 2806 * SiS900 (at least SiS963) requires us to register the address of 2807 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 2808 */ 2809 crc = 0x0ed423f9; 2810 2811 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2812 SIP_SIS900_REV(sc, SIS_REV_960) || 2813 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2814 /* Just want the 8 most significant bits. */ 2815 crc >>= 24; 2816 } else { 2817 /* Just want the 7 most significant bits. */ 2818 crc >>= 25; 2819 } 2820 2821 /* Set the corresponding bit in the hash table. */ 2822 mchash[crc >> 4] |= 1 << (crc & 0xf); 2823 2824 ETHER_FIRST_MULTI(step, ec, enm); 2825 while (enm != NULL) { 2826 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2827 /* 2828 * We must listen to a range of multicast addresses. 2829 * For now, just accept all multicasts, rather than 2830 * trying to set only those filter bits needed to match 2831 * the range. (At this time, the only use of address 2832 * ranges is for IP multicast routing, for which the 2833 * range is big enough to require all bits set.) 2834 */ 2835 goto allmulti; 2836 } 2837 2838 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2839 2840 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2841 SIP_SIS900_REV(sc, SIS_REV_960) || 2842 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2843 /* Just want the 8 most significant bits. */ 2844 crc >>= 24; 2845 } else { 2846 /* Just want the 7 most significant bits. */ 2847 crc >>= 25; 2848 } 2849 2850 /* Set the corresponding bit in the hash table. */ 2851 mchash[crc >> 4] |= 1 << (crc & 0xf); 2852 2853 ETHER_NEXT_MULTI(step, enm); 2854 } 2855 2856 ifp->if_flags &= ~IFF_ALLMULTI; 2857 goto setit; 2858 2859 allmulti: 2860 ifp->if_flags |= IFF_ALLMULTI; 2861 sc->sc_rfcr |= RFCR_AAM; 2862 2863 setit: 2864 #define FILTER_EMIT(addr, data) \ 2865 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2866 delay(1); \ 2867 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2868 delay(1) 2869 2870 /* 2871 * Disable receive filter, and program the node address. 2872 */ 2873 cp = LLADDR(ifp->if_sadl); 2874 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2875 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2876 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2877 2878 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2879 /* 2880 * Program the multicast hash table. 2881 */ 2882 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2883 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2884 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2885 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2886 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2887 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2888 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2889 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2890 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2891 SIP_SIS900_REV(sc, SIS_REV_960) || 2892 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2893 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2894 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2895 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2896 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2897 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2898 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2899 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2900 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2901 } 2902 } 2903 #undef FILTER_EMIT 2904 2905 /* 2906 * Re-enable the receiver filter. 2907 */ 2908 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2909 } 2910 #endif /* ! DP83820 */ 2911 2912 /* 2913 * sip_dp83815_set_filter: 2914 * 2915 * Set up the receive filter. 2916 */ 2917 void 2918 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2919 { 2920 bus_space_tag_t st = sc->sc_st; 2921 bus_space_handle_t sh = sc->sc_sh; 2922 struct ethercom *ec = &sc->sc_ethercom; 2923 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2924 struct ether_multi *enm; 2925 u_int8_t *cp; 2926 struct ether_multistep step; 2927 u_int32_t crc, hash, slot, bit; 2928 #ifdef DP83820 2929 #define MCHASH_NWORDS 128 2930 #else 2931 #define MCHASH_NWORDS 32 2932 #endif /* DP83820 */ 2933 u_int16_t mchash[MCHASH_NWORDS]; 2934 int i; 2935 2936 /* 2937 * Initialize the prototype RFCR. 2938 * Enable the receive filter, and accept on 2939 * Perfect (destination address) Match 2940 * If IFF_BROADCAST, also accept all broadcast packets. 2941 * If IFF_PROMISC, accept all unicast packets (and later, set 2942 * IFF_ALLMULTI and accept all multicast, too). 2943 */ 2944 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2945 if (ifp->if_flags & IFF_BROADCAST) 2946 sc->sc_rfcr |= RFCR_AAB; 2947 if (ifp->if_flags & IFF_PROMISC) { 2948 sc->sc_rfcr |= RFCR_AAP; 2949 goto allmulti; 2950 } 2951 2952 #ifdef DP83820 2953 /* 2954 * Set up the DP83820 multicast address filter by passing all multicast 2955 * addresses through a CRC generator, and then using the high-order 2956 * 11 bits as an index into the 2048 bit multicast hash table. The 2957 * high-order 7 bits select the slot, while the low-order 4 bits 2958 * select the bit within the slot. Note that only the low 16-bits 2959 * of each filter word are used, and there are 128 filter words. 2960 */ 2961 #else 2962 /* 2963 * Set up the DP83815 multicast address filter by passing all multicast 2964 * addresses through a CRC generator, and then using the high-order 2965 * 9 bits as an index into the 512 bit multicast hash table. The 2966 * high-order 5 bits select the slot, while the low-order 4 bits 2967 * select the bit within the slot. Note that only the low 16-bits 2968 * of each filter word are used, and there are 32 filter words. 2969 */ 2970 #endif /* DP83820 */ 2971 2972 memset(mchash, 0, sizeof(mchash)); 2973 2974 ifp->if_flags &= ~IFF_ALLMULTI; 2975 ETHER_FIRST_MULTI(step, ec, enm); 2976 if (enm == NULL) 2977 goto setit; 2978 while (enm != NULL) { 2979 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2980 /* 2981 * We must listen to a range of multicast addresses. 2982 * For now, just accept all multicasts, rather than 2983 * trying to set only those filter bits needed to match 2984 * the range. (At this time, the only use of address 2985 * ranges is for IP multicast routing, for which the 2986 * range is big enough to require all bits set.) 2987 */ 2988 goto allmulti; 2989 } 2990 2991 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2992 2993 #ifdef DP83820 2994 /* Just want the 11 most significant bits. */ 2995 hash = crc >> 21; 2996 #else 2997 /* Just want the 9 most significant bits. */ 2998 hash = crc >> 23; 2999 #endif /* DP83820 */ 3000 3001 slot = hash >> 4; 3002 bit = hash & 0xf; 3003 3004 /* Set the corresponding bit in the hash table. */ 3005 mchash[slot] |= 1 << bit; 3006 3007 ETHER_NEXT_MULTI(step, enm); 3008 } 3009 sc->sc_rfcr |= RFCR_MHEN; 3010 goto setit; 3011 3012 allmulti: 3013 ifp->if_flags |= IFF_ALLMULTI; 3014 sc->sc_rfcr |= RFCR_AAM; 3015 3016 setit: 3017 #define FILTER_EMIT(addr, data) \ 3018 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3019 delay(1); \ 3020 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3021 delay(1) 3022 3023 /* 3024 * Disable receive filter, and program the node address. 3025 */ 3026 cp = LLADDR(ifp->if_sadl); 3027 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3028 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3029 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3030 3031 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3032 /* 3033 * Program the multicast hash table. 3034 */ 3035 for (i = 0; i < MCHASH_NWORDS; i++) { 3036 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 3037 mchash[i]); 3038 } 3039 } 3040 #undef FILTER_EMIT 3041 #undef MCHASH_NWORDS 3042 3043 /* 3044 * Re-enable the receiver filter. 3045 */ 3046 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3047 } 3048 3049 #if defined(DP83820) 3050 /* 3051 * sip_dp83820_mii_readreg: [mii interface function] 3052 * 3053 * Read a PHY register on the MII of the DP83820. 3054 */ 3055 int 3056 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 3057 { 3058 struct sip_softc *sc = (void *) self; 3059 3060 if (sc->sc_cfg & CFG_TBI_EN) { 3061 bus_addr_t tbireg; 3062 int rv; 3063 3064 if (phy != 0) 3065 return (0); 3066 3067 switch (reg) { 3068 case MII_BMCR: tbireg = SIP_TBICR; break; 3069 case MII_BMSR: tbireg = SIP_TBISR; break; 3070 case MII_ANAR: tbireg = SIP_TANAR; break; 3071 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3072 case MII_ANER: tbireg = SIP_TANER; break; 3073 case MII_EXTSR: 3074 /* 3075 * Don't even bother reading the TESR register. 3076 * The manual documents that the device has 3077 * 1000baseX full/half capability, but the 3078 * register itself seems read back 0 on some 3079 * boards. Just hard-code the result. 3080 */ 3081 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3082 3083 default: 3084 return (0); 3085 } 3086 3087 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3088 if (tbireg == SIP_TBISR) { 3089 /* LINK and ACOMP are switched! */ 3090 int val = rv; 3091 3092 rv = 0; 3093 if (val & TBISR_MR_LINK_STATUS) 3094 rv |= BMSR_LINK; 3095 if (val & TBISR_MR_AN_COMPLETE) 3096 rv |= BMSR_ACOMP; 3097 3098 /* 3099 * The manual claims this register reads back 0 3100 * on hard and soft reset. But we want to let 3101 * the gentbi driver know that we support auto- 3102 * negotiation, so hard-code this bit in the 3103 * result. 3104 */ 3105 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3106 } 3107 3108 return (rv); 3109 } 3110 3111 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3112 phy, reg)); 3113 } 3114 3115 /* 3116 * sip_dp83820_mii_writereg: [mii interface function] 3117 * 3118 * Write a PHY register on the MII of the DP83820. 3119 */ 3120 void 3121 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 3122 { 3123 struct sip_softc *sc = (void *) self; 3124 3125 if (sc->sc_cfg & CFG_TBI_EN) { 3126 bus_addr_t tbireg; 3127 3128 if (phy != 0) 3129 return; 3130 3131 switch (reg) { 3132 case MII_BMCR: tbireg = SIP_TBICR; break; 3133 case MII_ANAR: tbireg = SIP_TANAR; break; 3134 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3135 default: 3136 return; 3137 } 3138 3139 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3140 return; 3141 } 3142 3143 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3144 phy, reg, val); 3145 } 3146 3147 /* 3148 * sip_dp83820_mii_statchg: [mii interface function] 3149 * 3150 * Callback from MII layer when media changes. 3151 */ 3152 void 3153 SIP_DECL(dp83820_mii_statchg)(struct device *self) 3154 { 3155 struct sip_softc *sc = (struct sip_softc *) self; 3156 struct mii_data *mii = &sc->sc_mii; 3157 u_int32_t cfg, pcr; 3158 3159 /* 3160 * Get flow control negotiation result. 3161 */ 3162 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3163 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3164 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3165 mii->mii_media_active &= ~IFM_ETH_FMASK; 3166 } 3167 3168 /* 3169 * Update TXCFG for full-duplex operation. 3170 */ 3171 if ((mii->mii_media_active & IFM_FDX) != 0) 3172 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3173 else 3174 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3175 3176 /* 3177 * Update RXCFG for full-duplex or loopback. 3178 */ 3179 if ((mii->mii_media_active & IFM_FDX) != 0 || 3180 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3181 sc->sc_rxcfg |= RXCFG_ATX; 3182 else 3183 sc->sc_rxcfg &= ~RXCFG_ATX; 3184 3185 /* 3186 * Update CFG for MII/GMII. 3187 */ 3188 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3189 cfg = sc->sc_cfg | CFG_MODE_1000; 3190 else 3191 cfg = sc->sc_cfg; 3192 3193 /* 3194 * 802.3x flow control. 3195 */ 3196 pcr = 0; 3197 if (sc->sc_flowflags & IFM_FLOW) { 3198 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3199 pcr |= sc->sc_rx_flow_thresh; 3200 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3201 pcr |= PCR_PSEN | PCR_PS_MCAST; 3202 } 3203 3204 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3205 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3206 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3207 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3208 } 3209 #endif /* ! DP83820 */ 3210 3211 /* 3212 * sip_mii_bitbang_read: [mii bit-bang interface function] 3213 * 3214 * Read the MII serial port for the MII bit-bang module. 3215 */ 3216 u_int32_t 3217 SIP_DECL(mii_bitbang_read)(struct device *self) 3218 { 3219 struct sip_softc *sc = (void *) self; 3220 3221 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3222 } 3223 3224 /* 3225 * sip_mii_bitbang_write: [mii big-bang interface function] 3226 * 3227 * Write the MII serial port for the MII bit-bang module. 3228 */ 3229 void 3230 SIP_DECL(mii_bitbang_write)(struct device *self, u_int32_t val) 3231 { 3232 struct sip_softc *sc = (void *) self; 3233 3234 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3235 } 3236 3237 #ifndef DP83820 3238 /* 3239 * sip_sis900_mii_readreg: [mii interface function] 3240 * 3241 * Read a PHY register on the MII. 3242 */ 3243 int 3244 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 3245 { 3246 struct sip_softc *sc = (struct sip_softc *) self; 3247 u_int32_t enphy; 3248 3249 /* 3250 * The PHY of recent SiS chipsets is accessed through bitbang 3251 * operations. 3252 */ 3253 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3254 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3255 phy, reg)); 3256 3257 #ifndef SIS900_MII_RESTRICT 3258 /* 3259 * The SiS 900 has only an internal PHY on the MII. Only allow 3260 * MII address 0. 3261 */ 3262 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3263 return (0); 3264 #endif 3265 3266 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3267 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3268 ENPHY_RWCMD | ENPHY_ACCESS); 3269 do { 3270 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3271 } while (enphy & ENPHY_ACCESS); 3272 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3273 } 3274 3275 /* 3276 * sip_sis900_mii_writereg: [mii interface function] 3277 * 3278 * Write a PHY register on the MII. 3279 */ 3280 void 3281 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 3282 { 3283 struct sip_softc *sc = (struct sip_softc *) self; 3284 u_int32_t enphy; 3285 3286 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3287 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3288 phy, reg, val); 3289 return; 3290 } 3291 3292 #ifndef SIS900_MII_RESTRICT 3293 /* 3294 * The SiS 900 has only an internal PHY on the MII. Only allow 3295 * MII address 0. 3296 */ 3297 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3298 return; 3299 #endif 3300 3301 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3302 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3303 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3304 do { 3305 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3306 } while (enphy & ENPHY_ACCESS); 3307 } 3308 3309 /* 3310 * sip_sis900_mii_statchg: [mii interface function] 3311 * 3312 * Callback from MII layer when media changes. 3313 */ 3314 void 3315 SIP_DECL(sis900_mii_statchg)(struct device *self) 3316 { 3317 struct sip_softc *sc = (struct sip_softc *) self; 3318 struct mii_data *mii = &sc->sc_mii; 3319 u_int32_t flowctl; 3320 3321 /* 3322 * Get flow control negotiation result. 3323 */ 3324 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3325 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3326 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3327 mii->mii_media_active &= ~IFM_ETH_FMASK; 3328 } 3329 3330 /* 3331 * Update TXCFG for full-duplex operation. 3332 */ 3333 if ((mii->mii_media_active & IFM_FDX) != 0) 3334 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3335 else 3336 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3337 3338 /* 3339 * Update RXCFG for full-duplex or loopback. 3340 */ 3341 if ((mii->mii_media_active & IFM_FDX) != 0 || 3342 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3343 sc->sc_rxcfg |= RXCFG_ATX; 3344 else 3345 sc->sc_rxcfg &= ~RXCFG_ATX; 3346 3347 /* 3348 * Update IMR for use of 802.3x flow control. 3349 */ 3350 if (sc->sc_flowflags & IFM_FLOW) { 3351 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3352 flowctl = FLOWCTL_FLOWEN; 3353 } else { 3354 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3355 flowctl = 0; 3356 } 3357 3358 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3359 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3360 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3361 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3362 } 3363 3364 /* 3365 * sip_dp83815_mii_readreg: [mii interface function] 3366 * 3367 * Read a PHY register on the MII. 3368 */ 3369 int 3370 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 3371 { 3372 struct sip_softc *sc = (struct sip_softc *) self; 3373 u_int32_t val; 3374 3375 /* 3376 * The DP83815 only has an internal PHY. Only allow 3377 * MII address 0. 3378 */ 3379 if (phy != 0) 3380 return (0); 3381 3382 /* 3383 * Apparently, after a reset, the DP83815 can take a while 3384 * to respond. During this recovery period, the BMSR returns 3385 * a value of 0. Catch this -- it's not supposed to happen 3386 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3387 * PHY to come back to life. 3388 * 3389 * This works out because the BMSR is the first register 3390 * read during the PHY probe process. 3391 */ 3392 do { 3393 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3394 } while (reg == MII_BMSR && val == 0); 3395 3396 return (val & 0xffff); 3397 } 3398 3399 /* 3400 * sip_dp83815_mii_writereg: [mii interface function] 3401 * 3402 * Write a PHY register to the MII. 3403 */ 3404 void 3405 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3406 { 3407 struct sip_softc *sc = (struct sip_softc *) self; 3408 3409 /* 3410 * The DP83815 only has an internal PHY. Only allow 3411 * MII address 0. 3412 */ 3413 if (phy != 0) 3414 return; 3415 3416 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3417 } 3418 3419 /* 3420 * sip_dp83815_mii_statchg: [mii interface function] 3421 * 3422 * Callback from MII layer when media changes. 3423 */ 3424 void 3425 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3426 { 3427 struct sip_softc *sc = (struct sip_softc *) self; 3428 3429 /* 3430 * Update TXCFG for full-duplex operation. 3431 */ 3432 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3433 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3434 else 3435 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3436 3437 /* 3438 * Update RXCFG for full-duplex or loopback. 3439 */ 3440 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3441 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3442 sc->sc_rxcfg |= RXCFG_ATX; 3443 else 3444 sc->sc_rxcfg &= ~RXCFG_ATX; 3445 3446 /* 3447 * XXX 802.3x flow control. 3448 */ 3449 3450 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3451 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3452 3453 /* 3454 * Some DP83815s experience problems when used with short 3455 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3456 * sequence adjusts the DSP's signal attenuation to fix the 3457 * problem. 3458 */ 3459 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3460 uint32_t reg; 3461 3462 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3463 3464 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3465 reg &= 0x0fff; 3466 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3467 delay(100); 3468 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3469 reg &= 0x00ff; 3470 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3471 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3472 0x00e8); 3473 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3474 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3475 reg | 0x20); 3476 } 3477 3478 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3479 } 3480 } 3481 #endif /* DP83820 */ 3482 3483 #if defined(DP83820) 3484 void 3485 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3486 const struct pci_attach_args *pa, u_int8_t *enaddr) 3487 { 3488 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3489 u_int8_t cksum, *e, match; 3490 int i; 3491 3492 /* 3493 * EEPROM data format for the DP83820 can be found in 3494 * the DP83820 manual, section 4.2.4. 3495 */ 3496 3497 SIP_DECL(read_eeprom)(sc, 0, 3498 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3499 3500 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3501 match = ~(match - 1); 3502 3503 cksum = 0x55; 3504 e = (u_int8_t *) eeprom_data; 3505 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3506 cksum += *e++; 3507 3508 if (cksum != match) 3509 printf("%s: Checksum (%x) mismatch (%x)", 3510 sc->sc_dev.dv_xname, cksum, match); 3511 3512 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3513 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3514 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3515 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3516 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3517 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3518 } 3519 #else /* ! DP83820 */ 3520 static void 3521 SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc) 3522 { 3523 int i; 3524 3525 /* 3526 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3527 * a reason, but I don't know it. 3528 */ 3529 for (i = 0; i < 10; i++) 3530 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3531 } 3532 3533 void 3534 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3535 const struct pci_attach_args *pa, u_int8_t *enaddr) 3536 { 3537 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3538 3539 switch (sc->sc_rev) { 3540 case SIS_REV_630S: 3541 case SIS_REV_630E: 3542 case SIS_REV_630EA1: 3543 case SIS_REV_630ET: 3544 case SIS_REV_635: 3545 /* 3546 * The MAC address for the on-board Ethernet of 3547 * the SiS 630 chipset is in the NVRAM. Kick 3548 * the chip into re-loading it from NVRAM, and 3549 * read the MAC address out of the filter registers. 3550 */ 3551 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3552 3553 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3554 RFCR_RFADDR_NODE0); 3555 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3556 0xffff; 3557 3558 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3559 RFCR_RFADDR_NODE2); 3560 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3561 0xffff; 3562 3563 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3564 RFCR_RFADDR_NODE4); 3565 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3566 0xffff; 3567 break; 3568 3569 case SIS_REV_960: 3570 { 3571 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3572 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3573 3574 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3575 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3576 3577 int waittime, i; 3578 3579 /* Allow to read EEPROM from LAN. It is shared 3580 * between a 1394 controller and the NIC and each 3581 * time we access it, we need to set SIS_EECMD_REQ. 3582 */ 3583 SIS_SET_EROMAR(sc, EROMAR_REQ); 3584 3585 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3586 /* Force EEPROM to idle state. */ 3587 3588 /* 3589 * XXX-cube This is ugly. I'll look for docs about it. 3590 */ 3591 SIS_SET_EROMAR(sc, EROMAR_EECS); 3592 SIP_DECL(sis900_eeprom_delay)(sc); 3593 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3594 SIS_SET_EROMAR(sc, EROMAR_EESK); 3595 SIP_DECL(sis900_eeprom_delay)(sc); 3596 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3597 SIP_DECL(sis900_eeprom_delay)(sc); 3598 } 3599 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3600 SIP_DECL(sis900_eeprom_delay)(sc); 3601 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3602 3603 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3604 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3605 sizeof(myea) / sizeof(myea[0]), myea); 3606 break; 3607 } 3608 DELAY(1); 3609 } 3610 3611 /* 3612 * Set SIS_EECTL_CLK to high, so a other master 3613 * can operate on the i2c bus. 3614 */ 3615 SIS_SET_EROMAR(sc, EROMAR_EESK); 3616 3617 /* Refuse EEPROM access by LAN */ 3618 SIS_SET_EROMAR(sc, EROMAR_DONE); 3619 } break; 3620 3621 default: 3622 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3623 sizeof(myea) / sizeof(myea[0]), myea); 3624 } 3625 3626 enaddr[0] = myea[0] & 0xff; 3627 enaddr[1] = myea[0] >> 8; 3628 enaddr[2] = myea[1] & 0xff; 3629 enaddr[3] = myea[1] >> 8; 3630 enaddr[4] = myea[2] & 0xff; 3631 enaddr[5] = myea[2] >> 8; 3632 } 3633 3634 /* Table and macro to bit-reverse an octet. */ 3635 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3636 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3637 3638 void 3639 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3640 const struct pci_attach_args *pa, u_int8_t *enaddr) 3641 { 3642 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3643 u_int8_t cksum, *e, match; 3644 int i; 3645 3646 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3647 sizeof(eeprom_data[0]), eeprom_data); 3648 3649 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3650 match = ~(match - 1); 3651 3652 cksum = 0x55; 3653 e = (u_int8_t *) eeprom_data; 3654 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3655 cksum += *e++; 3656 } 3657 if (cksum != match) { 3658 printf("%s: Checksum (%x) mismatch (%x)", 3659 sc->sc_dev.dv_xname, cksum, match); 3660 } 3661 3662 /* 3663 * Unrolled because it makes slightly more sense this way. 3664 * The DP83815 stores the MAC address in bit 0 of word 6 3665 * through bit 15 of word 8. 3666 */ 3667 ea = &eeprom_data[6]; 3668 enaddr[0] = ((*ea & 0x1) << 7); 3669 ea++; 3670 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3671 enaddr[1] = ((*ea & 0x1FE) >> 1); 3672 enaddr[2] = ((*ea & 0x1) << 7); 3673 ea++; 3674 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3675 enaddr[3] = ((*ea & 0x1FE) >> 1); 3676 enaddr[4] = ((*ea & 0x1) << 7); 3677 ea++; 3678 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3679 enaddr[5] = ((*ea & 0x1FE) >> 1); 3680 3681 /* 3682 * In case that's not weird enough, we also need to reverse 3683 * the bits in each byte. This all actually makes more sense 3684 * if you think about the EEPROM storage as an array of bits 3685 * being shifted into bytes, but that's not how we're looking 3686 * at it here... 3687 */ 3688 for (i = 0; i < 6 ;i++) 3689 enaddr[i] = bbr(enaddr[i]); 3690 } 3691 #endif /* DP83820 */ 3692 3693 /* 3694 * sip_mediastatus: [ifmedia interface function] 3695 * 3696 * Get the current interface media status. 3697 */ 3698 void 3699 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3700 { 3701 struct sip_softc *sc = ifp->if_softc; 3702 3703 mii_pollstat(&sc->sc_mii); 3704 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3705 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3706 sc->sc_flowflags; 3707 } 3708 3709 /* 3710 * sip_mediachange: [ifmedia interface function] 3711 * 3712 * Set hardware to newly-selected media. 3713 */ 3714 int 3715 SIP_DECL(mediachange)(struct ifnet *ifp) 3716 { 3717 struct sip_softc *sc = ifp->if_softc; 3718 3719 if (ifp->if_flags & IFF_UP) 3720 mii_mediachg(&sc->sc_mii); 3721 return (0); 3722 } 3723
Indexes created Tue Sep 30 11:09:46 GMT 2025