if_sip.c revision 1.78.2.4
1 /* $NetBSD: if_sip.c,v 1.78.2.4 2004/09/21 13:31:03 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.78.2.4 2004/09/21 13:31:03 skrll Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <machine/bus.h> 116 #include <machine/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/mii_bitbang.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/pci/if_sipreg.h> 128 129 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 130 #define SIP_DECL(x) __CONCAT(gsip_,x) 131 #else /* SiS900 and DP83815 */ 132 #define SIP_DECL(x) __CONCAT(sip_,x) 133 #endif 134 135 #define SIP_STR(x) __STRING(SIP_DECL(x)) 136 137 /* 138 * Transmit descriptor list size. This is arbitrary, but allocate 139 * enough descriptors for 128 pending transmissions, and 8 segments 140 * per packet (64 for DP83820 for jumbo frames). 141 * 142 * This MUST work out to a power of 2. 143 */ 144 #ifdef DP83820 145 #define SIP_NTXSEGS 64 146 #define SIP_NTXSEGS_ALLOC 16 147 #else 148 #define SIP_NTXSEGS 16 149 #define SIP_NTXSEGS_ALLOC 8 150 #endif 151 152 #define SIP_TXQUEUELEN 256 153 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 154 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 155 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 156 157 #if defined(DP83820) 158 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 159 #else 160 #define TX_DMAMAP_SIZE MCLBYTES 161 #endif 162 163 /* 164 * Receive descriptor list size. We have one Rx buffer per incoming 165 * packet, so this logic is a little simpler. 166 * 167 * Actually, on the DP83820, we allow the packet to consume more than 168 * one buffer, in order to support jumbo Ethernet frames. In that 169 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 170 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 171 * so we'd better be quick about handling receive interrupts. 172 */ 173 #if defined(DP83820) 174 #define SIP_NRXDESC 256 175 #else 176 #define SIP_NRXDESC 128 177 #endif /* DP83820 */ 178 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 179 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 180 181 /* 182 * Control structures are DMA'd to the SiS900 chip. We allocate them in 183 * a single clump that maps to a single DMA segment to make several things 184 * easier. 185 */ 186 struct sip_control_data { 187 /* 188 * The transmit descriptors. 189 */ 190 struct sip_desc scd_txdescs[SIP_NTXDESC]; 191 192 /* 193 * The receive descriptors. 194 */ 195 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 196 }; 197 198 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 199 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 200 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 201 202 /* 203 * Software state for transmit jobs. 204 */ 205 struct sip_txsoft { 206 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 207 bus_dmamap_t txs_dmamap; /* our DMA map */ 208 int txs_firstdesc; /* first descriptor in packet */ 209 int txs_lastdesc; /* last descriptor in packet */ 210 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 211 }; 212 213 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 214 215 /* 216 * Software state for receive jobs. 217 */ 218 struct sip_rxsoft { 219 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 220 bus_dmamap_t rxs_dmamap; /* our DMA map */ 221 }; 222 223 /* 224 * Software state per device. 225 */ 226 struct sip_softc { 227 struct device sc_dev; /* generic device information */ 228 bus_space_tag_t sc_st; /* bus space tag */ 229 bus_space_handle_t sc_sh; /* bus space handle */ 230 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 231 struct ethercom sc_ethercom; /* ethernet common data */ 232 void *sc_sdhook; /* shutdown hook */ 233 234 const struct sip_product *sc_model; /* which model are we? */ 235 int sc_rev; /* chip revision */ 236 237 void *sc_ih; /* interrupt cookie */ 238 239 struct mii_data sc_mii; /* MII/media information */ 240 241 struct callout sc_tick_ch; /* tick callout */ 242 243 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 244 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 245 246 /* 247 * Software state for transmit and receive descriptors. 248 */ 249 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 250 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 251 252 /* 253 * Control data structures. 254 */ 255 struct sip_control_data *sc_control_data; 256 #define sc_txdescs sc_control_data->scd_txdescs 257 #define sc_rxdescs sc_control_data->scd_rxdescs 258 259 #ifdef SIP_EVENT_COUNTERS 260 /* 261 * Event counters. 262 */ 263 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 264 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 265 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 266 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 267 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 268 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 269 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 270 struct evcnt sc_ev_rxpause; /* PAUSE received */ 271 #ifdef DP83820 272 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 273 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 274 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 275 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 276 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 277 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 278 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 279 #endif /* DP83820 */ 280 #endif /* SIP_EVENT_COUNTERS */ 281 282 u_int32_t sc_txcfg; /* prototype TXCFG register */ 283 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 284 u_int32_t sc_imr; /* prototype IMR register */ 285 u_int32_t sc_rfcr; /* prototype RFCR register */ 286 287 u_int32_t sc_cfg; /* prototype CFG register */ 288 289 #ifdef DP83820 290 u_int32_t sc_gpior; /* prototype GPIOR register */ 291 #endif /* DP83820 */ 292 293 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 294 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 295 296 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 297 298 int sc_flowflags; /* 802.3x flow control flags */ 299 #ifdef DP83820 300 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 301 #else 302 int sc_paused; /* paused indication */ 303 #endif 304 305 int sc_txfree; /* number of free Tx descriptors */ 306 int sc_txnext; /* next ready Tx descriptor */ 307 int sc_txwin; /* Tx descriptors since last intr */ 308 309 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 310 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 311 312 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 313 #if defined(DP83820) 314 int sc_rxdiscard; 315 int sc_rxlen; 316 struct mbuf *sc_rxhead; 317 struct mbuf *sc_rxtail; 318 struct mbuf **sc_rxtailp; 319 #endif /* DP83820 */ 320 321 #if NRND > 0 322 rndsource_element_t rnd_source; /* random source */ 323 #endif 324 }; 325 326 #ifdef DP83820 327 #define SIP_RXCHAIN_RESET(sc) \ 328 do { \ 329 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 330 *(sc)->sc_rxtailp = NULL; \ 331 (sc)->sc_rxlen = 0; \ 332 } while (/*CONSTCOND*/0) 333 334 #define SIP_RXCHAIN_LINK(sc, m) \ 335 do { \ 336 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 337 (sc)->sc_rxtailp = &(m)->m_next; \ 338 } while (/*CONSTCOND*/0) 339 #endif /* DP83820 */ 340 341 #ifdef SIP_EVENT_COUNTERS 342 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 343 #else 344 #define SIP_EVCNT_INCR(ev) /* nothing */ 345 #endif 346 347 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 348 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 349 350 #define SIP_CDTXSYNC(sc, x, n, ops) \ 351 do { \ 352 int __x, __n; \ 353 \ 354 __x = (x); \ 355 __n = (n); \ 356 \ 357 /* If it will wrap around, sync to the end of the ring. */ \ 358 if ((__x + __n) > SIP_NTXDESC) { \ 359 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 360 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 361 (SIP_NTXDESC - __x), (ops)); \ 362 __n -= (SIP_NTXDESC - __x); \ 363 __x = 0; \ 364 } \ 365 \ 366 /* Now sync whatever is left. */ \ 367 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 368 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 369 } while (0) 370 371 #define SIP_CDRXSYNC(sc, x, ops) \ 372 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 373 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 374 375 #ifdef DP83820 376 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 377 #define SIP_RXBUF_LEN (MCLBYTES - 8) 378 #else 379 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 380 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 381 #endif 382 #define SIP_INIT_RXDESC(sc, x) \ 383 do { \ 384 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 385 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 386 \ 387 __sipd->sipd_link = \ 388 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 389 __sipd->sipd_bufptr = \ 390 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 391 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 392 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 393 SIP_INIT_RXDESC_EXTSTS \ 394 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 395 } while (0) 396 397 #define SIP_CHIP_VERS(sc, v, p, r) \ 398 ((sc)->sc_model->sip_vendor == (v) && \ 399 (sc)->sc_model->sip_product == (p) && \ 400 (sc)->sc_rev == (r)) 401 402 #define SIP_CHIP_MODEL(sc, v, p) \ 403 ((sc)->sc_model->sip_vendor == (v) && \ 404 (sc)->sc_model->sip_product == (p)) 405 406 #if !defined(DP83820) 407 #define SIP_SIS900_REV(sc, rev) \ 408 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 409 #endif 410 411 #define SIP_TIMEOUT 1000 412 413 static void SIP_DECL(start)(struct ifnet *); 414 static void SIP_DECL(watchdog)(struct ifnet *); 415 static int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 416 static int SIP_DECL(init)(struct ifnet *); 417 static void SIP_DECL(stop)(struct ifnet *, int); 418 419 static void SIP_DECL(shutdown)(void *); 420 421 static void SIP_DECL(reset)(struct sip_softc *); 422 static void SIP_DECL(rxdrain)(struct sip_softc *); 423 static int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 424 static void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, 425 u_int16_t *); 426 static void SIP_DECL(tick)(void *); 427 428 #if !defined(DP83820) 429 static void SIP_DECL(sis900_set_filter)(struct sip_softc *); 430 #endif /* ! DP83820 */ 431 static void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 432 433 #if defined(DP83820) 434 static void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 435 const struct pci_attach_args *, u_int8_t *); 436 #else 437 static void SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc); 438 static void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 439 const struct pci_attach_args *, u_int8_t *); 440 static void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 441 const struct pci_attach_args *, u_int8_t *); 442 #endif /* DP83820 */ 443 444 static int SIP_DECL(intr)(void *); 445 static void SIP_DECL(txintr)(struct sip_softc *); 446 static void SIP_DECL(rxintr)(struct sip_softc *); 447 448 #if defined(DP83820) 449 static int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 450 static void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 451 static void SIP_DECL(dp83820_mii_statchg)(struct device *); 452 #else 453 static int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 454 static void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 455 static void SIP_DECL(sis900_mii_statchg)(struct device *); 456 457 static int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 458 static void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 459 static void SIP_DECL(dp83815_mii_statchg)(struct device *); 460 #endif /* DP83820 */ 461 462 static int SIP_DECL(mediachange)(struct ifnet *); 463 static void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 464 465 static int SIP_DECL(match)(struct device *, struct cfdata *, void *); 466 static void SIP_DECL(attach)(struct device *, struct device *, void *); 467 468 int SIP_DECL(copy_small) = 0; 469 470 #ifdef DP83820 471 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 472 gsip_match, gsip_attach, NULL, NULL); 473 #else 474 CFATTACH_DECL(sip, sizeof(struct sip_softc), 475 sip_match, sip_attach, NULL, NULL); 476 #endif 477 478 /* 479 * Descriptions of the variants of the SiS900. 480 */ 481 struct sip_variant { 482 int (*sipv_mii_readreg)(struct device *, int, int); 483 void (*sipv_mii_writereg)(struct device *, int, int, int); 484 void (*sipv_mii_statchg)(struct device *); 485 void (*sipv_set_filter)(struct sip_softc *); 486 void (*sipv_read_macaddr)(struct sip_softc *, 487 const struct pci_attach_args *, u_int8_t *); 488 }; 489 490 static u_int32_t SIP_DECL(mii_bitbang_read)(struct device *); 491 static void SIP_DECL(mii_bitbang_write)(struct device *, u_int32_t); 492 493 static const struct mii_bitbang_ops SIP_DECL(mii_bitbang_ops) = { 494 SIP_DECL(mii_bitbang_read), 495 SIP_DECL(mii_bitbang_write), 496 { 497 EROMAR_MDIO, /* MII_BIT_MDO */ 498 EROMAR_MDIO, /* MII_BIT_MDI */ 499 EROMAR_MDC, /* MII_BIT_MDC */ 500 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 501 0, /* MII_BIT_DIR_PHY_HOST */ 502 } 503 }; 504 505 #if defined(DP83820) 506 static const struct sip_variant SIP_DECL(variant_dp83820) = { 507 SIP_DECL(dp83820_mii_readreg), 508 SIP_DECL(dp83820_mii_writereg), 509 SIP_DECL(dp83820_mii_statchg), 510 SIP_DECL(dp83815_set_filter), 511 SIP_DECL(dp83820_read_macaddr), 512 }; 513 #else 514 static const struct sip_variant SIP_DECL(variant_sis900) = { 515 SIP_DECL(sis900_mii_readreg), 516 SIP_DECL(sis900_mii_writereg), 517 SIP_DECL(sis900_mii_statchg), 518 SIP_DECL(sis900_set_filter), 519 SIP_DECL(sis900_read_macaddr), 520 }; 521 522 static const struct sip_variant SIP_DECL(variant_dp83815) = { 523 SIP_DECL(dp83815_mii_readreg), 524 SIP_DECL(dp83815_mii_writereg), 525 SIP_DECL(dp83815_mii_statchg), 526 SIP_DECL(dp83815_set_filter), 527 SIP_DECL(dp83815_read_macaddr), 528 }; 529 #endif /* DP83820 */ 530 531 /* 532 * Devices supported by this driver. 533 */ 534 static const struct sip_product { 535 pci_vendor_id_t sip_vendor; 536 pci_product_id_t sip_product; 537 const char *sip_name; 538 const struct sip_variant *sip_variant; 539 } SIP_DECL(products)[] = { 540 #if defined(DP83820) 541 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 542 "NatSemi DP83820 Gigabit Ethernet", 543 &SIP_DECL(variant_dp83820) }, 544 #else 545 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 546 "SiS 900 10/100 Ethernet", 547 &SIP_DECL(variant_sis900) }, 548 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 549 "SiS 7016 10/100 Ethernet", 550 &SIP_DECL(variant_sis900) }, 551 552 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 553 "NatSemi DP83815 10/100 Ethernet", 554 &SIP_DECL(variant_dp83815) }, 555 #endif /* DP83820 */ 556 557 { 0, 0, 558 NULL, 559 NULL }, 560 }; 561 562 static const struct sip_product * 563 SIP_DECL(lookup)(const struct pci_attach_args *pa) 564 { 565 const struct sip_product *sip; 566 567 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 568 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 569 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 570 return (sip); 571 } 572 return (NULL); 573 } 574 575 #ifdef DP83820 576 /* 577 * I really hate stupid hardware vendors. There's a bit in the EEPROM 578 * which indicates if the card can do 64-bit data transfers. Unfortunately, 579 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 580 * which means we try to use 64-bit data transfers on those cards if we 581 * happen to be plugged into a 32-bit slot. 582 * 583 * What we do is use this table of cards known to be 64-bit cards. If 584 * you have a 64-bit card who's subsystem ID is not listed in this table, 585 * send the output of "pcictl dump ..." of the device to me so that your 586 * card will use the 64-bit data path when plugged into a 64-bit slot. 587 * 588 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 589 * June 30, 2002 590 */ 591 static int 592 SIP_DECL(check_64bit)(const struct pci_attach_args *pa) 593 { 594 static const struct { 595 pci_vendor_id_t c64_vendor; 596 pci_product_id_t c64_product; 597 } card64[] = { 598 /* Asante GigaNIX */ 599 { 0x128a, 0x0002 }, 600 601 /* Accton EN1407-T, Planex GN-1000TE */ 602 { 0x1113, 0x1407 }, 603 604 /* Netgear GA-621 */ 605 { 0x1385, 0x621a }, 606 607 /* SMC EZ Card */ 608 { 0x10b8, 0x9462 }, 609 610 { 0, 0} 611 }; 612 pcireg_t subsys; 613 int i; 614 615 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 616 617 for (i = 0; card64[i].c64_vendor != 0; i++) { 618 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 619 PCI_PRODUCT(subsys) == card64[i].c64_product) 620 return (1); 621 } 622 623 return (0); 624 } 625 #endif /* DP83820 */ 626 627 static int 628 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 629 { 630 struct pci_attach_args *pa = aux; 631 632 if (SIP_DECL(lookup)(pa) != NULL) 633 return (1); 634 635 return (0); 636 } 637 638 static void 639 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 640 { 641 struct sip_softc *sc = (struct sip_softc *) self; 642 struct pci_attach_args *pa = aux; 643 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 644 pci_chipset_tag_t pc = pa->pa_pc; 645 pci_intr_handle_t ih; 646 const char *intrstr = NULL; 647 bus_space_tag_t iot, memt; 648 bus_space_handle_t ioh, memh; 649 bus_dma_segment_t seg; 650 int ioh_valid, memh_valid; 651 int i, rseg, error; 652 const struct sip_product *sip; 653 pcireg_t pmode; 654 u_int8_t enaddr[ETHER_ADDR_LEN]; 655 int pmreg; 656 #ifdef DP83820 657 pcireg_t memtype; 658 u_int32_t reg; 659 #endif /* DP83820 */ 660 661 callout_init(&sc->sc_tick_ch); 662 663 sip = SIP_DECL(lookup)(pa); 664 if (sip == NULL) { 665 printf("\n"); 666 panic(SIP_STR(attach) ": impossible"); 667 } 668 sc->sc_rev = PCI_REVISION(pa->pa_class); 669 670 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 671 672 sc->sc_model = sip; 673 674 /* 675 * XXX Work-around broken PXE firmware on some boards. 676 * 677 * The DP83815 shares an address decoder with the MEM BAR 678 * and the ROM BAR. Make sure the ROM BAR is disabled, 679 * so that memory mapped access works. 680 */ 681 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 682 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 683 ~PCI_MAPREG_ROM_ENABLE); 684 685 /* 686 * Map the device. 687 */ 688 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 689 PCI_MAPREG_TYPE_IO, 0, 690 &iot, &ioh, NULL, NULL) == 0); 691 #ifdef DP83820 692 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 693 switch (memtype) { 694 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 695 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 696 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 697 memtype, 0, &memt, &memh, NULL, NULL) == 0); 698 break; 699 default: 700 memh_valid = 0; 701 } 702 #else 703 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 704 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 705 &memt, &memh, NULL, NULL) == 0); 706 #endif /* DP83820 */ 707 708 if (memh_valid) { 709 sc->sc_st = memt; 710 sc->sc_sh = memh; 711 } else if (ioh_valid) { 712 sc->sc_st = iot; 713 sc->sc_sh = ioh; 714 } else { 715 printf("%s: unable to map device registers\n", 716 sc->sc_dev.dv_xname); 717 return; 718 } 719 720 sc->sc_dmat = pa->pa_dmat; 721 722 /* 723 * Make sure bus mastering is enabled. Also make sure 724 * Write/Invalidate is enabled if we're allowed to use it. 725 */ 726 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 727 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 728 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 729 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 730 pmreg | PCI_COMMAND_MASTER_ENABLE); 731 732 /* Get it out of power save mode if needed. */ 733 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 734 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 735 PCI_PMCSR_STATE_MASK; 736 if (pmode == PCI_PMCSR_STATE_D3) { 737 /* 738 * The card has lost all configuration data in 739 * this state, so punt. 740 */ 741 printf("%s: unable to wake up from power state D3\n", 742 sc->sc_dev.dv_xname); 743 return; 744 } 745 if (pmode != PCI_PMCSR_STATE_D0) { 746 printf("%s: waking up from power state D%d\n", 747 sc->sc_dev.dv_xname, pmode); 748 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 749 PCI_PMCSR_STATE_D0); 750 } 751 } 752 753 /* 754 * Map and establish our interrupt. 755 */ 756 if (pci_intr_map(pa, &ih)) { 757 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 758 return; 759 } 760 intrstr = pci_intr_string(pc, ih); 761 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 762 if (sc->sc_ih == NULL) { 763 printf("%s: unable to establish interrupt", 764 sc->sc_dev.dv_xname); 765 if (intrstr != NULL) 766 printf(" at %s", intrstr); 767 printf("\n"); 768 return; 769 } 770 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 771 772 SIMPLEQ_INIT(&sc->sc_txfreeq); 773 SIMPLEQ_INIT(&sc->sc_txdirtyq); 774 775 /* 776 * Allocate the control data structures, and create and load the 777 * DMA map for it. 778 */ 779 if ((error = bus_dmamem_alloc(sc->sc_dmat, 780 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 781 0)) != 0) { 782 printf("%s: unable to allocate control data, error = %d\n", 783 sc->sc_dev.dv_xname, error); 784 goto fail_0; 785 } 786 787 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 788 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 789 BUS_DMA_COHERENT)) != 0) { 790 printf("%s: unable to map control data, error = %d\n", 791 sc->sc_dev.dv_xname, error); 792 goto fail_1; 793 } 794 795 if ((error = bus_dmamap_create(sc->sc_dmat, 796 sizeof(struct sip_control_data), 1, 797 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 798 printf("%s: unable to create control data DMA map, " 799 "error = %d\n", sc->sc_dev.dv_xname, error); 800 goto fail_2; 801 } 802 803 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 804 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 805 0)) != 0) { 806 printf("%s: unable to load control data DMA map, error = %d\n", 807 sc->sc_dev.dv_xname, error); 808 goto fail_3; 809 } 810 811 /* 812 * Create the transmit buffer DMA maps. 813 */ 814 for (i = 0; i < SIP_TXQUEUELEN; i++) { 815 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 816 SIP_NTXSEGS, MCLBYTES, 0, 0, 817 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 818 printf("%s: unable to create tx DMA map %d, " 819 "error = %d\n", sc->sc_dev.dv_xname, i, error); 820 goto fail_4; 821 } 822 } 823 824 /* 825 * Create the receive buffer DMA maps. 826 */ 827 for (i = 0; i < SIP_NRXDESC; i++) { 828 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 829 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 830 printf("%s: unable to create rx DMA map %d, " 831 "error = %d\n", sc->sc_dev.dv_xname, i, error); 832 goto fail_5; 833 } 834 sc->sc_rxsoft[i].rxs_mbuf = NULL; 835 } 836 837 /* 838 * Reset the chip to a known state. 839 */ 840 SIP_DECL(reset)(sc); 841 842 /* 843 * Read the Ethernet address from the EEPROM. This might 844 * also fetch other stuff from the EEPROM and stash it 845 * in the softc. 846 */ 847 sc->sc_cfg = 0; 848 #if !defined(DP83820) 849 if (SIP_SIS900_REV(sc,SIS_REV_635) || 850 SIP_SIS900_REV(sc,SIS_REV_900B)) 851 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 852 853 if (SIP_SIS900_REV(sc,SIS_REV_635) || 854 SIP_SIS900_REV(sc,SIS_REV_960) || 855 SIP_SIS900_REV(sc,SIS_REV_900B)) 856 sc->sc_cfg |= (bus_space_read_4(sc->sc_st, sc->sc_sh, 857 SIP_CFG) & CFG_EDBMASTEN); 858 #endif 859 860 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 861 862 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 863 ether_sprintf(enaddr)); 864 865 /* 866 * Initialize the configuration register: aggressive PCI 867 * bus request algorithm, default backoff, default OW timer, 868 * default parity error detection. 869 * 870 * NOTE: "Big endian mode" is useless on the SiS900 and 871 * friends -- it affects packet data, not descriptors. 872 */ 873 #ifdef DP83820 874 /* 875 * Cause the chip to load configuration data from the EEPROM. 876 */ 877 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 878 for (i = 0; i < 10000; i++) { 879 delay(10); 880 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 881 PTSCR_EELOAD_EN) == 0) 882 break; 883 } 884 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 885 PTSCR_EELOAD_EN) { 886 printf("%s: timeout loading configuration from EEPROM\n", 887 sc->sc_dev.dv_xname); 888 return; 889 } 890 891 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 892 893 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 894 if (reg & CFG_PCI64_DET) { 895 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 896 /* 897 * Check to see if this card is 64-bit. If so, enable 64-bit 898 * data transfers. 899 * 900 * We can't use the DATA64_EN bit in the EEPROM, because 901 * vendors of 32-bit cards fail to clear that bit in many 902 * cases (yet the card still detects that it's in a 64-bit 903 * slot; go figure). 904 */ 905 if (SIP_DECL(check_64bit)(pa)) { 906 sc->sc_cfg |= CFG_DATA64_EN; 907 printf(", using 64-bit data transfers"); 908 } 909 printf("\n"); 910 } 911 912 /* 913 * XXX Need some PCI flags indicating support for 914 * XXX 64-bit addressing. 915 */ 916 #if 0 917 if (reg & CFG_M64ADDR) 918 sc->sc_cfg |= CFG_M64ADDR; 919 if (reg & CFG_T64ADDR) 920 sc->sc_cfg |= CFG_T64ADDR; 921 #endif 922 923 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 924 const char *sep = ""; 925 printf("%s: using ", sc->sc_dev.dv_xname); 926 if (reg & CFG_EXT_125) { 927 sc->sc_cfg |= CFG_EXT_125; 928 printf("%s125MHz clock", sep); 929 sep = ", "; 930 } 931 if (reg & CFG_TBI_EN) { 932 sc->sc_cfg |= CFG_TBI_EN; 933 printf("%sten-bit interface", sep); 934 sep = ", "; 935 } 936 printf("\n"); 937 } 938 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 939 (reg & CFG_MRM_DIS) != 0) 940 sc->sc_cfg |= CFG_MRM_DIS; 941 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 942 (reg & CFG_MWI_DIS) != 0) 943 sc->sc_cfg |= CFG_MWI_DIS; 944 945 /* 946 * Use the extended descriptor format on the DP83820. This 947 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 948 * checksumming. 949 */ 950 sc->sc_cfg |= CFG_EXTSTS_EN; 951 #endif /* DP83820 */ 952 953 /* 954 * Initialize our media structures and probe the MII. 955 */ 956 sc->sc_mii.mii_ifp = ifp; 957 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 958 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 959 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 960 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, SIP_DECL(mediachange), 961 SIP_DECL(mediastatus)); 962 963 /* 964 * XXX We cannot handle flow control on the DP83815. 965 */ 966 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 967 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 968 MII_OFFSET_ANY, 0); 969 else 970 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 971 MII_OFFSET_ANY, MIIF_DOPAUSE); 972 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 973 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 974 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 975 } else 976 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 977 978 ifp = &sc->sc_ethercom.ec_if; 979 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 980 ifp->if_softc = sc; 981 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 982 ifp->if_ioctl = SIP_DECL(ioctl); 983 ifp->if_start = SIP_DECL(start); 984 ifp->if_watchdog = SIP_DECL(watchdog); 985 ifp->if_init = SIP_DECL(init); 986 ifp->if_stop = SIP_DECL(stop); 987 IFQ_SET_READY(&ifp->if_snd); 988 989 /* 990 * We can support 802.1Q VLAN-sized frames. 991 */ 992 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 993 994 #ifdef DP83820 995 /* 996 * And the DP83820 can do VLAN tagging in hardware, and 997 * support the jumbo Ethernet MTU. 998 */ 999 sc->sc_ethercom.ec_capabilities |= 1000 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1001 1002 /* 1003 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1004 * in hardware. 1005 */ 1006 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 1007 IFCAP_CSUM_UDPv4; 1008 #endif /* DP83820 */ 1009 1010 /* 1011 * Attach the interface. 1012 */ 1013 if_attach(ifp); 1014 ether_ifattach(ifp, enaddr); 1015 #if NRND > 0 1016 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1017 RND_TYPE_NET, 0); 1018 #endif 1019 1020 /* 1021 * The number of bytes that must be available in 1022 * the Tx FIFO before the bus master can DMA more 1023 * data into the FIFO. 1024 */ 1025 sc->sc_tx_fill_thresh = 64 / 32; 1026 1027 /* 1028 * Start at a drain threshold of 512 bytes. We will 1029 * increase it if a DMA underrun occurs. 1030 * 1031 * XXX The minimum value of this variable should be 1032 * tuned. We may be able to improve performance 1033 * by starting with a lower value. That, however, 1034 * may trash the first few outgoing packets if the 1035 * PCI bus is saturated. 1036 */ 1037 #ifdef DP83820 1038 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1039 #else 1040 sc->sc_tx_drain_thresh = 1504 / 32; 1041 #endif 1042 1043 /* 1044 * Initialize the Rx FIFO drain threshold. 1045 * 1046 * This is in units of 8 bytes. 1047 * 1048 * We should never set this value lower than 2; 14 bytes are 1049 * required to filter the packet. 1050 */ 1051 sc->sc_rx_drain_thresh = 128 / 8; 1052 1053 #ifdef SIP_EVENT_COUNTERS 1054 /* 1055 * Attach event counters. 1056 */ 1057 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1058 NULL, sc->sc_dev.dv_xname, "txsstall"); 1059 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1060 NULL, sc->sc_dev.dv_xname, "txdstall"); 1061 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1062 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1063 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1064 NULL, sc->sc_dev.dv_xname, "txdintr"); 1065 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1066 NULL, sc->sc_dev.dv_xname, "txiintr"); 1067 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1068 NULL, sc->sc_dev.dv_xname, "rxintr"); 1069 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1070 NULL, sc->sc_dev.dv_xname, "hiberr"); 1071 #ifndef DP83820 1072 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1073 NULL, sc->sc_dev.dv_xname, "rxpause"); 1074 #endif /* !DP83820 */ 1075 #ifdef DP83820 1076 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1077 NULL, sc->sc_dev.dv_xname, "rxpause"); 1078 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1079 NULL, sc->sc_dev.dv_xname, "txpause"); 1080 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1081 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1082 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1083 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1084 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1085 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1086 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1087 NULL, sc->sc_dev.dv_xname, "txipsum"); 1088 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1089 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1090 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1091 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1092 #endif /* DP83820 */ 1093 #endif /* SIP_EVENT_COUNTERS */ 1094 1095 /* 1096 * Make sure the interface is shutdown during reboot. 1097 */ 1098 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 1099 if (sc->sc_sdhook == NULL) 1100 printf("%s: WARNING: unable to establish shutdown hook\n", 1101 sc->sc_dev.dv_xname); 1102 return; 1103 1104 /* 1105 * Free any resources we've allocated during the failed attach 1106 * attempt. Do this in reverse order and fall through. 1107 */ 1108 fail_5: 1109 for (i = 0; i < SIP_NRXDESC; i++) { 1110 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1111 bus_dmamap_destroy(sc->sc_dmat, 1112 sc->sc_rxsoft[i].rxs_dmamap); 1113 } 1114 fail_4: 1115 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1116 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1117 bus_dmamap_destroy(sc->sc_dmat, 1118 sc->sc_txsoft[i].txs_dmamap); 1119 } 1120 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1121 fail_3: 1122 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1123 fail_2: 1124 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1125 sizeof(struct sip_control_data)); 1126 fail_1: 1127 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1128 fail_0: 1129 return; 1130 } 1131 1132 /* 1133 * sip_shutdown: 1134 * 1135 * Make sure the interface is stopped at reboot time. 1136 */ 1137 static void 1138 SIP_DECL(shutdown)(void *arg) 1139 { 1140 struct sip_softc *sc = arg; 1141 1142 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1143 } 1144 1145 /* 1146 * sip_start: [ifnet interface function] 1147 * 1148 * Start packet transmission on the interface. 1149 */ 1150 static void 1151 SIP_DECL(start)(struct ifnet *ifp) 1152 { 1153 struct sip_softc *sc = ifp->if_softc; 1154 struct mbuf *m0; 1155 #ifndef DP83820 1156 struct mbuf *m; 1157 #endif 1158 struct sip_txsoft *txs; 1159 bus_dmamap_t dmamap; 1160 int error, nexttx, lasttx, seg; 1161 int ofree = sc->sc_txfree; 1162 #if 0 1163 int firsttx = sc->sc_txnext; 1164 #endif 1165 #ifdef DP83820 1166 struct m_tag *mtag; 1167 u_int32_t extsts; 1168 #endif 1169 1170 #ifndef DP83820 1171 /* 1172 * If we've been told to pause, don't transmit any more packets. 1173 */ 1174 if (sc->sc_paused) 1175 ifp->if_flags |= IFF_OACTIVE; 1176 #endif 1177 1178 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1179 return; 1180 1181 /* 1182 * Loop through the send queue, setting up transmit descriptors 1183 * until we drain the queue, or use up all available transmit 1184 * descriptors. 1185 */ 1186 for (;;) { 1187 /* Get a work queue entry. */ 1188 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1189 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1190 break; 1191 } 1192 1193 /* 1194 * Grab a packet off the queue. 1195 */ 1196 IFQ_POLL(&ifp->if_snd, m0); 1197 if (m0 == NULL) 1198 break; 1199 #ifndef DP83820 1200 m = NULL; 1201 #endif 1202 1203 dmamap = txs->txs_dmamap; 1204 1205 #ifdef DP83820 1206 /* 1207 * Load the DMA map. If this fails, the packet either 1208 * didn't fit in the allotted number of segments, or we 1209 * were short on resources. For the too-many-segments 1210 * case, we simply report an error and drop the packet, 1211 * since we can't sanely copy a jumbo packet to a single 1212 * buffer. 1213 */ 1214 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1215 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1216 if (error) { 1217 if (error == EFBIG) { 1218 printf("%s: Tx packet consumes too many " 1219 "DMA segments, dropping...\n", 1220 sc->sc_dev.dv_xname); 1221 IFQ_DEQUEUE(&ifp->if_snd, m0); 1222 m_freem(m0); 1223 continue; 1224 } 1225 /* 1226 * Short on resources, just stop for now. 1227 */ 1228 break; 1229 } 1230 #else /* DP83820 */ 1231 /* 1232 * Load the DMA map. If this fails, the packet either 1233 * didn't fit in the alloted number of segments, or we 1234 * were short on resources. In this case, we'll copy 1235 * and try again. 1236 */ 1237 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1238 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1239 MGETHDR(m, M_DONTWAIT, MT_DATA); 1240 if (m == NULL) { 1241 printf("%s: unable to allocate Tx mbuf\n", 1242 sc->sc_dev.dv_xname); 1243 break; 1244 } 1245 if (m0->m_pkthdr.len > MHLEN) { 1246 MCLGET(m, M_DONTWAIT); 1247 if ((m->m_flags & M_EXT) == 0) { 1248 printf("%s: unable to allocate Tx " 1249 "cluster\n", sc->sc_dev.dv_xname); 1250 m_freem(m); 1251 break; 1252 } 1253 } 1254 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1255 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1256 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1257 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1258 if (error) { 1259 printf("%s: unable to load Tx buffer, " 1260 "error = %d\n", sc->sc_dev.dv_xname, error); 1261 break; 1262 } 1263 } 1264 #endif /* DP83820 */ 1265 1266 /* 1267 * Ensure we have enough descriptors free to describe 1268 * the packet. Note, we always reserve one descriptor 1269 * at the end of the ring as a termination point, to 1270 * prevent wrap-around. 1271 */ 1272 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1273 /* 1274 * Not enough free descriptors to transmit this 1275 * packet. We haven't committed anything yet, 1276 * so just unload the DMA map, put the packet 1277 * back on the queue, and punt. Notify the upper 1278 * layer that there are not more slots left. 1279 * 1280 * XXX We could allocate an mbuf and copy, but 1281 * XXX is it worth it? 1282 */ 1283 ifp->if_flags |= IFF_OACTIVE; 1284 bus_dmamap_unload(sc->sc_dmat, dmamap); 1285 #ifndef DP83820 1286 if (m != NULL) 1287 m_freem(m); 1288 #endif 1289 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1290 break; 1291 } 1292 1293 IFQ_DEQUEUE(&ifp->if_snd, m0); 1294 #ifndef DP83820 1295 if (m != NULL) { 1296 m_freem(m0); 1297 m0 = m; 1298 } 1299 #endif 1300 1301 /* 1302 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1303 */ 1304 1305 /* Sync the DMA map. */ 1306 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1307 BUS_DMASYNC_PREWRITE); 1308 1309 /* 1310 * Initialize the transmit descriptors. 1311 */ 1312 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1313 seg < dmamap->dm_nsegs; 1314 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1315 /* 1316 * If this is the first descriptor we're 1317 * enqueueing, don't set the OWN bit just 1318 * yet. That could cause a race condition. 1319 * We'll do it below. 1320 */ 1321 sc->sc_txdescs[nexttx].sipd_bufptr = 1322 htole32(dmamap->dm_segs[seg].ds_addr); 1323 sc->sc_txdescs[nexttx].sipd_cmdsts = 1324 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1325 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1326 #ifdef DP83820 1327 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1328 #endif /* DP83820 */ 1329 lasttx = nexttx; 1330 } 1331 1332 /* Clear the MORE bit on the last segment. */ 1333 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1334 1335 /* 1336 * If we're in the interrupt delay window, delay the 1337 * interrupt. 1338 */ 1339 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1340 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1341 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1342 htole32(CMDSTS_INTR); 1343 sc->sc_txwin = 0; 1344 } 1345 1346 #ifdef DP83820 1347 /* 1348 * If VLANs are enabled and the packet has a VLAN tag, set 1349 * up the descriptor to encapsulate the packet for us. 1350 * 1351 * This apparently has to be on the last descriptor of 1352 * the packet. 1353 */ 1354 if (sc->sc_ethercom.ec_nvlans != 0 && 1355 (mtag = m_tag_find(m0, PACKET_TAG_VLAN, NULL)) != NULL) { 1356 sc->sc_txdescs[lasttx].sipd_extsts |= 1357 htole32(EXTSTS_VPKT | 1358 (*(u_int *)(mtag + 1) & EXTSTS_VTCI)); 1359 } 1360 1361 /* 1362 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1363 * checksumming, set up the descriptor to do this work 1364 * for us. 1365 * 1366 * This apparently has to be on the first descriptor of 1367 * the packet. 1368 * 1369 * Byte-swap constants so the compiler can optimize. 1370 */ 1371 extsts = 0; 1372 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1373 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1374 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1375 extsts |= htole32(EXTSTS_IPPKT); 1376 } 1377 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1378 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1379 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1380 extsts |= htole32(EXTSTS_TCPPKT); 1381 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1382 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1383 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1384 extsts |= htole32(EXTSTS_UDPPKT); 1385 } 1386 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1387 #endif /* DP83820 */ 1388 1389 /* Sync the descriptors we're using. */ 1390 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1391 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1392 1393 /* 1394 * The entire packet is set up. Give the first descrptor 1395 * to the chip now. 1396 */ 1397 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1398 htole32(CMDSTS_OWN); 1399 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1400 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1401 1402 /* 1403 * Store a pointer to the packet so we can free it later, 1404 * and remember what txdirty will be once the packet is 1405 * done. 1406 */ 1407 txs->txs_mbuf = m0; 1408 txs->txs_firstdesc = sc->sc_txnext; 1409 txs->txs_lastdesc = lasttx; 1410 1411 /* Advance the tx pointer. */ 1412 sc->sc_txfree -= dmamap->dm_nsegs; 1413 sc->sc_txnext = nexttx; 1414 1415 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1416 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1417 1418 #if NBPFILTER > 0 1419 /* 1420 * Pass the packet to any BPF listeners. 1421 */ 1422 if (ifp->if_bpf) 1423 bpf_mtap(ifp->if_bpf, m0); 1424 #endif /* NBPFILTER > 0 */ 1425 } 1426 1427 if (txs == NULL || sc->sc_txfree == 0) { 1428 /* No more slots left; notify upper layer. */ 1429 ifp->if_flags |= IFF_OACTIVE; 1430 } 1431 1432 if (sc->sc_txfree != ofree) { 1433 /* 1434 * Start the transmit process. Note, the manual says 1435 * that if there are no pending transmissions in the 1436 * chip's internal queue (indicated by TXE being clear), 1437 * then the driver software must set the TXDP to the 1438 * first descriptor to be transmitted. However, if we 1439 * do this, it causes serious performance degredation on 1440 * the DP83820 under load, not setting TXDP doesn't seem 1441 * to adversely affect the SiS 900 or DP83815. 1442 * 1443 * Well, I guess it wouldn't be the first time a manual 1444 * has lied -- and they could be speaking of the NULL- 1445 * terminated descriptor list case, rather than OWN- 1446 * terminated rings. 1447 */ 1448 #if 0 1449 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1450 CR_TXE) == 0) { 1451 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1452 SIP_CDTXADDR(sc, firsttx)); 1453 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1454 } 1455 #else 1456 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1457 #endif 1458 1459 /* Set a watchdog timer in case the chip flakes out. */ 1460 #ifdef DP83820 1461 /* Gigabit autonegotiation takes 5 seconds. */ 1462 ifp->if_timer = 10; 1463 #else 1464 ifp->if_timer = 5; 1465 #endif 1466 } 1467 } 1468 1469 /* 1470 * sip_watchdog: [ifnet interface function] 1471 * 1472 * Watchdog timer handler. 1473 */ 1474 static void 1475 SIP_DECL(watchdog)(struct ifnet *ifp) 1476 { 1477 struct sip_softc *sc = ifp->if_softc; 1478 1479 /* 1480 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1481 * If we get a timeout, try and sweep up transmit descriptors. 1482 * If we manage to sweep them all up, ignore the lack of 1483 * interrupt. 1484 */ 1485 SIP_DECL(txintr)(sc); 1486 1487 if (sc->sc_txfree != SIP_NTXDESC) { 1488 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1489 ifp->if_oerrors++; 1490 1491 /* Reset the interface. */ 1492 (void) SIP_DECL(init)(ifp); 1493 } else if (ifp->if_flags & IFF_DEBUG) 1494 printf("%s: recovered from device timeout\n", 1495 sc->sc_dev.dv_xname); 1496 1497 /* Try to get more packets going. */ 1498 SIP_DECL(start)(ifp); 1499 } 1500 1501 /* 1502 * sip_ioctl: [ifnet interface function] 1503 * 1504 * Handle control requests from the operator. 1505 */ 1506 static int 1507 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1508 { 1509 struct sip_softc *sc = ifp->if_softc; 1510 struct ifreq *ifr = (struct ifreq *)data; 1511 int s, error; 1512 1513 s = splnet(); 1514 1515 switch (cmd) { 1516 case SIOCSIFMEDIA: 1517 /* Flow control requires full-duplex mode. */ 1518 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1519 (ifr->ifr_media & IFM_FDX) == 0) 1520 ifr->ifr_media &= ~IFM_ETH_FMASK; 1521 #ifdef DP83820 1522 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1523 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1524 /* We can do both TXPAUSE and RXPAUSE. */ 1525 ifr->ifr_media |= 1526 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1527 } 1528 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1529 } 1530 #else 1531 /* XXX */ 1532 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1533 ifr->ifr_media &= ~IFM_ETH_FMASK; 1534 1535 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1536 if (ifr->ifr_media & IFM_FLOW) { 1537 /* 1538 * Both TXPAUSE and RXPAUSE must be set. 1539 * (SiS900 and DP83815 don't have PAUSE_ASYM 1540 * feature.) 1541 * 1542 * XXX Can SiS900 and DP83815 send PAUSE? 1543 */ 1544 ifr->ifr_media |= 1545 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1546 } 1547 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1548 } 1549 #endif 1550 /* FALLTHROUGH */ 1551 case SIOCGIFMEDIA: 1552 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1553 break; 1554 1555 default: 1556 error = ether_ioctl(ifp, cmd, data); 1557 if (error == ENETRESET) { 1558 /* 1559 * Multicast list has changed; set the hardware filter 1560 * accordingly. 1561 */ 1562 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1563 error = 0; 1564 } 1565 break; 1566 } 1567 1568 /* Try to get more packets going. */ 1569 SIP_DECL(start)(ifp); 1570 1571 splx(s); 1572 return (error); 1573 } 1574 1575 /* 1576 * sip_intr: 1577 * 1578 * Interrupt service routine. 1579 */ 1580 static int 1581 SIP_DECL(intr)(void *arg) 1582 { 1583 struct sip_softc *sc = arg; 1584 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1585 u_int32_t isr; 1586 int handled = 0; 1587 1588 /* Disable interrupts. */ 1589 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1590 1591 for (;;) { 1592 /* Reading clears interrupt. */ 1593 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1594 if ((isr & sc->sc_imr) == 0) 1595 break; 1596 1597 #if NRND > 0 1598 if (RND_ENABLED(&sc->rnd_source)) 1599 rnd_add_uint32(&sc->rnd_source, isr); 1600 #endif 1601 1602 handled = 1; 1603 1604 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1605 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1606 1607 /* Grab any new packets. */ 1608 SIP_DECL(rxintr)(sc); 1609 1610 if (isr & ISR_RXORN) { 1611 printf("%s: receive FIFO overrun\n", 1612 sc->sc_dev.dv_xname); 1613 1614 /* XXX adjust rx_drain_thresh? */ 1615 } 1616 1617 if (isr & ISR_RXIDLE) { 1618 printf("%s: receive ring overrun\n", 1619 sc->sc_dev.dv_xname); 1620 1621 /* Get the receive process going again. */ 1622 bus_space_write_4(sc->sc_st, sc->sc_sh, 1623 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1624 bus_space_write_4(sc->sc_st, sc->sc_sh, 1625 SIP_CR, CR_RXE); 1626 } 1627 } 1628 1629 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1630 #ifdef SIP_EVENT_COUNTERS 1631 if (isr & ISR_TXDESC) 1632 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1633 else if (isr & ISR_TXIDLE) 1634 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1635 #endif 1636 1637 /* Sweep up transmit descriptors. */ 1638 SIP_DECL(txintr)(sc); 1639 1640 if (isr & ISR_TXURN) { 1641 u_int32_t thresh; 1642 1643 printf("%s: transmit FIFO underrun", 1644 sc->sc_dev.dv_xname); 1645 1646 thresh = sc->sc_tx_drain_thresh + 1; 1647 if (thresh <= TXCFG_DRTH && 1648 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1649 (sc->sc_tx_fill_thresh * 32))) { 1650 printf("; increasing Tx drain " 1651 "threshold to %u bytes\n", 1652 thresh * 32); 1653 sc->sc_tx_drain_thresh = thresh; 1654 (void) SIP_DECL(init)(ifp); 1655 } else { 1656 (void) SIP_DECL(init)(ifp); 1657 printf("\n"); 1658 } 1659 } 1660 } 1661 1662 #if !defined(DP83820) 1663 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1664 if (isr & ISR_PAUSE_ST) { 1665 sc->sc_paused = 1; 1666 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1667 ifp->if_flags |= IFF_OACTIVE; 1668 } 1669 if (isr & ISR_PAUSE_END) { 1670 sc->sc_paused = 0; 1671 ifp->if_flags &= ~IFF_OACTIVE; 1672 } 1673 } 1674 #endif /* ! DP83820 */ 1675 1676 if (isr & ISR_HIBERR) { 1677 int want_init = 0; 1678 1679 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1680 1681 #define PRINTERR(bit, str) \ 1682 do { \ 1683 if ((isr & (bit)) != 0) { \ 1684 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1685 printf("%s: %s\n", \ 1686 sc->sc_dev.dv_xname, str); \ 1687 want_init = 1; \ 1688 } \ 1689 } while (/*CONSTCOND*/0) 1690 1691 PRINTERR(ISR_DPERR, "parity error"); 1692 PRINTERR(ISR_SSERR, "system error"); 1693 PRINTERR(ISR_RMABT, "master abort"); 1694 PRINTERR(ISR_RTABT, "target abort"); 1695 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1696 /* 1697 * Ignore: 1698 * Tx reset complete 1699 * Rx reset complete 1700 */ 1701 if (want_init) 1702 (void) SIP_DECL(init)(ifp); 1703 #undef PRINTERR 1704 } 1705 } 1706 1707 /* Re-enable interrupts. */ 1708 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1709 1710 /* Try to get more packets going. */ 1711 SIP_DECL(start)(ifp); 1712 1713 return (handled); 1714 } 1715 1716 /* 1717 * sip_txintr: 1718 * 1719 * Helper; handle transmit interrupts. 1720 */ 1721 static void 1722 SIP_DECL(txintr)(struct sip_softc *sc) 1723 { 1724 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1725 struct sip_txsoft *txs; 1726 u_int32_t cmdsts; 1727 1728 #ifndef DP83820 1729 if (sc->sc_paused == 0) 1730 #endif 1731 ifp->if_flags &= ~IFF_OACTIVE; 1732 1733 /* 1734 * Go through our Tx list and free mbufs for those 1735 * frames which have been transmitted. 1736 */ 1737 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1738 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1739 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1740 1741 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1742 if (cmdsts & CMDSTS_OWN) 1743 break; 1744 1745 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1746 1747 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1748 1749 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1750 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1751 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1752 m_freem(txs->txs_mbuf); 1753 txs->txs_mbuf = NULL; 1754 1755 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1756 1757 /* 1758 * Check for errors and collisions. 1759 */ 1760 if (cmdsts & 1761 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1762 ifp->if_oerrors++; 1763 if (cmdsts & CMDSTS_Tx_EC) 1764 ifp->if_collisions += 16; 1765 if (ifp->if_flags & IFF_DEBUG) { 1766 if (cmdsts & CMDSTS_Tx_ED) 1767 printf("%s: excessive deferral\n", 1768 sc->sc_dev.dv_xname); 1769 if (cmdsts & CMDSTS_Tx_EC) 1770 printf("%s: excessive collisions\n", 1771 sc->sc_dev.dv_xname); 1772 } 1773 } else { 1774 /* Packet was transmitted successfully. */ 1775 ifp->if_opackets++; 1776 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1777 } 1778 } 1779 1780 /* 1781 * If there are no more pending transmissions, cancel the watchdog 1782 * timer. 1783 */ 1784 if (txs == NULL) { 1785 ifp->if_timer = 0; 1786 sc->sc_txwin = 0; 1787 } 1788 } 1789 1790 #if defined(DP83820) 1791 /* 1792 * sip_rxintr: 1793 * 1794 * Helper; handle receive interrupts. 1795 */ 1796 static void 1797 SIP_DECL(rxintr)(struct sip_softc *sc) 1798 { 1799 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1800 struct sip_rxsoft *rxs; 1801 struct mbuf *m, *tailm; 1802 u_int32_t cmdsts, extsts; 1803 int i, len, frame_len; 1804 1805 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1806 rxs = &sc->sc_rxsoft[i]; 1807 1808 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1809 1810 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1811 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1812 1813 /* 1814 * NOTE: OWN is set if owned by _consumer_. We're the 1815 * consumer of the receive ring, so if the bit is clear, 1816 * we have processed all of the packets. 1817 */ 1818 if ((cmdsts & CMDSTS_OWN) == 0) { 1819 /* 1820 * We have processed all of the receive buffers. 1821 */ 1822 break; 1823 } 1824 1825 if (__predict_false(sc->sc_rxdiscard)) { 1826 SIP_INIT_RXDESC(sc, i); 1827 if ((cmdsts & CMDSTS_MORE) == 0) { 1828 /* Reset our state. */ 1829 sc->sc_rxdiscard = 0; 1830 } 1831 continue; 1832 } 1833 1834 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1835 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1836 1837 m = rxs->rxs_mbuf; 1838 1839 /* 1840 * Add a new receive buffer to the ring. 1841 */ 1842 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1843 /* 1844 * Failed, throw away what we've done so 1845 * far, and discard the rest of the packet. 1846 */ 1847 ifp->if_ierrors++; 1848 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1849 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1850 SIP_INIT_RXDESC(sc, i); 1851 if (cmdsts & CMDSTS_MORE) 1852 sc->sc_rxdiscard = 1; 1853 if (sc->sc_rxhead != NULL) 1854 m_freem(sc->sc_rxhead); 1855 SIP_RXCHAIN_RESET(sc); 1856 continue; 1857 } 1858 1859 SIP_RXCHAIN_LINK(sc, m); 1860 1861 /* 1862 * If this is not the end of the packet, keep 1863 * looking. 1864 */ 1865 if (cmdsts & CMDSTS_MORE) { 1866 sc->sc_rxlen += m->m_len; 1867 continue; 1868 } 1869 1870 /* 1871 * Okay, we have the entire packet now... 1872 */ 1873 *sc->sc_rxtailp = NULL; 1874 m = sc->sc_rxhead; 1875 tailm = sc->sc_rxtail; 1876 frame_len = sc->sc_rxlen; 1877 1878 SIP_RXCHAIN_RESET(sc); 1879 1880 /* 1881 * If an error occurred, update stats and drop the packet. 1882 */ 1883 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1884 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1885 ifp->if_ierrors++; 1886 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1887 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1888 /* Receive overrun handled elsewhere. */ 1889 printf("%s: receive descriptor error\n", 1890 sc->sc_dev.dv_xname); 1891 } 1892 #define PRINTERR(bit, str) \ 1893 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1894 (cmdsts & (bit)) != 0) \ 1895 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1896 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1897 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1898 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1899 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1900 #undef PRINTERR 1901 m_freem(m); 1902 continue; 1903 } 1904 1905 /* 1906 * No errors. 1907 * 1908 * Note, the DP83820 includes the CRC with 1909 * every packet. 1910 */ 1911 len = CMDSTS_SIZE(cmdsts); 1912 frame_len += len; 1913 tailm->m_len = len; 1914 1915 /* 1916 * If the packet is small enough to fit in a 1917 * single header mbuf, allocate one and copy 1918 * the data into it. This greatly reduces 1919 * memory consumption when we receive lots 1920 * of small packets. 1921 */ 1922 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1923 struct mbuf *nm; 1924 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1925 if (nm == NULL) { 1926 ifp->if_ierrors++; 1927 m_freem(m); 1928 continue; 1929 } 1930 nm->m_data += 2; 1931 nm->m_pkthdr.len = nm->m_len = len; 1932 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1933 m_freem(m); 1934 m = nm; 1935 } 1936 #ifndef __NO_STRICT_ALIGNMENT 1937 else { 1938 /* 1939 * The DP83820's receive buffers must be 4-byte 1940 * aligned. But this means that the data after 1941 * the Ethernet header is misaligned. To compensate, 1942 * we have artificially shortened the buffer size 1943 * in the descriptor, and we do an overlapping copy 1944 * of the data two bytes further in (in the first 1945 * buffer of the chain only). 1946 */ 1947 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1948 m->m_len); 1949 m->m_data += 2; 1950 } 1951 #endif /* ! __NO_STRICT_ALIGNMENT */ 1952 1953 /* 1954 * If VLANs are enabled, VLAN packets have been unwrapped 1955 * for us. Associate the tag with the packet. 1956 */ 1957 if (sc->sc_ethercom.ec_nvlans != 0 && 1958 (extsts & EXTSTS_VPKT) != 0) { 1959 struct m_tag *vtag; 1960 1961 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 1962 M_NOWAIT); 1963 if (vtag == NULL) { 1964 ifp->if_ierrors++; 1965 printf("%s: unable to allocate VLAN tag\n", 1966 sc->sc_dev.dv_xname); 1967 m_freem(m); 1968 continue; 1969 } 1970 1971 *(u_int *)(vtag + 1) = ntohs(extsts & EXTSTS_VTCI); 1972 } 1973 1974 /* 1975 * Set the incoming checksum information for the 1976 * packet. 1977 */ 1978 if ((extsts & EXTSTS_IPPKT) != 0) { 1979 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1980 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1981 if (extsts & EXTSTS_Rx_IPERR) 1982 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1983 if (extsts & EXTSTS_TCPPKT) { 1984 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1985 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1986 if (extsts & EXTSTS_Rx_TCPERR) 1987 m->m_pkthdr.csum_flags |= 1988 M_CSUM_TCP_UDP_BAD; 1989 } else if (extsts & EXTSTS_UDPPKT) { 1990 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1991 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1992 if (extsts & EXTSTS_Rx_UDPERR) 1993 m->m_pkthdr.csum_flags |= 1994 M_CSUM_TCP_UDP_BAD; 1995 } 1996 } 1997 1998 ifp->if_ipackets++; 1999 m->m_flags |= M_HASFCS; 2000 m->m_pkthdr.rcvif = ifp; 2001 m->m_pkthdr.len = frame_len; 2002 2003 #if NBPFILTER > 0 2004 /* 2005 * Pass this up to any BPF listeners, but only 2006 * pass if up the stack if it's for us. 2007 */ 2008 if (ifp->if_bpf) 2009 bpf_mtap(ifp->if_bpf, m); 2010 #endif /* NBPFILTER > 0 */ 2011 2012 /* Pass it on. */ 2013 (*ifp->if_input)(ifp, m); 2014 } 2015 2016 /* Update the receive pointer. */ 2017 sc->sc_rxptr = i; 2018 } 2019 #else /* ! DP83820 */ 2020 /* 2021 * sip_rxintr: 2022 * 2023 * Helper; handle receive interrupts. 2024 */ 2025 static void 2026 SIP_DECL(rxintr)(struct sip_softc *sc) 2027 { 2028 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2029 struct sip_rxsoft *rxs; 2030 struct mbuf *m; 2031 u_int32_t cmdsts; 2032 int i, len; 2033 2034 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 2035 rxs = &sc->sc_rxsoft[i]; 2036 2037 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2038 2039 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 2040 2041 /* 2042 * NOTE: OWN is set if owned by _consumer_. We're the 2043 * consumer of the receive ring, so if the bit is clear, 2044 * we have processed all of the packets. 2045 */ 2046 if ((cmdsts & CMDSTS_OWN) == 0) { 2047 /* 2048 * We have processed all of the receive buffers. 2049 */ 2050 break; 2051 } 2052 2053 /* 2054 * If any collisions were seen on the wire, count one. 2055 */ 2056 if (cmdsts & CMDSTS_Rx_COL) 2057 ifp->if_collisions++; 2058 2059 /* 2060 * If an error occurred, update stats, clear the status 2061 * word, and leave the packet buffer in place. It will 2062 * simply be reused the next time the ring comes around. 2063 */ 2064 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2065 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2066 ifp->if_ierrors++; 2067 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2068 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2069 /* Receive overrun handled elsewhere. */ 2070 printf("%s: receive descriptor error\n", 2071 sc->sc_dev.dv_xname); 2072 } 2073 #define PRINTERR(bit, str) \ 2074 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2075 (cmdsts & (bit)) != 0) \ 2076 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 2077 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2078 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2079 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2080 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2081 #undef PRINTERR 2082 SIP_INIT_RXDESC(sc, i); 2083 continue; 2084 } 2085 2086 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2087 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2088 2089 /* 2090 * No errors; receive the packet. Note, the SiS 900 2091 * includes the CRC with every packet. 2092 */ 2093 len = CMDSTS_SIZE(cmdsts); 2094 2095 #ifdef __NO_STRICT_ALIGNMENT 2096 /* 2097 * If the packet is small enough to fit in a 2098 * single header mbuf, allocate one and copy 2099 * the data into it. This greatly reduces 2100 * memory consumption when we receive lots 2101 * of small packets. 2102 * 2103 * Otherwise, we add a new buffer to the receive 2104 * chain. If this fails, we drop the packet and 2105 * recycle the old buffer. 2106 */ 2107 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 2108 MGETHDR(m, M_DONTWAIT, MT_DATA); 2109 if (m == NULL) 2110 goto dropit; 2111 memcpy(mtod(m, caddr_t), 2112 mtod(rxs->rxs_mbuf, caddr_t), len); 2113 SIP_INIT_RXDESC(sc, i); 2114 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2115 rxs->rxs_dmamap->dm_mapsize, 2116 BUS_DMASYNC_PREREAD); 2117 } else { 2118 m = rxs->rxs_mbuf; 2119 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 2120 dropit: 2121 ifp->if_ierrors++; 2122 SIP_INIT_RXDESC(sc, i); 2123 bus_dmamap_sync(sc->sc_dmat, 2124 rxs->rxs_dmamap, 0, 2125 rxs->rxs_dmamap->dm_mapsize, 2126 BUS_DMASYNC_PREREAD); 2127 continue; 2128 } 2129 } 2130 #else 2131 /* 2132 * The SiS 900's receive buffers must be 4-byte aligned. 2133 * But this means that the data after the Ethernet header 2134 * is misaligned. We must allocate a new buffer and 2135 * copy the data, shifted forward 2 bytes. 2136 */ 2137 MGETHDR(m, M_DONTWAIT, MT_DATA); 2138 if (m == NULL) { 2139 dropit: 2140 ifp->if_ierrors++; 2141 SIP_INIT_RXDESC(sc, i); 2142 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2143 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2144 continue; 2145 } 2146 if (len > (MHLEN - 2)) { 2147 MCLGET(m, M_DONTWAIT); 2148 if ((m->m_flags & M_EXT) == 0) { 2149 m_freem(m); 2150 goto dropit; 2151 } 2152 } 2153 m->m_data += 2; 2154 2155 /* 2156 * Note that we use clusters for incoming frames, so the 2157 * buffer is virtually contiguous. 2158 */ 2159 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 2160 2161 /* Allow the receive descriptor to continue using its mbuf. */ 2162 SIP_INIT_RXDESC(sc, i); 2163 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2164 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2165 #endif /* __NO_STRICT_ALIGNMENT */ 2166 2167 ifp->if_ipackets++; 2168 m->m_flags |= M_HASFCS; 2169 m->m_pkthdr.rcvif = ifp; 2170 m->m_pkthdr.len = m->m_len = len; 2171 2172 #if NBPFILTER > 0 2173 /* 2174 * Pass this up to any BPF listeners, but only 2175 * pass if up the stack if it's for us. 2176 */ 2177 if (ifp->if_bpf) 2178 bpf_mtap(ifp->if_bpf, m); 2179 #endif /* NBPFILTER > 0 */ 2180 2181 /* Pass it on. */ 2182 (*ifp->if_input)(ifp, m); 2183 } 2184 2185 /* Update the receive pointer. */ 2186 sc->sc_rxptr = i; 2187 } 2188 #endif /* DP83820 */ 2189 2190 /* 2191 * sip_tick: 2192 * 2193 * One second timer, used to tick the MII. 2194 */ 2195 static void 2196 SIP_DECL(tick)(void *arg) 2197 { 2198 struct sip_softc *sc = arg; 2199 int s; 2200 2201 s = splnet(); 2202 #ifdef DP83820 2203 #ifdef SIP_EVENT_COUNTERS 2204 /* Read PAUSE related counts from MIB registers. */ 2205 sc->sc_ev_rxpause.ev_count += 2206 bus_space_read_4(sc->sc_st, sc->sc_sh, 2207 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2208 sc->sc_ev_txpause.ev_count += 2209 bus_space_read_4(sc->sc_st, sc->sc_sh, 2210 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2211 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2212 #endif /* SIP_EVENT_COUNTERS */ 2213 #endif /* DP83820 */ 2214 mii_tick(&sc->sc_mii); 2215 splx(s); 2216 2217 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2218 } 2219 2220 /* 2221 * sip_reset: 2222 * 2223 * Perform a soft reset on the SiS 900. 2224 */ 2225 static void 2226 SIP_DECL(reset)(struct sip_softc *sc) 2227 { 2228 bus_space_tag_t st = sc->sc_st; 2229 bus_space_handle_t sh = sc->sc_sh; 2230 int i; 2231 2232 bus_space_write_4(st, sh, SIP_IER, 0); 2233 bus_space_write_4(st, sh, SIP_IMR, 0); 2234 bus_space_write_4(st, sh, SIP_RFCR, 0); 2235 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2236 2237 for (i = 0; i < SIP_TIMEOUT; i++) { 2238 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2239 break; 2240 delay(2); 2241 } 2242 2243 if (i == SIP_TIMEOUT) 2244 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2245 2246 delay(1000); 2247 2248 #ifdef DP83820 2249 /* 2250 * Set the general purpose I/O bits. Do it here in case we 2251 * need to have GPIO set up to talk to the media interface. 2252 */ 2253 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2254 delay(1000); 2255 #endif /* DP83820 */ 2256 } 2257 2258 /* 2259 * sip_init: [ ifnet interface function ] 2260 * 2261 * Initialize the interface. Must be called at splnet(). 2262 */ 2263 static int 2264 SIP_DECL(init)(struct ifnet *ifp) 2265 { 2266 struct sip_softc *sc = ifp->if_softc; 2267 bus_space_tag_t st = sc->sc_st; 2268 bus_space_handle_t sh = sc->sc_sh; 2269 struct sip_txsoft *txs; 2270 struct sip_rxsoft *rxs; 2271 struct sip_desc *sipd; 2272 #if defined(DP83820) 2273 u_int32_t reg; 2274 #endif 2275 int i, error = 0; 2276 2277 /* 2278 * Cancel any pending I/O. 2279 */ 2280 SIP_DECL(stop)(ifp, 0); 2281 2282 /* 2283 * Reset the chip to a known state. 2284 */ 2285 SIP_DECL(reset)(sc); 2286 2287 #if !defined(DP83820) 2288 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2289 /* 2290 * DP83815 manual, page 78: 2291 * 4.4 Recommended Registers Configuration 2292 * For optimum performance of the DP83815, version noted 2293 * as DP83815CVNG (SRR = 203h), the listed register 2294 * modifications must be followed in sequence... 2295 * 2296 * It's not clear if this should be 302h or 203h because that 2297 * chip name is listed as SRR 302h in the description of the 2298 * SRR register. However, my revision 302h DP83815 on the 2299 * Netgear FA311 purchased in 02/2001 needs these settings 2300 * to avoid tons of errors in AcceptPerfectMatch (non- 2301 * IFF_PROMISC) mode. I do not know if other revisions need 2302 * this set or not. [briggs -- 09 March 2001] 2303 * 2304 * Note that only the low-order 12 bits of 0xe4 are documented 2305 * and that this sets reserved bits in that register. 2306 */ 2307 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2308 2309 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2310 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2311 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2312 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2313 2314 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2315 } 2316 #endif /* ! DP83820 */ 2317 2318 /* 2319 * Initialize the transmit descriptor ring. 2320 */ 2321 for (i = 0; i < SIP_NTXDESC; i++) { 2322 sipd = &sc->sc_txdescs[i]; 2323 memset(sipd, 0, sizeof(struct sip_desc)); 2324 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2325 } 2326 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2327 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2328 sc->sc_txfree = SIP_NTXDESC; 2329 sc->sc_txnext = 0; 2330 sc->sc_txwin = 0; 2331 2332 /* 2333 * Initialize the transmit job descriptors. 2334 */ 2335 SIMPLEQ_INIT(&sc->sc_txfreeq); 2336 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2337 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2338 txs = &sc->sc_txsoft[i]; 2339 txs->txs_mbuf = NULL; 2340 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2341 } 2342 2343 /* 2344 * Initialize the receive descriptor and receive job 2345 * descriptor rings. 2346 */ 2347 for (i = 0; i < SIP_NRXDESC; i++) { 2348 rxs = &sc->sc_rxsoft[i]; 2349 if (rxs->rxs_mbuf == NULL) { 2350 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2351 printf("%s: unable to allocate or map rx " 2352 "buffer %d, error = %d\n", 2353 sc->sc_dev.dv_xname, i, error); 2354 /* 2355 * XXX Should attempt to run with fewer receive 2356 * XXX buffers instead of just failing. 2357 */ 2358 SIP_DECL(rxdrain)(sc); 2359 goto out; 2360 } 2361 } else 2362 SIP_INIT_RXDESC(sc, i); 2363 } 2364 sc->sc_rxptr = 0; 2365 #ifdef DP83820 2366 sc->sc_rxdiscard = 0; 2367 SIP_RXCHAIN_RESET(sc); 2368 #endif /* DP83820 */ 2369 2370 /* 2371 * Set the configuration register; it's already initialized 2372 * in sip_attach(). 2373 */ 2374 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2375 2376 /* 2377 * Initialize the prototype TXCFG register. 2378 */ 2379 #if defined(DP83820) 2380 sc->sc_txcfg = TXCFG_MXDMA_512; 2381 sc->sc_rxcfg = RXCFG_MXDMA_512; 2382 #else 2383 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2384 SIP_SIS900_REV(sc, SIS_REV_960) || 2385 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2386 (sc->sc_cfg & CFG_EDBMASTEN)) { 2387 sc->sc_txcfg = TXCFG_MXDMA_64; 2388 sc->sc_rxcfg = RXCFG_MXDMA_64; 2389 } else { 2390 sc->sc_txcfg = TXCFG_MXDMA_512; 2391 sc->sc_rxcfg = RXCFG_MXDMA_512; 2392 } 2393 #endif /* DP83820 */ 2394 2395 sc->sc_txcfg |= TXCFG_ATP | 2396 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2397 sc->sc_tx_drain_thresh; 2398 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2399 2400 /* 2401 * Initialize the receive drain threshold if we have never 2402 * done so. 2403 */ 2404 if (sc->sc_rx_drain_thresh == 0) { 2405 /* 2406 * XXX This value should be tuned. This is set to the 2407 * maximum of 248 bytes, and we may be able to improve 2408 * performance by decreasing it (although we should never 2409 * set this value lower than 2; 14 bytes are required to 2410 * filter the packet). 2411 */ 2412 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2413 } 2414 2415 /* 2416 * Initialize the prototype RXCFG register. 2417 */ 2418 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2419 #ifdef DP83820 2420 /* 2421 * Accept long packets (including FCS) so we can handle 2422 * 802.1q-tagged frames and jumbo frames properly. 2423 */ 2424 if (ifp->if_mtu > ETHERMTU || 2425 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2426 sc->sc_rxcfg |= RXCFG_ALP; 2427 2428 /* 2429 * Checksum offloading is disabled if the user selects an MTU 2430 * larger than 8109. (FreeBSD says 8152, but there is emperical 2431 * evidence that >8109 does not work on some boards, such as the 2432 * Planex GN-1000TE). 2433 */ 2434 if (ifp->if_mtu > 8109 && 2435 (ifp->if_capenable & 2436 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4))) { 2437 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2438 "disabled.\n", sc->sc_dev.dv_xname); 2439 ifp->if_capenable &= ~(IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4| 2440 IFCAP_CSUM_UDPv4); 2441 ifp->if_csum_flags_tx = 0; 2442 ifp->if_csum_flags_rx = 0; 2443 } 2444 #else 2445 /* 2446 * Accept packets >1518 bytes (including FCS) so we can handle 2447 * 802.1q-tagged frames properly. 2448 */ 2449 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2450 sc->sc_rxcfg |= RXCFG_ALP; 2451 #endif 2452 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2453 2454 #ifdef DP83820 2455 /* 2456 * Initialize the VLAN/IP receive control register. 2457 * We enable checksum computation on all incoming 2458 * packets, and do not reject packets w/ bad checksums. 2459 */ 2460 reg = 0; 2461 if (ifp->if_capenable & 2462 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2463 reg |= VRCR_IPEN; 2464 if (sc->sc_ethercom.ec_nvlans != 0) 2465 reg |= VRCR_VTDEN|VRCR_VTREN; 2466 bus_space_write_4(st, sh, SIP_VRCR, reg); 2467 2468 /* 2469 * Initialize the VLAN/IP transmit control register. 2470 * We enable outgoing checksum computation on a 2471 * per-packet basis. 2472 */ 2473 reg = 0; 2474 if (ifp->if_capenable & 2475 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2476 reg |= VTCR_PPCHK; 2477 if (sc->sc_ethercom.ec_nvlans != 0) 2478 reg |= VTCR_VPPTI; 2479 bus_space_write_4(st, sh, SIP_VTCR, reg); 2480 2481 /* 2482 * If we're using VLANs, initialize the VLAN data register. 2483 * To understand why we bswap the VLAN Ethertype, see section 2484 * 4.2.36 of the DP83820 manual. 2485 */ 2486 if (sc->sc_ethercom.ec_nvlans != 0) 2487 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2488 #endif /* DP83820 */ 2489 2490 /* 2491 * Give the transmit and receive rings to the chip. 2492 */ 2493 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2494 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2495 2496 /* 2497 * Initialize the interrupt mask. 2498 */ 2499 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2500 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2501 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2502 2503 /* Set up the receive filter. */ 2504 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2505 2506 #ifdef DP83820 2507 /* 2508 * Tune sc_rx_flow_thresh. 2509 * XXX "More than 8KB" is too short for jumbo frames. 2510 * XXX TODO: Threshold value should be user-settable. 2511 */ 2512 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2513 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2514 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2515 #endif 2516 2517 /* 2518 * Set the current media. Do this after initializing the prototype 2519 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2520 * control. 2521 */ 2522 mii_mediachg(&sc->sc_mii); 2523 2524 #ifdef DP83820 2525 /* 2526 * Set the interrupt hold-off timer to 100us. 2527 */ 2528 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2529 #endif 2530 2531 /* 2532 * Enable interrupts. 2533 */ 2534 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2535 2536 /* 2537 * Start the transmit and receive processes. 2538 */ 2539 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2540 2541 /* 2542 * Start the one second MII clock. 2543 */ 2544 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2545 2546 /* 2547 * ...all done! 2548 */ 2549 ifp->if_flags |= IFF_RUNNING; 2550 ifp->if_flags &= ~IFF_OACTIVE; 2551 2552 out: 2553 if (error) 2554 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2555 return (error); 2556 } 2557 2558 /* 2559 * sip_drain: 2560 * 2561 * Drain the receive queue. 2562 */ 2563 static void 2564 SIP_DECL(rxdrain)(struct sip_softc *sc) 2565 { 2566 struct sip_rxsoft *rxs; 2567 int i; 2568 2569 for (i = 0; i < SIP_NRXDESC; i++) { 2570 rxs = &sc->sc_rxsoft[i]; 2571 if (rxs->rxs_mbuf != NULL) { 2572 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2573 m_freem(rxs->rxs_mbuf); 2574 rxs->rxs_mbuf = NULL; 2575 } 2576 } 2577 } 2578 2579 /* 2580 * sip_stop: [ ifnet interface function ] 2581 * 2582 * Stop transmission on the interface. 2583 */ 2584 static void 2585 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2586 { 2587 struct sip_softc *sc = ifp->if_softc; 2588 bus_space_tag_t st = sc->sc_st; 2589 bus_space_handle_t sh = sc->sc_sh; 2590 struct sip_txsoft *txs; 2591 u_int32_t cmdsts = 0; /* DEBUG */ 2592 2593 /* 2594 * Stop the one second clock. 2595 */ 2596 callout_stop(&sc->sc_tick_ch); 2597 2598 /* Down the MII. */ 2599 mii_down(&sc->sc_mii); 2600 2601 /* 2602 * Disable interrupts. 2603 */ 2604 bus_space_write_4(st, sh, SIP_IER, 0); 2605 2606 /* 2607 * Stop receiver and transmitter. 2608 */ 2609 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2610 2611 /* 2612 * Release any queued transmit buffers. 2613 */ 2614 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2615 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2616 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2617 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2618 CMDSTS_INTR) == 0) 2619 printf("%s: sip_stop: last descriptor does not " 2620 "have INTR bit set\n", sc->sc_dev.dv_xname); 2621 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2622 #ifdef DIAGNOSTIC 2623 if (txs->txs_mbuf == NULL) { 2624 printf("%s: dirty txsoft with no mbuf chain\n", 2625 sc->sc_dev.dv_xname); 2626 panic("sip_stop"); 2627 } 2628 #endif 2629 cmdsts |= /* DEBUG */ 2630 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2631 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2632 m_freem(txs->txs_mbuf); 2633 txs->txs_mbuf = NULL; 2634 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2635 } 2636 2637 if (disable) 2638 SIP_DECL(rxdrain)(sc); 2639 2640 /* 2641 * Mark the interface down and cancel the watchdog timer. 2642 */ 2643 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2644 ifp->if_timer = 0; 2645 2646 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2647 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2648 printf("%s: sip_stop: no INTR bits set in dirty tx " 2649 "descriptors\n", sc->sc_dev.dv_xname); 2650 } 2651 2652 /* 2653 * sip_read_eeprom: 2654 * 2655 * Read data from the serial EEPROM. 2656 */ 2657 static void 2658 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2659 u_int16_t *data) 2660 { 2661 bus_space_tag_t st = sc->sc_st; 2662 bus_space_handle_t sh = sc->sc_sh; 2663 u_int16_t reg; 2664 int i, x; 2665 2666 for (i = 0; i < wordcnt; i++) { 2667 /* Send CHIP SELECT. */ 2668 reg = EROMAR_EECS; 2669 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2670 2671 /* Shift in the READ opcode. */ 2672 for (x = 3; x > 0; x--) { 2673 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2674 reg |= EROMAR_EEDI; 2675 else 2676 reg &= ~EROMAR_EEDI; 2677 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2678 bus_space_write_4(st, sh, SIP_EROMAR, 2679 reg | EROMAR_EESK); 2680 delay(4); 2681 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2682 delay(4); 2683 } 2684 2685 /* Shift in address. */ 2686 for (x = 6; x > 0; x--) { 2687 if ((word + i) & (1 << (x - 1))) 2688 reg |= EROMAR_EEDI; 2689 else 2690 reg &= ~EROMAR_EEDI; 2691 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2692 bus_space_write_4(st, sh, SIP_EROMAR, 2693 reg | EROMAR_EESK); 2694 delay(4); 2695 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2696 delay(4); 2697 } 2698 2699 /* Shift out data. */ 2700 reg = EROMAR_EECS; 2701 data[i] = 0; 2702 for (x = 16; x > 0; x--) { 2703 bus_space_write_4(st, sh, SIP_EROMAR, 2704 reg | EROMAR_EESK); 2705 delay(4); 2706 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2707 data[i] |= (1 << (x - 1)); 2708 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2709 delay(4); 2710 } 2711 2712 /* Clear CHIP SELECT. */ 2713 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2714 delay(4); 2715 } 2716 } 2717 2718 /* 2719 * sip_add_rxbuf: 2720 * 2721 * Add a receive buffer to the indicated descriptor. 2722 */ 2723 static int 2724 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2725 { 2726 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2727 struct mbuf *m; 2728 int error; 2729 2730 MGETHDR(m, M_DONTWAIT, MT_DATA); 2731 if (m == NULL) 2732 return (ENOBUFS); 2733 2734 MCLGET(m, M_DONTWAIT); 2735 if ((m->m_flags & M_EXT) == 0) { 2736 m_freem(m); 2737 return (ENOBUFS); 2738 } 2739 2740 #if defined(DP83820) 2741 m->m_len = SIP_RXBUF_LEN; 2742 #endif /* DP83820 */ 2743 2744 if (rxs->rxs_mbuf != NULL) 2745 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2746 2747 rxs->rxs_mbuf = m; 2748 2749 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2750 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2751 BUS_DMA_READ|BUS_DMA_NOWAIT); 2752 if (error) { 2753 printf("%s: can't load rx DMA map %d, error = %d\n", 2754 sc->sc_dev.dv_xname, idx, error); 2755 panic("sip_add_rxbuf"); /* XXX */ 2756 } 2757 2758 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2759 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2760 2761 SIP_INIT_RXDESC(sc, idx); 2762 2763 return (0); 2764 } 2765 2766 #if !defined(DP83820) 2767 /* 2768 * sip_sis900_set_filter: 2769 * 2770 * Set up the receive filter. 2771 */ 2772 static void 2773 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2774 { 2775 bus_space_tag_t st = sc->sc_st; 2776 bus_space_handle_t sh = sc->sc_sh; 2777 struct ethercom *ec = &sc->sc_ethercom; 2778 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2779 struct ether_multi *enm; 2780 u_int8_t *cp; 2781 struct ether_multistep step; 2782 u_int32_t crc, mchash[16]; 2783 2784 /* 2785 * Initialize the prototype RFCR. 2786 */ 2787 sc->sc_rfcr = RFCR_RFEN; 2788 if (ifp->if_flags & IFF_BROADCAST) 2789 sc->sc_rfcr |= RFCR_AAB; 2790 if (ifp->if_flags & IFF_PROMISC) { 2791 sc->sc_rfcr |= RFCR_AAP; 2792 goto allmulti; 2793 } 2794 2795 /* 2796 * Set up the multicast address filter by passing all multicast 2797 * addresses through a CRC generator, and then using the high-order 2798 * 6 bits as an index into the 128 bit multicast hash table (only 2799 * the lower 16 bits of each 32 bit multicast hash register are 2800 * valid). The high order bits select the register, while the 2801 * rest of the bits select the bit within the register. 2802 */ 2803 2804 memset(mchash, 0, sizeof(mchash)); 2805 2806 /* 2807 * SiS900 (at least SiS963) requires us to register the address of 2808 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 2809 */ 2810 crc = 0x0ed423f9; 2811 2812 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2813 SIP_SIS900_REV(sc, SIS_REV_960) || 2814 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2815 /* Just want the 8 most significant bits. */ 2816 crc >>= 24; 2817 } else { 2818 /* Just want the 7 most significant bits. */ 2819 crc >>= 25; 2820 } 2821 2822 /* Set the corresponding bit in the hash table. */ 2823 mchash[crc >> 4] |= 1 << (crc & 0xf); 2824 2825 ETHER_FIRST_MULTI(step, ec, enm); 2826 while (enm != NULL) { 2827 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2828 /* 2829 * We must listen to a range of multicast addresses. 2830 * For now, just accept all multicasts, rather than 2831 * trying to set only those filter bits needed to match 2832 * the range. (At this time, the only use of address 2833 * ranges is for IP multicast routing, for which the 2834 * range is big enough to require all bits set.) 2835 */ 2836 goto allmulti; 2837 } 2838 2839 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2840 2841 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2842 SIP_SIS900_REV(sc, SIS_REV_960) || 2843 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2844 /* Just want the 8 most significant bits. */ 2845 crc >>= 24; 2846 } else { 2847 /* Just want the 7 most significant bits. */ 2848 crc >>= 25; 2849 } 2850 2851 /* Set the corresponding bit in the hash table. */ 2852 mchash[crc >> 4] |= 1 << (crc & 0xf); 2853 2854 ETHER_NEXT_MULTI(step, enm); 2855 } 2856 2857 ifp->if_flags &= ~IFF_ALLMULTI; 2858 goto setit; 2859 2860 allmulti: 2861 ifp->if_flags |= IFF_ALLMULTI; 2862 sc->sc_rfcr |= RFCR_AAM; 2863 2864 setit: 2865 #define FILTER_EMIT(addr, data) \ 2866 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2867 delay(1); \ 2868 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2869 delay(1) 2870 2871 /* 2872 * Disable receive filter, and program the node address. 2873 */ 2874 cp = LLADDR(ifp->if_sadl); 2875 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2876 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2877 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2878 2879 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2880 /* 2881 * Program the multicast hash table. 2882 */ 2883 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2884 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2885 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2886 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2887 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2888 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2889 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2890 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2891 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2892 SIP_SIS900_REV(sc, SIS_REV_960) || 2893 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2894 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2895 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2896 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2897 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2898 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2899 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2900 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2901 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2902 } 2903 } 2904 #undef FILTER_EMIT 2905 2906 /* 2907 * Re-enable the receiver filter. 2908 */ 2909 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2910 } 2911 #endif /* ! DP83820 */ 2912 2913 /* 2914 * sip_dp83815_set_filter: 2915 * 2916 * Set up the receive filter. 2917 */ 2918 static void 2919 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2920 { 2921 bus_space_tag_t st = sc->sc_st; 2922 bus_space_handle_t sh = sc->sc_sh; 2923 struct ethercom *ec = &sc->sc_ethercom; 2924 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2925 struct ether_multi *enm; 2926 u_int8_t *cp; 2927 struct ether_multistep step; 2928 u_int32_t crc, hash, slot, bit; 2929 #ifdef DP83820 2930 #define MCHASH_NWORDS 128 2931 #else 2932 #define MCHASH_NWORDS 32 2933 #endif /* DP83820 */ 2934 u_int16_t mchash[MCHASH_NWORDS]; 2935 int i; 2936 2937 /* 2938 * Initialize the prototype RFCR. 2939 * Enable the receive filter, and accept on 2940 * Perfect (destination address) Match 2941 * If IFF_BROADCAST, also accept all broadcast packets. 2942 * If IFF_PROMISC, accept all unicast packets (and later, set 2943 * IFF_ALLMULTI and accept all multicast, too). 2944 */ 2945 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2946 if (ifp->if_flags & IFF_BROADCAST) 2947 sc->sc_rfcr |= RFCR_AAB; 2948 if (ifp->if_flags & IFF_PROMISC) { 2949 sc->sc_rfcr |= RFCR_AAP; 2950 goto allmulti; 2951 } 2952 2953 #ifdef DP83820 2954 /* 2955 * Set up the DP83820 multicast address filter by passing all multicast 2956 * addresses through a CRC generator, and then using the high-order 2957 * 11 bits as an index into the 2048 bit multicast hash table. The 2958 * high-order 7 bits select the slot, while the low-order 4 bits 2959 * select the bit within the slot. Note that only the low 16-bits 2960 * of each filter word are used, and there are 128 filter words. 2961 */ 2962 #else 2963 /* 2964 * Set up the DP83815 multicast address filter by passing all multicast 2965 * addresses through a CRC generator, and then using the high-order 2966 * 9 bits as an index into the 512 bit multicast hash table. The 2967 * high-order 5 bits select the slot, while the low-order 4 bits 2968 * select the bit within the slot. Note that only the low 16-bits 2969 * of each filter word are used, and there are 32 filter words. 2970 */ 2971 #endif /* DP83820 */ 2972 2973 memset(mchash, 0, sizeof(mchash)); 2974 2975 ifp->if_flags &= ~IFF_ALLMULTI; 2976 ETHER_FIRST_MULTI(step, ec, enm); 2977 if (enm == NULL) 2978 goto setit; 2979 while (enm != NULL) { 2980 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2981 /* 2982 * We must listen to a range of multicast addresses. 2983 * For now, just accept all multicasts, rather than 2984 * trying to set only those filter bits needed to match 2985 * the range. (At this time, the only use of address 2986 * ranges is for IP multicast routing, for which the 2987 * range is big enough to require all bits set.) 2988 */ 2989 goto allmulti; 2990 } 2991 2992 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2993 2994 #ifdef DP83820 2995 /* Just want the 11 most significant bits. */ 2996 hash = crc >> 21; 2997 #else 2998 /* Just want the 9 most significant bits. */ 2999 hash = crc >> 23; 3000 #endif /* DP83820 */ 3001 3002 slot = hash >> 4; 3003 bit = hash & 0xf; 3004 3005 /* Set the corresponding bit in the hash table. */ 3006 mchash[slot] |= 1 << bit; 3007 3008 ETHER_NEXT_MULTI(step, enm); 3009 } 3010 sc->sc_rfcr |= RFCR_MHEN; 3011 goto setit; 3012 3013 allmulti: 3014 ifp->if_flags |= IFF_ALLMULTI; 3015 sc->sc_rfcr |= RFCR_AAM; 3016 3017 setit: 3018 #define FILTER_EMIT(addr, data) \ 3019 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3020 delay(1); \ 3021 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3022 delay(1) 3023 3024 /* 3025 * Disable receive filter, and program the node address. 3026 */ 3027 cp = LLADDR(ifp->if_sadl); 3028 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3029 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3030 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3031 3032 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3033 /* 3034 * Program the multicast hash table. 3035 */ 3036 for (i = 0; i < MCHASH_NWORDS; i++) { 3037 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 3038 mchash[i]); 3039 } 3040 } 3041 #undef FILTER_EMIT 3042 #undef MCHASH_NWORDS 3043 3044 /* 3045 * Re-enable the receiver filter. 3046 */ 3047 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3048 } 3049 3050 #if defined(DP83820) 3051 /* 3052 * sip_dp83820_mii_readreg: [mii interface function] 3053 * 3054 * Read a PHY register on the MII of the DP83820. 3055 */ 3056 static int 3057 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 3058 { 3059 struct sip_softc *sc = (void *) self; 3060 3061 if (sc->sc_cfg & CFG_TBI_EN) { 3062 bus_addr_t tbireg; 3063 int rv; 3064 3065 if (phy != 0) 3066 return (0); 3067 3068 switch (reg) { 3069 case MII_BMCR: tbireg = SIP_TBICR; break; 3070 case MII_BMSR: tbireg = SIP_TBISR; break; 3071 case MII_ANAR: tbireg = SIP_TANAR; break; 3072 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3073 case MII_ANER: tbireg = SIP_TANER; break; 3074 case MII_EXTSR: 3075 /* 3076 * Don't even bother reading the TESR register. 3077 * The manual documents that the device has 3078 * 1000baseX full/half capability, but the 3079 * register itself seems read back 0 on some 3080 * boards. Just hard-code the result. 3081 */ 3082 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3083 3084 default: 3085 return (0); 3086 } 3087 3088 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3089 if (tbireg == SIP_TBISR) { 3090 /* LINK and ACOMP are switched! */ 3091 int val = rv; 3092 3093 rv = 0; 3094 if (val & TBISR_MR_LINK_STATUS) 3095 rv |= BMSR_LINK; 3096 if (val & TBISR_MR_AN_COMPLETE) 3097 rv |= BMSR_ACOMP; 3098 3099 /* 3100 * The manual claims this register reads back 0 3101 * on hard and soft reset. But we want to let 3102 * the gentbi driver know that we support auto- 3103 * negotiation, so hard-code this bit in the 3104 * result. 3105 */ 3106 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3107 } 3108 3109 return (rv); 3110 } 3111 3112 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3113 phy, reg)); 3114 } 3115 3116 /* 3117 * sip_dp83820_mii_writereg: [mii interface function] 3118 * 3119 * Write a PHY register on the MII of the DP83820. 3120 */ 3121 static void 3122 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 3123 { 3124 struct sip_softc *sc = (void *) self; 3125 3126 if (sc->sc_cfg & CFG_TBI_EN) { 3127 bus_addr_t tbireg; 3128 3129 if (phy != 0) 3130 return; 3131 3132 switch (reg) { 3133 case MII_BMCR: tbireg = SIP_TBICR; break; 3134 case MII_ANAR: tbireg = SIP_TANAR; break; 3135 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3136 default: 3137 return; 3138 } 3139 3140 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3141 return; 3142 } 3143 3144 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3145 phy, reg, val); 3146 } 3147 3148 /* 3149 * sip_dp83820_mii_statchg: [mii interface function] 3150 * 3151 * Callback from MII layer when media changes. 3152 */ 3153 static void 3154 SIP_DECL(dp83820_mii_statchg)(struct device *self) 3155 { 3156 struct sip_softc *sc = (struct sip_softc *) self; 3157 struct mii_data *mii = &sc->sc_mii; 3158 u_int32_t cfg, pcr; 3159 3160 /* 3161 * Get flow control negotiation result. 3162 */ 3163 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3164 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3165 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3166 mii->mii_media_active &= ~IFM_ETH_FMASK; 3167 } 3168 3169 /* 3170 * Update TXCFG for full-duplex operation. 3171 */ 3172 if ((mii->mii_media_active & IFM_FDX) != 0) 3173 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3174 else 3175 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3176 3177 /* 3178 * Update RXCFG for full-duplex or loopback. 3179 */ 3180 if ((mii->mii_media_active & IFM_FDX) != 0 || 3181 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3182 sc->sc_rxcfg |= RXCFG_ATX; 3183 else 3184 sc->sc_rxcfg &= ~RXCFG_ATX; 3185 3186 /* 3187 * Update CFG for MII/GMII. 3188 */ 3189 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3190 cfg = sc->sc_cfg | CFG_MODE_1000; 3191 else 3192 cfg = sc->sc_cfg; 3193 3194 /* 3195 * 802.3x flow control. 3196 */ 3197 pcr = 0; 3198 if (sc->sc_flowflags & IFM_FLOW) { 3199 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3200 pcr |= sc->sc_rx_flow_thresh; 3201 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3202 pcr |= PCR_PSEN | PCR_PS_MCAST; 3203 } 3204 3205 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3206 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3207 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3208 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3209 } 3210 #endif /* ! DP83820 */ 3211 3212 /* 3213 * sip_mii_bitbang_read: [mii bit-bang interface function] 3214 * 3215 * Read the MII serial port for the MII bit-bang module. 3216 */ 3217 static u_int32_t 3218 SIP_DECL(mii_bitbang_read)(struct device *self) 3219 { 3220 struct sip_softc *sc = (void *) self; 3221 3222 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3223 } 3224 3225 /* 3226 * sip_mii_bitbang_write: [mii big-bang interface function] 3227 * 3228 * Write the MII serial port for the MII bit-bang module. 3229 */ 3230 static void 3231 SIP_DECL(mii_bitbang_write)(struct device *self, u_int32_t val) 3232 { 3233 struct sip_softc *sc = (void *) self; 3234 3235 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3236 } 3237 3238 #ifndef DP83820 3239 /* 3240 * sip_sis900_mii_readreg: [mii interface function] 3241 * 3242 * Read a PHY register on the MII. 3243 */ 3244 static int 3245 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 3246 { 3247 struct sip_softc *sc = (struct sip_softc *) self; 3248 u_int32_t enphy; 3249 3250 /* 3251 * The PHY of recent SiS chipsets is accessed through bitbang 3252 * operations. 3253 */ 3254 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3255 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3256 phy, reg)); 3257 3258 #ifndef SIS900_MII_RESTRICT 3259 /* 3260 * The SiS 900 has only an internal PHY on the MII. Only allow 3261 * MII address 0. 3262 */ 3263 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3264 return (0); 3265 #endif 3266 3267 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3268 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3269 ENPHY_RWCMD | ENPHY_ACCESS); 3270 do { 3271 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3272 } while (enphy & ENPHY_ACCESS); 3273 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3274 } 3275 3276 /* 3277 * sip_sis900_mii_writereg: [mii interface function] 3278 * 3279 * Write a PHY register on the MII. 3280 */ 3281 static void 3282 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 3283 { 3284 struct sip_softc *sc = (struct sip_softc *) self; 3285 u_int32_t enphy; 3286 3287 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3288 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3289 phy, reg, val); 3290 return; 3291 } 3292 3293 #ifndef SIS900_MII_RESTRICT 3294 /* 3295 * The SiS 900 has only an internal PHY on the MII. Only allow 3296 * MII address 0. 3297 */ 3298 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3299 return; 3300 #endif 3301 3302 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3303 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3304 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3305 do { 3306 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3307 } while (enphy & ENPHY_ACCESS); 3308 } 3309 3310 /* 3311 * sip_sis900_mii_statchg: [mii interface function] 3312 * 3313 * Callback from MII layer when media changes. 3314 */ 3315 static void 3316 SIP_DECL(sis900_mii_statchg)(struct device *self) 3317 { 3318 struct sip_softc *sc = (struct sip_softc *) self; 3319 struct mii_data *mii = &sc->sc_mii; 3320 u_int32_t flowctl; 3321 3322 /* 3323 * Get flow control negotiation result. 3324 */ 3325 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3326 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3327 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3328 mii->mii_media_active &= ~IFM_ETH_FMASK; 3329 } 3330 3331 /* 3332 * Update TXCFG for full-duplex operation. 3333 */ 3334 if ((mii->mii_media_active & IFM_FDX) != 0) 3335 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3336 else 3337 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3338 3339 /* 3340 * Update RXCFG for full-duplex or loopback. 3341 */ 3342 if ((mii->mii_media_active & IFM_FDX) != 0 || 3343 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3344 sc->sc_rxcfg |= RXCFG_ATX; 3345 else 3346 sc->sc_rxcfg &= ~RXCFG_ATX; 3347 3348 /* 3349 * Update IMR for use of 802.3x flow control. 3350 */ 3351 if (sc->sc_flowflags & IFM_FLOW) { 3352 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3353 flowctl = FLOWCTL_FLOWEN; 3354 } else { 3355 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3356 flowctl = 0; 3357 } 3358 3359 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3360 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3361 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3362 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3363 } 3364 3365 /* 3366 * sip_dp83815_mii_readreg: [mii interface function] 3367 * 3368 * Read a PHY register on the MII. 3369 */ 3370 static int 3371 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 3372 { 3373 struct sip_softc *sc = (struct sip_softc *) self; 3374 u_int32_t val; 3375 3376 /* 3377 * The DP83815 only has an internal PHY. Only allow 3378 * MII address 0. 3379 */ 3380 if (phy != 0) 3381 return (0); 3382 3383 /* 3384 * Apparently, after a reset, the DP83815 can take a while 3385 * to respond. During this recovery period, the BMSR returns 3386 * a value of 0. Catch this -- it's not supposed to happen 3387 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3388 * PHY to come back to life. 3389 * 3390 * This works out because the BMSR is the first register 3391 * read during the PHY probe process. 3392 */ 3393 do { 3394 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3395 } while (reg == MII_BMSR && val == 0); 3396 3397 return (val & 0xffff); 3398 } 3399 3400 /* 3401 * sip_dp83815_mii_writereg: [mii interface function] 3402 * 3403 * Write a PHY register to the MII. 3404 */ 3405 static void 3406 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3407 { 3408 struct sip_softc *sc = (struct sip_softc *) self; 3409 3410 /* 3411 * The DP83815 only has an internal PHY. Only allow 3412 * MII address 0. 3413 */ 3414 if (phy != 0) 3415 return; 3416 3417 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3418 } 3419 3420 /* 3421 * sip_dp83815_mii_statchg: [mii interface function] 3422 * 3423 * Callback from MII layer when media changes. 3424 */ 3425 static void 3426 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3427 { 3428 struct sip_softc *sc = (struct sip_softc *) self; 3429 3430 /* 3431 * Update TXCFG for full-duplex operation. 3432 */ 3433 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3434 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3435 else 3436 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3437 3438 /* 3439 * Update RXCFG for full-duplex or loopback. 3440 */ 3441 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3442 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3443 sc->sc_rxcfg |= RXCFG_ATX; 3444 else 3445 sc->sc_rxcfg &= ~RXCFG_ATX; 3446 3447 /* 3448 * XXX 802.3x flow control. 3449 */ 3450 3451 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3452 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3453 3454 /* 3455 * Some DP83815s experience problems when used with short 3456 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3457 * sequence adjusts the DSP's signal attenuation to fix the 3458 * problem. 3459 */ 3460 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3461 uint32_t reg; 3462 3463 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3464 3465 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3466 reg &= 0x0fff; 3467 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3468 delay(100); 3469 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3470 reg &= 0x00ff; 3471 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3472 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3473 0x00e8); 3474 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3475 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3476 reg | 0x20); 3477 } 3478 3479 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3480 } 3481 } 3482 #endif /* DP83820 */ 3483 3484 #if defined(DP83820) 3485 static void 3486 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3487 const struct pci_attach_args *pa, u_int8_t *enaddr) 3488 { 3489 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3490 u_int8_t cksum, *e, match; 3491 int i; 3492 3493 /* 3494 * EEPROM data format for the DP83820 can be found in 3495 * the DP83820 manual, section 4.2.4. 3496 */ 3497 3498 SIP_DECL(read_eeprom)(sc, 0, 3499 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3500 3501 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3502 match = ~(match - 1); 3503 3504 cksum = 0x55; 3505 e = (u_int8_t *) eeprom_data; 3506 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3507 cksum += *e++; 3508 3509 if (cksum != match) 3510 printf("%s: Checksum (%x) mismatch (%x)", 3511 sc->sc_dev.dv_xname, cksum, match); 3512 3513 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3514 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3515 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3516 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3517 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3518 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3519 } 3520 #else /* ! DP83820 */ 3521 static void 3522 SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc) 3523 { 3524 int i; 3525 3526 /* 3527 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3528 * a reason, but I don't know it. 3529 */ 3530 for (i = 0; i < 10; i++) 3531 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3532 } 3533 3534 static void 3535 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3536 const struct pci_attach_args *pa, u_int8_t *enaddr) 3537 { 3538 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3539 3540 switch (sc->sc_rev) { 3541 case SIS_REV_630S: 3542 case SIS_REV_630E: 3543 case SIS_REV_630EA1: 3544 case SIS_REV_630ET: 3545 case SIS_REV_635: 3546 /* 3547 * The MAC address for the on-board Ethernet of 3548 * the SiS 630 chipset is in the NVRAM. Kick 3549 * the chip into re-loading it from NVRAM, and 3550 * read the MAC address out of the filter registers. 3551 */ 3552 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3553 3554 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3555 RFCR_RFADDR_NODE0); 3556 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3557 0xffff; 3558 3559 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3560 RFCR_RFADDR_NODE2); 3561 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3562 0xffff; 3563 3564 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3565 RFCR_RFADDR_NODE4); 3566 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3567 0xffff; 3568 break; 3569 3570 case SIS_REV_960: 3571 { 3572 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3573 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3574 3575 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3576 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3577 3578 int waittime, i; 3579 3580 /* Allow to read EEPROM from LAN. It is shared 3581 * between a 1394 controller and the NIC and each 3582 * time we access it, we need to set SIS_EECMD_REQ. 3583 */ 3584 SIS_SET_EROMAR(sc, EROMAR_REQ); 3585 3586 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3587 /* Force EEPROM to idle state. */ 3588 3589 /* 3590 * XXX-cube This is ugly. I'll look for docs about it. 3591 */ 3592 SIS_SET_EROMAR(sc, EROMAR_EECS); 3593 SIP_DECL(sis900_eeprom_delay)(sc); 3594 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3595 SIS_SET_EROMAR(sc, EROMAR_EESK); 3596 SIP_DECL(sis900_eeprom_delay)(sc); 3597 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3598 SIP_DECL(sis900_eeprom_delay)(sc); 3599 } 3600 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3601 SIP_DECL(sis900_eeprom_delay)(sc); 3602 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3603 3604 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3605 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3606 sizeof(myea) / sizeof(myea[0]), myea); 3607 break; 3608 } 3609 DELAY(1); 3610 } 3611 3612 /* 3613 * Set SIS_EECTL_CLK to high, so a other master 3614 * can operate on the i2c bus. 3615 */ 3616 SIS_SET_EROMAR(sc, EROMAR_EESK); 3617 3618 /* Refuse EEPROM access by LAN */ 3619 SIS_SET_EROMAR(sc, EROMAR_DONE); 3620 } break; 3621 3622 default: 3623 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3624 sizeof(myea) / sizeof(myea[0]), myea); 3625 } 3626 3627 enaddr[0] = myea[0] & 0xff; 3628 enaddr[1] = myea[0] >> 8; 3629 enaddr[2] = myea[1] & 0xff; 3630 enaddr[3] = myea[1] >> 8; 3631 enaddr[4] = myea[2] & 0xff; 3632 enaddr[5] = myea[2] >> 8; 3633 } 3634 3635 /* Table and macro to bit-reverse an octet. */ 3636 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3637 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3638 3639 static void 3640 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3641 const struct pci_attach_args *pa, u_int8_t *enaddr) 3642 { 3643 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3644 u_int8_t cksum, *e, match; 3645 int i; 3646 3647 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3648 sizeof(eeprom_data[0]), eeprom_data); 3649 3650 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3651 match = ~(match - 1); 3652 3653 cksum = 0x55; 3654 e = (u_int8_t *) eeprom_data; 3655 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3656 cksum += *e++; 3657 } 3658 if (cksum != match) { 3659 printf("%s: Checksum (%x) mismatch (%x)", 3660 sc->sc_dev.dv_xname, cksum, match); 3661 } 3662 3663 /* 3664 * Unrolled because it makes slightly more sense this way. 3665 * The DP83815 stores the MAC address in bit 0 of word 6 3666 * through bit 15 of word 8. 3667 */ 3668 ea = &eeprom_data[6]; 3669 enaddr[0] = ((*ea & 0x1) << 7); 3670 ea++; 3671 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3672 enaddr[1] = ((*ea & 0x1FE) >> 1); 3673 enaddr[2] = ((*ea & 0x1) << 7); 3674 ea++; 3675 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3676 enaddr[3] = ((*ea & 0x1FE) >> 1); 3677 enaddr[4] = ((*ea & 0x1) << 7); 3678 ea++; 3679 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3680 enaddr[5] = ((*ea & 0x1FE) >> 1); 3681 3682 /* 3683 * In case that's not weird enough, we also need to reverse 3684 * the bits in each byte. This all actually makes more sense 3685 * if you think about the EEPROM storage as an array of bits 3686 * being shifted into bytes, but that's not how we're looking 3687 * at it here... 3688 */ 3689 for (i = 0; i < 6 ;i++) 3690 enaddr[i] = bbr(enaddr[i]); 3691 } 3692 #endif /* DP83820 */ 3693 3694 /* 3695 * sip_mediastatus: [ifmedia interface function] 3696 * 3697 * Get the current interface media status. 3698 */ 3699 static void 3700 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3701 { 3702 struct sip_softc *sc = ifp->if_softc; 3703 3704 mii_pollstat(&sc->sc_mii); 3705 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3706 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3707 sc->sc_flowflags; 3708 } 3709 3710 /* 3711 * sip_mediachange: [ifmedia interface function] 3712 * 3713 * Set hardware to newly-selected media. 3714 */ 3715 static int 3716 SIP_DECL(mediachange)(struct ifnet *ifp) 3717 { 3718 struct sip_softc *sc = ifp->if_softc; 3719 3720 if (ifp->if_flags & IFF_UP) 3721 mii_mediachg(&sc->sc_mii); 3722 return (0); 3723 } 3724
Indexes created Tue Sep 30 11:09:46 GMT 2025