if_sip.c revision 1.78.2.8
1 /* $NetBSD: if_sip.c,v 1.78.2.8 2005/02/06 09:02:36 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.78.2.8 2005/02/06 09:02:36 skrll Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <machine/bus.h> 116 #include <machine/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/mii_bitbang.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/pci/if_sipreg.h> 128 129 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 130 #define SIP_DECL(x) __CONCAT(gsip_,x) 131 #else /* SiS900 and DP83815 */ 132 #define SIP_DECL(x) __CONCAT(sip_,x) 133 #endif 134 135 #define SIP_STR(x) __STRING(SIP_DECL(x)) 136 137 /* 138 * Transmit descriptor list size. This is arbitrary, but allocate 139 * enough descriptors for 128 pending transmissions, and 8 segments 140 * per packet (64 for DP83820 for jumbo frames). 141 * 142 * This MUST work out to a power of 2. 143 */ 144 #ifdef DP83820 145 #define SIP_NTXSEGS 64 146 #define SIP_NTXSEGS_ALLOC 16 147 #else 148 #define SIP_NTXSEGS 16 149 #define SIP_NTXSEGS_ALLOC 8 150 #endif 151 152 #define SIP_TXQUEUELEN 256 153 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 154 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 155 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 156 157 #if defined(DP83820) 158 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 159 #else 160 #define TX_DMAMAP_SIZE MCLBYTES 161 #endif 162 163 /* 164 * Receive descriptor list size. We have one Rx buffer per incoming 165 * packet, so this logic is a little simpler. 166 * 167 * Actually, on the DP83820, we allow the packet to consume more than 168 * one buffer, in order to support jumbo Ethernet frames. In that 169 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 170 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 171 * so we'd better be quick about handling receive interrupts. 172 */ 173 #if defined(DP83820) 174 #define SIP_NRXDESC 256 175 #else 176 #define SIP_NRXDESC 128 177 #endif /* DP83820 */ 178 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 179 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 180 181 /* 182 * Control structures are DMA'd to the SiS900 chip. We allocate them in 183 * a single clump that maps to a single DMA segment to make several things 184 * easier. 185 */ 186 struct sip_control_data { 187 /* 188 * The transmit descriptors. 189 */ 190 struct sip_desc scd_txdescs[SIP_NTXDESC]; 191 192 /* 193 * The receive descriptors. 194 */ 195 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 196 }; 197 198 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 199 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 200 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 201 202 /* 203 * Software state for transmit jobs. 204 */ 205 struct sip_txsoft { 206 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 207 bus_dmamap_t txs_dmamap; /* our DMA map */ 208 int txs_firstdesc; /* first descriptor in packet */ 209 int txs_lastdesc; /* last descriptor in packet */ 210 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 211 }; 212 213 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 214 215 /* 216 * Software state for receive jobs. 217 */ 218 struct sip_rxsoft { 219 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 220 bus_dmamap_t rxs_dmamap; /* our DMA map */ 221 }; 222 223 /* 224 * Software state per device. 225 */ 226 struct sip_softc { 227 struct device sc_dev; /* generic device information */ 228 bus_space_tag_t sc_st; /* bus space tag */ 229 bus_space_handle_t sc_sh; /* bus space handle */ 230 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 231 struct ethercom sc_ethercom; /* ethernet common data */ 232 void *sc_sdhook; /* shutdown hook */ 233 234 const struct sip_product *sc_model; /* which model are we? */ 235 int sc_rev; /* chip revision */ 236 237 void *sc_ih; /* interrupt cookie */ 238 239 struct mii_data sc_mii; /* MII/media information */ 240 241 struct callout sc_tick_ch; /* tick callout */ 242 243 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 244 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 245 246 /* 247 * Software state for transmit and receive descriptors. 248 */ 249 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 250 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 251 252 /* 253 * Control data structures. 254 */ 255 struct sip_control_data *sc_control_data; 256 #define sc_txdescs sc_control_data->scd_txdescs 257 #define sc_rxdescs sc_control_data->scd_rxdescs 258 259 #ifdef SIP_EVENT_COUNTERS 260 /* 261 * Event counters. 262 */ 263 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 264 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 265 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 266 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 267 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 268 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 269 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 270 struct evcnt sc_ev_rxpause; /* PAUSE received */ 271 #ifdef DP83820 272 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 273 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 274 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 275 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 276 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 277 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 278 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 279 #endif /* DP83820 */ 280 #endif /* SIP_EVENT_COUNTERS */ 281 282 u_int32_t sc_txcfg; /* prototype TXCFG register */ 283 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 284 u_int32_t sc_imr; /* prototype IMR register */ 285 u_int32_t sc_rfcr; /* prototype RFCR register */ 286 287 u_int32_t sc_cfg; /* prototype CFG register */ 288 289 #ifdef DP83820 290 u_int32_t sc_gpior; /* prototype GPIOR register */ 291 #endif /* DP83820 */ 292 293 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 294 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 295 296 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 297 298 int sc_flowflags; /* 802.3x flow control flags */ 299 #ifdef DP83820 300 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 301 #else 302 int sc_paused; /* paused indication */ 303 #endif 304 305 int sc_txfree; /* number of free Tx descriptors */ 306 int sc_txnext; /* next ready Tx descriptor */ 307 int sc_txwin; /* Tx descriptors since last intr */ 308 309 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 310 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 311 312 short sc_if_flags; 313 314 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 315 #if defined(DP83820) 316 int sc_rxdiscard; 317 int sc_rxlen; 318 struct mbuf *sc_rxhead; 319 struct mbuf *sc_rxtail; 320 struct mbuf **sc_rxtailp; 321 #endif /* DP83820 */ 322 323 #if NRND > 0 324 rndsource_element_t rnd_source; /* random source */ 325 #endif 326 }; 327 328 #ifdef DP83820 329 #define SIP_RXCHAIN_RESET(sc) \ 330 do { \ 331 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 332 *(sc)->sc_rxtailp = NULL; \ 333 (sc)->sc_rxlen = 0; \ 334 } while (/*CONSTCOND*/0) 335 336 #define SIP_RXCHAIN_LINK(sc, m) \ 337 do { \ 338 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 339 (sc)->sc_rxtailp = &(m)->m_next; \ 340 } while (/*CONSTCOND*/0) 341 #endif /* DP83820 */ 342 343 #ifdef SIP_EVENT_COUNTERS 344 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 345 #else 346 #define SIP_EVCNT_INCR(ev) /* nothing */ 347 #endif 348 349 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 350 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 351 352 #define SIP_CDTXSYNC(sc, x, n, ops) \ 353 do { \ 354 int __x, __n; \ 355 \ 356 __x = (x); \ 357 __n = (n); \ 358 \ 359 /* If it will wrap around, sync to the end of the ring. */ \ 360 if ((__x + __n) > SIP_NTXDESC) { \ 361 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 362 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 363 (SIP_NTXDESC - __x), (ops)); \ 364 __n -= (SIP_NTXDESC - __x); \ 365 __x = 0; \ 366 } \ 367 \ 368 /* Now sync whatever is left. */ \ 369 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 370 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 371 } while (0) 372 373 #define SIP_CDRXSYNC(sc, x, ops) \ 374 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 375 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 376 377 #ifdef DP83820 378 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 379 #define SIP_RXBUF_LEN (MCLBYTES - 8) 380 #else 381 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 382 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 383 #endif 384 #define SIP_INIT_RXDESC(sc, x) \ 385 do { \ 386 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 387 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 388 \ 389 __sipd->sipd_link = \ 390 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 391 __sipd->sipd_bufptr = \ 392 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 393 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 394 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 395 SIP_INIT_RXDESC_EXTSTS \ 396 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 397 } while (0) 398 399 #define SIP_CHIP_VERS(sc, v, p, r) \ 400 ((sc)->sc_model->sip_vendor == (v) && \ 401 (sc)->sc_model->sip_product == (p) && \ 402 (sc)->sc_rev == (r)) 403 404 #define SIP_CHIP_MODEL(sc, v, p) \ 405 ((sc)->sc_model->sip_vendor == (v) && \ 406 (sc)->sc_model->sip_product == (p)) 407 408 #if !defined(DP83820) 409 #define SIP_SIS900_REV(sc, rev) \ 410 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 411 #endif 412 413 #define SIP_TIMEOUT 1000 414 415 static void SIP_DECL(start)(struct ifnet *); 416 static void SIP_DECL(watchdog)(struct ifnet *); 417 static int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 418 static int SIP_DECL(init)(struct ifnet *); 419 static void SIP_DECL(stop)(struct ifnet *, int); 420 421 static void SIP_DECL(shutdown)(void *); 422 423 static void SIP_DECL(reset)(struct sip_softc *); 424 static void SIP_DECL(rxdrain)(struct sip_softc *); 425 static int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 426 static void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, 427 u_int16_t *); 428 static void SIP_DECL(tick)(void *); 429 430 #if !defined(DP83820) 431 static void SIP_DECL(sis900_set_filter)(struct sip_softc *); 432 #endif /* ! DP83820 */ 433 static void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 434 435 #if defined(DP83820) 436 static void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 437 const struct pci_attach_args *, u_int8_t *); 438 #else 439 static void SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc); 440 static void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 441 const struct pci_attach_args *, u_int8_t *); 442 static void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 443 const struct pci_attach_args *, u_int8_t *); 444 #endif /* DP83820 */ 445 446 static int SIP_DECL(intr)(void *); 447 static void SIP_DECL(txintr)(struct sip_softc *); 448 static void SIP_DECL(rxintr)(struct sip_softc *); 449 450 #if defined(DP83820) 451 static int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 452 static void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 453 static void SIP_DECL(dp83820_mii_statchg)(struct device *); 454 #else 455 static int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 456 static void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 457 static void SIP_DECL(sis900_mii_statchg)(struct device *); 458 459 static int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 460 static void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 461 static void SIP_DECL(dp83815_mii_statchg)(struct device *); 462 #endif /* DP83820 */ 463 464 static int SIP_DECL(mediachange)(struct ifnet *); 465 static void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 466 467 static int SIP_DECL(match)(struct device *, struct cfdata *, void *); 468 static void SIP_DECL(attach)(struct device *, struct device *, void *); 469 470 int SIP_DECL(copy_small) = 0; 471 472 #ifdef DP83820 473 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 474 gsip_match, gsip_attach, NULL, NULL); 475 #else 476 CFATTACH_DECL(sip, sizeof(struct sip_softc), 477 sip_match, sip_attach, NULL, NULL); 478 #endif 479 480 /* 481 * Descriptions of the variants of the SiS900. 482 */ 483 struct sip_variant { 484 int (*sipv_mii_readreg)(struct device *, int, int); 485 void (*sipv_mii_writereg)(struct device *, int, int, int); 486 void (*sipv_mii_statchg)(struct device *); 487 void (*sipv_set_filter)(struct sip_softc *); 488 void (*sipv_read_macaddr)(struct sip_softc *, 489 const struct pci_attach_args *, u_int8_t *); 490 }; 491 492 static u_int32_t SIP_DECL(mii_bitbang_read)(struct device *); 493 static void SIP_DECL(mii_bitbang_write)(struct device *, u_int32_t); 494 495 static const struct mii_bitbang_ops SIP_DECL(mii_bitbang_ops) = { 496 SIP_DECL(mii_bitbang_read), 497 SIP_DECL(mii_bitbang_write), 498 { 499 EROMAR_MDIO, /* MII_BIT_MDO */ 500 EROMAR_MDIO, /* MII_BIT_MDI */ 501 EROMAR_MDC, /* MII_BIT_MDC */ 502 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 503 0, /* MII_BIT_DIR_PHY_HOST */ 504 } 505 }; 506 507 #if defined(DP83820) 508 static const struct sip_variant SIP_DECL(variant_dp83820) = { 509 SIP_DECL(dp83820_mii_readreg), 510 SIP_DECL(dp83820_mii_writereg), 511 SIP_DECL(dp83820_mii_statchg), 512 SIP_DECL(dp83815_set_filter), 513 SIP_DECL(dp83820_read_macaddr), 514 }; 515 #else 516 static const struct sip_variant SIP_DECL(variant_sis900) = { 517 SIP_DECL(sis900_mii_readreg), 518 SIP_DECL(sis900_mii_writereg), 519 SIP_DECL(sis900_mii_statchg), 520 SIP_DECL(sis900_set_filter), 521 SIP_DECL(sis900_read_macaddr), 522 }; 523 524 static const struct sip_variant SIP_DECL(variant_dp83815) = { 525 SIP_DECL(dp83815_mii_readreg), 526 SIP_DECL(dp83815_mii_writereg), 527 SIP_DECL(dp83815_mii_statchg), 528 SIP_DECL(dp83815_set_filter), 529 SIP_DECL(dp83815_read_macaddr), 530 }; 531 #endif /* DP83820 */ 532 533 /* 534 * Devices supported by this driver. 535 */ 536 static const struct sip_product { 537 pci_vendor_id_t sip_vendor; 538 pci_product_id_t sip_product; 539 const char *sip_name; 540 const struct sip_variant *sip_variant; 541 } SIP_DECL(products)[] = { 542 #if defined(DP83820) 543 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 544 "NatSemi DP83820 Gigabit Ethernet", 545 &SIP_DECL(variant_dp83820) }, 546 #else 547 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 548 "SiS 900 10/100 Ethernet", 549 &SIP_DECL(variant_sis900) }, 550 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 551 "SiS 7016 10/100 Ethernet", 552 &SIP_DECL(variant_sis900) }, 553 554 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 555 "NatSemi DP83815 10/100 Ethernet", 556 &SIP_DECL(variant_dp83815) }, 557 #endif /* DP83820 */ 558 559 { 0, 0, 560 NULL, 561 NULL }, 562 }; 563 564 static const struct sip_product * 565 SIP_DECL(lookup)(const struct pci_attach_args *pa) 566 { 567 const struct sip_product *sip; 568 569 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 570 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 571 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 572 return (sip); 573 } 574 return (NULL); 575 } 576 577 #ifdef DP83820 578 /* 579 * I really hate stupid hardware vendors. There's a bit in the EEPROM 580 * which indicates if the card can do 64-bit data transfers. Unfortunately, 581 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 582 * which means we try to use 64-bit data transfers on those cards if we 583 * happen to be plugged into a 32-bit slot. 584 * 585 * What we do is use this table of cards known to be 64-bit cards. If 586 * you have a 64-bit card who's subsystem ID is not listed in this table, 587 * send the output of "pcictl dump ..." of the device to me so that your 588 * card will use the 64-bit data path when plugged into a 64-bit slot. 589 * 590 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 591 * June 30, 2002 592 */ 593 static int 594 SIP_DECL(check_64bit)(const struct pci_attach_args *pa) 595 { 596 static const struct { 597 pci_vendor_id_t c64_vendor; 598 pci_product_id_t c64_product; 599 } card64[] = { 600 /* Asante GigaNIX */ 601 { 0x128a, 0x0002 }, 602 603 /* Accton EN1407-T, Planex GN-1000TE */ 604 { 0x1113, 0x1407 }, 605 606 /* Netgear GA-621 */ 607 { 0x1385, 0x621a }, 608 609 /* SMC EZ Card */ 610 { 0x10b8, 0x9462 }, 611 612 { 0, 0} 613 }; 614 pcireg_t subsys; 615 int i; 616 617 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 618 619 for (i = 0; card64[i].c64_vendor != 0; i++) { 620 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 621 PCI_PRODUCT(subsys) == card64[i].c64_product) 622 return (1); 623 } 624 625 return (0); 626 } 627 #endif /* DP83820 */ 628 629 static int 630 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 631 { 632 struct pci_attach_args *pa = aux; 633 634 if (SIP_DECL(lookup)(pa) != NULL) 635 return (1); 636 637 return (0); 638 } 639 640 static void 641 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 642 { 643 struct sip_softc *sc = (struct sip_softc *) self; 644 struct pci_attach_args *pa = aux; 645 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 646 pci_chipset_tag_t pc = pa->pa_pc; 647 pci_intr_handle_t ih; 648 const char *intrstr = NULL; 649 bus_space_tag_t iot, memt; 650 bus_space_handle_t ioh, memh; 651 bus_dma_segment_t seg; 652 int ioh_valid, memh_valid; 653 int i, rseg, error; 654 const struct sip_product *sip; 655 pcireg_t pmode; 656 u_int8_t enaddr[ETHER_ADDR_LEN]; 657 int pmreg; 658 #ifdef DP83820 659 pcireg_t memtype; 660 u_int32_t reg; 661 #endif /* DP83820 */ 662 663 callout_init(&sc->sc_tick_ch); 664 665 sip = SIP_DECL(lookup)(pa); 666 if (sip == NULL) { 667 printf("\n"); 668 panic(SIP_STR(attach) ": impossible"); 669 } 670 sc->sc_rev = PCI_REVISION(pa->pa_class); 671 672 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 673 674 sc->sc_model = sip; 675 676 /* 677 * XXX Work-around broken PXE firmware on some boards. 678 * 679 * The DP83815 shares an address decoder with the MEM BAR 680 * and the ROM BAR. Make sure the ROM BAR is disabled, 681 * so that memory mapped access works. 682 */ 683 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 684 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 685 ~PCI_MAPREG_ROM_ENABLE); 686 687 /* 688 * Map the device. 689 */ 690 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 691 PCI_MAPREG_TYPE_IO, 0, 692 &iot, &ioh, NULL, NULL) == 0); 693 #ifdef DP83820 694 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 695 switch (memtype) { 696 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 697 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 698 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 699 memtype, 0, &memt, &memh, NULL, NULL) == 0); 700 break; 701 default: 702 memh_valid = 0; 703 } 704 #else 705 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 706 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 707 &memt, &memh, NULL, NULL) == 0); 708 #endif /* DP83820 */ 709 710 if (memh_valid) { 711 sc->sc_st = memt; 712 sc->sc_sh = memh; 713 } else if (ioh_valid) { 714 sc->sc_st = iot; 715 sc->sc_sh = ioh; 716 } else { 717 printf("%s: unable to map device registers\n", 718 sc->sc_dev.dv_xname); 719 return; 720 } 721 722 sc->sc_dmat = pa->pa_dmat; 723 724 /* 725 * Make sure bus mastering is enabled. Also make sure 726 * Write/Invalidate is enabled if we're allowed to use it. 727 */ 728 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 729 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 730 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 731 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 732 pmreg | PCI_COMMAND_MASTER_ENABLE); 733 734 /* Get it out of power save mode if needed. */ 735 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 736 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 737 PCI_PMCSR_STATE_MASK; 738 if (pmode == PCI_PMCSR_STATE_D3) { 739 /* 740 * The card has lost all configuration data in 741 * this state, so punt. 742 */ 743 printf("%s: unable to wake up from power state D3\n", 744 sc->sc_dev.dv_xname); 745 return; 746 } 747 if (pmode != PCI_PMCSR_STATE_D0) { 748 printf("%s: waking up from power state D%d\n", 749 sc->sc_dev.dv_xname, pmode); 750 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 751 PCI_PMCSR_STATE_D0); 752 } 753 } 754 755 /* 756 * Map and establish our interrupt. 757 */ 758 if (pci_intr_map(pa, &ih)) { 759 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 760 return; 761 } 762 intrstr = pci_intr_string(pc, ih); 763 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 764 if (sc->sc_ih == NULL) { 765 printf("%s: unable to establish interrupt", 766 sc->sc_dev.dv_xname); 767 if (intrstr != NULL) 768 printf(" at %s", intrstr); 769 printf("\n"); 770 return; 771 } 772 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 773 774 SIMPLEQ_INIT(&sc->sc_txfreeq); 775 SIMPLEQ_INIT(&sc->sc_txdirtyq); 776 777 /* 778 * Allocate the control data structures, and create and load the 779 * DMA map for it. 780 */ 781 if ((error = bus_dmamem_alloc(sc->sc_dmat, 782 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 783 0)) != 0) { 784 printf("%s: unable to allocate control data, error = %d\n", 785 sc->sc_dev.dv_xname, error); 786 goto fail_0; 787 } 788 789 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 790 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 791 BUS_DMA_COHERENT)) != 0) { 792 printf("%s: unable to map control data, error = %d\n", 793 sc->sc_dev.dv_xname, error); 794 goto fail_1; 795 } 796 797 if ((error = bus_dmamap_create(sc->sc_dmat, 798 sizeof(struct sip_control_data), 1, 799 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 800 printf("%s: unable to create control data DMA map, " 801 "error = %d\n", sc->sc_dev.dv_xname, error); 802 goto fail_2; 803 } 804 805 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 806 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 807 0)) != 0) { 808 printf("%s: unable to load control data DMA map, error = %d\n", 809 sc->sc_dev.dv_xname, error); 810 goto fail_3; 811 } 812 813 /* 814 * Create the transmit buffer DMA maps. 815 */ 816 for (i = 0; i < SIP_TXQUEUELEN; i++) { 817 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 818 SIP_NTXSEGS, MCLBYTES, 0, 0, 819 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 820 printf("%s: unable to create tx DMA map %d, " 821 "error = %d\n", sc->sc_dev.dv_xname, i, error); 822 goto fail_4; 823 } 824 } 825 826 /* 827 * Create the receive buffer DMA maps. 828 */ 829 for (i = 0; i < SIP_NRXDESC; i++) { 830 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 831 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 832 printf("%s: unable to create rx DMA map %d, " 833 "error = %d\n", sc->sc_dev.dv_xname, i, error); 834 goto fail_5; 835 } 836 sc->sc_rxsoft[i].rxs_mbuf = NULL; 837 } 838 839 /* 840 * Reset the chip to a known state. 841 */ 842 SIP_DECL(reset)(sc); 843 844 /* 845 * Read the Ethernet address from the EEPROM. This might 846 * also fetch other stuff from the EEPROM and stash it 847 * in the softc. 848 */ 849 sc->sc_cfg = 0; 850 #if !defined(DP83820) 851 if (SIP_SIS900_REV(sc,SIS_REV_635) || 852 SIP_SIS900_REV(sc,SIS_REV_900B)) 853 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 854 855 if (SIP_SIS900_REV(sc,SIS_REV_635) || 856 SIP_SIS900_REV(sc,SIS_REV_960) || 857 SIP_SIS900_REV(sc,SIS_REV_900B)) 858 sc->sc_cfg |= (bus_space_read_4(sc->sc_st, sc->sc_sh, 859 SIP_CFG) & CFG_EDBMASTEN); 860 #endif 861 862 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 863 864 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 865 ether_sprintf(enaddr)); 866 867 /* 868 * Initialize the configuration register: aggressive PCI 869 * bus request algorithm, default backoff, default OW timer, 870 * default parity error detection. 871 * 872 * NOTE: "Big endian mode" is useless on the SiS900 and 873 * friends -- it affects packet data, not descriptors. 874 */ 875 #ifdef DP83820 876 /* 877 * Cause the chip to load configuration data from the EEPROM. 878 */ 879 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 880 for (i = 0; i < 10000; i++) { 881 delay(10); 882 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 883 PTSCR_EELOAD_EN) == 0) 884 break; 885 } 886 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 887 PTSCR_EELOAD_EN) { 888 printf("%s: timeout loading configuration from EEPROM\n", 889 sc->sc_dev.dv_xname); 890 return; 891 } 892 893 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 894 895 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 896 if (reg & CFG_PCI64_DET) { 897 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 898 /* 899 * Check to see if this card is 64-bit. If so, enable 64-bit 900 * data transfers. 901 * 902 * We can't use the DATA64_EN bit in the EEPROM, because 903 * vendors of 32-bit cards fail to clear that bit in many 904 * cases (yet the card still detects that it's in a 64-bit 905 * slot; go figure). 906 */ 907 if (SIP_DECL(check_64bit)(pa)) { 908 sc->sc_cfg |= CFG_DATA64_EN; 909 printf(", using 64-bit data transfers"); 910 } 911 printf("\n"); 912 } 913 914 /* 915 * XXX Need some PCI flags indicating support for 916 * XXX 64-bit addressing. 917 */ 918 #if 0 919 if (reg & CFG_M64ADDR) 920 sc->sc_cfg |= CFG_M64ADDR; 921 if (reg & CFG_T64ADDR) 922 sc->sc_cfg |= CFG_T64ADDR; 923 #endif 924 925 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 926 const char *sep = ""; 927 printf("%s: using ", sc->sc_dev.dv_xname); 928 if (reg & CFG_EXT_125) { 929 sc->sc_cfg |= CFG_EXT_125; 930 printf("%s125MHz clock", sep); 931 sep = ", "; 932 } 933 if (reg & CFG_TBI_EN) { 934 sc->sc_cfg |= CFG_TBI_EN; 935 printf("%sten-bit interface", sep); 936 sep = ", "; 937 } 938 printf("\n"); 939 } 940 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 941 (reg & CFG_MRM_DIS) != 0) 942 sc->sc_cfg |= CFG_MRM_DIS; 943 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 944 (reg & CFG_MWI_DIS) != 0) 945 sc->sc_cfg |= CFG_MWI_DIS; 946 947 /* 948 * Use the extended descriptor format on the DP83820. This 949 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 950 * checksumming. 951 */ 952 sc->sc_cfg |= CFG_EXTSTS_EN; 953 #endif /* DP83820 */ 954 955 /* 956 * Initialize our media structures and probe the MII. 957 */ 958 sc->sc_mii.mii_ifp = ifp; 959 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 960 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 961 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 962 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, SIP_DECL(mediachange), 963 SIP_DECL(mediastatus)); 964 965 /* 966 * XXX We cannot handle flow control on the DP83815. 967 */ 968 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 969 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 970 MII_OFFSET_ANY, 0); 971 else 972 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 973 MII_OFFSET_ANY, MIIF_DOPAUSE); 974 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 975 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 976 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 977 } else 978 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 979 980 ifp = &sc->sc_ethercom.ec_if; 981 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 982 ifp->if_softc = sc; 983 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 984 sc->sc_if_flags = ifp->if_flags; 985 ifp->if_ioctl = SIP_DECL(ioctl); 986 ifp->if_start = SIP_DECL(start); 987 ifp->if_watchdog = SIP_DECL(watchdog); 988 ifp->if_init = SIP_DECL(init); 989 ifp->if_stop = SIP_DECL(stop); 990 IFQ_SET_READY(&ifp->if_snd); 991 992 /* 993 * We can support 802.1Q VLAN-sized frames. 994 */ 995 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 996 997 #ifdef DP83820 998 /* 999 * And the DP83820 can do VLAN tagging in hardware, and 1000 * support the jumbo Ethernet MTU. 1001 */ 1002 sc->sc_ethercom.ec_capabilities |= 1003 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1004 1005 /* 1006 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1007 * in hardware. 1008 */ 1009 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 1010 IFCAP_CSUM_UDPv4; 1011 #endif /* DP83820 */ 1012 1013 /* 1014 * Attach the interface. 1015 */ 1016 if_attach(ifp); 1017 ether_ifattach(ifp, enaddr); 1018 #if NRND > 0 1019 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1020 RND_TYPE_NET, 0); 1021 #endif 1022 1023 /* 1024 * The number of bytes that must be available in 1025 * the Tx FIFO before the bus master can DMA more 1026 * data into the FIFO. 1027 */ 1028 sc->sc_tx_fill_thresh = 64 / 32; 1029 1030 /* 1031 * Start at a drain threshold of 512 bytes. We will 1032 * increase it if a DMA underrun occurs. 1033 * 1034 * XXX The minimum value of this variable should be 1035 * tuned. We may be able to improve performance 1036 * by starting with a lower value. That, however, 1037 * may trash the first few outgoing packets if the 1038 * PCI bus is saturated. 1039 */ 1040 #ifdef DP83820 1041 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1042 #else 1043 sc->sc_tx_drain_thresh = 1504 / 32; 1044 #endif 1045 1046 /* 1047 * Initialize the Rx FIFO drain threshold. 1048 * 1049 * This is in units of 8 bytes. 1050 * 1051 * We should never set this value lower than 2; 14 bytes are 1052 * required to filter the packet. 1053 */ 1054 sc->sc_rx_drain_thresh = 128 / 8; 1055 1056 #ifdef SIP_EVENT_COUNTERS 1057 /* 1058 * Attach event counters. 1059 */ 1060 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1061 NULL, sc->sc_dev.dv_xname, "txsstall"); 1062 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1063 NULL, sc->sc_dev.dv_xname, "txdstall"); 1064 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1065 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1066 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1067 NULL, sc->sc_dev.dv_xname, "txdintr"); 1068 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1069 NULL, sc->sc_dev.dv_xname, "txiintr"); 1070 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1071 NULL, sc->sc_dev.dv_xname, "rxintr"); 1072 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1073 NULL, sc->sc_dev.dv_xname, "hiberr"); 1074 #ifndef DP83820 1075 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1076 NULL, sc->sc_dev.dv_xname, "rxpause"); 1077 #endif /* !DP83820 */ 1078 #ifdef DP83820 1079 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1080 NULL, sc->sc_dev.dv_xname, "rxpause"); 1081 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1082 NULL, sc->sc_dev.dv_xname, "txpause"); 1083 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1084 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1085 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1086 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1087 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1088 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1089 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1090 NULL, sc->sc_dev.dv_xname, "txipsum"); 1091 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1092 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1093 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1094 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1095 #endif /* DP83820 */ 1096 #endif /* SIP_EVENT_COUNTERS */ 1097 1098 /* 1099 * Make sure the interface is shutdown during reboot. 1100 */ 1101 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 1102 if (sc->sc_sdhook == NULL) 1103 printf("%s: WARNING: unable to establish shutdown hook\n", 1104 sc->sc_dev.dv_xname); 1105 return; 1106 1107 /* 1108 * Free any resources we've allocated during the failed attach 1109 * attempt. Do this in reverse order and fall through. 1110 */ 1111 fail_5: 1112 for (i = 0; i < SIP_NRXDESC; i++) { 1113 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1114 bus_dmamap_destroy(sc->sc_dmat, 1115 sc->sc_rxsoft[i].rxs_dmamap); 1116 } 1117 fail_4: 1118 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1119 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1120 bus_dmamap_destroy(sc->sc_dmat, 1121 sc->sc_txsoft[i].txs_dmamap); 1122 } 1123 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1124 fail_3: 1125 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1126 fail_2: 1127 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1128 sizeof(struct sip_control_data)); 1129 fail_1: 1130 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1131 fail_0: 1132 return; 1133 } 1134 1135 /* 1136 * sip_shutdown: 1137 * 1138 * Make sure the interface is stopped at reboot time. 1139 */ 1140 static void 1141 SIP_DECL(shutdown)(void *arg) 1142 { 1143 struct sip_softc *sc = arg; 1144 1145 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1146 } 1147 1148 /* 1149 * sip_start: [ifnet interface function] 1150 * 1151 * Start packet transmission on the interface. 1152 */ 1153 static void 1154 SIP_DECL(start)(struct ifnet *ifp) 1155 { 1156 struct sip_softc *sc = ifp->if_softc; 1157 struct mbuf *m0; 1158 #ifndef DP83820 1159 struct mbuf *m; 1160 #endif 1161 struct sip_txsoft *txs; 1162 bus_dmamap_t dmamap; 1163 int error, nexttx, lasttx, seg; 1164 int ofree = sc->sc_txfree; 1165 #if 0 1166 int firsttx = sc->sc_txnext; 1167 #endif 1168 #ifdef DP83820 1169 struct m_tag *mtag; 1170 u_int32_t extsts; 1171 #endif 1172 1173 #ifndef DP83820 1174 /* 1175 * If we've been told to pause, don't transmit any more packets. 1176 */ 1177 if (sc->sc_paused) 1178 ifp->if_flags |= IFF_OACTIVE; 1179 #endif 1180 1181 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1182 return; 1183 1184 /* 1185 * Loop through the send queue, setting up transmit descriptors 1186 * until we drain the queue, or use up all available transmit 1187 * descriptors. 1188 */ 1189 for (;;) { 1190 /* Get a work queue entry. */ 1191 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1192 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1193 break; 1194 } 1195 1196 /* 1197 * Grab a packet off the queue. 1198 */ 1199 IFQ_POLL(&ifp->if_snd, m0); 1200 if (m0 == NULL) 1201 break; 1202 #ifndef DP83820 1203 m = NULL; 1204 #endif 1205 1206 dmamap = txs->txs_dmamap; 1207 1208 #ifdef DP83820 1209 /* 1210 * Load the DMA map. If this fails, the packet either 1211 * didn't fit in the allotted number of segments, or we 1212 * were short on resources. For the too-many-segments 1213 * case, we simply report an error and drop the packet, 1214 * since we can't sanely copy a jumbo packet to a single 1215 * buffer. 1216 */ 1217 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1218 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1219 if (error) { 1220 if (error == EFBIG) { 1221 printf("%s: Tx packet consumes too many " 1222 "DMA segments, dropping...\n", 1223 sc->sc_dev.dv_xname); 1224 IFQ_DEQUEUE(&ifp->if_snd, m0); 1225 m_freem(m0); 1226 continue; 1227 } 1228 /* 1229 * Short on resources, just stop for now. 1230 */ 1231 break; 1232 } 1233 #else /* DP83820 */ 1234 /* 1235 * Load the DMA map. If this fails, the packet either 1236 * didn't fit in the alloted number of segments, or we 1237 * were short on resources. In this case, we'll copy 1238 * and try again. 1239 */ 1240 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1241 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1242 MGETHDR(m, M_DONTWAIT, MT_DATA); 1243 if (m == NULL) { 1244 printf("%s: unable to allocate Tx mbuf\n", 1245 sc->sc_dev.dv_xname); 1246 break; 1247 } 1248 if (m0->m_pkthdr.len > MHLEN) { 1249 MCLGET(m, M_DONTWAIT); 1250 if ((m->m_flags & M_EXT) == 0) { 1251 printf("%s: unable to allocate Tx " 1252 "cluster\n", sc->sc_dev.dv_xname); 1253 m_freem(m); 1254 break; 1255 } 1256 } 1257 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1258 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1259 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1260 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1261 if (error) { 1262 printf("%s: unable to load Tx buffer, " 1263 "error = %d\n", sc->sc_dev.dv_xname, error); 1264 break; 1265 } 1266 } 1267 #endif /* DP83820 */ 1268 1269 /* 1270 * Ensure we have enough descriptors free to describe 1271 * the packet. Note, we always reserve one descriptor 1272 * at the end of the ring as a termination point, to 1273 * prevent wrap-around. 1274 */ 1275 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1276 /* 1277 * Not enough free descriptors to transmit this 1278 * packet. We haven't committed anything yet, 1279 * so just unload the DMA map, put the packet 1280 * back on the queue, and punt. Notify the upper 1281 * layer that there are not more slots left. 1282 * 1283 * XXX We could allocate an mbuf and copy, but 1284 * XXX is it worth it? 1285 */ 1286 ifp->if_flags |= IFF_OACTIVE; 1287 bus_dmamap_unload(sc->sc_dmat, dmamap); 1288 #ifndef DP83820 1289 if (m != NULL) 1290 m_freem(m); 1291 #endif 1292 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1293 break; 1294 } 1295 1296 IFQ_DEQUEUE(&ifp->if_snd, m0); 1297 #ifndef DP83820 1298 if (m != NULL) { 1299 m_freem(m0); 1300 m0 = m; 1301 } 1302 #endif 1303 1304 /* 1305 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1306 */ 1307 1308 /* Sync the DMA map. */ 1309 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1310 BUS_DMASYNC_PREWRITE); 1311 1312 /* 1313 * Initialize the transmit descriptors. 1314 */ 1315 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1316 seg < dmamap->dm_nsegs; 1317 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1318 /* 1319 * If this is the first descriptor we're 1320 * enqueueing, don't set the OWN bit just 1321 * yet. That could cause a race condition. 1322 * We'll do it below. 1323 */ 1324 sc->sc_txdescs[nexttx].sipd_bufptr = 1325 htole32(dmamap->dm_segs[seg].ds_addr); 1326 sc->sc_txdescs[nexttx].sipd_cmdsts = 1327 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1328 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1329 #ifdef DP83820 1330 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1331 #endif /* DP83820 */ 1332 lasttx = nexttx; 1333 } 1334 1335 /* Clear the MORE bit on the last segment. */ 1336 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1337 1338 /* 1339 * If we're in the interrupt delay window, delay the 1340 * interrupt. 1341 */ 1342 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1343 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1344 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1345 htole32(CMDSTS_INTR); 1346 sc->sc_txwin = 0; 1347 } 1348 1349 #ifdef DP83820 1350 /* 1351 * If VLANs are enabled and the packet has a VLAN tag, set 1352 * up the descriptor to encapsulate the packet for us. 1353 * 1354 * This apparently has to be on the last descriptor of 1355 * the packet. 1356 */ 1357 if (sc->sc_ethercom.ec_nvlans != 0 && 1358 (mtag = m_tag_find(m0, PACKET_TAG_VLAN, NULL)) != NULL) { 1359 sc->sc_txdescs[lasttx].sipd_extsts |= 1360 htole32(EXTSTS_VPKT | 1361 (*(u_int *)(mtag + 1) & EXTSTS_VTCI)); 1362 } 1363 1364 /* 1365 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1366 * checksumming, set up the descriptor to do this work 1367 * for us. 1368 * 1369 * This apparently has to be on the first descriptor of 1370 * the packet. 1371 * 1372 * Byte-swap constants so the compiler can optimize. 1373 */ 1374 extsts = 0; 1375 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1376 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1377 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1378 extsts |= htole32(EXTSTS_IPPKT); 1379 } 1380 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1381 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1382 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1383 extsts |= htole32(EXTSTS_TCPPKT); 1384 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1385 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1386 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1387 extsts |= htole32(EXTSTS_UDPPKT); 1388 } 1389 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1390 #endif /* DP83820 */ 1391 1392 /* Sync the descriptors we're using. */ 1393 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1394 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1395 1396 /* 1397 * The entire packet is set up. Give the first descrptor 1398 * to the chip now. 1399 */ 1400 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1401 htole32(CMDSTS_OWN); 1402 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1403 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1404 1405 /* 1406 * Store a pointer to the packet so we can free it later, 1407 * and remember what txdirty will be once the packet is 1408 * done. 1409 */ 1410 txs->txs_mbuf = m0; 1411 txs->txs_firstdesc = sc->sc_txnext; 1412 txs->txs_lastdesc = lasttx; 1413 1414 /* Advance the tx pointer. */ 1415 sc->sc_txfree -= dmamap->dm_nsegs; 1416 sc->sc_txnext = nexttx; 1417 1418 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1419 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1420 1421 #if NBPFILTER > 0 1422 /* 1423 * Pass the packet to any BPF listeners. 1424 */ 1425 if (ifp->if_bpf) 1426 bpf_mtap(ifp->if_bpf, m0); 1427 #endif /* NBPFILTER > 0 */ 1428 } 1429 1430 if (txs == NULL || sc->sc_txfree == 0) { 1431 /* No more slots left; notify upper layer. */ 1432 ifp->if_flags |= IFF_OACTIVE; 1433 } 1434 1435 if (sc->sc_txfree != ofree) { 1436 /* 1437 * Start the transmit process. Note, the manual says 1438 * that if there are no pending transmissions in the 1439 * chip's internal queue (indicated by TXE being clear), 1440 * then the driver software must set the TXDP to the 1441 * first descriptor to be transmitted. However, if we 1442 * do this, it causes serious performance degredation on 1443 * the DP83820 under load, not setting TXDP doesn't seem 1444 * to adversely affect the SiS 900 or DP83815. 1445 * 1446 * Well, I guess it wouldn't be the first time a manual 1447 * has lied -- and they could be speaking of the NULL- 1448 * terminated descriptor list case, rather than OWN- 1449 * terminated rings. 1450 */ 1451 #if 0 1452 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1453 CR_TXE) == 0) { 1454 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1455 SIP_CDTXADDR(sc, firsttx)); 1456 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1457 } 1458 #else 1459 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1460 #endif 1461 1462 /* Set a watchdog timer in case the chip flakes out. */ 1463 #ifdef DP83820 1464 /* Gigabit autonegotiation takes 5 seconds. */ 1465 ifp->if_timer = 10; 1466 #else 1467 ifp->if_timer = 5; 1468 #endif 1469 } 1470 } 1471 1472 /* 1473 * sip_watchdog: [ifnet interface function] 1474 * 1475 * Watchdog timer handler. 1476 */ 1477 static void 1478 SIP_DECL(watchdog)(struct ifnet *ifp) 1479 { 1480 struct sip_softc *sc = ifp->if_softc; 1481 1482 /* 1483 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1484 * If we get a timeout, try and sweep up transmit descriptors. 1485 * If we manage to sweep them all up, ignore the lack of 1486 * interrupt. 1487 */ 1488 SIP_DECL(txintr)(sc); 1489 1490 if (sc->sc_txfree != SIP_NTXDESC) { 1491 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1492 ifp->if_oerrors++; 1493 1494 /* Reset the interface. */ 1495 (void) SIP_DECL(init)(ifp); 1496 } else if (ifp->if_flags & IFF_DEBUG) 1497 printf("%s: recovered from device timeout\n", 1498 sc->sc_dev.dv_xname); 1499 1500 /* Try to get more packets going. */ 1501 SIP_DECL(start)(ifp); 1502 } 1503 1504 /* 1505 * sip_ioctl: [ifnet interface function] 1506 * 1507 * Handle control requests from the operator. 1508 */ 1509 static int 1510 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1511 { 1512 struct sip_softc *sc = ifp->if_softc; 1513 struct ifreq *ifr = (struct ifreq *)data; 1514 int s, error; 1515 1516 s = splnet(); 1517 1518 switch (cmd) { 1519 case SIOCSIFMEDIA: 1520 /* Flow control requires full-duplex mode. */ 1521 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1522 (ifr->ifr_media & IFM_FDX) == 0) 1523 ifr->ifr_media &= ~IFM_ETH_FMASK; 1524 #ifdef DP83820 1525 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1526 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1527 /* We can do both TXPAUSE and RXPAUSE. */ 1528 ifr->ifr_media |= 1529 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1530 } 1531 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1532 } 1533 #else 1534 /* XXX */ 1535 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1536 ifr->ifr_media &= ~IFM_ETH_FMASK; 1537 1538 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1539 if (ifr->ifr_media & IFM_FLOW) { 1540 /* 1541 * Both TXPAUSE and RXPAUSE must be set. 1542 * (SiS900 and DP83815 don't have PAUSE_ASYM 1543 * feature.) 1544 * 1545 * XXX Can SiS900 and DP83815 send PAUSE? 1546 */ 1547 ifr->ifr_media |= 1548 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1549 } 1550 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1551 } 1552 #endif 1553 /* FALLTHROUGH */ 1554 case SIOCGIFMEDIA: 1555 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1556 break; 1557 case SIOCSIFFLAGS: 1558 /* If the interface is up and running, only modify the receive 1559 * filter when setting promiscuous or debug mode. Otherwise 1560 * fall through to ether_ioctl, which will reset the chip. 1561 */ 1562 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 1563 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 1564 == (IFF_UP|IFF_RUNNING)) 1565 && ((ifp->if_flags & (~RESETIGN)) 1566 == (sc->sc_if_flags & (~RESETIGN)))) { 1567 /* Set up the receive filter. */ 1568 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1569 error = 0; 1570 break; 1571 #undef RESETIGN 1572 } 1573 /* FALLTHROUGH */ 1574 default: 1575 error = ether_ioctl(ifp, cmd, data); 1576 if (error == ENETRESET) { 1577 /* 1578 * Multicast list has changed; set the hardware filter 1579 * accordingly. 1580 */ 1581 if (ifp->if_flags & IFF_RUNNING) 1582 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1583 error = 0; 1584 } 1585 break; 1586 } 1587 1588 /* Try to get more packets going. */ 1589 SIP_DECL(start)(ifp); 1590 1591 sc->sc_if_flags = ifp->if_flags; 1592 splx(s); 1593 return (error); 1594 } 1595 1596 /* 1597 * sip_intr: 1598 * 1599 * Interrupt service routine. 1600 */ 1601 static int 1602 SIP_DECL(intr)(void *arg) 1603 { 1604 struct sip_softc *sc = arg; 1605 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1606 u_int32_t isr; 1607 int handled = 0; 1608 1609 /* Disable interrupts. */ 1610 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1611 1612 for (;;) { 1613 /* Reading clears interrupt. */ 1614 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1615 if ((isr & sc->sc_imr) == 0) 1616 break; 1617 1618 #if NRND > 0 1619 if (RND_ENABLED(&sc->rnd_source)) 1620 rnd_add_uint32(&sc->rnd_source, isr); 1621 #endif 1622 1623 handled = 1; 1624 1625 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1626 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1627 1628 /* Grab any new packets. */ 1629 SIP_DECL(rxintr)(sc); 1630 1631 if (isr & ISR_RXORN) { 1632 printf("%s: receive FIFO overrun\n", 1633 sc->sc_dev.dv_xname); 1634 1635 /* XXX adjust rx_drain_thresh? */ 1636 } 1637 1638 if (isr & ISR_RXIDLE) { 1639 printf("%s: receive ring overrun\n", 1640 sc->sc_dev.dv_xname); 1641 1642 /* Get the receive process going again. */ 1643 bus_space_write_4(sc->sc_st, sc->sc_sh, 1644 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1645 bus_space_write_4(sc->sc_st, sc->sc_sh, 1646 SIP_CR, CR_RXE); 1647 } 1648 } 1649 1650 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1651 #ifdef SIP_EVENT_COUNTERS 1652 if (isr & ISR_TXDESC) 1653 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1654 else if (isr & ISR_TXIDLE) 1655 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1656 #endif 1657 1658 /* Sweep up transmit descriptors. */ 1659 SIP_DECL(txintr)(sc); 1660 1661 if (isr & ISR_TXURN) { 1662 u_int32_t thresh; 1663 1664 printf("%s: transmit FIFO underrun", 1665 sc->sc_dev.dv_xname); 1666 1667 thresh = sc->sc_tx_drain_thresh + 1; 1668 if (thresh <= TXCFG_DRTH && 1669 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1670 (sc->sc_tx_fill_thresh * 32))) { 1671 printf("; increasing Tx drain " 1672 "threshold to %u bytes\n", 1673 thresh * 32); 1674 sc->sc_tx_drain_thresh = thresh; 1675 (void) SIP_DECL(init)(ifp); 1676 } else { 1677 (void) SIP_DECL(init)(ifp); 1678 printf("\n"); 1679 } 1680 } 1681 } 1682 1683 #if !defined(DP83820) 1684 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1685 if (isr & ISR_PAUSE_ST) { 1686 sc->sc_paused = 1; 1687 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1688 ifp->if_flags |= IFF_OACTIVE; 1689 } 1690 if (isr & ISR_PAUSE_END) { 1691 sc->sc_paused = 0; 1692 ifp->if_flags &= ~IFF_OACTIVE; 1693 } 1694 } 1695 #endif /* ! DP83820 */ 1696 1697 if (isr & ISR_HIBERR) { 1698 int want_init = 0; 1699 1700 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1701 1702 #define PRINTERR(bit, str) \ 1703 do { \ 1704 if ((isr & (bit)) != 0) { \ 1705 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1706 printf("%s: %s\n", \ 1707 sc->sc_dev.dv_xname, str); \ 1708 want_init = 1; \ 1709 } \ 1710 } while (/*CONSTCOND*/0) 1711 1712 PRINTERR(ISR_DPERR, "parity error"); 1713 PRINTERR(ISR_SSERR, "system error"); 1714 PRINTERR(ISR_RMABT, "master abort"); 1715 PRINTERR(ISR_RTABT, "target abort"); 1716 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1717 /* 1718 * Ignore: 1719 * Tx reset complete 1720 * Rx reset complete 1721 */ 1722 if (want_init) 1723 (void) SIP_DECL(init)(ifp); 1724 #undef PRINTERR 1725 } 1726 } 1727 1728 /* Re-enable interrupts. */ 1729 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1730 1731 /* Try to get more packets going. */ 1732 SIP_DECL(start)(ifp); 1733 1734 return (handled); 1735 } 1736 1737 /* 1738 * sip_txintr: 1739 * 1740 * Helper; handle transmit interrupts. 1741 */ 1742 static void 1743 SIP_DECL(txintr)(struct sip_softc *sc) 1744 { 1745 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1746 struct sip_txsoft *txs; 1747 u_int32_t cmdsts; 1748 1749 #ifndef DP83820 1750 if (sc->sc_paused == 0) 1751 #endif 1752 ifp->if_flags &= ~IFF_OACTIVE; 1753 1754 /* 1755 * Go through our Tx list and free mbufs for those 1756 * frames which have been transmitted. 1757 */ 1758 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1759 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1760 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1761 1762 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1763 if (cmdsts & CMDSTS_OWN) 1764 break; 1765 1766 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1767 1768 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1769 1770 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1771 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1772 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1773 m_freem(txs->txs_mbuf); 1774 txs->txs_mbuf = NULL; 1775 1776 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1777 1778 /* 1779 * Check for errors and collisions. 1780 */ 1781 if (cmdsts & 1782 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1783 ifp->if_oerrors++; 1784 if (cmdsts & CMDSTS_Tx_EC) 1785 ifp->if_collisions += 16; 1786 if (ifp->if_flags & IFF_DEBUG) { 1787 if (cmdsts & CMDSTS_Tx_ED) 1788 printf("%s: excessive deferral\n", 1789 sc->sc_dev.dv_xname); 1790 if (cmdsts & CMDSTS_Tx_EC) 1791 printf("%s: excessive collisions\n", 1792 sc->sc_dev.dv_xname); 1793 } 1794 } else { 1795 /* Packet was transmitted successfully. */ 1796 ifp->if_opackets++; 1797 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1798 } 1799 } 1800 1801 /* 1802 * If there are no more pending transmissions, cancel the watchdog 1803 * timer. 1804 */ 1805 if (txs == NULL) { 1806 ifp->if_timer = 0; 1807 sc->sc_txwin = 0; 1808 } 1809 } 1810 1811 #if defined(DP83820) 1812 /* 1813 * sip_rxintr: 1814 * 1815 * Helper; handle receive interrupts. 1816 */ 1817 static void 1818 SIP_DECL(rxintr)(struct sip_softc *sc) 1819 { 1820 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1821 struct sip_rxsoft *rxs; 1822 struct mbuf *m; 1823 u_int32_t cmdsts, extsts; 1824 int i, len; 1825 1826 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1827 rxs = &sc->sc_rxsoft[i]; 1828 1829 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1830 1831 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1832 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1833 len = CMDSTS_SIZE(cmdsts); 1834 1835 /* 1836 * NOTE: OWN is set if owned by _consumer_. We're the 1837 * consumer of the receive ring, so if the bit is clear, 1838 * we have processed all of the packets. 1839 */ 1840 if ((cmdsts & CMDSTS_OWN) == 0) { 1841 /* 1842 * We have processed all of the receive buffers. 1843 */ 1844 break; 1845 } 1846 1847 if (__predict_false(sc->sc_rxdiscard)) { 1848 SIP_INIT_RXDESC(sc, i); 1849 if ((cmdsts & CMDSTS_MORE) == 0) { 1850 /* Reset our state. */ 1851 sc->sc_rxdiscard = 0; 1852 } 1853 continue; 1854 } 1855 1856 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1857 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1858 1859 m = rxs->rxs_mbuf; 1860 1861 /* 1862 * Add a new receive buffer to the ring. 1863 */ 1864 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1865 /* 1866 * Failed, throw away what we've done so 1867 * far, and discard the rest of the packet. 1868 */ 1869 ifp->if_ierrors++; 1870 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1871 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1872 SIP_INIT_RXDESC(sc, i); 1873 if (cmdsts & CMDSTS_MORE) 1874 sc->sc_rxdiscard = 1; 1875 if (sc->sc_rxhead != NULL) 1876 m_freem(sc->sc_rxhead); 1877 SIP_RXCHAIN_RESET(sc); 1878 continue; 1879 } 1880 1881 SIP_RXCHAIN_LINK(sc, m); 1882 1883 m->m_len = len; 1884 1885 /* 1886 * If this is not the end of the packet, keep 1887 * looking. 1888 */ 1889 if (cmdsts & CMDSTS_MORE) { 1890 sc->sc_rxlen += len; 1891 continue; 1892 } 1893 1894 /* 1895 * Okay, we have the entire packet now. The chip includes 1896 * the FCS, so we need to trim it. 1897 */ 1898 m->m_len -= ETHER_CRC_LEN; 1899 1900 *sc->sc_rxtailp = NULL; 1901 m = sc->sc_rxhead; 1902 len = m->m_len + sc->sc_rxlen; 1903 1904 SIP_RXCHAIN_RESET(sc); 1905 1906 /* 1907 * If an error occurred, update stats and drop the packet. 1908 */ 1909 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1910 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1911 ifp->if_ierrors++; 1912 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1913 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1914 /* Receive overrun handled elsewhere. */ 1915 printf("%s: receive descriptor error\n", 1916 sc->sc_dev.dv_xname); 1917 } 1918 #define PRINTERR(bit, str) \ 1919 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1920 (cmdsts & (bit)) != 0) \ 1921 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1922 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1923 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1924 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1925 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1926 #undef PRINTERR 1927 m_freem(m); 1928 continue; 1929 } 1930 1931 /* 1932 * If the packet is small enough to fit in a 1933 * single header mbuf, allocate one and copy 1934 * the data into it. This greatly reduces 1935 * memory consumption when we receive lots 1936 * of small packets. 1937 */ 1938 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1939 struct mbuf *nm; 1940 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1941 if (nm == NULL) { 1942 ifp->if_ierrors++; 1943 m_freem(m); 1944 continue; 1945 } 1946 nm->m_data += 2; 1947 nm->m_pkthdr.len = nm->m_len = len; 1948 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1949 m_freem(m); 1950 m = nm; 1951 } 1952 #ifndef __NO_STRICT_ALIGNMENT 1953 else { 1954 /* 1955 * The DP83820's receive buffers must be 4-byte 1956 * aligned. But this means that the data after 1957 * the Ethernet header is misaligned. To compensate, 1958 * we have artificially shortened the buffer size 1959 * in the descriptor, and we do an overlapping copy 1960 * of the data two bytes further in (in the first 1961 * buffer of the chain only). 1962 */ 1963 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1964 m->m_len); 1965 m->m_data += 2; 1966 } 1967 #endif /* ! __NO_STRICT_ALIGNMENT */ 1968 1969 /* 1970 * If VLANs are enabled, VLAN packets have been unwrapped 1971 * for us. Associate the tag with the packet. 1972 */ 1973 if (sc->sc_ethercom.ec_nvlans != 0 && 1974 (extsts & EXTSTS_VPKT) != 0) { 1975 struct m_tag *vtag; 1976 1977 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 1978 M_NOWAIT); 1979 if (vtag == NULL) { 1980 ifp->if_ierrors++; 1981 printf("%s: unable to allocate VLAN tag\n", 1982 sc->sc_dev.dv_xname); 1983 m_freem(m); 1984 continue; 1985 } 1986 1987 *(u_int *)(vtag + 1) = ntohs(extsts & EXTSTS_VTCI); 1988 } 1989 1990 /* 1991 * Set the incoming checksum information for the 1992 * packet. 1993 */ 1994 if ((extsts & EXTSTS_IPPKT) != 0) { 1995 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1996 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1997 if (extsts & EXTSTS_Rx_IPERR) 1998 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1999 if (extsts & EXTSTS_TCPPKT) { 2000 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2001 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2002 if (extsts & EXTSTS_Rx_TCPERR) 2003 m->m_pkthdr.csum_flags |= 2004 M_CSUM_TCP_UDP_BAD; 2005 } else if (extsts & EXTSTS_UDPPKT) { 2006 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2007 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2008 if (extsts & EXTSTS_Rx_UDPERR) 2009 m->m_pkthdr.csum_flags |= 2010 M_CSUM_TCP_UDP_BAD; 2011 } 2012 } 2013 2014 ifp->if_ipackets++; 2015 m->m_pkthdr.rcvif = ifp; 2016 m->m_pkthdr.len = len; 2017 2018 #if NBPFILTER > 0 2019 /* 2020 * Pass this up to any BPF listeners, but only 2021 * pass if up the stack if it's for us. 2022 */ 2023 if (ifp->if_bpf) 2024 bpf_mtap(ifp->if_bpf, m); 2025 #endif /* NBPFILTER > 0 */ 2026 2027 /* Pass it on. */ 2028 (*ifp->if_input)(ifp, m); 2029 } 2030 2031 /* Update the receive pointer. */ 2032 sc->sc_rxptr = i; 2033 } 2034 #else /* ! DP83820 */ 2035 /* 2036 * sip_rxintr: 2037 * 2038 * Helper; handle receive interrupts. 2039 */ 2040 static void 2041 SIP_DECL(rxintr)(struct sip_softc *sc) 2042 { 2043 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2044 struct sip_rxsoft *rxs; 2045 struct mbuf *m; 2046 u_int32_t cmdsts; 2047 int i, len; 2048 2049 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 2050 rxs = &sc->sc_rxsoft[i]; 2051 2052 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2053 2054 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 2055 2056 /* 2057 * NOTE: OWN is set if owned by _consumer_. We're the 2058 * consumer of the receive ring, so if the bit is clear, 2059 * we have processed all of the packets. 2060 */ 2061 if ((cmdsts & CMDSTS_OWN) == 0) { 2062 /* 2063 * We have processed all of the receive buffers. 2064 */ 2065 break; 2066 } 2067 2068 /* 2069 * If any collisions were seen on the wire, count one. 2070 */ 2071 if (cmdsts & CMDSTS_Rx_COL) 2072 ifp->if_collisions++; 2073 2074 /* 2075 * If an error occurred, update stats, clear the status 2076 * word, and leave the packet buffer in place. It will 2077 * simply be reused the next time the ring comes around. 2078 */ 2079 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2080 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2081 ifp->if_ierrors++; 2082 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2083 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2084 /* Receive overrun handled elsewhere. */ 2085 printf("%s: receive descriptor error\n", 2086 sc->sc_dev.dv_xname); 2087 } 2088 #define PRINTERR(bit, str) \ 2089 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2090 (cmdsts & (bit)) != 0) \ 2091 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 2092 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2093 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2094 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2095 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2096 #undef PRINTERR 2097 SIP_INIT_RXDESC(sc, i); 2098 continue; 2099 } 2100 2101 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2102 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2103 2104 /* 2105 * No errors; receive the packet. Note, the SiS 900 2106 * includes the CRC with every packet. 2107 */ 2108 len = CMDSTS_SIZE(cmdsts) - ETHER_CRC_LEN; 2109 2110 #ifdef __NO_STRICT_ALIGNMENT 2111 /* 2112 * If the packet is small enough to fit in a 2113 * single header mbuf, allocate one and copy 2114 * the data into it. This greatly reduces 2115 * memory consumption when we receive lots 2116 * of small packets. 2117 * 2118 * Otherwise, we add a new buffer to the receive 2119 * chain. If this fails, we drop the packet and 2120 * recycle the old buffer. 2121 */ 2122 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 2123 MGETHDR(m, M_DONTWAIT, MT_DATA); 2124 if (m == NULL) 2125 goto dropit; 2126 memcpy(mtod(m, caddr_t), 2127 mtod(rxs->rxs_mbuf, caddr_t), len); 2128 SIP_INIT_RXDESC(sc, i); 2129 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2130 rxs->rxs_dmamap->dm_mapsize, 2131 BUS_DMASYNC_PREREAD); 2132 } else { 2133 m = rxs->rxs_mbuf; 2134 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 2135 dropit: 2136 ifp->if_ierrors++; 2137 SIP_INIT_RXDESC(sc, i); 2138 bus_dmamap_sync(sc->sc_dmat, 2139 rxs->rxs_dmamap, 0, 2140 rxs->rxs_dmamap->dm_mapsize, 2141 BUS_DMASYNC_PREREAD); 2142 continue; 2143 } 2144 } 2145 #else 2146 /* 2147 * The SiS 900's receive buffers must be 4-byte aligned. 2148 * But this means that the data after the Ethernet header 2149 * is misaligned. We must allocate a new buffer and 2150 * copy the data, shifted forward 2 bytes. 2151 */ 2152 MGETHDR(m, M_DONTWAIT, MT_DATA); 2153 if (m == NULL) { 2154 dropit: 2155 ifp->if_ierrors++; 2156 SIP_INIT_RXDESC(sc, i); 2157 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2158 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2159 continue; 2160 } 2161 if (len > (MHLEN - 2)) { 2162 MCLGET(m, M_DONTWAIT); 2163 if ((m->m_flags & M_EXT) == 0) { 2164 m_freem(m); 2165 goto dropit; 2166 } 2167 } 2168 m->m_data += 2; 2169 2170 /* 2171 * Note that we use clusters for incoming frames, so the 2172 * buffer is virtually contiguous. 2173 */ 2174 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 2175 2176 /* Allow the receive descriptor to continue using its mbuf. */ 2177 SIP_INIT_RXDESC(sc, i); 2178 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2179 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2180 #endif /* __NO_STRICT_ALIGNMENT */ 2181 2182 ifp->if_ipackets++; 2183 m->m_pkthdr.rcvif = ifp; 2184 m->m_pkthdr.len = m->m_len = len; 2185 2186 #if NBPFILTER > 0 2187 /* 2188 * Pass this up to any BPF listeners, but only 2189 * pass if up the stack if it's for us. 2190 */ 2191 if (ifp->if_bpf) 2192 bpf_mtap(ifp->if_bpf, m); 2193 #endif /* NBPFILTER > 0 */ 2194 2195 /* Pass it on. */ 2196 (*ifp->if_input)(ifp, m); 2197 } 2198 2199 /* Update the receive pointer. */ 2200 sc->sc_rxptr = i; 2201 } 2202 #endif /* DP83820 */ 2203 2204 /* 2205 * sip_tick: 2206 * 2207 * One second timer, used to tick the MII. 2208 */ 2209 static void 2210 SIP_DECL(tick)(void *arg) 2211 { 2212 struct sip_softc *sc = arg; 2213 int s; 2214 2215 s = splnet(); 2216 #ifdef DP83820 2217 #ifdef SIP_EVENT_COUNTERS 2218 /* Read PAUSE related counts from MIB registers. */ 2219 sc->sc_ev_rxpause.ev_count += 2220 bus_space_read_4(sc->sc_st, sc->sc_sh, 2221 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2222 sc->sc_ev_txpause.ev_count += 2223 bus_space_read_4(sc->sc_st, sc->sc_sh, 2224 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2225 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2226 #endif /* SIP_EVENT_COUNTERS */ 2227 #endif /* DP83820 */ 2228 mii_tick(&sc->sc_mii); 2229 splx(s); 2230 2231 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2232 } 2233 2234 /* 2235 * sip_reset: 2236 * 2237 * Perform a soft reset on the SiS 900. 2238 */ 2239 static void 2240 SIP_DECL(reset)(struct sip_softc *sc) 2241 { 2242 bus_space_tag_t st = sc->sc_st; 2243 bus_space_handle_t sh = sc->sc_sh; 2244 int i; 2245 2246 bus_space_write_4(st, sh, SIP_IER, 0); 2247 bus_space_write_4(st, sh, SIP_IMR, 0); 2248 bus_space_write_4(st, sh, SIP_RFCR, 0); 2249 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2250 2251 for (i = 0; i < SIP_TIMEOUT; i++) { 2252 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2253 break; 2254 delay(2); 2255 } 2256 2257 if (i == SIP_TIMEOUT) 2258 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2259 2260 delay(1000); 2261 2262 #ifdef DP83820 2263 /* 2264 * Set the general purpose I/O bits. Do it here in case we 2265 * need to have GPIO set up to talk to the media interface. 2266 */ 2267 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2268 delay(1000); 2269 #endif /* DP83820 */ 2270 } 2271 2272 /* 2273 * sip_init: [ ifnet interface function ] 2274 * 2275 * Initialize the interface. Must be called at splnet(). 2276 */ 2277 static int 2278 SIP_DECL(init)(struct ifnet *ifp) 2279 { 2280 struct sip_softc *sc = ifp->if_softc; 2281 bus_space_tag_t st = sc->sc_st; 2282 bus_space_handle_t sh = sc->sc_sh; 2283 struct sip_txsoft *txs; 2284 struct sip_rxsoft *rxs; 2285 struct sip_desc *sipd; 2286 #if defined(DP83820) 2287 u_int32_t reg; 2288 #endif 2289 int i, error = 0; 2290 2291 /* 2292 * Cancel any pending I/O. 2293 */ 2294 SIP_DECL(stop)(ifp, 0); 2295 2296 /* 2297 * Reset the chip to a known state. 2298 */ 2299 SIP_DECL(reset)(sc); 2300 2301 #if !defined(DP83820) 2302 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2303 /* 2304 * DP83815 manual, page 78: 2305 * 4.4 Recommended Registers Configuration 2306 * For optimum performance of the DP83815, version noted 2307 * as DP83815CVNG (SRR = 203h), the listed register 2308 * modifications must be followed in sequence... 2309 * 2310 * It's not clear if this should be 302h or 203h because that 2311 * chip name is listed as SRR 302h in the description of the 2312 * SRR register. However, my revision 302h DP83815 on the 2313 * Netgear FA311 purchased in 02/2001 needs these settings 2314 * to avoid tons of errors in AcceptPerfectMatch (non- 2315 * IFF_PROMISC) mode. I do not know if other revisions need 2316 * this set or not. [briggs -- 09 March 2001] 2317 * 2318 * Note that only the low-order 12 bits of 0xe4 are documented 2319 * and that this sets reserved bits in that register. 2320 */ 2321 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2322 2323 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2324 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2325 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2326 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2327 2328 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2329 } 2330 #endif /* ! DP83820 */ 2331 2332 /* 2333 * Initialize the transmit descriptor ring. 2334 */ 2335 for (i = 0; i < SIP_NTXDESC; i++) { 2336 sipd = &sc->sc_txdescs[i]; 2337 memset(sipd, 0, sizeof(struct sip_desc)); 2338 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2339 } 2340 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2341 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2342 sc->sc_txfree = SIP_NTXDESC; 2343 sc->sc_txnext = 0; 2344 sc->sc_txwin = 0; 2345 2346 /* 2347 * Initialize the transmit job descriptors. 2348 */ 2349 SIMPLEQ_INIT(&sc->sc_txfreeq); 2350 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2351 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2352 txs = &sc->sc_txsoft[i]; 2353 txs->txs_mbuf = NULL; 2354 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2355 } 2356 2357 /* 2358 * Initialize the receive descriptor and receive job 2359 * descriptor rings. 2360 */ 2361 for (i = 0; i < SIP_NRXDESC; i++) { 2362 rxs = &sc->sc_rxsoft[i]; 2363 if (rxs->rxs_mbuf == NULL) { 2364 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2365 printf("%s: unable to allocate or map rx " 2366 "buffer %d, error = %d\n", 2367 sc->sc_dev.dv_xname, i, error); 2368 /* 2369 * XXX Should attempt to run with fewer receive 2370 * XXX buffers instead of just failing. 2371 */ 2372 SIP_DECL(rxdrain)(sc); 2373 goto out; 2374 } 2375 } else 2376 SIP_INIT_RXDESC(sc, i); 2377 } 2378 sc->sc_rxptr = 0; 2379 #ifdef DP83820 2380 sc->sc_rxdiscard = 0; 2381 SIP_RXCHAIN_RESET(sc); 2382 #endif /* DP83820 */ 2383 2384 /* 2385 * Set the configuration register; it's already initialized 2386 * in sip_attach(). 2387 */ 2388 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2389 2390 /* 2391 * Initialize the prototype TXCFG register. 2392 */ 2393 #if defined(DP83820) 2394 sc->sc_txcfg = TXCFG_MXDMA_512; 2395 sc->sc_rxcfg = RXCFG_MXDMA_512; 2396 #else 2397 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2398 SIP_SIS900_REV(sc, SIS_REV_960) || 2399 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2400 (sc->sc_cfg & CFG_EDBMASTEN)) { 2401 sc->sc_txcfg = TXCFG_MXDMA_64; 2402 sc->sc_rxcfg = RXCFG_MXDMA_64; 2403 } else { 2404 sc->sc_txcfg = TXCFG_MXDMA_512; 2405 sc->sc_rxcfg = RXCFG_MXDMA_512; 2406 } 2407 #endif /* DP83820 */ 2408 2409 sc->sc_txcfg |= TXCFG_ATP | 2410 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2411 sc->sc_tx_drain_thresh; 2412 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2413 2414 /* 2415 * Initialize the receive drain threshold if we have never 2416 * done so. 2417 */ 2418 if (sc->sc_rx_drain_thresh == 0) { 2419 /* 2420 * XXX This value should be tuned. This is set to the 2421 * maximum of 248 bytes, and we may be able to improve 2422 * performance by decreasing it (although we should never 2423 * set this value lower than 2; 14 bytes are required to 2424 * filter the packet). 2425 */ 2426 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2427 } 2428 2429 /* 2430 * Initialize the prototype RXCFG register. 2431 */ 2432 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2433 #ifdef DP83820 2434 /* 2435 * Accept long packets (including FCS) so we can handle 2436 * 802.1q-tagged frames and jumbo frames properly. 2437 */ 2438 if (ifp->if_mtu > ETHERMTU || 2439 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2440 sc->sc_rxcfg |= RXCFG_ALP; 2441 2442 /* 2443 * Checksum offloading is disabled if the user selects an MTU 2444 * larger than 8109. (FreeBSD says 8152, but there is emperical 2445 * evidence that >8109 does not work on some boards, such as the 2446 * Planex GN-1000TE). 2447 */ 2448 if (ifp->if_mtu > 8109 && 2449 (ifp->if_capenable & 2450 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4))) { 2451 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2452 "disabled.\n", sc->sc_dev.dv_xname); 2453 ifp->if_capenable &= ~(IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4| 2454 IFCAP_CSUM_UDPv4); 2455 ifp->if_csum_flags_tx = 0; 2456 ifp->if_csum_flags_rx = 0; 2457 } 2458 #else 2459 /* 2460 * Accept packets >1518 bytes (including FCS) so we can handle 2461 * 802.1q-tagged frames properly. 2462 */ 2463 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2464 sc->sc_rxcfg |= RXCFG_ALP; 2465 #endif 2466 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2467 2468 #ifdef DP83820 2469 /* 2470 * Initialize the VLAN/IP receive control register. 2471 * We enable checksum computation on all incoming 2472 * packets, and do not reject packets w/ bad checksums. 2473 */ 2474 reg = 0; 2475 if (ifp->if_capenable & 2476 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2477 reg |= VRCR_IPEN; 2478 if (sc->sc_ethercom.ec_nvlans != 0) 2479 reg |= VRCR_VTDEN|VRCR_VTREN; 2480 bus_space_write_4(st, sh, SIP_VRCR, reg); 2481 2482 /* 2483 * Initialize the VLAN/IP transmit control register. 2484 * We enable outgoing checksum computation on a 2485 * per-packet basis. 2486 */ 2487 reg = 0; 2488 if (ifp->if_capenable & 2489 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2490 reg |= VTCR_PPCHK; 2491 if (sc->sc_ethercom.ec_nvlans != 0) 2492 reg |= VTCR_VPPTI; 2493 bus_space_write_4(st, sh, SIP_VTCR, reg); 2494 2495 /* 2496 * If we're using VLANs, initialize the VLAN data register. 2497 * To understand why we bswap the VLAN Ethertype, see section 2498 * 4.2.36 of the DP83820 manual. 2499 */ 2500 if (sc->sc_ethercom.ec_nvlans != 0) 2501 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2502 #endif /* DP83820 */ 2503 2504 /* 2505 * Give the transmit and receive rings to the chip. 2506 */ 2507 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2508 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2509 2510 /* 2511 * Initialize the interrupt mask. 2512 */ 2513 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2514 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2515 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2516 2517 /* Set up the receive filter. */ 2518 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2519 2520 #ifdef DP83820 2521 /* 2522 * Tune sc_rx_flow_thresh. 2523 * XXX "More than 8KB" is too short for jumbo frames. 2524 * XXX TODO: Threshold value should be user-settable. 2525 */ 2526 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2527 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2528 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2529 #endif 2530 2531 /* 2532 * Set the current media. Do this after initializing the prototype 2533 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2534 * control. 2535 */ 2536 mii_mediachg(&sc->sc_mii); 2537 2538 #ifdef DP83820 2539 /* 2540 * Set the interrupt hold-off timer to 100us. 2541 */ 2542 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2543 #endif 2544 2545 /* 2546 * Enable interrupts. 2547 */ 2548 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2549 2550 /* 2551 * Start the transmit and receive processes. 2552 */ 2553 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2554 2555 /* 2556 * Start the one second MII clock. 2557 */ 2558 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2559 2560 /* 2561 * ...all done! 2562 */ 2563 ifp->if_flags |= IFF_RUNNING; 2564 ifp->if_flags &= ~IFF_OACTIVE; 2565 sc->sc_if_flags = ifp->if_flags; 2566 2567 out: 2568 if (error) 2569 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2570 return (error); 2571 } 2572 2573 /* 2574 * sip_drain: 2575 * 2576 * Drain the receive queue. 2577 */ 2578 static void 2579 SIP_DECL(rxdrain)(struct sip_softc *sc) 2580 { 2581 struct sip_rxsoft *rxs; 2582 int i; 2583 2584 for (i = 0; i < SIP_NRXDESC; i++) { 2585 rxs = &sc->sc_rxsoft[i]; 2586 if (rxs->rxs_mbuf != NULL) { 2587 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2588 m_freem(rxs->rxs_mbuf); 2589 rxs->rxs_mbuf = NULL; 2590 } 2591 } 2592 } 2593 2594 /* 2595 * sip_stop: [ ifnet interface function ] 2596 * 2597 * Stop transmission on the interface. 2598 */ 2599 static void 2600 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2601 { 2602 struct sip_softc *sc = ifp->if_softc; 2603 bus_space_tag_t st = sc->sc_st; 2604 bus_space_handle_t sh = sc->sc_sh; 2605 struct sip_txsoft *txs; 2606 u_int32_t cmdsts = 0; /* DEBUG */ 2607 2608 /* 2609 * Stop the one second clock. 2610 */ 2611 callout_stop(&sc->sc_tick_ch); 2612 2613 /* Down the MII. */ 2614 mii_down(&sc->sc_mii); 2615 2616 /* 2617 * Disable interrupts. 2618 */ 2619 bus_space_write_4(st, sh, SIP_IER, 0); 2620 2621 /* 2622 * Stop receiver and transmitter. 2623 */ 2624 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2625 2626 /* 2627 * Release any queued transmit buffers. 2628 */ 2629 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2630 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2631 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2632 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2633 CMDSTS_INTR) == 0) 2634 printf("%s: sip_stop: last descriptor does not " 2635 "have INTR bit set\n", sc->sc_dev.dv_xname); 2636 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2637 #ifdef DIAGNOSTIC 2638 if (txs->txs_mbuf == NULL) { 2639 printf("%s: dirty txsoft with no mbuf chain\n", 2640 sc->sc_dev.dv_xname); 2641 panic("sip_stop"); 2642 } 2643 #endif 2644 cmdsts |= /* DEBUG */ 2645 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2646 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2647 m_freem(txs->txs_mbuf); 2648 txs->txs_mbuf = NULL; 2649 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2650 } 2651 2652 if (disable) 2653 SIP_DECL(rxdrain)(sc); 2654 2655 /* 2656 * Mark the interface down and cancel the watchdog timer. 2657 */ 2658 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2659 ifp->if_timer = 0; 2660 2661 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2662 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2663 printf("%s: sip_stop: no INTR bits set in dirty tx " 2664 "descriptors\n", sc->sc_dev.dv_xname); 2665 } 2666 2667 /* 2668 * sip_read_eeprom: 2669 * 2670 * Read data from the serial EEPROM. 2671 */ 2672 static void 2673 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2674 u_int16_t *data) 2675 { 2676 bus_space_tag_t st = sc->sc_st; 2677 bus_space_handle_t sh = sc->sc_sh; 2678 u_int16_t reg; 2679 int i, x; 2680 2681 for (i = 0; i < wordcnt; i++) { 2682 /* Send CHIP SELECT. */ 2683 reg = EROMAR_EECS; 2684 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2685 2686 /* Shift in the READ opcode. */ 2687 for (x = 3; x > 0; x--) { 2688 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2689 reg |= EROMAR_EEDI; 2690 else 2691 reg &= ~EROMAR_EEDI; 2692 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2693 bus_space_write_4(st, sh, SIP_EROMAR, 2694 reg | EROMAR_EESK); 2695 delay(4); 2696 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2697 delay(4); 2698 } 2699 2700 /* Shift in address. */ 2701 for (x = 6; x > 0; x--) { 2702 if ((word + i) & (1 << (x - 1))) 2703 reg |= EROMAR_EEDI; 2704 else 2705 reg &= ~EROMAR_EEDI; 2706 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2707 bus_space_write_4(st, sh, SIP_EROMAR, 2708 reg | EROMAR_EESK); 2709 delay(4); 2710 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2711 delay(4); 2712 } 2713 2714 /* Shift out data. */ 2715 reg = EROMAR_EECS; 2716 data[i] = 0; 2717 for (x = 16; x > 0; x--) { 2718 bus_space_write_4(st, sh, SIP_EROMAR, 2719 reg | EROMAR_EESK); 2720 delay(4); 2721 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2722 data[i] |= (1 << (x - 1)); 2723 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2724 delay(4); 2725 } 2726 2727 /* Clear CHIP SELECT. */ 2728 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2729 delay(4); 2730 } 2731 } 2732 2733 /* 2734 * sip_add_rxbuf: 2735 * 2736 * Add a receive buffer to the indicated descriptor. 2737 */ 2738 static int 2739 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2740 { 2741 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2742 struct mbuf *m; 2743 int error; 2744 2745 MGETHDR(m, M_DONTWAIT, MT_DATA); 2746 if (m == NULL) 2747 return (ENOBUFS); 2748 2749 MCLGET(m, M_DONTWAIT); 2750 if ((m->m_flags & M_EXT) == 0) { 2751 m_freem(m); 2752 return (ENOBUFS); 2753 } 2754 2755 #if defined(DP83820) 2756 m->m_len = SIP_RXBUF_LEN; 2757 #endif /* DP83820 */ 2758 2759 if (rxs->rxs_mbuf != NULL) 2760 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2761 2762 rxs->rxs_mbuf = m; 2763 2764 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2765 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2766 BUS_DMA_READ|BUS_DMA_NOWAIT); 2767 if (error) { 2768 printf("%s: can't load rx DMA map %d, error = %d\n", 2769 sc->sc_dev.dv_xname, idx, error); 2770 panic("sip_add_rxbuf"); /* XXX */ 2771 } 2772 2773 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2774 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2775 2776 SIP_INIT_RXDESC(sc, idx); 2777 2778 return (0); 2779 } 2780 2781 #if !defined(DP83820) 2782 /* 2783 * sip_sis900_set_filter: 2784 * 2785 * Set up the receive filter. 2786 */ 2787 static void 2788 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2789 { 2790 bus_space_tag_t st = sc->sc_st; 2791 bus_space_handle_t sh = sc->sc_sh; 2792 struct ethercom *ec = &sc->sc_ethercom; 2793 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2794 struct ether_multi *enm; 2795 u_int8_t *cp; 2796 struct ether_multistep step; 2797 u_int32_t crc, mchash[16]; 2798 2799 /* 2800 * Initialize the prototype RFCR. 2801 */ 2802 sc->sc_rfcr = RFCR_RFEN; 2803 if (ifp->if_flags & IFF_BROADCAST) 2804 sc->sc_rfcr |= RFCR_AAB; 2805 if (ifp->if_flags & IFF_PROMISC) { 2806 sc->sc_rfcr |= RFCR_AAP; 2807 goto allmulti; 2808 } 2809 2810 /* 2811 * Set up the multicast address filter by passing all multicast 2812 * addresses through a CRC generator, and then using the high-order 2813 * 6 bits as an index into the 128 bit multicast hash table (only 2814 * the lower 16 bits of each 32 bit multicast hash register are 2815 * valid). The high order bits select the register, while the 2816 * rest of the bits select the bit within the register. 2817 */ 2818 2819 memset(mchash, 0, sizeof(mchash)); 2820 2821 /* 2822 * SiS900 (at least SiS963) requires us to register the address of 2823 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 2824 */ 2825 crc = 0x0ed423f9; 2826 2827 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2828 SIP_SIS900_REV(sc, SIS_REV_960) || 2829 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2830 /* Just want the 8 most significant bits. */ 2831 crc >>= 24; 2832 } else { 2833 /* Just want the 7 most significant bits. */ 2834 crc >>= 25; 2835 } 2836 2837 /* Set the corresponding bit in the hash table. */ 2838 mchash[crc >> 4] |= 1 << (crc & 0xf); 2839 2840 ETHER_FIRST_MULTI(step, ec, enm); 2841 while (enm != NULL) { 2842 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2843 /* 2844 * We must listen to a range of multicast addresses. 2845 * For now, just accept all multicasts, rather than 2846 * trying to set only those filter bits needed to match 2847 * the range. (At this time, the only use of address 2848 * ranges is for IP multicast routing, for which the 2849 * range is big enough to require all bits set.) 2850 */ 2851 goto allmulti; 2852 } 2853 2854 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2855 2856 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2857 SIP_SIS900_REV(sc, SIS_REV_960) || 2858 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2859 /* Just want the 8 most significant bits. */ 2860 crc >>= 24; 2861 } else { 2862 /* Just want the 7 most significant bits. */ 2863 crc >>= 25; 2864 } 2865 2866 /* Set the corresponding bit in the hash table. */ 2867 mchash[crc >> 4] |= 1 << (crc & 0xf); 2868 2869 ETHER_NEXT_MULTI(step, enm); 2870 } 2871 2872 ifp->if_flags &= ~IFF_ALLMULTI; 2873 goto setit; 2874 2875 allmulti: 2876 ifp->if_flags |= IFF_ALLMULTI; 2877 sc->sc_rfcr |= RFCR_AAM; 2878 2879 setit: 2880 #define FILTER_EMIT(addr, data) \ 2881 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2882 delay(1); \ 2883 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2884 delay(1) 2885 2886 /* 2887 * Disable receive filter, and program the node address. 2888 */ 2889 cp = LLADDR(ifp->if_sadl); 2890 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2891 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2892 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2893 2894 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2895 /* 2896 * Program the multicast hash table. 2897 */ 2898 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2899 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2900 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2901 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2902 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2903 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2904 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2905 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2906 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2907 SIP_SIS900_REV(sc, SIS_REV_960) || 2908 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2909 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2910 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2911 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2912 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2913 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2914 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2915 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2916 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2917 } 2918 } 2919 #undef FILTER_EMIT 2920 2921 /* 2922 * Re-enable the receiver filter. 2923 */ 2924 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2925 } 2926 #endif /* ! DP83820 */ 2927 2928 /* 2929 * sip_dp83815_set_filter: 2930 * 2931 * Set up the receive filter. 2932 */ 2933 static void 2934 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2935 { 2936 bus_space_tag_t st = sc->sc_st; 2937 bus_space_handle_t sh = sc->sc_sh; 2938 struct ethercom *ec = &sc->sc_ethercom; 2939 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2940 struct ether_multi *enm; 2941 u_int8_t *cp; 2942 struct ether_multistep step; 2943 u_int32_t crc, hash, slot, bit; 2944 #ifdef DP83820 2945 #define MCHASH_NWORDS 128 2946 #else 2947 #define MCHASH_NWORDS 32 2948 #endif /* DP83820 */ 2949 u_int16_t mchash[MCHASH_NWORDS]; 2950 int i; 2951 2952 /* 2953 * Initialize the prototype RFCR. 2954 * Enable the receive filter, and accept on 2955 * Perfect (destination address) Match 2956 * If IFF_BROADCAST, also accept all broadcast packets. 2957 * If IFF_PROMISC, accept all unicast packets (and later, set 2958 * IFF_ALLMULTI and accept all multicast, too). 2959 */ 2960 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2961 if (ifp->if_flags & IFF_BROADCAST) 2962 sc->sc_rfcr |= RFCR_AAB; 2963 if (ifp->if_flags & IFF_PROMISC) { 2964 sc->sc_rfcr |= RFCR_AAP; 2965 goto allmulti; 2966 } 2967 2968 #ifdef DP83820 2969 /* 2970 * Set up the DP83820 multicast address filter by passing all multicast 2971 * addresses through a CRC generator, and then using the high-order 2972 * 11 bits as an index into the 2048 bit multicast hash table. The 2973 * high-order 7 bits select the slot, while the low-order 4 bits 2974 * select the bit within the slot. Note that only the low 16-bits 2975 * of each filter word are used, and there are 128 filter words. 2976 */ 2977 #else 2978 /* 2979 * Set up the DP83815 multicast address filter by passing all multicast 2980 * addresses through a CRC generator, and then using the high-order 2981 * 9 bits as an index into the 512 bit multicast hash table. The 2982 * high-order 5 bits select the slot, while the low-order 4 bits 2983 * select the bit within the slot. Note that only the low 16-bits 2984 * of each filter word are used, and there are 32 filter words. 2985 */ 2986 #endif /* DP83820 */ 2987 2988 memset(mchash, 0, sizeof(mchash)); 2989 2990 ifp->if_flags &= ~IFF_ALLMULTI; 2991 ETHER_FIRST_MULTI(step, ec, enm); 2992 if (enm == NULL) 2993 goto setit; 2994 while (enm != NULL) { 2995 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2996 /* 2997 * We must listen to a range of multicast addresses. 2998 * For now, just accept all multicasts, rather than 2999 * trying to set only those filter bits needed to match 3000 * the range. (At this time, the only use of address 3001 * ranges is for IP multicast routing, for which the 3002 * range is big enough to require all bits set.) 3003 */ 3004 goto allmulti; 3005 } 3006 3007 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3008 3009 #ifdef DP83820 3010 /* Just want the 11 most significant bits. */ 3011 hash = crc >> 21; 3012 #else 3013 /* Just want the 9 most significant bits. */ 3014 hash = crc >> 23; 3015 #endif /* DP83820 */ 3016 3017 slot = hash >> 4; 3018 bit = hash & 0xf; 3019 3020 /* Set the corresponding bit in the hash table. */ 3021 mchash[slot] |= 1 << bit; 3022 3023 ETHER_NEXT_MULTI(step, enm); 3024 } 3025 sc->sc_rfcr |= RFCR_MHEN; 3026 goto setit; 3027 3028 allmulti: 3029 ifp->if_flags |= IFF_ALLMULTI; 3030 sc->sc_rfcr |= RFCR_AAM; 3031 3032 setit: 3033 #define FILTER_EMIT(addr, data) \ 3034 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3035 delay(1); \ 3036 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3037 delay(1) 3038 3039 /* 3040 * Disable receive filter, and program the node address. 3041 */ 3042 cp = LLADDR(ifp->if_sadl); 3043 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3044 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3045 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3046 3047 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3048 /* 3049 * Program the multicast hash table. 3050 */ 3051 for (i = 0; i < MCHASH_NWORDS; i++) { 3052 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 3053 mchash[i]); 3054 } 3055 } 3056 #undef FILTER_EMIT 3057 #undef MCHASH_NWORDS 3058 3059 /* 3060 * Re-enable the receiver filter. 3061 */ 3062 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3063 } 3064 3065 #if defined(DP83820) 3066 /* 3067 * sip_dp83820_mii_readreg: [mii interface function] 3068 * 3069 * Read a PHY register on the MII of the DP83820. 3070 */ 3071 static int 3072 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 3073 { 3074 struct sip_softc *sc = (void *) self; 3075 3076 if (sc->sc_cfg & CFG_TBI_EN) { 3077 bus_addr_t tbireg; 3078 int rv; 3079 3080 if (phy != 0) 3081 return (0); 3082 3083 switch (reg) { 3084 case MII_BMCR: tbireg = SIP_TBICR; break; 3085 case MII_BMSR: tbireg = SIP_TBISR; break; 3086 case MII_ANAR: tbireg = SIP_TANAR; break; 3087 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3088 case MII_ANER: tbireg = SIP_TANER; break; 3089 case MII_EXTSR: 3090 /* 3091 * Don't even bother reading the TESR register. 3092 * The manual documents that the device has 3093 * 1000baseX full/half capability, but the 3094 * register itself seems read back 0 on some 3095 * boards. Just hard-code the result. 3096 */ 3097 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3098 3099 default: 3100 return (0); 3101 } 3102 3103 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3104 if (tbireg == SIP_TBISR) { 3105 /* LINK and ACOMP are switched! */ 3106 int val = rv; 3107 3108 rv = 0; 3109 if (val & TBISR_MR_LINK_STATUS) 3110 rv |= BMSR_LINK; 3111 if (val & TBISR_MR_AN_COMPLETE) 3112 rv |= BMSR_ACOMP; 3113 3114 /* 3115 * The manual claims this register reads back 0 3116 * on hard and soft reset. But we want to let 3117 * the gentbi driver know that we support auto- 3118 * negotiation, so hard-code this bit in the 3119 * result. 3120 */ 3121 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3122 } 3123 3124 return (rv); 3125 } 3126 3127 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3128 phy, reg)); 3129 } 3130 3131 /* 3132 * sip_dp83820_mii_writereg: [mii interface function] 3133 * 3134 * Write a PHY register on the MII of the DP83820. 3135 */ 3136 static void 3137 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 3138 { 3139 struct sip_softc *sc = (void *) self; 3140 3141 if (sc->sc_cfg & CFG_TBI_EN) { 3142 bus_addr_t tbireg; 3143 3144 if (phy != 0) 3145 return; 3146 3147 switch (reg) { 3148 case MII_BMCR: tbireg = SIP_TBICR; break; 3149 case MII_ANAR: tbireg = SIP_TANAR; break; 3150 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3151 default: 3152 return; 3153 } 3154 3155 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3156 return; 3157 } 3158 3159 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3160 phy, reg, val); 3161 } 3162 3163 /* 3164 * sip_dp83820_mii_statchg: [mii interface function] 3165 * 3166 * Callback from MII layer when media changes. 3167 */ 3168 static void 3169 SIP_DECL(dp83820_mii_statchg)(struct device *self) 3170 { 3171 struct sip_softc *sc = (struct sip_softc *) self; 3172 struct mii_data *mii = &sc->sc_mii; 3173 u_int32_t cfg, pcr; 3174 3175 /* 3176 * Get flow control negotiation result. 3177 */ 3178 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3179 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3180 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3181 mii->mii_media_active &= ~IFM_ETH_FMASK; 3182 } 3183 3184 /* 3185 * Update TXCFG for full-duplex operation. 3186 */ 3187 if ((mii->mii_media_active & IFM_FDX) != 0) 3188 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3189 else 3190 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3191 3192 /* 3193 * Update RXCFG for full-duplex or loopback. 3194 */ 3195 if ((mii->mii_media_active & IFM_FDX) != 0 || 3196 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3197 sc->sc_rxcfg |= RXCFG_ATX; 3198 else 3199 sc->sc_rxcfg &= ~RXCFG_ATX; 3200 3201 /* 3202 * Update CFG for MII/GMII. 3203 */ 3204 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3205 cfg = sc->sc_cfg | CFG_MODE_1000; 3206 else 3207 cfg = sc->sc_cfg; 3208 3209 /* 3210 * 802.3x flow control. 3211 */ 3212 pcr = 0; 3213 if (sc->sc_flowflags & IFM_FLOW) { 3214 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3215 pcr |= sc->sc_rx_flow_thresh; 3216 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3217 pcr |= PCR_PSEN | PCR_PS_MCAST; 3218 } 3219 3220 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3221 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3222 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3223 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3224 } 3225 #endif /* ! DP83820 */ 3226 3227 /* 3228 * sip_mii_bitbang_read: [mii bit-bang interface function] 3229 * 3230 * Read the MII serial port for the MII bit-bang module. 3231 */ 3232 static u_int32_t 3233 SIP_DECL(mii_bitbang_read)(struct device *self) 3234 { 3235 struct sip_softc *sc = (void *) self; 3236 3237 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3238 } 3239 3240 /* 3241 * sip_mii_bitbang_write: [mii big-bang interface function] 3242 * 3243 * Write the MII serial port for the MII bit-bang module. 3244 */ 3245 static void 3246 SIP_DECL(mii_bitbang_write)(struct device *self, u_int32_t val) 3247 { 3248 struct sip_softc *sc = (void *) self; 3249 3250 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3251 } 3252 3253 #ifndef DP83820 3254 /* 3255 * sip_sis900_mii_readreg: [mii interface function] 3256 * 3257 * Read a PHY register on the MII. 3258 */ 3259 static int 3260 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 3261 { 3262 struct sip_softc *sc = (struct sip_softc *) self; 3263 u_int32_t enphy; 3264 3265 /* 3266 * The PHY of recent SiS chipsets is accessed through bitbang 3267 * operations. 3268 */ 3269 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3270 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3271 phy, reg)); 3272 3273 #ifndef SIS900_MII_RESTRICT 3274 /* 3275 * The SiS 900 has only an internal PHY on the MII. Only allow 3276 * MII address 0. 3277 */ 3278 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3279 return (0); 3280 #endif 3281 3282 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3283 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3284 ENPHY_RWCMD | ENPHY_ACCESS); 3285 do { 3286 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3287 } while (enphy & ENPHY_ACCESS); 3288 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3289 } 3290 3291 /* 3292 * sip_sis900_mii_writereg: [mii interface function] 3293 * 3294 * Write a PHY register on the MII. 3295 */ 3296 static void 3297 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 3298 { 3299 struct sip_softc *sc = (struct sip_softc *) self; 3300 u_int32_t enphy; 3301 3302 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3303 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3304 phy, reg, val); 3305 return; 3306 } 3307 3308 #ifndef SIS900_MII_RESTRICT 3309 /* 3310 * The SiS 900 has only an internal PHY on the MII. Only allow 3311 * MII address 0. 3312 */ 3313 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3314 return; 3315 #endif 3316 3317 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3318 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3319 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3320 do { 3321 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3322 } while (enphy & ENPHY_ACCESS); 3323 } 3324 3325 /* 3326 * sip_sis900_mii_statchg: [mii interface function] 3327 * 3328 * Callback from MII layer when media changes. 3329 */ 3330 static void 3331 SIP_DECL(sis900_mii_statchg)(struct device *self) 3332 { 3333 struct sip_softc *sc = (struct sip_softc *) self; 3334 struct mii_data *mii = &sc->sc_mii; 3335 u_int32_t flowctl; 3336 3337 /* 3338 * Get flow control negotiation result. 3339 */ 3340 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3341 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3342 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3343 mii->mii_media_active &= ~IFM_ETH_FMASK; 3344 } 3345 3346 /* 3347 * Update TXCFG for full-duplex operation. 3348 */ 3349 if ((mii->mii_media_active & IFM_FDX) != 0) 3350 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3351 else 3352 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3353 3354 /* 3355 * Update RXCFG for full-duplex or loopback. 3356 */ 3357 if ((mii->mii_media_active & IFM_FDX) != 0 || 3358 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3359 sc->sc_rxcfg |= RXCFG_ATX; 3360 else 3361 sc->sc_rxcfg &= ~RXCFG_ATX; 3362 3363 /* 3364 * Update IMR for use of 802.3x flow control. 3365 */ 3366 if (sc->sc_flowflags & IFM_FLOW) { 3367 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3368 flowctl = FLOWCTL_FLOWEN; 3369 } else { 3370 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3371 flowctl = 0; 3372 } 3373 3374 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3375 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3376 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3377 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3378 } 3379 3380 /* 3381 * sip_dp83815_mii_readreg: [mii interface function] 3382 * 3383 * Read a PHY register on the MII. 3384 */ 3385 static int 3386 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 3387 { 3388 struct sip_softc *sc = (struct sip_softc *) self; 3389 u_int32_t val; 3390 3391 /* 3392 * The DP83815 only has an internal PHY. Only allow 3393 * MII address 0. 3394 */ 3395 if (phy != 0) 3396 return (0); 3397 3398 /* 3399 * Apparently, after a reset, the DP83815 can take a while 3400 * to respond. During this recovery period, the BMSR returns 3401 * a value of 0. Catch this -- it's not supposed to happen 3402 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3403 * PHY to come back to life. 3404 * 3405 * This works out because the BMSR is the first register 3406 * read during the PHY probe process. 3407 */ 3408 do { 3409 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3410 } while (reg == MII_BMSR && val == 0); 3411 3412 return (val & 0xffff); 3413 } 3414 3415 /* 3416 * sip_dp83815_mii_writereg: [mii interface function] 3417 * 3418 * Write a PHY register to the MII. 3419 */ 3420 static void 3421 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3422 { 3423 struct sip_softc *sc = (struct sip_softc *) self; 3424 3425 /* 3426 * The DP83815 only has an internal PHY. Only allow 3427 * MII address 0. 3428 */ 3429 if (phy != 0) 3430 return; 3431 3432 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3433 } 3434 3435 /* 3436 * sip_dp83815_mii_statchg: [mii interface function] 3437 * 3438 * Callback from MII layer when media changes. 3439 */ 3440 static void 3441 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3442 { 3443 struct sip_softc *sc = (struct sip_softc *) self; 3444 3445 /* 3446 * Update TXCFG for full-duplex operation. 3447 */ 3448 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3449 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3450 else 3451 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3452 3453 /* 3454 * Update RXCFG for full-duplex or loopback. 3455 */ 3456 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3457 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3458 sc->sc_rxcfg |= RXCFG_ATX; 3459 else 3460 sc->sc_rxcfg &= ~RXCFG_ATX; 3461 3462 /* 3463 * XXX 802.3x flow control. 3464 */ 3465 3466 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3467 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3468 3469 /* 3470 * Some DP83815s experience problems when used with short 3471 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3472 * sequence adjusts the DSP's signal attenuation to fix the 3473 * problem. 3474 */ 3475 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3476 uint32_t reg; 3477 3478 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3479 3480 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3481 reg &= 0x0fff; 3482 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3483 delay(100); 3484 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3485 reg &= 0x00ff; 3486 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3487 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3488 0x00e8); 3489 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3490 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3491 reg | 0x20); 3492 } 3493 3494 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3495 } 3496 } 3497 #endif /* DP83820 */ 3498 3499 #if defined(DP83820) 3500 static void 3501 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3502 const struct pci_attach_args *pa, u_int8_t *enaddr) 3503 { 3504 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3505 u_int8_t cksum, *e, match; 3506 int i; 3507 3508 /* 3509 * EEPROM data format for the DP83820 can be found in 3510 * the DP83820 manual, section 4.2.4. 3511 */ 3512 3513 SIP_DECL(read_eeprom)(sc, 0, 3514 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3515 3516 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3517 match = ~(match - 1); 3518 3519 cksum = 0x55; 3520 e = (u_int8_t *) eeprom_data; 3521 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3522 cksum += *e++; 3523 3524 if (cksum != match) 3525 printf("%s: Checksum (%x) mismatch (%x)", 3526 sc->sc_dev.dv_xname, cksum, match); 3527 3528 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3529 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3530 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3531 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3532 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3533 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3534 } 3535 #else /* ! DP83820 */ 3536 static void 3537 SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc) 3538 { 3539 int i; 3540 3541 /* 3542 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3543 * a reason, but I don't know it. 3544 */ 3545 for (i = 0; i < 10; i++) 3546 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3547 } 3548 3549 static void 3550 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3551 const struct pci_attach_args *pa, u_int8_t *enaddr) 3552 { 3553 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3554 3555 switch (sc->sc_rev) { 3556 case SIS_REV_630S: 3557 case SIS_REV_630E: 3558 case SIS_REV_630EA1: 3559 case SIS_REV_630ET: 3560 case SIS_REV_635: 3561 /* 3562 * The MAC address for the on-board Ethernet of 3563 * the SiS 630 chipset is in the NVRAM. Kick 3564 * the chip into re-loading it from NVRAM, and 3565 * read the MAC address out of the filter registers. 3566 */ 3567 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3568 3569 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3570 RFCR_RFADDR_NODE0); 3571 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3572 0xffff; 3573 3574 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3575 RFCR_RFADDR_NODE2); 3576 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3577 0xffff; 3578 3579 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3580 RFCR_RFADDR_NODE4); 3581 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3582 0xffff; 3583 break; 3584 3585 case SIS_REV_960: 3586 { 3587 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3588 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3589 3590 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3591 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3592 3593 int waittime, i; 3594 3595 /* Allow to read EEPROM from LAN. It is shared 3596 * between a 1394 controller and the NIC and each 3597 * time we access it, we need to set SIS_EECMD_REQ. 3598 */ 3599 SIS_SET_EROMAR(sc, EROMAR_REQ); 3600 3601 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3602 /* Force EEPROM to idle state. */ 3603 3604 /* 3605 * XXX-cube This is ugly. I'll look for docs about it. 3606 */ 3607 SIS_SET_EROMAR(sc, EROMAR_EECS); 3608 SIP_DECL(sis900_eeprom_delay)(sc); 3609 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3610 SIS_SET_EROMAR(sc, EROMAR_EESK); 3611 SIP_DECL(sis900_eeprom_delay)(sc); 3612 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3613 SIP_DECL(sis900_eeprom_delay)(sc); 3614 } 3615 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3616 SIP_DECL(sis900_eeprom_delay)(sc); 3617 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3618 3619 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3620 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3621 sizeof(myea) / sizeof(myea[0]), myea); 3622 break; 3623 } 3624 DELAY(1); 3625 } 3626 3627 /* 3628 * Set SIS_EECTL_CLK to high, so a other master 3629 * can operate on the i2c bus. 3630 */ 3631 SIS_SET_EROMAR(sc, EROMAR_EESK); 3632 3633 /* Refuse EEPROM access by LAN */ 3634 SIS_SET_EROMAR(sc, EROMAR_DONE); 3635 } break; 3636 3637 default: 3638 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3639 sizeof(myea) / sizeof(myea[0]), myea); 3640 } 3641 3642 enaddr[0] = myea[0] & 0xff; 3643 enaddr[1] = myea[0] >> 8; 3644 enaddr[2] = myea[1] & 0xff; 3645 enaddr[3] = myea[1] >> 8; 3646 enaddr[4] = myea[2] & 0xff; 3647 enaddr[5] = myea[2] >> 8; 3648 } 3649 3650 /* Table and macro to bit-reverse an octet. */ 3651 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3652 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3653 3654 static void 3655 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3656 const struct pci_attach_args *pa, u_int8_t *enaddr) 3657 { 3658 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3659 u_int8_t cksum, *e, match; 3660 int i; 3661 3662 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3663 sizeof(eeprom_data[0]), eeprom_data); 3664 3665 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3666 match = ~(match - 1); 3667 3668 cksum = 0x55; 3669 e = (u_int8_t *) eeprom_data; 3670 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3671 cksum += *e++; 3672 } 3673 if (cksum != match) { 3674 printf("%s: Checksum (%x) mismatch (%x)", 3675 sc->sc_dev.dv_xname, cksum, match); 3676 } 3677 3678 /* 3679 * Unrolled because it makes slightly more sense this way. 3680 * The DP83815 stores the MAC address in bit 0 of word 6 3681 * through bit 15 of word 8. 3682 */ 3683 ea = &eeprom_data[6]; 3684 enaddr[0] = ((*ea & 0x1) << 7); 3685 ea++; 3686 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3687 enaddr[1] = ((*ea & 0x1FE) >> 1); 3688 enaddr[2] = ((*ea & 0x1) << 7); 3689 ea++; 3690 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3691 enaddr[3] = ((*ea & 0x1FE) >> 1); 3692 enaddr[4] = ((*ea & 0x1) << 7); 3693 ea++; 3694 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3695 enaddr[5] = ((*ea & 0x1FE) >> 1); 3696 3697 /* 3698 * In case that's not weird enough, we also need to reverse 3699 * the bits in each byte. This all actually makes more sense 3700 * if you think about the EEPROM storage as an array of bits 3701 * being shifted into bytes, but that's not how we're looking 3702 * at it here... 3703 */ 3704 for (i = 0; i < 6 ;i++) 3705 enaddr[i] = bbr(enaddr[i]); 3706 } 3707 #endif /* DP83820 */ 3708 3709 /* 3710 * sip_mediastatus: [ifmedia interface function] 3711 * 3712 * Get the current interface media status. 3713 */ 3714 static void 3715 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3716 { 3717 struct sip_softc *sc = ifp->if_softc; 3718 3719 mii_pollstat(&sc->sc_mii); 3720 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3721 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3722 sc->sc_flowflags; 3723 } 3724 3725 /* 3726 * sip_mediachange: [ifmedia interface function] 3727 * 3728 * Set hardware to newly-selected media. 3729 */ 3730 static int 3731 SIP_DECL(mediachange)(struct ifnet *ifp) 3732 { 3733 struct sip_softc *sc = ifp->if_softc; 3734 3735 if (ifp->if_flags & IFF_UP) 3736 mii_mediachg(&sc->sc_mii); 3737 return (0); 3738 } 3739
Indexes created Tue Sep 30 11:09:46 GMT 2025