if_sip.c revision 1.80
1 /* $NetBSD: if_sip.c,v 1.80 2003/08/25 20:36:47 itojun Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.80 2003/08/25 20:36:47 itojun Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <machine/bus.h> 116 #include <machine/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #ifdef DP83820 122 #include <dev/mii/mii_bitbang.h> 123 #endif /* DP83820 */ 124 125 #include <dev/pci/pcireg.h> 126 #include <dev/pci/pcivar.h> 127 #include <dev/pci/pcidevs.h> 128 129 #include <dev/pci/if_sipreg.h> 130 131 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 132 #define SIP_DECL(x) __CONCAT(gsip_,x) 133 #else /* SiS900 and DP83815 */ 134 #define SIP_DECL(x) __CONCAT(sip_,x) 135 #endif 136 137 #define SIP_STR(x) __STRING(SIP_DECL(x)) 138 139 /* 140 * Transmit descriptor list size. This is arbitrary, but allocate 141 * enough descriptors for 128 pending transmissions, and 8 segments 142 * per packet. This MUST work out to a power of 2. 143 */ 144 #define SIP_NTXSEGS 16 145 #define SIP_NTXSEGS_ALLOC 8 146 147 #define SIP_TXQUEUELEN 256 148 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 149 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 150 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 151 152 #if defined(DP83020) 153 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 154 #else 155 #define TX_DMAMAP_SIZE MCLBYTES 156 #endif 157 158 /* 159 * Receive descriptor list size. We have one Rx buffer per incoming 160 * packet, so this logic is a little simpler. 161 * 162 * Actually, on the DP83820, we allow the packet to consume more than 163 * one buffer, in order to support jumbo Ethernet frames. In that 164 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 165 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 166 * so we'd better be quick about handling receive interrupts. 167 */ 168 #if defined(DP83820) 169 #define SIP_NRXDESC 256 170 #else 171 #define SIP_NRXDESC 128 172 #endif /* DP83820 */ 173 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 174 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 175 176 /* 177 * Control structures are DMA'd to the SiS900 chip. We allocate them in 178 * a single clump that maps to a single DMA segment to make several things 179 * easier. 180 */ 181 struct sip_control_data { 182 /* 183 * The transmit descriptors. 184 */ 185 struct sip_desc scd_txdescs[SIP_NTXDESC]; 186 187 /* 188 * The receive descriptors. 189 */ 190 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 191 }; 192 193 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 194 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 195 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 196 197 /* 198 * Software state for transmit jobs. 199 */ 200 struct sip_txsoft { 201 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 202 bus_dmamap_t txs_dmamap; /* our DMA map */ 203 int txs_firstdesc; /* first descriptor in packet */ 204 int txs_lastdesc; /* last descriptor in packet */ 205 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 206 }; 207 208 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 209 210 /* 211 * Software state for receive jobs. 212 */ 213 struct sip_rxsoft { 214 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 215 bus_dmamap_t rxs_dmamap; /* our DMA map */ 216 }; 217 218 /* 219 * Software state per device. 220 */ 221 struct sip_softc { 222 struct device sc_dev; /* generic device information */ 223 bus_space_tag_t sc_st; /* bus space tag */ 224 bus_space_handle_t sc_sh; /* bus space handle */ 225 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 226 struct ethercom sc_ethercom; /* ethernet common data */ 227 void *sc_sdhook; /* shutdown hook */ 228 229 const struct sip_product *sc_model; /* which model are we? */ 230 int sc_rev; /* chip revision */ 231 232 void *sc_ih; /* interrupt cookie */ 233 234 struct mii_data sc_mii; /* MII/media information */ 235 236 struct callout sc_tick_ch; /* tick callout */ 237 238 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 239 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 240 241 /* 242 * Software state for transmit and receive descriptors. 243 */ 244 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 245 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 246 247 /* 248 * Control data structures. 249 */ 250 struct sip_control_data *sc_control_data; 251 #define sc_txdescs sc_control_data->scd_txdescs 252 #define sc_rxdescs sc_control_data->scd_rxdescs 253 254 #ifdef SIP_EVENT_COUNTERS 255 /* 256 * Event counters. 257 */ 258 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 259 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 260 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 261 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 262 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 263 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 264 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 265 #ifdef DP83820 266 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 267 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 268 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 269 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 270 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 271 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 272 #endif /* DP83820 */ 273 #endif /* SIP_EVENT_COUNTERS */ 274 275 u_int32_t sc_txcfg; /* prototype TXCFG register */ 276 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 277 u_int32_t sc_imr; /* prototype IMR register */ 278 u_int32_t sc_rfcr; /* prototype RFCR register */ 279 280 u_int32_t sc_cfg; /* prototype CFG register */ 281 282 #ifdef DP83820 283 u_int32_t sc_gpior; /* prototype GPIOR register */ 284 #endif /* DP83820 */ 285 286 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 287 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 288 289 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 290 291 int sc_flags; /* misc. flags; see below */ 292 293 int sc_txfree; /* number of free Tx descriptors */ 294 int sc_txnext; /* next ready Tx descriptor */ 295 int sc_txwin; /* Tx descriptors since last intr */ 296 297 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 298 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 299 300 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 301 #if defined(DP83820) 302 int sc_rxdiscard; 303 int sc_rxlen; 304 struct mbuf *sc_rxhead; 305 struct mbuf *sc_rxtail; 306 struct mbuf **sc_rxtailp; 307 #endif /* DP83820 */ 308 309 #if NRND > 0 310 rndsource_element_t rnd_source; /* random source */ 311 #endif 312 }; 313 314 /* sc_flags */ 315 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 316 317 #ifdef DP83820 318 #define SIP_RXCHAIN_RESET(sc) \ 319 do { \ 320 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 321 *(sc)->sc_rxtailp = NULL; \ 322 (sc)->sc_rxlen = 0; \ 323 } while (/*CONSTCOND*/0) 324 325 #define SIP_RXCHAIN_LINK(sc, m) \ 326 do { \ 327 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 328 (sc)->sc_rxtailp = &(m)->m_next; \ 329 } while (/*CONSTCOND*/0) 330 #endif /* DP83820 */ 331 332 #ifdef SIP_EVENT_COUNTERS 333 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 334 #else 335 #define SIP_EVCNT_INCR(ev) /* nothing */ 336 #endif 337 338 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 339 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 340 341 #define SIP_CDTXSYNC(sc, x, n, ops) \ 342 do { \ 343 int __x, __n; \ 344 \ 345 __x = (x); \ 346 __n = (n); \ 347 \ 348 /* If it will wrap around, sync to the end of the ring. */ \ 349 if ((__x + __n) > SIP_NTXDESC) { \ 350 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 351 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 352 (SIP_NTXDESC - __x), (ops)); \ 353 __n -= (SIP_NTXDESC - __x); \ 354 __x = 0; \ 355 } \ 356 \ 357 /* Now sync whatever is left. */ \ 358 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 359 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 360 } while (0) 361 362 #define SIP_CDRXSYNC(sc, x, ops) \ 363 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 364 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 365 366 #ifdef DP83820 367 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 368 #define SIP_RXBUF_LEN (MCLBYTES - 4) 369 #else 370 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 371 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 372 #endif 373 #define SIP_INIT_RXDESC(sc, x) \ 374 do { \ 375 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 376 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 377 \ 378 __sipd->sipd_link = \ 379 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 380 __sipd->sipd_bufptr = \ 381 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 382 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 383 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 384 SIP_INIT_RXDESC_EXTSTS \ 385 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 386 } while (0) 387 388 #define SIP_CHIP_VERS(sc, v, p, r) \ 389 ((sc)->sc_model->sip_vendor == (v) && \ 390 (sc)->sc_model->sip_product == (p) && \ 391 (sc)->sc_rev == (r)) 392 393 #define SIP_CHIP_MODEL(sc, v, p) \ 394 ((sc)->sc_model->sip_vendor == (v) && \ 395 (sc)->sc_model->sip_product == (p)) 396 397 #if !defined(DP83820) 398 #define SIP_SIS900_REV(sc, rev) \ 399 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 400 #endif 401 402 #define SIP_TIMEOUT 1000 403 404 void SIP_DECL(start)(struct ifnet *); 405 void SIP_DECL(watchdog)(struct ifnet *); 406 int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 407 int SIP_DECL(init)(struct ifnet *); 408 void SIP_DECL(stop)(struct ifnet *, int); 409 410 void SIP_DECL(shutdown)(void *); 411 412 void SIP_DECL(reset)(struct sip_softc *); 413 void SIP_DECL(rxdrain)(struct sip_softc *); 414 int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 415 void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, u_int16_t *); 416 void SIP_DECL(tick)(void *); 417 418 #if !defined(DP83820) 419 void SIP_DECL(sis900_set_filter)(struct sip_softc *); 420 #endif /* ! DP83820 */ 421 void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 422 423 #if defined(DP83820) 424 void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 425 const struct pci_attach_args *, u_int8_t *); 426 #else 427 void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 428 const struct pci_attach_args *, u_int8_t *); 429 void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 430 const struct pci_attach_args *, u_int8_t *); 431 #endif /* DP83820 */ 432 433 int SIP_DECL(intr)(void *); 434 void SIP_DECL(txintr)(struct sip_softc *); 435 void SIP_DECL(rxintr)(struct sip_softc *); 436 437 #if defined(DP83820) 438 int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 439 void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 440 void SIP_DECL(dp83820_mii_statchg)(struct device *); 441 #else 442 int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 443 void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 444 void SIP_DECL(sis900_mii_statchg)(struct device *); 445 446 int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 447 void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 448 void SIP_DECL(dp83815_mii_statchg)(struct device *); 449 #endif /* DP83820 */ 450 451 int SIP_DECL(mediachange)(struct ifnet *); 452 void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 453 454 int SIP_DECL(match)(struct device *, struct cfdata *, void *); 455 void SIP_DECL(attach)(struct device *, struct device *, void *); 456 457 int SIP_DECL(copy_small) = 0; 458 459 #ifdef DP83820 460 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 461 gsip_match, gsip_attach, NULL, NULL); 462 #else 463 CFATTACH_DECL(sip, sizeof(struct sip_softc), 464 sip_match, sip_attach, NULL, NULL); 465 #endif 466 467 /* 468 * Descriptions of the variants of the SiS900. 469 */ 470 struct sip_variant { 471 int (*sipv_mii_readreg)(struct device *, int, int); 472 void (*sipv_mii_writereg)(struct device *, int, int, int); 473 void (*sipv_mii_statchg)(struct device *); 474 void (*sipv_set_filter)(struct sip_softc *); 475 void (*sipv_read_macaddr)(struct sip_softc *, 476 const struct pci_attach_args *, u_int8_t *); 477 }; 478 479 #if defined(DP83820) 480 u_int32_t SIP_DECL(dp83820_mii_bitbang_read)(struct device *); 481 void SIP_DECL(dp83820_mii_bitbang_write)(struct device *, u_int32_t); 482 483 const struct mii_bitbang_ops SIP_DECL(dp83820_mii_bitbang_ops) = { 484 SIP_DECL(dp83820_mii_bitbang_read), 485 SIP_DECL(dp83820_mii_bitbang_write), 486 { 487 EROMAR_MDIO, /* MII_BIT_MDO */ 488 EROMAR_MDIO, /* MII_BIT_MDI */ 489 EROMAR_MDC, /* MII_BIT_MDC */ 490 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 491 0, /* MII_BIT_DIR_PHY_HOST */ 492 } 493 }; 494 #endif /* DP83820 */ 495 496 #if defined(DP83820) 497 const struct sip_variant SIP_DECL(variant_dp83820) = { 498 SIP_DECL(dp83820_mii_readreg), 499 SIP_DECL(dp83820_mii_writereg), 500 SIP_DECL(dp83820_mii_statchg), 501 SIP_DECL(dp83815_set_filter), 502 SIP_DECL(dp83820_read_macaddr), 503 }; 504 #else 505 const struct sip_variant SIP_DECL(variant_sis900) = { 506 SIP_DECL(sis900_mii_readreg), 507 SIP_DECL(sis900_mii_writereg), 508 SIP_DECL(sis900_mii_statchg), 509 SIP_DECL(sis900_set_filter), 510 SIP_DECL(sis900_read_macaddr), 511 }; 512 513 const struct sip_variant SIP_DECL(variant_dp83815) = { 514 SIP_DECL(dp83815_mii_readreg), 515 SIP_DECL(dp83815_mii_writereg), 516 SIP_DECL(dp83815_mii_statchg), 517 SIP_DECL(dp83815_set_filter), 518 SIP_DECL(dp83815_read_macaddr), 519 }; 520 #endif /* DP83820 */ 521 522 /* 523 * Devices supported by this driver. 524 */ 525 const struct sip_product { 526 pci_vendor_id_t sip_vendor; 527 pci_product_id_t sip_product; 528 const char *sip_name; 529 const struct sip_variant *sip_variant; 530 } SIP_DECL(products)[] = { 531 #if defined(DP83820) 532 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 533 "NatSemi DP83820 Gigabit Ethernet", 534 &SIP_DECL(variant_dp83820) }, 535 #else 536 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 537 "SiS 900 10/100 Ethernet", 538 &SIP_DECL(variant_sis900) }, 539 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 540 "SiS 7016 10/100 Ethernet", 541 &SIP_DECL(variant_sis900) }, 542 543 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 544 "NatSemi DP83815 10/100 Ethernet", 545 &SIP_DECL(variant_dp83815) }, 546 #endif /* DP83820 */ 547 548 { 0, 0, 549 NULL, 550 NULL }, 551 }; 552 553 static const struct sip_product * 554 SIP_DECL(lookup)(const struct pci_attach_args *pa) 555 { 556 const struct sip_product *sip; 557 558 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 559 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 560 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 561 return (sip); 562 } 563 return (NULL); 564 } 565 566 #ifdef DP83820 567 /* 568 * I really hate stupid hardware vendors. There's a bit in the EEPROM 569 * which indicates if the card can do 64-bit data transfers. Unfortunately, 570 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 571 * which means we try to use 64-bit data transfers on those cards if we 572 * happen to be plugged into a 32-bit slot. 573 * 574 * What we do is use this table of cards known to be 64-bit cards. If 575 * you have a 64-bit card who's subsystem ID is not listed in this table, 576 * send the output of "pcictl dump ..." of the device to me so that your 577 * card will use the 64-bit data path when plugged into a 64-bit slot. 578 * 579 * -- Jason R. Thorpe <thorpej (at) netbsd.org> 580 * June 30, 2002 581 */ 582 static int 583 SIP_DECL(check_64bit)(const struct pci_attach_args *pa) 584 { 585 static const struct { 586 pci_vendor_id_t c64_vendor; 587 pci_product_id_t c64_product; 588 } card64[] = { 589 /* Asante GigaNIX */ 590 { 0x128a, 0x0002 }, 591 592 /* Accton EN1407-T, Planex GN-1000TE */ 593 { 0x1113, 0x1407 }, 594 595 /* Netgear GA-621 */ 596 { 0x1385, 0x621a }, 597 598 /* SMC EZ Card */ 599 { 0x10b8, 0x9462 }, 600 601 { 0, 0} 602 }; 603 pcireg_t subsys; 604 int i; 605 606 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 607 608 for (i = 0; card64[i].c64_vendor != 0; i++) { 609 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 610 PCI_PRODUCT(subsys) == card64[i].c64_product) 611 return (1); 612 } 613 614 return (0); 615 } 616 #endif /* DP83820 */ 617 618 int 619 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 620 { 621 struct pci_attach_args *pa = aux; 622 623 if (SIP_DECL(lookup)(pa) != NULL) 624 return (1); 625 626 return (0); 627 } 628 629 void 630 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 631 { 632 struct sip_softc *sc = (struct sip_softc *) self; 633 struct pci_attach_args *pa = aux; 634 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 635 pci_chipset_tag_t pc = pa->pa_pc; 636 pci_intr_handle_t ih; 637 const char *intrstr = NULL; 638 bus_space_tag_t iot, memt; 639 bus_space_handle_t ioh, memh; 640 bus_dma_segment_t seg; 641 int ioh_valid, memh_valid; 642 int i, rseg, error; 643 const struct sip_product *sip; 644 pcireg_t pmode; 645 u_int8_t enaddr[ETHER_ADDR_LEN]; 646 int pmreg; 647 #ifdef DP83820 648 pcireg_t memtype; 649 u_int32_t reg; 650 #endif /* DP83820 */ 651 652 callout_init(&sc->sc_tick_ch); 653 654 sip = SIP_DECL(lookup)(pa); 655 if (sip == NULL) { 656 printf("\n"); 657 panic(SIP_STR(attach) ": impossible"); 658 } 659 sc->sc_rev = PCI_REVISION(pa->pa_class); 660 661 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 662 663 sc->sc_model = sip; 664 665 /* 666 * XXX Work-around broken PXE firmware on some boards. 667 * 668 * The DP83815 shares an address decoder with the MEM BAR 669 * and the ROM BAR. Make sure the ROM BAR is disabled, 670 * so that memory mapped access works. 671 */ 672 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 673 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 674 ~PCI_MAPREG_ROM_ENABLE); 675 676 /* 677 * Map the device. 678 */ 679 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 680 PCI_MAPREG_TYPE_IO, 0, 681 &iot, &ioh, NULL, NULL) == 0); 682 #ifdef DP83820 683 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 684 switch (memtype) { 685 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 686 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 687 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 688 memtype, 0, &memt, &memh, NULL, NULL) == 0); 689 break; 690 default: 691 memh_valid = 0; 692 } 693 #else 694 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 695 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 696 &memt, &memh, NULL, NULL) == 0); 697 #endif /* DP83820 */ 698 699 if (memh_valid) { 700 sc->sc_st = memt; 701 sc->sc_sh = memh; 702 } else if (ioh_valid) { 703 sc->sc_st = iot; 704 sc->sc_sh = ioh; 705 } else { 706 printf("%s: unable to map device registers\n", 707 sc->sc_dev.dv_xname); 708 return; 709 } 710 711 sc->sc_dmat = pa->pa_dmat; 712 713 /* 714 * Make sure bus mastering is enabled. Also make sure 715 * Write/Invalidate is enabled if we're allowed to use it. 716 */ 717 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 718 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 719 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 720 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 721 pmreg | PCI_COMMAND_MASTER_ENABLE); 722 723 /* Get it out of power save mode if needed. */ 724 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 725 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 726 PCI_PMCSR_STATE_MASK; 727 if (pmode == PCI_PMCSR_STATE_D3) { 728 /* 729 * The card has lost all configuration data in 730 * this state, so punt. 731 */ 732 printf("%s: unable to wake up from power state D3\n", 733 sc->sc_dev.dv_xname); 734 return; 735 } 736 if (pmode != PCI_PMCSR_STATE_D0) { 737 printf("%s: waking up from power state D%d\n", 738 sc->sc_dev.dv_xname, pmode); 739 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 740 PCI_PMCSR_STATE_D0); 741 } 742 } 743 744 /* 745 * Map and establish our interrupt. 746 */ 747 if (pci_intr_map(pa, &ih)) { 748 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 749 return; 750 } 751 intrstr = pci_intr_string(pc, ih); 752 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 753 if (sc->sc_ih == NULL) { 754 printf("%s: unable to establish interrupt", 755 sc->sc_dev.dv_xname); 756 if (intrstr != NULL) 757 printf(" at %s", intrstr); 758 printf("\n"); 759 return; 760 } 761 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 762 763 SIMPLEQ_INIT(&sc->sc_txfreeq); 764 SIMPLEQ_INIT(&sc->sc_txdirtyq); 765 766 /* 767 * Allocate the control data structures, and create and load the 768 * DMA map for it. 769 */ 770 if ((error = bus_dmamem_alloc(sc->sc_dmat, 771 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 772 0)) != 0) { 773 printf("%s: unable to allocate control data, error = %d\n", 774 sc->sc_dev.dv_xname, error); 775 goto fail_0; 776 } 777 778 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 779 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 780 BUS_DMA_COHERENT)) != 0) { 781 printf("%s: unable to map control data, error = %d\n", 782 sc->sc_dev.dv_xname, error); 783 goto fail_1; 784 } 785 786 if ((error = bus_dmamap_create(sc->sc_dmat, 787 sizeof(struct sip_control_data), 1, 788 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 789 printf("%s: unable to create control data DMA map, " 790 "error = %d\n", sc->sc_dev.dv_xname, error); 791 goto fail_2; 792 } 793 794 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 795 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 796 0)) != 0) { 797 printf("%s: unable to load control data DMA map, error = %d\n", 798 sc->sc_dev.dv_xname, error); 799 goto fail_3; 800 } 801 802 /* 803 * Create the transmit buffer DMA maps. 804 */ 805 for (i = 0; i < SIP_TXQUEUELEN; i++) { 806 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 807 SIP_NTXSEGS, MCLBYTES, 0, 0, 808 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 809 printf("%s: unable to create tx DMA map %d, " 810 "error = %d\n", sc->sc_dev.dv_xname, i, error); 811 goto fail_4; 812 } 813 } 814 815 /* 816 * Create the receive buffer DMA maps. 817 */ 818 for (i = 0; i < SIP_NRXDESC; i++) { 819 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 820 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 821 printf("%s: unable to create rx DMA map %d, " 822 "error = %d\n", sc->sc_dev.dv_xname, i, error); 823 goto fail_5; 824 } 825 sc->sc_rxsoft[i].rxs_mbuf = NULL; 826 } 827 828 /* 829 * Reset the chip to a known state. 830 */ 831 SIP_DECL(reset)(sc); 832 833 /* 834 * Read the Ethernet address from the EEPROM. This might 835 * also fetch other stuff from the EEPROM and stash it 836 * in the softc. 837 */ 838 sc->sc_cfg = 0; 839 #if !defined(DP83820) 840 if (SIP_SIS900_REV(sc,SIS_REV_635) || 841 SIP_SIS900_REV(sc,SIS_REV_900B)) 842 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 843 #endif 844 845 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 846 847 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 848 ether_sprintf(enaddr)); 849 850 /* 851 * Initialize the configuration register: aggressive PCI 852 * bus request algorithm, default backoff, default OW timer, 853 * default parity error detection. 854 * 855 * NOTE: "Big endian mode" is useless on the SiS900 and 856 * friends -- it affects packet data, not descriptors. 857 */ 858 #ifdef DP83820 859 /* 860 * Cause the chip to load configuration data from the EEPROM. 861 */ 862 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 863 for (i = 0; i < 10000; i++) { 864 delay(10); 865 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 866 PTSCR_EELOAD_EN) == 0) 867 break; 868 } 869 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 870 PTSCR_EELOAD_EN) { 871 printf("%s: timeout loading configuration from EEPROM\n", 872 sc->sc_dev.dv_xname); 873 return; 874 } 875 876 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 877 878 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 879 if (reg & CFG_PCI64_DET) { 880 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 881 /* 882 * Check to see if this card is 64-bit. If so, enable 64-bit 883 * data transfers. 884 * 885 * We can't use the DATA64_EN bit in the EEPROM, because 886 * vendors of 32-bit cards fail to clear that bit in many 887 * cases (yet the card still detects that it's in a 64-bit 888 * slot; go figure). 889 */ 890 if (SIP_DECL(check_64bit)(pa)) { 891 sc->sc_cfg |= CFG_DATA64_EN; 892 printf(", using 64-bit data transfers"); 893 } 894 printf("\n"); 895 } 896 897 /* 898 * XXX Need some PCI flags indicating support for 899 * XXX 64-bit addressing. 900 */ 901 #if 0 902 if (reg & CFG_M64ADDR) 903 sc->sc_cfg |= CFG_M64ADDR; 904 if (reg & CFG_T64ADDR) 905 sc->sc_cfg |= CFG_T64ADDR; 906 #endif 907 908 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 909 const char *sep = ""; 910 printf("%s: using ", sc->sc_dev.dv_xname); 911 if (reg & CFG_EXT_125) { 912 sc->sc_cfg |= CFG_EXT_125; 913 printf("%s125MHz clock", sep); 914 sep = ", "; 915 } 916 if (reg & CFG_TBI_EN) { 917 sc->sc_cfg |= CFG_TBI_EN; 918 printf("%sten-bit interface", sep); 919 sep = ", "; 920 } 921 printf("\n"); 922 } 923 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 924 (reg & CFG_MRM_DIS) != 0) 925 sc->sc_cfg |= CFG_MRM_DIS; 926 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 927 (reg & CFG_MWI_DIS) != 0) 928 sc->sc_cfg |= CFG_MWI_DIS; 929 930 /* 931 * Use the extended descriptor format on the DP83820. This 932 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 933 * checksumming. 934 */ 935 sc->sc_cfg |= CFG_EXTSTS_EN; 936 #endif /* DP83820 */ 937 938 /* 939 * Initialize our media structures and probe the MII. 940 */ 941 sc->sc_mii.mii_ifp = ifp; 942 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 943 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 944 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 945 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, SIP_DECL(mediachange), 946 SIP_DECL(mediastatus)); 947 948 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 949 MII_OFFSET_ANY, 0); 950 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 951 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 952 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 953 } else 954 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 955 956 ifp = &sc->sc_ethercom.ec_if; 957 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 958 ifp->if_softc = sc; 959 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 960 ifp->if_ioctl = SIP_DECL(ioctl); 961 ifp->if_start = SIP_DECL(start); 962 ifp->if_watchdog = SIP_DECL(watchdog); 963 ifp->if_init = SIP_DECL(init); 964 ifp->if_stop = SIP_DECL(stop); 965 IFQ_SET_READY(&ifp->if_snd); 966 967 /* 968 * We can support 802.1Q VLAN-sized frames. 969 */ 970 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 971 972 #ifdef DP83820 973 /* 974 * And the DP83820 can do VLAN tagging in hardware, and 975 * support the jumbo Ethernet MTU. 976 */ 977 sc->sc_ethercom.ec_capabilities |= 978 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 979 980 /* 981 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 982 * in hardware. 983 */ 984 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 985 IFCAP_CSUM_UDPv4; 986 #endif /* DP83820 */ 987 988 /* 989 * Attach the interface. 990 */ 991 if_attach(ifp); 992 ether_ifattach(ifp, enaddr); 993 #if NRND > 0 994 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 995 RND_TYPE_NET, 0); 996 #endif 997 998 /* 999 * The number of bytes that must be available in 1000 * the Tx FIFO before the bus master can DMA more 1001 * data into the FIFO. 1002 */ 1003 sc->sc_tx_fill_thresh = 64 / 32; 1004 1005 /* 1006 * Start at a drain threshold of 512 bytes. We will 1007 * increase it if a DMA underrun occurs. 1008 * 1009 * XXX The minimum value of this variable should be 1010 * tuned. We may be able to improve performance 1011 * by starting with a lower value. That, however, 1012 * may trash the first few outgoing packets if the 1013 * PCI bus is saturated. 1014 */ 1015 sc->sc_tx_drain_thresh = 1504 / 32; 1016 1017 /* 1018 * Initialize the Rx FIFO drain threshold. 1019 * 1020 * This is in units of 8 bytes. 1021 * 1022 * We should never set this value lower than 2; 14 bytes are 1023 * required to filter the packet. 1024 */ 1025 sc->sc_rx_drain_thresh = 128 / 8; 1026 1027 #ifdef SIP_EVENT_COUNTERS 1028 /* 1029 * Attach event counters. 1030 */ 1031 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1032 NULL, sc->sc_dev.dv_xname, "txsstall"); 1033 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1034 NULL, sc->sc_dev.dv_xname, "txdstall"); 1035 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1036 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1037 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1038 NULL, sc->sc_dev.dv_xname, "txdintr"); 1039 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1040 NULL, sc->sc_dev.dv_xname, "txiintr"); 1041 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1042 NULL, sc->sc_dev.dv_xname, "rxintr"); 1043 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1044 NULL, sc->sc_dev.dv_xname, "hiberr"); 1045 #ifdef DP83820 1046 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1047 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1048 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1049 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1050 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1051 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1052 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1053 NULL, sc->sc_dev.dv_xname, "txipsum"); 1054 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1055 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1056 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1057 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1058 #endif /* DP83820 */ 1059 #endif /* SIP_EVENT_COUNTERS */ 1060 1061 /* 1062 * Make sure the interface is shutdown during reboot. 1063 */ 1064 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 1065 if (sc->sc_sdhook == NULL) 1066 printf("%s: WARNING: unable to establish shutdown hook\n", 1067 sc->sc_dev.dv_xname); 1068 return; 1069 1070 /* 1071 * Free any resources we've allocated during the failed attach 1072 * attempt. Do this in reverse order and fall through. 1073 */ 1074 fail_5: 1075 for (i = 0; i < SIP_NRXDESC; i++) { 1076 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1077 bus_dmamap_destroy(sc->sc_dmat, 1078 sc->sc_rxsoft[i].rxs_dmamap); 1079 } 1080 fail_4: 1081 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1082 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1083 bus_dmamap_destroy(sc->sc_dmat, 1084 sc->sc_txsoft[i].txs_dmamap); 1085 } 1086 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1087 fail_3: 1088 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1089 fail_2: 1090 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1091 sizeof(struct sip_control_data)); 1092 fail_1: 1093 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1094 fail_0: 1095 return; 1096 } 1097 1098 /* 1099 * sip_shutdown: 1100 * 1101 * Make sure the interface is stopped at reboot time. 1102 */ 1103 void 1104 SIP_DECL(shutdown)(void *arg) 1105 { 1106 struct sip_softc *sc = arg; 1107 1108 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1109 } 1110 1111 /* 1112 * sip_start: [ifnet interface function] 1113 * 1114 * Start packet transmission on the interface. 1115 */ 1116 void 1117 SIP_DECL(start)(struct ifnet *ifp) 1118 { 1119 struct sip_softc *sc = ifp->if_softc; 1120 struct mbuf *m0, *m; 1121 struct sip_txsoft *txs; 1122 bus_dmamap_t dmamap; 1123 int error, nexttx, lasttx, seg; 1124 int ofree = sc->sc_txfree; 1125 #if 0 1126 int firsttx = sc->sc_txnext; 1127 #endif 1128 #ifdef DP83820 1129 struct m_tag *mtag; 1130 u_int32_t extsts; 1131 #endif 1132 1133 /* 1134 * If we've been told to pause, don't transmit any more packets. 1135 */ 1136 if (sc->sc_flags & SIPF_PAUSED) 1137 ifp->if_flags |= IFF_OACTIVE; 1138 1139 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1140 return; 1141 1142 /* 1143 * Loop through the send queue, setting up transmit descriptors 1144 * until we drain the queue, or use up all available transmit 1145 * descriptors. 1146 */ 1147 for (;;) { 1148 /* Get a work queue entry. */ 1149 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1150 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1151 break; 1152 } 1153 1154 /* 1155 * Grab a packet off the queue. 1156 */ 1157 IFQ_POLL(&ifp->if_snd, m0); 1158 if (m0 == NULL) 1159 break; 1160 #ifndef DP83820 1161 m = NULL; 1162 #endif 1163 1164 dmamap = txs->txs_dmamap; 1165 1166 #ifdef DP83820 1167 /* 1168 * Load the DMA map. If this fails, the packet either 1169 * didn't fit in the allotted number of segments, or we 1170 * were short on resources. For the too-many-segments 1171 * case, we simply report an error and drop the packet, 1172 * since we can't sanely copy a jumbo packet to a single 1173 * buffer. 1174 */ 1175 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1176 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1177 if (error) { 1178 if (error == EFBIG) { 1179 printf("%s: Tx packet consumes too many " 1180 "DMA segments, dropping...\n", 1181 sc->sc_dev.dv_xname); 1182 IFQ_DEQUEUE(&ifp->if_snd, m0); 1183 m_freem(m0); 1184 continue; 1185 } 1186 /* 1187 * Short on resources, just stop for now. 1188 */ 1189 break; 1190 } 1191 #else /* DP83820 */ 1192 /* 1193 * Load the DMA map. If this fails, the packet either 1194 * didn't fit in the alloted number of segments, or we 1195 * were short on resources. In this case, we'll copy 1196 * and try again. 1197 */ 1198 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1199 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1200 MGETHDR(m, M_DONTWAIT, MT_DATA); 1201 if (m == NULL) { 1202 printf("%s: unable to allocate Tx mbuf\n", 1203 sc->sc_dev.dv_xname); 1204 break; 1205 } 1206 if (m0->m_pkthdr.len > MHLEN) { 1207 MCLGET(m, M_DONTWAIT); 1208 if ((m->m_flags & M_EXT) == 0) { 1209 printf("%s: unable to allocate Tx " 1210 "cluster\n", sc->sc_dev.dv_xname); 1211 m_freem(m); 1212 break; 1213 } 1214 } 1215 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1216 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1217 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1218 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1219 if (error) { 1220 printf("%s: unable to load Tx buffer, " 1221 "error = %d\n", sc->sc_dev.dv_xname, error); 1222 break; 1223 } 1224 } 1225 #endif /* DP83820 */ 1226 1227 /* 1228 * Ensure we have enough descriptors free to describe 1229 * the packet. Note, we always reserve one descriptor 1230 * at the end of the ring as a termination point, to 1231 * prevent wrap-around. 1232 */ 1233 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1234 /* 1235 * Not enough free descriptors to transmit this 1236 * packet. We haven't committed anything yet, 1237 * so just unload the DMA map, put the packet 1238 * back on the queue, and punt. Notify the upper 1239 * layer that there are not more slots left. 1240 * 1241 * XXX We could allocate an mbuf and copy, but 1242 * XXX is it worth it? 1243 */ 1244 ifp->if_flags |= IFF_OACTIVE; 1245 bus_dmamap_unload(sc->sc_dmat, dmamap); 1246 #ifndef DP83820 1247 if (m != NULL) 1248 m_freem(m); 1249 #endif 1250 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1251 break; 1252 } 1253 1254 IFQ_DEQUEUE(&ifp->if_snd, m0); 1255 #ifndef DP83820 1256 if (m != NULL) { 1257 m_freem(m0); 1258 m0 = m; 1259 } 1260 #endif 1261 1262 /* 1263 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1264 */ 1265 1266 /* Sync the DMA map. */ 1267 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1268 BUS_DMASYNC_PREWRITE); 1269 1270 /* 1271 * Initialize the transmit descriptors. 1272 */ 1273 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1274 seg < dmamap->dm_nsegs; 1275 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1276 /* 1277 * If this is the first descriptor we're 1278 * enqueueing, don't set the OWN bit just 1279 * yet. That could cause a race condition. 1280 * We'll do it below. 1281 */ 1282 sc->sc_txdescs[nexttx].sipd_bufptr = 1283 htole32(dmamap->dm_segs[seg].ds_addr); 1284 sc->sc_txdescs[nexttx].sipd_cmdsts = 1285 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1286 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1287 #ifdef DP83820 1288 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1289 #endif /* DP83820 */ 1290 lasttx = nexttx; 1291 } 1292 1293 /* Clear the MORE bit on the last segment. */ 1294 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1295 1296 /* 1297 * If we're in the interrupt delay window, delay the 1298 * interrupt. 1299 */ 1300 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1301 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1302 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1303 htole32(CMDSTS_INTR); 1304 sc->sc_txwin = 0; 1305 } 1306 1307 #ifdef DP83820 1308 /* 1309 * If VLANs are enabled and the packet has a VLAN tag, set 1310 * up the descriptor to encapsulate the packet for us. 1311 * 1312 * This apparently has to be on the last descriptor of 1313 * the packet. 1314 */ 1315 if (sc->sc_ethercom.ec_nvlans != 0 && 1316 (mtag = m_tag_find(m0, PACKET_TAG_VLAN, NULL)) != NULL) { 1317 sc->sc_txdescs[lasttx].sipd_extsts |= 1318 htole32(EXTSTS_VPKT | 1319 htons(*mtod(m, int *) & EXTSTS_VTCI)); 1320 } 1321 1322 /* 1323 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1324 * checksumming, set up the descriptor to do this work 1325 * for us. 1326 * 1327 * This apparently has to be on the first descriptor of 1328 * the packet. 1329 * 1330 * Byte-swap constants so the compiler can optimize. 1331 */ 1332 extsts = 0; 1333 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1334 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1335 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1336 extsts |= htole32(EXTSTS_IPPKT); 1337 } 1338 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1339 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1340 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1341 extsts |= htole32(EXTSTS_TCPPKT); 1342 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1343 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1344 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1345 extsts |= htole32(EXTSTS_UDPPKT); 1346 } 1347 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1348 #endif /* DP83820 */ 1349 1350 /* Sync the descriptors we're using. */ 1351 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1352 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1353 1354 /* 1355 * The entire packet is set up. Give the first descrptor 1356 * to the chip now. 1357 */ 1358 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1359 htole32(CMDSTS_OWN); 1360 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1361 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1362 1363 /* 1364 * Store a pointer to the packet so we can free it later, 1365 * and remember what txdirty will be once the packet is 1366 * done. 1367 */ 1368 txs->txs_mbuf = m0; 1369 txs->txs_firstdesc = sc->sc_txnext; 1370 txs->txs_lastdesc = lasttx; 1371 1372 /* Advance the tx pointer. */ 1373 sc->sc_txfree -= dmamap->dm_nsegs; 1374 sc->sc_txnext = nexttx; 1375 1376 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1377 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1378 1379 #if NBPFILTER > 0 1380 /* 1381 * Pass the packet to any BPF listeners. 1382 */ 1383 if (ifp->if_bpf) 1384 bpf_mtap(ifp->if_bpf, m0); 1385 #endif /* NBPFILTER > 0 */ 1386 } 1387 1388 if (txs == NULL || sc->sc_txfree == 0) { 1389 /* No more slots left; notify upper layer. */ 1390 ifp->if_flags |= IFF_OACTIVE; 1391 } 1392 1393 if (sc->sc_txfree != ofree) { 1394 /* 1395 * Start the transmit process. Note, the manual says 1396 * that if there are no pending transmissions in the 1397 * chip's internal queue (indicated by TXE being clear), 1398 * then the driver software must set the TXDP to the 1399 * first descriptor to be transmitted. However, if we 1400 * do this, it causes serious performance degredation on 1401 * the DP83820 under load, not setting TXDP doesn't seem 1402 * to adversely affect the SiS 900 or DP83815. 1403 * 1404 * Well, I guess it wouldn't be the first time a manual 1405 * has lied -- and they could be speaking of the NULL- 1406 * terminated descriptor list case, rather than OWN- 1407 * terminated rings. 1408 */ 1409 #if 0 1410 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1411 CR_TXE) == 0) { 1412 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1413 SIP_CDTXADDR(sc, firsttx)); 1414 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1415 } 1416 #else 1417 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1418 #endif 1419 1420 /* Set a watchdog timer in case the chip flakes out. */ 1421 ifp->if_timer = 5; 1422 } 1423 } 1424 1425 /* 1426 * sip_watchdog: [ifnet interface function] 1427 * 1428 * Watchdog timer handler. 1429 */ 1430 void 1431 SIP_DECL(watchdog)(struct ifnet *ifp) 1432 { 1433 struct sip_softc *sc = ifp->if_softc; 1434 1435 /* 1436 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1437 * If we get a timeout, try and sweep up transmit descriptors. 1438 * If we manage to sweep them all up, ignore the lack of 1439 * interrupt. 1440 */ 1441 SIP_DECL(txintr)(sc); 1442 1443 if (sc->sc_txfree != SIP_NTXDESC) { 1444 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1445 ifp->if_oerrors++; 1446 1447 /* Reset the interface. */ 1448 (void) SIP_DECL(init)(ifp); 1449 } else if (ifp->if_flags & IFF_DEBUG) 1450 printf("%s: recovered from device timeout\n", 1451 sc->sc_dev.dv_xname); 1452 1453 /* Try to get more packets going. */ 1454 SIP_DECL(start)(ifp); 1455 } 1456 1457 /* 1458 * sip_ioctl: [ifnet interface function] 1459 * 1460 * Handle control requests from the operator. 1461 */ 1462 int 1463 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1464 { 1465 struct sip_softc *sc = ifp->if_softc; 1466 struct ifreq *ifr = (struct ifreq *)data; 1467 int s, error; 1468 1469 s = splnet(); 1470 1471 switch (cmd) { 1472 case SIOCSIFMEDIA: 1473 case SIOCGIFMEDIA: 1474 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1475 break; 1476 1477 default: 1478 error = ether_ioctl(ifp, cmd, data); 1479 if (error == ENETRESET) { 1480 /* 1481 * Multicast list has changed; set the hardware filter 1482 * accordingly. 1483 */ 1484 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1485 error = 0; 1486 } 1487 break; 1488 } 1489 1490 /* Try to get more packets going. */ 1491 SIP_DECL(start)(ifp); 1492 1493 splx(s); 1494 return (error); 1495 } 1496 1497 /* 1498 * sip_intr: 1499 * 1500 * Interrupt service routine. 1501 */ 1502 int 1503 SIP_DECL(intr)(void *arg) 1504 { 1505 struct sip_softc *sc = arg; 1506 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1507 u_int32_t isr; 1508 int handled = 0; 1509 1510 for (;;) { 1511 /* Reading clears interrupt. */ 1512 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1513 if ((isr & sc->sc_imr) == 0) 1514 break; 1515 1516 #if NRND > 0 1517 if (RND_ENABLED(&sc->rnd_source)) 1518 rnd_add_uint32(&sc->rnd_source, isr); 1519 #endif 1520 1521 handled = 1; 1522 1523 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1524 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1525 1526 /* Grab any new packets. */ 1527 SIP_DECL(rxintr)(sc); 1528 1529 if (isr & ISR_RXORN) { 1530 printf("%s: receive FIFO overrun\n", 1531 sc->sc_dev.dv_xname); 1532 1533 /* XXX adjust rx_drain_thresh? */ 1534 } 1535 1536 if (isr & ISR_RXIDLE) { 1537 printf("%s: receive ring overrun\n", 1538 sc->sc_dev.dv_xname); 1539 1540 /* Get the receive process going again. */ 1541 bus_space_write_4(sc->sc_st, sc->sc_sh, 1542 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1543 bus_space_write_4(sc->sc_st, sc->sc_sh, 1544 SIP_CR, CR_RXE); 1545 } 1546 } 1547 1548 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1549 #ifdef SIP_EVENT_COUNTERS 1550 if (isr & ISR_TXDESC) 1551 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1552 else if (isr & ISR_TXIDLE) 1553 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1554 #endif 1555 1556 /* Sweep up transmit descriptors. */ 1557 SIP_DECL(txintr)(sc); 1558 1559 if (isr & ISR_TXURN) { 1560 u_int32_t thresh; 1561 1562 printf("%s: transmit FIFO underrun", 1563 sc->sc_dev.dv_xname); 1564 1565 thresh = sc->sc_tx_drain_thresh + 1; 1566 if (thresh <= TXCFG_DRTH && 1567 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1568 (sc->sc_tx_fill_thresh * 32))) { 1569 printf("; increasing Tx drain " 1570 "threshold to %u bytes\n", 1571 thresh * 32); 1572 sc->sc_tx_drain_thresh = thresh; 1573 (void) SIP_DECL(init)(ifp); 1574 } else { 1575 (void) SIP_DECL(init)(ifp); 1576 printf("\n"); 1577 } 1578 } 1579 } 1580 1581 #if !defined(DP83820) 1582 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1583 if (isr & ISR_PAUSE_ST) { 1584 sc->sc_flags |= SIPF_PAUSED; 1585 ifp->if_flags |= IFF_OACTIVE; 1586 } 1587 if (isr & ISR_PAUSE_END) { 1588 sc->sc_flags &= ~SIPF_PAUSED; 1589 ifp->if_flags &= ~IFF_OACTIVE; 1590 } 1591 } 1592 #endif /* ! DP83820 */ 1593 1594 if (isr & ISR_HIBERR) { 1595 int want_init = 0; 1596 1597 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1598 1599 #define PRINTERR(bit, str) \ 1600 do { \ 1601 if ((isr & (bit)) != 0) { \ 1602 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1603 printf("%s: %s\n", \ 1604 sc->sc_dev.dv_xname, str); \ 1605 want_init = 1; \ 1606 } \ 1607 } while (/*CONSTCOND*/0) 1608 1609 PRINTERR(ISR_DPERR, "parity error"); 1610 PRINTERR(ISR_SSERR, "system error"); 1611 PRINTERR(ISR_RMABT, "master abort"); 1612 PRINTERR(ISR_RTABT, "target abort"); 1613 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1614 /* 1615 * Ignore: 1616 * Tx reset complete 1617 * Rx reset complete 1618 */ 1619 if (want_init) 1620 (void) SIP_DECL(init)(ifp); 1621 #undef PRINTERR 1622 } 1623 } 1624 1625 /* Try to get more packets going. */ 1626 SIP_DECL(start)(ifp); 1627 1628 return (handled); 1629 } 1630 1631 /* 1632 * sip_txintr: 1633 * 1634 * Helper; handle transmit interrupts. 1635 */ 1636 void 1637 SIP_DECL(txintr)(struct sip_softc *sc) 1638 { 1639 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1640 struct sip_txsoft *txs; 1641 u_int32_t cmdsts; 1642 1643 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1644 ifp->if_flags &= ~IFF_OACTIVE; 1645 1646 /* 1647 * Go through our Tx list and free mbufs for those 1648 * frames which have been transmitted. 1649 */ 1650 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1651 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1652 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1653 1654 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1655 if (cmdsts & CMDSTS_OWN) 1656 break; 1657 1658 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1659 1660 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1661 1662 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1663 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1664 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1665 m_freem(txs->txs_mbuf); 1666 txs->txs_mbuf = NULL; 1667 1668 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1669 1670 /* 1671 * Check for errors and collisions. 1672 */ 1673 if (cmdsts & 1674 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1675 ifp->if_oerrors++; 1676 if (cmdsts & CMDSTS_Tx_EC) 1677 ifp->if_collisions += 16; 1678 if (ifp->if_flags & IFF_DEBUG) { 1679 if (cmdsts & CMDSTS_Tx_ED) 1680 printf("%s: excessive deferral\n", 1681 sc->sc_dev.dv_xname); 1682 if (cmdsts & CMDSTS_Tx_EC) 1683 printf("%s: excessive collisions\n", 1684 sc->sc_dev.dv_xname); 1685 } 1686 } else { 1687 /* Packet was transmitted successfully. */ 1688 ifp->if_opackets++; 1689 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1690 } 1691 } 1692 1693 /* 1694 * If there are no more pending transmissions, cancel the watchdog 1695 * timer. 1696 */ 1697 if (txs == NULL) { 1698 ifp->if_timer = 0; 1699 sc->sc_txwin = 0; 1700 } 1701 } 1702 1703 #if defined(DP83820) 1704 /* 1705 * sip_rxintr: 1706 * 1707 * Helper; handle receive interrupts. 1708 */ 1709 void 1710 SIP_DECL(rxintr)(struct sip_softc *sc) 1711 { 1712 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1713 struct sip_rxsoft *rxs; 1714 struct mbuf *m, *tailm; 1715 u_int32_t cmdsts, extsts; 1716 int i, len; 1717 1718 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1719 rxs = &sc->sc_rxsoft[i]; 1720 1721 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1722 1723 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1724 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1725 1726 /* 1727 * NOTE: OWN is set if owned by _consumer_. We're the 1728 * consumer of the receive ring, so if the bit is clear, 1729 * we have processed all of the packets. 1730 */ 1731 if ((cmdsts & CMDSTS_OWN) == 0) { 1732 /* 1733 * We have processed all of the receive buffers. 1734 */ 1735 break; 1736 } 1737 1738 if (__predict_false(sc->sc_rxdiscard)) { 1739 SIP_INIT_RXDESC(sc, i); 1740 if ((cmdsts & CMDSTS_MORE) == 0) { 1741 /* Reset our state. */ 1742 sc->sc_rxdiscard = 0; 1743 } 1744 continue; 1745 } 1746 1747 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1748 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1749 1750 m = rxs->rxs_mbuf; 1751 1752 /* 1753 * Add a new receive buffer to the ring. 1754 */ 1755 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1756 /* 1757 * Failed, throw away what we've done so 1758 * far, and discard the rest of the packet. 1759 */ 1760 ifp->if_ierrors++; 1761 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1762 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1763 SIP_INIT_RXDESC(sc, i); 1764 if (cmdsts & CMDSTS_MORE) 1765 sc->sc_rxdiscard = 1; 1766 if (sc->sc_rxhead != NULL) 1767 m_freem(sc->sc_rxhead); 1768 SIP_RXCHAIN_RESET(sc); 1769 continue; 1770 } 1771 1772 SIP_RXCHAIN_LINK(sc, m); 1773 1774 /* 1775 * If this is not the end of the packet, keep 1776 * looking. 1777 */ 1778 if (cmdsts & CMDSTS_MORE) { 1779 sc->sc_rxlen += m->m_len; 1780 continue; 1781 } 1782 1783 /* 1784 * Okay, we have the entire packet now... 1785 */ 1786 *sc->sc_rxtailp = NULL; 1787 m = sc->sc_rxhead; 1788 tailm = sc->sc_rxtail; 1789 1790 SIP_RXCHAIN_RESET(sc); 1791 1792 /* 1793 * If an error occurred, update stats and drop the packet. 1794 */ 1795 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1796 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1797 ifp->if_ierrors++; 1798 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1799 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1800 /* Receive overrun handled elsewhere. */ 1801 printf("%s: receive descriptor error\n", 1802 sc->sc_dev.dv_xname); 1803 } 1804 #define PRINTERR(bit, str) \ 1805 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1806 (cmdsts & (bit)) != 0) \ 1807 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1808 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1809 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1810 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1811 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1812 #undef PRINTERR 1813 m_freem(m); 1814 continue; 1815 } 1816 1817 /* 1818 * No errors. 1819 * 1820 * Note, the DP83820 includes the CRC with 1821 * every packet. 1822 */ 1823 len = CMDSTS_SIZE(cmdsts); 1824 tailm->m_len = len - sc->sc_rxlen; 1825 1826 /* 1827 * If the packet is small enough to fit in a 1828 * single header mbuf, allocate one and copy 1829 * the data into it. This greatly reduces 1830 * memory consumption when we receive lots 1831 * of small packets. 1832 */ 1833 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1834 struct mbuf *nm; 1835 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1836 if (nm == NULL) { 1837 ifp->if_ierrors++; 1838 m_freem(m); 1839 continue; 1840 } 1841 nm->m_data += 2; 1842 nm->m_pkthdr.len = nm->m_len = len; 1843 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1844 m_freem(m); 1845 m = nm; 1846 } 1847 #ifndef __NO_STRICT_ALIGNMENT 1848 else { 1849 /* 1850 * The DP83820's receive buffers must be 4-byte 1851 * aligned. But this means that the data after 1852 * the Ethernet header is misaligned. To compensate, 1853 * we have artificially shortened the buffer size 1854 * in the descriptor, and we do an overlapping copy 1855 * of the data two bytes further in (in the first 1856 * buffer of the chain only). 1857 */ 1858 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1859 m->m_len); 1860 m->m_data += 2; 1861 } 1862 #endif /* ! __NO_STRICT_ALIGNMENT */ 1863 1864 /* 1865 * If VLANs are enabled, VLAN packets have been unwrapped 1866 * for us. Associate the tag with the packet. 1867 */ 1868 if (sc->sc_ethercom.ec_nvlans != 0 && 1869 (extsts & EXTSTS_VPKT) != 0) { 1870 struct m_tag *vtag; 1871 1872 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 1873 M_NOWAIT); 1874 if (vtag == NULL) { 1875 ifp->if_ierrors++; 1876 printf("%s: unable to allocate VLAN tag\n", 1877 sc->sc_dev.dv_xname); 1878 m_freem(m); 1879 continue; 1880 } 1881 1882 *(u_int *)(vtag + 1) = ntohs(extsts & EXTSTS_VTCI); 1883 } 1884 1885 /* 1886 * Set the incoming checksum information for the 1887 * packet. 1888 */ 1889 if ((extsts & EXTSTS_IPPKT) != 0) { 1890 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1891 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1892 if (extsts & EXTSTS_Rx_IPERR) 1893 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1894 if (extsts & EXTSTS_TCPPKT) { 1895 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1896 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1897 if (extsts & EXTSTS_Rx_TCPERR) 1898 m->m_pkthdr.csum_flags |= 1899 M_CSUM_TCP_UDP_BAD; 1900 } else if (extsts & EXTSTS_UDPPKT) { 1901 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1902 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1903 if (extsts & EXTSTS_Rx_UDPERR) 1904 m->m_pkthdr.csum_flags |= 1905 M_CSUM_TCP_UDP_BAD; 1906 } 1907 } 1908 1909 ifp->if_ipackets++; 1910 m->m_flags |= M_HASFCS; 1911 m->m_pkthdr.rcvif = ifp; 1912 m->m_pkthdr.len = len; 1913 1914 #if NBPFILTER > 0 1915 /* 1916 * Pass this up to any BPF listeners, but only 1917 * pass if up the stack if it's for us. 1918 */ 1919 if (ifp->if_bpf) 1920 bpf_mtap(ifp->if_bpf, m); 1921 #endif /* NBPFILTER > 0 */ 1922 1923 /* Pass it on. */ 1924 (*ifp->if_input)(ifp, m); 1925 } 1926 1927 /* Update the receive pointer. */ 1928 sc->sc_rxptr = i; 1929 } 1930 #else /* ! DP83820 */ 1931 /* 1932 * sip_rxintr: 1933 * 1934 * Helper; handle receive interrupts. 1935 */ 1936 void 1937 SIP_DECL(rxintr)(struct sip_softc *sc) 1938 { 1939 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1940 struct sip_rxsoft *rxs; 1941 struct mbuf *m; 1942 u_int32_t cmdsts; 1943 int i, len; 1944 1945 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1946 rxs = &sc->sc_rxsoft[i]; 1947 1948 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1949 1950 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1951 1952 /* 1953 * NOTE: OWN is set if owned by _consumer_. We're the 1954 * consumer of the receive ring, so if the bit is clear, 1955 * we have processed all of the packets. 1956 */ 1957 if ((cmdsts & CMDSTS_OWN) == 0) { 1958 /* 1959 * We have processed all of the receive buffers. 1960 */ 1961 break; 1962 } 1963 1964 /* 1965 * If any collisions were seen on the wire, count one. 1966 */ 1967 if (cmdsts & CMDSTS_Rx_COL) 1968 ifp->if_collisions++; 1969 1970 /* 1971 * If an error occurred, update stats, clear the status 1972 * word, and leave the packet buffer in place. It will 1973 * simply be reused the next time the ring comes around. 1974 */ 1975 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1976 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1977 ifp->if_ierrors++; 1978 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1979 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1980 /* Receive overrun handled elsewhere. */ 1981 printf("%s: receive descriptor error\n", 1982 sc->sc_dev.dv_xname); 1983 } 1984 #define PRINTERR(bit, str) \ 1985 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1986 (cmdsts & (bit)) != 0) \ 1987 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1988 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1989 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1990 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1991 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1992 #undef PRINTERR 1993 SIP_INIT_RXDESC(sc, i); 1994 continue; 1995 } 1996 1997 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1998 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1999 2000 /* 2001 * No errors; receive the packet. Note, the SiS 900 2002 * includes the CRC with every packet. 2003 */ 2004 len = CMDSTS_SIZE(cmdsts); 2005 2006 #ifdef __NO_STRICT_ALIGNMENT 2007 /* 2008 * If the packet is small enough to fit in a 2009 * single header mbuf, allocate one and copy 2010 * the data into it. This greatly reduces 2011 * memory consumption when we receive lots 2012 * of small packets. 2013 * 2014 * Otherwise, we add a new buffer to the receive 2015 * chain. If this fails, we drop the packet and 2016 * recycle the old buffer. 2017 */ 2018 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 2019 MGETHDR(m, M_DONTWAIT, MT_DATA); 2020 if (m == NULL) 2021 goto dropit; 2022 memcpy(mtod(m, caddr_t), 2023 mtod(rxs->rxs_mbuf, caddr_t), len); 2024 SIP_INIT_RXDESC(sc, i); 2025 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2026 rxs->rxs_dmamap->dm_mapsize, 2027 BUS_DMASYNC_PREREAD); 2028 } else { 2029 m = rxs->rxs_mbuf; 2030 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 2031 dropit: 2032 ifp->if_ierrors++; 2033 SIP_INIT_RXDESC(sc, i); 2034 bus_dmamap_sync(sc->sc_dmat, 2035 rxs->rxs_dmamap, 0, 2036 rxs->rxs_dmamap->dm_mapsize, 2037 BUS_DMASYNC_PREREAD); 2038 continue; 2039 } 2040 } 2041 #else 2042 /* 2043 * The SiS 900's receive buffers must be 4-byte aligned. 2044 * But this means that the data after the Ethernet header 2045 * is misaligned. We must allocate a new buffer and 2046 * copy the data, shifted forward 2 bytes. 2047 */ 2048 MGETHDR(m, M_DONTWAIT, MT_DATA); 2049 if (m == NULL) { 2050 dropit: 2051 ifp->if_ierrors++; 2052 SIP_INIT_RXDESC(sc, i); 2053 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2054 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2055 continue; 2056 } 2057 if (len > (MHLEN - 2)) { 2058 MCLGET(m, M_DONTWAIT); 2059 if ((m->m_flags & M_EXT) == 0) { 2060 m_freem(m); 2061 goto dropit; 2062 } 2063 } 2064 m->m_data += 2; 2065 2066 /* 2067 * Note that we use clusters for incoming frames, so the 2068 * buffer is virtually contiguous. 2069 */ 2070 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 2071 2072 /* Allow the receive descriptor to continue using its mbuf. */ 2073 SIP_INIT_RXDESC(sc, i); 2074 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2075 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2076 #endif /* __NO_STRICT_ALIGNMENT */ 2077 2078 ifp->if_ipackets++; 2079 m->m_flags |= M_HASFCS; 2080 m->m_pkthdr.rcvif = ifp; 2081 m->m_pkthdr.len = m->m_len = len; 2082 2083 #if NBPFILTER > 0 2084 /* 2085 * Pass this up to any BPF listeners, but only 2086 * pass if up the stack if it's for us. 2087 */ 2088 if (ifp->if_bpf) 2089 bpf_mtap(ifp->if_bpf, m); 2090 #endif /* NBPFILTER > 0 */ 2091 2092 /* Pass it on. */ 2093 (*ifp->if_input)(ifp, m); 2094 } 2095 2096 /* Update the receive pointer. */ 2097 sc->sc_rxptr = i; 2098 } 2099 #endif /* DP83820 */ 2100 2101 /* 2102 * sip_tick: 2103 * 2104 * One second timer, used to tick the MII. 2105 */ 2106 void 2107 SIP_DECL(tick)(void *arg) 2108 { 2109 struct sip_softc *sc = arg; 2110 int s; 2111 2112 s = splnet(); 2113 mii_tick(&sc->sc_mii); 2114 splx(s); 2115 2116 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2117 } 2118 2119 /* 2120 * sip_reset: 2121 * 2122 * Perform a soft reset on the SiS 900. 2123 */ 2124 void 2125 SIP_DECL(reset)(struct sip_softc *sc) 2126 { 2127 bus_space_tag_t st = sc->sc_st; 2128 bus_space_handle_t sh = sc->sc_sh; 2129 int i; 2130 2131 bus_space_write_4(st, sh, SIP_IER, 0); 2132 bus_space_write_4(st, sh, SIP_IMR, 0); 2133 bus_space_write_4(st, sh, SIP_RFCR, 0); 2134 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2135 2136 for (i = 0; i < SIP_TIMEOUT; i++) { 2137 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2138 break; 2139 delay(2); 2140 } 2141 2142 if (i == SIP_TIMEOUT) 2143 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2144 2145 delay(1000); 2146 2147 #ifdef DP83820 2148 /* 2149 * Set the general purpose I/O bits. Do it here in case we 2150 * need to have GPIO set up to talk to the media interface. 2151 */ 2152 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2153 delay(1000); 2154 #endif /* DP83820 */ 2155 } 2156 2157 /* 2158 * sip_init: [ ifnet interface function ] 2159 * 2160 * Initialize the interface. Must be called at splnet(). 2161 */ 2162 int 2163 SIP_DECL(init)(struct ifnet *ifp) 2164 { 2165 struct sip_softc *sc = ifp->if_softc; 2166 bus_space_tag_t st = sc->sc_st; 2167 bus_space_handle_t sh = sc->sc_sh; 2168 struct sip_txsoft *txs; 2169 struct sip_rxsoft *rxs; 2170 struct sip_desc *sipd; 2171 #if defined(DP83820) 2172 u_int32_t reg; 2173 #endif 2174 int i, error = 0; 2175 2176 /* 2177 * Cancel any pending I/O. 2178 */ 2179 SIP_DECL(stop)(ifp, 0); 2180 2181 /* 2182 * Reset the chip to a known state. 2183 */ 2184 SIP_DECL(reset)(sc); 2185 2186 #if !defined(DP83820) 2187 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2188 /* 2189 * DP83815 manual, page 78: 2190 * 4.4 Recommended Registers Configuration 2191 * For optimum performance of the DP83815, version noted 2192 * as DP83815CVNG (SRR = 203h), the listed register 2193 * modifications must be followed in sequence... 2194 * 2195 * It's not clear if this should be 302h or 203h because that 2196 * chip name is listed as SRR 302h in the description of the 2197 * SRR register. However, my revision 302h DP83815 on the 2198 * Netgear FA311 purchased in 02/2001 needs these settings 2199 * to avoid tons of errors in AcceptPerfectMatch (non- 2200 * IFF_PROMISC) mode. I do not know if other revisions need 2201 * this set or not. [briggs -- 09 March 2001] 2202 * 2203 * Note that only the low-order 12 bits of 0xe4 are documented 2204 * and that this sets reserved bits in that register. 2205 */ 2206 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2207 2208 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2209 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2210 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2211 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2212 2213 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2214 } 2215 #endif /* ! DP83820 */ 2216 2217 /* 2218 * Initialize the transmit descriptor ring. 2219 */ 2220 for (i = 0; i < SIP_NTXDESC; i++) { 2221 sipd = &sc->sc_txdescs[i]; 2222 memset(sipd, 0, sizeof(struct sip_desc)); 2223 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2224 } 2225 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2226 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2227 sc->sc_txfree = SIP_NTXDESC; 2228 sc->sc_txnext = 0; 2229 sc->sc_txwin = 0; 2230 2231 /* 2232 * Initialize the transmit job descriptors. 2233 */ 2234 SIMPLEQ_INIT(&sc->sc_txfreeq); 2235 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2236 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2237 txs = &sc->sc_txsoft[i]; 2238 txs->txs_mbuf = NULL; 2239 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2240 } 2241 2242 /* 2243 * Initialize the receive descriptor and receive job 2244 * descriptor rings. 2245 */ 2246 for (i = 0; i < SIP_NRXDESC; i++) { 2247 rxs = &sc->sc_rxsoft[i]; 2248 if (rxs->rxs_mbuf == NULL) { 2249 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2250 printf("%s: unable to allocate or map rx " 2251 "buffer %d, error = %d\n", 2252 sc->sc_dev.dv_xname, i, error); 2253 /* 2254 * XXX Should attempt to run with fewer receive 2255 * XXX buffers instead of just failing. 2256 */ 2257 SIP_DECL(rxdrain)(sc); 2258 goto out; 2259 } 2260 } else 2261 SIP_INIT_RXDESC(sc, i); 2262 } 2263 sc->sc_rxptr = 0; 2264 #ifdef DP83820 2265 sc->sc_rxdiscard = 0; 2266 SIP_RXCHAIN_RESET(sc); 2267 #endif /* DP83820 */ 2268 2269 /* 2270 * Set the configuration register; it's already initialized 2271 * in sip_attach(). 2272 */ 2273 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2274 2275 /* 2276 * Initialize the prototype TXCFG register. 2277 */ 2278 #if defined(DP83820) 2279 sc->sc_txcfg = TXCFG_MXDMA_512; 2280 sc->sc_rxcfg = RXCFG_MXDMA_512; 2281 #else 2282 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2283 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2284 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & CFG_EDBMASTEN)) { 2285 sc->sc_txcfg = TXCFG_MXDMA_64; 2286 sc->sc_rxcfg = RXCFG_MXDMA_64; 2287 } else { 2288 sc->sc_txcfg = TXCFG_MXDMA_512; 2289 sc->sc_rxcfg = RXCFG_MXDMA_512; 2290 } 2291 #endif /* DP83820 */ 2292 2293 sc->sc_txcfg |= TXCFG_ATP | 2294 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2295 sc->sc_tx_drain_thresh; 2296 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2297 2298 /* 2299 * Initialize the receive drain threshold if we have never 2300 * done so. 2301 */ 2302 if (sc->sc_rx_drain_thresh == 0) { 2303 /* 2304 * XXX This value should be tuned. This is set to the 2305 * maximum of 248 bytes, and we may be able to improve 2306 * performance by decreasing it (although we should never 2307 * set this value lower than 2; 14 bytes are required to 2308 * filter the packet). 2309 */ 2310 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2311 } 2312 2313 /* 2314 * Initialize the prototype RXCFG register. 2315 */ 2316 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2317 #ifndef DP83820 2318 /* 2319 * Accept packets >1518 bytes (including FCS) so we can handle 2320 * 802.1q-tagged frames properly. 2321 */ 2322 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2323 sc->sc_rxcfg |= RXCFG_ALP; 2324 #endif 2325 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2326 2327 #ifdef DP83820 2328 /* 2329 * Initialize the VLAN/IP receive control register. 2330 * We enable checksum computation on all incoming 2331 * packets, and do not reject packets w/ bad checksums. 2332 */ 2333 reg = 0; 2334 if (ifp->if_capenable & 2335 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2336 reg |= VRCR_IPEN; 2337 if (sc->sc_ethercom.ec_nvlans != 0) 2338 reg |= VRCR_VTDEN|VRCR_VTREN; 2339 bus_space_write_4(st, sh, SIP_VRCR, reg); 2340 2341 /* 2342 * Initialize the VLAN/IP transmit control register. 2343 * We enable outgoing checksum computation on a 2344 * per-packet basis. 2345 */ 2346 reg = 0; 2347 if (ifp->if_capenable & 2348 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2349 reg |= VTCR_PPCHK; 2350 if (sc->sc_ethercom.ec_nvlans != 0) 2351 reg |= VTCR_VPPTI; 2352 bus_space_write_4(st, sh, SIP_VTCR, reg); 2353 2354 /* 2355 * If we're using VLANs, initialize the VLAN data register. 2356 * To understand why we bswap the VLAN Ethertype, see section 2357 * 4.2.36 of the DP83820 manual. 2358 */ 2359 if (sc->sc_ethercom.ec_nvlans != 0) 2360 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2361 #endif /* DP83820 */ 2362 2363 /* 2364 * Give the transmit and receive rings to the chip. 2365 */ 2366 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2367 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2368 2369 /* 2370 * Initialize the interrupt mask. 2371 */ 2372 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2373 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2374 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2375 2376 /* Set up the receive filter. */ 2377 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2378 2379 /* 2380 * Set the current media. Do this after initializing the prototype 2381 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2382 * control. 2383 */ 2384 mii_mediachg(&sc->sc_mii); 2385 2386 /* 2387 * Enable interrupts. 2388 */ 2389 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2390 2391 /* 2392 * Start the transmit and receive processes. 2393 */ 2394 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2395 2396 /* 2397 * Start the one second MII clock. 2398 */ 2399 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2400 2401 /* 2402 * ...all done! 2403 */ 2404 ifp->if_flags |= IFF_RUNNING; 2405 ifp->if_flags &= ~IFF_OACTIVE; 2406 2407 out: 2408 if (error) 2409 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2410 return (error); 2411 } 2412 2413 /* 2414 * sip_drain: 2415 * 2416 * Drain the receive queue. 2417 */ 2418 void 2419 SIP_DECL(rxdrain)(struct sip_softc *sc) 2420 { 2421 struct sip_rxsoft *rxs; 2422 int i; 2423 2424 for (i = 0; i < SIP_NRXDESC; i++) { 2425 rxs = &sc->sc_rxsoft[i]; 2426 if (rxs->rxs_mbuf != NULL) { 2427 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2428 m_freem(rxs->rxs_mbuf); 2429 rxs->rxs_mbuf = NULL; 2430 } 2431 } 2432 } 2433 2434 /* 2435 * sip_stop: [ ifnet interface function ] 2436 * 2437 * Stop transmission on the interface. 2438 */ 2439 void 2440 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2441 { 2442 struct sip_softc *sc = ifp->if_softc; 2443 bus_space_tag_t st = sc->sc_st; 2444 bus_space_handle_t sh = sc->sc_sh; 2445 struct sip_txsoft *txs; 2446 u_int32_t cmdsts = 0; /* DEBUG */ 2447 2448 /* 2449 * Stop the one second clock. 2450 */ 2451 callout_stop(&sc->sc_tick_ch); 2452 2453 /* Down the MII. */ 2454 mii_down(&sc->sc_mii); 2455 2456 /* 2457 * Disable interrupts. 2458 */ 2459 bus_space_write_4(st, sh, SIP_IER, 0); 2460 2461 /* 2462 * Stop receiver and transmitter. 2463 */ 2464 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2465 2466 /* 2467 * Release any queued transmit buffers. 2468 */ 2469 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2470 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2471 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2472 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2473 CMDSTS_INTR) == 0) 2474 printf("%s: sip_stop: last descriptor does not " 2475 "have INTR bit set\n", sc->sc_dev.dv_xname); 2476 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2477 #ifdef DIAGNOSTIC 2478 if (txs->txs_mbuf == NULL) { 2479 printf("%s: dirty txsoft with no mbuf chain\n", 2480 sc->sc_dev.dv_xname); 2481 panic("sip_stop"); 2482 } 2483 #endif 2484 cmdsts |= /* DEBUG */ 2485 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2486 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2487 m_freem(txs->txs_mbuf); 2488 txs->txs_mbuf = NULL; 2489 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2490 } 2491 2492 if (disable) 2493 SIP_DECL(rxdrain)(sc); 2494 2495 /* 2496 * Mark the interface down and cancel the watchdog timer. 2497 */ 2498 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2499 ifp->if_timer = 0; 2500 2501 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2502 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2503 printf("%s: sip_stop: no INTR bits set in dirty tx " 2504 "descriptors\n", sc->sc_dev.dv_xname); 2505 } 2506 2507 /* 2508 * sip_read_eeprom: 2509 * 2510 * Read data from the serial EEPROM. 2511 */ 2512 void 2513 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2514 u_int16_t *data) 2515 { 2516 bus_space_tag_t st = sc->sc_st; 2517 bus_space_handle_t sh = sc->sc_sh; 2518 u_int16_t reg; 2519 int i, x; 2520 2521 for (i = 0; i < wordcnt; i++) { 2522 /* Send CHIP SELECT. */ 2523 reg = EROMAR_EECS; 2524 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2525 2526 /* Shift in the READ opcode. */ 2527 for (x = 3; x > 0; x--) { 2528 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2529 reg |= EROMAR_EEDI; 2530 else 2531 reg &= ~EROMAR_EEDI; 2532 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2533 bus_space_write_4(st, sh, SIP_EROMAR, 2534 reg | EROMAR_EESK); 2535 delay(4); 2536 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2537 delay(4); 2538 } 2539 2540 /* Shift in address. */ 2541 for (x = 6; x > 0; x--) { 2542 if ((word + i) & (1 << (x - 1))) 2543 reg |= EROMAR_EEDI; 2544 else 2545 reg &= ~EROMAR_EEDI; 2546 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2547 bus_space_write_4(st, sh, SIP_EROMAR, 2548 reg | EROMAR_EESK); 2549 delay(4); 2550 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2551 delay(4); 2552 } 2553 2554 /* Shift out data. */ 2555 reg = EROMAR_EECS; 2556 data[i] = 0; 2557 for (x = 16; x > 0; x--) { 2558 bus_space_write_4(st, sh, SIP_EROMAR, 2559 reg | EROMAR_EESK); 2560 delay(4); 2561 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2562 data[i] |= (1 << (x - 1)); 2563 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2564 delay(4); 2565 } 2566 2567 /* Clear CHIP SELECT. */ 2568 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2569 delay(4); 2570 } 2571 } 2572 2573 /* 2574 * sip_add_rxbuf: 2575 * 2576 * Add a receive buffer to the indicated descriptor. 2577 */ 2578 int 2579 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2580 { 2581 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2582 struct mbuf *m; 2583 int error; 2584 2585 MGETHDR(m, M_DONTWAIT, MT_DATA); 2586 if (m == NULL) 2587 return (ENOBUFS); 2588 2589 MCLGET(m, M_DONTWAIT); 2590 if ((m->m_flags & M_EXT) == 0) { 2591 m_freem(m); 2592 return (ENOBUFS); 2593 } 2594 2595 #if defined(DP83820) 2596 m->m_len = SIP_RXBUF_LEN; 2597 #endif /* DP83820 */ 2598 2599 if (rxs->rxs_mbuf != NULL) 2600 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2601 2602 rxs->rxs_mbuf = m; 2603 2604 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2605 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2606 BUS_DMA_READ|BUS_DMA_NOWAIT); 2607 if (error) { 2608 printf("%s: can't load rx DMA map %d, error = %d\n", 2609 sc->sc_dev.dv_xname, idx, error); 2610 panic("sip_add_rxbuf"); /* XXX */ 2611 } 2612 2613 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2614 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2615 2616 SIP_INIT_RXDESC(sc, idx); 2617 2618 return (0); 2619 } 2620 2621 #if !defined(DP83820) 2622 /* 2623 * sip_sis900_set_filter: 2624 * 2625 * Set up the receive filter. 2626 */ 2627 void 2628 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2629 { 2630 bus_space_tag_t st = sc->sc_st; 2631 bus_space_handle_t sh = sc->sc_sh; 2632 struct ethercom *ec = &sc->sc_ethercom; 2633 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2634 struct ether_multi *enm; 2635 u_int8_t *cp; 2636 struct ether_multistep step; 2637 u_int32_t crc, mchash[16]; 2638 2639 /* 2640 * Initialize the prototype RFCR. 2641 */ 2642 sc->sc_rfcr = RFCR_RFEN; 2643 if (ifp->if_flags & IFF_BROADCAST) 2644 sc->sc_rfcr |= RFCR_AAB; 2645 if (ifp->if_flags & IFF_PROMISC) { 2646 sc->sc_rfcr |= RFCR_AAP; 2647 goto allmulti; 2648 } 2649 2650 /* 2651 * Set up the multicast address filter by passing all multicast 2652 * addresses through a CRC generator, and then using the high-order 2653 * 6 bits as an index into the 128 bit multicast hash table (only 2654 * the lower 16 bits of each 32 bit multicast hash register are 2655 * valid). The high order bits select the register, while the 2656 * rest of the bits select the bit within the register. 2657 */ 2658 2659 memset(mchash, 0, sizeof(mchash)); 2660 2661 ETHER_FIRST_MULTI(step, ec, enm); 2662 while (enm != NULL) { 2663 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2664 /* 2665 * We must listen to a range of multicast addresses. 2666 * For now, just accept all multicasts, rather than 2667 * trying to set only those filter bits needed to match 2668 * the range. (At this time, the only use of address 2669 * ranges is for IP multicast routing, for which the 2670 * range is big enough to require all bits set.) 2671 */ 2672 goto allmulti; 2673 } 2674 2675 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2676 2677 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2678 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2679 /* Just want the 8 most significant bits. */ 2680 crc >>= 24; 2681 } else { 2682 /* Just want the 7 most significant bits. */ 2683 crc >>= 25; 2684 } 2685 2686 /* Set the corresponding bit in the hash table. */ 2687 mchash[crc >> 4] |= 1 << (crc & 0xf); 2688 2689 ETHER_NEXT_MULTI(step, enm); 2690 } 2691 2692 ifp->if_flags &= ~IFF_ALLMULTI; 2693 goto setit; 2694 2695 allmulti: 2696 ifp->if_flags |= IFF_ALLMULTI; 2697 sc->sc_rfcr |= RFCR_AAM; 2698 2699 setit: 2700 #define FILTER_EMIT(addr, data) \ 2701 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2702 delay(1); \ 2703 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2704 delay(1) 2705 2706 /* 2707 * Disable receive filter, and program the node address. 2708 */ 2709 cp = LLADDR(ifp->if_sadl); 2710 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2711 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2712 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2713 2714 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2715 /* 2716 * Program the multicast hash table. 2717 */ 2718 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2719 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2720 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2721 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2722 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2723 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2724 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2725 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2726 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2727 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2728 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2729 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2730 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2731 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2732 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2733 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2734 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2735 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2736 } 2737 } 2738 #undef FILTER_EMIT 2739 2740 /* 2741 * Re-enable the receiver filter. 2742 */ 2743 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2744 } 2745 #endif /* ! DP83820 */ 2746 2747 /* 2748 * sip_dp83815_set_filter: 2749 * 2750 * Set up the receive filter. 2751 */ 2752 void 2753 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2754 { 2755 bus_space_tag_t st = sc->sc_st; 2756 bus_space_handle_t sh = sc->sc_sh; 2757 struct ethercom *ec = &sc->sc_ethercom; 2758 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2759 struct ether_multi *enm; 2760 u_int8_t *cp; 2761 struct ether_multistep step; 2762 u_int32_t crc, hash, slot, bit; 2763 #ifdef DP83820 2764 #define MCHASH_NWORDS 128 2765 #else 2766 #define MCHASH_NWORDS 32 2767 #endif /* DP83820 */ 2768 u_int16_t mchash[MCHASH_NWORDS]; 2769 int i; 2770 2771 /* 2772 * Initialize the prototype RFCR. 2773 * Enable the receive filter, and accept on 2774 * Perfect (destination address) Match 2775 * If IFF_BROADCAST, also accept all broadcast packets. 2776 * If IFF_PROMISC, accept all unicast packets (and later, set 2777 * IFF_ALLMULTI and accept all multicast, too). 2778 */ 2779 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2780 if (ifp->if_flags & IFF_BROADCAST) 2781 sc->sc_rfcr |= RFCR_AAB; 2782 if (ifp->if_flags & IFF_PROMISC) { 2783 sc->sc_rfcr |= RFCR_AAP; 2784 goto allmulti; 2785 } 2786 2787 #ifdef DP83820 2788 /* 2789 * Set up the DP83820 multicast address filter by passing all multicast 2790 * addresses through a CRC generator, and then using the high-order 2791 * 11 bits as an index into the 2048 bit multicast hash table. The 2792 * high-order 7 bits select the slot, while the low-order 4 bits 2793 * select the bit within the slot. Note that only the low 16-bits 2794 * of each filter word are used, and there are 128 filter words. 2795 */ 2796 #else 2797 /* 2798 * Set up the DP83815 multicast address filter by passing all multicast 2799 * addresses through a CRC generator, and then using the high-order 2800 * 9 bits as an index into the 512 bit multicast hash table. The 2801 * high-order 5 bits select the slot, while the low-order 4 bits 2802 * select the bit within the slot. Note that only the low 16-bits 2803 * of each filter word are used, and there are 32 filter words. 2804 */ 2805 #endif /* DP83820 */ 2806 2807 memset(mchash, 0, sizeof(mchash)); 2808 2809 ifp->if_flags &= ~IFF_ALLMULTI; 2810 ETHER_FIRST_MULTI(step, ec, enm); 2811 if (enm == NULL) 2812 goto setit; 2813 while (enm != NULL) { 2814 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2815 /* 2816 * We must listen to a range of multicast addresses. 2817 * For now, just accept all multicasts, rather than 2818 * trying to set only those filter bits needed to match 2819 * the range. (At this time, the only use of address 2820 * ranges is for IP multicast routing, for which the 2821 * range is big enough to require all bits set.) 2822 */ 2823 goto allmulti; 2824 } 2825 2826 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2827 2828 #ifdef DP83820 2829 /* Just want the 11 most significant bits. */ 2830 hash = crc >> 21; 2831 #else 2832 /* Just want the 9 most significant bits. */ 2833 hash = crc >> 23; 2834 #endif /* DP83820 */ 2835 2836 slot = hash >> 4; 2837 bit = hash & 0xf; 2838 2839 /* Set the corresponding bit in the hash table. */ 2840 mchash[slot] |= 1 << bit; 2841 2842 ETHER_NEXT_MULTI(step, enm); 2843 } 2844 sc->sc_rfcr |= RFCR_MHEN; 2845 goto setit; 2846 2847 allmulti: 2848 ifp->if_flags |= IFF_ALLMULTI; 2849 sc->sc_rfcr |= RFCR_AAM; 2850 2851 setit: 2852 #define FILTER_EMIT(addr, data) \ 2853 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2854 delay(1); \ 2855 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2856 delay(1) 2857 2858 /* 2859 * Disable receive filter, and program the node address. 2860 */ 2861 cp = LLADDR(ifp->if_sadl); 2862 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 2863 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 2864 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 2865 2866 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2867 /* 2868 * Program the multicast hash table. 2869 */ 2870 for (i = 0; i < MCHASH_NWORDS; i++) { 2871 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 2872 mchash[i]); 2873 } 2874 } 2875 #undef FILTER_EMIT 2876 #undef MCHASH_NWORDS 2877 2878 /* 2879 * Re-enable the receiver filter. 2880 */ 2881 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2882 } 2883 2884 #if defined(DP83820) 2885 /* 2886 * sip_dp83820_mii_readreg: [mii interface function] 2887 * 2888 * Read a PHY register on the MII of the DP83820. 2889 */ 2890 int 2891 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 2892 { 2893 struct sip_softc *sc = (void *) self; 2894 2895 if (sc->sc_cfg & CFG_TBI_EN) { 2896 bus_addr_t tbireg; 2897 int rv; 2898 2899 if (phy != 0) 2900 return (0); 2901 2902 switch (reg) { 2903 case MII_BMCR: tbireg = SIP_TBICR; break; 2904 case MII_BMSR: tbireg = SIP_TBISR; break; 2905 case MII_ANAR: tbireg = SIP_TANAR; break; 2906 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 2907 case MII_ANER: tbireg = SIP_TANER; break; 2908 case MII_EXTSR: 2909 /* 2910 * Don't even bother reading the TESR register. 2911 * The manual documents that the device has 2912 * 1000baseX full/half capability, but the 2913 * register itself seems read back 0 on some 2914 * boards. Just hard-code the result. 2915 */ 2916 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 2917 2918 default: 2919 return (0); 2920 } 2921 2922 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 2923 if (tbireg == SIP_TBISR) { 2924 /* LINK and ACOMP are switched! */ 2925 int val = rv; 2926 2927 rv = 0; 2928 if (val & TBISR_MR_LINK_STATUS) 2929 rv |= BMSR_LINK; 2930 if (val & TBISR_MR_AN_COMPLETE) 2931 rv |= BMSR_ACOMP; 2932 2933 /* 2934 * The manual claims this register reads back 0 2935 * on hard and soft reset. But we want to let 2936 * the gentbi driver know that we support auto- 2937 * negotiation, so hard-code this bit in the 2938 * result. 2939 */ 2940 rv |= BMSR_ANEG | BMSR_EXTSTAT; 2941 } 2942 2943 return (rv); 2944 } 2945 2946 return (mii_bitbang_readreg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2947 phy, reg)); 2948 } 2949 2950 /* 2951 * sip_dp83820_mii_writereg: [mii interface function] 2952 * 2953 * Write a PHY register on the MII of the DP83820. 2954 */ 2955 void 2956 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 2957 { 2958 struct sip_softc *sc = (void *) self; 2959 2960 if (sc->sc_cfg & CFG_TBI_EN) { 2961 bus_addr_t tbireg; 2962 2963 if (phy != 0) 2964 return; 2965 2966 switch (reg) { 2967 case MII_BMCR: tbireg = SIP_TBICR; break; 2968 case MII_ANAR: tbireg = SIP_TANAR; break; 2969 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 2970 default: 2971 return; 2972 } 2973 2974 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 2975 return; 2976 } 2977 2978 mii_bitbang_writereg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2979 phy, reg, val); 2980 } 2981 2982 /* 2983 * sip_dp83815_mii_statchg: [mii interface function] 2984 * 2985 * Callback from MII layer when media changes. 2986 */ 2987 void 2988 SIP_DECL(dp83820_mii_statchg)(struct device *self) 2989 { 2990 struct sip_softc *sc = (struct sip_softc *) self; 2991 u_int32_t cfg; 2992 2993 /* 2994 * Update TXCFG for full-duplex operation. 2995 */ 2996 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2997 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 2998 else 2999 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3000 3001 /* 3002 * Update RXCFG for full-duplex or loopback. 3003 */ 3004 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3005 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3006 sc->sc_rxcfg |= RXCFG_ATX; 3007 else 3008 sc->sc_rxcfg &= ~RXCFG_ATX; 3009 3010 /* 3011 * Update CFG for MII/GMII. 3012 */ 3013 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3014 cfg = sc->sc_cfg | CFG_MODE_1000; 3015 else 3016 cfg = sc->sc_cfg; 3017 3018 /* 3019 * XXX 802.3x flow control. 3020 */ 3021 3022 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3023 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3024 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3025 } 3026 3027 /* 3028 * sip_dp83820_mii_bitbang_read: [mii bit-bang interface function] 3029 * 3030 * Read the MII serial port for the MII bit-bang module. 3031 */ 3032 u_int32_t 3033 SIP_DECL(dp83820_mii_bitbang_read)(struct device *self) 3034 { 3035 struct sip_softc *sc = (void *) self; 3036 3037 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3038 } 3039 3040 /* 3041 * sip_dp83820_mii_bitbang_write: [mii big-bang interface function] 3042 * 3043 * Write the MII serial port for the MII bit-bang module. 3044 */ 3045 void 3046 SIP_DECL(dp83820_mii_bitbang_write)(struct device *self, u_int32_t val) 3047 { 3048 struct sip_softc *sc = (void *) self; 3049 3050 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3051 } 3052 #else /* ! DP83820 */ 3053 /* 3054 * sip_sis900_mii_readreg: [mii interface function] 3055 * 3056 * Read a PHY register on the MII. 3057 */ 3058 int 3059 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 3060 { 3061 struct sip_softc *sc = (struct sip_softc *) self; 3062 u_int32_t enphy; 3063 3064 /* 3065 * The SiS 900 has only an internal PHY on the MII. Only allow 3066 * MII address 0. 3067 */ 3068 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 3069 sc->sc_rev < SIS_REV_635 && phy != 0) 3070 return (0); 3071 3072 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3073 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3074 ENPHY_RWCMD | ENPHY_ACCESS); 3075 do { 3076 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3077 } while (enphy & ENPHY_ACCESS); 3078 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3079 } 3080 3081 /* 3082 * sip_sis900_mii_writereg: [mii interface function] 3083 * 3084 * Write a PHY register on the MII. 3085 */ 3086 void 3087 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 3088 { 3089 struct sip_softc *sc = (struct sip_softc *) self; 3090 u_int32_t enphy; 3091 3092 /* 3093 * The SiS 900 has only an internal PHY on the MII. Only allow 3094 * MII address 0. 3095 */ 3096 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 3097 sc->sc_rev < SIS_REV_635 && phy != 0) 3098 return; 3099 3100 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3101 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3102 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3103 do { 3104 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3105 } while (enphy & ENPHY_ACCESS); 3106 } 3107 3108 /* 3109 * sip_sis900_mii_statchg: [mii interface function] 3110 * 3111 * Callback from MII layer when media changes. 3112 */ 3113 void 3114 SIP_DECL(sis900_mii_statchg)(struct device *self) 3115 { 3116 struct sip_softc *sc = (struct sip_softc *) self; 3117 u_int32_t flowctl; 3118 3119 /* 3120 * Update TXCFG for full-duplex operation. 3121 */ 3122 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3123 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3124 else 3125 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3126 3127 /* 3128 * Update RXCFG for full-duplex or loopback. 3129 */ 3130 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3131 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3132 sc->sc_rxcfg |= RXCFG_ATX; 3133 else 3134 sc->sc_rxcfg &= ~RXCFG_ATX; 3135 3136 /* 3137 * Update IMR for use of 802.3x flow control. 3138 */ 3139 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 3140 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3141 flowctl = FLOWCTL_FLOWEN; 3142 } else { 3143 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3144 flowctl = 0; 3145 } 3146 3147 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3148 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3149 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3150 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3151 } 3152 3153 /* 3154 * sip_dp83815_mii_readreg: [mii interface function] 3155 * 3156 * Read a PHY register on the MII. 3157 */ 3158 int 3159 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 3160 { 3161 struct sip_softc *sc = (struct sip_softc *) self; 3162 u_int32_t val; 3163 3164 /* 3165 * The DP83815 only has an internal PHY. Only allow 3166 * MII address 0. 3167 */ 3168 if (phy != 0) 3169 return (0); 3170 3171 /* 3172 * Apparently, after a reset, the DP83815 can take a while 3173 * to respond. During this recovery period, the BMSR returns 3174 * a value of 0. Catch this -- it's not supposed to happen 3175 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3176 * PHY to come back to life. 3177 * 3178 * This works out because the BMSR is the first register 3179 * read during the PHY probe process. 3180 */ 3181 do { 3182 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3183 } while (reg == MII_BMSR && val == 0); 3184 3185 return (val & 0xffff); 3186 } 3187 3188 /* 3189 * sip_dp83815_mii_writereg: [mii interface function] 3190 * 3191 * Write a PHY register to the MII. 3192 */ 3193 void 3194 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3195 { 3196 struct sip_softc *sc = (struct sip_softc *) self; 3197 3198 /* 3199 * The DP83815 only has an internal PHY. Only allow 3200 * MII address 0. 3201 */ 3202 if (phy != 0) 3203 return; 3204 3205 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3206 } 3207 3208 /* 3209 * sip_dp83815_mii_statchg: [mii interface function] 3210 * 3211 * Callback from MII layer when media changes. 3212 */ 3213 void 3214 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3215 { 3216 struct sip_softc *sc = (struct sip_softc *) self; 3217 3218 /* 3219 * Update TXCFG for full-duplex operation. 3220 */ 3221 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3222 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3223 else 3224 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3225 3226 /* 3227 * Update RXCFG for full-duplex or loopback. 3228 */ 3229 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3230 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3231 sc->sc_rxcfg |= RXCFG_ATX; 3232 else 3233 sc->sc_rxcfg &= ~RXCFG_ATX; 3234 3235 /* 3236 * XXX 802.3x flow control. 3237 */ 3238 3239 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3240 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3241 3242 /* 3243 * Some DP83815s experience problems when used with short 3244 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3245 * sequence adjusts the DSP's signal attenuation to fix the 3246 * problem. 3247 */ 3248 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3249 uint32_t reg; 3250 3251 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3252 3253 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3254 reg &= 0x0fff; 3255 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3256 delay(100); 3257 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3258 reg &= 0x00ff; 3259 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3260 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3261 0x00e8); 3262 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3263 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3264 reg | 0x20); 3265 } 3266 3267 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3268 } 3269 } 3270 #endif /* DP83820 */ 3271 3272 #if defined(DP83820) 3273 void 3274 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3275 const struct pci_attach_args *pa, u_int8_t *enaddr) 3276 { 3277 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3278 u_int8_t cksum, *e, match; 3279 int i; 3280 3281 /* 3282 * EEPROM data format for the DP83820 can be found in 3283 * the DP83820 manual, section 4.2.4. 3284 */ 3285 3286 SIP_DECL(read_eeprom)(sc, 0, 3287 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3288 3289 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3290 match = ~(match - 1); 3291 3292 cksum = 0x55; 3293 e = (u_int8_t *) eeprom_data; 3294 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3295 cksum += *e++; 3296 3297 if (cksum != match) 3298 printf("%s: Checksum (%x) mismatch (%x)", 3299 sc->sc_dev.dv_xname, cksum, match); 3300 3301 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3302 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3303 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3304 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3305 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3306 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3307 } 3308 #else /* ! DP83820 */ 3309 void 3310 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3311 const struct pci_attach_args *pa, u_int8_t *enaddr) 3312 { 3313 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3314 3315 switch (sc->sc_rev) { 3316 case SIS_REV_630S: 3317 case SIS_REV_630E: 3318 case SIS_REV_630EA1: 3319 case SIS_REV_630ET: 3320 case SIS_REV_635: 3321 /* 3322 * The MAC address for the on-board Ethernet of 3323 * the SiS 630 chipset is in the NVRAM. Kick 3324 * the chip into re-loading it from NVRAM, and 3325 * read the MAC address out of the filter registers. 3326 */ 3327 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3328 3329 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3330 RFCR_RFADDR_NODE0); 3331 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3332 0xffff; 3333 3334 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3335 RFCR_RFADDR_NODE2); 3336 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3337 0xffff; 3338 3339 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3340 RFCR_RFADDR_NODE4); 3341 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3342 0xffff; 3343 break; 3344 3345 default: 3346 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3347 sizeof(myea) / sizeof(myea[0]), myea); 3348 } 3349 3350 enaddr[0] = myea[0] & 0xff; 3351 enaddr[1] = myea[0] >> 8; 3352 enaddr[2] = myea[1] & 0xff; 3353 enaddr[3] = myea[1] >> 8; 3354 enaddr[4] = myea[2] & 0xff; 3355 enaddr[5] = myea[2] >> 8; 3356 } 3357 3358 /* Table and macro to bit-reverse an octet. */ 3359 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3360 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3361 3362 void 3363 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3364 const struct pci_attach_args *pa, u_int8_t *enaddr) 3365 { 3366 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3367 u_int8_t cksum, *e, match; 3368 int i; 3369 3370 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3371 sizeof(eeprom_data[0]), eeprom_data); 3372 3373 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3374 match = ~(match - 1); 3375 3376 cksum = 0x55; 3377 e = (u_int8_t *) eeprom_data; 3378 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3379 cksum += *e++; 3380 } 3381 if (cksum != match) { 3382 printf("%s: Checksum (%x) mismatch (%x)", 3383 sc->sc_dev.dv_xname, cksum, match); 3384 } 3385 3386 /* 3387 * Unrolled because it makes slightly more sense this way. 3388 * The DP83815 stores the MAC address in bit 0 of word 6 3389 * through bit 15 of word 8. 3390 */ 3391 ea = &eeprom_data[6]; 3392 enaddr[0] = ((*ea & 0x1) << 7); 3393 ea++; 3394 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3395 enaddr[1] = ((*ea & 0x1FE) >> 1); 3396 enaddr[2] = ((*ea & 0x1) << 7); 3397 ea++; 3398 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3399 enaddr[3] = ((*ea & 0x1FE) >> 1); 3400 enaddr[4] = ((*ea & 0x1) << 7); 3401 ea++; 3402 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3403 enaddr[5] = ((*ea & 0x1FE) >> 1); 3404 3405 /* 3406 * In case that's not weird enough, we also need to reverse 3407 * the bits in each byte. This all actually makes more sense 3408 * if you think about the EEPROM storage as an array of bits 3409 * being shifted into bytes, but that's not how we're looking 3410 * at it here... 3411 */ 3412 for (i = 0; i < 6 ;i++) 3413 enaddr[i] = bbr(enaddr[i]); 3414 } 3415 #endif /* DP83820 */ 3416 3417 /* 3418 * sip_mediastatus: [ifmedia interface function] 3419 * 3420 * Get the current interface media status. 3421 */ 3422 void 3423 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3424 { 3425 struct sip_softc *sc = ifp->if_softc; 3426 3427 mii_pollstat(&sc->sc_mii); 3428 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3429 ifmr->ifm_active = sc->sc_mii.mii_media_active; 3430 } 3431 3432 /* 3433 * sip_mediachange: [ifmedia interface function] 3434 * 3435 * Set hardware to newly-selected media. 3436 */ 3437 int 3438 SIP_DECL(mediachange)(struct ifnet *ifp) 3439 { 3440 struct sip_softc *sc = ifp->if_softc; 3441 3442 if (ifp->if_flags & IFF_UP) 3443 mii_mediachg(&sc->sc_mii); 3444 return (0); 3445 } 3446
Indexes created Wed Sep 24 02:09:48 GMT 2025