if_sip.c revision 1.83
1 /* $NetBSD: if_sip.c,v 1.83 2003/10/29 03:31:22 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.83 2003/10/29 03:31:22 mycroft Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <machine/bus.h> 116 #include <machine/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #ifdef DP83820 122 #include <dev/mii/mii_bitbang.h> 123 #endif /* DP83820 */ 124 125 #include <dev/pci/pcireg.h> 126 #include <dev/pci/pcivar.h> 127 #include <dev/pci/pcidevs.h> 128 129 #include <dev/pci/if_sipreg.h> 130 131 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 132 #define SIP_DECL(x) __CONCAT(gsip_,x) 133 #else /* SiS900 and DP83815 */ 134 #define SIP_DECL(x) __CONCAT(sip_,x) 135 #endif 136 137 #define SIP_STR(x) __STRING(SIP_DECL(x)) 138 139 /* 140 * Transmit descriptor list size. This is arbitrary, but allocate 141 * enough descriptors for 128 pending transmissions, and 8 segments 142 * per packet. This MUST work out to a power of 2. 143 */ 144 #define SIP_NTXSEGS 16 145 #define SIP_NTXSEGS_ALLOC 8 146 147 #define SIP_TXQUEUELEN 256 148 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 149 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 150 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 151 152 #if defined(DP83820) 153 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 154 #else 155 #define TX_DMAMAP_SIZE MCLBYTES 156 #endif 157 158 /* 159 * Receive descriptor list size. We have one Rx buffer per incoming 160 * packet, so this logic is a little simpler. 161 * 162 * Actually, on the DP83820, we allow the packet to consume more than 163 * one buffer, in order to support jumbo Ethernet frames. In that 164 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 165 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 166 * so we'd better be quick about handling receive interrupts. 167 */ 168 #if defined(DP83820) 169 #define SIP_NRXDESC 256 170 #else 171 #define SIP_NRXDESC 128 172 #endif /* DP83820 */ 173 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 174 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 175 176 /* 177 * Control structures are DMA'd to the SiS900 chip. We allocate them in 178 * a single clump that maps to a single DMA segment to make several things 179 * easier. 180 */ 181 struct sip_control_data { 182 /* 183 * The transmit descriptors. 184 */ 185 struct sip_desc scd_txdescs[SIP_NTXDESC]; 186 187 /* 188 * The receive descriptors. 189 */ 190 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 191 }; 192 193 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 194 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 195 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 196 197 /* 198 * Software state for transmit jobs. 199 */ 200 struct sip_txsoft { 201 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 202 bus_dmamap_t txs_dmamap; /* our DMA map */ 203 int txs_firstdesc; /* first descriptor in packet */ 204 int txs_lastdesc; /* last descriptor in packet */ 205 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 206 }; 207 208 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 209 210 /* 211 * Software state for receive jobs. 212 */ 213 struct sip_rxsoft { 214 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 215 bus_dmamap_t rxs_dmamap; /* our DMA map */ 216 }; 217 218 /* 219 * Software state per device. 220 */ 221 struct sip_softc { 222 struct device sc_dev; /* generic device information */ 223 bus_space_tag_t sc_st; /* bus space tag */ 224 bus_space_handle_t sc_sh; /* bus space handle */ 225 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 226 struct ethercom sc_ethercom; /* ethernet common data */ 227 void *sc_sdhook; /* shutdown hook */ 228 229 const struct sip_product *sc_model; /* which model are we? */ 230 int sc_rev; /* chip revision */ 231 232 void *sc_ih; /* interrupt cookie */ 233 234 struct mii_data sc_mii; /* MII/media information */ 235 236 struct callout sc_tick_ch; /* tick callout */ 237 238 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 239 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 240 241 /* 242 * Software state for transmit and receive descriptors. 243 */ 244 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 245 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 246 247 /* 248 * Control data structures. 249 */ 250 struct sip_control_data *sc_control_data; 251 #define sc_txdescs sc_control_data->scd_txdescs 252 #define sc_rxdescs sc_control_data->scd_rxdescs 253 254 #ifdef SIP_EVENT_COUNTERS 255 /* 256 * Event counters. 257 */ 258 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 259 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 260 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 261 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 262 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 263 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 264 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 265 #ifdef DP83820 266 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 267 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 268 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 269 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 270 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 271 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 272 #endif /* DP83820 */ 273 #endif /* SIP_EVENT_COUNTERS */ 274 275 u_int32_t sc_txcfg; /* prototype TXCFG register */ 276 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 277 u_int32_t sc_imr; /* prototype IMR register */ 278 u_int32_t sc_rfcr; /* prototype RFCR register */ 279 280 u_int32_t sc_cfg; /* prototype CFG register */ 281 282 #ifdef DP83820 283 u_int32_t sc_gpior; /* prototype GPIOR register */ 284 #endif /* DP83820 */ 285 286 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 287 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 288 289 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 290 291 int sc_flags; /* misc. flags; see below */ 292 293 int sc_txfree; /* number of free Tx descriptors */ 294 int sc_txnext; /* next ready Tx descriptor */ 295 int sc_txwin; /* Tx descriptors since last intr */ 296 297 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 298 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 299 300 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 301 #if defined(DP83820) 302 int sc_rxdiscard; 303 int sc_rxlen; 304 struct mbuf *sc_rxhead; 305 struct mbuf *sc_rxtail; 306 struct mbuf **sc_rxtailp; 307 #endif /* DP83820 */ 308 309 #if NRND > 0 310 rndsource_element_t rnd_source; /* random source */ 311 #endif 312 }; 313 314 /* sc_flags */ 315 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 316 317 #ifdef DP83820 318 #define SIP_RXCHAIN_RESET(sc) \ 319 do { \ 320 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 321 *(sc)->sc_rxtailp = NULL; \ 322 (sc)->sc_rxlen = 0; \ 323 } while (/*CONSTCOND*/0) 324 325 #define SIP_RXCHAIN_LINK(sc, m) \ 326 do { \ 327 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 328 (sc)->sc_rxtailp = &(m)->m_next; \ 329 } while (/*CONSTCOND*/0) 330 #endif /* DP83820 */ 331 332 #ifdef SIP_EVENT_COUNTERS 333 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 334 #else 335 #define SIP_EVCNT_INCR(ev) /* nothing */ 336 #endif 337 338 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 339 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 340 341 #define SIP_CDTXSYNC(sc, x, n, ops) \ 342 do { \ 343 int __x, __n; \ 344 \ 345 __x = (x); \ 346 __n = (n); \ 347 \ 348 /* If it will wrap around, sync to the end of the ring. */ \ 349 if ((__x + __n) > SIP_NTXDESC) { \ 350 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 351 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 352 (SIP_NTXDESC - __x), (ops)); \ 353 __n -= (SIP_NTXDESC - __x); \ 354 __x = 0; \ 355 } \ 356 \ 357 /* Now sync whatever is left. */ \ 358 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 359 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 360 } while (0) 361 362 #define SIP_CDRXSYNC(sc, x, ops) \ 363 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 364 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 365 366 #ifdef DP83820 367 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 368 #define SIP_RXBUF_LEN (MCLBYTES - 4) 369 #else 370 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 371 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 372 #endif 373 #define SIP_INIT_RXDESC(sc, x) \ 374 do { \ 375 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 376 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 377 \ 378 __sipd->sipd_link = \ 379 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 380 __sipd->sipd_bufptr = \ 381 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 382 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 383 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 384 SIP_INIT_RXDESC_EXTSTS \ 385 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 386 } while (0) 387 388 #define SIP_CHIP_VERS(sc, v, p, r) \ 389 ((sc)->sc_model->sip_vendor == (v) && \ 390 (sc)->sc_model->sip_product == (p) && \ 391 (sc)->sc_rev == (r)) 392 393 #define SIP_CHIP_MODEL(sc, v, p) \ 394 ((sc)->sc_model->sip_vendor == (v) && \ 395 (sc)->sc_model->sip_product == (p)) 396 397 #if !defined(DP83820) 398 #define SIP_SIS900_REV(sc, rev) \ 399 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 400 #endif 401 402 #define SIP_TIMEOUT 1000 403 404 void SIP_DECL(start)(struct ifnet *); 405 void SIP_DECL(watchdog)(struct ifnet *); 406 int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 407 int SIP_DECL(init)(struct ifnet *); 408 void SIP_DECL(stop)(struct ifnet *, int); 409 410 void SIP_DECL(shutdown)(void *); 411 412 void SIP_DECL(reset)(struct sip_softc *); 413 void SIP_DECL(rxdrain)(struct sip_softc *); 414 int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 415 void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, u_int16_t *); 416 void SIP_DECL(tick)(void *); 417 418 #if !defined(DP83820) 419 void SIP_DECL(sis900_set_filter)(struct sip_softc *); 420 #endif /* ! DP83820 */ 421 void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 422 423 #if defined(DP83820) 424 void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 425 const struct pci_attach_args *, u_int8_t *); 426 #else 427 void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 428 const struct pci_attach_args *, u_int8_t *); 429 void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 430 const struct pci_attach_args *, u_int8_t *); 431 #endif /* DP83820 */ 432 433 int SIP_DECL(intr)(void *); 434 void SIP_DECL(txintr)(struct sip_softc *); 435 void SIP_DECL(rxintr)(struct sip_softc *); 436 437 #if defined(DP83820) 438 int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 439 void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 440 void SIP_DECL(dp83820_mii_statchg)(struct device *); 441 #else 442 int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 443 void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 444 void SIP_DECL(sis900_mii_statchg)(struct device *); 445 446 int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 447 void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 448 void SIP_DECL(dp83815_mii_statchg)(struct device *); 449 #endif /* DP83820 */ 450 451 int SIP_DECL(mediachange)(struct ifnet *); 452 void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 453 454 int SIP_DECL(match)(struct device *, struct cfdata *, void *); 455 void SIP_DECL(attach)(struct device *, struct device *, void *); 456 457 int SIP_DECL(copy_small) = 0; 458 459 #ifdef DP83820 460 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 461 gsip_match, gsip_attach, NULL, NULL); 462 #else 463 CFATTACH_DECL(sip, sizeof(struct sip_softc), 464 sip_match, sip_attach, NULL, NULL); 465 #endif 466 467 /* 468 * Descriptions of the variants of the SiS900. 469 */ 470 struct sip_variant { 471 int (*sipv_mii_readreg)(struct device *, int, int); 472 void (*sipv_mii_writereg)(struct device *, int, int, int); 473 void (*sipv_mii_statchg)(struct device *); 474 void (*sipv_set_filter)(struct sip_softc *); 475 void (*sipv_read_macaddr)(struct sip_softc *, 476 const struct pci_attach_args *, u_int8_t *); 477 }; 478 479 #if defined(DP83820) 480 u_int32_t SIP_DECL(dp83820_mii_bitbang_read)(struct device *); 481 void SIP_DECL(dp83820_mii_bitbang_write)(struct device *, u_int32_t); 482 483 const struct mii_bitbang_ops SIP_DECL(dp83820_mii_bitbang_ops) = { 484 SIP_DECL(dp83820_mii_bitbang_read), 485 SIP_DECL(dp83820_mii_bitbang_write), 486 { 487 EROMAR_MDIO, /* MII_BIT_MDO */ 488 EROMAR_MDIO, /* MII_BIT_MDI */ 489 EROMAR_MDC, /* MII_BIT_MDC */ 490 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 491 0, /* MII_BIT_DIR_PHY_HOST */ 492 } 493 }; 494 #endif /* DP83820 */ 495 496 #if defined(DP83820) 497 const struct sip_variant SIP_DECL(variant_dp83820) = { 498 SIP_DECL(dp83820_mii_readreg), 499 SIP_DECL(dp83820_mii_writereg), 500 SIP_DECL(dp83820_mii_statchg), 501 SIP_DECL(dp83815_set_filter), 502 SIP_DECL(dp83820_read_macaddr), 503 }; 504 #else 505 const struct sip_variant SIP_DECL(variant_sis900) = { 506 SIP_DECL(sis900_mii_readreg), 507 SIP_DECL(sis900_mii_writereg), 508 SIP_DECL(sis900_mii_statchg), 509 SIP_DECL(sis900_set_filter), 510 SIP_DECL(sis900_read_macaddr), 511 }; 512 513 const struct sip_variant SIP_DECL(variant_dp83815) = { 514 SIP_DECL(dp83815_mii_readreg), 515 SIP_DECL(dp83815_mii_writereg), 516 SIP_DECL(dp83815_mii_statchg), 517 SIP_DECL(dp83815_set_filter), 518 SIP_DECL(dp83815_read_macaddr), 519 }; 520 #endif /* DP83820 */ 521 522 /* 523 * Devices supported by this driver. 524 */ 525 const struct sip_product { 526 pci_vendor_id_t sip_vendor; 527 pci_product_id_t sip_product; 528 const char *sip_name; 529 const struct sip_variant *sip_variant; 530 } SIP_DECL(products)[] = { 531 #if defined(DP83820) 532 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 533 "NatSemi DP83820 Gigabit Ethernet", 534 &SIP_DECL(variant_dp83820) }, 535 #else 536 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 537 "SiS 900 10/100 Ethernet", 538 &SIP_DECL(variant_sis900) }, 539 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 540 "SiS 7016 10/100 Ethernet", 541 &SIP_DECL(variant_sis900) }, 542 543 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 544 "NatSemi DP83815 10/100 Ethernet", 545 &SIP_DECL(variant_dp83815) }, 546 #endif /* DP83820 */ 547 548 { 0, 0, 549 NULL, 550 NULL }, 551 }; 552 553 static const struct sip_product * 554 SIP_DECL(lookup)(const struct pci_attach_args *pa) 555 { 556 const struct sip_product *sip; 557 558 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 559 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 560 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 561 return (sip); 562 } 563 return (NULL); 564 } 565 566 #ifdef DP83820 567 /* 568 * I really hate stupid hardware vendors. There's a bit in the EEPROM 569 * which indicates if the card can do 64-bit data transfers. Unfortunately, 570 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 571 * which means we try to use 64-bit data transfers on those cards if we 572 * happen to be plugged into a 32-bit slot. 573 * 574 * What we do is use this table of cards known to be 64-bit cards. If 575 * you have a 64-bit card who's subsystem ID is not listed in this table, 576 * send the output of "pcictl dump ..." of the device to me so that your 577 * card will use the 64-bit data path when plugged into a 64-bit slot. 578 * 579 * -- Jason R. Thorpe <thorpej (at) netbsd.org> 580 * June 30, 2002 581 */ 582 static int 583 SIP_DECL(check_64bit)(const struct pci_attach_args *pa) 584 { 585 static const struct { 586 pci_vendor_id_t c64_vendor; 587 pci_product_id_t c64_product; 588 } card64[] = { 589 /* Asante GigaNIX */ 590 { 0x128a, 0x0002 }, 591 592 /* Accton EN1407-T, Planex GN-1000TE */ 593 { 0x1113, 0x1407 }, 594 595 /* Netgear GA-621 */ 596 { 0x1385, 0x621a }, 597 598 /* SMC EZ Card */ 599 { 0x10b8, 0x9462 }, 600 601 { 0, 0} 602 }; 603 pcireg_t subsys; 604 int i; 605 606 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 607 608 for (i = 0; card64[i].c64_vendor != 0; i++) { 609 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 610 PCI_PRODUCT(subsys) == card64[i].c64_product) 611 return (1); 612 } 613 614 return (0); 615 } 616 #endif /* DP83820 */ 617 618 int 619 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 620 { 621 struct pci_attach_args *pa = aux; 622 623 if (SIP_DECL(lookup)(pa) != NULL) 624 return (1); 625 626 return (0); 627 } 628 629 void 630 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 631 { 632 struct sip_softc *sc = (struct sip_softc *) self; 633 struct pci_attach_args *pa = aux; 634 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 635 pci_chipset_tag_t pc = pa->pa_pc; 636 pci_intr_handle_t ih; 637 const char *intrstr = NULL; 638 bus_space_tag_t iot, memt; 639 bus_space_handle_t ioh, memh; 640 bus_dma_segment_t seg; 641 int ioh_valid, memh_valid; 642 int i, rseg, error; 643 const struct sip_product *sip; 644 pcireg_t pmode; 645 u_int8_t enaddr[ETHER_ADDR_LEN]; 646 int pmreg; 647 #ifdef DP83820 648 pcireg_t memtype; 649 u_int32_t reg; 650 #endif /* DP83820 */ 651 652 callout_init(&sc->sc_tick_ch); 653 654 sip = SIP_DECL(lookup)(pa); 655 if (sip == NULL) { 656 printf("\n"); 657 panic(SIP_STR(attach) ": impossible"); 658 } 659 sc->sc_rev = PCI_REVISION(pa->pa_class); 660 661 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 662 663 sc->sc_model = sip; 664 665 /* 666 * XXX Work-around broken PXE firmware on some boards. 667 * 668 * The DP83815 shares an address decoder with the MEM BAR 669 * and the ROM BAR. Make sure the ROM BAR is disabled, 670 * so that memory mapped access works. 671 */ 672 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 673 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 674 ~PCI_MAPREG_ROM_ENABLE); 675 676 /* 677 * Map the device. 678 */ 679 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 680 PCI_MAPREG_TYPE_IO, 0, 681 &iot, &ioh, NULL, NULL) == 0); 682 #ifdef DP83820 683 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 684 switch (memtype) { 685 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 686 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 687 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 688 memtype, 0, &memt, &memh, NULL, NULL) == 0); 689 break; 690 default: 691 memh_valid = 0; 692 } 693 #else 694 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 695 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 696 &memt, &memh, NULL, NULL) == 0); 697 #endif /* DP83820 */ 698 699 if (memh_valid) { 700 sc->sc_st = memt; 701 sc->sc_sh = memh; 702 } else if (ioh_valid) { 703 sc->sc_st = iot; 704 sc->sc_sh = ioh; 705 } else { 706 printf("%s: unable to map device registers\n", 707 sc->sc_dev.dv_xname); 708 return; 709 } 710 711 sc->sc_dmat = pa->pa_dmat; 712 713 /* 714 * Make sure bus mastering is enabled. Also make sure 715 * Write/Invalidate is enabled if we're allowed to use it. 716 */ 717 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 718 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 719 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 720 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 721 pmreg | PCI_COMMAND_MASTER_ENABLE); 722 723 /* Get it out of power save mode if needed. */ 724 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 725 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 726 PCI_PMCSR_STATE_MASK; 727 if (pmode == PCI_PMCSR_STATE_D3) { 728 /* 729 * The card has lost all configuration data in 730 * this state, so punt. 731 */ 732 printf("%s: unable to wake up from power state D3\n", 733 sc->sc_dev.dv_xname); 734 return; 735 } 736 if (pmode != PCI_PMCSR_STATE_D0) { 737 printf("%s: waking up from power state D%d\n", 738 sc->sc_dev.dv_xname, pmode); 739 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 740 PCI_PMCSR_STATE_D0); 741 } 742 } 743 744 /* 745 * Map and establish our interrupt. 746 */ 747 if (pci_intr_map(pa, &ih)) { 748 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 749 return; 750 } 751 intrstr = pci_intr_string(pc, ih); 752 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 753 if (sc->sc_ih == NULL) { 754 printf("%s: unable to establish interrupt", 755 sc->sc_dev.dv_xname); 756 if (intrstr != NULL) 757 printf(" at %s", intrstr); 758 printf("\n"); 759 return; 760 } 761 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 762 763 SIMPLEQ_INIT(&sc->sc_txfreeq); 764 SIMPLEQ_INIT(&sc->sc_txdirtyq); 765 766 /* 767 * Allocate the control data structures, and create and load the 768 * DMA map for it. 769 */ 770 if ((error = bus_dmamem_alloc(sc->sc_dmat, 771 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 772 0)) != 0) { 773 printf("%s: unable to allocate control data, error = %d\n", 774 sc->sc_dev.dv_xname, error); 775 goto fail_0; 776 } 777 778 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 779 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 780 BUS_DMA_COHERENT)) != 0) { 781 printf("%s: unable to map control data, error = %d\n", 782 sc->sc_dev.dv_xname, error); 783 goto fail_1; 784 } 785 786 if ((error = bus_dmamap_create(sc->sc_dmat, 787 sizeof(struct sip_control_data), 1, 788 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 789 printf("%s: unable to create control data DMA map, " 790 "error = %d\n", sc->sc_dev.dv_xname, error); 791 goto fail_2; 792 } 793 794 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 795 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 796 0)) != 0) { 797 printf("%s: unable to load control data DMA map, error = %d\n", 798 sc->sc_dev.dv_xname, error); 799 goto fail_3; 800 } 801 802 /* 803 * Create the transmit buffer DMA maps. 804 */ 805 for (i = 0; i < SIP_TXQUEUELEN; i++) { 806 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 807 SIP_NTXSEGS, MCLBYTES, 0, 0, 808 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 809 printf("%s: unable to create tx DMA map %d, " 810 "error = %d\n", sc->sc_dev.dv_xname, i, error); 811 goto fail_4; 812 } 813 } 814 815 /* 816 * Create the receive buffer DMA maps. 817 */ 818 for (i = 0; i < SIP_NRXDESC; i++) { 819 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 820 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 821 printf("%s: unable to create rx DMA map %d, " 822 "error = %d\n", sc->sc_dev.dv_xname, i, error); 823 goto fail_5; 824 } 825 sc->sc_rxsoft[i].rxs_mbuf = NULL; 826 } 827 828 /* 829 * Reset the chip to a known state. 830 */ 831 SIP_DECL(reset)(sc); 832 833 /* 834 * Read the Ethernet address from the EEPROM. This might 835 * also fetch other stuff from the EEPROM and stash it 836 * in the softc. 837 */ 838 sc->sc_cfg = 0; 839 #if !defined(DP83820) 840 if (SIP_SIS900_REV(sc,SIS_REV_635) || 841 SIP_SIS900_REV(sc,SIS_REV_900B)) 842 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 843 #endif 844 845 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 846 847 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 848 ether_sprintf(enaddr)); 849 850 /* 851 * Initialize the configuration register: aggressive PCI 852 * bus request algorithm, default backoff, default OW timer, 853 * default parity error detection. 854 * 855 * NOTE: "Big endian mode" is useless on the SiS900 and 856 * friends -- it affects packet data, not descriptors. 857 */ 858 #ifdef DP83820 859 /* 860 * Cause the chip to load configuration data from the EEPROM. 861 */ 862 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 863 for (i = 0; i < 10000; i++) { 864 delay(10); 865 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 866 PTSCR_EELOAD_EN) == 0) 867 break; 868 } 869 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 870 PTSCR_EELOAD_EN) { 871 printf("%s: timeout loading configuration from EEPROM\n", 872 sc->sc_dev.dv_xname); 873 return; 874 } 875 876 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 877 878 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 879 if (reg & CFG_PCI64_DET) { 880 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 881 /* 882 * Check to see if this card is 64-bit. If so, enable 64-bit 883 * data transfers. 884 * 885 * We can't use the DATA64_EN bit in the EEPROM, because 886 * vendors of 32-bit cards fail to clear that bit in many 887 * cases (yet the card still detects that it's in a 64-bit 888 * slot; go figure). 889 */ 890 if (SIP_DECL(check_64bit)(pa)) { 891 sc->sc_cfg |= CFG_DATA64_EN; 892 printf(", using 64-bit data transfers"); 893 } 894 printf("\n"); 895 } 896 897 /* 898 * XXX Need some PCI flags indicating support for 899 * XXX 64-bit addressing. 900 */ 901 #if 0 902 if (reg & CFG_M64ADDR) 903 sc->sc_cfg |= CFG_M64ADDR; 904 if (reg & CFG_T64ADDR) 905 sc->sc_cfg |= CFG_T64ADDR; 906 #endif 907 908 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 909 const char *sep = ""; 910 printf("%s: using ", sc->sc_dev.dv_xname); 911 if (reg & CFG_EXT_125) { 912 sc->sc_cfg |= CFG_EXT_125; 913 printf("%s125MHz clock", sep); 914 sep = ", "; 915 } 916 if (reg & CFG_TBI_EN) { 917 sc->sc_cfg |= CFG_TBI_EN; 918 printf("%sten-bit interface", sep); 919 sep = ", "; 920 } 921 printf("\n"); 922 } 923 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 924 (reg & CFG_MRM_DIS) != 0) 925 sc->sc_cfg |= CFG_MRM_DIS; 926 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 927 (reg & CFG_MWI_DIS) != 0) 928 sc->sc_cfg |= CFG_MWI_DIS; 929 930 /* 931 * Use the extended descriptor format on the DP83820. This 932 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 933 * checksumming. 934 */ 935 sc->sc_cfg |= CFG_EXTSTS_EN; 936 #endif /* DP83820 */ 937 938 /* 939 * Initialize our media structures and probe the MII. 940 */ 941 sc->sc_mii.mii_ifp = ifp; 942 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 943 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 944 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 945 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, SIP_DECL(mediachange), 946 SIP_DECL(mediastatus)); 947 948 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 949 MII_OFFSET_ANY, 0); 950 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 951 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 952 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 953 } else 954 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 955 956 ifp = &sc->sc_ethercom.ec_if; 957 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 958 ifp->if_softc = sc; 959 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 960 ifp->if_ioctl = SIP_DECL(ioctl); 961 ifp->if_start = SIP_DECL(start); 962 ifp->if_watchdog = SIP_DECL(watchdog); 963 ifp->if_init = SIP_DECL(init); 964 ifp->if_stop = SIP_DECL(stop); 965 IFQ_SET_READY(&ifp->if_snd); 966 967 /* 968 * We can support 802.1Q VLAN-sized frames. 969 */ 970 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 971 972 #ifdef DP83820 973 /* 974 * And the DP83820 can do VLAN tagging in hardware, and 975 * support the jumbo Ethernet MTU. 976 */ 977 sc->sc_ethercom.ec_capabilities |= 978 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 979 980 /* 981 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 982 * in hardware. 983 */ 984 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 985 IFCAP_CSUM_UDPv4; 986 #endif /* DP83820 */ 987 988 /* 989 * Attach the interface. 990 */ 991 if_attach(ifp); 992 ether_ifattach(ifp, enaddr); 993 #if NRND > 0 994 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 995 RND_TYPE_NET, 0); 996 #endif 997 998 /* 999 * The number of bytes that must be available in 1000 * the Tx FIFO before the bus master can DMA more 1001 * data into the FIFO. 1002 */ 1003 sc->sc_tx_fill_thresh = 64 / 32; 1004 1005 /* 1006 * Start at a drain threshold of 512 bytes. We will 1007 * increase it if a DMA underrun occurs. 1008 * 1009 * XXX The minimum value of this variable should be 1010 * tuned. We may be able to improve performance 1011 * by starting with a lower value. That, however, 1012 * may trash the first few outgoing packets if the 1013 * PCI bus is saturated. 1014 */ 1015 sc->sc_tx_drain_thresh = 1504 / 32; 1016 1017 /* 1018 * Initialize the Rx FIFO drain threshold. 1019 * 1020 * This is in units of 8 bytes. 1021 * 1022 * We should never set this value lower than 2; 14 bytes are 1023 * required to filter the packet. 1024 */ 1025 sc->sc_rx_drain_thresh = 128 / 8; 1026 1027 #ifdef SIP_EVENT_COUNTERS 1028 /* 1029 * Attach event counters. 1030 */ 1031 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1032 NULL, sc->sc_dev.dv_xname, "txsstall"); 1033 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1034 NULL, sc->sc_dev.dv_xname, "txdstall"); 1035 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1036 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1037 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1038 NULL, sc->sc_dev.dv_xname, "txdintr"); 1039 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1040 NULL, sc->sc_dev.dv_xname, "txiintr"); 1041 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1042 NULL, sc->sc_dev.dv_xname, "rxintr"); 1043 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1044 NULL, sc->sc_dev.dv_xname, "hiberr"); 1045 #ifdef DP83820 1046 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1047 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1048 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1049 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1050 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1051 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1052 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1053 NULL, sc->sc_dev.dv_xname, "txipsum"); 1054 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1055 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1056 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1057 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1058 #endif /* DP83820 */ 1059 #endif /* SIP_EVENT_COUNTERS */ 1060 1061 /* 1062 * Make sure the interface is shutdown during reboot. 1063 */ 1064 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 1065 if (sc->sc_sdhook == NULL) 1066 printf("%s: WARNING: unable to establish shutdown hook\n", 1067 sc->sc_dev.dv_xname); 1068 return; 1069 1070 /* 1071 * Free any resources we've allocated during the failed attach 1072 * attempt. Do this in reverse order and fall through. 1073 */ 1074 fail_5: 1075 for (i = 0; i < SIP_NRXDESC; i++) { 1076 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1077 bus_dmamap_destroy(sc->sc_dmat, 1078 sc->sc_rxsoft[i].rxs_dmamap); 1079 } 1080 fail_4: 1081 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1082 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1083 bus_dmamap_destroy(sc->sc_dmat, 1084 sc->sc_txsoft[i].txs_dmamap); 1085 } 1086 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1087 fail_3: 1088 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1089 fail_2: 1090 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1091 sizeof(struct sip_control_data)); 1092 fail_1: 1093 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1094 fail_0: 1095 return; 1096 } 1097 1098 /* 1099 * sip_shutdown: 1100 * 1101 * Make sure the interface is stopped at reboot time. 1102 */ 1103 void 1104 SIP_DECL(shutdown)(void *arg) 1105 { 1106 struct sip_softc *sc = arg; 1107 1108 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1109 } 1110 1111 /* 1112 * sip_start: [ifnet interface function] 1113 * 1114 * Start packet transmission on the interface. 1115 */ 1116 void 1117 SIP_DECL(start)(struct ifnet *ifp) 1118 { 1119 struct sip_softc *sc = ifp->if_softc; 1120 struct mbuf *m0; 1121 #ifndef DP83820 1122 struct mbuf *m; 1123 #endif 1124 struct sip_txsoft *txs; 1125 bus_dmamap_t dmamap; 1126 int error, nexttx, lasttx, seg; 1127 int ofree = sc->sc_txfree; 1128 #if 0 1129 int firsttx = sc->sc_txnext; 1130 #endif 1131 #ifdef DP83820 1132 struct m_tag *mtag; 1133 u_int32_t extsts; 1134 #endif 1135 1136 /* 1137 * If we've been told to pause, don't transmit any more packets. 1138 */ 1139 if (sc->sc_flags & SIPF_PAUSED) 1140 ifp->if_flags |= IFF_OACTIVE; 1141 1142 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1143 return; 1144 1145 /* 1146 * Loop through the send queue, setting up transmit descriptors 1147 * until we drain the queue, or use up all available transmit 1148 * descriptors. 1149 */ 1150 for (;;) { 1151 /* Get a work queue entry. */ 1152 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1153 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1154 break; 1155 } 1156 1157 /* 1158 * Grab a packet off the queue. 1159 */ 1160 IFQ_POLL(&ifp->if_snd, m0); 1161 if (m0 == NULL) 1162 break; 1163 #ifndef DP83820 1164 m = NULL; 1165 #endif 1166 1167 dmamap = txs->txs_dmamap; 1168 1169 #ifdef DP83820 1170 /* 1171 * Load the DMA map. If this fails, the packet either 1172 * didn't fit in the allotted number of segments, or we 1173 * were short on resources. For the too-many-segments 1174 * case, we simply report an error and drop the packet, 1175 * since we can't sanely copy a jumbo packet to a single 1176 * buffer. 1177 */ 1178 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1179 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1180 if (error) { 1181 if (error == EFBIG) { 1182 printf("%s: Tx packet consumes too many " 1183 "DMA segments, dropping...\n", 1184 sc->sc_dev.dv_xname); 1185 IFQ_DEQUEUE(&ifp->if_snd, m0); 1186 m_freem(m0); 1187 continue; 1188 } 1189 /* 1190 * Short on resources, just stop for now. 1191 */ 1192 break; 1193 } 1194 #else /* DP83820 */ 1195 /* 1196 * Load the DMA map. If this fails, the packet either 1197 * didn't fit in the alloted number of segments, or we 1198 * were short on resources. In this case, we'll copy 1199 * and try again. 1200 */ 1201 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1202 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1203 MGETHDR(m, M_DONTWAIT, MT_DATA); 1204 if (m == NULL) { 1205 printf("%s: unable to allocate Tx mbuf\n", 1206 sc->sc_dev.dv_xname); 1207 break; 1208 } 1209 if (m0->m_pkthdr.len > MHLEN) { 1210 MCLGET(m, M_DONTWAIT); 1211 if ((m->m_flags & M_EXT) == 0) { 1212 printf("%s: unable to allocate Tx " 1213 "cluster\n", sc->sc_dev.dv_xname); 1214 m_freem(m); 1215 break; 1216 } 1217 } 1218 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1219 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1220 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1221 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1222 if (error) { 1223 printf("%s: unable to load Tx buffer, " 1224 "error = %d\n", sc->sc_dev.dv_xname, error); 1225 break; 1226 } 1227 } 1228 #endif /* DP83820 */ 1229 1230 /* 1231 * Ensure we have enough descriptors free to describe 1232 * the packet. Note, we always reserve one descriptor 1233 * at the end of the ring as a termination point, to 1234 * prevent wrap-around. 1235 */ 1236 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1237 /* 1238 * Not enough free descriptors to transmit this 1239 * packet. We haven't committed anything yet, 1240 * so just unload the DMA map, put the packet 1241 * back on the queue, and punt. Notify the upper 1242 * layer that there are not more slots left. 1243 * 1244 * XXX We could allocate an mbuf and copy, but 1245 * XXX is it worth it? 1246 */ 1247 ifp->if_flags |= IFF_OACTIVE; 1248 bus_dmamap_unload(sc->sc_dmat, dmamap); 1249 #ifndef DP83820 1250 if (m != NULL) 1251 m_freem(m); 1252 #endif 1253 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1254 break; 1255 } 1256 1257 IFQ_DEQUEUE(&ifp->if_snd, m0); 1258 #ifndef DP83820 1259 if (m != NULL) { 1260 m_freem(m0); 1261 m0 = m; 1262 } 1263 #endif 1264 1265 /* 1266 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1267 */ 1268 1269 /* Sync the DMA map. */ 1270 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1271 BUS_DMASYNC_PREWRITE); 1272 1273 /* 1274 * Initialize the transmit descriptors. 1275 */ 1276 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1277 seg < dmamap->dm_nsegs; 1278 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1279 /* 1280 * If this is the first descriptor we're 1281 * enqueueing, don't set the OWN bit just 1282 * yet. That could cause a race condition. 1283 * We'll do it below. 1284 */ 1285 sc->sc_txdescs[nexttx].sipd_bufptr = 1286 htole32(dmamap->dm_segs[seg].ds_addr); 1287 sc->sc_txdescs[nexttx].sipd_cmdsts = 1288 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1289 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1290 #ifdef DP83820 1291 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1292 #endif /* DP83820 */ 1293 lasttx = nexttx; 1294 } 1295 1296 /* Clear the MORE bit on the last segment. */ 1297 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1298 1299 /* 1300 * If we're in the interrupt delay window, delay the 1301 * interrupt. 1302 */ 1303 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1304 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1305 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1306 htole32(CMDSTS_INTR); 1307 sc->sc_txwin = 0; 1308 } 1309 1310 #ifdef DP83820 1311 /* 1312 * If VLANs are enabled and the packet has a VLAN tag, set 1313 * up the descriptor to encapsulate the packet for us. 1314 * 1315 * This apparently has to be on the last descriptor of 1316 * the packet. 1317 */ 1318 if (sc->sc_ethercom.ec_nvlans != 0 && 1319 (mtag = m_tag_find(m0, PACKET_TAG_VLAN, NULL)) != NULL) { 1320 sc->sc_txdescs[lasttx].sipd_extsts |= 1321 htole32(EXTSTS_VPKT | 1322 (*(u_int *)(mtag + 1) & EXTSTS_VTCI)); 1323 } 1324 1325 /* 1326 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1327 * checksumming, set up the descriptor to do this work 1328 * for us. 1329 * 1330 * This apparently has to be on the first descriptor of 1331 * the packet. 1332 * 1333 * Byte-swap constants so the compiler can optimize. 1334 */ 1335 extsts = 0; 1336 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1337 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1338 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1339 extsts |= htole32(EXTSTS_IPPKT); 1340 } 1341 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1342 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1343 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1344 extsts |= htole32(EXTSTS_TCPPKT); 1345 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1346 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1347 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1348 extsts |= htole32(EXTSTS_UDPPKT); 1349 } 1350 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1351 #endif /* DP83820 */ 1352 1353 /* Sync the descriptors we're using. */ 1354 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1355 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1356 1357 /* 1358 * The entire packet is set up. Give the first descrptor 1359 * to the chip now. 1360 */ 1361 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1362 htole32(CMDSTS_OWN); 1363 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1364 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1365 1366 /* 1367 * Store a pointer to the packet so we can free it later, 1368 * and remember what txdirty will be once the packet is 1369 * done. 1370 */ 1371 txs->txs_mbuf = m0; 1372 txs->txs_firstdesc = sc->sc_txnext; 1373 txs->txs_lastdesc = lasttx; 1374 1375 /* Advance the tx pointer. */ 1376 sc->sc_txfree -= dmamap->dm_nsegs; 1377 sc->sc_txnext = nexttx; 1378 1379 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1380 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1381 1382 #if NBPFILTER > 0 1383 /* 1384 * Pass the packet to any BPF listeners. 1385 */ 1386 if (ifp->if_bpf) 1387 bpf_mtap(ifp->if_bpf, m0); 1388 #endif /* NBPFILTER > 0 */ 1389 } 1390 1391 if (txs == NULL || sc->sc_txfree == 0) { 1392 /* No more slots left; notify upper layer. */ 1393 ifp->if_flags |= IFF_OACTIVE; 1394 } 1395 1396 if (sc->sc_txfree != ofree) { 1397 /* 1398 * Start the transmit process. Note, the manual says 1399 * that if there are no pending transmissions in the 1400 * chip's internal queue (indicated by TXE being clear), 1401 * then the driver software must set the TXDP to the 1402 * first descriptor to be transmitted. However, if we 1403 * do this, it causes serious performance degredation on 1404 * the DP83820 under load, not setting TXDP doesn't seem 1405 * to adversely affect the SiS 900 or DP83815. 1406 * 1407 * Well, I guess it wouldn't be the first time a manual 1408 * has lied -- and they could be speaking of the NULL- 1409 * terminated descriptor list case, rather than OWN- 1410 * terminated rings. 1411 */ 1412 #if 0 1413 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1414 CR_TXE) == 0) { 1415 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1416 SIP_CDTXADDR(sc, firsttx)); 1417 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1418 } 1419 #else 1420 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1421 #endif 1422 1423 /* Set a watchdog timer in case the chip flakes out. */ 1424 ifp->if_timer = 5; 1425 } 1426 } 1427 1428 /* 1429 * sip_watchdog: [ifnet interface function] 1430 * 1431 * Watchdog timer handler. 1432 */ 1433 void 1434 SIP_DECL(watchdog)(struct ifnet *ifp) 1435 { 1436 struct sip_softc *sc = ifp->if_softc; 1437 1438 /* 1439 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1440 * If we get a timeout, try and sweep up transmit descriptors. 1441 * If we manage to sweep them all up, ignore the lack of 1442 * interrupt. 1443 */ 1444 SIP_DECL(txintr)(sc); 1445 1446 if (sc->sc_txfree != SIP_NTXDESC) { 1447 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1448 ifp->if_oerrors++; 1449 1450 /* Reset the interface. */ 1451 (void) SIP_DECL(init)(ifp); 1452 } else if (ifp->if_flags & IFF_DEBUG) 1453 printf("%s: recovered from device timeout\n", 1454 sc->sc_dev.dv_xname); 1455 1456 /* Try to get more packets going. */ 1457 SIP_DECL(start)(ifp); 1458 } 1459 1460 /* 1461 * sip_ioctl: [ifnet interface function] 1462 * 1463 * Handle control requests from the operator. 1464 */ 1465 int 1466 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1467 { 1468 struct sip_softc *sc = ifp->if_softc; 1469 struct ifreq *ifr = (struct ifreq *)data; 1470 int s, error; 1471 1472 s = splnet(); 1473 1474 switch (cmd) { 1475 case SIOCSIFMEDIA: 1476 case SIOCGIFMEDIA: 1477 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1478 break; 1479 1480 default: 1481 error = ether_ioctl(ifp, cmd, data); 1482 if (error == ENETRESET) { 1483 /* 1484 * Multicast list has changed; set the hardware filter 1485 * accordingly. 1486 */ 1487 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1488 error = 0; 1489 } 1490 break; 1491 } 1492 1493 /* Try to get more packets going. */ 1494 SIP_DECL(start)(ifp); 1495 1496 splx(s); 1497 return (error); 1498 } 1499 1500 /* 1501 * sip_intr: 1502 * 1503 * Interrupt service routine. 1504 */ 1505 int 1506 SIP_DECL(intr)(void *arg) 1507 { 1508 struct sip_softc *sc = arg; 1509 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1510 u_int32_t isr; 1511 int handled = 0; 1512 1513 for (;;) { 1514 /* Reading clears interrupt. */ 1515 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1516 if ((isr & sc->sc_imr) == 0) 1517 break; 1518 1519 #if NRND > 0 1520 if (RND_ENABLED(&sc->rnd_source)) 1521 rnd_add_uint32(&sc->rnd_source, isr); 1522 #endif 1523 1524 handled = 1; 1525 1526 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1527 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1528 1529 /* Grab any new packets. */ 1530 SIP_DECL(rxintr)(sc); 1531 1532 if (isr & ISR_RXORN) { 1533 printf("%s: receive FIFO overrun\n", 1534 sc->sc_dev.dv_xname); 1535 1536 /* XXX adjust rx_drain_thresh? */ 1537 } 1538 1539 if (isr & ISR_RXIDLE) { 1540 printf("%s: receive ring overrun\n", 1541 sc->sc_dev.dv_xname); 1542 1543 /* Get the receive process going again. */ 1544 bus_space_write_4(sc->sc_st, sc->sc_sh, 1545 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1546 bus_space_write_4(sc->sc_st, sc->sc_sh, 1547 SIP_CR, CR_RXE); 1548 } 1549 } 1550 1551 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1552 #ifdef SIP_EVENT_COUNTERS 1553 if (isr & ISR_TXDESC) 1554 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1555 else if (isr & ISR_TXIDLE) 1556 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1557 #endif 1558 1559 /* Sweep up transmit descriptors. */ 1560 SIP_DECL(txintr)(sc); 1561 1562 if (isr & ISR_TXURN) { 1563 u_int32_t thresh; 1564 1565 printf("%s: transmit FIFO underrun", 1566 sc->sc_dev.dv_xname); 1567 1568 thresh = sc->sc_tx_drain_thresh + 1; 1569 if (thresh <= TXCFG_DRTH && 1570 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1571 (sc->sc_tx_fill_thresh * 32))) { 1572 printf("; increasing Tx drain " 1573 "threshold to %u bytes\n", 1574 thresh * 32); 1575 sc->sc_tx_drain_thresh = thresh; 1576 (void) SIP_DECL(init)(ifp); 1577 } else { 1578 (void) SIP_DECL(init)(ifp); 1579 printf("\n"); 1580 } 1581 } 1582 } 1583 1584 #if !defined(DP83820) 1585 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1586 if (isr & ISR_PAUSE_ST) { 1587 sc->sc_flags |= SIPF_PAUSED; 1588 ifp->if_flags |= IFF_OACTIVE; 1589 } 1590 if (isr & ISR_PAUSE_END) { 1591 sc->sc_flags &= ~SIPF_PAUSED; 1592 ifp->if_flags &= ~IFF_OACTIVE; 1593 } 1594 } 1595 #endif /* ! DP83820 */ 1596 1597 if (isr & ISR_HIBERR) { 1598 int want_init = 0; 1599 1600 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1601 1602 #define PRINTERR(bit, str) \ 1603 do { \ 1604 if ((isr & (bit)) != 0) { \ 1605 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1606 printf("%s: %s\n", \ 1607 sc->sc_dev.dv_xname, str); \ 1608 want_init = 1; \ 1609 } \ 1610 } while (/*CONSTCOND*/0) 1611 1612 PRINTERR(ISR_DPERR, "parity error"); 1613 PRINTERR(ISR_SSERR, "system error"); 1614 PRINTERR(ISR_RMABT, "master abort"); 1615 PRINTERR(ISR_RTABT, "target abort"); 1616 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1617 /* 1618 * Ignore: 1619 * Tx reset complete 1620 * Rx reset complete 1621 */ 1622 if (want_init) 1623 (void) SIP_DECL(init)(ifp); 1624 #undef PRINTERR 1625 } 1626 } 1627 1628 /* Try to get more packets going. */ 1629 SIP_DECL(start)(ifp); 1630 1631 return (handled); 1632 } 1633 1634 /* 1635 * sip_txintr: 1636 * 1637 * Helper; handle transmit interrupts. 1638 */ 1639 void 1640 SIP_DECL(txintr)(struct sip_softc *sc) 1641 { 1642 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1643 struct sip_txsoft *txs; 1644 u_int32_t cmdsts; 1645 1646 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1647 ifp->if_flags &= ~IFF_OACTIVE; 1648 1649 /* 1650 * Go through our Tx list and free mbufs for those 1651 * frames which have been transmitted. 1652 */ 1653 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1654 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1655 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1656 1657 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1658 if (cmdsts & CMDSTS_OWN) 1659 break; 1660 1661 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1662 1663 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1664 1665 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1666 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1667 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1668 m_freem(txs->txs_mbuf); 1669 txs->txs_mbuf = NULL; 1670 1671 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1672 1673 /* 1674 * Check for errors and collisions. 1675 */ 1676 if (cmdsts & 1677 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1678 ifp->if_oerrors++; 1679 if (cmdsts & CMDSTS_Tx_EC) 1680 ifp->if_collisions += 16; 1681 if (ifp->if_flags & IFF_DEBUG) { 1682 if (cmdsts & CMDSTS_Tx_ED) 1683 printf("%s: excessive deferral\n", 1684 sc->sc_dev.dv_xname); 1685 if (cmdsts & CMDSTS_Tx_EC) 1686 printf("%s: excessive collisions\n", 1687 sc->sc_dev.dv_xname); 1688 } 1689 } else { 1690 /* Packet was transmitted successfully. */ 1691 ifp->if_opackets++; 1692 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1693 } 1694 } 1695 1696 /* 1697 * If there are no more pending transmissions, cancel the watchdog 1698 * timer. 1699 */ 1700 if (txs == NULL) { 1701 ifp->if_timer = 0; 1702 sc->sc_txwin = 0; 1703 } 1704 } 1705 1706 #if defined(DP83820) 1707 /* 1708 * sip_rxintr: 1709 * 1710 * Helper; handle receive interrupts. 1711 */ 1712 void 1713 SIP_DECL(rxintr)(struct sip_softc *sc) 1714 { 1715 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1716 struct sip_rxsoft *rxs; 1717 struct mbuf *m, *tailm; 1718 u_int32_t cmdsts, extsts; 1719 int i, len; 1720 1721 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1722 rxs = &sc->sc_rxsoft[i]; 1723 1724 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1725 1726 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1727 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1728 1729 /* 1730 * NOTE: OWN is set if owned by _consumer_. We're the 1731 * consumer of the receive ring, so if the bit is clear, 1732 * we have processed all of the packets. 1733 */ 1734 if ((cmdsts & CMDSTS_OWN) == 0) { 1735 /* 1736 * We have processed all of the receive buffers. 1737 */ 1738 break; 1739 } 1740 1741 if (__predict_false(sc->sc_rxdiscard)) { 1742 SIP_INIT_RXDESC(sc, i); 1743 if ((cmdsts & CMDSTS_MORE) == 0) { 1744 /* Reset our state. */ 1745 sc->sc_rxdiscard = 0; 1746 } 1747 continue; 1748 } 1749 1750 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1751 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1752 1753 m = rxs->rxs_mbuf; 1754 1755 /* 1756 * Add a new receive buffer to the ring. 1757 */ 1758 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1759 /* 1760 * Failed, throw away what we've done so 1761 * far, and discard the rest of the packet. 1762 */ 1763 ifp->if_ierrors++; 1764 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1765 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1766 SIP_INIT_RXDESC(sc, i); 1767 if (cmdsts & CMDSTS_MORE) 1768 sc->sc_rxdiscard = 1; 1769 if (sc->sc_rxhead != NULL) 1770 m_freem(sc->sc_rxhead); 1771 SIP_RXCHAIN_RESET(sc); 1772 continue; 1773 } 1774 1775 SIP_RXCHAIN_LINK(sc, m); 1776 1777 /* 1778 * If this is not the end of the packet, keep 1779 * looking. 1780 */ 1781 if (cmdsts & CMDSTS_MORE) { 1782 sc->sc_rxlen += m->m_len; 1783 continue; 1784 } 1785 1786 /* 1787 * Okay, we have the entire packet now... 1788 */ 1789 *sc->sc_rxtailp = NULL; 1790 m = sc->sc_rxhead; 1791 tailm = sc->sc_rxtail; 1792 1793 SIP_RXCHAIN_RESET(sc); 1794 1795 /* 1796 * If an error occurred, update stats and drop the packet. 1797 */ 1798 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1799 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1800 ifp->if_ierrors++; 1801 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1802 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1803 /* Receive overrun handled elsewhere. */ 1804 printf("%s: receive descriptor error\n", 1805 sc->sc_dev.dv_xname); 1806 } 1807 #define PRINTERR(bit, str) \ 1808 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1809 (cmdsts & (bit)) != 0) \ 1810 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1811 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1812 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1813 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1814 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1815 #undef PRINTERR 1816 m_freem(m); 1817 continue; 1818 } 1819 1820 /* 1821 * No errors. 1822 * 1823 * Note, the DP83820 includes the CRC with 1824 * every packet. 1825 */ 1826 len = CMDSTS_SIZE(cmdsts); 1827 tailm->m_len = len - sc->sc_rxlen; 1828 1829 /* 1830 * If the packet is small enough to fit in a 1831 * single header mbuf, allocate one and copy 1832 * the data into it. This greatly reduces 1833 * memory consumption when we receive lots 1834 * of small packets. 1835 */ 1836 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1837 struct mbuf *nm; 1838 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1839 if (nm == NULL) { 1840 ifp->if_ierrors++; 1841 m_freem(m); 1842 continue; 1843 } 1844 nm->m_data += 2; 1845 nm->m_pkthdr.len = nm->m_len = len; 1846 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1847 m_freem(m); 1848 m = nm; 1849 } 1850 #ifndef __NO_STRICT_ALIGNMENT 1851 else { 1852 /* 1853 * The DP83820's receive buffers must be 4-byte 1854 * aligned. But this means that the data after 1855 * the Ethernet header is misaligned. To compensate, 1856 * we have artificially shortened the buffer size 1857 * in the descriptor, and we do an overlapping copy 1858 * of the data two bytes further in (in the first 1859 * buffer of the chain only). 1860 */ 1861 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1862 m->m_len); 1863 m->m_data += 2; 1864 } 1865 #endif /* ! __NO_STRICT_ALIGNMENT */ 1866 1867 /* 1868 * If VLANs are enabled, VLAN packets have been unwrapped 1869 * for us. Associate the tag with the packet. 1870 */ 1871 if (sc->sc_ethercom.ec_nvlans != 0 && 1872 (extsts & EXTSTS_VPKT) != 0) { 1873 struct m_tag *vtag; 1874 1875 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 1876 M_NOWAIT); 1877 if (vtag == NULL) { 1878 ifp->if_ierrors++; 1879 printf("%s: unable to allocate VLAN tag\n", 1880 sc->sc_dev.dv_xname); 1881 m_freem(m); 1882 continue; 1883 } 1884 1885 *(u_int *)(vtag + 1) = ntohs(extsts & EXTSTS_VTCI); 1886 } 1887 1888 /* 1889 * Set the incoming checksum information for the 1890 * packet. 1891 */ 1892 if ((extsts & EXTSTS_IPPKT) != 0) { 1893 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1894 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1895 if (extsts & EXTSTS_Rx_IPERR) 1896 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1897 if (extsts & EXTSTS_TCPPKT) { 1898 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1899 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1900 if (extsts & EXTSTS_Rx_TCPERR) 1901 m->m_pkthdr.csum_flags |= 1902 M_CSUM_TCP_UDP_BAD; 1903 } else if (extsts & EXTSTS_UDPPKT) { 1904 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1905 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1906 if (extsts & EXTSTS_Rx_UDPERR) 1907 m->m_pkthdr.csum_flags |= 1908 M_CSUM_TCP_UDP_BAD; 1909 } 1910 } 1911 1912 ifp->if_ipackets++; 1913 m->m_flags |= M_HASFCS; 1914 m->m_pkthdr.rcvif = ifp; 1915 m->m_pkthdr.len = len; 1916 1917 #if NBPFILTER > 0 1918 /* 1919 * Pass this up to any BPF listeners, but only 1920 * pass if up the stack if it's for us. 1921 */ 1922 if (ifp->if_bpf) 1923 bpf_mtap(ifp->if_bpf, m); 1924 #endif /* NBPFILTER > 0 */ 1925 1926 /* Pass it on. */ 1927 (*ifp->if_input)(ifp, m); 1928 } 1929 1930 /* Update the receive pointer. */ 1931 sc->sc_rxptr = i; 1932 } 1933 #else /* ! DP83820 */ 1934 /* 1935 * sip_rxintr: 1936 * 1937 * Helper; handle receive interrupts. 1938 */ 1939 void 1940 SIP_DECL(rxintr)(struct sip_softc *sc) 1941 { 1942 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1943 struct sip_rxsoft *rxs; 1944 struct mbuf *m; 1945 u_int32_t cmdsts; 1946 int i, len; 1947 1948 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1949 rxs = &sc->sc_rxsoft[i]; 1950 1951 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1952 1953 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1954 1955 /* 1956 * NOTE: OWN is set if owned by _consumer_. We're the 1957 * consumer of the receive ring, so if the bit is clear, 1958 * we have processed all of the packets. 1959 */ 1960 if ((cmdsts & CMDSTS_OWN) == 0) { 1961 /* 1962 * We have processed all of the receive buffers. 1963 */ 1964 break; 1965 } 1966 1967 /* 1968 * If any collisions were seen on the wire, count one. 1969 */ 1970 if (cmdsts & CMDSTS_Rx_COL) 1971 ifp->if_collisions++; 1972 1973 /* 1974 * If an error occurred, update stats, clear the status 1975 * word, and leave the packet buffer in place. It will 1976 * simply be reused the next time the ring comes around. 1977 */ 1978 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1979 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1980 ifp->if_ierrors++; 1981 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1982 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1983 /* Receive overrun handled elsewhere. */ 1984 printf("%s: receive descriptor error\n", 1985 sc->sc_dev.dv_xname); 1986 } 1987 #define PRINTERR(bit, str) \ 1988 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1989 (cmdsts & (bit)) != 0) \ 1990 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1991 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1992 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1993 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1994 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1995 #undef PRINTERR 1996 SIP_INIT_RXDESC(sc, i); 1997 continue; 1998 } 1999 2000 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2001 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2002 2003 /* 2004 * No errors; receive the packet. Note, the SiS 900 2005 * includes the CRC with every packet. 2006 */ 2007 len = CMDSTS_SIZE(cmdsts); 2008 2009 #ifdef __NO_STRICT_ALIGNMENT 2010 /* 2011 * If the packet is small enough to fit in a 2012 * single header mbuf, allocate one and copy 2013 * the data into it. This greatly reduces 2014 * memory consumption when we receive lots 2015 * of small packets. 2016 * 2017 * Otherwise, we add a new buffer to the receive 2018 * chain. If this fails, we drop the packet and 2019 * recycle the old buffer. 2020 */ 2021 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 2022 MGETHDR(m, M_DONTWAIT, MT_DATA); 2023 if (m == NULL) 2024 goto dropit; 2025 memcpy(mtod(m, caddr_t), 2026 mtod(rxs->rxs_mbuf, caddr_t), len); 2027 SIP_INIT_RXDESC(sc, i); 2028 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2029 rxs->rxs_dmamap->dm_mapsize, 2030 BUS_DMASYNC_PREREAD); 2031 } else { 2032 m = rxs->rxs_mbuf; 2033 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 2034 dropit: 2035 ifp->if_ierrors++; 2036 SIP_INIT_RXDESC(sc, i); 2037 bus_dmamap_sync(sc->sc_dmat, 2038 rxs->rxs_dmamap, 0, 2039 rxs->rxs_dmamap->dm_mapsize, 2040 BUS_DMASYNC_PREREAD); 2041 continue; 2042 } 2043 } 2044 #else 2045 /* 2046 * The SiS 900's receive buffers must be 4-byte aligned. 2047 * But this means that the data after the Ethernet header 2048 * is misaligned. We must allocate a new buffer and 2049 * copy the data, shifted forward 2 bytes. 2050 */ 2051 MGETHDR(m, M_DONTWAIT, MT_DATA); 2052 if (m == NULL) { 2053 dropit: 2054 ifp->if_ierrors++; 2055 SIP_INIT_RXDESC(sc, i); 2056 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2057 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2058 continue; 2059 } 2060 if (len > (MHLEN - 2)) { 2061 MCLGET(m, M_DONTWAIT); 2062 if ((m->m_flags & M_EXT) == 0) { 2063 m_freem(m); 2064 goto dropit; 2065 } 2066 } 2067 m->m_data += 2; 2068 2069 /* 2070 * Note that we use clusters for incoming frames, so the 2071 * buffer is virtually contiguous. 2072 */ 2073 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 2074 2075 /* Allow the receive descriptor to continue using its mbuf. */ 2076 SIP_INIT_RXDESC(sc, i); 2077 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2078 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2079 #endif /* __NO_STRICT_ALIGNMENT */ 2080 2081 ifp->if_ipackets++; 2082 m->m_flags |= M_HASFCS; 2083 m->m_pkthdr.rcvif = ifp; 2084 m->m_pkthdr.len = m->m_len = len; 2085 2086 #if NBPFILTER > 0 2087 /* 2088 * Pass this up to any BPF listeners, but only 2089 * pass if up the stack if it's for us. 2090 */ 2091 if (ifp->if_bpf) 2092 bpf_mtap(ifp->if_bpf, m); 2093 #endif /* NBPFILTER > 0 */ 2094 2095 /* Pass it on. */ 2096 (*ifp->if_input)(ifp, m); 2097 } 2098 2099 /* Update the receive pointer. */ 2100 sc->sc_rxptr = i; 2101 } 2102 #endif /* DP83820 */ 2103 2104 /* 2105 * sip_tick: 2106 * 2107 * One second timer, used to tick the MII. 2108 */ 2109 void 2110 SIP_DECL(tick)(void *arg) 2111 { 2112 struct sip_softc *sc = arg; 2113 int s; 2114 2115 s = splnet(); 2116 mii_tick(&sc->sc_mii); 2117 splx(s); 2118 2119 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2120 } 2121 2122 /* 2123 * sip_reset: 2124 * 2125 * Perform a soft reset on the SiS 900. 2126 */ 2127 void 2128 SIP_DECL(reset)(struct sip_softc *sc) 2129 { 2130 bus_space_tag_t st = sc->sc_st; 2131 bus_space_handle_t sh = sc->sc_sh; 2132 int i; 2133 2134 bus_space_write_4(st, sh, SIP_IER, 0); 2135 bus_space_write_4(st, sh, SIP_IMR, 0); 2136 bus_space_write_4(st, sh, SIP_RFCR, 0); 2137 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2138 2139 for (i = 0; i < SIP_TIMEOUT; i++) { 2140 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2141 break; 2142 delay(2); 2143 } 2144 2145 if (i == SIP_TIMEOUT) 2146 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2147 2148 delay(1000); 2149 2150 #ifdef DP83820 2151 /* 2152 * Set the general purpose I/O bits. Do it here in case we 2153 * need to have GPIO set up to talk to the media interface. 2154 */ 2155 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2156 delay(1000); 2157 #endif /* DP83820 */ 2158 } 2159 2160 /* 2161 * sip_init: [ ifnet interface function ] 2162 * 2163 * Initialize the interface. Must be called at splnet(). 2164 */ 2165 int 2166 SIP_DECL(init)(struct ifnet *ifp) 2167 { 2168 struct sip_softc *sc = ifp->if_softc; 2169 bus_space_tag_t st = sc->sc_st; 2170 bus_space_handle_t sh = sc->sc_sh; 2171 struct sip_txsoft *txs; 2172 struct sip_rxsoft *rxs; 2173 struct sip_desc *sipd; 2174 #if defined(DP83820) 2175 u_int32_t reg; 2176 #endif 2177 int i, error = 0; 2178 2179 /* 2180 * Cancel any pending I/O. 2181 */ 2182 SIP_DECL(stop)(ifp, 0); 2183 2184 /* 2185 * Reset the chip to a known state. 2186 */ 2187 SIP_DECL(reset)(sc); 2188 2189 #if !defined(DP83820) 2190 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2191 /* 2192 * DP83815 manual, page 78: 2193 * 4.4 Recommended Registers Configuration 2194 * For optimum performance of the DP83815, version noted 2195 * as DP83815CVNG (SRR = 203h), the listed register 2196 * modifications must be followed in sequence... 2197 * 2198 * It's not clear if this should be 302h or 203h because that 2199 * chip name is listed as SRR 302h in the description of the 2200 * SRR register. However, my revision 302h DP83815 on the 2201 * Netgear FA311 purchased in 02/2001 needs these settings 2202 * to avoid tons of errors in AcceptPerfectMatch (non- 2203 * IFF_PROMISC) mode. I do not know if other revisions need 2204 * this set or not. [briggs -- 09 March 2001] 2205 * 2206 * Note that only the low-order 12 bits of 0xe4 are documented 2207 * and that this sets reserved bits in that register. 2208 */ 2209 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2210 2211 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2212 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2213 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2214 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2215 2216 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2217 } 2218 #endif /* ! DP83820 */ 2219 2220 /* 2221 * Initialize the transmit descriptor ring. 2222 */ 2223 for (i = 0; i < SIP_NTXDESC; i++) { 2224 sipd = &sc->sc_txdescs[i]; 2225 memset(sipd, 0, sizeof(struct sip_desc)); 2226 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2227 } 2228 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2229 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2230 sc->sc_txfree = SIP_NTXDESC; 2231 sc->sc_txnext = 0; 2232 sc->sc_txwin = 0; 2233 2234 /* 2235 * Initialize the transmit job descriptors. 2236 */ 2237 SIMPLEQ_INIT(&sc->sc_txfreeq); 2238 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2239 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2240 txs = &sc->sc_txsoft[i]; 2241 txs->txs_mbuf = NULL; 2242 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2243 } 2244 2245 /* 2246 * Initialize the receive descriptor and receive job 2247 * descriptor rings. 2248 */ 2249 for (i = 0; i < SIP_NRXDESC; i++) { 2250 rxs = &sc->sc_rxsoft[i]; 2251 if (rxs->rxs_mbuf == NULL) { 2252 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2253 printf("%s: unable to allocate or map rx " 2254 "buffer %d, error = %d\n", 2255 sc->sc_dev.dv_xname, i, error); 2256 /* 2257 * XXX Should attempt to run with fewer receive 2258 * XXX buffers instead of just failing. 2259 */ 2260 SIP_DECL(rxdrain)(sc); 2261 goto out; 2262 } 2263 } else 2264 SIP_INIT_RXDESC(sc, i); 2265 } 2266 sc->sc_rxptr = 0; 2267 #ifdef DP83820 2268 sc->sc_rxdiscard = 0; 2269 SIP_RXCHAIN_RESET(sc); 2270 #endif /* DP83820 */ 2271 2272 /* 2273 * Set the configuration register; it's already initialized 2274 * in sip_attach(). 2275 */ 2276 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2277 2278 /* 2279 * Initialize the prototype TXCFG register. 2280 */ 2281 #if defined(DP83820) 2282 sc->sc_txcfg = TXCFG_MXDMA_512; 2283 sc->sc_rxcfg = RXCFG_MXDMA_512; 2284 #else 2285 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2286 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2287 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & CFG_EDBMASTEN)) { 2288 sc->sc_txcfg = TXCFG_MXDMA_64; 2289 sc->sc_rxcfg = RXCFG_MXDMA_64; 2290 } else { 2291 sc->sc_txcfg = TXCFG_MXDMA_512; 2292 sc->sc_rxcfg = RXCFG_MXDMA_512; 2293 } 2294 #endif /* DP83820 */ 2295 2296 sc->sc_txcfg |= TXCFG_ATP | 2297 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2298 sc->sc_tx_drain_thresh; 2299 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2300 2301 /* 2302 * Initialize the receive drain threshold if we have never 2303 * done so. 2304 */ 2305 if (sc->sc_rx_drain_thresh == 0) { 2306 /* 2307 * XXX This value should be tuned. This is set to the 2308 * maximum of 248 bytes, and we may be able to improve 2309 * performance by decreasing it (although we should never 2310 * set this value lower than 2; 14 bytes are required to 2311 * filter the packet). 2312 */ 2313 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2314 } 2315 2316 /* 2317 * Initialize the prototype RXCFG register. 2318 */ 2319 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2320 #ifndef DP83820 2321 /* 2322 * Accept packets >1518 bytes (including FCS) so we can handle 2323 * 802.1q-tagged frames properly. 2324 */ 2325 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2326 sc->sc_rxcfg |= RXCFG_ALP; 2327 #endif 2328 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2329 2330 #ifdef DP83820 2331 /* 2332 * Initialize the VLAN/IP receive control register. 2333 * We enable checksum computation on all incoming 2334 * packets, and do not reject packets w/ bad checksums. 2335 */ 2336 reg = 0; 2337 if (ifp->if_capenable & 2338 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2339 reg |= VRCR_IPEN; 2340 if (sc->sc_ethercom.ec_nvlans != 0) 2341 reg |= VRCR_VTDEN|VRCR_VTREN; 2342 bus_space_write_4(st, sh, SIP_VRCR, reg); 2343 2344 /* 2345 * Initialize the VLAN/IP transmit control register. 2346 * We enable outgoing checksum computation on a 2347 * per-packet basis. 2348 */ 2349 reg = 0; 2350 if (ifp->if_capenable & 2351 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2352 reg |= VTCR_PPCHK; 2353 if (sc->sc_ethercom.ec_nvlans != 0) 2354 reg |= VTCR_VPPTI; 2355 bus_space_write_4(st, sh, SIP_VTCR, reg); 2356 2357 /* 2358 * If we're using VLANs, initialize the VLAN data register. 2359 * To understand why we bswap the VLAN Ethertype, see section 2360 * 4.2.36 of the DP83820 manual. 2361 */ 2362 if (sc->sc_ethercom.ec_nvlans != 0) 2363 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2364 #endif /* DP83820 */ 2365 2366 /* 2367 * Give the transmit and receive rings to the chip. 2368 */ 2369 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2370 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2371 2372 /* 2373 * Initialize the interrupt mask. 2374 */ 2375 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2376 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2377 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2378 2379 /* Set up the receive filter. */ 2380 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2381 2382 /* 2383 * Set the current media. Do this after initializing the prototype 2384 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2385 * control. 2386 */ 2387 mii_mediachg(&sc->sc_mii); 2388 2389 /* 2390 * Enable interrupts. 2391 */ 2392 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2393 2394 /* 2395 * Start the transmit and receive processes. 2396 */ 2397 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2398 2399 /* 2400 * Start the one second MII clock. 2401 */ 2402 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2403 2404 /* 2405 * ...all done! 2406 */ 2407 ifp->if_flags |= IFF_RUNNING; 2408 ifp->if_flags &= ~IFF_OACTIVE; 2409 2410 out: 2411 if (error) 2412 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2413 return (error); 2414 } 2415 2416 /* 2417 * sip_drain: 2418 * 2419 * Drain the receive queue. 2420 */ 2421 void 2422 SIP_DECL(rxdrain)(struct sip_softc *sc) 2423 { 2424 struct sip_rxsoft *rxs; 2425 int i; 2426 2427 for (i = 0; i < SIP_NRXDESC; i++) { 2428 rxs = &sc->sc_rxsoft[i]; 2429 if (rxs->rxs_mbuf != NULL) { 2430 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2431 m_freem(rxs->rxs_mbuf); 2432 rxs->rxs_mbuf = NULL; 2433 } 2434 } 2435 } 2436 2437 /* 2438 * sip_stop: [ ifnet interface function ] 2439 * 2440 * Stop transmission on the interface. 2441 */ 2442 void 2443 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2444 { 2445 struct sip_softc *sc = ifp->if_softc; 2446 bus_space_tag_t st = sc->sc_st; 2447 bus_space_handle_t sh = sc->sc_sh; 2448 struct sip_txsoft *txs; 2449 u_int32_t cmdsts = 0; /* DEBUG */ 2450 2451 /* 2452 * Stop the one second clock. 2453 */ 2454 callout_stop(&sc->sc_tick_ch); 2455 2456 /* Down the MII. */ 2457 mii_down(&sc->sc_mii); 2458 2459 /* 2460 * Disable interrupts. 2461 */ 2462 bus_space_write_4(st, sh, SIP_IER, 0); 2463 2464 /* 2465 * Stop receiver and transmitter. 2466 */ 2467 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2468 2469 /* 2470 * Release any queued transmit buffers. 2471 */ 2472 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2473 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2474 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2475 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2476 CMDSTS_INTR) == 0) 2477 printf("%s: sip_stop: last descriptor does not " 2478 "have INTR bit set\n", sc->sc_dev.dv_xname); 2479 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2480 #ifdef DIAGNOSTIC 2481 if (txs->txs_mbuf == NULL) { 2482 printf("%s: dirty txsoft with no mbuf chain\n", 2483 sc->sc_dev.dv_xname); 2484 panic("sip_stop"); 2485 } 2486 #endif 2487 cmdsts |= /* DEBUG */ 2488 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2489 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2490 m_freem(txs->txs_mbuf); 2491 txs->txs_mbuf = NULL; 2492 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2493 } 2494 2495 if (disable) 2496 SIP_DECL(rxdrain)(sc); 2497 2498 /* 2499 * Mark the interface down and cancel the watchdog timer. 2500 */ 2501 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2502 ifp->if_timer = 0; 2503 2504 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2505 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2506 printf("%s: sip_stop: no INTR bits set in dirty tx " 2507 "descriptors\n", sc->sc_dev.dv_xname); 2508 } 2509 2510 /* 2511 * sip_read_eeprom: 2512 * 2513 * Read data from the serial EEPROM. 2514 */ 2515 void 2516 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2517 u_int16_t *data) 2518 { 2519 bus_space_tag_t st = sc->sc_st; 2520 bus_space_handle_t sh = sc->sc_sh; 2521 u_int16_t reg; 2522 int i, x; 2523 2524 for (i = 0; i < wordcnt; i++) { 2525 /* Send CHIP SELECT. */ 2526 reg = EROMAR_EECS; 2527 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2528 2529 /* Shift in the READ opcode. */ 2530 for (x = 3; x > 0; x--) { 2531 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2532 reg |= EROMAR_EEDI; 2533 else 2534 reg &= ~EROMAR_EEDI; 2535 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2536 bus_space_write_4(st, sh, SIP_EROMAR, 2537 reg | EROMAR_EESK); 2538 delay(4); 2539 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2540 delay(4); 2541 } 2542 2543 /* Shift in address. */ 2544 for (x = 6; x > 0; x--) { 2545 if ((word + i) & (1 << (x - 1))) 2546 reg |= EROMAR_EEDI; 2547 else 2548 reg &= ~EROMAR_EEDI; 2549 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2550 bus_space_write_4(st, sh, SIP_EROMAR, 2551 reg | EROMAR_EESK); 2552 delay(4); 2553 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2554 delay(4); 2555 } 2556 2557 /* Shift out data. */ 2558 reg = EROMAR_EECS; 2559 data[i] = 0; 2560 for (x = 16; x > 0; x--) { 2561 bus_space_write_4(st, sh, SIP_EROMAR, 2562 reg | EROMAR_EESK); 2563 delay(4); 2564 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2565 data[i] |= (1 << (x - 1)); 2566 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2567 delay(4); 2568 } 2569 2570 /* Clear CHIP SELECT. */ 2571 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2572 delay(4); 2573 } 2574 } 2575 2576 /* 2577 * sip_add_rxbuf: 2578 * 2579 * Add a receive buffer to the indicated descriptor. 2580 */ 2581 int 2582 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2583 { 2584 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2585 struct mbuf *m; 2586 int error; 2587 2588 MGETHDR(m, M_DONTWAIT, MT_DATA); 2589 if (m == NULL) 2590 return (ENOBUFS); 2591 2592 MCLGET(m, M_DONTWAIT); 2593 if ((m->m_flags & M_EXT) == 0) { 2594 m_freem(m); 2595 return (ENOBUFS); 2596 } 2597 2598 #if defined(DP83820) 2599 m->m_len = SIP_RXBUF_LEN; 2600 #endif /* DP83820 */ 2601 2602 if (rxs->rxs_mbuf != NULL) 2603 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2604 2605 rxs->rxs_mbuf = m; 2606 2607 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2608 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2609 BUS_DMA_READ|BUS_DMA_NOWAIT); 2610 if (error) { 2611 printf("%s: can't load rx DMA map %d, error = %d\n", 2612 sc->sc_dev.dv_xname, idx, error); 2613 panic("sip_add_rxbuf"); /* XXX */ 2614 } 2615 2616 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2617 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2618 2619 SIP_INIT_RXDESC(sc, idx); 2620 2621 return (0); 2622 } 2623 2624 #if !defined(DP83820) 2625 /* 2626 * sip_sis900_set_filter: 2627 * 2628 * Set up the receive filter. 2629 */ 2630 void 2631 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2632 { 2633 bus_space_tag_t st = sc->sc_st; 2634 bus_space_handle_t sh = sc->sc_sh; 2635 struct ethercom *ec = &sc->sc_ethercom; 2636 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2637 struct ether_multi *enm; 2638 u_int8_t *cp; 2639 struct ether_multistep step; 2640 u_int32_t crc, mchash[16]; 2641 2642 /* 2643 * Initialize the prototype RFCR. 2644 */ 2645 sc->sc_rfcr = RFCR_RFEN; 2646 if (ifp->if_flags & IFF_BROADCAST) 2647 sc->sc_rfcr |= RFCR_AAB; 2648 if (ifp->if_flags & IFF_PROMISC) { 2649 sc->sc_rfcr |= RFCR_AAP; 2650 goto allmulti; 2651 } 2652 2653 /* 2654 * Set up the multicast address filter by passing all multicast 2655 * addresses through a CRC generator, and then using the high-order 2656 * 6 bits as an index into the 128 bit multicast hash table (only 2657 * the lower 16 bits of each 32 bit multicast hash register are 2658 * valid). The high order bits select the register, while the 2659 * rest of the bits select the bit within the register. 2660 */ 2661 2662 memset(mchash, 0, sizeof(mchash)); 2663 2664 ETHER_FIRST_MULTI(step, ec, enm); 2665 while (enm != NULL) { 2666 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2667 /* 2668 * We must listen to a range of multicast addresses. 2669 * For now, just accept all multicasts, rather than 2670 * trying to set only those filter bits needed to match 2671 * the range. (At this time, the only use of address 2672 * ranges is for IP multicast routing, for which the 2673 * range is big enough to require all bits set.) 2674 */ 2675 goto allmulti; 2676 } 2677 2678 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2679 2680 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2681 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2682 /* Just want the 8 most significant bits. */ 2683 crc >>= 24; 2684 } else { 2685 /* Just want the 7 most significant bits. */ 2686 crc >>= 25; 2687 } 2688 2689 /* Set the corresponding bit in the hash table. */ 2690 mchash[crc >> 4] |= 1 << (crc & 0xf); 2691 2692 ETHER_NEXT_MULTI(step, enm); 2693 } 2694 2695 ifp->if_flags &= ~IFF_ALLMULTI; 2696 goto setit; 2697 2698 allmulti: 2699 ifp->if_flags |= IFF_ALLMULTI; 2700 sc->sc_rfcr |= RFCR_AAM; 2701 2702 setit: 2703 #define FILTER_EMIT(addr, data) \ 2704 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2705 delay(1); \ 2706 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2707 delay(1) 2708 2709 /* 2710 * Disable receive filter, and program the node address. 2711 */ 2712 cp = LLADDR(ifp->if_sadl); 2713 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2714 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2715 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2716 2717 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2718 /* 2719 * Program the multicast hash table. 2720 */ 2721 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2722 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2723 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2724 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2725 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2726 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2727 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2728 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2729 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2730 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2731 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2732 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2733 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2734 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2735 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2736 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2737 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2738 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2739 } 2740 } 2741 #undef FILTER_EMIT 2742 2743 /* 2744 * Re-enable the receiver filter. 2745 */ 2746 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2747 } 2748 #endif /* ! DP83820 */ 2749 2750 /* 2751 * sip_dp83815_set_filter: 2752 * 2753 * Set up the receive filter. 2754 */ 2755 void 2756 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2757 { 2758 bus_space_tag_t st = sc->sc_st; 2759 bus_space_handle_t sh = sc->sc_sh; 2760 struct ethercom *ec = &sc->sc_ethercom; 2761 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2762 struct ether_multi *enm; 2763 u_int8_t *cp; 2764 struct ether_multistep step; 2765 u_int32_t crc, hash, slot, bit; 2766 #ifdef DP83820 2767 #define MCHASH_NWORDS 128 2768 #else 2769 #define MCHASH_NWORDS 32 2770 #endif /* DP83820 */ 2771 u_int16_t mchash[MCHASH_NWORDS]; 2772 int i; 2773 2774 /* 2775 * Initialize the prototype RFCR. 2776 * Enable the receive filter, and accept on 2777 * Perfect (destination address) Match 2778 * If IFF_BROADCAST, also accept all broadcast packets. 2779 * If IFF_PROMISC, accept all unicast packets (and later, set 2780 * IFF_ALLMULTI and accept all multicast, too). 2781 */ 2782 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2783 if (ifp->if_flags & IFF_BROADCAST) 2784 sc->sc_rfcr |= RFCR_AAB; 2785 if (ifp->if_flags & IFF_PROMISC) { 2786 sc->sc_rfcr |= RFCR_AAP; 2787 goto allmulti; 2788 } 2789 2790 #ifdef DP83820 2791 /* 2792 * Set up the DP83820 multicast address filter by passing all multicast 2793 * addresses through a CRC generator, and then using the high-order 2794 * 11 bits as an index into the 2048 bit multicast hash table. The 2795 * high-order 7 bits select the slot, while the low-order 4 bits 2796 * select the bit within the slot. Note that only the low 16-bits 2797 * of each filter word are used, and there are 128 filter words. 2798 */ 2799 #else 2800 /* 2801 * Set up the DP83815 multicast address filter by passing all multicast 2802 * addresses through a CRC generator, and then using the high-order 2803 * 9 bits as an index into the 512 bit multicast hash table. The 2804 * high-order 5 bits select the slot, while the low-order 4 bits 2805 * select the bit within the slot. Note that only the low 16-bits 2806 * of each filter word are used, and there are 32 filter words. 2807 */ 2808 #endif /* DP83820 */ 2809 2810 memset(mchash, 0, sizeof(mchash)); 2811 2812 ifp->if_flags &= ~IFF_ALLMULTI; 2813 ETHER_FIRST_MULTI(step, ec, enm); 2814 if (enm == NULL) 2815 goto setit; 2816 while (enm != NULL) { 2817 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2818 /* 2819 * We must listen to a range of multicast addresses. 2820 * For now, just accept all multicasts, rather than 2821 * trying to set only those filter bits needed to match 2822 * the range. (At this time, the only use of address 2823 * ranges is for IP multicast routing, for which the 2824 * range is big enough to require all bits set.) 2825 */ 2826 goto allmulti; 2827 } 2828 2829 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2830 2831 #ifdef DP83820 2832 /* Just want the 11 most significant bits. */ 2833 hash = crc >> 21; 2834 #else 2835 /* Just want the 9 most significant bits. */ 2836 hash = crc >> 23; 2837 #endif /* DP83820 */ 2838 2839 slot = hash >> 4; 2840 bit = hash & 0xf; 2841 2842 /* Set the corresponding bit in the hash table. */ 2843 mchash[slot] |= 1 << bit; 2844 2845 ETHER_NEXT_MULTI(step, enm); 2846 } 2847 sc->sc_rfcr |= RFCR_MHEN; 2848 goto setit; 2849 2850 allmulti: 2851 ifp->if_flags |= IFF_ALLMULTI; 2852 sc->sc_rfcr |= RFCR_AAM; 2853 2854 setit: 2855 #define FILTER_EMIT(addr, data) \ 2856 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2857 delay(1); \ 2858 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2859 delay(1) 2860 2861 /* 2862 * Disable receive filter, and program the node address. 2863 */ 2864 cp = LLADDR(ifp->if_sadl); 2865 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 2866 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 2867 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 2868 2869 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2870 /* 2871 * Program the multicast hash table. 2872 */ 2873 for (i = 0; i < MCHASH_NWORDS; i++) { 2874 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 2875 mchash[i]); 2876 } 2877 } 2878 #undef FILTER_EMIT 2879 #undef MCHASH_NWORDS 2880 2881 /* 2882 * Re-enable the receiver filter. 2883 */ 2884 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2885 } 2886 2887 #if defined(DP83820) 2888 /* 2889 * sip_dp83820_mii_readreg: [mii interface function] 2890 * 2891 * Read a PHY register on the MII of the DP83820. 2892 */ 2893 int 2894 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 2895 { 2896 struct sip_softc *sc = (void *) self; 2897 2898 if (sc->sc_cfg & CFG_TBI_EN) { 2899 bus_addr_t tbireg; 2900 int rv; 2901 2902 if (phy != 0) 2903 return (0); 2904 2905 switch (reg) { 2906 case MII_BMCR: tbireg = SIP_TBICR; break; 2907 case MII_BMSR: tbireg = SIP_TBISR; break; 2908 case MII_ANAR: tbireg = SIP_TANAR; break; 2909 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 2910 case MII_ANER: tbireg = SIP_TANER; break; 2911 case MII_EXTSR: 2912 /* 2913 * Don't even bother reading the TESR register. 2914 * The manual documents that the device has 2915 * 1000baseX full/half capability, but the 2916 * register itself seems read back 0 on some 2917 * boards. Just hard-code the result. 2918 */ 2919 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 2920 2921 default: 2922 return (0); 2923 } 2924 2925 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 2926 if (tbireg == SIP_TBISR) { 2927 /* LINK and ACOMP are switched! */ 2928 int val = rv; 2929 2930 rv = 0; 2931 if (val & TBISR_MR_LINK_STATUS) 2932 rv |= BMSR_LINK; 2933 if (val & TBISR_MR_AN_COMPLETE) 2934 rv |= BMSR_ACOMP; 2935 2936 /* 2937 * The manual claims this register reads back 0 2938 * on hard and soft reset. But we want to let 2939 * the gentbi driver know that we support auto- 2940 * negotiation, so hard-code this bit in the 2941 * result. 2942 */ 2943 rv |= BMSR_ANEG | BMSR_EXTSTAT; 2944 } 2945 2946 return (rv); 2947 } 2948 2949 return (mii_bitbang_readreg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2950 phy, reg)); 2951 } 2952 2953 /* 2954 * sip_dp83820_mii_writereg: [mii interface function] 2955 * 2956 * Write a PHY register on the MII of the DP83820. 2957 */ 2958 void 2959 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 2960 { 2961 struct sip_softc *sc = (void *) self; 2962 2963 if (sc->sc_cfg & CFG_TBI_EN) { 2964 bus_addr_t tbireg; 2965 2966 if (phy != 0) 2967 return; 2968 2969 switch (reg) { 2970 case MII_BMCR: tbireg = SIP_TBICR; break; 2971 case MII_ANAR: tbireg = SIP_TANAR; break; 2972 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 2973 default: 2974 return; 2975 } 2976 2977 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 2978 return; 2979 } 2980 2981 mii_bitbang_writereg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2982 phy, reg, val); 2983 } 2984 2985 /* 2986 * sip_dp83815_mii_statchg: [mii interface function] 2987 * 2988 * Callback from MII layer when media changes. 2989 */ 2990 void 2991 SIP_DECL(dp83820_mii_statchg)(struct device *self) 2992 { 2993 struct sip_softc *sc = (struct sip_softc *) self; 2994 u_int32_t cfg; 2995 2996 /* 2997 * Update TXCFG for full-duplex operation. 2998 */ 2999 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3000 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3001 else 3002 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3003 3004 /* 3005 * Update RXCFG for full-duplex or loopback. 3006 */ 3007 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3008 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3009 sc->sc_rxcfg |= RXCFG_ATX; 3010 else 3011 sc->sc_rxcfg &= ~RXCFG_ATX; 3012 3013 /* 3014 * Update CFG for MII/GMII. 3015 */ 3016 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3017 cfg = sc->sc_cfg | CFG_MODE_1000; 3018 else 3019 cfg = sc->sc_cfg; 3020 3021 /* 3022 * XXX 802.3x flow control. 3023 */ 3024 3025 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3026 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3027 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3028 } 3029 3030 /* 3031 * sip_dp83820_mii_bitbang_read: [mii bit-bang interface function] 3032 * 3033 * Read the MII serial port for the MII bit-bang module. 3034 */ 3035 u_int32_t 3036 SIP_DECL(dp83820_mii_bitbang_read)(struct device *self) 3037 { 3038 struct sip_softc *sc = (void *) self; 3039 3040 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3041 } 3042 3043 /* 3044 * sip_dp83820_mii_bitbang_write: [mii big-bang interface function] 3045 * 3046 * Write the MII serial port for the MII bit-bang module. 3047 */ 3048 void 3049 SIP_DECL(dp83820_mii_bitbang_write)(struct device *self, u_int32_t val) 3050 { 3051 struct sip_softc *sc = (void *) self; 3052 3053 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3054 } 3055 #else /* ! DP83820 */ 3056 /* 3057 * sip_sis900_mii_readreg: [mii interface function] 3058 * 3059 * Read a PHY register on the MII. 3060 */ 3061 int 3062 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 3063 { 3064 struct sip_softc *sc = (struct sip_softc *) self; 3065 u_int32_t enphy; 3066 3067 /* 3068 * The SiS 900 has only an internal PHY on the MII. Only allow 3069 * MII address 0. 3070 */ 3071 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 3072 sc->sc_rev < SIS_REV_635 && phy != 0) 3073 return (0); 3074 3075 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3076 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3077 ENPHY_RWCMD | ENPHY_ACCESS); 3078 do { 3079 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3080 } while (enphy & ENPHY_ACCESS); 3081 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3082 } 3083 3084 /* 3085 * sip_sis900_mii_writereg: [mii interface function] 3086 * 3087 * Write a PHY register on the MII. 3088 */ 3089 void 3090 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 3091 { 3092 struct sip_softc *sc = (struct sip_softc *) self; 3093 u_int32_t enphy; 3094 3095 /* 3096 * The SiS 900 has only an internal PHY on the MII. Only allow 3097 * MII address 0. 3098 */ 3099 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 3100 sc->sc_rev < SIS_REV_635 && phy != 0) 3101 return; 3102 3103 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3104 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3105 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3106 do { 3107 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3108 } while (enphy & ENPHY_ACCESS); 3109 } 3110 3111 /* 3112 * sip_sis900_mii_statchg: [mii interface function] 3113 * 3114 * Callback from MII layer when media changes. 3115 */ 3116 void 3117 SIP_DECL(sis900_mii_statchg)(struct device *self) 3118 { 3119 struct sip_softc *sc = (struct sip_softc *) self; 3120 u_int32_t flowctl; 3121 3122 /* 3123 * Update TXCFG for full-duplex operation. 3124 */ 3125 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3126 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3127 else 3128 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3129 3130 /* 3131 * Update RXCFG for full-duplex or loopback. 3132 */ 3133 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3134 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3135 sc->sc_rxcfg |= RXCFG_ATX; 3136 else 3137 sc->sc_rxcfg &= ~RXCFG_ATX; 3138 3139 /* 3140 * Update IMR for use of 802.3x flow control. 3141 */ 3142 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 3143 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3144 flowctl = FLOWCTL_FLOWEN; 3145 } else { 3146 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3147 flowctl = 0; 3148 } 3149 3150 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3151 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3152 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3153 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3154 } 3155 3156 /* 3157 * sip_dp83815_mii_readreg: [mii interface function] 3158 * 3159 * Read a PHY register on the MII. 3160 */ 3161 int 3162 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 3163 { 3164 struct sip_softc *sc = (struct sip_softc *) self; 3165 u_int32_t val; 3166 3167 /* 3168 * The DP83815 only has an internal PHY. Only allow 3169 * MII address 0. 3170 */ 3171 if (phy != 0) 3172 return (0); 3173 3174 /* 3175 * Apparently, after a reset, the DP83815 can take a while 3176 * to respond. During this recovery period, the BMSR returns 3177 * a value of 0. Catch this -- it's not supposed to happen 3178 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3179 * PHY to come back to life. 3180 * 3181 * This works out because the BMSR is the first register 3182 * read during the PHY probe process. 3183 */ 3184 do { 3185 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3186 } while (reg == MII_BMSR && val == 0); 3187 3188 return (val & 0xffff); 3189 } 3190 3191 /* 3192 * sip_dp83815_mii_writereg: [mii interface function] 3193 * 3194 * Write a PHY register to the MII. 3195 */ 3196 void 3197 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3198 { 3199 struct sip_softc *sc = (struct sip_softc *) self; 3200 3201 /* 3202 * The DP83815 only has an internal PHY. Only allow 3203 * MII address 0. 3204 */ 3205 if (phy != 0) 3206 return; 3207 3208 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3209 } 3210 3211 /* 3212 * sip_dp83815_mii_statchg: [mii interface function] 3213 * 3214 * Callback from MII layer when media changes. 3215 */ 3216 void 3217 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3218 { 3219 struct sip_softc *sc = (struct sip_softc *) self; 3220 3221 /* 3222 * Update TXCFG for full-duplex operation. 3223 */ 3224 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3225 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3226 else 3227 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3228 3229 /* 3230 * Update RXCFG for full-duplex or loopback. 3231 */ 3232 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3233 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3234 sc->sc_rxcfg |= RXCFG_ATX; 3235 else 3236 sc->sc_rxcfg &= ~RXCFG_ATX; 3237 3238 /* 3239 * XXX 802.3x flow control. 3240 */ 3241 3242 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3243 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3244 3245 /* 3246 * Some DP83815s experience problems when used with short 3247 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3248 * sequence adjusts the DSP's signal attenuation to fix the 3249 * problem. 3250 */ 3251 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3252 uint32_t reg; 3253 3254 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3255 3256 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3257 reg &= 0x0fff; 3258 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3259 delay(100); 3260 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3261 reg &= 0x00ff; 3262 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3263 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3264 0x00e8); 3265 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3266 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3267 reg | 0x20); 3268 } 3269 3270 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3271 } 3272 } 3273 #endif /* DP83820 */ 3274 3275 #if defined(DP83820) 3276 void 3277 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3278 const struct pci_attach_args *pa, u_int8_t *enaddr) 3279 { 3280 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3281 u_int8_t cksum, *e, match; 3282 int i; 3283 3284 /* 3285 * EEPROM data format for the DP83820 can be found in 3286 * the DP83820 manual, section 4.2.4. 3287 */ 3288 3289 SIP_DECL(read_eeprom)(sc, 0, 3290 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3291 3292 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3293 match = ~(match - 1); 3294 3295 cksum = 0x55; 3296 e = (u_int8_t *) eeprom_data; 3297 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3298 cksum += *e++; 3299 3300 if (cksum != match) 3301 printf("%s: Checksum (%x) mismatch (%x)", 3302 sc->sc_dev.dv_xname, cksum, match); 3303 3304 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3305 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3306 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3307 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3308 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3309 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3310 } 3311 #else /* ! DP83820 */ 3312 void 3313 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3314 const struct pci_attach_args *pa, u_int8_t *enaddr) 3315 { 3316 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3317 3318 switch (sc->sc_rev) { 3319 case SIS_REV_630S: 3320 case SIS_REV_630E: 3321 case SIS_REV_630EA1: 3322 case SIS_REV_630ET: 3323 case SIS_REV_635: 3324 /* 3325 * The MAC address for the on-board Ethernet of 3326 * the SiS 630 chipset is in the NVRAM. Kick 3327 * the chip into re-loading it from NVRAM, and 3328 * read the MAC address out of the filter registers. 3329 */ 3330 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3331 3332 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3333 RFCR_RFADDR_NODE0); 3334 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3335 0xffff; 3336 3337 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3338 RFCR_RFADDR_NODE2); 3339 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3340 0xffff; 3341 3342 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3343 RFCR_RFADDR_NODE4); 3344 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3345 0xffff; 3346 break; 3347 3348 default: 3349 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3350 sizeof(myea) / sizeof(myea[0]), myea); 3351 } 3352 3353 enaddr[0] = myea[0] & 0xff; 3354 enaddr[1] = myea[0] >> 8; 3355 enaddr[2] = myea[1] & 0xff; 3356 enaddr[3] = myea[1] >> 8; 3357 enaddr[4] = myea[2] & 0xff; 3358 enaddr[5] = myea[2] >> 8; 3359 } 3360 3361 /* Table and macro to bit-reverse an octet. */ 3362 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3363 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3364 3365 void 3366 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3367 const struct pci_attach_args *pa, u_int8_t *enaddr) 3368 { 3369 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3370 u_int8_t cksum, *e, match; 3371 int i; 3372 3373 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3374 sizeof(eeprom_data[0]), eeprom_data); 3375 3376 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3377 match = ~(match - 1); 3378 3379 cksum = 0x55; 3380 e = (u_int8_t *) eeprom_data; 3381 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3382 cksum += *e++; 3383 } 3384 if (cksum != match) { 3385 printf("%s: Checksum (%x) mismatch (%x)", 3386 sc->sc_dev.dv_xname, cksum, match); 3387 } 3388 3389 /* 3390 * Unrolled because it makes slightly more sense this way. 3391 * The DP83815 stores the MAC address in bit 0 of word 6 3392 * through bit 15 of word 8. 3393 */ 3394 ea = &eeprom_data[6]; 3395 enaddr[0] = ((*ea & 0x1) << 7); 3396 ea++; 3397 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3398 enaddr[1] = ((*ea & 0x1FE) >> 1); 3399 enaddr[2] = ((*ea & 0x1) << 7); 3400 ea++; 3401 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3402 enaddr[3] = ((*ea & 0x1FE) >> 1); 3403 enaddr[4] = ((*ea & 0x1) << 7); 3404 ea++; 3405 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3406 enaddr[5] = ((*ea & 0x1FE) >> 1); 3407 3408 /* 3409 * In case that's not weird enough, we also need to reverse 3410 * the bits in each byte. This all actually makes more sense 3411 * if you think about the EEPROM storage as an array of bits 3412 * being shifted into bytes, but that's not how we're looking 3413 * at it here... 3414 */ 3415 for (i = 0; i < 6 ;i++) 3416 enaddr[i] = bbr(enaddr[i]); 3417 } 3418 #endif /* DP83820 */ 3419 3420 /* 3421 * sip_mediastatus: [ifmedia interface function] 3422 * 3423 * Get the current interface media status. 3424 */ 3425 void 3426 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3427 { 3428 struct sip_softc *sc = ifp->if_softc; 3429 3430 mii_pollstat(&sc->sc_mii); 3431 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3432 ifmr->ifm_active = sc->sc_mii.mii_media_active; 3433 } 3434 3435 /* 3436 * sip_mediachange: [ifmedia interface function] 3437 * 3438 * Set hardware to newly-selected media. 3439 */ 3440 int 3441 SIP_DECL(mediachange)(struct ifnet *ifp) 3442 { 3443 struct sip_softc *sc = ifp->if_softc; 3444 3445 if (ifp->if_flags & IFF_UP) 3446 mii_mediachg(&sc->sc_mii); 3447 return (0); 3448 } 3449
Indexes created Tue Sep 30 11:09:46 GMT 2025