if_sip.c revision 1.85
1 /* $NetBSD: if_sip.c,v 1.85 2003/12/04 13:57:31 keihan Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.85 2003/12/04 13:57:31 keihan Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <machine/bus.h> 116 #include <machine/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #ifdef DP83820 122 #include <dev/mii/mii_bitbang.h> 123 #endif /* DP83820 */ 124 125 #include <dev/pci/pcireg.h> 126 #include <dev/pci/pcivar.h> 127 #include <dev/pci/pcidevs.h> 128 129 #include <dev/pci/if_sipreg.h> 130 131 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 132 #define SIP_DECL(x) __CONCAT(gsip_,x) 133 #else /* SiS900 and DP83815 */ 134 #define SIP_DECL(x) __CONCAT(sip_,x) 135 #endif 136 137 #define SIP_STR(x) __STRING(SIP_DECL(x)) 138 139 /* 140 * Transmit descriptor list size. This is arbitrary, but allocate 141 * enough descriptors for 128 pending transmissions, and 8 segments 142 * per packet. This MUST work out to a power of 2. 143 */ 144 #define SIP_NTXSEGS 16 145 #define SIP_NTXSEGS_ALLOC 8 146 147 #define SIP_TXQUEUELEN 256 148 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 149 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 150 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 151 152 #if defined(DP83820) 153 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 154 #else 155 #define TX_DMAMAP_SIZE MCLBYTES 156 #endif 157 158 /* 159 * Receive descriptor list size. We have one Rx buffer per incoming 160 * packet, so this logic is a little simpler. 161 * 162 * Actually, on the DP83820, we allow the packet to consume more than 163 * one buffer, in order to support jumbo Ethernet frames. In that 164 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 165 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 166 * so we'd better be quick about handling receive interrupts. 167 */ 168 #if defined(DP83820) 169 #define SIP_NRXDESC 256 170 #else 171 #define SIP_NRXDESC 128 172 #endif /* DP83820 */ 173 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 174 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 175 176 /* 177 * Control structures are DMA'd to the SiS900 chip. We allocate them in 178 * a single clump that maps to a single DMA segment to make several things 179 * easier. 180 */ 181 struct sip_control_data { 182 /* 183 * The transmit descriptors. 184 */ 185 struct sip_desc scd_txdescs[SIP_NTXDESC]; 186 187 /* 188 * The receive descriptors. 189 */ 190 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 191 }; 192 193 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 194 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 195 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 196 197 /* 198 * Software state for transmit jobs. 199 */ 200 struct sip_txsoft { 201 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 202 bus_dmamap_t txs_dmamap; /* our DMA map */ 203 int txs_firstdesc; /* first descriptor in packet */ 204 int txs_lastdesc; /* last descriptor in packet */ 205 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 206 }; 207 208 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 209 210 /* 211 * Software state for receive jobs. 212 */ 213 struct sip_rxsoft { 214 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 215 bus_dmamap_t rxs_dmamap; /* our DMA map */ 216 }; 217 218 /* 219 * Software state per device. 220 */ 221 struct sip_softc { 222 struct device sc_dev; /* generic device information */ 223 bus_space_tag_t sc_st; /* bus space tag */ 224 bus_space_handle_t sc_sh; /* bus space handle */ 225 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 226 struct ethercom sc_ethercom; /* ethernet common data */ 227 void *sc_sdhook; /* shutdown hook */ 228 229 const struct sip_product *sc_model; /* which model are we? */ 230 int sc_rev; /* chip revision */ 231 232 void *sc_ih; /* interrupt cookie */ 233 234 struct mii_data sc_mii; /* MII/media information */ 235 236 struct callout sc_tick_ch; /* tick callout */ 237 238 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 239 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 240 241 /* 242 * Software state for transmit and receive descriptors. 243 */ 244 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 245 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 246 247 /* 248 * Control data structures. 249 */ 250 struct sip_control_data *sc_control_data; 251 #define sc_txdescs sc_control_data->scd_txdescs 252 #define sc_rxdescs sc_control_data->scd_rxdescs 253 254 #ifdef SIP_EVENT_COUNTERS 255 /* 256 * Event counters. 257 */ 258 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 259 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 260 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 261 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 262 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 263 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 264 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 265 #ifdef DP83820 266 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 267 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 268 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 269 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 270 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 271 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 272 #endif /* DP83820 */ 273 #endif /* SIP_EVENT_COUNTERS */ 274 275 u_int32_t sc_txcfg; /* prototype TXCFG register */ 276 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 277 u_int32_t sc_imr; /* prototype IMR register */ 278 u_int32_t sc_rfcr; /* prototype RFCR register */ 279 280 u_int32_t sc_cfg; /* prototype CFG register */ 281 282 #ifdef DP83820 283 u_int32_t sc_gpior; /* prototype GPIOR register */ 284 #endif /* DP83820 */ 285 286 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 287 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 288 289 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 290 291 int sc_flags; /* misc. flags; see below */ 292 293 int sc_txfree; /* number of free Tx descriptors */ 294 int sc_txnext; /* next ready Tx descriptor */ 295 int sc_txwin; /* Tx descriptors since last intr */ 296 297 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 298 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 299 300 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 301 #if defined(DP83820) 302 int sc_rxdiscard; 303 int sc_rxlen; 304 struct mbuf *sc_rxhead; 305 struct mbuf *sc_rxtail; 306 struct mbuf **sc_rxtailp; 307 #endif /* DP83820 */ 308 309 #if NRND > 0 310 rndsource_element_t rnd_source; /* random source */ 311 #endif 312 }; 313 314 /* sc_flags */ 315 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 316 317 #ifdef DP83820 318 #define SIP_RXCHAIN_RESET(sc) \ 319 do { \ 320 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 321 *(sc)->sc_rxtailp = NULL; \ 322 (sc)->sc_rxlen = 0; \ 323 } while (/*CONSTCOND*/0) 324 325 #define SIP_RXCHAIN_LINK(sc, m) \ 326 do { \ 327 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 328 (sc)->sc_rxtailp = &(m)->m_next; \ 329 } while (/*CONSTCOND*/0) 330 #endif /* DP83820 */ 331 332 #ifdef SIP_EVENT_COUNTERS 333 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 334 #else 335 #define SIP_EVCNT_INCR(ev) /* nothing */ 336 #endif 337 338 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 339 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 340 341 #define SIP_CDTXSYNC(sc, x, n, ops) \ 342 do { \ 343 int __x, __n; \ 344 \ 345 __x = (x); \ 346 __n = (n); \ 347 \ 348 /* If it will wrap around, sync to the end of the ring. */ \ 349 if ((__x + __n) > SIP_NTXDESC) { \ 350 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 351 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 352 (SIP_NTXDESC - __x), (ops)); \ 353 __n -= (SIP_NTXDESC - __x); \ 354 __x = 0; \ 355 } \ 356 \ 357 /* Now sync whatever is left. */ \ 358 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 359 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 360 } while (0) 361 362 #define SIP_CDRXSYNC(sc, x, ops) \ 363 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 364 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 365 366 #ifdef DP83820 367 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 368 #define SIP_RXBUF_LEN (MCLBYTES - 4) 369 #else 370 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 371 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 372 #endif 373 #define SIP_INIT_RXDESC(sc, x) \ 374 do { \ 375 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 376 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 377 \ 378 __sipd->sipd_link = \ 379 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 380 __sipd->sipd_bufptr = \ 381 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 382 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 383 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 384 SIP_INIT_RXDESC_EXTSTS \ 385 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 386 } while (0) 387 388 #define SIP_CHIP_VERS(sc, v, p, r) \ 389 ((sc)->sc_model->sip_vendor == (v) && \ 390 (sc)->sc_model->sip_product == (p) && \ 391 (sc)->sc_rev == (r)) 392 393 #define SIP_CHIP_MODEL(sc, v, p) \ 394 ((sc)->sc_model->sip_vendor == (v) && \ 395 (sc)->sc_model->sip_product == (p)) 396 397 #if !defined(DP83820) 398 #define SIP_SIS900_REV(sc, rev) \ 399 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 400 #endif 401 402 #define SIP_TIMEOUT 1000 403 404 void SIP_DECL(start)(struct ifnet *); 405 void SIP_DECL(watchdog)(struct ifnet *); 406 int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 407 int SIP_DECL(init)(struct ifnet *); 408 void SIP_DECL(stop)(struct ifnet *, int); 409 410 void SIP_DECL(shutdown)(void *); 411 412 void SIP_DECL(reset)(struct sip_softc *); 413 void SIP_DECL(rxdrain)(struct sip_softc *); 414 int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 415 void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, u_int16_t *); 416 void SIP_DECL(tick)(void *); 417 418 #if !defined(DP83820) 419 void SIP_DECL(sis900_set_filter)(struct sip_softc *); 420 #endif /* ! DP83820 */ 421 void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 422 423 #if defined(DP83820) 424 void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 425 const struct pci_attach_args *, u_int8_t *); 426 #else 427 static void SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc); 428 void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 429 const struct pci_attach_args *, u_int8_t *); 430 void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 431 const struct pci_attach_args *, u_int8_t *); 432 #endif /* DP83820 */ 433 434 int SIP_DECL(intr)(void *); 435 void SIP_DECL(txintr)(struct sip_softc *); 436 void SIP_DECL(rxintr)(struct sip_softc *); 437 438 #if defined(DP83820) 439 int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 440 void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 441 void SIP_DECL(dp83820_mii_statchg)(struct device *); 442 #else 443 static void SIP_DECL(sis900_mii_sync)(struct sip_softc *); 444 static void SIP_DECL(sis900_mii_send)(struct sip_softc *, u_int32_t, int); 445 int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 446 void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 447 void SIP_DECL(sis900_mii_statchg)(struct device *); 448 449 int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 450 void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 451 void SIP_DECL(dp83815_mii_statchg)(struct device *); 452 #endif /* DP83820 */ 453 454 int SIP_DECL(mediachange)(struct ifnet *); 455 void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 456 457 int SIP_DECL(match)(struct device *, struct cfdata *, void *); 458 void SIP_DECL(attach)(struct device *, struct device *, void *); 459 460 int SIP_DECL(copy_small) = 0; 461 462 #ifdef DP83820 463 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 464 gsip_match, gsip_attach, NULL, NULL); 465 #else 466 CFATTACH_DECL(sip, sizeof(struct sip_softc), 467 sip_match, sip_attach, NULL, NULL); 468 #endif 469 470 /* 471 * Descriptions of the variants of the SiS900. 472 */ 473 struct sip_variant { 474 int (*sipv_mii_readreg)(struct device *, int, int); 475 void (*sipv_mii_writereg)(struct device *, int, int, int); 476 void (*sipv_mii_statchg)(struct device *); 477 void (*sipv_set_filter)(struct sip_softc *); 478 void (*sipv_read_macaddr)(struct sip_softc *, 479 const struct pci_attach_args *, u_int8_t *); 480 }; 481 482 #if defined(DP83820) 483 u_int32_t SIP_DECL(dp83820_mii_bitbang_read)(struct device *); 484 void SIP_DECL(dp83820_mii_bitbang_write)(struct device *, u_int32_t); 485 486 const struct mii_bitbang_ops SIP_DECL(dp83820_mii_bitbang_ops) = { 487 SIP_DECL(dp83820_mii_bitbang_read), 488 SIP_DECL(dp83820_mii_bitbang_write), 489 { 490 EROMAR_MDIO, /* MII_BIT_MDO */ 491 EROMAR_MDIO, /* MII_BIT_MDI */ 492 EROMAR_MDC, /* MII_BIT_MDC */ 493 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 494 0, /* MII_BIT_DIR_PHY_HOST */ 495 } 496 }; 497 #endif /* DP83820 */ 498 499 #if defined(DP83820) 500 const struct sip_variant SIP_DECL(variant_dp83820) = { 501 SIP_DECL(dp83820_mii_readreg), 502 SIP_DECL(dp83820_mii_writereg), 503 SIP_DECL(dp83820_mii_statchg), 504 SIP_DECL(dp83815_set_filter), 505 SIP_DECL(dp83820_read_macaddr), 506 }; 507 #else 508 const struct sip_variant SIP_DECL(variant_sis900) = { 509 SIP_DECL(sis900_mii_readreg), 510 SIP_DECL(sis900_mii_writereg), 511 SIP_DECL(sis900_mii_statchg), 512 SIP_DECL(sis900_set_filter), 513 SIP_DECL(sis900_read_macaddr), 514 }; 515 516 const struct sip_variant SIP_DECL(variant_dp83815) = { 517 SIP_DECL(dp83815_mii_readreg), 518 SIP_DECL(dp83815_mii_writereg), 519 SIP_DECL(dp83815_mii_statchg), 520 SIP_DECL(dp83815_set_filter), 521 SIP_DECL(dp83815_read_macaddr), 522 }; 523 #endif /* DP83820 */ 524 525 /* 526 * Devices supported by this driver. 527 */ 528 const struct sip_product { 529 pci_vendor_id_t sip_vendor; 530 pci_product_id_t sip_product; 531 const char *sip_name; 532 const struct sip_variant *sip_variant; 533 } SIP_DECL(products)[] = { 534 #if defined(DP83820) 535 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 536 "NatSemi DP83820 Gigabit Ethernet", 537 &SIP_DECL(variant_dp83820) }, 538 #else 539 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 540 "SiS 900 10/100 Ethernet", 541 &SIP_DECL(variant_sis900) }, 542 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 543 "SiS 7016 10/100 Ethernet", 544 &SIP_DECL(variant_sis900) }, 545 546 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 547 "NatSemi DP83815 10/100 Ethernet", 548 &SIP_DECL(variant_dp83815) }, 549 #endif /* DP83820 */ 550 551 { 0, 0, 552 NULL, 553 NULL }, 554 }; 555 556 static const struct sip_product * 557 SIP_DECL(lookup)(const struct pci_attach_args *pa) 558 { 559 const struct sip_product *sip; 560 561 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 562 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 563 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 564 return (sip); 565 } 566 return (NULL); 567 } 568 569 #ifdef DP83820 570 /* 571 * I really hate stupid hardware vendors. There's a bit in the EEPROM 572 * which indicates if the card can do 64-bit data transfers. Unfortunately, 573 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 574 * which means we try to use 64-bit data transfers on those cards if we 575 * happen to be plugged into a 32-bit slot. 576 * 577 * What we do is use this table of cards known to be 64-bit cards. If 578 * you have a 64-bit card who's subsystem ID is not listed in this table, 579 * send the output of "pcictl dump ..." of the device to me so that your 580 * card will use the 64-bit data path when plugged into a 64-bit slot. 581 * 582 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 583 * June 30, 2002 584 */ 585 static int 586 SIP_DECL(check_64bit)(const struct pci_attach_args *pa) 587 { 588 static const struct { 589 pci_vendor_id_t c64_vendor; 590 pci_product_id_t c64_product; 591 } card64[] = { 592 /* Asante GigaNIX */ 593 { 0x128a, 0x0002 }, 594 595 /* Accton EN1407-T, Planex GN-1000TE */ 596 { 0x1113, 0x1407 }, 597 598 /* Netgear GA-621 */ 599 { 0x1385, 0x621a }, 600 601 /* SMC EZ Card */ 602 { 0x10b8, 0x9462 }, 603 604 { 0, 0} 605 }; 606 pcireg_t subsys; 607 int i; 608 609 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 610 611 for (i = 0; card64[i].c64_vendor != 0; i++) { 612 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 613 PCI_PRODUCT(subsys) == card64[i].c64_product) 614 return (1); 615 } 616 617 return (0); 618 } 619 #endif /* DP83820 */ 620 621 int 622 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 623 { 624 struct pci_attach_args *pa = aux; 625 626 if (SIP_DECL(lookup)(pa) != NULL) 627 return (1); 628 629 return (0); 630 } 631 632 void 633 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 634 { 635 struct sip_softc *sc = (struct sip_softc *) self; 636 struct pci_attach_args *pa = aux; 637 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 638 pci_chipset_tag_t pc = pa->pa_pc; 639 pci_intr_handle_t ih; 640 const char *intrstr = NULL; 641 bus_space_tag_t iot, memt; 642 bus_space_handle_t ioh, memh; 643 bus_dma_segment_t seg; 644 int ioh_valid, memh_valid; 645 int i, rseg, error; 646 const struct sip_product *sip; 647 pcireg_t pmode; 648 u_int8_t enaddr[ETHER_ADDR_LEN]; 649 int pmreg; 650 #ifdef DP83820 651 pcireg_t memtype; 652 u_int32_t reg; 653 #endif /* DP83820 */ 654 655 callout_init(&sc->sc_tick_ch); 656 657 sip = SIP_DECL(lookup)(pa); 658 if (sip == NULL) { 659 printf("\n"); 660 panic(SIP_STR(attach) ": impossible"); 661 } 662 sc->sc_rev = PCI_REVISION(pa->pa_class); 663 664 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 665 666 sc->sc_model = sip; 667 668 /* 669 * XXX Work-around broken PXE firmware on some boards. 670 * 671 * The DP83815 shares an address decoder with the MEM BAR 672 * and the ROM BAR. Make sure the ROM BAR is disabled, 673 * so that memory mapped access works. 674 */ 675 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 676 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 677 ~PCI_MAPREG_ROM_ENABLE); 678 679 /* 680 * Map the device. 681 */ 682 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 683 PCI_MAPREG_TYPE_IO, 0, 684 &iot, &ioh, NULL, NULL) == 0); 685 #ifdef DP83820 686 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 687 switch (memtype) { 688 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 689 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 690 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 691 memtype, 0, &memt, &memh, NULL, NULL) == 0); 692 break; 693 default: 694 memh_valid = 0; 695 } 696 #else 697 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 698 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 699 &memt, &memh, NULL, NULL) == 0); 700 #endif /* DP83820 */ 701 702 if (memh_valid) { 703 sc->sc_st = memt; 704 sc->sc_sh = memh; 705 } else if (ioh_valid) { 706 sc->sc_st = iot; 707 sc->sc_sh = ioh; 708 } else { 709 printf("%s: unable to map device registers\n", 710 sc->sc_dev.dv_xname); 711 return; 712 } 713 714 sc->sc_dmat = pa->pa_dmat; 715 716 /* 717 * Make sure bus mastering is enabled. Also make sure 718 * Write/Invalidate is enabled if we're allowed to use it. 719 */ 720 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 721 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 722 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 723 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 724 pmreg | PCI_COMMAND_MASTER_ENABLE); 725 726 /* Get it out of power save mode if needed. */ 727 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 728 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 729 PCI_PMCSR_STATE_MASK; 730 if (pmode == PCI_PMCSR_STATE_D3) { 731 /* 732 * The card has lost all configuration data in 733 * this state, so punt. 734 */ 735 printf("%s: unable to wake up from power state D3\n", 736 sc->sc_dev.dv_xname); 737 return; 738 } 739 if (pmode != PCI_PMCSR_STATE_D0) { 740 printf("%s: waking up from power state D%d\n", 741 sc->sc_dev.dv_xname, pmode); 742 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 743 PCI_PMCSR_STATE_D0); 744 } 745 } 746 747 /* 748 * Map and establish our interrupt. 749 */ 750 if (pci_intr_map(pa, &ih)) { 751 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 752 return; 753 } 754 intrstr = pci_intr_string(pc, ih); 755 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 756 if (sc->sc_ih == NULL) { 757 printf("%s: unable to establish interrupt", 758 sc->sc_dev.dv_xname); 759 if (intrstr != NULL) 760 printf(" at %s", intrstr); 761 printf("\n"); 762 return; 763 } 764 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 765 766 SIMPLEQ_INIT(&sc->sc_txfreeq); 767 SIMPLEQ_INIT(&sc->sc_txdirtyq); 768 769 /* 770 * Allocate the control data structures, and create and load the 771 * DMA map for it. 772 */ 773 if ((error = bus_dmamem_alloc(sc->sc_dmat, 774 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 775 0)) != 0) { 776 printf("%s: unable to allocate control data, error = %d\n", 777 sc->sc_dev.dv_xname, error); 778 goto fail_0; 779 } 780 781 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 782 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 783 BUS_DMA_COHERENT)) != 0) { 784 printf("%s: unable to map control data, error = %d\n", 785 sc->sc_dev.dv_xname, error); 786 goto fail_1; 787 } 788 789 if ((error = bus_dmamap_create(sc->sc_dmat, 790 sizeof(struct sip_control_data), 1, 791 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 792 printf("%s: unable to create control data DMA map, " 793 "error = %d\n", sc->sc_dev.dv_xname, error); 794 goto fail_2; 795 } 796 797 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 798 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 799 0)) != 0) { 800 printf("%s: unable to load control data DMA map, error = %d\n", 801 sc->sc_dev.dv_xname, error); 802 goto fail_3; 803 } 804 805 /* 806 * Create the transmit buffer DMA maps. 807 */ 808 for (i = 0; i < SIP_TXQUEUELEN; i++) { 809 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 810 SIP_NTXSEGS, MCLBYTES, 0, 0, 811 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 812 printf("%s: unable to create tx DMA map %d, " 813 "error = %d\n", sc->sc_dev.dv_xname, i, error); 814 goto fail_4; 815 } 816 } 817 818 /* 819 * Create the receive buffer DMA maps. 820 */ 821 for (i = 0; i < SIP_NRXDESC; i++) { 822 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 823 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 824 printf("%s: unable to create rx DMA map %d, " 825 "error = %d\n", sc->sc_dev.dv_xname, i, error); 826 goto fail_5; 827 } 828 sc->sc_rxsoft[i].rxs_mbuf = NULL; 829 } 830 831 /* 832 * Reset the chip to a known state. 833 */ 834 SIP_DECL(reset)(sc); 835 836 /* 837 * Read the Ethernet address from the EEPROM. This might 838 * also fetch other stuff from the EEPROM and stash it 839 * in the softc. 840 */ 841 sc->sc_cfg = 0; 842 #if !defined(DP83820) 843 if (SIP_SIS900_REV(sc,SIS_REV_635) || 844 SIP_SIS900_REV(sc,SIS_REV_900B)) 845 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 846 #endif 847 848 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 849 850 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 851 ether_sprintf(enaddr)); 852 853 /* 854 * Initialize the configuration register: aggressive PCI 855 * bus request algorithm, default backoff, default OW timer, 856 * default parity error detection. 857 * 858 * NOTE: "Big endian mode" is useless on the SiS900 and 859 * friends -- it affects packet data, not descriptors. 860 */ 861 #ifdef DP83820 862 /* 863 * Cause the chip to load configuration data from the EEPROM. 864 */ 865 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 866 for (i = 0; i < 10000; i++) { 867 delay(10); 868 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 869 PTSCR_EELOAD_EN) == 0) 870 break; 871 } 872 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 873 PTSCR_EELOAD_EN) { 874 printf("%s: timeout loading configuration from EEPROM\n", 875 sc->sc_dev.dv_xname); 876 return; 877 } 878 879 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 880 881 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 882 if (reg & CFG_PCI64_DET) { 883 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 884 /* 885 * Check to see if this card is 64-bit. If so, enable 64-bit 886 * data transfers. 887 * 888 * We can't use the DATA64_EN bit in the EEPROM, because 889 * vendors of 32-bit cards fail to clear that bit in many 890 * cases (yet the card still detects that it's in a 64-bit 891 * slot; go figure). 892 */ 893 if (SIP_DECL(check_64bit)(pa)) { 894 sc->sc_cfg |= CFG_DATA64_EN; 895 printf(", using 64-bit data transfers"); 896 } 897 printf("\n"); 898 } 899 900 /* 901 * XXX Need some PCI flags indicating support for 902 * XXX 64-bit addressing. 903 */ 904 #if 0 905 if (reg & CFG_M64ADDR) 906 sc->sc_cfg |= CFG_M64ADDR; 907 if (reg & CFG_T64ADDR) 908 sc->sc_cfg |= CFG_T64ADDR; 909 #endif 910 911 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 912 const char *sep = ""; 913 printf("%s: using ", sc->sc_dev.dv_xname); 914 if (reg & CFG_EXT_125) { 915 sc->sc_cfg |= CFG_EXT_125; 916 printf("%s125MHz clock", sep); 917 sep = ", "; 918 } 919 if (reg & CFG_TBI_EN) { 920 sc->sc_cfg |= CFG_TBI_EN; 921 printf("%sten-bit interface", sep); 922 sep = ", "; 923 } 924 printf("\n"); 925 } 926 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 927 (reg & CFG_MRM_DIS) != 0) 928 sc->sc_cfg |= CFG_MRM_DIS; 929 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 930 (reg & CFG_MWI_DIS) != 0) 931 sc->sc_cfg |= CFG_MWI_DIS; 932 933 /* 934 * Use the extended descriptor format on the DP83820. This 935 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 936 * checksumming. 937 */ 938 sc->sc_cfg |= CFG_EXTSTS_EN; 939 #endif /* DP83820 */ 940 941 /* 942 * Initialize our media structures and probe the MII. 943 */ 944 sc->sc_mii.mii_ifp = ifp; 945 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 946 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 947 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 948 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, SIP_DECL(mediachange), 949 SIP_DECL(mediastatus)); 950 951 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 952 MII_OFFSET_ANY, 0); 953 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 954 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 955 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 956 } else 957 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 958 959 ifp = &sc->sc_ethercom.ec_if; 960 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 961 ifp->if_softc = sc; 962 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 963 ifp->if_ioctl = SIP_DECL(ioctl); 964 ifp->if_start = SIP_DECL(start); 965 ifp->if_watchdog = SIP_DECL(watchdog); 966 ifp->if_init = SIP_DECL(init); 967 ifp->if_stop = SIP_DECL(stop); 968 IFQ_SET_READY(&ifp->if_snd); 969 970 /* 971 * We can support 802.1Q VLAN-sized frames. 972 */ 973 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 974 975 #ifdef DP83820 976 /* 977 * And the DP83820 can do VLAN tagging in hardware, and 978 * support the jumbo Ethernet MTU. 979 */ 980 sc->sc_ethercom.ec_capabilities |= 981 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 982 983 /* 984 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 985 * in hardware. 986 */ 987 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 988 IFCAP_CSUM_UDPv4; 989 #endif /* DP83820 */ 990 991 /* 992 * Attach the interface. 993 */ 994 if_attach(ifp); 995 ether_ifattach(ifp, enaddr); 996 #if NRND > 0 997 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 998 RND_TYPE_NET, 0); 999 #endif 1000 1001 /* 1002 * The number of bytes that must be available in 1003 * the Tx FIFO before the bus master can DMA more 1004 * data into the FIFO. 1005 */ 1006 sc->sc_tx_fill_thresh = 64 / 32; 1007 1008 /* 1009 * Start at a drain threshold of 512 bytes. We will 1010 * increase it if a DMA underrun occurs. 1011 * 1012 * XXX The minimum value of this variable should be 1013 * tuned. We may be able to improve performance 1014 * by starting with a lower value. That, however, 1015 * may trash the first few outgoing packets if the 1016 * PCI bus is saturated. 1017 */ 1018 sc->sc_tx_drain_thresh = 1504 / 32; 1019 1020 /* 1021 * Initialize the Rx FIFO drain threshold. 1022 * 1023 * This is in units of 8 bytes. 1024 * 1025 * We should never set this value lower than 2; 14 bytes are 1026 * required to filter the packet. 1027 */ 1028 sc->sc_rx_drain_thresh = 128 / 8; 1029 1030 #ifdef SIP_EVENT_COUNTERS 1031 /* 1032 * Attach event counters. 1033 */ 1034 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1035 NULL, sc->sc_dev.dv_xname, "txsstall"); 1036 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1037 NULL, sc->sc_dev.dv_xname, "txdstall"); 1038 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1039 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1040 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1041 NULL, sc->sc_dev.dv_xname, "txdintr"); 1042 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1043 NULL, sc->sc_dev.dv_xname, "txiintr"); 1044 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1045 NULL, sc->sc_dev.dv_xname, "rxintr"); 1046 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1047 NULL, sc->sc_dev.dv_xname, "hiberr"); 1048 #ifdef DP83820 1049 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1050 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1051 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1052 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1053 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1054 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1055 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1056 NULL, sc->sc_dev.dv_xname, "txipsum"); 1057 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1058 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1059 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1060 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1061 #endif /* DP83820 */ 1062 #endif /* SIP_EVENT_COUNTERS */ 1063 1064 /* 1065 * Make sure the interface is shutdown during reboot. 1066 */ 1067 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 1068 if (sc->sc_sdhook == NULL) 1069 printf("%s: WARNING: unable to establish shutdown hook\n", 1070 sc->sc_dev.dv_xname); 1071 return; 1072 1073 /* 1074 * Free any resources we've allocated during the failed attach 1075 * attempt. Do this in reverse order and fall through. 1076 */ 1077 fail_5: 1078 for (i = 0; i < SIP_NRXDESC; i++) { 1079 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1080 bus_dmamap_destroy(sc->sc_dmat, 1081 sc->sc_rxsoft[i].rxs_dmamap); 1082 } 1083 fail_4: 1084 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1085 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1086 bus_dmamap_destroy(sc->sc_dmat, 1087 sc->sc_txsoft[i].txs_dmamap); 1088 } 1089 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1090 fail_3: 1091 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1092 fail_2: 1093 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1094 sizeof(struct sip_control_data)); 1095 fail_1: 1096 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1097 fail_0: 1098 return; 1099 } 1100 1101 /* 1102 * sip_shutdown: 1103 * 1104 * Make sure the interface is stopped at reboot time. 1105 */ 1106 void 1107 SIP_DECL(shutdown)(void *arg) 1108 { 1109 struct sip_softc *sc = arg; 1110 1111 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1112 } 1113 1114 /* 1115 * sip_start: [ifnet interface function] 1116 * 1117 * Start packet transmission on the interface. 1118 */ 1119 void 1120 SIP_DECL(start)(struct ifnet *ifp) 1121 { 1122 struct sip_softc *sc = ifp->if_softc; 1123 struct mbuf *m0; 1124 #ifndef DP83820 1125 struct mbuf *m; 1126 #endif 1127 struct sip_txsoft *txs; 1128 bus_dmamap_t dmamap; 1129 int error, nexttx, lasttx, seg; 1130 int ofree = sc->sc_txfree; 1131 #if 0 1132 int firsttx = sc->sc_txnext; 1133 #endif 1134 #ifdef DP83820 1135 struct m_tag *mtag; 1136 u_int32_t extsts; 1137 #endif 1138 1139 /* 1140 * If we've been told to pause, don't transmit any more packets. 1141 */ 1142 if (sc->sc_flags & SIPF_PAUSED) 1143 ifp->if_flags |= IFF_OACTIVE; 1144 1145 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1146 return; 1147 1148 /* 1149 * Loop through the send queue, setting up transmit descriptors 1150 * until we drain the queue, or use up all available transmit 1151 * descriptors. 1152 */ 1153 for (;;) { 1154 /* Get a work queue entry. */ 1155 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1156 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1157 break; 1158 } 1159 1160 /* 1161 * Grab a packet off the queue. 1162 */ 1163 IFQ_POLL(&ifp->if_snd, m0); 1164 if (m0 == NULL) 1165 break; 1166 #ifndef DP83820 1167 m = NULL; 1168 #endif 1169 1170 dmamap = txs->txs_dmamap; 1171 1172 #ifdef DP83820 1173 /* 1174 * Load the DMA map. If this fails, the packet either 1175 * didn't fit in the allotted number of segments, or we 1176 * were short on resources. For the too-many-segments 1177 * case, we simply report an error and drop the packet, 1178 * since we can't sanely copy a jumbo packet to a single 1179 * buffer. 1180 */ 1181 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1182 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1183 if (error) { 1184 if (error == EFBIG) { 1185 printf("%s: Tx packet consumes too many " 1186 "DMA segments, dropping...\n", 1187 sc->sc_dev.dv_xname); 1188 IFQ_DEQUEUE(&ifp->if_snd, m0); 1189 m_freem(m0); 1190 continue; 1191 } 1192 /* 1193 * Short on resources, just stop for now. 1194 */ 1195 break; 1196 } 1197 #else /* DP83820 */ 1198 /* 1199 * Load the DMA map. If this fails, the packet either 1200 * didn't fit in the alloted number of segments, or we 1201 * were short on resources. In this case, we'll copy 1202 * and try again. 1203 */ 1204 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1205 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1206 MGETHDR(m, M_DONTWAIT, MT_DATA); 1207 if (m == NULL) { 1208 printf("%s: unable to allocate Tx mbuf\n", 1209 sc->sc_dev.dv_xname); 1210 break; 1211 } 1212 if (m0->m_pkthdr.len > MHLEN) { 1213 MCLGET(m, M_DONTWAIT); 1214 if ((m->m_flags & M_EXT) == 0) { 1215 printf("%s: unable to allocate Tx " 1216 "cluster\n", sc->sc_dev.dv_xname); 1217 m_freem(m); 1218 break; 1219 } 1220 } 1221 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1222 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1223 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1224 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1225 if (error) { 1226 printf("%s: unable to load Tx buffer, " 1227 "error = %d\n", sc->sc_dev.dv_xname, error); 1228 break; 1229 } 1230 } 1231 #endif /* DP83820 */ 1232 1233 /* 1234 * Ensure we have enough descriptors free to describe 1235 * the packet. Note, we always reserve one descriptor 1236 * at the end of the ring as a termination point, to 1237 * prevent wrap-around. 1238 */ 1239 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1240 /* 1241 * Not enough free descriptors to transmit this 1242 * packet. We haven't committed anything yet, 1243 * so just unload the DMA map, put the packet 1244 * back on the queue, and punt. Notify the upper 1245 * layer that there are not more slots left. 1246 * 1247 * XXX We could allocate an mbuf and copy, but 1248 * XXX is it worth it? 1249 */ 1250 ifp->if_flags |= IFF_OACTIVE; 1251 bus_dmamap_unload(sc->sc_dmat, dmamap); 1252 #ifndef DP83820 1253 if (m != NULL) 1254 m_freem(m); 1255 #endif 1256 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1257 break; 1258 } 1259 1260 IFQ_DEQUEUE(&ifp->if_snd, m0); 1261 #ifndef DP83820 1262 if (m != NULL) { 1263 m_freem(m0); 1264 m0 = m; 1265 } 1266 #endif 1267 1268 /* 1269 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1270 */ 1271 1272 /* Sync the DMA map. */ 1273 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1274 BUS_DMASYNC_PREWRITE); 1275 1276 /* 1277 * Initialize the transmit descriptors. 1278 */ 1279 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1280 seg < dmamap->dm_nsegs; 1281 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1282 /* 1283 * If this is the first descriptor we're 1284 * enqueueing, don't set the OWN bit just 1285 * yet. That could cause a race condition. 1286 * We'll do it below. 1287 */ 1288 sc->sc_txdescs[nexttx].sipd_bufptr = 1289 htole32(dmamap->dm_segs[seg].ds_addr); 1290 sc->sc_txdescs[nexttx].sipd_cmdsts = 1291 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1292 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1293 #ifdef DP83820 1294 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1295 #endif /* DP83820 */ 1296 lasttx = nexttx; 1297 } 1298 1299 /* Clear the MORE bit on the last segment. */ 1300 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1301 1302 /* 1303 * If we're in the interrupt delay window, delay the 1304 * interrupt. 1305 */ 1306 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1307 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1308 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1309 htole32(CMDSTS_INTR); 1310 sc->sc_txwin = 0; 1311 } 1312 1313 #ifdef DP83820 1314 /* 1315 * If VLANs are enabled and the packet has a VLAN tag, set 1316 * up the descriptor to encapsulate the packet for us. 1317 * 1318 * This apparently has to be on the last descriptor of 1319 * the packet. 1320 */ 1321 if (sc->sc_ethercom.ec_nvlans != 0 && 1322 (mtag = m_tag_find(m0, PACKET_TAG_VLAN, NULL)) != NULL) { 1323 sc->sc_txdescs[lasttx].sipd_extsts |= 1324 htole32(EXTSTS_VPKT | 1325 (*(u_int *)(mtag + 1) & EXTSTS_VTCI)); 1326 } 1327 1328 /* 1329 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1330 * checksumming, set up the descriptor to do this work 1331 * for us. 1332 * 1333 * This apparently has to be on the first descriptor of 1334 * the packet. 1335 * 1336 * Byte-swap constants so the compiler can optimize. 1337 */ 1338 extsts = 0; 1339 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1340 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1341 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1342 extsts |= htole32(EXTSTS_IPPKT); 1343 } 1344 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1345 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1346 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1347 extsts |= htole32(EXTSTS_TCPPKT); 1348 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1349 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1350 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1351 extsts |= htole32(EXTSTS_UDPPKT); 1352 } 1353 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1354 #endif /* DP83820 */ 1355 1356 /* Sync the descriptors we're using. */ 1357 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1358 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1359 1360 /* 1361 * The entire packet is set up. Give the first descrptor 1362 * to the chip now. 1363 */ 1364 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1365 htole32(CMDSTS_OWN); 1366 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1367 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1368 1369 /* 1370 * Store a pointer to the packet so we can free it later, 1371 * and remember what txdirty will be once the packet is 1372 * done. 1373 */ 1374 txs->txs_mbuf = m0; 1375 txs->txs_firstdesc = sc->sc_txnext; 1376 txs->txs_lastdesc = lasttx; 1377 1378 /* Advance the tx pointer. */ 1379 sc->sc_txfree -= dmamap->dm_nsegs; 1380 sc->sc_txnext = nexttx; 1381 1382 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1383 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1384 1385 #if NBPFILTER > 0 1386 /* 1387 * Pass the packet to any BPF listeners. 1388 */ 1389 if (ifp->if_bpf) 1390 bpf_mtap(ifp->if_bpf, m0); 1391 #endif /* NBPFILTER > 0 */ 1392 } 1393 1394 if (txs == NULL || sc->sc_txfree == 0) { 1395 /* No more slots left; notify upper layer. */ 1396 ifp->if_flags |= IFF_OACTIVE; 1397 } 1398 1399 if (sc->sc_txfree != ofree) { 1400 /* 1401 * Start the transmit process. Note, the manual says 1402 * that if there are no pending transmissions in the 1403 * chip's internal queue (indicated by TXE being clear), 1404 * then the driver software must set the TXDP to the 1405 * first descriptor to be transmitted. However, if we 1406 * do this, it causes serious performance degredation on 1407 * the DP83820 under load, not setting TXDP doesn't seem 1408 * to adversely affect the SiS 900 or DP83815. 1409 * 1410 * Well, I guess it wouldn't be the first time a manual 1411 * has lied -- and they could be speaking of the NULL- 1412 * terminated descriptor list case, rather than OWN- 1413 * terminated rings. 1414 */ 1415 #if 0 1416 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1417 CR_TXE) == 0) { 1418 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1419 SIP_CDTXADDR(sc, firsttx)); 1420 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1421 } 1422 #else 1423 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1424 #endif 1425 1426 /* Set a watchdog timer in case the chip flakes out. */ 1427 ifp->if_timer = 5; 1428 } 1429 } 1430 1431 /* 1432 * sip_watchdog: [ifnet interface function] 1433 * 1434 * Watchdog timer handler. 1435 */ 1436 void 1437 SIP_DECL(watchdog)(struct ifnet *ifp) 1438 { 1439 struct sip_softc *sc = ifp->if_softc; 1440 1441 /* 1442 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1443 * If we get a timeout, try and sweep up transmit descriptors. 1444 * If we manage to sweep them all up, ignore the lack of 1445 * interrupt. 1446 */ 1447 SIP_DECL(txintr)(sc); 1448 1449 if (sc->sc_txfree != SIP_NTXDESC) { 1450 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1451 ifp->if_oerrors++; 1452 1453 /* Reset the interface. */ 1454 (void) SIP_DECL(init)(ifp); 1455 } else if (ifp->if_flags & IFF_DEBUG) 1456 printf("%s: recovered from device timeout\n", 1457 sc->sc_dev.dv_xname); 1458 1459 /* Try to get more packets going. */ 1460 SIP_DECL(start)(ifp); 1461 } 1462 1463 /* 1464 * sip_ioctl: [ifnet interface function] 1465 * 1466 * Handle control requests from the operator. 1467 */ 1468 int 1469 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1470 { 1471 struct sip_softc *sc = ifp->if_softc; 1472 struct ifreq *ifr = (struct ifreq *)data; 1473 int s, error; 1474 1475 s = splnet(); 1476 1477 switch (cmd) { 1478 case SIOCSIFMEDIA: 1479 case SIOCGIFMEDIA: 1480 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1481 break; 1482 1483 default: 1484 error = ether_ioctl(ifp, cmd, data); 1485 if (error == ENETRESET) { 1486 /* 1487 * Multicast list has changed; set the hardware filter 1488 * accordingly. 1489 */ 1490 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1491 error = 0; 1492 } 1493 break; 1494 } 1495 1496 /* Try to get more packets going. */ 1497 SIP_DECL(start)(ifp); 1498 1499 splx(s); 1500 return (error); 1501 } 1502 1503 /* 1504 * sip_intr: 1505 * 1506 * Interrupt service routine. 1507 */ 1508 int 1509 SIP_DECL(intr)(void *arg) 1510 { 1511 struct sip_softc *sc = arg; 1512 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1513 u_int32_t isr; 1514 int handled = 0; 1515 1516 for (;;) { 1517 /* Reading clears interrupt. */ 1518 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1519 if ((isr & sc->sc_imr) == 0) 1520 break; 1521 1522 #if NRND > 0 1523 if (RND_ENABLED(&sc->rnd_source)) 1524 rnd_add_uint32(&sc->rnd_source, isr); 1525 #endif 1526 1527 handled = 1; 1528 1529 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1530 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1531 1532 /* Grab any new packets. */ 1533 SIP_DECL(rxintr)(sc); 1534 1535 if (isr & ISR_RXORN) { 1536 printf("%s: receive FIFO overrun\n", 1537 sc->sc_dev.dv_xname); 1538 1539 /* XXX adjust rx_drain_thresh? */ 1540 } 1541 1542 if (isr & ISR_RXIDLE) { 1543 printf("%s: receive ring overrun\n", 1544 sc->sc_dev.dv_xname); 1545 1546 /* Get the receive process going again. */ 1547 bus_space_write_4(sc->sc_st, sc->sc_sh, 1548 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1549 bus_space_write_4(sc->sc_st, sc->sc_sh, 1550 SIP_CR, CR_RXE); 1551 } 1552 } 1553 1554 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1555 #ifdef SIP_EVENT_COUNTERS 1556 if (isr & ISR_TXDESC) 1557 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1558 else if (isr & ISR_TXIDLE) 1559 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1560 #endif 1561 1562 /* Sweep up transmit descriptors. */ 1563 SIP_DECL(txintr)(sc); 1564 1565 if (isr & ISR_TXURN) { 1566 u_int32_t thresh; 1567 1568 printf("%s: transmit FIFO underrun", 1569 sc->sc_dev.dv_xname); 1570 1571 thresh = sc->sc_tx_drain_thresh + 1; 1572 if (thresh <= TXCFG_DRTH && 1573 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1574 (sc->sc_tx_fill_thresh * 32))) { 1575 printf("; increasing Tx drain " 1576 "threshold to %u bytes\n", 1577 thresh * 32); 1578 sc->sc_tx_drain_thresh = thresh; 1579 (void) SIP_DECL(init)(ifp); 1580 } else { 1581 (void) SIP_DECL(init)(ifp); 1582 printf("\n"); 1583 } 1584 } 1585 } 1586 1587 #if !defined(DP83820) 1588 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1589 if (isr & ISR_PAUSE_ST) { 1590 sc->sc_flags |= SIPF_PAUSED; 1591 ifp->if_flags |= IFF_OACTIVE; 1592 } 1593 if (isr & ISR_PAUSE_END) { 1594 sc->sc_flags &= ~SIPF_PAUSED; 1595 ifp->if_flags &= ~IFF_OACTIVE; 1596 } 1597 } 1598 #endif /* ! DP83820 */ 1599 1600 if (isr & ISR_HIBERR) { 1601 int want_init = 0; 1602 1603 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1604 1605 #define PRINTERR(bit, str) \ 1606 do { \ 1607 if ((isr & (bit)) != 0) { \ 1608 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1609 printf("%s: %s\n", \ 1610 sc->sc_dev.dv_xname, str); \ 1611 want_init = 1; \ 1612 } \ 1613 } while (/*CONSTCOND*/0) 1614 1615 PRINTERR(ISR_DPERR, "parity error"); 1616 PRINTERR(ISR_SSERR, "system error"); 1617 PRINTERR(ISR_RMABT, "master abort"); 1618 PRINTERR(ISR_RTABT, "target abort"); 1619 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1620 /* 1621 * Ignore: 1622 * Tx reset complete 1623 * Rx reset complete 1624 */ 1625 if (want_init) 1626 (void) SIP_DECL(init)(ifp); 1627 #undef PRINTERR 1628 } 1629 } 1630 1631 /* Try to get more packets going. */ 1632 SIP_DECL(start)(ifp); 1633 1634 return (handled); 1635 } 1636 1637 /* 1638 * sip_txintr: 1639 * 1640 * Helper; handle transmit interrupts. 1641 */ 1642 void 1643 SIP_DECL(txintr)(struct sip_softc *sc) 1644 { 1645 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1646 struct sip_txsoft *txs; 1647 u_int32_t cmdsts; 1648 1649 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1650 ifp->if_flags &= ~IFF_OACTIVE; 1651 1652 /* 1653 * Go through our Tx list and free mbufs for those 1654 * frames which have been transmitted. 1655 */ 1656 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1657 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1658 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1659 1660 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1661 if (cmdsts & CMDSTS_OWN) 1662 break; 1663 1664 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1665 1666 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1667 1668 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1669 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1670 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1671 m_freem(txs->txs_mbuf); 1672 txs->txs_mbuf = NULL; 1673 1674 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1675 1676 /* 1677 * Check for errors and collisions. 1678 */ 1679 if (cmdsts & 1680 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1681 ifp->if_oerrors++; 1682 if (cmdsts & CMDSTS_Tx_EC) 1683 ifp->if_collisions += 16; 1684 if (ifp->if_flags & IFF_DEBUG) { 1685 if (cmdsts & CMDSTS_Tx_ED) 1686 printf("%s: excessive deferral\n", 1687 sc->sc_dev.dv_xname); 1688 if (cmdsts & CMDSTS_Tx_EC) 1689 printf("%s: excessive collisions\n", 1690 sc->sc_dev.dv_xname); 1691 } 1692 } else { 1693 /* Packet was transmitted successfully. */ 1694 ifp->if_opackets++; 1695 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1696 } 1697 } 1698 1699 /* 1700 * If there are no more pending transmissions, cancel the watchdog 1701 * timer. 1702 */ 1703 if (txs == NULL) { 1704 ifp->if_timer = 0; 1705 sc->sc_txwin = 0; 1706 } 1707 } 1708 1709 #if defined(DP83820) 1710 /* 1711 * sip_rxintr: 1712 * 1713 * Helper; handle receive interrupts. 1714 */ 1715 void 1716 SIP_DECL(rxintr)(struct sip_softc *sc) 1717 { 1718 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1719 struct sip_rxsoft *rxs; 1720 struct mbuf *m, *tailm; 1721 u_int32_t cmdsts, extsts; 1722 int i, len; 1723 1724 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1725 rxs = &sc->sc_rxsoft[i]; 1726 1727 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1728 1729 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1730 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1731 1732 /* 1733 * NOTE: OWN is set if owned by _consumer_. We're the 1734 * consumer of the receive ring, so if the bit is clear, 1735 * we have processed all of the packets. 1736 */ 1737 if ((cmdsts & CMDSTS_OWN) == 0) { 1738 /* 1739 * We have processed all of the receive buffers. 1740 */ 1741 break; 1742 } 1743 1744 if (__predict_false(sc->sc_rxdiscard)) { 1745 SIP_INIT_RXDESC(sc, i); 1746 if ((cmdsts & CMDSTS_MORE) == 0) { 1747 /* Reset our state. */ 1748 sc->sc_rxdiscard = 0; 1749 } 1750 continue; 1751 } 1752 1753 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1754 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1755 1756 m = rxs->rxs_mbuf; 1757 1758 /* 1759 * Add a new receive buffer to the ring. 1760 */ 1761 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1762 /* 1763 * Failed, throw away what we've done so 1764 * far, and discard the rest of the packet. 1765 */ 1766 ifp->if_ierrors++; 1767 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1768 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1769 SIP_INIT_RXDESC(sc, i); 1770 if (cmdsts & CMDSTS_MORE) 1771 sc->sc_rxdiscard = 1; 1772 if (sc->sc_rxhead != NULL) 1773 m_freem(sc->sc_rxhead); 1774 SIP_RXCHAIN_RESET(sc); 1775 continue; 1776 } 1777 1778 SIP_RXCHAIN_LINK(sc, m); 1779 1780 /* 1781 * If this is not the end of the packet, keep 1782 * looking. 1783 */ 1784 if (cmdsts & CMDSTS_MORE) { 1785 sc->sc_rxlen += m->m_len; 1786 continue; 1787 } 1788 1789 /* 1790 * Okay, we have the entire packet now... 1791 */ 1792 *sc->sc_rxtailp = NULL; 1793 m = sc->sc_rxhead; 1794 tailm = sc->sc_rxtail; 1795 1796 SIP_RXCHAIN_RESET(sc); 1797 1798 /* 1799 * If an error occurred, update stats and drop the packet. 1800 */ 1801 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1802 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1803 ifp->if_ierrors++; 1804 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1805 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1806 /* Receive overrun handled elsewhere. */ 1807 printf("%s: receive descriptor error\n", 1808 sc->sc_dev.dv_xname); 1809 } 1810 #define PRINTERR(bit, str) \ 1811 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1812 (cmdsts & (bit)) != 0) \ 1813 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1814 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1815 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1816 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1817 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1818 #undef PRINTERR 1819 m_freem(m); 1820 continue; 1821 } 1822 1823 /* 1824 * No errors. 1825 * 1826 * Note, the DP83820 includes the CRC with 1827 * every packet. 1828 */ 1829 len = CMDSTS_SIZE(cmdsts); 1830 tailm->m_len = len - sc->sc_rxlen; 1831 1832 /* 1833 * If the packet is small enough to fit in a 1834 * single header mbuf, allocate one and copy 1835 * the data into it. This greatly reduces 1836 * memory consumption when we receive lots 1837 * of small packets. 1838 */ 1839 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1840 struct mbuf *nm; 1841 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1842 if (nm == NULL) { 1843 ifp->if_ierrors++; 1844 m_freem(m); 1845 continue; 1846 } 1847 nm->m_data += 2; 1848 nm->m_pkthdr.len = nm->m_len = len; 1849 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1850 m_freem(m); 1851 m = nm; 1852 } 1853 #ifndef __NO_STRICT_ALIGNMENT 1854 else { 1855 /* 1856 * The DP83820's receive buffers must be 4-byte 1857 * aligned. But this means that the data after 1858 * the Ethernet header is misaligned. To compensate, 1859 * we have artificially shortened the buffer size 1860 * in the descriptor, and we do an overlapping copy 1861 * of the data two bytes further in (in the first 1862 * buffer of the chain only). 1863 */ 1864 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1865 m->m_len); 1866 m->m_data += 2; 1867 } 1868 #endif /* ! __NO_STRICT_ALIGNMENT */ 1869 1870 /* 1871 * If VLANs are enabled, VLAN packets have been unwrapped 1872 * for us. Associate the tag with the packet. 1873 */ 1874 if (sc->sc_ethercom.ec_nvlans != 0 && 1875 (extsts & EXTSTS_VPKT) != 0) { 1876 struct m_tag *vtag; 1877 1878 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 1879 M_NOWAIT); 1880 if (vtag == NULL) { 1881 ifp->if_ierrors++; 1882 printf("%s: unable to allocate VLAN tag\n", 1883 sc->sc_dev.dv_xname); 1884 m_freem(m); 1885 continue; 1886 } 1887 1888 *(u_int *)(vtag + 1) = ntohs(extsts & EXTSTS_VTCI); 1889 } 1890 1891 /* 1892 * Set the incoming checksum information for the 1893 * packet. 1894 */ 1895 if ((extsts & EXTSTS_IPPKT) != 0) { 1896 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1897 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1898 if (extsts & EXTSTS_Rx_IPERR) 1899 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1900 if (extsts & EXTSTS_TCPPKT) { 1901 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1902 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1903 if (extsts & EXTSTS_Rx_TCPERR) 1904 m->m_pkthdr.csum_flags |= 1905 M_CSUM_TCP_UDP_BAD; 1906 } else if (extsts & EXTSTS_UDPPKT) { 1907 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1908 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1909 if (extsts & EXTSTS_Rx_UDPERR) 1910 m->m_pkthdr.csum_flags |= 1911 M_CSUM_TCP_UDP_BAD; 1912 } 1913 } 1914 1915 ifp->if_ipackets++; 1916 m->m_flags |= M_HASFCS; 1917 m->m_pkthdr.rcvif = ifp; 1918 m->m_pkthdr.len = len; 1919 1920 #if NBPFILTER > 0 1921 /* 1922 * Pass this up to any BPF listeners, but only 1923 * pass if up the stack if it's for us. 1924 */ 1925 if (ifp->if_bpf) 1926 bpf_mtap(ifp->if_bpf, m); 1927 #endif /* NBPFILTER > 0 */ 1928 1929 /* Pass it on. */ 1930 (*ifp->if_input)(ifp, m); 1931 } 1932 1933 /* Update the receive pointer. */ 1934 sc->sc_rxptr = i; 1935 } 1936 #else /* ! DP83820 */ 1937 /* 1938 * sip_rxintr: 1939 * 1940 * Helper; handle receive interrupts. 1941 */ 1942 void 1943 SIP_DECL(rxintr)(struct sip_softc *sc) 1944 { 1945 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1946 struct sip_rxsoft *rxs; 1947 struct mbuf *m; 1948 u_int32_t cmdsts; 1949 int i, len; 1950 1951 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1952 rxs = &sc->sc_rxsoft[i]; 1953 1954 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1955 1956 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1957 1958 /* 1959 * NOTE: OWN is set if owned by _consumer_. We're the 1960 * consumer of the receive ring, so if the bit is clear, 1961 * we have processed all of the packets. 1962 */ 1963 if ((cmdsts & CMDSTS_OWN) == 0) { 1964 /* 1965 * We have processed all of the receive buffers. 1966 */ 1967 break; 1968 } 1969 1970 /* 1971 * If any collisions were seen on the wire, count one. 1972 */ 1973 if (cmdsts & CMDSTS_Rx_COL) 1974 ifp->if_collisions++; 1975 1976 /* 1977 * If an error occurred, update stats, clear the status 1978 * word, and leave the packet buffer in place. It will 1979 * simply be reused the next time the ring comes around. 1980 */ 1981 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1982 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1983 ifp->if_ierrors++; 1984 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1985 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1986 /* Receive overrun handled elsewhere. */ 1987 printf("%s: receive descriptor error\n", 1988 sc->sc_dev.dv_xname); 1989 } 1990 #define PRINTERR(bit, str) \ 1991 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1992 (cmdsts & (bit)) != 0) \ 1993 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1994 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1995 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1996 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1997 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1998 #undef PRINTERR 1999 SIP_INIT_RXDESC(sc, i); 2000 continue; 2001 } 2002 2003 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2004 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2005 2006 /* 2007 * No errors; receive the packet. Note, the SiS 900 2008 * includes the CRC with every packet. 2009 */ 2010 len = CMDSTS_SIZE(cmdsts); 2011 2012 #ifdef __NO_STRICT_ALIGNMENT 2013 /* 2014 * If the packet is small enough to fit in a 2015 * single header mbuf, allocate one and copy 2016 * the data into it. This greatly reduces 2017 * memory consumption when we receive lots 2018 * of small packets. 2019 * 2020 * Otherwise, we add a new buffer to the receive 2021 * chain. If this fails, we drop the packet and 2022 * recycle the old buffer. 2023 */ 2024 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 2025 MGETHDR(m, M_DONTWAIT, MT_DATA); 2026 if (m == NULL) 2027 goto dropit; 2028 memcpy(mtod(m, caddr_t), 2029 mtod(rxs->rxs_mbuf, caddr_t), len); 2030 SIP_INIT_RXDESC(sc, i); 2031 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2032 rxs->rxs_dmamap->dm_mapsize, 2033 BUS_DMASYNC_PREREAD); 2034 } else { 2035 m = rxs->rxs_mbuf; 2036 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 2037 dropit: 2038 ifp->if_ierrors++; 2039 SIP_INIT_RXDESC(sc, i); 2040 bus_dmamap_sync(sc->sc_dmat, 2041 rxs->rxs_dmamap, 0, 2042 rxs->rxs_dmamap->dm_mapsize, 2043 BUS_DMASYNC_PREREAD); 2044 continue; 2045 } 2046 } 2047 #else 2048 /* 2049 * The SiS 900's receive buffers must be 4-byte aligned. 2050 * But this means that the data after the Ethernet header 2051 * is misaligned. We must allocate a new buffer and 2052 * copy the data, shifted forward 2 bytes. 2053 */ 2054 MGETHDR(m, M_DONTWAIT, MT_DATA); 2055 if (m == NULL) { 2056 dropit: 2057 ifp->if_ierrors++; 2058 SIP_INIT_RXDESC(sc, i); 2059 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2060 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2061 continue; 2062 } 2063 if (len > (MHLEN - 2)) { 2064 MCLGET(m, M_DONTWAIT); 2065 if ((m->m_flags & M_EXT) == 0) { 2066 m_freem(m); 2067 goto dropit; 2068 } 2069 } 2070 m->m_data += 2; 2071 2072 /* 2073 * Note that we use clusters for incoming frames, so the 2074 * buffer is virtually contiguous. 2075 */ 2076 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 2077 2078 /* Allow the receive descriptor to continue using its mbuf. */ 2079 SIP_INIT_RXDESC(sc, i); 2080 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2081 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2082 #endif /* __NO_STRICT_ALIGNMENT */ 2083 2084 ifp->if_ipackets++; 2085 m->m_flags |= M_HASFCS; 2086 m->m_pkthdr.rcvif = ifp; 2087 m->m_pkthdr.len = m->m_len = len; 2088 2089 #if NBPFILTER > 0 2090 /* 2091 * Pass this up to any BPF listeners, but only 2092 * pass if up the stack if it's for us. 2093 */ 2094 if (ifp->if_bpf) 2095 bpf_mtap(ifp->if_bpf, m); 2096 #endif /* NBPFILTER > 0 */ 2097 2098 /* Pass it on. */ 2099 (*ifp->if_input)(ifp, m); 2100 } 2101 2102 /* Update the receive pointer. */ 2103 sc->sc_rxptr = i; 2104 } 2105 #endif /* DP83820 */ 2106 2107 /* 2108 * sip_tick: 2109 * 2110 * One second timer, used to tick the MII. 2111 */ 2112 void 2113 SIP_DECL(tick)(void *arg) 2114 { 2115 struct sip_softc *sc = arg; 2116 int s; 2117 2118 s = splnet(); 2119 mii_tick(&sc->sc_mii); 2120 splx(s); 2121 2122 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2123 } 2124 2125 /* 2126 * sip_reset: 2127 * 2128 * Perform a soft reset on the SiS 900. 2129 */ 2130 void 2131 SIP_DECL(reset)(struct sip_softc *sc) 2132 { 2133 bus_space_tag_t st = sc->sc_st; 2134 bus_space_handle_t sh = sc->sc_sh; 2135 int i; 2136 2137 bus_space_write_4(st, sh, SIP_IER, 0); 2138 bus_space_write_4(st, sh, SIP_IMR, 0); 2139 bus_space_write_4(st, sh, SIP_RFCR, 0); 2140 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2141 2142 for (i = 0; i < SIP_TIMEOUT; i++) { 2143 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2144 break; 2145 delay(2); 2146 } 2147 2148 if (i == SIP_TIMEOUT) 2149 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2150 2151 delay(1000); 2152 2153 #ifdef DP83820 2154 /* 2155 * Set the general purpose I/O bits. Do it here in case we 2156 * need to have GPIO set up to talk to the media interface. 2157 */ 2158 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2159 delay(1000); 2160 #endif /* DP83820 */ 2161 } 2162 2163 /* 2164 * sip_init: [ ifnet interface function ] 2165 * 2166 * Initialize the interface. Must be called at splnet(). 2167 */ 2168 int 2169 SIP_DECL(init)(struct ifnet *ifp) 2170 { 2171 struct sip_softc *sc = ifp->if_softc; 2172 bus_space_tag_t st = sc->sc_st; 2173 bus_space_handle_t sh = sc->sc_sh; 2174 struct sip_txsoft *txs; 2175 struct sip_rxsoft *rxs; 2176 struct sip_desc *sipd; 2177 #if defined(DP83820) 2178 u_int32_t reg; 2179 #endif 2180 int i, error = 0; 2181 2182 /* 2183 * Cancel any pending I/O. 2184 */ 2185 SIP_DECL(stop)(ifp, 0); 2186 2187 /* 2188 * Reset the chip to a known state. 2189 */ 2190 SIP_DECL(reset)(sc); 2191 2192 #if !defined(DP83820) 2193 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2194 /* 2195 * DP83815 manual, page 78: 2196 * 4.4 Recommended Registers Configuration 2197 * For optimum performance of the DP83815, version noted 2198 * as DP83815CVNG (SRR = 203h), the listed register 2199 * modifications must be followed in sequence... 2200 * 2201 * It's not clear if this should be 302h or 203h because that 2202 * chip name is listed as SRR 302h in the description of the 2203 * SRR register. However, my revision 302h DP83815 on the 2204 * Netgear FA311 purchased in 02/2001 needs these settings 2205 * to avoid tons of errors in AcceptPerfectMatch (non- 2206 * IFF_PROMISC) mode. I do not know if other revisions need 2207 * this set or not. [briggs -- 09 March 2001] 2208 * 2209 * Note that only the low-order 12 bits of 0xe4 are documented 2210 * and that this sets reserved bits in that register. 2211 */ 2212 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2213 2214 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2215 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2216 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2217 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2218 2219 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2220 } 2221 #endif /* ! DP83820 */ 2222 2223 /* 2224 * Initialize the transmit descriptor ring. 2225 */ 2226 for (i = 0; i < SIP_NTXDESC; i++) { 2227 sipd = &sc->sc_txdescs[i]; 2228 memset(sipd, 0, sizeof(struct sip_desc)); 2229 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2230 } 2231 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2232 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2233 sc->sc_txfree = SIP_NTXDESC; 2234 sc->sc_txnext = 0; 2235 sc->sc_txwin = 0; 2236 2237 /* 2238 * Initialize the transmit job descriptors. 2239 */ 2240 SIMPLEQ_INIT(&sc->sc_txfreeq); 2241 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2242 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2243 txs = &sc->sc_txsoft[i]; 2244 txs->txs_mbuf = NULL; 2245 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2246 } 2247 2248 /* 2249 * Initialize the receive descriptor and receive job 2250 * descriptor rings. 2251 */ 2252 for (i = 0; i < SIP_NRXDESC; i++) { 2253 rxs = &sc->sc_rxsoft[i]; 2254 if (rxs->rxs_mbuf == NULL) { 2255 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2256 printf("%s: unable to allocate or map rx " 2257 "buffer %d, error = %d\n", 2258 sc->sc_dev.dv_xname, i, error); 2259 /* 2260 * XXX Should attempt to run with fewer receive 2261 * XXX buffers instead of just failing. 2262 */ 2263 SIP_DECL(rxdrain)(sc); 2264 goto out; 2265 } 2266 } else 2267 SIP_INIT_RXDESC(sc, i); 2268 } 2269 sc->sc_rxptr = 0; 2270 #ifdef DP83820 2271 sc->sc_rxdiscard = 0; 2272 SIP_RXCHAIN_RESET(sc); 2273 #endif /* DP83820 */ 2274 2275 /* 2276 * Set the configuration register; it's already initialized 2277 * in sip_attach(). 2278 */ 2279 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2280 2281 /* 2282 * Initialize the prototype TXCFG register. 2283 */ 2284 #if defined(DP83820) 2285 sc->sc_txcfg = TXCFG_MXDMA_512; 2286 sc->sc_rxcfg = RXCFG_MXDMA_512; 2287 #else 2288 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2289 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2290 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & CFG_EDBMASTEN)) { 2291 sc->sc_txcfg = TXCFG_MXDMA_64; 2292 sc->sc_rxcfg = RXCFG_MXDMA_64; 2293 } else { 2294 sc->sc_txcfg = TXCFG_MXDMA_512; 2295 sc->sc_rxcfg = RXCFG_MXDMA_512; 2296 } 2297 #endif /* DP83820 */ 2298 2299 sc->sc_txcfg |= TXCFG_ATP | 2300 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2301 sc->sc_tx_drain_thresh; 2302 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2303 2304 /* 2305 * Initialize the receive drain threshold if we have never 2306 * done so. 2307 */ 2308 if (sc->sc_rx_drain_thresh == 0) { 2309 /* 2310 * XXX This value should be tuned. This is set to the 2311 * maximum of 248 bytes, and we may be able to improve 2312 * performance by decreasing it (although we should never 2313 * set this value lower than 2; 14 bytes are required to 2314 * filter the packet). 2315 */ 2316 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2317 } 2318 2319 /* 2320 * Initialize the prototype RXCFG register. 2321 */ 2322 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2323 #ifndef DP83820 2324 /* 2325 * Accept packets >1518 bytes (including FCS) so we can handle 2326 * 802.1q-tagged frames properly. 2327 */ 2328 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2329 sc->sc_rxcfg |= RXCFG_ALP; 2330 #endif 2331 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2332 2333 #ifdef DP83820 2334 /* 2335 * Initialize the VLAN/IP receive control register. 2336 * We enable checksum computation on all incoming 2337 * packets, and do not reject packets w/ bad checksums. 2338 */ 2339 reg = 0; 2340 if (ifp->if_capenable & 2341 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2342 reg |= VRCR_IPEN; 2343 if (sc->sc_ethercom.ec_nvlans != 0) 2344 reg |= VRCR_VTDEN|VRCR_VTREN; 2345 bus_space_write_4(st, sh, SIP_VRCR, reg); 2346 2347 /* 2348 * Initialize the VLAN/IP transmit control register. 2349 * We enable outgoing checksum computation on a 2350 * per-packet basis. 2351 */ 2352 reg = 0; 2353 if (ifp->if_capenable & 2354 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2355 reg |= VTCR_PPCHK; 2356 if (sc->sc_ethercom.ec_nvlans != 0) 2357 reg |= VTCR_VPPTI; 2358 bus_space_write_4(st, sh, SIP_VTCR, reg); 2359 2360 /* 2361 * If we're using VLANs, initialize the VLAN data register. 2362 * To understand why we bswap the VLAN Ethertype, see section 2363 * 4.2.36 of the DP83820 manual. 2364 */ 2365 if (sc->sc_ethercom.ec_nvlans != 0) 2366 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2367 #endif /* DP83820 */ 2368 2369 /* 2370 * Give the transmit and receive rings to the chip. 2371 */ 2372 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2373 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2374 2375 /* 2376 * Initialize the interrupt mask. 2377 */ 2378 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2379 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2380 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2381 2382 /* Set up the receive filter. */ 2383 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2384 2385 /* 2386 * Set the current media. Do this after initializing the prototype 2387 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2388 * control. 2389 */ 2390 mii_mediachg(&sc->sc_mii); 2391 2392 /* 2393 * Enable interrupts. 2394 */ 2395 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2396 2397 /* 2398 * Start the transmit and receive processes. 2399 */ 2400 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2401 2402 /* 2403 * Start the one second MII clock. 2404 */ 2405 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2406 2407 /* 2408 * ...all done! 2409 */ 2410 ifp->if_flags |= IFF_RUNNING; 2411 ifp->if_flags &= ~IFF_OACTIVE; 2412 2413 out: 2414 if (error) 2415 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2416 return (error); 2417 } 2418 2419 /* 2420 * sip_drain: 2421 * 2422 * Drain the receive queue. 2423 */ 2424 void 2425 SIP_DECL(rxdrain)(struct sip_softc *sc) 2426 { 2427 struct sip_rxsoft *rxs; 2428 int i; 2429 2430 for (i = 0; i < SIP_NRXDESC; i++) { 2431 rxs = &sc->sc_rxsoft[i]; 2432 if (rxs->rxs_mbuf != NULL) { 2433 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2434 m_freem(rxs->rxs_mbuf); 2435 rxs->rxs_mbuf = NULL; 2436 } 2437 } 2438 } 2439 2440 /* 2441 * sip_stop: [ ifnet interface function ] 2442 * 2443 * Stop transmission on the interface. 2444 */ 2445 void 2446 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2447 { 2448 struct sip_softc *sc = ifp->if_softc; 2449 bus_space_tag_t st = sc->sc_st; 2450 bus_space_handle_t sh = sc->sc_sh; 2451 struct sip_txsoft *txs; 2452 u_int32_t cmdsts = 0; /* DEBUG */ 2453 2454 /* 2455 * Stop the one second clock. 2456 */ 2457 callout_stop(&sc->sc_tick_ch); 2458 2459 /* Down the MII. */ 2460 mii_down(&sc->sc_mii); 2461 2462 /* 2463 * Disable interrupts. 2464 */ 2465 bus_space_write_4(st, sh, SIP_IER, 0); 2466 2467 /* 2468 * Stop receiver and transmitter. 2469 */ 2470 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2471 2472 /* 2473 * Release any queued transmit buffers. 2474 */ 2475 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2476 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2477 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2478 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2479 CMDSTS_INTR) == 0) 2480 printf("%s: sip_stop: last descriptor does not " 2481 "have INTR bit set\n", sc->sc_dev.dv_xname); 2482 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2483 #ifdef DIAGNOSTIC 2484 if (txs->txs_mbuf == NULL) { 2485 printf("%s: dirty txsoft with no mbuf chain\n", 2486 sc->sc_dev.dv_xname); 2487 panic("sip_stop"); 2488 } 2489 #endif 2490 cmdsts |= /* DEBUG */ 2491 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2492 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2493 m_freem(txs->txs_mbuf); 2494 txs->txs_mbuf = NULL; 2495 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2496 } 2497 2498 if (disable) 2499 SIP_DECL(rxdrain)(sc); 2500 2501 /* 2502 * Mark the interface down and cancel the watchdog timer. 2503 */ 2504 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2505 ifp->if_timer = 0; 2506 2507 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2508 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2509 printf("%s: sip_stop: no INTR bits set in dirty tx " 2510 "descriptors\n", sc->sc_dev.dv_xname); 2511 } 2512 2513 /* 2514 * sip_read_eeprom: 2515 * 2516 * Read data from the serial EEPROM. 2517 */ 2518 void 2519 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2520 u_int16_t *data) 2521 { 2522 bus_space_tag_t st = sc->sc_st; 2523 bus_space_handle_t sh = sc->sc_sh; 2524 u_int16_t reg; 2525 int i, x; 2526 2527 for (i = 0; i < wordcnt; i++) { 2528 /* Send CHIP SELECT. */ 2529 reg = EROMAR_EECS; 2530 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2531 2532 /* Shift in the READ opcode. */ 2533 for (x = 3; x > 0; x--) { 2534 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2535 reg |= EROMAR_EEDI; 2536 else 2537 reg &= ~EROMAR_EEDI; 2538 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2539 bus_space_write_4(st, sh, SIP_EROMAR, 2540 reg | EROMAR_EESK); 2541 delay(4); 2542 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2543 delay(4); 2544 } 2545 2546 /* Shift in address. */ 2547 for (x = 6; x > 0; x--) { 2548 if ((word + i) & (1 << (x - 1))) 2549 reg |= EROMAR_EEDI; 2550 else 2551 reg &= ~EROMAR_EEDI; 2552 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2553 bus_space_write_4(st, sh, SIP_EROMAR, 2554 reg | EROMAR_EESK); 2555 delay(4); 2556 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2557 delay(4); 2558 } 2559 2560 /* Shift out data. */ 2561 reg = EROMAR_EECS; 2562 data[i] = 0; 2563 for (x = 16; x > 0; x--) { 2564 bus_space_write_4(st, sh, SIP_EROMAR, 2565 reg | EROMAR_EESK); 2566 delay(4); 2567 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2568 data[i] |= (1 << (x - 1)); 2569 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2570 delay(4); 2571 } 2572 2573 /* Clear CHIP SELECT. */ 2574 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2575 delay(4); 2576 } 2577 } 2578 2579 /* 2580 * sip_add_rxbuf: 2581 * 2582 * Add a receive buffer to the indicated descriptor. 2583 */ 2584 int 2585 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2586 { 2587 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2588 struct mbuf *m; 2589 int error; 2590 2591 MGETHDR(m, M_DONTWAIT, MT_DATA); 2592 if (m == NULL) 2593 return (ENOBUFS); 2594 2595 MCLGET(m, M_DONTWAIT); 2596 if ((m->m_flags & M_EXT) == 0) { 2597 m_freem(m); 2598 return (ENOBUFS); 2599 } 2600 2601 #if defined(DP83820) 2602 m->m_len = SIP_RXBUF_LEN; 2603 #endif /* DP83820 */ 2604 2605 if (rxs->rxs_mbuf != NULL) 2606 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2607 2608 rxs->rxs_mbuf = m; 2609 2610 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2611 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2612 BUS_DMA_READ|BUS_DMA_NOWAIT); 2613 if (error) { 2614 printf("%s: can't load rx DMA map %d, error = %d\n", 2615 sc->sc_dev.dv_xname, idx, error); 2616 panic("sip_add_rxbuf"); /* XXX */ 2617 } 2618 2619 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2620 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2621 2622 SIP_INIT_RXDESC(sc, idx); 2623 2624 return (0); 2625 } 2626 2627 #if !defined(DP83820) 2628 /* 2629 * sip_sis900_set_filter: 2630 * 2631 * Set up the receive filter. 2632 */ 2633 void 2634 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2635 { 2636 bus_space_tag_t st = sc->sc_st; 2637 bus_space_handle_t sh = sc->sc_sh; 2638 struct ethercom *ec = &sc->sc_ethercom; 2639 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2640 struct ether_multi *enm; 2641 u_int8_t *cp; 2642 struct ether_multistep step; 2643 u_int32_t crc, mchash[16]; 2644 2645 /* 2646 * Initialize the prototype RFCR. 2647 */ 2648 sc->sc_rfcr = RFCR_RFEN; 2649 if (ifp->if_flags & IFF_BROADCAST) 2650 sc->sc_rfcr |= RFCR_AAB; 2651 if (ifp->if_flags & IFF_PROMISC) { 2652 sc->sc_rfcr |= RFCR_AAP; 2653 goto allmulti; 2654 } 2655 2656 /* 2657 * Set up the multicast address filter by passing all multicast 2658 * addresses through a CRC generator, and then using the high-order 2659 * 6 bits as an index into the 128 bit multicast hash table (only 2660 * the lower 16 bits of each 32 bit multicast hash register are 2661 * valid). The high order bits select the register, while the 2662 * rest of the bits select the bit within the register. 2663 */ 2664 2665 memset(mchash, 0, sizeof(mchash)); 2666 2667 ETHER_FIRST_MULTI(step, ec, enm); 2668 while (enm != NULL) { 2669 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2670 /* 2671 * We must listen to a range of multicast addresses. 2672 * For now, just accept all multicasts, rather than 2673 * trying to set only those filter bits needed to match 2674 * the range. (At this time, the only use of address 2675 * ranges is for IP multicast routing, for which the 2676 * range is big enough to require all bits set.) 2677 */ 2678 goto allmulti; 2679 } 2680 2681 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2682 2683 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2684 SIP_SIS900_REV(sc, SIS_REV_960) || 2685 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2686 /* Just want the 8 most significant bits. */ 2687 crc >>= 24; 2688 } else { 2689 /* Just want the 7 most significant bits. */ 2690 crc >>= 25; 2691 } 2692 2693 /* Set the corresponding bit in the hash table. */ 2694 mchash[crc >> 4] |= 1 << (crc & 0xf); 2695 2696 ETHER_NEXT_MULTI(step, enm); 2697 } 2698 2699 ifp->if_flags &= ~IFF_ALLMULTI; 2700 goto setit; 2701 2702 allmulti: 2703 ifp->if_flags |= IFF_ALLMULTI; 2704 sc->sc_rfcr |= RFCR_AAM; 2705 2706 setit: 2707 #define FILTER_EMIT(addr, data) \ 2708 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2709 delay(1); \ 2710 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2711 delay(1) 2712 2713 /* 2714 * Disable receive filter, and program the node address. 2715 */ 2716 cp = LLADDR(ifp->if_sadl); 2717 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2718 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2719 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2720 2721 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2722 /* 2723 * Program the multicast hash table. 2724 */ 2725 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2726 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2727 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2728 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2729 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2730 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2731 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2732 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2733 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2734 SIP_SIS900_REV(sc, SIS_REV_960) || 2735 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2736 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2737 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2738 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2739 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2740 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2741 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2742 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2743 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2744 } 2745 } 2746 #undef FILTER_EMIT 2747 2748 /* 2749 * Re-enable the receiver filter. 2750 */ 2751 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2752 } 2753 #endif /* ! DP83820 */ 2754 2755 /* 2756 * sip_dp83815_set_filter: 2757 * 2758 * Set up the receive filter. 2759 */ 2760 void 2761 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2762 { 2763 bus_space_tag_t st = sc->sc_st; 2764 bus_space_handle_t sh = sc->sc_sh; 2765 struct ethercom *ec = &sc->sc_ethercom; 2766 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2767 struct ether_multi *enm; 2768 u_int8_t *cp; 2769 struct ether_multistep step; 2770 u_int32_t crc, hash, slot, bit; 2771 #ifdef DP83820 2772 #define MCHASH_NWORDS 128 2773 #else 2774 #define MCHASH_NWORDS 32 2775 #endif /* DP83820 */ 2776 u_int16_t mchash[MCHASH_NWORDS]; 2777 int i; 2778 2779 /* 2780 * Initialize the prototype RFCR. 2781 * Enable the receive filter, and accept on 2782 * Perfect (destination address) Match 2783 * If IFF_BROADCAST, also accept all broadcast packets. 2784 * If IFF_PROMISC, accept all unicast packets (and later, set 2785 * IFF_ALLMULTI and accept all multicast, too). 2786 */ 2787 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2788 if (ifp->if_flags & IFF_BROADCAST) 2789 sc->sc_rfcr |= RFCR_AAB; 2790 if (ifp->if_flags & IFF_PROMISC) { 2791 sc->sc_rfcr |= RFCR_AAP; 2792 goto allmulti; 2793 } 2794 2795 #ifdef DP83820 2796 /* 2797 * Set up the DP83820 multicast address filter by passing all multicast 2798 * addresses through a CRC generator, and then using the high-order 2799 * 11 bits as an index into the 2048 bit multicast hash table. The 2800 * high-order 7 bits select the slot, while the low-order 4 bits 2801 * select the bit within the slot. Note that only the low 16-bits 2802 * of each filter word are used, and there are 128 filter words. 2803 */ 2804 #else 2805 /* 2806 * Set up the DP83815 multicast address filter by passing all multicast 2807 * addresses through a CRC generator, and then using the high-order 2808 * 9 bits as an index into the 512 bit multicast hash table. The 2809 * high-order 5 bits select the slot, while the low-order 4 bits 2810 * select the bit within the slot. Note that only the low 16-bits 2811 * of each filter word are used, and there are 32 filter words. 2812 */ 2813 #endif /* DP83820 */ 2814 2815 memset(mchash, 0, sizeof(mchash)); 2816 2817 ifp->if_flags &= ~IFF_ALLMULTI; 2818 ETHER_FIRST_MULTI(step, ec, enm); 2819 if (enm == NULL) 2820 goto setit; 2821 while (enm != NULL) { 2822 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2823 /* 2824 * We must listen to a range of multicast addresses. 2825 * For now, just accept all multicasts, rather than 2826 * trying to set only those filter bits needed to match 2827 * the range. (At this time, the only use of address 2828 * ranges is for IP multicast routing, for which the 2829 * range is big enough to require all bits set.) 2830 */ 2831 goto allmulti; 2832 } 2833 2834 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2835 2836 #ifdef DP83820 2837 /* Just want the 11 most significant bits. */ 2838 hash = crc >> 21; 2839 #else 2840 /* Just want the 9 most significant bits. */ 2841 hash = crc >> 23; 2842 #endif /* DP83820 */ 2843 2844 slot = hash >> 4; 2845 bit = hash & 0xf; 2846 2847 /* Set the corresponding bit in the hash table. */ 2848 mchash[slot] |= 1 << bit; 2849 2850 ETHER_NEXT_MULTI(step, enm); 2851 } 2852 sc->sc_rfcr |= RFCR_MHEN; 2853 goto setit; 2854 2855 allmulti: 2856 ifp->if_flags |= IFF_ALLMULTI; 2857 sc->sc_rfcr |= RFCR_AAM; 2858 2859 setit: 2860 #define FILTER_EMIT(addr, data) \ 2861 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2862 delay(1); \ 2863 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2864 delay(1) 2865 2866 /* 2867 * Disable receive filter, and program the node address. 2868 */ 2869 cp = LLADDR(ifp->if_sadl); 2870 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 2871 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 2872 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 2873 2874 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2875 /* 2876 * Program the multicast hash table. 2877 */ 2878 for (i = 0; i < MCHASH_NWORDS; i++) { 2879 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 2880 mchash[i]); 2881 } 2882 } 2883 #undef FILTER_EMIT 2884 #undef MCHASH_NWORDS 2885 2886 /* 2887 * Re-enable the receiver filter. 2888 */ 2889 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2890 } 2891 2892 #if defined(DP83820) 2893 /* 2894 * sip_dp83820_mii_readreg: [mii interface function] 2895 * 2896 * Read a PHY register on the MII of the DP83820. 2897 */ 2898 int 2899 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 2900 { 2901 struct sip_softc *sc = (void *) self; 2902 2903 if (sc->sc_cfg & CFG_TBI_EN) { 2904 bus_addr_t tbireg; 2905 int rv; 2906 2907 if (phy != 0) 2908 return (0); 2909 2910 switch (reg) { 2911 case MII_BMCR: tbireg = SIP_TBICR; break; 2912 case MII_BMSR: tbireg = SIP_TBISR; break; 2913 case MII_ANAR: tbireg = SIP_TANAR; break; 2914 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 2915 case MII_ANER: tbireg = SIP_TANER; break; 2916 case MII_EXTSR: 2917 /* 2918 * Don't even bother reading the TESR register. 2919 * The manual documents that the device has 2920 * 1000baseX full/half capability, but the 2921 * register itself seems read back 0 on some 2922 * boards. Just hard-code the result. 2923 */ 2924 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 2925 2926 default: 2927 return (0); 2928 } 2929 2930 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 2931 if (tbireg == SIP_TBISR) { 2932 /* LINK and ACOMP are switched! */ 2933 int val = rv; 2934 2935 rv = 0; 2936 if (val & TBISR_MR_LINK_STATUS) 2937 rv |= BMSR_LINK; 2938 if (val & TBISR_MR_AN_COMPLETE) 2939 rv |= BMSR_ACOMP; 2940 2941 /* 2942 * The manual claims this register reads back 0 2943 * on hard and soft reset. But we want to let 2944 * the gentbi driver know that we support auto- 2945 * negotiation, so hard-code this bit in the 2946 * result. 2947 */ 2948 rv |= BMSR_ANEG | BMSR_EXTSTAT; 2949 } 2950 2951 return (rv); 2952 } 2953 2954 return (mii_bitbang_readreg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2955 phy, reg)); 2956 } 2957 2958 /* 2959 * sip_dp83820_mii_writereg: [mii interface function] 2960 * 2961 * Write a PHY register on the MII of the DP83820. 2962 */ 2963 void 2964 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 2965 { 2966 struct sip_softc *sc = (void *) self; 2967 2968 if (sc->sc_cfg & CFG_TBI_EN) { 2969 bus_addr_t tbireg; 2970 2971 if (phy != 0) 2972 return; 2973 2974 switch (reg) { 2975 case MII_BMCR: tbireg = SIP_TBICR; break; 2976 case MII_ANAR: tbireg = SIP_TANAR; break; 2977 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 2978 default: 2979 return; 2980 } 2981 2982 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 2983 return; 2984 } 2985 2986 mii_bitbang_writereg(self, &SIP_DECL(dp83820_mii_bitbang_ops), 2987 phy, reg, val); 2988 } 2989 2990 /* 2991 * sip_dp83815_mii_statchg: [mii interface function] 2992 * 2993 * Callback from MII layer when media changes. 2994 */ 2995 void 2996 SIP_DECL(dp83820_mii_statchg)(struct device *self) 2997 { 2998 struct sip_softc *sc = (struct sip_softc *) self; 2999 u_int32_t cfg; 3000 3001 /* 3002 * Update TXCFG for full-duplex operation. 3003 */ 3004 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3005 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3006 else 3007 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3008 3009 /* 3010 * Update RXCFG for full-duplex or loopback. 3011 */ 3012 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3013 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3014 sc->sc_rxcfg |= RXCFG_ATX; 3015 else 3016 sc->sc_rxcfg &= ~RXCFG_ATX; 3017 3018 /* 3019 * Update CFG for MII/GMII. 3020 */ 3021 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3022 cfg = sc->sc_cfg | CFG_MODE_1000; 3023 else 3024 cfg = sc->sc_cfg; 3025 3026 /* 3027 * XXX 802.3x flow control. 3028 */ 3029 3030 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3031 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3032 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3033 } 3034 3035 /* 3036 * sip_dp83820_mii_bitbang_read: [mii bit-bang interface function] 3037 * 3038 * Read the MII serial port for the MII bit-bang module. 3039 */ 3040 u_int32_t 3041 SIP_DECL(dp83820_mii_bitbang_read)(struct device *self) 3042 { 3043 struct sip_softc *sc = (void *) self; 3044 3045 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3046 } 3047 3048 /* 3049 * sip_dp83820_mii_bitbang_write: [mii big-bang interface function] 3050 * 3051 * Write the MII serial port for the MII bit-bang module. 3052 */ 3053 void 3054 SIP_DECL(dp83820_mii_bitbang_write)(struct device *self, u_int32_t val) 3055 { 3056 struct sip_softc *sc = (void *) self; 3057 3058 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3059 } 3060 #else /* ! DP83820 */ 3061 3062 /* SiS MII functions */ 3063 3064 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3065 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3066 3067 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3068 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3069 3070 /* 3071 * Sync the PHYs by setting data bit and strobing the clock 32 times. 3072 */ 3073 static void 3074 SIP_DECL(sis900_mii_sync)(struct sip_softc *sc) 3075 { 3076 register int i; 3077 3078 SIS_SET_EROMAR(sc, EROMAR_MDDIR | EROMAR_MDIO); 3079 3080 for (i = 0; i < 32; i++) { 3081 SIS_SET_EROMAR(sc, EROMAR_MDC); 3082 DELAY(1); 3083 SIS_CLR_EROMAR(sc, EROMAR_MDC); 3084 DELAY(1); 3085 } 3086 } 3087 3088 /* 3089 * Clock a series of bits through the MII. 3090 */ 3091 static void 3092 SIP_DECL(sis900_mii_send)(struct sip_softc *sc, u_int32_t bits, int cnt) 3093 { 3094 int i; 3095 3096 SIS_CLR_EROMAR(sc, EROMAR_MDC); 3097 3098 /* Send first cnt bits of 'bits' */ 3099 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 3100 if (bits & i) 3101 SIS_SET_EROMAR(sc, EROMAR_MDIO); 3102 else 3103 SIS_CLR_EROMAR(sc, EROMAR_MDIO); 3104 DELAY(1); 3105 SIS_CLR_EROMAR(sc, EROMAR_MDC); 3106 DELAY(1); 3107 SIS_SET_EROMAR(sc, EROMAR_MDC); 3108 } 3109 } 3110 3111 /* 3112 * sip_sis900_mii_readreg: [mii interface function] 3113 * 3114 * Read a PHY register on the MII. 3115 */ 3116 int 3117 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 3118 { 3119 struct sip_softc *sc = (struct sip_softc *) self; 3120 u_int32_t ack, val = 0; 3121 int s, i; 3122 3123 /* 3124 * The SiS 900 has only an internal PHY on the MII. Only allow 3125 * MII address 0. 3126 */ 3127 if (sc->sc_model->sip_product != PCI_PRODUCT_SIS_900 || 3128 sc->sc_rev < SIS_REV_635) { 3129 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3130 return (0); 3131 3132 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3133 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3134 ENPHY_RWCMD | ENPHY_ACCESS); 3135 do { 3136 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3137 } while (val & ENPHY_ACCESS); 3138 return ((val & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3139 } 3140 3141 s = splnet(); 3142 3143 /* Use mdio access from FreeBSD (apparently inspired by Linux) */ 3144 SIS_SET_EROMAR(sc, EROMAR_MDDIR); 3145 3146 SIP_DECL(sis900_mii_sync)(sc); 3147 3148 /* 3149 * Send command/address info. 3150 */ 3151 SIP_DECL(sis900_mii_send)(sc, SIS_MII_STARTDELIM, 2); 3152 SIP_DECL(sis900_mii_send)(sc, SIS_MII_READOP, 2); 3153 SIP_DECL(sis900_mii_send)(sc, phy, 5); 3154 SIP_DECL(sis900_mii_send)(sc, reg, 5); 3155 3156 /* Idle bit */ 3157 SIS_CLR_EROMAR(sc, EROMAR_MDC | EROMAR_MDIO); 3158 DELAY(1); 3159 SIS_SET_EROMAR(sc, EROMAR_MDC); 3160 DELAY(1); 3161 3162 /* Turn off xmit. */ 3163 SIS_CLR_EROMAR(sc, EROMAR_MDDIR); 3164 3165 /* Check for ack */ 3166 SIS_CLR_EROMAR(sc, EROMAR_MDC); 3167 DELAY(1); 3168 3169 ack = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_MDIO; 3170 3171 SIS_SET_EROMAR(sc, EROMAR_MDC); 3172 DELAY(1); 3173 3174 /* 3175 * Now try reading data bits. If the ack failed, we still 3176 * need to clock through 16 cycles to keep the PHY(s) in sync. 3177 */ 3178 if (ack) 3179 for (i = 0; i < 16; i++) { 3180 SIS_CLR_EROMAR(sc, EROMAR_MDC); 3181 DELAY(1); 3182 SIS_SET_EROMAR(sc, EROMAR_MDC); 3183 DELAY(1); 3184 } 3185 else 3186 for (i = 0x8000; i; i >>= 1) { 3187 SIS_CLR_EROMAR(sc, EROMAR_MDC); 3188 DELAY(1); 3189 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_MDIO) 3190 val |= i; 3191 DELAY(1); 3192 SIS_SET_EROMAR(sc, EROMAR_MDC); 3193 DELAY(1); 3194 } 3195 3196 SIS_CLR_EROMAR(sc, EROMAR_MDC); 3197 DELAY(1); 3198 SIS_SET_EROMAR(sc, EROMAR_MDC); 3199 DELAY(1); 3200 3201 splx(s); 3202 3203 return(val); 3204 } 3205 3206 /* 3207 * sip_sis900_mii_writereg: [mii interface function] 3208 * 3209 * Write a PHY register on the MII. 3210 */ 3211 void 3212 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 3213 { 3214 struct sip_softc *sc = (struct sip_softc *) self; 3215 u_int32_t enphy; 3216 int s; 3217 3218 /* 3219 * The SiS 900 has only an internal PHY on the MII. Only allow 3220 * MII address 0. 3221 */ 3222 if (sc->sc_model->sip_product != PCI_PRODUCT_SIS_900 || 3223 sc->sc_rev < SIS_REV_635) { 3224 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3225 return; 3226 3227 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3228 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3229 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3230 do { 3231 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3232 } while (enphy & ENPHY_ACCESS); 3233 return; 3234 } 3235 3236 s = splnet(); 3237 3238 /* 3239 * Turn on data output. 3240 */ 3241 SIS_SET_EROMAR(sc, EROMAR_MDDIR); 3242 3243 SIP_DECL(sis900_mii_sync)(sc); 3244 3245 SIP_DECL(sis900_mii_send)(sc, SIS_MII_STARTDELIM, 2); 3246 SIP_DECL(sis900_mii_send)(sc, SIS_MII_WRITEOP, 2); 3247 SIP_DECL(sis900_mii_send)(sc, phy, 5); 3248 SIP_DECL(sis900_mii_send)(sc, reg, 5); 3249 SIP_DECL(sis900_mii_send)(sc, SIS_MII_TURNAROUND, 2); 3250 SIP_DECL(sis900_mii_send)(sc, val, 16); 3251 3252 /* Idle bit. */ 3253 SIS_SET_EROMAR(sc, EROMAR_MDC); 3254 DELAY(1); 3255 SIS_CLR_EROMAR(sc, EROMAR_MDC); 3256 DELAY(1); 3257 3258 /* 3259 * Turn off xmit. 3260 */ 3261 SIS_CLR_EROMAR(sc, EROMAR_MDDIR); 3262 3263 splx(s); 3264 } 3265 3266 /* 3267 * sip_sis900_mii_statchg: [mii interface function] 3268 * 3269 * Callback from MII layer when media changes. 3270 */ 3271 void 3272 SIP_DECL(sis900_mii_statchg)(struct device *self) 3273 { 3274 struct sip_softc *sc = (struct sip_softc *) self; 3275 u_int32_t flowctl; 3276 3277 /* 3278 * Update TXCFG for full-duplex operation. 3279 */ 3280 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3281 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3282 else 3283 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3284 3285 /* 3286 * Update RXCFG for full-duplex or loopback. 3287 */ 3288 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3289 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3290 sc->sc_rxcfg |= RXCFG_ATX; 3291 else 3292 sc->sc_rxcfg &= ~RXCFG_ATX; 3293 3294 /* 3295 * Update IMR for use of 802.3x flow control. 3296 */ 3297 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 3298 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3299 flowctl = FLOWCTL_FLOWEN; 3300 } else { 3301 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3302 flowctl = 0; 3303 } 3304 3305 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3306 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3307 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3308 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3309 } 3310 3311 /* 3312 * sip_dp83815_mii_readreg: [mii interface function] 3313 * 3314 * Read a PHY register on the MII. 3315 */ 3316 int 3317 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 3318 { 3319 struct sip_softc *sc = (struct sip_softc *) self; 3320 u_int32_t val; 3321 3322 /* 3323 * The DP83815 only has an internal PHY. Only allow 3324 * MII address 0. 3325 */ 3326 if (phy != 0) 3327 return (0); 3328 3329 /* 3330 * Apparently, after a reset, the DP83815 can take a while 3331 * to respond. During this recovery period, the BMSR returns 3332 * a value of 0. Catch this -- it's not supposed to happen 3333 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3334 * PHY to come back to life. 3335 * 3336 * This works out because the BMSR is the first register 3337 * read during the PHY probe process. 3338 */ 3339 do { 3340 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3341 } while (reg == MII_BMSR && val == 0); 3342 3343 return (val & 0xffff); 3344 } 3345 3346 /* 3347 * sip_dp83815_mii_writereg: [mii interface function] 3348 * 3349 * Write a PHY register to the MII. 3350 */ 3351 void 3352 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3353 { 3354 struct sip_softc *sc = (struct sip_softc *) self; 3355 3356 /* 3357 * The DP83815 only has an internal PHY. Only allow 3358 * MII address 0. 3359 */ 3360 if (phy != 0) 3361 return; 3362 3363 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3364 } 3365 3366 /* 3367 * sip_dp83815_mii_statchg: [mii interface function] 3368 * 3369 * Callback from MII layer when media changes. 3370 */ 3371 void 3372 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3373 { 3374 struct sip_softc *sc = (struct sip_softc *) self; 3375 3376 /* 3377 * Update TXCFG for full-duplex operation. 3378 */ 3379 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3380 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3381 else 3382 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3383 3384 /* 3385 * Update RXCFG for full-duplex or loopback. 3386 */ 3387 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3388 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3389 sc->sc_rxcfg |= RXCFG_ATX; 3390 else 3391 sc->sc_rxcfg &= ~RXCFG_ATX; 3392 3393 /* 3394 * XXX 802.3x flow control. 3395 */ 3396 3397 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3398 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3399 3400 /* 3401 * Some DP83815s experience problems when used with short 3402 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3403 * sequence adjusts the DSP's signal attenuation to fix the 3404 * problem. 3405 */ 3406 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3407 uint32_t reg; 3408 3409 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3410 3411 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3412 reg &= 0x0fff; 3413 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3414 delay(100); 3415 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3416 reg &= 0x00ff; 3417 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3418 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3419 0x00e8); 3420 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3421 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3422 reg | 0x20); 3423 } 3424 3425 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3426 } 3427 } 3428 #endif /* DP83820 */ 3429 3430 #if defined(DP83820) 3431 void 3432 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3433 const struct pci_attach_args *pa, u_int8_t *enaddr) 3434 { 3435 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3436 u_int8_t cksum, *e, match; 3437 int i; 3438 3439 /* 3440 * EEPROM data format for the DP83820 can be found in 3441 * the DP83820 manual, section 4.2.4. 3442 */ 3443 3444 SIP_DECL(read_eeprom)(sc, 0, 3445 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3446 3447 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3448 match = ~(match - 1); 3449 3450 cksum = 0x55; 3451 e = (u_int8_t *) eeprom_data; 3452 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3453 cksum += *e++; 3454 3455 if (cksum != match) 3456 printf("%s: Checksum (%x) mismatch (%x)", 3457 sc->sc_dev.dv_xname, cksum, match); 3458 3459 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3460 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3461 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3462 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3463 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3464 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3465 } 3466 #else /* ! DP83820 */ 3467 static void 3468 SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc) 3469 { 3470 int i; 3471 3472 /* 3473 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3474 * a reason, but I don't know it. 3475 */ 3476 for (i = 0; i < 10; i++) 3477 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3478 } 3479 3480 void 3481 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3482 const struct pci_attach_args *pa, u_int8_t *enaddr) 3483 { 3484 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3485 3486 switch (sc->sc_rev) { 3487 case SIS_REV_630S: 3488 case SIS_REV_630E: 3489 case SIS_REV_630EA1: 3490 case SIS_REV_630ET: 3491 case SIS_REV_635: 3492 /* 3493 * The MAC address for the on-board Ethernet of 3494 * the SiS 630 chipset is in the NVRAM. Kick 3495 * the chip into re-loading it from NVRAM, and 3496 * read the MAC address out of the filter registers. 3497 */ 3498 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3499 3500 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3501 RFCR_RFADDR_NODE0); 3502 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3503 0xffff; 3504 3505 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3506 RFCR_RFADDR_NODE2); 3507 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3508 0xffff; 3509 3510 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3511 RFCR_RFADDR_NODE4); 3512 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3513 0xffff; 3514 break; 3515 3516 case SIS_REV_960: 3517 { 3518 int waittime, i; 3519 3520 /* Allow to read EEPROM from LAN. It is shared 3521 * between a 1394 controller and the NIC and each 3522 * time we access it, we need to set SIS_EECMD_REQ. 3523 */ 3524 SIS_SET_EROMAR(sc, EROMAR_REQ); 3525 3526 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3527 /* Force EEPROM to idle state. */ 3528 3529 /* 3530 * XXX-cube This is ugly. I'll look for docs about it. 3531 */ 3532 SIS_SET_EROMAR(sc, EROMAR_EECS); 3533 SIP_DECL(sis900_eeprom_delay)(sc); 3534 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3535 SIS_SET_EROMAR(sc, EROMAR_EESK); 3536 SIP_DECL(sis900_eeprom_delay)(sc); 3537 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3538 SIP_DECL(sis900_eeprom_delay)(sc); 3539 } 3540 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3541 SIP_DECL(sis900_eeprom_delay)(sc); 3542 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3543 3544 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3545 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3546 sizeof(myea) / sizeof(myea[0]), myea); 3547 break; 3548 } 3549 DELAY(1); 3550 } 3551 3552 /* 3553 * Set SIS_EECTL_CLK to high, so a other master 3554 * can operate on the i2c bus. 3555 */ 3556 SIS_SET_EROMAR(sc, EROMAR_EESK); 3557 3558 /* Refuse EEPROM access by LAN */ 3559 SIS_SET_EROMAR(sc, EROMAR_DONE); 3560 } break; 3561 3562 default: 3563 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3564 sizeof(myea) / sizeof(myea[0]), myea); 3565 } 3566 3567 enaddr[0] = myea[0] & 0xff; 3568 enaddr[1] = myea[0] >> 8; 3569 enaddr[2] = myea[1] & 0xff; 3570 enaddr[3] = myea[1] >> 8; 3571 enaddr[4] = myea[2] & 0xff; 3572 enaddr[5] = myea[2] >> 8; 3573 } 3574 3575 /* Table and macro to bit-reverse an octet. */ 3576 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3577 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3578 3579 void 3580 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3581 const struct pci_attach_args *pa, u_int8_t *enaddr) 3582 { 3583 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3584 u_int8_t cksum, *e, match; 3585 int i; 3586 3587 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3588 sizeof(eeprom_data[0]), eeprom_data); 3589 3590 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3591 match = ~(match - 1); 3592 3593 cksum = 0x55; 3594 e = (u_int8_t *) eeprom_data; 3595 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3596 cksum += *e++; 3597 } 3598 if (cksum != match) { 3599 printf("%s: Checksum (%x) mismatch (%x)", 3600 sc->sc_dev.dv_xname, cksum, match); 3601 } 3602 3603 /* 3604 * Unrolled because it makes slightly more sense this way. 3605 * The DP83815 stores the MAC address in bit 0 of word 6 3606 * through bit 15 of word 8. 3607 */ 3608 ea = &eeprom_data[6]; 3609 enaddr[0] = ((*ea & 0x1) << 7); 3610 ea++; 3611 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3612 enaddr[1] = ((*ea & 0x1FE) >> 1); 3613 enaddr[2] = ((*ea & 0x1) << 7); 3614 ea++; 3615 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3616 enaddr[3] = ((*ea & 0x1FE) >> 1); 3617 enaddr[4] = ((*ea & 0x1) << 7); 3618 ea++; 3619 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3620 enaddr[5] = ((*ea & 0x1FE) >> 1); 3621 3622 /* 3623 * In case that's not weird enough, we also need to reverse 3624 * the bits in each byte. This all actually makes more sense 3625 * if you think about the EEPROM storage as an array of bits 3626 * being shifted into bytes, but that's not how we're looking 3627 * at it here... 3628 */ 3629 for (i = 0; i < 6 ;i++) 3630 enaddr[i] = bbr(enaddr[i]); 3631 } 3632 #endif /* DP83820 */ 3633 3634 /* 3635 * sip_mediastatus: [ifmedia interface function] 3636 * 3637 * Get the current interface media status. 3638 */ 3639 void 3640 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3641 { 3642 struct sip_softc *sc = ifp->if_softc; 3643 3644 mii_pollstat(&sc->sc_mii); 3645 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3646 ifmr->ifm_active = sc->sc_mii.mii_media_active; 3647 } 3648 3649 /* 3650 * sip_mediachange: [ifmedia interface function] 3651 * 3652 * Set hardware to newly-selected media. 3653 */ 3654 int 3655 SIP_DECL(mediachange)(struct ifnet *ifp) 3656 { 3657 struct sip_softc *sc = ifp->if_softc; 3658 3659 if (ifp->if_flags & IFF_UP) 3660 mii_mediachg(&sc->sc_mii); 3661 return (0); 3662 } 3663
Indexes created Tue Sep 30 11:09:46 GMT 2025