if_sip.c revision 1.86
1 /* $NetBSD: if_sip.c,v 1.86 2003/12/05 22:34:44 cube Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.86 2003/12/05 22:34:44 cube Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <machine/bus.h> 116 #include <machine/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/mii_bitbang.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/pci/if_sipreg.h> 128 129 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 130 #define SIP_DECL(x) __CONCAT(gsip_,x) 131 #else /* SiS900 and DP83815 */ 132 #define SIP_DECL(x) __CONCAT(sip_,x) 133 #endif 134 135 #define SIP_STR(x) __STRING(SIP_DECL(x)) 136 137 /* 138 * Transmit descriptor list size. This is arbitrary, but allocate 139 * enough descriptors for 128 pending transmissions, and 8 segments 140 * per packet. This MUST work out to a power of 2. 141 */ 142 #define SIP_NTXSEGS 16 143 #define SIP_NTXSEGS_ALLOC 8 144 145 #define SIP_TXQUEUELEN 256 146 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 147 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 148 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 149 150 #if defined(DP83820) 151 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 152 #else 153 #define TX_DMAMAP_SIZE MCLBYTES 154 #endif 155 156 /* 157 * Receive descriptor list size. We have one Rx buffer per incoming 158 * packet, so this logic is a little simpler. 159 * 160 * Actually, on the DP83820, we allow the packet to consume more than 161 * one buffer, in order to support jumbo Ethernet frames. In that 162 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 163 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 164 * so we'd better be quick about handling receive interrupts. 165 */ 166 #if defined(DP83820) 167 #define SIP_NRXDESC 256 168 #else 169 #define SIP_NRXDESC 128 170 #endif /* DP83820 */ 171 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 172 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 173 174 /* 175 * Control structures are DMA'd to the SiS900 chip. We allocate them in 176 * a single clump that maps to a single DMA segment to make several things 177 * easier. 178 */ 179 struct sip_control_data { 180 /* 181 * The transmit descriptors. 182 */ 183 struct sip_desc scd_txdescs[SIP_NTXDESC]; 184 185 /* 186 * The receive descriptors. 187 */ 188 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 189 }; 190 191 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 192 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 193 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 194 195 /* 196 * Software state for transmit jobs. 197 */ 198 struct sip_txsoft { 199 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 200 bus_dmamap_t txs_dmamap; /* our DMA map */ 201 int txs_firstdesc; /* first descriptor in packet */ 202 int txs_lastdesc; /* last descriptor in packet */ 203 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 204 }; 205 206 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 207 208 /* 209 * Software state for receive jobs. 210 */ 211 struct sip_rxsoft { 212 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 213 bus_dmamap_t rxs_dmamap; /* our DMA map */ 214 }; 215 216 /* 217 * Software state per device. 218 */ 219 struct sip_softc { 220 struct device sc_dev; /* generic device information */ 221 bus_space_tag_t sc_st; /* bus space tag */ 222 bus_space_handle_t sc_sh; /* bus space handle */ 223 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 224 struct ethercom sc_ethercom; /* ethernet common data */ 225 void *sc_sdhook; /* shutdown hook */ 226 227 const struct sip_product *sc_model; /* which model are we? */ 228 int sc_rev; /* chip revision */ 229 230 void *sc_ih; /* interrupt cookie */ 231 232 struct mii_data sc_mii; /* MII/media information */ 233 234 struct callout sc_tick_ch; /* tick callout */ 235 236 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 237 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 238 239 /* 240 * Software state for transmit and receive descriptors. 241 */ 242 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 243 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 244 245 /* 246 * Control data structures. 247 */ 248 struct sip_control_data *sc_control_data; 249 #define sc_txdescs sc_control_data->scd_txdescs 250 #define sc_rxdescs sc_control_data->scd_rxdescs 251 252 #ifdef SIP_EVENT_COUNTERS 253 /* 254 * Event counters. 255 */ 256 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 257 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 258 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 259 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 260 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 261 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 262 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 263 #ifdef DP83820 264 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 265 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 266 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 267 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 268 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 269 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 270 #endif /* DP83820 */ 271 #endif /* SIP_EVENT_COUNTERS */ 272 273 u_int32_t sc_txcfg; /* prototype TXCFG register */ 274 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 275 u_int32_t sc_imr; /* prototype IMR register */ 276 u_int32_t sc_rfcr; /* prototype RFCR register */ 277 278 u_int32_t sc_cfg; /* prototype CFG register */ 279 280 #ifdef DP83820 281 u_int32_t sc_gpior; /* prototype GPIOR register */ 282 #endif /* DP83820 */ 283 284 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 285 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 286 287 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 288 289 int sc_flags; /* misc. flags; see below */ 290 291 int sc_txfree; /* number of free Tx descriptors */ 292 int sc_txnext; /* next ready Tx descriptor */ 293 int sc_txwin; /* Tx descriptors since last intr */ 294 295 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 296 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 297 298 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 299 #if defined(DP83820) 300 int sc_rxdiscard; 301 int sc_rxlen; 302 struct mbuf *sc_rxhead; 303 struct mbuf *sc_rxtail; 304 struct mbuf **sc_rxtailp; 305 #endif /* DP83820 */ 306 307 #if NRND > 0 308 rndsource_element_t rnd_source; /* random source */ 309 #endif 310 }; 311 312 /* sc_flags */ 313 #define SIPF_PAUSED 0x00000001 /* paused (802.3x flow control) */ 314 315 #ifdef DP83820 316 #define SIP_RXCHAIN_RESET(sc) \ 317 do { \ 318 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 319 *(sc)->sc_rxtailp = NULL; \ 320 (sc)->sc_rxlen = 0; \ 321 } while (/*CONSTCOND*/0) 322 323 #define SIP_RXCHAIN_LINK(sc, m) \ 324 do { \ 325 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 326 (sc)->sc_rxtailp = &(m)->m_next; \ 327 } while (/*CONSTCOND*/0) 328 #endif /* DP83820 */ 329 330 #ifdef SIP_EVENT_COUNTERS 331 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 332 #else 333 #define SIP_EVCNT_INCR(ev) /* nothing */ 334 #endif 335 336 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 337 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 338 339 #define SIP_CDTXSYNC(sc, x, n, ops) \ 340 do { \ 341 int __x, __n; \ 342 \ 343 __x = (x); \ 344 __n = (n); \ 345 \ 346 /* If it will wrap around, sync to the end of the ring. */ \ 347 if ((__x + __n) > SIP_NTXDESC) { \ 348 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 349 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 350 (SIP_NTXDESC - __x), (ops)); \ 351 __n -= (SIP_NTXDESC - __x); \ 352 __x = 0; \ 353 } \ 354 \ 355 /* Now sync whatever is left. */ \ 356 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 357 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 358 } while (0) 359 360 #define SIP_CDRXSYNC(sc, x, ops) \ 361 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 362 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 363 364 #ifdef DP83820 365 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 366 #define SIP_RXBUF_LEN (MCLBYTES - 4) 367 #else 368 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 369 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 370 #endif 371 #define SIP_INIT_RXDESC(sc, x) \ 372 do { \ 373 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 374 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 375 \ 376 __sipd->sipd_link = \ 377 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 378 __sipd->sipd_bufptr = \ 379 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 380 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 381 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 382 SIP_INIT_RXDESC_EXTSTS \ 383 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 384 } while (0) 385 386 #define SIP_CHIP_VERS(sc, v, p, r) \ 387 ((sc)->sc_model->sip_vendor == (v) && \ 388 (sc)->sc_model->sip_product == (p) && \ 389 (sc)->sc_rev == (r)) 390 391 #define SIP_CHIP_MODEL(sc, v, p) \ 392 ((sc)->sc_model->sip_vendor == (v) && \ 393 (sc)->sc_model->sip_product == (p)) 394 395 #if !defined(DP83820) 396 #define SIP_SIS900_REV(sc, rev) \ 397 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 398 #endif 399 400 #define SIP_TIMEOUT 1000 401 402 void SIP_DECL(start)(struct ifnet *); 403 void SIP_DECL(watchdog)(struct ifnet *); 404 int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 405 int SIP_DECL(init)(struct ifnet *); 406 void SIP_DECL(stop)(struct ifnet *, int); 407 408 void SIP_DECL(shutdown)(void *); 409 410 void SIP_DECL(reset)(struct sip_softc *); 411 void SIP_DECL(rxdrain)(struct sip_softc *); 412 int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 413 void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, u_int16_t *); 414 void SIP_DECL(tick)(void *); 415 416 #if !defined(DP83820) 417 void SIP_DECL(sis900_set_filter)(struct sip_softc *); 418 #endif /* ! DP83820 */ 419 void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 420 421 #if defined(DP83820) 422 void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 423 const struct pci_attach_args *, u_int8_t *); 424 #else 425 static void SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc); 426 void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 427 const struct pci_attach_args *, u_int8_t *); 428 void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 429 const struct pci_attach_args *, u_int8_t *); 430 #endif /* DP83820 */ 431 432 int SIP_DECL(intr)(void *); 433 void SIP_DECL(txintr)(struct sip_softc *); 434 void SIP_DECL(rxintr)(struct sip_softc *); 435 436 #if defined(DP83820) 437 int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 438 void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 439 void SIP_DECL(dp83820_mii_statchg)(struct device *); 440 #else 441 int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 442 void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 443 void SIP_DECL(sis900_mii_statchg)(struct device *); 444 445 int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 446 void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 447 void SIP_DECL(dp83815_mii_statchg)(struct device *); 448 #endif /* DP83820 */ 449 450 int SIP_DECL(mediachange)(struct ifnet *); 451 void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 452 453 int SIP_DECL(match)(struct device *, struct cfdata *, void *); 454 void SIP_DECL(attach)(struct device *, struct device *, void *); 455 456 int SIP_DECL(copy_small) = 0; 457 458 #ifdef DP83820 459 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 460 gsip_match, gsip_attach, NULL, NULL); 461 #else 462 CFATTACH_DECL(sip, sizeof(struct sip_softc), 463 sip_match, sip_attach, NULL, NULL); 464 #endif 465 466 /* 467 * Descriptions of the variants of the SiS900. 468 */ 469 struct sip_variant { 470 int (*sipv_mii_readreg)(struct device *, int, int); 471 void (*sipv_mii_writereg)(struct device *, int, int, int); 472 void (*sipv_mii_statchg)(struct device *); 473 void (*sipv_set_filter)(struct sip_softc *); 474 void (*sipv_read_macaddr)(struct sip_softc *, 475 const struct pci_attach_args *, u_int8_t *); 476 }; 477 478 u_int32_t SIP_DECL(mii_bitbang_read)(struct device *); 479 void SIP_DECL(mii_bitbang_write)(struct device *, u_int32_t); 480 481 const struct mii_bitbang_ops SIP_DECL(mii_bitbang_ops) = { 482 SIP_DECL(mii_bitbang_read), 483 SIP_DECL(mii_bitbang_write), 484 { 485 EROMAR_MDIO, /* MII_BIT_MDO */ 486 EROMAR_MDIO, /* MII_BIT_MDI */ 487 EROMAR_MDC, /* MII_BIT_MDC */ 488 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 489 0, /* MII_BIT_DIR_PHY_HOST */ 490 } 491 }; 492 493 #if defined(DP83820) 494 const struct sip_variant SIP_DECL(variant_dp83820) = { 495 SIP_DECL(dp83820_mii_readreg), 496 SIP_DECL(dp83820_mii_writereg), 497 SIP_DECL(dp83820_mii_statchg), 498 SIP_DECL(dp83815_set_filter), 499 SIP_DECL(dp83820_read_macaddr), 500 }; 501 #else 502 const struct sip_variant SIP_DECL(variant_sis900) = { 503 SIP_DECL(sis900_mii_readreg), 504 SIP_DECL(sis900_mii_writereg), 505 SIP_DECL(sis900_mii_statchg), 506 SIP_DECL(sis900_set_filter), 507 SIP_DECL(sis900_read_macaddr), 508 }; 509 510 const struct sip_variant SIP_DECL(variant_dp83815) = { 511 SIP_DECL(dp83815_mii_readreg), 512 SIP_DECL(dp83815_mii_writereg), 513 SIP_DECL(dp83815_mii_statchg), 514 SIP_DECL(dp83815_set_filter), 515 SIP_DECL(dp83815_read_macaddr), 516 }; 517 #endif /* DP83820 */ 518 519 /* 520 * Devices supported by this driver. 521 */ 522 const struct sip_product { 523 pci_vendor_id_t sip_vendor; 524 pci_product_id_t sip_product; 525 const char *sip_name; 526 const struct sip_variant *sip_variant; 527 } SIP_DECL(products)[] = { 528 #if defined(DP83820) 529 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 530 "NatSemi DP83820 Gigabit Ethernet", 531 &SIP_DECL(variant_dp83820) }, 532 #else 533 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 534 "SiS 900 10/100 Ethernet", 535 &SIP_DECL(variant_sis900) }, 536 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 537 "SiS 7016 10/100 Ethernet", 538 &SIP_DECL(variant_sis900) }, 539 540 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 541 "NatSemi DP83815 10/100 Ethernet", 542 &SIP_DECL(variant_dp83815) }, 543 #endif /* DP83820 */ 544 545 { 0, 0, 546 NULL, 547 NULL }, 548 }; 549 550 static const struct sip_product * 551 SIP_DECL(lookup)(const struct pci_attach_args *pa) 552 { 553 const struct sip_product *sip; 554 555 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 556 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 557 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 558 return (sip); 559 } 560 return (NULL); 561 } 562 563 #ifdef DP83820 564 /* 565 * I really hate stupid hardware vendors. There's a bit in the EEPROM 566 * which indicates if the card can do 64-bit data transfers. Unfortunately, 567 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 568 * which means we try to use 64-bit data transfers on those cards if we 569 * happen to be plugged into a 32-bit slot. 570 * 571 * What we do is use this table of cards known to be 64-bit cards. If 572 * you have a 64-bit card who's subsystem ID is not listed in this table, 573 * send the output of "pcictl dump ..." of the device to me so that your 574 * card will use the 64-bit data path when plugged into a 64-bit slot. 575 * 576 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 577 * June 30, 2002 578 */ 579 static int 580 SIP_DECL(check_64bit)(const struct pci_attach_args *pa) 581 { 582 static const struct { 583 pci_vendor_id_t c64_vendor; 584 pci_product_id_t c64_product; 585 } card64[] = { 586 /* Asante GigaNIX */ 587 { 0x128a, 0x0002 }, 588 589 /* Accton EN1407-T, Planex GN-1000TE */ 590 { 0x1113, 0x1407 }, 591 592 /* Netgear GA-621 */ 593 { 0x1385, 0x621a }, 594 595 /* SMC EZ Card */ 596 { 0x10b8, 0x9462 }, 597 598 { 0, 0} 599 }; 600 pcireg_t subsys; 601 int i; 602 603 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 604 605 for (i = 0; card64[i].c64_vendor != 0; i++) { 606 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 607 PCI_PRODUCT(subsys) == card64[i].c64_product) 608 return (1); 609 } 610 611 return (0); 612 } 613 #endif /* DP83820 */ 614 615 int 616 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 617 { 618 struct pci_attach_args *pa = aux; 619 620 if (SIP_DECL(lookup)(pa) != NULL) 621 return (1); 622 623 return (0); 624 } 625 626 void 627 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 628 { 629 struct sip_softc *sc = (struct sip_softc *) self; 630 struct pci_attach_args *pa = aux; 631 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 632 pci_chipset_tag_t pc = pa->pa_pc; 633 pci_intr_handle_t ih; 634 const char *intrstr = NULL; 635 bus_space_tag_t iot, memt; 636 bus_space_handle_t ioh, memh; 637 bus_dma_segment_t seg; 638 int ioh_valid, memh_valid; 639 int i, rseg, error; 640 const struct sip_product *sip; 641 pcireg_t pmode; 642 u_int8_t enaddr[ETHER_ADDR_LEN]; 643 int pmreg; 644 #ifdef DP83820 645 pcireg_t memtype; 646 u_int32_t reg; 647 #endif /* DP83820 */ 648 649 callout_init(&sc->sc_tick_ch); 650 651 sip = SIP_DECL(lookup)(pa); 652 if (sip == NULL) { 653 printf("\n"); 654 panic(SIP_STR(attach) ": impossible"); 655 } 656 sc->sc_rev = PCI_REVISION(pa->pa_class); 657 658 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 659 660 sc->sc_model = sip; 661 662 /* 663 * XXX Work-around broken PXE firmware on some boards. 664 * 665 * The DP83815 shares an address decoder with the MEM BAR 666 * and the ROM BAR. Make sure the ROM BAR is disabled, 667 * so that memory mapped access works. 668 */ 669 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 670 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 671 ~PCI_MAPREG_ROM_ENABLE); 672 673 /* 674 * Map the device. 675 */ 676 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 677 PCI_MAPREG_TYPE_IO, 0, 678 &iot, &ioh, NULL, NULL) == 0); 679 #ifdef DP83820 680 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 681 switch (memtype) { 682 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 683 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 684 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 685 memtype, 0, &memt, &memh, NULL, NULL) == 0); 686 break; 687 default: 688 memh_valid = 0; 689 } 690 #else 691 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 692 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 693 &memt, &memh, NULL, NULL) == 0); 694 #endif /* DP83820 */ 695 696 if (memh_valid) { 697 sc->sc_st = memt; 698 sc->sc_sh = memh; 699 } else if (ioh_valid) { 700 sc->sc_st = iot; 701 sc->sc_sh = ioh; 702 } else { 703 printf("%s: unable to map device registers\n", 704 sc->sc_dev.dv_xname); 705 return; 706 } 707 708 sc->sc_dmat = pa->pa_dmat; 709 710 /* 711 * Make sure bus mastering is enabled. Also make sure 712 * Write/Invalidate is enabled if we're allowed to use it. 713 */ 714 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 715 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 716 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 717 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 718 pmreg | PCI_COMMAND_MASTER_ENABLE); 719 720 /* Get it out of power save mode if needed. */ 721 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 722 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 723 PCI_PMCSR_STATE_MASK; 724 if (pmode == PCI_PMCSR_STATE_D3) { 725 /* 726 * The card has lost all configuration data in 727 * this state, so punt. 728 */ 729 printf("%s: unable to wake up from power state D3\n", 730 sc->sc_dev.dv_xname); 731 return; 732 } 733 if (pmode != PCI_PMCSR_STATE_D0) { 734 printf("%s: waking up from power state D%d\n", 735 sc->sc_dev.dv_xname, pmode); 736 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 737 PCI_PMCSR_STATE_D0); 738 } 739 } 740 741 /* 742 * Map and establish our interrupt. 743 */ 744 if (pci_intr_map(pa, &ih)) { 745 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 746 return; 747 } 748 intrstr = pci_intr_string(pc, ih); 749 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 750 if (sc->sc_ih == NULL) { 751 printf("%s: unable to establish interrupt", 752 sc->sc_dev.dv_xname); 753 if (intrstr != NULL) 754 printf(" at %s", intrstr); 755 printf("\n"); 756 return; 757 } 758 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 759 760 SIMPLEQ_INIT(&sc->sc_txfreeq); 761 SIMPLEQ_INIT(&sc->sc_txdirtyq); 762 763 /* 764 * Allocate the control data structures, and create and load the 765 * DMA map for it. 766 */ 767 if ((error = bus_dmamem_alloc(sc->sc_dmat, 768 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 769 0)) != 0) { 770 printf("%s: unable to allocate control data, error = %d\n", 771 sc->sc_dev.dv_xname, error); 772 goto fail_0; 773 } 774 775 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 776 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 777 BUS_DMA_COHERENT)) != 0) { 778 printf("%s: unable to map control data, error = %d\n", 779 sc->sc_dev.dv_xname, error); 780 goto fail_1; 781 } 782 783 if ((error = bus_dmamap_create(sc->sc_dmat, 784 sizeof(struct sip_control_data), 1, 785 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 786 printf("%s: unable to create control data DMA map, " 787 "error = %d\n", sc->sc_dev.dv_xname, error); 788 goto fail_2; 789 } 790 791 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 792 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 793 0)) != 0) { 794 printf("%s: unable to load control data DMA map, error = %d\n", 795 sc->sc_dev.dv_xname, error); 796 goto fail_3; 797 } 798 799 /* 800 * Create the transmit buffer DMA maps. 801 */ 802 for (i = 0; i < SIP_TXQUEUELEN; i++) { 803 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 804 SIP_NTXSEGS, MCLBYTES, 0, 0, 805 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 806 printf("%s: unable to create tx DMA map %d, " 807 "error = %d\n", sc->sc_dev.dv_xname, i, error); 808 goto fail_4; 809 } 810 } 811 812 /* 813 * Create the receive buffer DMA maps. 814 */ 815 for (i = 0; i < SIP_NRXDESC; i++) { 816 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 817 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 818 printf("%s: unable to create rx DMA map %d, " 819 "error = %d\n", sc->sc_dev.dv_xname, i, error); 820 goto fail_5; 821 } 822 sc->sc_rxsoft[i].rxs_mbuf = NULL; 823 } 824 825 /* 826 * Reset the chip to a known state. 827 */ 828 SIP_DECL(reset)(sc); 829 830 /* 831 * Read the Ethernet address from the EEPROM. This might 832 * also fetch other stuff from the EEPROM and stash it 833 * in the softc. 834 */ 835 sc->sc_cfg = 0; 836 #if !defined(DP83820) 837 if (SIP_SIS900_REV(sc,SIS_REV_635) || 838 SIP_SIS900_REV(sc,SIS_REV_900B)) 839 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 840 #endif 841 842 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 843 844 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 845 ether_sprintf(enaddr)); 846 847 /* 848 * Initialize the configuration register: aggressive PCI 849 * bus request algorithm, default backoff, default OW timer, 850 * default parity error detection. 851 * 852 * NOTE: "Big endian mode" is useless on the SiS900 and 853 * friends -- it affects packet data, not descriptors. 854 */ 855 #ifdef DP83820 856 /* 857 * Cause the chip to load configuration data from the EEPROM. 858 */ 859 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 860 for (i = 0; i < 10000; i++) { 861 delay(10); 862 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 863 PTSCR_EELOAD_EN) == 0) 864 break; 865 } 866 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 867 PTSCR_EELOAD_EN) { 868 printf("%s: timeout loading configuration from EEPROM\n", 869 sc->sc_dev.dv_xname); 870 return; 871 } 872 873 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 874 875 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 876 if (reg & CFG_PCI64_DET) { 877 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 878 /* 879 * Check to see if this card is 64-bit. If so, enable 64-bit 880 * data transfers. 881 * 882 * We can't use the DATA64_EN bit in the EEPROM, because 883 * vendors of 32-bit cards fail to clear that bit in many 884 * cases (yet the card still detects that it's in a 64-bit 885 * slot; go figure). 886 */ 887 if (SIP_DECL(check_64bit)(pa)) { 888 sc->sc_cfg |= CFG_DATA64_EN; 889 printf(", using 64-bit data transfers"); 890 } 891 printf("\n"); 892 } 893 894 /* 895 * XXX Need some PCI flags indicating support for 896 * XXX 64-bit addressing. 897 */ 898 #if 0 899 if (reg & CFG_M64ADDR) 900 sc->sc_cfg |= CFG_M64ADDR; 901 if (reg & CFG_T64ADDR) 902 sc->sc_cfg |= CFG_T64ADDR; 903 #endif 904 905 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 906 const char *sep = ""; 907 printf("%s: using ", sc->sc_dev.dv_xname); 908 if (reg & CFG_EXT_125) { 909 sc->sc_cfg |= CFG_EXT_125; 910 printf("%s125MHz clock", sep); 911 sep = ", "; 912 } 913 if (reg & CFG_TBI_EN) { 914 sc->sc_cfg |= CFG_TBI_EN; 915 printf("%sten-bit interface", sep); 916 sep = ", "; 917 } 918 printf("\n"); 919 } 920 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 921 (reg & CFG_MRM_DIS) != 0) 922 sc->sc_cfg |= CFG_MRM_DIS; 923 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 924 (reg & CFG_MWI_DIS) != 0) 925 sc->sc_cfg |= CFG_MWI_DIS; 926 927 /* 928 * Use the extended descriptor format on the DP83820. This 929 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 930 * checksumming. 931 */ 932 sc->sc_cfg |= CFG_EXTSTS_EN; 933 #endif /* DP83820 */ 934 935 /* 936 * Initialize our media structures and probe the MII. 937 */ 938 sc->sc_mii.mii_ifp = ifp; 939 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 940 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 941 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 942 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, SIP_DECL(mediachange), 943 SIP_DECL(mediastatus)); 944 945 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 946 MII_OFFSET_ANY, 0); 947 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 948 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 949 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 950 } else 951 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 952 953 ifp = &sc->sc_ethercom.ec_if; 954 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 955 ifp->if_softc = sc; 956 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 957 ifp->if_ioctl = SIP_DECL(ioctl); 958 ifp->if_start = SIP_DECL(start); 959 ifp->if_watchdog = SIP_DECL(watchdog); 960 ifp->if_init = SIP_DECL(init); 961 ifp->if_stop = SIP_DECL(stop); 962 IFQ_SET_READY(&ifp->if_snd); 963 964 /* 965 * We can support 802.1Q VLAN-sized frames. 966 */ 967 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 968 969 #ifdef DP83820 970 /* 971 * And the DP83820 can do VLAN tagging in hardware, and 972 * support the jumbo Ethernet MTU. 973 */ 974 sc->sc_ethercom.ec_capabilities |= 975 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 976 977 /* 978 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 979 * in hardware. 980 */ 981 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 982 IFCAP_CSUM_UDPv4; 983 #endif /* DP83820 */ 984 985 /* 986 * Attach the interface. 987 */ 988 if_attach(ifp); 989 ether_ifattach(ifp, enaddr); 990 #if NRND > 0 991 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 992 RND_TYPE_NET, 0); 993 #endif 994 995 /* 996 * The number of bytes that must be available in 997 * the Tx FIFO before the bus master can DMA more 998 * data into the FIFO. 999 */ 1000 sc->sc_tx_fill_thresh = 64 / 32; 1001 1002 /* 1003 * Start at a drain threshold of 512 bytes. We will 1004 * increase it if a DMA underrun occurs. 1005 * 1006 * XXX The minimum value of this variable should be 1007 * tuned. We may be able to improve performance 1008 * by starting with a lower value. That, however, 1009 * may trash the first few outgoing packets if the 1010 * PCI bus is saturated. 1011 */ 1012 sc->sc_tx_drain_thresh = 1504 / 32; 1013 1014 /* 1015 * Initialize the Rx FIFO drain threshold. 1016 * 1017 * This is in units of 8 bytes. 1018 * 1019 * We should never set this value lower than 2; 14 bytes are 1020 * required to filter the packet. 1021 */ 1022 sc->sc_rx_drain_thresh = 128 / 8; 1023 1024 #ifdef SIP_EVENT_COUNTERS 1025 /* 1026 * Attach event counters. 1027 */ 1028 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1029 NULL, sc->sc_dev.dv_xname, "txsstall"); 1030 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1031 NULL, sc->sc_dev.dv_xname, "txdstall"); 1032 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1033 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1034 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1035 NULL, sc->sc_dev.dv_xname, "txdintr"); 1036 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1037 NULL, sc->sc_dev.dv_xname, "txiintr"); 1038 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1039 NULL, sc->sc_dev.dv_xname, "rxintr"); 1040 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1041 NULL, sc->sc_dev.dv_xname, "hiberr"); 1042 #ifdef DP83820 1043 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1044 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1045 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1046 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1047 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1048 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1049 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1050 NULL, sc->sc_dev.dv_xname, "txipsum"); 1051 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1052 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1053 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1054 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1055 #endif /* DP83820 */ 1056 #endif /* SIP_EVENT_COUNTERS */ 1057 1058 /* 1059 * Make sure the interface is shutdown during reboot. 1060 */ 1061 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 1062 if (sc->sc_sdhook == NULL) 1063 printf("%s: WARNING: unable to establish shutdown hook\n", 1064 sc->sc_dev.dv_xname); 1065 return; 1066 1067 /* 1068 * Free any resources we've allocated during the failed attach 1069 * attempt. Do this in reverse order and fall through. 1070 */ 1071 fail_5: 1072 for (i = 0; i < SIP_NRXDESC; i++) { 1073 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1074 bus_dmamap_destroy(sc->sc_dmat, 1075 sc->sc_rxsoft[i].rxs_dmamap); 1076 } 1077 fail_4: 1078 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1079 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1080 bus_dmamap_destroy(sc->sc_dmat, 1081 sc->sc_txsoft[i].txs_dmamap); 1082 } 1083 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1084 fail_3: 1085 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1086 fail_2: 1087 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1088 sizeof(struct sip_control_data)); 1089 fail_1: 1090 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1091 fail_0: 1092 return; 1093 } 1094 1095 /* 1096 * sip_shutdown: 1097 * 1098 * Make sure the interface is stopped at reboot time. 1099 */ 1100 void 1101 SIP_DECL(shutdown)(void *arg) 1102 { 1103 struct sip_softc *sc = arg; 1104 1105 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1106 } 1107 1108 /* 1109 * sip_start: [ifnet interface function] 1110 * 1111 * Start packet transmission on the interface. 1112 */ 1113 void 1114 SIP_DECL(start)(struct ifnet *ifp) 1115 { 1116 struct sip_softc *sc = ifp->if_softc; 1117 struct mbuf *m0; 1118 #ifndef DP83820 1119 struct mbuf *m; 1120 #endif 1121 struct sip_txsoft *txs; 1122 bus_dmamap_t dmamap; 1123 int error, nexttx, lasttx, seg; 1124 int ofree = sc->sc_txfree; 1125 #if 0 1126 int firsttx = sc->sc_txnext; 1127 #endif 1128 #ifdef DP83820 1129 struct m_tag *mtag; 1130 u_int32_t extsts; 1131 #endif 1132 1133 /* 1134 * If we've been told to pause, don't transmit any more packets. 1135 */ 1136 if (sc->sc_flags & SIPF_PAUSED) 1137 ifp->if_flags |= IFF_OACTIVE; 1138 1139 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1140 return; 1141 1142 /* 1143 * Loop through the send queue, setting up transmit descriptors 1144 * until we drain the queue, or use up all available transmit 1145 * descriptors. 1146 */ 1147 for (;;) { 1148 /* Get a work queue entry. */ 1149 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1150 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1151 break; 1152 } 1153 1154 /* 1155 * Grab a packet off the queue. 1156 */ 1157 IFQ_POLL(&ifp->if_snd, m0); 1158 if (m0 == NULL) 1159 break; 1160 #ifndef DP83820 1161 m = NULL; 1162 #endif 1163 1164 dmamap = txs->txs_dmamap; 1165 1166 #ifdef DP83820 1167 /* 1168 * Load the DMA map. If this fails, the packet either 1169 * didn't fit in the allotted number of segments, or we 1170 * were short on resources. For the too-many-segments 1171 * case, we simply report an error and drop the packet, 1172 * since we can't sanely copy a jumbo packet to a single 1173 * buffer. 1174 */ 1175 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1176 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1177 if (error) { 1178 if (error == EFBIG) { 1179 printf("%s: Tx packet consumes too many " 1180 "DMA segments, dropping...\n", 1181 sc->sc_dev.dv_xname); 1182 IFQ_DEQUEUE(&ifp->if_snd, m0); 1183 m_freem(m0); 1184 continue; 1185 } 1186 /* 1187 * Short on resources, just stop for now. 1188 */ 1189 break; 1190 } 1191 #else /* DP83820 */ 1192 /* 1193 * Load the DMA map. If this fails, the packet either 1194 * didn't fit in the alloted number of segments, or we 1195 * were short on resources. In this case, we'll copy 1196 * and try again. 1197 */ 1198 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1199 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1200 MGETHDR(m, M_DONTWAIT, MT_DATA); 1201 if (m == NULL) { 1202 printf("%s: unable to allocate Tx mbuf\n", 1203 sc->sc_dev.dv_xname); 1204 break; 1205 } 1206 if (m0->m_pkthdr.len > MHLEN) { 1207 MCLGET(m, M_DONTWAIT); 1208 if ((m->m_flags & M_EXT) == 0) { 1209 printf("%s: unable to allocate Tx " 1210 "cluster\n", sc->sc_dev.dv_xname); 1211 m_freem(m); 1212 break; 1213 } 1214 } 1215 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1216 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1217 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1218 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1219 if (error) { 1220 printf("%s: unable to load Tx buffer, " 1221 "error = %d\n", sc->sc_dev.dv_xname, error); 1222 break; 1223 } 1224 } 1225 #endif /* DP83820 */ 1226 1227 /* 1228 * Ensure we have enough descriptors free to describe 1229 * the packet. Note, we always reserve one descriptor 1230 * at the end of the ring as a termination point, to 1231 * prevent wrap-around. 1232 */ 1233 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1234 /* 1235 * Not enough free descriptors to transmit this 1236 * packet. We haven't committed anything yet, 1237 * so just unload the DMA map, put the packet 1238 * back on the queue, and punt. Notify the upper 1239 * layer that there are not more slots left. 1240 * 1241 * XXX We could allocate an mbuf and copy, but 1242 * XXX is it worth it? 1243 */ 1244 ifp->if_flags |= IFF_OACTIVE; 1245 bus_dmamap_unload(sc->sc_dmat, dmamap); 1246 #ifndef DP83820 1247 if (m != NULL) 1248 m_freem(m); 1249 #endif 1250 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1251 break; 1252 } 1253 1254 IFQ_DEQUEUE(&ifp->if_snd, m0); 1255 #ifndef DP83820 1256 if (m != NULL) { 1257 m_freem(m0); 1258 m0 = m; 1259 } 1260 #endif 1261 1262 /* 1263 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1264 */ 1265 1266 /* Sync the DMA map. */ 1267 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1268 BUS_DMASYNC_PREWRITE); 1269 1270 /* 1271 * Initialize the transmit descriptors. 1272 */ 1273 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1274 seg < dmamap->dm_nsegs; 1275 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1276 /* 1277 * If this is the first descriptor we're 1278 * enqueueing, don't set the OWN bit just 1279 * yet. That could cause a race condition. 1280 * We'll do it below. 1281 */ 1282 sc->sc_txdescs[nexttx].sipd_bufptr = 1283 htole32(dmamap->dm_segs[seg].ds_addr); 1284 sc->sc_txdescs[nexttx].sipd_cmdsts = 1285 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1286 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1287 #ifdef DP83820 1288 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1289 #endif /* DP83820 */ 1290 lasttx = nexttx; 1291 } 1292 1293 /* Clear the MORE bit on the last segment. */ 1294 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1295 1296 /* 1297 * If we're in the interrupt delay window, delay the 1298 * interrupt. 1299 */ 1300 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1301 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1302 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1303 htole32(CMDSTS_INTR); 1304 sc->sc_txwin = 0; 1305 } 1306 1307 #ifdef DP83820 1308 /* 1309 * If VLANs are enabled and the packet has a VLAN tag, set 1310 * up the descriptor to encapsulate the packet for us. 1311 * 1312 * This apparently has to be on the last descriptor of 1313 * the packet. 1314 */ 1315 if (sc->sc_ethercom.ec_nvlans != 0 && 1316 (mtag = m_tag_find(m0, PACKET_TAG_VLAN, NULL)) != NULL) { 1317 sc->sc_txdescs[lasttx].sipd_extsts |= 1318 htole32(EXTSTS_VPKT | 1319 (*(u_int *)(mtag + 1) & EXTSTS_VTCI)); 1320 } 1321 1322 /* 1323 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1324 * checksumming, set up the descriptor to do this work 1325 * for us. 1326 * 1327 * This apparently has to be on the first descriptor of 1328 * the packet. 1329 * 1330 * Byte-swap constants so the compiler can optimize. 1331 */ 1332 extsts = 0; 1333 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1334 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1335 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1336 extsts |= htole32(EXTSTS_IPPKT); 1337 } 1338 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1339 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1340 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1341 extsts |= htole32(EXTSTS_TCPPKT); 1342 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1343 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1344 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1345 extsts |= htole32(EXTSTS_UDPPKT); 1346 } 1347 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1348 #endif /* DP83820 */ 1349 1350 /* Sync the descriptors we're using. */ 1351 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1352 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1353 1354 /* 1355 * The entire packet is set up. Give the first descrptor 1356 * to the chip now. 1357 */ 1358 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1359 htole32(CMDSTS_OWN); 1360 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1361 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1362 1363 /* 1364 * Store a pointer to the packet so we can free it later, 1365 * and remember what txdirty will be once the packet is 1366 * done. 1367 */ 1368 txs->txs_mbuf = m0; 1369 txs->txs_firstdesc = sc->sc_txnext; 1370 txs->txs_lastdesc = lasttx; 1371 1372 /* Advance the tx pointer. */ 1373 sc->sc_txfree -= dmamap->dm_nsegs; 1374 sc->sc_txnext = nexttx; 1375 1376 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1377 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1378 1379 #if NBPFILTER > 0 1380 /* 1381 * Pass the packet to any BPF listeners. 1382 */ 1383 if (ifp->if_bpf) 1384 bpf_mtap(ifp->if_bpf, m0); 1385 #endif /* NBPFILTER > 0 */ 1386 } 1387 1388 if (txs == NULL || sc->sc_txfree == 0) { 1389 /* No more slots left; notify upper layer. */ 1390 ifp->if_flags |= IFF_OACTIVE; 1391 } 1392 1393 if (sc->sc_txfree != ofree) { 1394 /* 1395 * Start the transmit process. Note, the manual says 1396 * that if there are no pending transmissions in the 1397 * chip's internal queue (indicated by TXE being clear), 1398 * then the driver software must set the TXDP to the 1399 * first descriptor to be transmitted. However, if we 1400 * do this, it causes serious performance degredation on 1401 * the DP83820 under load, not setting TXDP doesn't seem 1402 * to adversely affect the SiS 900 or DP83815. 1403 * 1404 * Well, I guess it wouldn't be the first time a manual 1405 * has lied -- and they could be speaking of the NULL- 1406 * terminated descriptor list case, rather than OWN- 1407 * terminated rings. 1408 */ 1409 #if 0 1410 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1411 CR_TXE) == 0) { 1412 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1413 SIP_CDTXADDR(sc, firsttx)); 1414 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1415 } 1416 #else 1417 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1418 #endif 1419 1420 /* Set a watchdog timer in case the chip flakes out. */ 1421 ifp->if_timer = 5; 1422 } 1423 } 1424 1425 /* 1426 * sip_watchdog: [ifnet interface function] 1427 * 1428 * Watchdog timer handler. 1429 */ 1430 void 1431 SIP_DECL(watchdog)(struct ifnet *ifp) 1432 { 1433 struct sip_softc *sc = ifp->if_softc; 1434 1435 /* 1436 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1437 * If we get a timeout, try and sweep up transmit descriptors. 1438 * If we manage to sweep them all up, ignore the lack of 1439 * interrupt. 1440 */ 1441 SIP_DECL(txintr)(sc); 1442 1443 if (sc->sc_txfree != SIP_NTXDESC) { 1444 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1445 ifp->if_oerrors++; 1446 1447 /* Reset the interface. */ 1448 (void) SIP_DECL(init)(ifp); 1449 } else if (ifp->if_flags & IFF_DEBUG) 1450 printf("%s: recovered from device timeout\n", 1451 sc->sc_dev.dv_xname); 1452 1453 /* Try to get more packets going. */ 1454 SIP_DECL(start)(ifp); 1455 } 1456 1457 /* 1458 * sip_ioctl: [ifnet interface function] 1459 * 1460 * Handle control requests from the operator. 1461 */ 1462 int 1463 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1464 { 1465 struct sip_softc *sc = ifp->if_softc; 1466 struct ifreq *ifr = (struct ifreq *)data; 1467 int s, error; 1468 1469 s = splnet(); 1470 1471 switch (cmd) { 1472 case SIOCSIFMEDIA: 1473 case SIOCGIFMEDIA: 1474 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1475 break; 1476 1477 default: 1478 error = ether_ioctl(ifp, cmd, data); 1479 if (error == ENETRESET) { 1480 /* 1481 * Multicast list has changed; set the hardware filter 1482 * accordingly. 1483 */ 1484 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1485 error = 0; 1486 } 1487 break; 1488 } 1489 1490 /* Try to get more packets going. */ 1491 SIP_DECL(start)(ifp); 1492 1493 splx(s); 1494 return (error); 1495 } 1496 1497 /* 1498 * sip_intr: 1499 * 1500 * Interrupt service routine. 1501 */ 1502 int 1503 SIP_DECL(intr)(void *arg) 1504 { 1505 struct sip_softc *sc = arg; 1506 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1507 u_int32_t isr; 1508 int handled = 0; 1509 1510 for (;;) { 1511 /* Reading clears interrupt. */ 1512 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1513 if ((isr & sc->sc_imr) == 0) 1514 break; 1515 1516 #if NRND > 0 1517 if (RND_ENABLED(&sc->rnd_source)) 1518 rnd_add_uint32(&sc->rnd_source, isr); 1519 #endif 1520 1521 handled = 1; 1522 1523 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1524 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1525 1526 /* Grab any new packets. */ 1527 SIP_DECL(rxintr)(sc); 1528 1529 if (isr & ISR_RXORN) { 1530 printf("%s: receive FIFO overrun\n", 1531 sc->sc_dev.dv_xname); 1532 1533 /* XXX adjust rx_drain_thresh? */ 1534 } 1535 1536 if (isr & ISR_RXIDLE) { 1537 printf("%s: receive ring overrun\n", 1538 sc->sc_dev.dv_xname); 1539 1540 /* Get the receive process going again. */ 1541 bus_space_write_4(sc->sc_st, sc->sc_sh, 1542 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1543 bus_space_write_4(sc->sc_st, sc->sc_sh, 1544 SIP_CR, CR_RXE); 1545 } 1546 } 1547 1548 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1549 #ifdef SIP_EVENT_COUNTERS 1550 if (isr & ISR_TXDESC) 1551 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1552 else if (isr & ISR_TXIDLE) 1553 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1554 #endif 1555 1556 /* Sweep up transmit descriptors. */ 1557 SIP_DECL(txintr)(sc); 1558 1559 if (isr & ISR_TXURN) { 1560 u_int32_t thresh; 1561 1562 printf("%s: transmit FIFO underrun", 1563 sc->sc_dev.dv_xname); 1564 1565 thresh = sc->sc_tx_drain_thresh + 1; 1566 if (thresh <= TXCFG_DRTH && 1567 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1568 (sc->sc_tx_fill_thresh * 32))) { 1569 printf("; increasing Tx drain " 1570 "threshold to %u bytes\n", 1571 thresh * 32); 1572 sc->sc_tx_drain_thresh = thresh; 1573 (void) SIP_DECL(init)(ifp); 1574 } else { 1575 (void) SIP_DECL(init)(ifp); 1576 printf("\n"); 1577 } 1578 } 1579 } 1580 1581 #if !defined(DP83820) 1582 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1583 if (isr & ISR_PAUSE_ST) { 1584 sc->sc_flags |= SIPF_PAUSED; 1585 ifp->if_flags |= IFF_OACTIVE; 1586 } 1587 if (isr & ISR_PAUSE_END) { 1588 sc->sc_flags &= ~SIPF_PAUSED; 1589 ifp->if_flags &= ~IFF_OACTIVE; 1590 } 1591 } 1592 #endif /* ! DP83820 */ 1593 1594 if (isr & ISR_HIBERR) { 1595 int want_init = 0; 1596 1597 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1598 1599 #define PRINTERR(bit, str) \ 1600 do { \ 1601 if ((isr & (bit)) != 0) { \ 1602 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1603 printf("%s: %s\n", \ 1604 sc->sc_dev.dv_xname, str); \ 1605 want_init = 1; \ 1606 } \ 1607 } while (/*CONSTCOND*/0) 1608 1609 PRINTERR(ISR_DPERR, "parity error"); 1610 PRINTERR(ISR_SSERR, "system error"); 1611 PRINTERR(ISR_RMABT, "master abort"); 1612 PRINTERR(ISR_RTABT, "target abort"); 1613 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1614 /* 1615 * Ignore: 1616 * Tx reset complete 1617 * Rx reset complete 1618 */ 1619 if (want_init) 1620 (void) SIP_DECL(init)(ifp); 1621 #undef PRINTERR 1622 } 1623 } 1624 1625 /* Try to get more packets going. */ 1626 SIP_DECL(start)(ifp); 1627 1628 return (handled); 1629 } 1630 1631 /* 1632 * sip_txintr: 1633 * 1634 * Helper; handle transmit interrupts. 1635 */ 1636 void 1637 SIP_DECL(txintr)(struct sip_softc *sc) 1638 { 1639 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1640 struct sip_txsoft *txs; 1641 u_int32_t cmdsts; 1642 1643 if ((sc->sc_flags & SIPF_PAUSED) == 0) 1644 ifp->if_flags &= ~IFF_OACTIVE; 1645 1646 /* 1647 * Go through our Tx list and free mbufs for those 1648 * frames which have been transmitted. 1649 */ 1650 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1651 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1652 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1653 1654 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1655 if (cmdsts & CMDSTS_OWN) 1656 break; 1657 1658 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1659 1660 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1661 1662 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1663 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1664 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1665 m_freem(txs->txs_mbuf); 1666 txs->txs_mbuf = NULL; 1667 1668 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1669 1670 /* 1671 * Check for errors and collisions. 1672 */ 1673 if (cmdsts & 1674 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1675 ifp->if_oerrors++; 1676 if (cmdsts & CMDSTS_Tx_EC) 1677 ifp->if_collisions += 16; 1678 if (ifp->if_flags & IFF_DEBUG) { 1679 if (cmdsts & CMDSTS_Tx_ED) 1680 printf("%s: excessive deferral\n", 1681 sc->sc_dev.dv_xname); 1682 if (cmdsts & CMDSTS_Tx_EC) 1683 printf("%s: excessive collisions\n", 1684 sc->sc_dev.dv_xname); 1685 } 1686 } else { 1687 /* Packet was transmitted successfully. */ 1688 ifp->if_opackets++; 1689 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1690 } 1691 } 1692 1693 /* 1694 * If there are no more pending transmissions, cancel the watchdog 1695 * timer. 1696 */ 1697 if (txs == NULL) { 1698 ifp->if_timer = 0; 1699 sc->sc_txwin = 0; 1700 } 1701 } 1702 1703 #if defined(DP83820) 1704 /* 1705 * sip_rxintr: 1706 * 1707 * Helper; handle receive interrupts. 1708 */ 1709 void 1710 SIP_DECL(rxintr)(struct sip_softc *sc) 1711 { 1712 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1713 struct sip_rxsoft *rxs; 1714 struct mbuf *m, *tailm; 1715 u_int32_t cmdsts, extsts; 1716 int i, len; 1717 1718 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1719 rxs = &sc->sc_rxsoft[i]; 1720 1721 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1722 1723 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1724 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1725 1726 /* 1727 * NOTE: OWN is set if owned by _consumer_. We're the 1728 * consumer of the receive ring, so if the bit is clear, 1729 * we have processed all of the packets. 1730 */ 1731 if ((cmdsts & CMDSTS_OWN) == 0) { 1732 /* 1733 * We have processed all of the receive buffers. 1734 */ 1735 break; 1736 } 1737 1738 if (__predict_false(sc->sc_rxdiscard)) { 1739 SIP_INIT_RXDESC(sc, i); 1740 if ((cmdsts & CMDSTS_MORE) == 0) { 1741 /* Reset our state. */ 1742 sc->sc_rxdiscard = 0; 1743 } 1744 continue; 1745 } 1746 1747 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1748 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1749 1750 m = rxs->rxs_mbuf; 1751 1752 /* 1753 * Add a new receive buffer to the ring. 1754 */ 1755 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1756 /* 1757 * Failed, throw away what we've done so 1758 * far, and discard the rest of the packet. 1759 */ 1760 ifp->if_ierrors++; 1761 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1762 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1763 SIP_INIT_RXDESC(sc, i); 1764 if (cmdsts & CMDSTS_MORE) 1765 sc->sc_rxdiscard = 1; 1766 if (sc->sc_rxhead != NULL) 1767 m_freem(sc->sc_rxhead); 1768 SIP_RXCHAIN_RESET(sc); 1769 continue; 1770 } 1771 1772 SIP_RXCHAIN_LINK(sc, m); 1773 1774 /* 1775 * If this is not the end of the packet, keep 1776 * looking. 1777 */ 1778 if (cmdsts & CMDSTS_MORE) { 1779 sc->sc_rxlen += m->m_len; 1780 continue; 1781 } 1782 1783 /* 1784 * Okay, we have the entire packet now... 1785 */ 1786 *sc->sc_rxtailp = NULL; 1787 m = sc->sc_rxhead; 1788 tailm = sc->sc_rxtail; 1789 1790 SIP_RXCHAIN_RESET(sc); 1791 1792 /* 1793 * If an error occurred, update stats and drop the packet. 1794 */ 1795 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1796 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1797 ifp->if_ierrors++; 1798 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1799 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1800 /* Receive overrun handled elsewhere. */ 1801 printf("%s: receive descriptor error\n", 1802 sc->sc_dev.dv_xname); 1803 } 1804 #define PRINTERR(bit, str) \ 1805 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1806 (cmdsts & (bit)) != 0) \ 1807 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1808 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1809 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1810 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1811 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1812 #undef PRINTERR 1813 m_freem(m); 1814 continue; 1815 } 1816 1817 /* 1818 * No errors. 1819 * 1820 * Note, the DP83820 includes the CRC with 1821 * every packet. 1822 */ 1823 len = CMDSTS_SIZE(cmdsts); 1824 tailm->m_len = len - sc->sc_rxlen; 1825 1826 /* 1827 * If the packet is small enough to fit in a 1828 * single header mbuf, allocate one and copy 1829 * the data into it. This greatly reduces 1830 * memory consumption when we receive lots 1831 * of small packets. 1832 */ 1833 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1834 struct mbuf *nm; 1835 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1836 if (nm == NULL) { 1837 ifp->if_ierrors++; 1838 m_freem(m); 1839 continue; 1840 } 1841 nm->m_data += 2; 1842 nm->m_pkthdr.len = nm->m_len = len; 1843 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1844 m_freem(m); 1845 m = nm; 1846 } 1847 #ifndef __NO_STRICT_ALIGNMENT 1848 else { 1849 /* 1850 * The DP83820's receive buffers must be 4-byte 1851 * aligned. But this means that the data after 1852 * the Ethernet header is misaligned. To compensate, 1853 * we have artificially shortened the buffer size 1854 * in the descriptor, and we do an overlapping copy 1855 * of the data two bytes further in (in the first 1856 * buffer of the chain only). 1857 */ 1858 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1859 m->m_len); 1860 m->m_data += 2; 1861 } 1862 #endif /* ! __NO_STRICT_ALIGNMENT */ 1863 1864 /* 1865 * If VLANs are enabled, VLAN packets have been unwrapped 1866 * for us. Associate the tag with the packet. 1867 */ 1868 if (sc->sc_ethercom.ec_nvlans != 0 && 1869 (extsts & EXTSTS_VPKT) != 0) { 1870 struct m_tag *vtag; 1871 1872 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 1873 M_NOWAIT); 1874 if (vtag == NULL) { 1875 ifp->if_ierrors++; 1876 printf("%s: unable to allocate VLAN tag\n", 1877 sc->sc_dev.dv_xname); 1878 m_freem(m); 1879 continue; 1880 } 1881 1882 *(u_int *)(vtag + 1) = ntohs(extsts & EXTSTS_VTCI); 1883 } 1884 1885 /* 1886 * Set the incoming checksum information for the 1887 * packet. 1888 */ 1889 if ((extsts & EXTSTS_IPPKT) != 0) { 1890 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1891 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1892 if (extsts & EXTSTS_Rx_IPERR) 1893 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1894 if (extsts & EXTSTS_TCPPKT) { 1895 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1896 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1897 if (extsts & EXTSTS_Rx_TCPERR) 1898 m->m_pkthdr.csum_flags |= 1899 M_CSUM_TCP_UDP_BAD; 1900 } else if (extsts & EXTSTS_UDPPKT) { 1901 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1902 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1903 if (extsts & EXTSTS_Rx_UDPERR) 1904 m->m_pkthdr.csum_flags |= 1905 M_CSUM_TCP_UDP_BAD; 1906 } 1907 } 1908 1909 ifp->if_ipackets++; 1910 m->m_flags |= M_HASFCS; 1911 m->m_pkthdr.rcvif = ifp; 1912 m->m_pkthdr.len = len; 1913 1914 #if NBPFILTER > 0 1915 /* 1916 * Pass this up to any BPF listeners, but only 1917 * pass if up the stack if it's for us. 1918 */ 1919 if (ifp->if_bpf) 1920 bpf_mtap(ifp->if_bpf, m); 1921 #endif /* NBPFILTER > 0 */ 1922 1923 /* Pass it on. */ 1924 (*ifp->if_input)(ifp, m); 1925 } 1926 1927 /* Update the receive pointer. */ 1928 sc->sc_rxptr = i; 1929 } 1930 #else /* ! DP83820 */ 1931 /* 1932 * sip_rxintr: 1933 * 1934 * Helper; handle receive interrupts. 1935 */ 1936 void 1937 SIP_DECL(rxintr)(struct sip_softc *sc) 1938 { 1939 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1940 struct sip_rxsoft *rxs; 1941 struct mbuf *m; 1942 u_int32_t cmdsts; 1943 int i, len; 1944 1945 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1946 rxs = &sc->sc_rxsoft[i]; 1947 1948 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1949 1950 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1951 1952 /* 1953 * NOTE: OWN is set if owned by _consumer_. We're the 1954 * consumer of the receive ring, so if the bit is clear, 1955 * we have processed all of the packets. 1956 */ 1957 if ((cmdsts & CMDSTS_OWN) == 0) { 1958 /* 1959 * We have processed all of the receive buffers. 1960 */ 1961 break; 1962 } 1963 1964 /* 1965 * If any collisions were seen on the wire, count one. 1966 */ 1967 if (cmdsts & CMDSTS_Rx_COL) 1968 ifp->if_collisions++; 1969 1970 /* 1971 * If an error occurred, update stats, clear the status 1972 * word, and leave the packet buffer in place. It will 1973 * simply be reused the next time the ring comes around. 1974 */ 1975 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1976 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1977 ifp->if_ierrors++; 1978 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1979 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1980 /* Receive overrun handled elsewhere. */ 1981 printf("%s: receive descriptor error\n", 1982 sc->sc_dev.dv_xname); 1983 } 1984 #define PRINTERR(bit, str) \ 1985 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1986 (cmdsts & (bit)) != 0) \ 1987 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1988 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1989 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1990 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1991 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1992 #undef PRINTERR 1993 SIP_INIT_RXDESC(sc, i); 1994 continue; 1995 } 1996 1997 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1998 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1999 2000 /* 2001 * No errors; receive the packet. Note, the SiS 900 2002 * includes the CRC with every packet. 2003 */ 2004 len = CMDSTS_SIZE(cmdsts); 2005 2006 #ifdef __NO_STRICT_ALIGNMENT 2007 /* 2008 * If the packet is small enough to fit in a 2009 * single header mbuf, allocate one and copy 2010 * the data into it. This greatly reduces 2011 * memory consumption when we receive lots 2012 * of small packets. 2013 * 2014 * Otherwise, we add a new buffer to the receive 2015 * chain. If this fails, we drop the packet and 2016 * recycle the old buffer. 2017 */ 2018 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 2019 MGETHDR(m, M_DONTWAIT, MT_DATA); 2020 if (m == NULL) 2021 goto dropit; 2022 memcpy(mtod(m, caddr_t), 2023 mtod(rxs->rxs_mbuf, caddr_t), len); 2024 SIP_INIT_RXDESC(sc, i); 2025 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2026 rxs->rxs_dmamap->dm_mapsize, 2027 BUS_DMASYNC_PREREAD); 2028 } else { 2029 m = rxs->rxs_mbuf; 2030 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 2031 dropit: 2032 ifp->if_ierrors++; 2033 SIP_INIT_RXDESC(sc, i); 2034 bus_dmamap_sync(sc->sc_dmat, 2035 rxs->rxs_dmamap, 0, 2036 rxs->rxs_dmamap->dm_mapsize, 2037 BUS_DMASYNC_PREREAD); 2038 continue; 2039 } 2040 } 2041 #else 2042 /* 2043 * The SiS 900's receive buffers must be 4-byte aligned. 2044 * But this means that the data after the Ethernet header 2045 * is misaligned. We must allocate a new buffer and 2046 * copy the data, shifted forward 2 bytes. 2047 */ 2048 MGETHDR(m, M_DONTWAIT, MT_DATA); 2049 if (m == NULL) { 2050 dropit: 2051 ifp->if_ierrors++; 2052 SIP_INIT_RXDESC(sc, i); 2053 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2054 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2055 continue; 2056 } 2057 if (len > (MHLEN - 2)) { 2058 MCLGET(m, M_DONTWAIT); 2059 if ((m->m_flags & M_EXT) == 0) { 2060 m_freem(m); 2061 goto dropit; 2062 } 2063 } 2064 m->m_data += 2; 2065 2066 /* 2067 * Note that we use clusters for incoming frames, so the 2068 * buffer is virtually contiguous. 2069 */ 2070 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 2071 2072 /* Allow the receive descriptor to continue using its mbuf. */ 2073 SIP_INIT_RXDESC(sc, i); 2074 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2075 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2076 #endif /* __NO_STRICT_ALIGNMENT */ 2077 2078 ifp->if_ipackets++; 2079 m->m_flags |= M_HASFCS; 2080 m->m_pkthdr.rcvif = ifp; 2081 m->m_pkthdr.len = m->m_len = len; 2082 2083 #if NBPFILTER > 0 2084 /* 2085 * Pass this up to any BPF listeners, but only 2086 * pass if up the stack if it's for us. 2087 */ 2088 if (ifp->if_bpf) 2089 bpf_mtap(ifp->if_bpf, m); 2090 #endif /* NBPFILTER > 0 */ 2091 2092 /* Pass it on. */ 2093 (*ifp->if_input)(ifp, m); 2094 } 2095 2096 /* Update the receive pointer. */ 2097 sc->sc_rxptr = i; 2098 } 2099 #endif /* DP83820 */ 2100 2101 /* 2102 * sip_tick: 2103 * 2104 * One second timer, used to tick the MII. 2105 */ 2106 void 2107 SIP_DECL(tick)(void *arg) 2108 { 2109 struct sip_softc *sc = arg; 2110 int s; 2111 2112 s = splnet(); 2113 mii_tick(&sc->sc_mii); 2114 splx(s); 2115 2116 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2117 } 2118 2119 /* 2120 * sip_reset: 2121 * 2122 * Perform a soft reset on the SiS 900. 2123 */ 2124 void 2125 SIP_DECL(reset)(struct sip_softc *sc) 2126 { 2127 bus_space_tag_t st = sc->sc_st; 2128 bus_space_handle_t sh = sc->sc_sh; 2129 int i; 2130 2131 bus_space_write_4(st, sh, SIP_IER, 0); 2132 bus_space_write_4(st, sh, SIP_IMR, 0); 2133 bus_space_write_4(st, sh, SIP_RFCR, 0); 2134 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2135 2136 for (i = 0; i < SIP_TIMEOUT; i++) { 2137 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2138 break; 2139 delay(2); 2140 } 2141 2142 if (i == SIP_TIMEOUT) 2143 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2144 2145 delay(1000); 2146 2147 #ifdef DP83820 2148 /* 2149 * Set the general purpose I/O bits. Do it here in case we 2150 * need to have GPIO set up to talk to the media interface. 2151 */ 2152 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2153 delay(1000); 2154 #endif /* DP83820 */ 2155 } 2156 2157 /* 2158 * sip_init: [ ifnet interface function ] 2159 * 2160 * Initialize the interface. Must be called at splnet(). 2161 */ 2162 int 2163 SIP_DECL(init)(struct ifnet *ifp) 2164 { 2165 struct sip_softc *sc = ifp->if_softc; 2166 bus_space_tag_t st = sc->sc_st; 2167 bus_space_handle_t sh = sc->sc_sh; 2168 struct sip_txsoft *txs; 2169 struct sip_rxsoft *rxs; 2170 struct sip_desc *sipd; 2171 #if defined(DP83820) 2172 u_int32_t reg; 2173 #endif 2174 int i, error = 0; 2175 2176 /* 2177 * Cancel any pending I/O. 2178 */ 2179 SIP_DECL(stop)(ifp, 0); 2180 2181 /* 2182 * Reset the chip to a known state. 2183 */ 2184 SIP_DECL(reset)(sc); 2185 2186 #if !defined(DP83820) 2187 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2188 /* 2189 * DP83815 manual, page 78: 2190 * 4.4 Recommended Registers Configuration 2191 * For optimum performance of the DP83815, version noted 2192 * as DP83815CVNG (SRR = 203h), the listed register 2193 * modifications must be followed in sequence... 2194 * 2195 * It's not clear if this should be 302h or 203h because that 2196 * chip name is listed as SRR 302h in the description of the 2197 * SRR register. However, my revision 302h DP83815 on the 2198 * Netgear FA311 purchased in 02/2001 needs these settings 2199 * to avoid tons of errors in AcceptPerfectMatch (non- 2200 * IFF_PROMISC) mode. I do not know if other revisions need 2201 * this set or not. [briggs -- 09 March 2001] 2202 * 2203 * Note that only the low-order 12 bits of 0xe4 are documented 2204 * and that this sets reserved bits in that register. 2205 */ 2206 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2207 2208 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2209 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2210 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2211 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2212 2213 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2214 } 2215 #endif /* ! DP83820 */ 2216 2217 /* 2218 * Initialize the transmit descriptor ring. 2219 */ 2220 for (i = 0; i < SIP_NTXDESC; i++) { 2221 sipd = &sc->sc_txdescs[i]; 2222 memset(sipd, 0, sizeof(struct sip_desc)); 2223 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2224 } 2225 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2226 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2227 sc->sc_txfree = SIP_NTXDESC; 2228 sc->sc_txnext = 0; 2229 sc->sc_txwin = 0; 2230 2231 /* 2232 * Initialize the transmit job descriptors. 2233 */ 2234 SIMPLEQ_INIT(&sc->sc_txfreeq); 2235 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2236 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2237 txs = &sc->sc_txsoft[i]; 2238 txs->txs_mbuf = NULL; 2239 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2240 } 2241 2242 /* 2243 * Initialize the receive descriptor and receive job 2244 * descriptor rings. 2245 */ 2246 for (i = 0; i < SIP_NRXDESC; i++) { 2247 rxs = &sc->sc_rxsoft[i]; 2248 if (rxs->rxs_mbuf == NULL) { 2249 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2250 printf("%s: unable to allocate or map rx " 2251 "buffer %d, error = %d\n", 2252 sc->sc_dev.dv_xname, i, error); 2253 /* 2254 * XXX Should attempt to run with fewer receive 2255 * XXX buffers instead of just failing. 2256 */ 2257 SIP_DECL(rxdrain)(sc); 2258 goto out; 2259 } 2260 } else 2261 SIP_INIT_RXDESC(sc, i); 2262 } 2263 sc->sc_rxptr = 0; 2264 #ifdef DP83820 2265 sc->sc_rxdiscard = 0; 2266 SIP_RXCHAIN_RESET(sc); 2267 #endif /* DP83820 */ 2268 2269 /* 2270 * Set the configuration register; it's already initialized 2271 * in sip_attach(). 2272 */ 2273 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2274 2275 /* 2276 * Initialize the prototype TXCFG register. 2277 */ 2278 #if defined(DP83820) 2279 sc->sc_txcfg = TXCFG_MXDMA_512; 2280 sc->sc_rxcfg = RXCFG_MXDMA_512; 2281 #else 2282 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2283 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2284 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & CFG_EDBMASTEN)) { 2285 sc->sc_txcfg = TXCFG_MXDMA_64; 2286 sc->sc_rxcfg = RXCFG_MXDMA_64; 2287 } else { 2288 sc->sc_txcfg = TXCFG_MXDMA_512; 2289 sc->sc_rxcfg = RXCFG_MXDMA_512; 2290 } 2291 #endif /* DP83820 */ 2292 2293 sc->sc_txcfg |= TXCFG_ATP | 2294 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2295 sc->sc_tx_drain_thresh; 2296 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2297 2298 /* 2299 * Initialize the receive drain threshold if we have never 2300 * done so. 2301 */ 2302 if (sc->sc_rx_drain_thresh == 0) { 2303 /* 2304 * XXX This value should be tuned. This is set to the 2305 * maximum of 248 bytes, and we may be able to improve 2306 * performance by decreasing it (although we should never 2307 * set this value lower than 2; 14 bytes are required to 2308 * filter the packet). 2309 */ 2310 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2311 } 2312 2313 /* 2314 * Initialize the prototype RXCFG register. 2315 */ 2316 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2317 #ifndef DP83820 2318 /* 2319 * Accept packets >1518 bytes (including FCS) so we can handle 2320 * 802.1q-tagged frames properly. 2321 */ 2322 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2323 sc->sc_rxcfg |= RXCFG_ALP; 2324 #endif 2325 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2326 2327 #ifdef DP83820 2328 /* 2329 * Initialize the VLAN/IP receive control register. 2330 * We enable checksum computation on all incoming 2331 * packets, and do not reject packets w/ bad checksums. 2332 */ 2333 reg = 0; 2334 if (ifp->if_capenable & 2335 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2336 reg |= VRCR_IPEN; 2337 if (sc->sc_ethercom.ec_nvlans != 0) 2338 reg |= VRCR_VTDEN|VRCR_VTREN; 2339 bus_space_write_4(st, sh, SIP_VRCR, reg); 2340 2341 /* 2342 * Initialize the VLAN/IP transmit control register. 2343 * We enable outgoing checksum computation on a 2344 * per-packet basis. 2345 */ 2346 reg = 0; 2347 if (ifp->if_capenable & 2348 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2349 reg |= VTCR_PPCHK; 2350 if (sc->sc_ethercom.ec_nvlans != 0) 2351 reg |= VTCR_VPPTI; 2352 bus_space_write_4(st, sh, SIP_VTCR, reg); 2353 2354 /* 2355 * If we're using VLANs, initialize the VLAN data register. 2356 * To understand why we bswap the VLAN Ethertype, see section 2357 * 4.2.36 of the DP83820 manual. 2358 */ 2359 if (sc->sc_ethercom.ec_nvlans != 0) 2360 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2361 #endif /* DP83820 */ 2362 2363 /* 2364 * Give the transmit and receive rings to the chip. 2365 */ 2366 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2367 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2368 2369 /* 2370 * Initialize the interrupt mask. 2371 */ 2372 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2373 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2374 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2375 2376 /* Set up the receive filter. */ 2377 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2378 2379 /* 2380 * Set the current media. Do this after initializing the prototype 2381 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2382 * control. 2383 */ 2384 mii_mediachg(&sc->sc_mii); 2385 2386 /* 2387 * Enable interrupts. 2388 */ 2389 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2390 2391 /* 2392 * Start the transmit and receive processes. 2393 */ 2394 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2395 2396 /* 2397 * Start the one second MII clock. 2398 */ 2399 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2400 2401 /* 2402 * ...all done! 2403 */ 2404 ifp->if_flags |= IFF_RUNNING; 2405 ifp->if_flags &= ~IFF_OACTIVE; 2406 2407 out: 2408 if (error) 2409 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2410 return (error); 2411 } 2412 2413 /* 2414 * sip_drain: 2415 * 2416 * Drain the receive queue. 2417 */ 2418 void 2419 SIP_DECL(rxdrain)(struct sip_softc *sc) 2420 { 2421 struct sip_rxsoft *rxs; 2422 int i; 2423 2424 for (i = 0; i < SIP_NRXDESC; i++) { 2425 rxs = &sc->sc_rxsoft[i]; 2426 if (rxs->rxs_mbuf != NULL) { 2427 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2428 m_freem(rxs->rxs_mbuf); 2429 rxs->rxs_mbuf = NULL; 2430 } 2431 } 2432 } 2433 2434 /* 2435 * sip_stop: [ ifnet interface function ] 2436 * 2437 * Stop transmission on the interface. 2438 */ 2439 void 2440 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2441 { 2442 struct sip_softc *sc = ifp->if_softc; 2443 bus_space_tag_t st = sc->sc_st; 2444 bus_space_handle_t sh = sc->sc_sh; 2445 struct sip_txsoft *txs; 2446 u_int32_t cmdsts = 0; /* DEBUG */ 2447 2448 /* 2449 * Stop the one second clock. 2450 */ 2451 callout_stop(&sc->sc_tick_ch); 2452 2453 /* Down the MII. */ 2454 mii_down(&sc->sc_mii); 2455 2456 /* 2457 * Disable interrupts. 2458 */ 2459 bus_space_write_4(st, sh, SIP_IER, 0); 2460 2461 /* 2462 * Stop receiver and transmitter. 2463 */ 2464 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2465 2466 /* 2467 * Release any queued transmit buffers. 2468 */ 2469 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2470 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2471 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2472 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2473 CMDSTS_INTR) == 0) 2474 printf("%s: sip_stop: last descriptor does not " 2475 "have INTR bit set\n", sc->sc_dev.dv_xname); 2476 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2477 #ifdef DIAGNOSTIC 2478 if (txs->txs_mbuf == NULL) { 2479 printf("%s: dirty txsoft with no mbuf chain\n", 2480 sc->sc_dev.dv_xname); 2481 panic("sip_stop"); 2482 } 2483 #endif 2484 cmdsts |= /* DEBUG */ 2485 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2486 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2487 m_freem(txs->txs_mbuf); 2488 txs->txs_mbuf = NULL; 2489 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2490 } 2491 2492 if (disable) 2493 SIP_DECL(rxdrain)(sc); 2494 2495 /* 2496 * Mark the interface down and cancel the watchdog timer. 2497 */ 2498 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2499 ifp->if_timer = 0; 2500 2501 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2502 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2503 printf("%s: sip_stop: no INTR bits set in dirty tx " 2504 "descriptors\n", sc->sc_dev.dv_xname); 2505 } 2506 2507 /* 2508 * sip_read_eeprom: 2509 * 2510 * Read data from the serial EEPROM. 2511 */ 2512 void 2513 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2514 u_int16_t *data) 2515 { 2516 bus_space_tag_t st = sc->sc_st; 2517 bus_space_handle_t sh = sc->sc_sh; 2518 u_int16_t reg; 2519 int i, x; 2520 2521 for (i = 0; i < wordcnt; i++) { 2522 /* Send CHIP SELECT. */ 2523 reg = EROMAR_EECS; 2524 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2525 2526 /* Shift in the READ opcode. */ 2527 for (x = 3; x > 0; x--) { 2528 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2529 reg |= EROMAR_EEDI; 2530 else 2531 reg &= ~EROMAR_EEDI; 2532 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2533 bus_space_write_4(st, sh, SIP_EROMAR, 2534 reg | EROMAR_EESK); 2535 delay(4); 2536 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2537 delay(4); 2538 } 2539 2540 /* Shift in address. */ 2541 for (x = 6; x > 0; x--) { 2542 if ((word + i) & (1 << (x - 1))) 2543 reg |= EROMAR_EEDI; 2544 else 2545 reg &= ~EROMAR_EEDI; 2546 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2547 bus_space_write_4(st, sh, SIP_EROMAR, 2548 reg | EROMAR_EESK); 2549 delay(4); 2550 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2551 delay(4); 2552 } 2553 2554 /* Shift out data. */ 2555 reg = EROMAR_EECS; 2556 data[i] = 0; 2557 for (x = 16; x > 0; x--) { 2558 bus_space_write_4(st, sh, SIP_EROMAR, 2559 reg | EROMAR_EESK); 2560 delay(4); 2561 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2562 data[i] |= (1 << (x - 1)); 2563 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2564 delay(4); 2565 } 2566 2567 /* Clear CHIP SELECT. */ 2568 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2569 delay(4); 2570 } 2571 } 2572 2573 /* 2574 * sip_add_rxbuf: 2575 * 2576 * Add a receive buffer to the indicated descriptor. 2577 */ 2578 int 2579 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2580 { 2581 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2582 struct mbuf *m; 2583 int error; 2584 2585 MGETHDR(m, M_DONTWAIT, MT_DATA); 2586 if (m == NULL) 2587 return (ENOBUFS); 2588 2589 MCLGET(m, M_DONTWAIT); 2590 if ((m->m_flags & M_EXT) == 0) { 2591 m_freem(m); 2592 return (ENOBUFS); 2593 } 2594 2595 #if defined(DP83820) 2596 m->m_len = SIP_RXBUF_LEN; 2597 #endif /* DP83820 */ 2598 2599 if (rxs->rxs_mbuf != NULL) 2600 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2601 2602 rxs->rxs_mbuf = m; 2603 2604 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2605 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2606 BUS_DMA_READ|BUS_DMA_NOWAIT); 2607 if (error) { 2608 printf("%s: can't load rx DMA map %d, error = %d\n", 2609 sc->sc_dev.dv_xname, idx, error); 2610 panic("sip_add_rxbuf"); /* XXX */ 2611 } 2612 2613 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2614 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2615 2616 SIP_INIT_RXDESC(sc, idx); 2617 2618 return (0); 2619 } 2620 2621 #if !defined(DP83820) 2622 /* 2623 * sip_sis900_set_filter: 2624 * 2625 * Set up the receive filter. 2626 */ 2627 void 2628 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2629 { 2630 bus_space_tag_t st = sc->sc_st; 2631 bus_space_handle_t sh = sc->sc_sh; 2632 struct ethercom *ec = &sc->sc_ethercom; 2633 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2634 struct ether_multi *enm; 2635 u_int8_t *cp; 2636 struct ether_multistep step; 2637 u_int32_t crc, mchash[16]; 2638 2639 /* 2640 * Initialize the prototype RFCR. 2641 */ 2642 sc->sc_rfcr = RFCR_RFEN; 2643 if (ifp->if_flags & IFF_BROADCAST) 2644 sc->sc_rfcr |= RFCR_AAB; 2645 if (ifp->if_flags & IFF_PROMISC) { 2646 sc->sc_rfcr |= RFCR_AAP; 2647 goto allmulti; 2648 } 2649 2650 /* 2651 * Set up the multicast address filter by passing all multicast 2652 * addresses through a CRC generator, and then using the high-order 2653 * 6 bits as an index into the 128 bit multicast hash table (only 2654 * the lower 16 bits of each 32 bit multicast hash register are 2655 * valid). The high order bits select the register, while the 2656 * rest of the bits select the bit within the register. 2657 */ 2658 2659 memset(mchash, 0, sizeof(mchash)); 2660 2661 ETHER_FIRST_MULTI(step, ec, enm); 2662 while (enm != NULL) { 2663 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2664 /* 2665 * We must listen to a range of multicast addresses. 2666 * For now, just accept all multicasts, rather than 2667 * trying to set only those filter bits needed to match 2668 * the range. (At this time, the only use of address 2669 * ranges is for IP multicast routing, for which the 2670 * range is big enough to require all bits set.) 2671 */ 2672 goto allmulti; 2673 } 2674 2675 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2676 2677 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2678 SIP_SIS900_REV(sc, SIS_REV_960) || 2679 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2680 /* Just want the 8 most significant bits. */ 2681 crc >>= 24; 2682 } else { 2683 /* Just want the 7 most significant bits. */ 2684 crc >>= 25; 2685 } 2686 2687 /* Set the corresponding bit in the hash table. */ 2688 mchash[crc >> 4] |= 1 << (crc & 0xf); 2689 2690 ETHER_NEXT_MULTI(step, enm); 2691 } 2692 2693 ifp->if_flags &= ~IFF_ALLMULTI; 2694 goto setit; 2695 2696 allmulti: 2697 ifp->if_flags |= IFF_ALLMULTI; 2698 sc->sc_rfcr |= RFCR_AAM; 2699 2700 setit: 2701 #define FILTER_EMIT(addr, data) \ 2702 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2703 delay(1); \ 2704 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2705 delay(1) 2706 2707 /* 2708 * Disable receive filter, and program the node address. 2709 */ 2710 cp = LLADDR(ifp->if_sadl); 2711 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2712 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2713 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2714 2715 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2716 /* 2717 * Program the multicast hash table. 2718 */ 2719 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2720 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2721 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2722 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2723 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2724 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2725 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2726 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2727 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2728 SIP_SIS900_REV(sc, SIS_REV_960) || 2729 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2730 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2731 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2732 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2733 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2734 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2735 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2736 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2737 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2738 } 2739 } 2740 #undef FILTER_EMIT 2741 2742 /* 2743 * Re-enable the receiver filter. 2744 */ 2745 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2746 } 2747 #endif /* ! DP83820 */ 2748 2749 /* 2750 * sip_dp83815_set_filter: 2751 * 2752 * Set up the receive filter. 2753 */ 2754 void 2755 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2756 { 2757 bus_space_tag_t st = sc->sc_st; 2758 bus_space_handle_t sh = sc->sc_sh; 2759 struct ethercom *ec = &sc->sc_ethercom; 2760 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2761 struct ether_multi *enm; 2762 u_int8_t *cp; 2763 struct ether_multistep step; 2764 u_int32_t crc, hash, slot, bit; 2765 #ifdef DP83820 2766 #define MCHASH_NWORDS 128 2767 #else 2768 #define MCHASH_NWORDS 32 2769 #endif /* DP83820 */ 2770 u_int16_t mchash[MCHASH_NWORDS]; 2771 int i; 2772 2773 /* 2774 * Initialize the prototype RFCR. 2775 * Enable the receive filter, and accept on 2776 * Perfect (destination address) Match 2777 * If IFF_BROADCAST, also accept all broadcast packets. 2778 * If IFF_PROMISC, accept all unicast packets (and later, set 2779 * IFF_ALLMULTI and accept all multicast, too). 2780 */ 2781 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2782 if (ifp->if_flags & IFF_BROADCAST) 2783 sc->sc_rfcr |= RFCR_AAB; 2784 if (ifp->if_flags & IFF_PROMISC) { 2785 sc->sc_rfcr |= RFCR_AAP; 2786 goto allmulti; 2787 } 2788 2789 #ifdef DP83820 2790 /* 2791 * Set up the DP83820 multicast address filter by passing all multicast 2792 * addresses through a CRC generator, and then using the high-order 2793 * 11 bits as an index into the 2048 bit multicast hash table. The 2794 * high-order 7 bits select the slot, while the low-order 4 bits 2795 * select the bit within the slot. Note that only the low 16-bits 2796 * of each filter word are used, and there are 128 filter words. 2797 */ 2798 #else 2799 /* 2800 * Set up the DP83815 multicast address filter by passing all multicast 2801 * addresses through a CRC generator, and then using the high-order 2802 * 9 bits as an index into the 512 bit multicast hash table. The 2803 * high-order 5 bits select the slot, while the low-order 4 bits 2804 * select the bit within the slot. Note that only the low 16-bits 2805 * of each filter word are used, and there are 32 filter words. 2806 */ 2807 #endif /* DP83820 */ 2808 2809 memset(mchash, 0, sizeof(mchash)); 2810 2811 ifp->if_flags &= ~IFF_ALLMULTI; 2812 ETHER_FIRST_MULTI(step, ec, enm); 2813 if (enm == NULL) 2814 goto setit; 2815 while (enm != NULL) { 2816 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2817 /* 2818 * We must listen to a range of multicast addresses. 2819 * For now, just accept all multicasts, rather than 2820 * trying to set only those filter bits needed to match 2821 * the range. (At this time, the only use of address 2822 * ranges is for IP multicast routing, for which the 2823 * range is big enough to require all bits set.) 2824 */ 2825 goto allmulti; 2826 } 2827 2828 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2829 2830 #ifdef DP83820 2831 /* Just want the 11 most significant bits. */ 2832 hash = crc >> 21; 2833 #else 2834 /* Just want the 9 most significant bits. */ 2835 hash = crc >> 23; 2836 #endif /* DP83820 */ 2837 2838 slot = hash >> 4; 2839 bit = hash & 0xf; 2840 2841 /* Set the corresponding bit in the hash table. */ 2842 mchash[slot] |= 1 << bit; 2843 2844 ETHER_NEXT_MULTI(step, enm); 2845 } 2846 sc->sc_rfcr |= RFCR_MHEN; 2847 goto setit; 2848 2849 allmulti: 2850 ifp->if_flags |= IFF_ALLMULTI; 2851 sc->sc_rfcr |= RFCR_AAM; 2852 2853 setit: 2854 #define FILTER_EMIT(addr, data) \ 2855 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2856 delay(1); \ 2857 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2858 delay(1) 2859 2860 /* 2861 * Disable receive filter, and program the node address. 2862 */ 2863 cp = LLADDR(ifp->if_sadl); 2864 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 2865 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 2866 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 2867 2868 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2869 /* 2870 * Program the multicast hash table. 2871 */ 2872 for (i = 0; i < MCHASH_NWORDS; i++) { 2873 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 2874 mchash[i]); 2875 } 2876 } 2877 #undef FILTER_EMIT 2878 #undef MCHASH_NWORDS 2879 2880 /* 2881 * Re-enable the receiver filter. 2882 */ 2883 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2884 } 2885 2886 #if defined(DP83820) 2887 /* 2888 * sip_dp83820_mii_readreg: [mii interface function] 2889 * 2890 * Read a PHY register on the MII of the DP83820. 2891 */ 2892 int 2893 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 2894 { 2895 struct sip_softc *sc = (void *) self; 2896 2897 if (sc->sc_cfg & CFG_TBI_EN) { 2898 bus_addr_t tbireg; 2899 int rv; 2900 2901 if (phy != 0) 2902 return (0); 2903 2904 switch (reg) { 2905 case MII_BMCR: tbireg = SIP_TBICR; break; 2906 case MII_BMSR: tbireg = SIP_TBISR; break; 2907 case MII_ANAR: tbireg = SIP_TANAR; break; 2908 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 2909 case MII_ANER: tbireg = SIP_TANER; break; 2910 case MII_EXTSR: 2911 /* 2912 * Don't even bother reading the TESR register. 2913 * The manual documents that the device has 2914 * 1000baseX full/half capability, but the 2915 * register itself seems read back 0 on some 2916 * boards. Just hard-code the result. 2917 */ 2918 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 2919 2920 default: 2921 return (0); 2922 } 2923 2924 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 2925 if (tbireg == SIP_TBISR) { 2926 /* LINK and ACOMP are switched! */ 2927 int val = rv; 2928 2929 rv = 0; 2930 if (val & TBISR_MR_LINK_STATUS) 2931 rv |= BMSR_LINK; 2932 if (val & TBISR_MR_AN_COMPLETE) 2933 rv |= BMSR_ACOMP; 2934 2935 /* 2936 * The manual claims this register reads back 0 2937 * on hard and soft reset. But we want to let 2938 * the gentbi driver know that we support auto- 2939 * negotiation, so hard-code this bit in the 2940 * result. 2941 */ 2942 rv |= BMSR_ANEG | BMSR_EXTSTAT; 2943 } 2944 2945 return (rv); 2946 } 2947 2948 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 2949 phy, reg)); 2950 } 2951 2952 /* 2953 * sip_dp83820_mii_writereg: [mii interface function] 2954 * 2955 * Write a PHY register on the MII of the DP83820. 2956 */ 2957 void 2958 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 2959 { 2960 struct sip_softc *sc = (void *) self; 2961 2962 if (sc->sc_cfg & CFG_TBI_EN) { 2963 bus_addr_t tbireg; 2964 2965 if (phy != 0) 2966 return; 2967 2968 switch (reg) { 2969 case MII_BMCR: tbireg = SIP_TBICR; break; 2970 case MII_ANAR: tbireg = SIP_TANAR; break; 2971 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 2972 default: 2973 return; 2974 } 2975 2976 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 2977 return; 2978 } 2979 2980 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 2981 phy, reg, val); 2982 } 2983 2984 /* 2985 * sip_dp83815_mii_statchg: [mii interface function] 2986 * 2987 * Callback from MII layer when media changes. 2988 */ 2989 void 2990 SIP_DECL(dp83820_mii_statchg)(struct device *self) 2991 { 2992 struct sip_softc *sc = (struct sip_softc *) self; 2993 u_int32_t cfg; 2994 2995 /* 2996 * Update TXCFG for full-duplex operation. 2997 */ 2998 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2999 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3000 else 3001 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3002 3003 /* 3004 * Update RXCFG for full-duplex or loopback. 3005 */ 3006 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3007 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3008 sc->sc_rxcfg |= RXCFG_ATX; 3009 else 3010 sc->sc_rxcfg &= ~RXCFG_ATX; 3011 3012 /* 3013 * Update CFG for MII/GMII. 3014 */ 3015 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3016 cfg = sc->sc_cfg | CFG_MODE_1000; 3017 else 3018 cfg = sc->sc_cfg; 3019 3020 /* 3021 * XXX 802.3x flow control. 3022 */ 3023 3024 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3025 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3026 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3027 } 3028 #endif /* ! DP83820 */ 3029 3030 /* 3031 * sip_mii_bitbang_read: [mii bit-bang interface function] 3032 * 3033 * Read the MII serial port for the MII bit-bang module. 3034 */ 3035 u_int32_t 3036 SIP_DECL(mii_bitbang_read)(struct device *self) 3037 { 3038 struct sip_softc *sc = (void *) self; 3039 3040 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3041 } 3042 3043 /* 3044 * sip_mii_bitbang_write: [mii big-bang interface function] 3045 * 3046 * Write the MII serial port for the MII bit-bang module. 3047 */ 3048 void 3049 SIP_DECL(mii_bitbang_write)(struct device *self, u_int32_t val) 3050 { 3051 struct sip_softc *sc = (void *) self; 3052 3053 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3054 } 3055 3056 #ifndef DP83820 3057 /* 3058 * sip_sis900_mii_readreg: [mii interface function] 3059 * 3060 * Read a PHY register on the MII. 3061 */ 3062 int 3063 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 3064 { 3065 struct sip_softc *sc = (struct sip_softc *) self; 3066 u_int32_t enphy; 3067 3068 /* 3069 * The PHY of recent SiS chipsets is accessed through bitbang 3070 * operations. 3071 */ 3072 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 3073 sc->sc_rev >= SIS_REV_635) 3074 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3075 phy, reg)); 3076 3077 /* 3078 * The SiS 900 has only an internal PHY on the MII. Only allow 3079 * MII address 0. 3080 */ 3081 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3082 return (0); 3083 3084 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3085 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3086 ENPHY_RWCMD | ENPHY_ACCESS); 3087 do { 3088 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3089 } while (enphy & ENPHY_ACCESS); 3090 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3091 } 3092 3093 /* 3094 * sip_sis900_mii_writereg: [mii interface function] 3095 * 3096 * Write a PHY register on the MII. 3097 */ 3098 void 3099 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 3100 { 3101 struct sip_softc *sc = (struct sip_softc *) self; 3102 u_int32_t enphy; 3103 3104 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && 3105 sc->sc_rev >= SIS_REV_635) { 3106 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3107 phy, reg, val); 3108 return; 3109 } 3110 3111 /* 3112 * The SiS 900 has only an internal PHY on the MII. Only allow 3113 * MII address 0. 3114 */ 3115 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3116 return; 3117 3118 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3119 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3120 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3121 do { 3122 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3123 } while (enphy & ENPHY_ACCESS); 3124 } 3125 3126 /* 3127 * sip_sis900_mii_statchg: [mii interface function] 3128 * 3129 * Callback from MII layer when media changes. 3130 */ 3131 void 3132 SIP_DECL(sis900_mii_statchg)(struct device *self) 3133 { 3134 struct sip_softc *sc = (struct sip_softc *) self; 3135 u_int32_t flowctl; 3136 3137 /* 3138 * Update TXCFG for full-duplex operation. 3139 */ 3140 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3141 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3142 else 3143 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3144 3145 /* 3146 * Update RXCFG for full-duplex or loopback. 3147 */ 3148 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3149 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3150 sc->sc_rxcfg |= RXCFG_ATX; 3151 else 3152 sc->sc_rxcfg &= ~RXCFG_ATX; 3153 3154 /* 3155 * Update IMR for use of 802.3x flow control. 3156 */ 3157 if ((sc->sc_mii.mii_media_active & IFM_FLOW) != 0) { 3158 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3159 flowctl = FLOWCTL_FLOWEN; 3160 } else { 3161 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3162 flowctl = 0; 3163 } 3164 3165 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3166 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3167 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3168 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3169 } 3170 3171 /* 3172 * sip_dp83815_mii_readreg: [mii interface function] 3173 * 3174 * Read a PHY register on the MII. 3175 */ 3176 int 3177 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 3178 { 3179 struct sip_softc *sc = (struct sip_softc *) self; 3180 u_int32_t val; 3181 3182 /* 3183 * The DP83815 only has an internal PHY. Only allow 3184 * MII address 0. 3185 */ 3186 if (phy != 0) 3187 return (0); 3188 3189 /* 3190 * Apparently, after a reset, the DP83815 can take a while 3191 * to respond. During this recovery period, the BMSR returns 3192 * a value of 0. Catch this -- it's not supposed to happen 3193 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3194 * PHY to come back to life. 3195 * 3196 * This works out because the BMSR is the first register 3197 * read during the PHY probe process. 3198 */ 3199 do { 3200 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3201 } while (reg == MII_BMSR && val == 0); 3202 3203 return (val & 0xffff); 3204 } 3205 3206 /* 3207 * sip_dp83815_mii_writereg: [mii interface function] 3208 * 3209 * Write a PHY register to the MII. 3210 */ 3211 void 3212 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3213 { 3214 struct sip_softc *sc = (struct sip_softc *) self; 3215 3216 /* 3217 * The DP83815 only has an internal PHY. Only allow 3218 * MII address 0. 3219 */ 3220 if (phy != 0) 3221 return; 3222 3223 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3224 } 3225 3226 /* 3227 * sip_dp83815_mii_statchg: [mii interface function] 3228 * 3229 * Callback from MII layer when media changes. 3230 */ 3231 void 3232 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3233 { 3234 struct sip_softc *sc = (struct sip_softc *) self; 3235 3236 /* 3237 * Update TXCFG for full-duplex operation. 3238 */ 3239 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3240 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3241 else 3242 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3243 3244 /* 3245 * Update RXCFG for full-duplex or loopback. 3246 */ 3247 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3248 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3249 sc->sc_rxcfg |= RXCFG_ATX; 3250 else 3251 sc->sc_rxcfg &= ~RXCFG_ATX; 3252 3253 /* 3254 * XXX 802.3x flow control. 3255 */ 3256 3257 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3258 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3259 3260 /* 3261 * Some DP83815s experience problems when used with short 3262 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3263 * sequence adjusts the DSP's signal attenuation to fix the 3264 * problem. 3265 */ 3266 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3267 uint32_t reg; 3268 3269 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3270 3271 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3272 reg &= 0x0fff; 3273 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3274 delay(100); 3275 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3276 reg &= 0x00ff; 3277 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3278 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3279 0x00e8); 3280 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3281 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3282 reg | 0x20); 3283 } 3284 3285 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3286 } 3287 } 3288 #endif /* DP83820 */ 3289 3290 #if defined(DP83820) 3291 void 3292 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3293 const struct pci_attach_args *pa, u_int8_t *enaddr) 3294 { 3295 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3296 u_int8_t cksum, *e, match; 3297 int i; 3298 3299 /* 3300 * EEPROM data format for the DP83820 can be found in 3301 * the DP83820 manual, section 4.2.4. 3302 */ 3303 3304 SIP_DECL(read_eeprom)(sc, 0, 3305 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3306 3307 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3308 match = ~(match - 1); 3309 3310 cksum = 0x55; 3311 e = (u_int8_t *) eeprom_data; 3312 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3313 cksum += *e++; 3314 3315 if (cksum != match) 3316 printf("%s: Checksum (%x) mismatch (%x)", 3317 sc->sc_dev.dv_xname, cksum, match); 3318 3319 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3320 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3321 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3322 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3323 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3324 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3325 } 3326 #else /* ! DP83820 */ 3327 static void 3328 SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc) 3329 { 3330 int i; 3331 3332 /* 3333 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3334 * a reason, but I don't know it. 3335 */ 3336 for (i = 0; i < 10; i++) 3337 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3338 } 3339 3340 void 3341 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3342 const struct pci_attach_args *pa, u_int8_t *enaddr) 3343 { 3344 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3345 3346 switch (sc->sc_rev) { 3347 case SIS_REV_630S: 3348 case SIS_REV_630E: 3349 case SIS_REV_630EA1: 3350 case SIS_REV_630ET: 3351 case SIS_REV_635: 3352 /* 3353 * The MAC address for the on-board Ethernet of 3354 * the SiS 630 chipset is in the NVRAM. Kick 3355 * the chip into re-loading it from NVRAM, and 3356 * read the MAC address out of the filter registers. 3357 */ 3358 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3359 3360 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3361 RFCR_RFADDR_NODE0); 3362 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3363 0xffff; 3364 3365 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3366 RFCR_RFADDR_NODE2); 3367 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3368 0xffff; 3369 3370 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3371 RFCR_RFADDR_NODE4); 3372 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3373 0xffff; 3374 break; 3375 3376 case SIS_REV_960: 3377 { 3378 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3379 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3380 3381 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3382 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3383 3384 int waittime, i; 3385 3386 /* Allow to read EEPROM from LAN. It is shared 3387 * between a 1394 controller and the NIC and each 3388 * time we access it, we need to set SIS_EECMD_REQ. 3389 */ 3390 SIS_SET_EROMAR(sc, EROMAR_REQ); 3391 3392 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3393 /* Force EEPROM to idle state. */ 3394 3395 /* 3396 * XXX-cube This is ugly. I'll look for docs about it. 3397 */ 3398 SIS_SET_EROMAR(sc, EROMAR_EECS); 3399 SIP_DECL(sis900_eeprom_delay)(sc); 3400 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3401 SIS_SET_EROMAR(sc, EROMAR_EESK); 3402 SIP_DECL(sis900_eeprom_delay)(sc); 3403 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3404 SIP_DECL(sis900_eeprom_delay)(sc); 3405 } 3406 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3407 SIP_DECL(sis900_eeprom_delay)(sc); 3408 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3409 3410 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3411 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3412 sizeof(myea) / sizeof(myea[0]), myea); 3413 break; 3414 } 3415 DELAY(1); 3416 } 3417 3418 /* 3419 * Set SIS_EECTL_CLK to high, so a other master 3420 * can operate on the i2c bus. 3421 */ 3422 SIS_SET_EROMAR(sc, EROMAR_EESK); 3423 3424 /* Refuse EEPROM access by LAN */ 3425 SIS_SET_EROMAR(sc, EROMAR_DONE); 3426 } break; 3427 3428 default: 3429 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3430 sizeof(myea) / sizeof(myea[0]), myea); 3431 } 3432 3433 enaddr[0] = myea[0] & 0xff; 3434 enaddr[1] = myea[0] >> 8; 3435 enaddr[2] = myea[1] & 0xff; 3436 enaddr[3] = myea[1] >> 8; 3437 enaddr[4] = myea[2] & 0xff; 3438 enaddr[5] = myea[2] >> 8; 3439 } 3440 3441 /* Table and macro to bit-reverse an octet. */ 3442 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3443 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3444 3445 void 3446 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3447 const struct pci_attach_args *pa, u_int8_t *enaddr) 3448 { 3449 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3450 u_int8_t cksum, *e, match; 3451 int i; 3452 3453 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3454 sizeof(eeprom_data[0]), eeprom_data); 3455 3456 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3457 match = ~(match - 1); 3458 3459 cksum = 0x55; 3460 e = (u_int8_t *) eeprom_data; 3461 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3462 cksum += *e++; 3463 } 3464 if (cksum != match) { 3465 printf("%s: Checksum (%x) mismatch (%x)", 3466 sc->sc_dev.dv_xname, cksum, match); 3467 } 3468 3469 /* 3470 * Unrolled because it makes slightly more sense this way. 3471 * The DP83815 stores the MAC address in bit 0 of word 6 3472 * through bit 15 of word 8. 3473 */ 3474 ea = &eeprom_data[6]; 3475 enaddr[0] = ((*ea & 0x1) << 7); 3476 ea++; 3477 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3478 enaddr[1] = ((*ea & 0x1FE) >> 1); 3479 enaddr[2] = ((*ea & 0x1) << 7); 3480 ea++; 3481 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3482 enaddr[3] = ((*ea & 0x1FE) >> 1); 3483 enaddr[4] = ((*ea & 0x1) << 7); 3484 ea++; 3485 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3486 enaddr[5] = ((*ea & 0x1FE) >> 1); 3487 3488 /* 3489 * In case that's not weird enough, we also need to reverse 3490 * the bits in each byte. This all actually makes more sense 3491 * if you think about the EEPROM storage as an array of bits 3492 * being shifted into bytes, but that's not how we're looking 3493 * at it here... 3494 */ 3495 for (i = 0; i < 6 ;i++) 3496 enaddr[i] = bbr(enaddr[i]); 3497 } 3498 #endif /* DP83820 */ 3499 3500 /* 3501 * sip_mediastatus: [ifmedia interface function] 3502 * 3503 * Get the current interface media status. 3504 */ 3505 void 3506 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3507 { 3508 struct sip_softc *sc = ifp->if_softc; 3509 3510 mii_pollstat(&sc->sc_mii); 3511 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3512 ifmr->ifm_active = sc->sc_mii.mii_media_active; 3513 } 3514 3515 /* 3516 * sip_mediachange: [ifmedia interface function] 3517 * 3518 * Set hardware to newly-selected media. 3519 */ 3520 int 3521 SIP_DECL(mediachange)(struct ifnet *ifp) 3522 { 3523 struct sip_softc *sc = ifp->if_softc; 3524 3525 if (ifp->if_flags & IFF_UP) 3526 mii_mediachg(&sc->sc_mii); 3527 return (0); 3528 } 3529
Indexes created Tue Sep 30 11:09:46 GMT 2025