if_sip.c revision 1.93
1 /* $NetBSD: if_sip.c,v 1.93 2004/05/15 22:26:49 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.93 2004/05/15 22:26:49 thorpej Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <machine/bus.h> 116 #include <machine/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/mii_bitbang.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/pci/if_sipreg.h> 128 129 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 130 #define SIP_DECL(x) __CONCAT(gsip_,x) 131 #else /* SiS900 and DP83815 */ 132 #define SIP_DECL(x) __CONCAT(sip_,x) 133 #endif 134 135 #define SIP_STR(x) __STRING(SIP_DECL(x)) 136 137 /* 138 * Transmit descriptor list size. This is arbitrary, but allocate 139 * enough descriptors for 128 pending transmissions, and 8 segments 140 * per packet (64 for DP83820 for jumbo frames). 141 * 142 * This MUST work out to a power of 2. 143 */ 144 #ifdef DP83820 145 #define SIP_NTXSEGS 64 146 #define SIP_NTXSEGS_ALLOC 16 147 #else 148 #define SIP_NTXSEGS 16 149 #define SIP_NTXSEGS_ALLOC 8 150 #endif 151 152 #define SIP_TXQUEUELEN 256 153 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 154 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 155 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 156 157 #if defined(DP83820) 158 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 159 #else 160 #define TX_DMAMAP_SIZE MCLBYTES 161 #endif 162 163 /* 164 * Receive descriptor list size. We have one Rx buffer per incoming 165 * packet, so this logic is a little simpler. 166 * 167 * Actually, on the DP83820, we allow the packet to consume more than 168 * one buffer, in order to support jumbo Ethernet frames. In that 169 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 170 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 171 * so we'd better be quick about handling receive interrupts. 172 */ 173 #if defined(DP83820) 174 #define SIP_NRXDESC 256 175 #else 176 #define SIP_NRXDESC 128 177 #endif /* DP83820 */ 178 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 179 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 180 181 /* 182 * Control structures are DMA'd to the SiS900 chip. We allocate them in 183 * a single clump that maps to a single DMA segment to make several things 184 * easier. 185 */ 186 struct sip_control_data { 187 /* 188 * The transmit descriptors. 189 */ 190 struct sip_desc scd_txdescs[SIP_NTXDESC]; 191 192 /* 193 * The receive descriptors. 194 */ 195 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 196 }; 197 198 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 199 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 200 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 201 202 /* 203 * Software state for transmit jobs. 204 */ 205 struct sip_txsoft { 206 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 207 bus_dmamap_t txs_dmamap; /* our DMA map */ 208 int txs_firstdesc; /* first descriptor in packet */ 209 int txs_lastdesc; /* last descriptor in packet */ 210 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 211 }; 212 213 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 214 215 /* 216 * Software state for receive jobs. 217 */ 218 struct sip_rxsoft { 219 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 220 bus_dmamap_t rxs_dmamap; /* our DMA map */ 221 }; 222 223 /* 224 * Software state per device. 225 */ 226 struct sip_softc { 227 struct device sc_dev; /* generic device information */ 228 bus_space_tag_t sc_st; /* bus space tag */ 229 bus_space_handle_t sc_sh; /* bus space handle */ 230 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 231 struct ethercom sc_ethercom; /* ethernet common data */ 232 void *sc_sdhook; /* shutdown hook */ 233 234 const struct sip_product *sc_model; /* which model are we? */ 235 int sc_rev; /* chip revision */ 236 237 void *sc_ih; /* interrupt cookie */ 238 239 struct mii_data sc_mii; /* MII/media information */ 240 241 struct callout sc_tick_ch; /* tick callout */ 242 243 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 244 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 245 246 /* 247 * Software state for transmit and receive descriptors. 248 */ 249 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 250 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 251 252 /* 253 * Control data structures. 254 */ 255 struct sip_control_data *sc_control_data; 256 #define sc_txdescs sc_control_data->scd_txdescs 257 #define sc_rxdescs sc_control_data->scd_rxdescs 258 259 #ifdef SIP_EVENT_COUNTERS 260 /* 261 * Event counters. 262 */ 263 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 264 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 265 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 266 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 267 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 268 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 269 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 270 #ifdef DP83820 271 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 272 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 273 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 274 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 275 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 276 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 277 #endif /* DP83820 */ 278 #endif /* SIP_EVENT_COUNTERS */ 279 280 u_int32_t sc_txcfg; /* prototype TXCFG register */ 281 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 282 u_int32_t sc_imr; /* prototype IMR register */ 283 u_int32_t sc_rfcr; /* prototype RFCR register */ 284 285 u_int32_t sc_cfg; /* prototype CFG register */ 286 287 #ifdef DP83820 288 u_int32_t sc_gpior; /* prototype GPIOR register */ 289 #endif /* DP83820 */ 290 291 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 292 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 293 294 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 295 296 int sc_flowflags; /* 802.3x flow control flags */ 297 #ifdef DP83820 298 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 299 #else 300 int sc_paused; /* paused indication */ 301 #endif 302 303 int sc_txfree; /* number of free Tx descriptors */ 304 int sc_txnext; /* next ready Tx descriptor */ 305 int sc_txwin; /* Tx descriptors since last intr */ 306 307 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 308 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 309 310 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 311 #if defined(DP83820) 312 int sc_rxdiscard; 313 int sc_rxlen; 314 struct mbuf *sc_rxhead; 315 struct mbuf *sc_rxtail; 316 struct mbuf **sc_rxtailp; 317 #endif /* DP83820 */ 318 319 #if NRND > 0 320 rndsource_element_t rnd_source; /* random source */ 321 #endif 322 }; 323 324 #ifdef DP83820 325 #define SIP_RXCHAIN_RESET(sc) \ 326 do { \ 327 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 328 *(sc)->sc_rxtailp = NULL; \ 329 (sc)->sc_rxlen = 0; \ 330 } while (/*CONSTCOND*/0) 331 332 #define SIP_RXCHAIN_LINK(sc, m) \ 333 do { \ 334 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 335 (sc)->sc_rxtailp = &(m)->m_next; \ 336 } while (/*CONSTCOND*/0) 337 #endif /* DP83820 */ 338 339 #ifdef SIP_EVENT_COUNTERS 340 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 341 #else 342 #define SIP_EVCNT_INCR(ev) /* nothing */ 343 #endif 344 345 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 346 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 347 348 #define SIP_CDTXSYNC(sc, x, n, ops) \ 349 do { \ 350 int __x, __n; \ 351 \ 352 __x = (x); \ 353 __n = (n); \ 354 \ 355 /* If it will wrap around, sync to the end of the ring. */ \ 356 if ((__x + __n) > SIP_NTXDESC) { \ 357 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 358 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 359 (SIP_NTXDESC - __x), (ops)); \ 360 __n -= (SIP_NTXDESC - __x); \ 361 __x = 0; \ 362 } \ 363 \ 364 /* Now sync whatever is left. */ \ 365 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 366 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 367 } while (0) 368 369 #define SIP_CDRXSYNC(sc, x, ops) \ 370 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 371 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 372 373 #ifdef DP83820 374 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 375 #define SIP_RXBUF_LEN (MCLBYTES - 8) 376 #else 377 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 378 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 379 #endif 380 #define SIP_INIT_RXDESC(sc, x) \ 381 do { \ 382 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 383 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 384 \ 385 __sipd->sipd_link = \ 386 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 387 __sipd->sipd_bufptr = \ 388 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 389 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 390 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 391 SIP_INIT_RXDESC_EXTSTS \ 392 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 393 } while (0) 394 395 #define SIP_CHIP_VERS(sc, v, p, r) \ 396 ((sc)->sc_model->sip_vendor == (v) && \ 397 (sc)->sc_model->sip_product == (p) && \ 398 (sc)->sc_rev == (r)) 399 400 #define SIP_CHIP_MODEL(sc, v, p) \ 401 ((sc)->sc_model->sip_vendor == (v) && \ 402 (sc)->sc_model->sip_product == (p)) 403 404 #if !defined(DP83820) 405 #define SIP_SIS900_REV(sc, rev) \ 406 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 407 #endif 408 409 #define SIP_TIMEOUT 1000 410 411 void SIP_DECL(start)(struct ifnet *); 412 void SIP_DECL(watchdog)(struct ifnet *); 413 int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 414 int SIP_DECL(init)(struct ifnet *); 415 void SIP_DECL(stop)(struct ifnet *, int); 416 417 void SIP_DECL(shutdown)(void *); 418 419 void SIP_DECL(reset)(struct sip_softc *); 420 void SIP_DECL(rxdrain)(struct sip_softc *); 421 int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 422 void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, u_int16_t *); 423 void SIP_DECL(tick)(void *); 424 425 #if !defined(DP83820) 426 void SIP_DECL(sis900_set_filter)(struct sip_softc *); 427 #endif /* ! DP83820 */ 428 void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 429 430 #if defined(DP83820) 431 void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 432 const struct pci_attach_args *, u_int8_t *); 433 #else 434 static void SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc); 435 void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 436 const struct pci_attach_args *, u_int8_t *); 437 void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 438 const struct pci_attach_args *, u_int8_t *); 439 #endif /* DP83820 */ 440 441 int SIP_DECL(intr)(void *); 442 void SIP_DECL(txintr)(struct sip_softc *); 443 void SIP_DECL(rxintr)(struct sip_softc *); 444 445 #if defined(DP83820) 446 int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 447 void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 448 void SIP_DECL(dp83820_mii_statchg)(struct device *); 449 #else 450 int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 451 void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 452 void SIP_DECL(sis900_mii_statchg)(struct device *); 453 454 int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 455 void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 456 void SIP_DECL(dp83815_mii_statchg)(struct device *); 457 #endif /* DP83820 */ 458 459 int SIP_DECL(mediachange)(struct ifnet *); 460 void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 461 462 int SIP_DECL(match)(struct device *, struct cfdata *, void *); 463 void SIP_DECL(attach)(struct device *, struct device *, void *); 464 465 int SIP_DECL(copy_small) = 0; 466 467 #ifdef DP83820 468 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 469 gsip_match, gsip_attach, NULL, NULL); 470 #else 471 CFATTACH_DECL(sip, sizeof(struct sip_softc), 472 sip_match, sip_attach, NULL, NULL); 473 #endif 474 475 /* 476 * Descriptions of the variants of the SiS900. 477 */ 478 struct sip_variant { 479 int (*sipv_mii_readreg)(struct device *, int, int); 480 void (*sipv_mii_writereg)(struct device *, int, int, int); 481 void (*sipv_mii_statchg)(struct device *); 482 void (*sipv_set_filter)(struct sip_softc *); 483 void (*sipv_read_macaddr)(struct sip_softc *, 484 const struct pci_attach_args *, u_int8_t *); 485 }; 486 487 u_int32_t SIP_DECL(mii_bitbang_read)(struct device *); 488 void SIP_DECL(mii_bitbang_write)(struct device *, u_int32_t); 489 490 const struct mii_bitbang_ops SIP_DECL(mii_bitbang_ops) = { 491 SIP_DECL(mii_bitbang_read), 492 SIP_DECL(mii_bitbang_write), 493 { 494 EROMAR_MDIO, /* MII_BIT_MDO */ 495 EROMAR_MDIO, /* MII_BIT_MDI */ 496 EROMAR_MDC, /* MII_BIT_MDC */ 497 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 498 0, /* MII_BIT_DIR_PHY_HOST */ 499 } 500 }; 501 502 #if defined(DP83820) 503 const struct sip_variant SIP_DECL(variant_dp83820) = { 504 SIP_DECL(dp83820_mii_readreg), 505 SIP_DECL(dp83820_mii_writereg), 506 SIP_DECL(dp83820_mii_statchg), 507 SIP_DECL(dp83815_set_filter), 508 SIP_DECL(dp83820_read_macaddr), 509 }; 510 #else 511 const struct sip_variant SIP_DECL(variant_sis900) = { 512 SIP_DECL(sis900_mii_readreg), 513 SIP_DECL(sis900_mii_writereg), 514 SIP_DECL(sis900_mii_statchg), 515 SIP_DECL(sis900_set_filter), 516 SIP_DECL(sis900_read_macaddr), 517 }; 518 519 const struct sip_variant SIP_DECL(variant_dp83815) = { 520 SIP_DECL(dp83815_mii_readreg), 521 SIP_DECL(dp83815_mii_writereg), 522 SIP_DECL(dp83815_mii_statchg), 523 SIP_DECL(dp83815_set_filter), 524 SIP_DECL(dp83815_read_macaddr), 525 }; 526 #endif /* DP83820 */ 527 528 /* 529 * Devices supported by this driver. 530 */ 531 const struct sip_product { 532 pci_vendor_id_t sip_vendor; 533 pci_product_id_t sip_product; 534 const char *sip_name; 535 const struct sip_variant *sip_variant; 536 } SIP_DECL(products)[] = { 537 #if defined(DP83820) 538 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 539 "NatSemi DP83820 Gigabit Ethernet", 540 &SIP_DECL(variant_dp83820) }, 541 #else 542 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 543 "SiS 900 10/100 Ethernet", 544 &SIP_DECL(variant_sis900) }, 545 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 546 "SiS 7016 10/100 Ethernet", 547 &SIP_DECL(variant_sis900) }, 548 549 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 550 "NatSemi DP83815 10/100 Ethernet", 551 &SIP_DECL(variant_dp83815) }, 552 #endif /* DP83820 */ 553 554 { 0, 0, 555 NULL, 556 NULL }, 557 }; 558 559 static const struct sip_product * 560 SIP_DECL(lookup)(const struct pci_attach_args *pa) 561 { 562 const struct sip_product *sip; 563 564 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 565 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 566 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 567 return (sip); 568 } 569 return (NULL); 570 } 571 572 #ifdef DP83820 573 /* 574 * I really hate stupid hardware vendors. There's a bit in the EEPROM 575 * which indicates if the card can do 64-bit data transfers. Unfortunately, 576 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 577 * which means we try to use 64-bit data transfers on those cards if we 578 * happen to be plugged into a 32-bit slot. 579 * 580 * What we do is use this table of cards known to be 64-bit cards. If 581 * you have a 64-bit card who's subsystem ID is not listed in this table, 582 * send the output of "pcictl dump ..." of the device to me so that your 583 * card will use the 64-bit data path when plugged into a 64-bit slot. 584 * 585 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 586 * June 30, 2002 587 */ 588 static int 589 SIP_DECL(check_64bit)(const struct pci_attach_args *pa) 590 { 591 static const struct { 592 pci_vendor_id_t c64_vendor; 593 pci_product_id_t c64_product; 594 } card64[] = { 595 /* Asante GigaNIX */ 596 { 0x128a, 0x0002 }, 597 598 /* Accton EN1407-T, Planex GN-1000TE */ 599 { 0x1113, 0x1407 }, 600 601 /* Netgear GA-621 */ 602 { 0x1385, 0x621a }, 603 604 /* SMC EZ Card */ 605 { 0x10b8, 0x9462 }, 606 607 { 0, 0} 608 }; 609 pcireg_t subsys; 610 int i; 611 612 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 613 614 for (i = 0; card64[i].c64_vendor != 0; i++) { 615 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 616 PCI_PRODUCT(subsys) == card64[i].c64_product) 617 return (1); 618 } 619 620 return (0); 621 } 622 #endif /* DP83820 */ 623 624 int 625 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 626 { 627 struct pci_attach_args *pa = aux; 628 629 if (SIP_DECL(lookup)(pa) != NULL) 630 return (1); 631 632 return (0); 633 } 634 635 void 636 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 637 { 638 struct sip_softc *sc = (struct sip_softc *) self; 639 struct pci_attach_args *pa = aux; 640 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 641 pci_chipset_tag_t pc = pa->pa_pc; 642 pci_intr_handle_t ih; 643 const char *intrstr = NULL; 644 bus_space_tag_t iot, memt; 645 bus_space_handle_t ioh, memh; 646 bus_dma_segment_t seg; 647 int ioh_valid, memh_valid; 648 int i, rseg, error; 649 const struct sip_product *sip; 650 pcireg_t pmode; 651 u_int8_t enaddr[ETHER_ADDR_LEN]; 652 int pmreg; 653 #ifdef DP83820 654 pcireg_t memtype; 655 u_int32_t reg; 656 #endif /* DP83820 */ 657 658 callout_init(&sc->sc_tick_ch); 659 660 sip = SIP_DECL(lookup)(pa); 661 if (sip == NULL) { 662 printf("\n"); 663 panic(SIP_STR(attach) ": impossible"); 664 } 665 sc->sc_rev = PCI_REVISION(pa->pa_class); 666 667 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 668 669 sc->sc_model = sip; 670 671 /* 672 * XXX Work-around broken PXE firmware on some boards. 673 * 674 * The DP83815 shares an address decoder with the MEM BAR 675 * and the ROM BAR. Make sure the ROM BAR is disabled, 676 * so that memory mapped access works. 677 */ 678 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 679 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 680 ~PCI_MAPREG_ROM_ENABLE); 681 682 /* 683 * Map the device. 684 */ 685 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 686 PCI_MAPREG_TYPE_IO, 0, 687 &iot, &ioh, NULL, NULL) == 0); 688 #ifdef DP83820 689 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 690 switch (memtype) { 691 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 692 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 693 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 694 memtype, 0, &memt, &memh, NULL, NULL) == 0); 695 break; 696 default: 697 memh_valid = 0; 698 } 699 #else 700 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 701 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 702 &memt, &memh, NULL, NULL) == 0); 703 #endif /* DP83820 */ 704 705 if (memh_valid) { 706 sc->sc_st = memt; 707 sc->sc_sh = memh; 708 } else if (ioh_valid) { 709 sc->sc_st = iot; 710 sc->sc_sh = ioh; 711 } else { 712 printf("%s: unable to map device registers\n", 713 sc->sc_dev.dv_xname); 714 return; 715 } 716 717 sc->sc_dmat = pa->pa_dmat; 718 719 /* 720 * Make sure bus mastering is enabled. Also make sure 721 * Write/Invalidate is enabled if we're allowed to use it. 722 */ 723 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 724 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 725 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 726 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 727 pmreg | PCI_COMMAND_MASTER_ENABLE); 728 729 /* Get it out of power save mode if needed. */ 730 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 731 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 732 PCI_PMCSR_STATE_MASK; 733 if (pmode == PCI_PMCSR_STATE_D3) { 734 /* 735 * The card has lost all configuration data in 736 * this state, so punt. 737 */ 738 printf("%s: unable to wake up from power state D3\n", 739 sc->sc_dev.dv_xname); 740 return; 741 } 742 if (pmode != PCI_PMCSR_STATE_D0) { 743 printf("%s: waking up from power state D%d\n", 744 sc->sc_dev.dv_xname, pmode); 745 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 746 PCI_PMCSR_STATE_D0); 747 } 748 } 749 750 /* 751 * Map and establish our interrupt. 752 */ 753 if (pci_intr_map(pa, &ih)) { 754 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 755 return; 756 } 757 intrstr = pci_intr_string(pc, ih); 758 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 759 if (sc->sc_ih == NULL) { 760 printf("%s: unable to establish interrupt", 761 sc->sc_dev.dv_xname); 762 if (intrstr != NULL) 763 printf(" at %s", intrstr); 764 printf("\n"); 765 return; 766 } 767 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 768 769 SIMPLEQ_INIT(&sc->sc_txfreeq); 770 SIMPLEQ_INIT(&sc->sc_txdirtyq); 771 772 /* 773 * Allocate the control data structures, and create and load the 774 * DMA map for it. 775 */ 776 if ((error = bus_dmamem_alloc(sc->sc_dmat, 777 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 778 0)) != 0) { 779 printf("%s: unable to allocate control data, error = %d\n", 780 sc->sc_dev.dv_xname, error); 781 goto fail_0; 782 } 783 784 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 785 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 786 BUS_DMA_COHERENT)) != 0) { 787 printf("%s: unable to map control data, error = %d\n", 788 sc->sc_dev.dv_xname, error); 789 goto fail_1; 790 } 791 792 if ((error = bus_dmamap_create(sc->sc_dmat, 793 sizeof(struct sip_control_data), 1, 794 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 795 printf("%s: unable to create control data DMA map, " 796 "error = %d\n", sc->sc_dev.dv_xname, error); 797 goto fail_2; 798 } 799 800 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 801 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 802 0)) != 0) { 803 printf("%s: unable to load control data DMA map, error = %d\n", 804 sc->sc_dev.dv_xname, error); 805 goto fail_3; 806 } 807 808 /* 809 * Create the transmit buffer DMA maps. 810 */ 811 for (i = 0; i < SIP_TXQUEUELEN; i++) { 812 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 813 SIP_NTXSEGS, MCLBYTES, 0, 0, 814 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 815 printf("%s: unable to create tx DMA map %d, " 816 "error = %d\n", sc->sc_dev.dv_xname, i, error); 817 goto fail_4; 818 } 819 } 820 821 /* 822 * Create the receive buffer DMA maps. 823 */ 824 for (i = 0; i < SIP_NRXDESC; i++) { 825 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 826 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 827 printf("%s: unable to create rx DMA map %d, " 828 "error = %d\n", sc->sc_dev.dv_xname, i, error); 829 goto fail_5; 830 } 831 sc->sc_rxsoft[i].rxs_mbuf = NULL; 832 } 833 834 /* 835 * Reset the chip to a known state. 836 */ 837 SIP_DECL(reset)(sc); 838 839 /* 840 * Read the Ethernet address from the EEPROM. This might 841 * also fetch other stuff from the EEPROM and stash it 842 * in the softc. 843 */ 844 sc->sc_cfg = 0; 845 #if !defined(DP83820) 846 if (SIP_SIS900_REV(sc,SIS_REV_635) || 847 SIP_SIS900_REV(sc,SIS_REV_900B)) 848 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 849 850 if (SIP_SIS900_REV(sc,SIS_REV_635) || 851 SIP_SIS900_REV(sc,SIS_REV_960) || 852 SIP_SIS900_REV(sc,SIS_REV_900B)) 853 sc->sc_cfg |= (bus_space_read_4(sc->sc_st, sc->sc_sh, 854 SIP_CFG) & CFG_EDBMASTEN); 855 #endif 856 857 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 858 859 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 860 ether_sprintf(enaddr)); 861 862 /* 863 * Initialize the configuration register: aggressive PCI 864 * bus request algorithm, default backoff, default OW timer, 865 * default parity error detection. 866 * 867 * NOTE: "Big endian mode" is useless on the SiS900 and 868 * friends -- it affects packet data, not descriptors. 869 */ 870 #ifdef DP83820 871 /* 872 * Cause the chip to load configuration data from the EEPROM. 873 */ 874 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 875 for (i = 0; i < 10000; i++) { 876 delay(10); 877 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 878 PTSCR_EELOAD_EN) == 0) 879 break; 880 } 881 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 882 PTSCR_EELOAD_EN) { 883 printf("%s: timeout loading configuration from EEPROM\n", 884 sc->sc_dev.dv_xname); 885 return; 886 } 887 888 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 889 890 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 891 if (reg & CFG_PCI64_DET) { 892 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 893 /* 894 * Check to see if this card is 64-bit. If so, enable 64-bit 895 * data transfers. 896 * 897 * We can't use the DATA64_EN bit in the EEPROM, because 898 * vendors of 32-bit cards fail to clear that bit in many 899 * cases (yet the card still detects that it's in a 64-bit 900 * slot; go figure). 901 */ 902 if (SIP_DECL(check_64bit)(pa)) { 903 sc->sc_cfg |= CFG_DATA64_EN; 904 printf(", using 64-bit data transfers"); 905 } 906 printf("\n"); 907 } 908 909 /* 910 * XXX Need some PCI flags indicating support for 911 * XXX 64-bit addressing. 912 */ 913 #if 0 914 if (reg & CFG_M64ADDR) 915 sc->sc_cfg |= CFG_M64ADDR; 916 if (reg & CFG_T64ADDR) 917 sc->sc_cfg |= CFG_T64ADDR; 918 #endif 919 920 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 921 const char *sep = ""; 922 printf("%s: using ", sc->sc_dev.dv_xname); 923 if (reg & CFG_EXT_125) { 924 sc->sc_cfg |= CFG_EXT_125; 925 printf("%s125MHz clock", sep); 926 sep = ", "; 927 } 928 if (reg & CFG_TBI_EN) { 929 sc->sc_cfg |= CFG_TBI_EN; 930 printf("%sten-bit interface", sep); 931 sep = ", "; 932 } 933 printf("\n"); 934 } 935 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 936 (reg & CFG_MRM_DIS) != 0) 937 sc->sc_cfg |= CFG_MRM_DIS; 938 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 939 (reg & CFG_MWI_DIS) != 0) 940 sc->sc_cfg |= CFG_MWI_DIS; 941 942 /* 943 * Use the extended descriptor format on the DP83820. This 944 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 945 * checksumming. 946 */ 947 sc->sc_cfg |= CFG_EXTSTS_EN; 948 #endif /* DP83820 */ 949 950 /* 951 * Initialize our media structures and probe the MII. 952 */ 953 sc->sc_mii.mii_ifp = ifp; 954 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 955 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 956 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 957 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, SIP_DECL(mediachange), 958 SIP_DECL(mediastatus)); 959 960 /* 961 * XXX We cannot handle flow control on the DP83815. 962 */ 963 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 964 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 965 MII_OFFSET_ANY, 0); 966 else 967 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 968 MII_OFFSET_ANY, MIIF_DOPAUSE); 969 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 970 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 971 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 972 } else 973 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 974 975 ifp = &sc->sc_ethercom.ec_if; 976 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 977 ifp->if_softc = sc; 978 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 979 ifp->if_ioctl = SIP_DECL(ioctl); 980 ifp->if_start = SIP_DECL(start); 981 ifp->if_watchdog = SIP_DECL(watchdog); 982 ifp->if_init = SIP_DECL(init); 983 ifp->if_stop = SIP_DECL(stop); 984 IFQ_SET_READY(&ifp->if_snd); 985 986 /* 987 * We can support 802.1Q VLAN-sized frames. 988 */ 989 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 990 991 #ifdef DP83820 992 /* 993 * And the DP83820 can do VLAN tagging in hardware, and 994 * support the jumbo Ethernet MTU. 995 */ 996 sc->sc_ethercom.ec_capabilities |= 997 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 998 999 /* 1000 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1001 * in hardware. 1002 */ 1003 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 1004 IFCAP_CSUM_UDPv4; 1005 #endif /* DP83820 */ 1006 1007 /* 1008 * Attach the interface. 1009 */ 1010 if_attach(ifp); 1011 ether_ifattach(ifp, enaddr); 1012 #if NRND > 0 1013 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1014 RND_TYPE_NET, 0); 1015 #endif 1016 1017 /* 1018 * The number of bytes that must be available in 1019 * the Tx FIFO before the bus master can DMA more 1020 * data into the FIFO. 1021 */ 1022 sc->sc_tx_fill_thresh = 64 / 32; 1023 1024 /* 1025 * Start at a drain threshold of 512 bytes. We will 1026 * increase it if a DMA underrun occurs. 1027 * 1028 * XXX The minimum value of this variable should be 1029 * tuned. We may be able to improve performance 1030 * by starting with a lower value. That, however, 1031 * may trash the first few outgoing packets if the 1032 * PCI bus is saturated. 1033 */ 1034 #ifdef DP83820 1035 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1036 #else 1037 sc->sc_tx_drain_thresh = 1504 / 32; 1038 #endif 1039 1040 /* 1041 * Initialize the Rx FIFO drain threshold. 1042 * 1043 * This is in units of 8 bytes. 1044 * 1045 * We should never set this value lower than 2; 14 bytes are 1046 * required to filter the packet. 1047 */ 1048 sc->sc_rx_drain_thresh = 128 / 8; 1049 1050 #ifdef SIP_EVENT_COUNTERS 1051 /* 1052 * Attach event counters. 1053 */ 1054 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1055 NULL, sc->sc_dev.dv_xname, "txsstall"); 1056 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1057 NULL, sc->sc_dev.dv_xname, "txdstall"); 1058 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1059 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1060 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1061 NULL, sc->sc_dev.dv_xname, "txdintr"); 1062 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1063 NULL, sc->sc_dev.dv_xname, "txiintr"); 1064 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1065 NULL, sc->sc_dev.dv_xname, "rxintr"); 1066 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1067 NULL, sc->sc_dev.dv_xname, "hiberr"); 1068 #ifdef DP83820 1069 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1070 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1071 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1072 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1073 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1074 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1075 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1076 NULL, sc->sc_dev.dv_xname, "txipsum"); 1077 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1078 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1079 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1080 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1081 #endif /* DP83820 */ 1082 #endif /* SIP_EVENT_COUNTERS */ 1083 1084 /* 1085 * Make sure the interface is shutdown during reboot. 1086 */ 1087 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 1088 if (sc->sc_sdhook == NULL) 1089 printf("%s: WARNING: unable to establish shutdown hook\n", 1090 sc->sc_dev.dv_xname); 1091 return; 1092 1093 /* 1094 * Free any resources we've allocated during the failed attach 1095 * attempt. Do this in reverse order and fall through. 1096 */ 1097 fail_5: 1098 for (i = 0; i < SIP_NRXDESC; i++) { 1099 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1100 bus_dmamap_destroy(sc->sc_dmat, 1101 sc->sc_rxsoft[i].rxs_dmamap); 1102 } 1103 fail_4: 1104 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1105 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1106 bus_dmamap_destroy(sc->sc_dmat, 1107 sc->sc_txsoft[i].txs_dmamap); 1108 } 1109 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1110 fail_3: 1111 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1112 fail_2: 1113 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1114 sizeof(struct sip_control_data)); 1115 fail_1: 1116 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1117 fail_0: 1118 return; 1119 } 1120 1121 /* 1122 * sip_shutdown: 1123 * 1124 * Make sure the interface is stopped at reboot time. 1125 */ 1126 void 1127 SIP_DECL(shutdown)(void *arg) 1128 { 1129 struct sip_softc *sc = arg; 1130 1131 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1132 } 1133 1134 /* 1135 * sip_start: [ifnet interface function] 1136 * 1137 * Start packet transmission on the interface. 1138 */ 1139 void 1140 SIP_DECL(start)(struct ifnet *ifp) 1141 { 1142 struct sip_softc *sc = ifp->if_softc; 1143 struct mbuf *m0; 1144 #ifndef DP83820 1145 struct mbuf *m; 1146 #endif 1147 struct sip_txsoft *txs; 1148 bus_dmamap_t dmamap; 1149 int error, nexttx, lasttx, seg; 1150 int ofree = sc->sc_txfree; 1151 #if 0 1152 int firsttx = sc->sc_txnext; 1153 #endif 1154 #ifdef DP83820 1155 struct m_tag *mtag; 1156 u_int32_t extsts; 1157 #endif 1158 1159 #ifndef DP83820 1160 /* 1161 * If we've been told to pause, don't transmit any more packets. 1162 */ 1163 if (sc->sc_paused) 1164 ifp->if_flags |= IFF_OACTIVE; 1165 #endif 1166 1167 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1168 return; 1169 1170 /* 1171 * Loop through the send queue, setting up transmit descriptors 1172 * until we drain the queue, or use up all available transmit 1173 * descriptors. 1174 */ 1175 for (;;) { 1176 /* Get a work queue entry. */ 1177 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1178 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1179 break; 1180 } 1181 1182 /* 1183 * Grab a packet off the queue. 1184 */ 1185 IFQ_POLL(&ifp->if_snd, m0); 1186 if (m0 == NULL) 1187 break; 1188 #ifndef DP83820 1189 m = NULL; 1190 #endif 1191 1192 dmamap = txs->txs_dmamap; 1193 1194 #ifdef DP83820 1195 /* 1196 * Load the DMA map. If this fails, the packet either 1197 * didn't fit in the allotted number of segments, or we 1198 * were short on resources. For the too-many-segments 1199 * case, we simply report an error and drop the packet, 1200 * since we can't sanely copy a jumbo packet to a single 1201 * buffer. 1202 */ 1203 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1204 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1205 if (error) { 1206 if (error == EFBIG) { 1207 printf("%s: Tx packet consumes too many " 1208 "DMA segments, dropping...\n", 1209 sc->sc_dev.dv_xname); 1210 IFQ_DEQUEUE(&ifp->if_snd, m0); 1211 m_freem(m0); 1212 continue; 1213 } 1214 /* 1215 * Short on resources, just stop for now. 1216 */ 1217 break; 1218 } 1219 #else /* DP83820 */ 1220 /* 1221 * Load the DMA map. If this fails, the packet either 1222 * didn't fit in the alloted number of segments, or we 1223 * were short on resources. In this case, we'll copy 1224 * and try again. 1225 */ 1226 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1227 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1228 MGETHDR(m, M_DONTWAIT, MT_DATA); 1229 if (m == NULL) { 1230 printf("%s: unable to allocate Tx mbuf\n", 1231 sc->sc_dev.dv_xname); 1232 break; 1233 } 1234 if (m0->m_pkthdr.len > MHLEN) { 1235 MCLGET(m, M_DONTWAIT); 1236 if ((m->m_flags & M_EXT) == 0) { 1237 printf("%s: unable to allocate Tx " 1238 "cluster\n", sc->sc_dev.dv_xname); 1239 m_freem(m); 1240 break; 1241 } 1242 } 1243 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1244 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1245 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1246 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1247 if (error) { 1248 printf("%s: unable to load Tx buffer, " 1249 "error = %d\n", sc->sc_dev.dv_xname, error); 1250 break; 1251 } 1252 } 1253 #endif /* DP83820 */ 1254 1255 /* 1256 * Ensure we have enough descriptors free to describe 1257 * the packet. Note, we always reserve one descriptor 1258 * at the end of the ring as a termination point, to 1259 * prevent wrap-around. 1260 */ 1261 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1262 /* 1263 * Not enough free descriptors to transmit this 1264 * packet. We haven't committed anything yet, 1265 * so just unload the DMA map, put the packet 1266 * back on the queue, and punt. Notify the upper 1267 * layer that there are not more slots left. 1268 * 1269 * XXX We could allocate an mbuf and copy, but 1270 * XXX is it worth it? 1271 */ 1272 ifp->if_flags |= IFF_OACTIVE; 1273 bus_dmamap_unload(sc->sc_dmat, dmamap); 1274 #ifndef DP83820 1275 if (m != NULL) 1276 m_freem(m); 1277 #endif 1278 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1279 break; 1280 } 1281 1282 IFQ_DEQUEUE(&ifp->if_snd, m0); 1283 #ifndef DP83820 1284 if (m != NULL) { 1285 m_freem(m0); 1286 m0 = m; 1287 } 1288 #endif 1289 1290 /* 1291 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1292 */ 1293 1294 /* Sync the DMA map. */ 1295 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1296 BUS_DMASYNC_PREWRITE); 1297 1298 /* 1299 * Initialize the transmit descriptors. 1300 */ 1301 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1302 seg < dmamap->dm_nsegs; 1303 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1304 /* 1305 * If this is the first descriptor we're 1306 * enqueueing, don't set the OWN bit just 1307 * yet. That could cause a race condition. 1308 * We'll do it below. 1309 */ 1310 sc->sc_txdescs[nexttx].sipd_bufptr = 1311 htole32(dmamap->dm_segs[seg].ds_addr); 1312 sc->sc_txdescs[nexttx].sipd_cmdsts = 1313 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1314 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1315 #ifdef DP83820 1316 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1317 #endif /* DP83820 */ 1318 lasttx = nexttx; 1319 } 1320 1321 /* Clear the MORE bit on the last segment. */ 1322 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1323 1324 /* 1325 * If we're in the interrupt delay window, delay the 1326 * interrupt. 1327 */ 1328 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1329 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1330 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1331 htole32(CMDSTS_INTR); 1332 sc->sc_txwin = 0; 1333 } 1334 1335 #ifdef DP83820 1336 /* 1337 * If VLANs are enabled and the packet has a VLAN tag, set 1338 * up the descriptor to encapsulate the packet for us. 1339 * 1340 * This apparently has to be on the last descriptor of 1341 * the packet. 1342 */ 1343 if (sc->sc_ethercom.ec_nvlans != 0 && 1344 (mtag = m_tag_find(m0, PACKET_TAG_VLAN, NULL)) != NULL) { 1345 sc->sc_txdescs[lasttx].sipd_extsts |= 1346 htole32(EXTSTS_VPKT | 1347 (*(u_int *)(mtag + 1) & EXTSTS_VTCI)); 1348 } 1349 1350 /* 1351 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1352 * checksumming, set up the descriptor to do this work 1353 * for us. 1354 * 1355 * This apparently has to be on the first descriptor of 1356 * the packet. 1357 * 1358 * Byte-swap constants so the compiler can optimize. 1359 */ 1360 extsts = 0; 1361 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1362 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1363 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1364 extsts |= htole32(EXTSTS_IPPKT); 1365 } 1366 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1367 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1368 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1369 extsts |= htole32(EXTSTS_TCPPKT); 1370 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1371 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1372 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1373 extsts |= htole32(EXTSTS_UDPPKT); 1374 } 1375 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1376 #endif /* DP83820 */ 1377 1378 /* Sync the descriptors we're using. */ 1379 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1380 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1381 1382 /* 1383 * The entire packet is set up. Give the first descrptor 1384 * to the chip now. 1385 */ 1386 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1387 htole32(CMDSTS_OWN); 1388 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1389 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1390 1391 /* 1392 * Store a pointer to the packet so we can free it later, 1393 * and remember what txdirty will be once the packet is 1394 * done. 1395 */ 1396 txs->txs_mbuf = m0; 1397 txs->txs_firstdesc = sc->sc_txnext; 1398 txs->txs_lastdesc = lasttx; 1399 1400 /* Advance the tx pointer. */ 1401 sc->sc_txfree -= dmamap->dm_nsegs; 1402 sc->sc_txnext = nexttx; 1403 1404 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1405 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1406 1407 #if NBPFILTER > 0 1408 /* 1409 * Pass the packet to any BPF listeners. 1410 */ 1411 if (ifp->if_bpf) 1412 bpf_mtap(ifp->if_bpf, m0); 1413 #endif /* NBPFILTER > 0 */ 1414 } 1415 1416 if (txs == NULL || sc->sc_txfree == 0) { 1417 /* No more slots left; notify upper layer. */ 1418 ifp->if_flags |= IFF_OACTIVE; 1419 } 1420 1421 if (sc->sc_txfree != ofree) { 1422 /* 1423 * Start the transmit process. Note, the manual says 1424 * that if there are no pending transmissions in the 1425 * chip's internal queue (indicated by TXE being clear), 1426 * then the driver software must set the TXDP to the 1427 * first descriptor to be transmitted. However, if we 1428 * do this, it causes serious performance degredation on 1429 * the DP83820 under load, not setting TXDP doesn't seem 1430 * to adversely affect the SiS 900 or DP83815. 1431 * 1432 * Well, I guess it wouldn't be the first time a manual 1433 * has lied -- and they could be speaking of the NULL- 1434 * terminated descriptor list case, rather than OWN- 1435 * terminated rings. 1436 */ 1437 #if 0 1438 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1439 CR_TXE) == 0) { 1440 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1441 SIP_CDTXADDR(sc, firsttx)); 1442 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1443 } 1444 #else 1445 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1446 #endif 1447 1448 /* Set a watchdog timer in case the chip flakes out. */ 1449 #ifdef DP83820 1450 /* Gigabit autonegotiation takes 5 seconds. */ 1451 ifp->if_timer = 10; 1452 #else 1453 ifp->if_timer = 5; 1454 #endif 1455 } 1456 } 1457 1458 /* 1459 * sip_watchdog: [ifnet interface function] 1460 * 1461 * Watchdog timer handler. 1462 */ 1463 void 1464 SIP_DECL(watchdog)(struct ifnet *ifp) 1465 { 1466 struct sip_softc *sc = ifp->if_softc; 1467 1468 /* 1469 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1470 * If we get a timeout, try and sweep up transmit descriptors. 1471 * If we manage to sweep them all up, ignore the lack of 1472 * interrupt. 1473 */ 1474 SIP_DECL(txintr)(sc); 1475 1476 if (sc->sc_txfree != SIP_NTXDESC) { 1477 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1478 ifp->if_oerrors++; 1479 1480 /* Reset the interface. */ 1481 (void) SIP_DECL(init)(ifp); 1482 } else if (ifp->if_flags & IFF_DEBUG) 1483 printf("%s: recovered from device timeout\n", 1484 sc->sc_dev.dv_xname); 1485 1486 /* Try to get more packets going. */ 1487 SIP_DECL(start)(ifp); 1488 } 1489 1490 /* 1491 * sip_ioctl: [ifnet interface function] 1492 * 1493 * Handle control requests from the operator. 1494 */ 1495 int 1496 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1497 { 1498 struct sip_softc *sc = ifp->if_softc; 1499 struct ifreq *ifr = (struct ifreq *)data; 1500 int s, error; 1501 1502 s = splnet(); 1503 1504 switch (cmd) { 1505 case SIOCSIFMEDIA: 1506 /* Flow control requires full-duplex mode. */ 1507 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1508 (ifr->ifr_media & IFM_FDX) == 0) 1509 ifr->ifr_media &= ~IFM_ETH_FMASK; 1510 #ifdef DP83820 1511 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1512 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1513 /* We can do both TXPAUSE and RXPAUSE. */ 1514 ifr->ifr_media |= 1515 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1516 } 1517 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1518 } 1519 #else 1520 /* XXX */ 1521 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1522 ifr->ifr_media &= ~IFM_ETH_FMASK; 1523 1524 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1525 if (ifr->ifr_media & IFM_FLOW) { 1526 /* 1527 * Both TXPAUSE and RXPAUSE must be set. 1528 * (SiS900 and DP83815 don't have PAUSE_ASYM 1529 * feature.) 1530 * 1531 * XXX Can SiS900 and DP83815 send PAUSE? 1532 */ 1533 ifr->ifr_media |= 1534 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1535 } 1536 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1537 } 1538 #endif 1539 /* FALLTHROUGH */ 1540 case SIOCGIFMEDIA: 1541 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1542 break; 1543 1544 default: 1545 error = ether_ioctl(ifp, cmd, data); 1546 if (error == ENETRESET) { 1547 /* 1548 * Multicast list has changed; set the hardware filter 1549 * accordingly. 1550 */ 1551 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1552 error = 0; 1553 } 1554 break; 1555 } 1556 1557 /* Try to get more packets going. */ 1558 SIP_DECL(start)(ifp); 1559 1560 splx(s); 1561 return (error); 1562 } 1563 1564 /* 1565 * sip_intr: 1566 * 1567 * Interrupt service routine. 1568 */ 1569 int 1570 SIP_DECL(intr)(void *arg) 1571 { 1572 struct sip_softc *sc = arg; 1573 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1574 u_int32_t isr; 1575 int handled = 0; 1576 1577 /* Disable interrupts. */ 1578 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1579 1580 for (;;) { 1581 /* Reading clears interrupt. */ 1582 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1583 if ((isr & sc->sc_imr) == 0) 1584 break; 1585 1586 #if NRND > 0 1587 if (RND_ENABLED(&sc->rnd_source)) 1588 rnd_add_uint32(&sc->rnd_source, isr); 1589 #endif 1590 1591 handled = 1; 1592 1593 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1594 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1595 1596 /* Grab any new packets. */ 1597 SIP_DECL(rxintr)(sc); 1598 1599 if (isr & ISR_RXORN) { 1600 printf("%s: receive FIFO overrun\n", 1601 sc->sc_dev.dv_xname); 1602 1603 /* XXX adjust rx_drain_thresh? */ 1604 } 1605 1606 if (isr & ISR_RXIDLE) { 1607 printf("%s: receive ring overrun\n", 1608 sc->sc_dev.dv_xname); 1609 1610 /* Get the receive process going again. */ 1611 bus_space_write_4(sc->sc_st, sc->sc_sh, 1612 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1613 bus_space_write_4(sc->sc_st, sc->sc_sh, 1614 SIP_CR, CR_RXE); 1615 } 1616 } 1617 1618 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1619 #ifdef SIP_EVENT_COUNTERS 1620 if (isr & ISR_TXDESC) 1621 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1622 else if (isr & ISR_TXIDLE) 1623 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1624 #endif 1625 1626 /* Sweep up transmit descriptors. */ 1627 SIP_DECL(txintr)(sc); 1628 1629 if (isr & ISR_TXURN) { 1630 u_int32_t thresh; 1631 1632 printf("%s: transmit FIFO underrun", 1633 sc->sc_dev.dv_xname); 1634 1635 thresh = sc->sc_tx_drain_thresh + 1; 1636 if (thresh <= TXCFG_DRTH && 1637 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1638 (sc->sc_tx_fill_thresh * 32))) { 1639 printf("; increasing Tx drain " 1640 "threshold to %u bytes\n", 1641 thresh * 32); 1642 sc->sc_tx_drain_thresh = thresh; 1643 (void) SIP_DECL(init)(ifp); 1644 } else { 1645 (void) SIP_DECL(init)(ifp); 1646 printf("\n"); 1647 } 1648 } 1649 } 1650 1651 #if !defined(DP83820) 1652 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1653 if (isr & ISR_PAUSE_ST) { 1654 sc->sc_paused = 1; 1655 ifp->if_flags |= IFF_OACTIVE; 1656 } 1657 if (isr & ISR_PAUSE_END) { 1658 sc->sc_paused = 0; 1659 ifp->if_flags &= ~IFF_OACTIVE; 1660 } 1661 } 1662 #endif /* ! DP83820 */ 1663 1664 if (isr & ISR_HIBERR) { 1665 int want_init = 0; 1666 1667 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1668 1669 #define PRINTERR(bit, str) \ 1670 do { \ 1671 if ((isr & (bit)) != 0) { \ 1672 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1673 printf("%s: %s\n", \ 1674 sc->sc_dev.dv_xname, str); \ 1675 want_init = 1; \ 1676 } \ 1677 } while (/*CONSTCOND*/0) 1678 1679 PRINTERR(ISR_DPERR, "parity error"); 1680 PRINTERR(ISR_SSERR, "system error"); 1681 PRINTERR(ISR_RMABT, "master abort"); 1682 PRINTERR(ISR_RTABT, "target abort"); 1683 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1684 /* 1685 * Ignore: 1686 * Tx reset complete 1687 * Rx reset complete 1688 */ 1689 if (want_init) 1690 (void) SIP_DECL(init)(ifp); 1691 #undef PRINTERR 1692 } 1693 } 1694 1695 /* Re-enable interrupts. */ 1696 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1697 1698 /* Try to get more packets going. */ 1699 SIP_DECL(start)(ifp); 1700 1701 return (handled); 1702 } 1703 1704 /* 1705 * sip_txintr: 1706 * 1707 * Helper; handle transmit interrupts. 1708 */ 1709 void 1710 SIP_DECL(txintr)(struct sip_softc *sc) 1711 { 1712 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1713 struct sip_txsoft *txs; 1714 u_int32_t cmdsts; 1715 1716 #ifndef DP83820 1717 if (sc->sc_paused == 0) 1718 #endif 1719 ifp->if_flags &= ~IFF_OACTIVE; 1720 1721 /* 1722 * Go through our Tx list and free mbufs for those 1723 * frames which have been transmitted. 1724 */ 1725 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1726 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1727 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1728 1729 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1730 if (cmdsts & CMDSTS_OWN) 1731 break; 1732 1733 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1734 1735 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1736 1737 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1738 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1739 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1740 m_freem(txs->txs_mbuf); 1741 txs->txs_mbuf = NULL; 1742 1743 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1744 1745 /* 1746 * Check for errors and collisions. 1747 */ 1748 if (cmdsts & 1749 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1750 ifp->if_oerrors++; 1751 if (cmdsts & CMDSTS_Tx_EC) 1752 ifp->if_collisions += 16; 1753 if (ifp->if_flags & IFF_DEBUG) { 1754 if (cmdsts & CMDSTS_Tx_ED) 1755 printf("%s: excessive deferral\n", 1756 sc->sc_dev.dv_xname); 1757 if (cmdsts & CMDSTS_Tx_EC) 1758 printf("%s: excessive collisions\n", 1759 sc->sc_dev.dv_xname); 1760 } 1761 } else { 1762 /* Packet was transmitted successfully. */ 1763 ifp->if_opackets++; 1764 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1765 } 1766 } 1767 1768 /* 1769 * If there are no more pending transmissions, cancel the watchdog 1770 * timer. 1771 */ 1772 if (txs == NULL) { 1773 ifp->if_timer = 0; 1774 sc->sc_txwin = 0; 1775 } 1776 } 1777 1778 #if defined(DP83820) 1779 /* 1780 * sip_rxintr: 1781 * 1782 * Helper; handle receive interrupts. 1783 */ 1784 void 1785 SIP_DECL(rxintr)(struct sip_softc *sc) 1786 { 1787 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1788 struct sip_rxsoft *rxs; 1789 struct mbuf *m, *tailm; 1790 u_int32_t cmdsts, extsts; 1791 int i, len, frame_len; 1792 1793 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1794 rxs = &sc->sc_rxsoft[i]; 1795 1796 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1797 1798 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1799 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1800 1801 /* 1802 * NOTE: OWN is set if owned by _consumer_. We're the 1803 * consumer of the receive ring, so if the bit is clear, 1804 * we have processed all of the packets. 1805 */ 1806 if ((cmdsts & CMDSTS_OWN) == 0) { 1807 /* 1808 * We have processed all of the receive buffers. 1809 */ 1810 break; 1811 } 1812 1813 if (__predict_false(sc->sc_rxdiscard)) { 1814 SIP_INIT_RXDESC(sc, i); 1815 if ((cmdsts & CMDSTS_MORE) == 0) { 1816 /* Reset our state. */ 1817 sc->sc_rxdiscard = 0; 1818 } 1819 continue; 1820 } 1821 1822 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1823 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1824 1825 m = rxs->rxs_mbuf; 1826 1827 /* 1828 * Add a new receive buffer to the ring. 1829 */ 1830 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1831 /* 1832 * Failed, throw away what we've done so 1833 * far, and discard the rest of the packet. 1834 */ 1835 ifp->if_ierrors++; 1836 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1837 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1838 SIP_INIT_RXDESC(sc, i); 1839 if (cmdsts & CMDSTS_MORE) 1840 sc->sc_rxdiscard = 1; 1841 if (sc->sc_rxhead != NULL) 1842 m_freem(sc->sc_rxhead); 1843 SIP_RXCHAIN_RESET(sc); 1844 continue; 1845 } 1846 1847 SIP_RXCHAIN_LINK(sc, m); 1848 1849 /* 1850 * If this is not the end of the packet, keep 1851 * looking. 1852 */ 1853 if (cmdsts & CMDSTS_MORE) { 1854 sc->sc_rxlen += m->m_len; 1855 continue; 1856 } 1857 1858 /* 1859 * Okay, we have the entire packet now... 1860 */ 1861 *sc->sc_rxtailp = NULL; 1862 m = sc->sc_rxhead; 1863 tailm = sc->sc_rxtail; 1864 frame_len = sc->sc_rxlen; 1865 1866 SIP_RXCHAIN_RESET(sc); 1867 1868 /* 1869 * If an error occurred, update stats and drop the packet. 1870 */ 1871 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1872 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1873 ifp->if_ierrors++; 1874 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1875 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1876 /* Receive overrun handled elsewhere. */ 1877 printf("%s: receive descriptor error\n", 1878 sc->sc_dev.dv_xname); 1879 } 1880 #define PRINTERR(bit, str) \ 1881 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1882 (cmdsts & (bit)) != 0) \ 1883 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1884 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1885 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1886 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1887 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1888 #undef PRINTERR 1889 m_freem(m); 1890 continue; 1891 } 1892 1893 /* 1894 * No errors. 1895 * 1896 * Note, the DP83820 includes the CRC with 1897 * every packet. 1898 */ 1899 len = CMDSTS_SIZE(cmdsts); 1900 frame_len += len; 1901 tailm->m_len = len; 1902 1903 /* 1904 * If the packet is small enough to fit in a 1905 * single header mbuf, allocate one and copy 1906 * the data into it. This greatly reduces 1907 * memory consumption when we receive lots 1908 * of small packets. 1909 */ 1910 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1911 struct mbuf *nm; 1912 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1913 if (nm == NULL) { 1914 ifp->if_ierrors++; 1915 m_freem(m); 1916 continue; 1917 } 1918 nm->m_data += 2; 1919 nm->m_pkthdr.len = nm->m_len = len; 1920 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1921 m_freem(m); 1922 m = nm; 1923 } 1924 #ifndef __NO_STRICT_ALIGNMENT 1925 else { 1926 /* 1927 * The DP83820's receive buffers must be 4-byte 1928 * aligned. But this means that the data after 1929 * the Ethernet header is misaligned. To compensate, 1930 * we have artificially shortened the buffer size 1931 * in the descriptor, and we do an overlapping copy 1932 * of the data two bytes further in (in the first 1933 * buffer of the chain only). 1934 */ 1935 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1936 m->m_len); 1937 m->m_data += 2; 1938 } 1939 #endif /* ! __NO_STRICT_ALIGNMENT */ 1940 1941 /* 1942 * If VLANs are enabled, VLAN packets have been unwrapped 1943 * for us. Associate the tag with the packet. 1944 */ 1945 if (sc->sc_ethercom.ec_nvlans != 0 && 1946 (extsts & EXTSTS_VPKT) != 0) { 1947 struct m_tag *vtag; 1948 1949 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 1950 M_NOWAIT); 1951 if (vtag == NULL) { 1952 ifp->if_ierrors++; 1953 printf("%s: unable to allocate VLAN tag\n", 1954 sc->sc_dev.dv_xname); 1955 m_freem(m); 1956 continue; 1957 } 1958 1959 *(u_int *)(vtag + 1) = ntohs(extsts & EXTSTS_VTCI); 1960 } 1961 1962 /* 1963 * Set the incoming checksum information for the 1964 * packet. 1965 */ 1966 if ((extsts & EXTSTS_IPPKT) != 0) { 1967 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1968 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1969 if (extsts & EXTSTS_Rx_IPERR) 1970 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1971 if (extsts & EXTSTS_TCPPKT) { 1972 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1973 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1974 if (extsts & EXTSTS_Rx_TCPERR) 1975 m->m_pkthdr.csum_flags |= 1976 M_CSUM_TCP_UDP_BAD; 1977 } else if (extsts & EXTSTS_UDPPKT) { 1978 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1979 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1980 if (extsts & EXTSTS_Rx_UDPERR) 1981 m->m_pkthdr.csum_flags |= 1982 M_CSUM_TCP_UDP_BAD; 1983 } 1984 } 1985 1986 ifp->if_ipackets++; 1987 m->m_flags |= M_HASFCS; 1988 m->m_pkthdr.rcvif = ifp; 1989 m->m_pkthdr.len = frame_len; 1990 1991 #if NBPFILTER > 0 1992 /* 1993 * Pass this up to any BPF listeners, but only 1994 * pass if up the stack if it's for us. 1995 */ 1996 if (ifp->if_bpf) 1997 bpf_mtap(ifp->if_bpf, m); 1998 #endif /* NBPFILTER > 0 */ 1999 2000 /* Pass it on. */ 2001 (*ifp->if_input)(ifp, m); 2002 } 2003 2004 /* Update the receive pointer. */ 2005 sc->sc_rxptr = i; 2006 } 2007 #else /* ! DP83820 */ 2008 /* 2009 * sip_rxintr: 2010 * 2011 * Helper; handle receive interrupts. 2012 */ 2013 void 2014 SIP_DECL(rxintr)(struct sip_softc *sc) 2015 { 2016 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2017 struct sip_rxsoft *rxs; 2018 struct mbuf *m; 2019 u_int32_t cmdsts; 2020 int i, len; 2021 2022 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 2023 rxs = &sc->sc_rxsoft[i]; 2024 2025 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2026 2027 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 2028 2029 /* 2030 * NOTE: OWN is set if owned by _consumer_. We're the 2031 * consumer of the receive ring, so if the bit is clear, 2032 * we have processed all of the packets. 2033 */ 2034 if ((cmdsts & CMDSTS_OWN) == 0) { 2035 /* 2036 * We have processed all of the receive buffers. 2037 */ 2038 break; 2039 } 2040 2041 /* 2042 * If any collisions were seen on the wire, count one. 2043 */ 2044 if (cmdsts & CMDSTS_Rx_COL) 2045 ifp->if_collisions++; 2046 2047 /* 2048 * If an error occurred, update stats, clear the status 2049 * word, and leave the packet buffer in place. It will 2050 * simply be reused the next time the ring comes around. 2051 */ 2052 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2053 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2054 ifp->if_ierrors++; 2055 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2056 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2057 /* Receive overrun handled elsewhere. */ 2058 printf("%s: receive descriptor error\n", 2059 sc->sc_dev.dv_xname); 2060 } 2061 #define PRINTERR(bit, str) \ 2062 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2063 (cmdsts & (bit)) != 0) \ 2064 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 2065 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2066 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2067 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2068 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2069 #undef PRINTERR 2070 SIP_INIT_RXDESC(sc, i); 2071 continue; 2072 } 2073 2074 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2075 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2076 2077 /* 2078 * No errors; receive the packet. Note, the SiS 900 2079 * includes the CRC with every packet. 2080 */ 2081 len = CMDSTS_SIZE(cmdsts); 2082 2083 #ifdef __NO_STRICT_ALIGNMENT 2084 /* 2085 * If the packet is small enough to fit in a 2086 * single header mbuf, allocate one and copy 2087 * the data into it. This greatly reduces 2088 * memory consumption when we receive lots 2089 * of small packets. 2090 * 2091 * Otherwise, we add a new buffer to the receive 2092 * chain. If this fails, we drop the packet and 2093 * recycle the old buffer. 2094 */ 2095 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 2096 MGETHDR(m, M_DONTWAIT, MT_DATA); 2097 if (m == NULL) 2098 goto dropit; 2099 memcpy(mtod(m, caddr_t), 2100 mtod(rxs->rxs_mbuf, caddr_t), len); 2101 SIP_INIT_RXDESC(sc, i); 2102 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2103 rxs->rxs_dmamap->dm_mapsize, 2104 BUS_DMASYNC_PREREAD); 2105 } else { 2106 m = rxs->rxs_mbuf; 2107 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 2108 dropit: 2109 ifp->if_ierrors++; 2110 SIP_INIT_RXDESC(sc, i); 2111 bus_dmamap_sync(sc->sc_dmat, 2112 rxs->rxs_dmamap, 0, 2113 rxs->rxs_dmamap->dm_mapsize, 2114 BUS_DMASYNC_PREREAD); 2115 continue; 2116 } 2117 } 2118 #else 2119 /* 2120 * The SiS 900's receive buffers must be 4-byte aligned. 2121 * But this means that the data after the Ethernet header 2122 * is misaligned. We must allocate a new buffer and 2123 * copy the data, shifted forward 2 bytes. 2124 */ 2125 MGETHDR(m, M_DONTWAIT, MT_DATA); 2126 if (m == NULL) { 2127 dropit: 2128 ifp->if_ierrors++; 2129 SIP_INIT_RXDESC(sc, i); 2130 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2131 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2132 continue; 2133 } 2134 if (len > (MHLEN - 2)) { 2135 MCLGET(m, M_DONTWAIT); 2136 if ((m->m_flags & M_EXT) == 0) { 2137 m_freem(m); 2138 goto dropit; 2139 } 2140 } 2141 m->m_data += 2; 2142 2143 /* 2144 * Note that we use clusters for incoming frames, so the 2145 * buffer is virtually contiguous. 2146 */ 2147 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 2148 2149 /* Allow the receive descriptor to continue using its mbuf. */ 2150 SIP_INIT_RXDESC(sc, i); 2151 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2152 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2153 #endif /* __NO_STRICT_ALIGNMENT */ 2154 2155 ifp->if_ipackets++; 2156 m->m_flags |= M_HASFCS; 2157 m->m_pkthdr.rcvif = ifp; 2158 m->m_pkthdr.len = m->m_len = len; 2159 2160 #if NBPFILTER > 0 2161 /* 2162 * Pass this up to any BPF listeners, but only 2163 * pass if up the stack if it's for us. 2164 */ 2165 if (ifp->if_bpf) 2166 bpf_mtap(ifp->if_bpf, m); 2167 #endif /* NBPFILTER > 0 */ 2168 2169 /* Pass it on. */ 2170 (*ifp->if_input)(ifp, m); 2171 } 2172 2173 /* Update the receive pointer. */ 2174 sc->sc_rxptr = i; 2175 } 2176 #endif /* DP83820 */ 2177 2178 /* 2179 * sip_tick: 2180 * 2181 * One second timer, used to tick the MII. 2182 */ 2183 void 2184 SIP_DECL(tick)(void *arg) 2185 { 2186 struct sip_softc *sc = arg; 2187 int s; 2188 2189 s = splnet(); 2190 mii_tick(&sc->sc_mii); 2191 splx(s); 2192 2193 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2194 } 2195 2196 /* 2197 * sip_reset: 2198 * 2199 * Perform a soft reset on the SiS 900. 2200 */ 2201 void 2202 SIP_DECL(reset)(struct sip_softc *sc) 2203 { 2204 bus_space_tag_t st = sc->sc_st; 2205 bus_space_handle_t sh = sc->sc_sh; 2206 int i; 2207 2208 bus_space_write_4(st, sh, SIP_IER, 0); 2209 bus_space_write_4(st, sh, SIP_IMR, 0); 2210 bus_space_write_4(st, sh, SIP_RFCR, 0); 2211 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2212 2213 for (i = 0; i < SIP_TIMEOUT; i++) { 2214 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2215 break; 2216 delay(2); 2217 } 2218 2219 if (i == SIP_TIMEOUT) 2220 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2221 2222 delay(1000); 2223 2224 #ifdef DP83820 2225 /* 2226 * Set the general purpose I/O bits. Do it here in case we 2227 * need to have GPIO set up to talk to the media interface. 2228 */ 2229 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2230 delay(1000); 2231 #endif /* DP83820 */ 2232 } 2233 2234 /* 2235 * sip_init: [ ifnet interface function ] 2236 * 2237 * Initialize the interface. Must be called at splnet(). 2238 */ 2239 int 2240 SIP_DECL(init)(struct ifnet *ifp) 2241 { 2242 struct sip_softc *sc = ifp->if_softc; 2243 bus_space_tag_t st = sc->sc_st; 2244 bus_space_handle_t sh = sc->sc_sh; 2245 struct sip_txsoft *txs; 2246 struct sip_rxsoft *rxs; 2247 struct sip_desc *sipd; 2248 #if defined(DP83820) 2249 u_int32_t reg; 2250 #endif 2251 int i, error = 0; 2252 2253 /* 2254 * Cancel any pending I/O. 2255 */ 2256 SIP_DECL(stop)(ifp, 0); 2257 2258 /* 2259 * Reset the chip to a known state. 2260 */ 2261 SIP_DECL(reset)(sc); 2262 2263 #if !defined(DP83820) 2264 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2265 /* 2266 * DP83815 manual, page 78: 2267 * 4.4 Recommended Registers Configuration 2268 * For optimum performance of the DP83815, version noted 2269 * as DP83815CVNG (SRR = 203h), the listed register 2270 * modifications must be followed in sequence... 2271 * 2272 * It's not clear if this should be 302h or 203h because that 2273 * chip name is listed as SRR 302h in the description of the 2274 * SRR register. However, my revision 302h DP83815 on the 2275 * Netgear FA311 purchased in 02/2001 needs these settings 2276 * to avoid tons of errors in AcceptPerfectMatch (non- 2277 * IFF_PROMISC) mode. I do not know if other revisions need 2278 * this set or not. [briggs -- 09 March 2001] 2279 * 2280 * Note that only the low-order 12 bits of 0xe4 are documented 2281 * and that this sets reserved bits in that register. 2282 */ 2283 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2284 2285 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2286 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2287 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2288 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2289 2290 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2291 } 2292 #endif /* ! DP83820 */ 2293 2294 /* 2295 * Initialize the transmit descriptor ring. 2296 */ 2297 for (i = 0; i < SIP_NTXDESC; i++) { 2298 sipd = &sc->sc_txdescs[i]; 2299 memset(sipd, 0, sizeof(struct sip_desc)); 2300 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2301 } 2302 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2303 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2304 sc->sc_txfree = SIP_NTXDESC; 2305 sc->sc_txnext = 0; 2306 sc->sc_txwin = 0; 2307 2308 /* 2309 * Initialize the transmit job descriptors. 2310 */ 2311 SIMPLEQ_INIT(&sc->sc_txfreeq); 2312 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2313 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2314 txs = &sc->sc_txsoft[i]; 2315 txs->txs_mbuf = NULL; 2316 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2317 } 2318 2319 /* 2320 * Initialize the receive descriptor and receive job 2321 * descriptor rings. 2322 */ 2323 for (i = 0; i < SIP_NRXDESC; i++) { 2324 rxs = &sc->sc_rxsoft[i]; 2325 if (rxs->rxs_mbuf == NULL) { 2326 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2327 printf("%s: unable to allocate or map rx " 2328 "buffer %d, error = %d\n", 2329 sc->sc_dev.dv_xname, i, error); 2330 /* 2331 * XXX Should attempt to run with fewer receive 2332 * XXX buffers instead of just failing. 2333 */ 2334 SIP_DECL(rxdrain)(sc); 2335 goto out; 2336 } 2337 } else 2338 SIP_INIT_RXDESC(sc, i); 2339 } 2340 sc->sc_rxptr = 0; 2341 #ifdef DP83820 2342 sc->sc_rxdiscard = 0; 2343 SIP_RXCHAIN_RESET(sc); 2344 #endif /* DP83820 */ 2345 2346 /* 2347 * Set the configuration register; it's already initialized 2348 * in sip_attach(). 2349 */ 2350 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2351 2352 /* 2353 * Initialize the prototype TXCFG register. 2354 */ 2355 #if defined(DP83820) 2356 sc->sc_txcfg = TXCFG_MXDMA_512; 2357 sc->sc_rxcfg = RXCFG_MXDMA_512; 2358 #else 2359 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2360 SIP_SIS900_REV(sc, SIS_REV_960) || 2361 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2362 (sc->sc_cfg & CFG_EDBMASTEN)) { 2363 sc->sc_txcfg = TXCFG_MXDMA_64; 2364 sc->sc_rxcfg = RXCFG_MXDMA_64; 2365 } else { 2366 sc->sc_txcfg = TXCFG_MXDMA_512; 2367 sc->sc_rxcfg = RXCFG_MXDMA_512; 2368 } 2369 #endif /* DP83820 */ 2370 2371 sc->sc_txcfg |= TXCFG_ATP | 2372 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2373 sc->sc_tx_drain_thresh; 2374 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2375 2376 /* 2377 * Initialize the receive drain threshold if we have never 2378 * done so. 2379 */ 2380 if (sc->sc_rx_drain_thresh == 0) { 2381 /* 2382 * XXX This value should be tuned. This is set to the 2383 * maximum of 248 bytes, and we may be able to improve 2384 * performance by decreasing it (although we should never 2385 * set this value lower than 2; 14 bytes are required to 2386 * filter the packet). 2387 */ 2388 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2389 } 2390 2391 /* 2392 * Initialize the prototype RXCFG register. 2393 */ 2394 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2395 #ifdef DP83820 2396 /* 2397 * Accept long packets (including FCS) so we can handle 2398 * 802.1q-tagged frames and jumbo frames properly. 2399 */ 2400 if (ifp->if_mtu > ETHERMTU || 2401 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2402 sc->sc_rxcfg |= RXCFG_ALP; 2403 2404 /* 2405 * Checksum offloading is disabled if the user selects an MTU 2406 * larger than 8109. (FreeBSD says 8152, but there is emperical 2407 * evidence that >8109 does not work on some boards, such as the 2408 * Planex GN-1000TE). 2409 */ 2410 if (ifp->if_mtu > 8109 && 2411 (ifp->if_capenable & 2412 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4))) { 2413 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2414 "disabled.\n", sc->sc_dev.dv_xname); 2415 ifp->if_capenable &= ~(IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4| 2416 IFCAP_CSUM_UDPv4); 2417 ifp->if_csum_flags_tx = 0; 2418 ifp->if_csum_flags_rx = 0; 2419 } 2420 #else 2421 /* 2422 * Accept packets >1518 bytes (including FCS) so we can handle 2423 * 802.1q-tagged frames properly. 2424 */ 2425 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2426 sc->sc_rxcfg |= RXCFG_ALP; 2427 #endif 2428 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2429 2430 #ifdef DP83820 2431 /* 2432 * Initialize the VLAN/IP receive control register. 2433 * We enable checksum computation on all incoming 2434 * packets, and do not reject packets w/ bad checksums. 2435 */ 2436 reg = 0; 2437 if (ifp->if_capenable & 2438 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2439 reg |= VRCR_IPEN; 2440 if (sc->sc_ethercom.ec_nvlans != 0) 2441 reg |= VRCR_VTDEN|VRCR_VTREN; 2442 bus_space_write_4(st, sh, SIP_VRCR, reg); 2443 2444 /* 2445 * Initialize the VLAN/IP transmit control register. 2446 * We enable outgoing checksum computation on a 2447 * per-packet basis. 2448 */ 2449 reg = 0; 2450 if (ifp->if_capenable & 2451 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2452 reg |= VTCR_PPCHK; 2453 if (sc->sc_ethercom.ec_nvlans != 0) 2454 reg |= VTCR_VPPTI; 2455 bus_space_write_4(st, sh, SIP_VTCR, reg); 2456 2457 /* 2458 * If we're using VLANs, initialize the VLAN data register. 2459 * To understand why we bswap the VLAN Ethertype, see section 2460 * 4.2.36 of the DP83820 manual. 2461 */ 2462 if (sc->sc_ethercom.ec_nvlans != 0) 2463 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2464 #endif /* DP83820 */ 2465 2466 /* 2467 * Give the transmit and receive rings to the chip. 2468 */ 2469 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2470 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2471 2472 /* 2473 * Initialize the interrupt mask. 2474 */ 2475 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2476 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2477 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2478 2479 /* Set up the receive filter. */ 2480 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2481 2482 #ifdef DP83820 2483 /* 2484 * Tune sc_rx_flow_thresh. 2485 * XXX "More than 8KB" is too short for jumbo frames. 2486 * XXX TODO: Threshold value should be user-settable. 2487 */ 2488 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2489 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2490 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2491 #endif 2492 2493 /* 2494 * Set the current media. Do this after initializing the prototype 2495 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2496 * control. 2497 */ 2498 mii_mediachg(&sc->sc_mii); 2499 2500 #ifdef DP83820 2501 /* 2502 * Set the interrupt hold-off timer to 100us. 2503 */ 2504 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2505 #endif 2506 2507 /* 2508 * Enable interrupts. 2509 */ 2510 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2511 2512 /* 2513 * Start the transmit and receive processes. 2514 */ 2515 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2516 2517 /* 2518 * Start the one second MII clock. 2519 */ 2520 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2521 2522 /* 2523 * ...all done! 2524 */ 2525 ifp->if_flags |= IFF_RUNNING; 2526 ifp->if_flags &= ~IFF_OACTIVE; 2527 2528 out: 2529 if (error) 2530 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2531 return (error); 2532 } 2533 2534 /* 2535 * sip_drain: 2536 * 2537 * Drain the receive queue. 2538 */ 2539 void 2540 SIP_DECL(rxdrain)(struct sip_softc *sc) 2541 { 2542 struct sip_rxsoft *rxs; 2543 int i; 2544 2545 for (i = 0; i < SIP_NRXDESC; i++) { 2546 rxs = &sc->sc_rxsoft[i]; 2547 if (rxs->rxs_mbuf != NULL) { 2548 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2549 m_freem(rxs->rxs_mbuf); 2550 rxs->rxs_mbuf = NULL; 2551 } 2552 } 2553 } 2554 2555 /* 2556 * sip_stop: [ ifnet interface function ] 2557 * 2558 * Stop transmission on the interface. 2559 */ 2560 void 2561 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2562 { 2563 struct sip_softc *sc = ifp->if_softc; 2564 bus_space_tag_t st = sc->sc_st; 2565 bus_space_handle_t sh = sc->sc_sh; 2566 struct sip_txsoft *txs; 2567 u_int32_t cmdsts = 0; /* DEBUG */ 2568 2569 /* 2570 * Stop the one second clock. 2571 */ 2572 callout_stop(&sc->sc_tick_ch); 2573 2574 /* Down the MII. */ 2575 mii_down(&sc->sc_mii); 2576 2577 /* 2578 * Disable interrupts. 2579 */ 2580 bus_space_write_4(st, sh, SIP_IER, 0); 2581 2582 /* 2583 * Stop receiver and transmitter. 2584 */ 2585 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2586 2587 /* 2588 * Release any queued transmit buffers. 2589 */ 2590 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2591 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2592 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2593 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2594 CMDSTS_INTR) == 0) 2595 printf("%s: sip_stop: last descriptor does not " 2596 "have INTR bit set\n", sc->sc_dev.dv_xname); 2597 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2598 #ifdef DIAGNOSTIC 2599 if (txs->txs_mbuf == NULL) { 2600 printf("%s: dirty txsoft with no mbuf chain\n", 2601 sc->sc_dev.dv_xname); 2602 panic("sip_stop"); 2603 } 2604 #endif 2605 cmdsts |= /* DEBUG */ 2606 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2607 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2608 m_freem(txs->txs_mbuf); 2609 txs->txs_mbuf = NULL; 2610 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2611 } 2612 2613 if (disable) 2614 SIP_DECL(rxdrain)(sc); 2615 2616 /* 2617 * Mark the interface down and cancel the watchdog timer. 2618 */ 2619 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2620 ifp->if_timer = 0; 2621 2622 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2623 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2624 printf("%s: sip_stop: no INTR bits set in dirty tx " 2625 "descriptors\n", sc->sc_dev.dv_xname); 2626 } 2627 2628 /* 2629 * sip_read_eeprom: 2630 * 2631 * Read data from the serial EEPROM. 2632 */ 2633 void 2634 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2635 u_int16_t *data) 2636 { 2637 bus_space_tag_t st = sc->sc_st; 2638 bus_space_handle_t sh = sc->sc_sh; 2639 u_int16_t reg; 2640 int i, x; 2641 2642 for (i = 0; i < wordcnt; i++) { 2643 /* Send CHIP SELECT. */ 2644 reg = EROMAR_EECS; 2645 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2646 2647 /* Shift in the READ opcode. */ 2648 for (x = 3; x > 0; x--) { 2649 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2650 reg |= EROMAR_EEDI; 2651 else 2652 reg &= ~EROMAR_EEDI; 2653 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2654 bus_space_write_4(st, sh, SIP_EROMAR, 2655 reg | EROMAR_EESK); 2656 delay(4); 2657 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2658 delay(4); 2659 } 2660 2661 /* Shift in address. */ 2662 for (x = 6; x > 0; x--) { 2663 if ((word + i) & (1 << (x - 1))) 2664 reg |= EROMAR_EEDI; 2665 else 2666 reg &= ~EROMAR_EEDI; 2667 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2668 bus_space_write_4(st, sh, SIP_EROMAR, 2669 reg | EROMAR_EESK); 2670 delay(4); 2671 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2672 delay(4); 2673 } 2674 2675 /* Shift out data. */ 2676 reg = EROMAR_EECS; 2677 data[i] = 0; 2678 for (x = 16; x > 0; x--) { 2679 bus_space_write_4(st, sh, SIP_EROMAR, 2680 reg | EROMAR_EESK); 2681 delay(4); 2682 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2683 data[i] |= (1 << (x - 1)); 2684 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2685 delay(4); 2686 } 2687 2688 /* Clear CHIP SELECT. */ 2689 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2690 delay(4); 2691 } 2692 } 2693 2694 /* 2695 * sip_add_rxbuf: 2696 * 2697 * Add a receive buffer to the indicated descriptor. 2698 */ 2699 int 2700 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2701 { 2702 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2703 struct mbuf *m; 2704 int error; 2705 2706 MGETHDR(m, M_DONTWAIT, MT_DATA); 2707 if (m == NULL) 2708 return (ENOBUFS); 2709 2710 MCLGET(m, M_DONTWAIT); 2711 if ((m->m_flags & M_EXT) == 0) { 2712 m_freem(m); 2713 return (ENOBUFS); 2714 } 2715 2716 #if defined(DP83820) 2717 m->m_len = SIP_RXBUF_LEN; 2718 #endif /* DP83820 */ 2719 2720 if (rxs->rxs_mbuf != NULL) 2721 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2722 2723 rxs->rxs_mbuf = m; 2724 2725 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2726 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2727 BUS_DMA_READ|BUS_DMA_NOWAIT); 2728 if (error) { 2729 printf("%s: can't load rx DMA map %d, error = %d\n", 2730 sc->sc_dev.dv_xname, idx, error); 2731 panic("sip_add_rxbuf"); /* XXX */ 2732 } 2733 2734 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2735 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2736 2737 SIP_INIT_RXDESC(sc, idx); 2738 2739 return (0); 2740 } 2741 2742 #if !defined(DP83820) 2743 /* 2744 * sip_sis900_set_filter: 2745 * 2746 * Set up the receive filter. 2747 */ 2748 void 2749 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2750 { 2751 bus_space_tag_t st = sc->sc_st; 2752 bus_space_handle_t sh = sc->sc_sh; 2753 struct ethercom *ec = &sc->sc_ethercom; 2754 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2755 struct ether_multi *enm; 2756 u_int8_t *cp; 2757 struct ether_multistep step; 2758 u_int32_t crc, mchash[16]; 2759 2760 /* 2761 * Initialize the prototype RFCR. 2762 */ 2763 sc->sc_rfcr = RFCR_RFEN; 2764 if (ifp->if_flags & IFF_BROADCAST) 2765 sc->sc_rfcr |= RFCR_AAB; 2766 if (ifp->if_flags & IFF_PROMISC) { 2767 sc->sc_rfcr |= RFCR_AAP; 2768 goto allmulti; 2769 } 2770 2771 /* 2772 * Set up the multicast address filter by passing all multicast 2773 * addresses through a CRC generator, and then using the high-order 2774 * 6 bits as an index into the 128 bit multicast hash table (only 2775 * the lower 16 bits of each 32 bit multicast hash register are 2776 * valid). The high order bits select the register, while the 2777 * rest of the bits select the bit within the register. 2778 */ 2779 2780 memset(mchash, 0, sizeof(mchash)); 2781 2782 /* 2783 * SiS900 (at least SiS963) requires us to register the address of 2784 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 2785 */ 2786 crc = 0x0ed423f9; 2787 2788 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2789 SIP_SIS900_REV(sc, SIS_REV_960) || 2790 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2791 /* Just want the 8 most significant bits. */ 2792 crc >>= 24; 2793 } else { 2794 /* Just want the 7 most significant bits. */ 2795 crc >>= 25; 2796 } 2797 2798 /* Set the corresponding bit in the hash table. */ 2799 mchash[crc >> 4] |= 1 << (crc & 0xf); 2800 2801 ETHER_FIRST_MULTI(step, ec, enm); 2802 while (enm != NULL) { 2803 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2804 /* 2805 * We must listen to a range of multicast addresses. 2806 * For now, just accept all multicasts, rather than 2807 * trying to set only those filter bits needed to match 2808 * the range. (At this time, the only use of address 2809 * ranges is for IP multicast routing, for which the 2810 * range is big enough to require all bits set.) 2811 */ 2812 goto allmulti; 2813 } 2814 2815 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2816 2817 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2818 SIP_SIS900_REV(sc, SIS_REV_960) || 2819 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2820 /* Just want the 8 most significant bits. */ 2821 crc >>= 24; 2822 } else { 2823 /* Just want the 7 most significant bits. */ 2824 crc >>= 25; 2825 } 2826 2827 /* Set the corresponding bit in the hash table. */ 2828 mchash[crc >> 4] |= 1 << (crc & 0xf); 2829 2830 ETHER_NEXT_MULTI(step, enm); 2831 } 2832 2833 ifp->if_flags &= ~IFF_ALLMULTI; 2834 goto setit; 2835 2836 allmulti: 2837 ifp->if_flags |= IFF_ALLMULTI; 2838 sc->sc_rfcr |= RFCR_AAM; 2839 2840 setit: 2841 #define FILTER_EMIT(addr, data) \ 2842 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2843 delay(1); \ 2844 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2845 delay(1) 2846 2847 /* 2848 * Disable receive filter, and program the node address. 2849 */ 2850 cp = LLADDR(ifp->if_sadl); 2851 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2852 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2853 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2854 2855 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2856 /* 2857 * Program the multicast hash table. 2858 */ 2859 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2860 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2861 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2862 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2863 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2864 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2865 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2866 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2867 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2868 SIP_SIS900_REV(sc, SIS_REV_960) || 2869 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2870 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2871 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2872 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2873 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2874 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2875 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2876 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2877 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2878 } 2879 } 2880 #undef FILTER_EMIT 2881 2882 /* 2883 * Re-enable the receiver filter. 2884 */ 2885 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2886 } 2887 #endif /* ! DP83820 */ 2888 2889 /* 2890 * sip_dp83815_set_filter: 2891 * 2892 * Set up the receive filter. 2893 */ 2894 void 2895 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2896 { 2897 bus_space_tag_t st = sc->sc_st; 2898 bus_space_handle_t sh = sc->sc_sh; 2899 struct ethercom *ec = &sc->sc_ethercom; 2900 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2901 struct ether_multi *enm; 2902 u_int8_t *cp; 2903 struct ether_multistep step; 2904 u_int32_t crc, hash, slot, bit; 2905 #ifdef DP83820 2906 #define MCHASH_NWORDS 128 2907 #else 2908 #define MCHASH_NWORDS 32 2909 #endif /* DP83820 */ 2910 u_int16_t mchash[MCHASH_NWORDS]; 2911 int i; 2912 2913 /* 2914 * Initialize the prototype RFCR. 2915 * Enable the receive filter, and accept on 2916 * Perfect (destination address) Match 2917 * If IFF_BROADCAST, also accept all broadcast packets. 2918 * If IFF_PROMISC, accept all unicast packets (and later, set 2919 * IFF_ALLMULTI and accept all multicast, too). 2920 */ 2921 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2922 if (ifp->if_flags & IFF_BROADCAST) 2923 sc->sc_rfcr |= RFCR_AAB; 2924 if (ifp->if_flags & IFF_PROMISC) { 2925 sc->sc_rfcr |= RFCR_AAP; 2926 goto allmulti; 2927 } 2928 2929 #ifdef DP83820 2930 /* 2931 * Set up the DP83820 multicast address filter by passing all multicast 2932 * addresses through a CRC generator, and then using the high-order 2933 * 11 bits as an index into the 2048 bit multicast hash table. The 2934 * high-order 7 bits select the slot, while the low-order 4 bits 2935 * select the bit within the slot. Note that only the low 16-bits 2936 * of each filter word are used, and there are 128 filter words. 2937 */ 2938 #else 2939 /* 2940 * Set up the DP83815 multicast address filter by passing all multicast 2941 * addresses through a CRC generator, and then using the high-order 2942 * 9 bits as an index into the 512 bit multicast hash table. The 2943 * high-order 5 bits select the slot, while the low-order 4 bits 2944 * select the bit within the slot. Note that only the low 16-bits 2945 * of each filter word are used, and there are 32 filter words. 2946 */ 2947 #endif /* DP83820 */ 2948 2949 memset(mchash, 0, sizeof(mchash)); 2950 2951 ifp->if_flags &= ~IFF_ALLMULTI; 2952 ETHER_FIRST_MULTI(step, ec, enm); 2953 if (enm == NULL) 2954 goto setit; 2955 while (enm != NULL) { 2956 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2957 /* 2958 * We must listen to a range of multicast addresses. 2959 * For now, just accept all multicasts, rather than 2960 * trying to set only those filter bits needed to match 2961 * the range. (At this time, the only use of address 2962 * ranges is for IP multicast routing, for which the 2963 * range is big enough to require all bits set.) 2964 */ 2965 goto allmulti; 2966 } 2967 2968 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2969 2970 #ifdef DP83820 2971 /* Just want the 11 most significant bits. */ 2972 hash = crc >> 21; 2973 #else 2974 /* Just want the 9 most significant bits. */ 2975 hash = crc >> 23; 2976 #endif /* DP83820 */ 2977 2978 slot = hash >> 4; 2979 bit = hash & 0xf; 2980 2981 /* Set the corresponding bit in the hash table. */ 2982 mchash[slot] |= 1 << bit; 2983 2984 ETHER_NEXT_MULTI(step, enm); 2985 } 2986 sc->sc_rfcr |= RFCR_MHEN; 2987 goto setit; 2988 2989 allmulti: 2990 ifp->if_flags |= IFF_ALLMULTI; 2991 sc->sc_rfcr |= RFCR_AAM; 2992 2993 setit: 2994 #define FILTER_EMIT(addr, data) \ 2995 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2996 delay(1); \ 2997 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2998 delay(1) 2999 3000 /* 3001 * Disable receive filter, and program the node address. 3002 */ 3003 cp = LLADDR(ifp->if_sadl); 3004 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3005 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3006 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3007 3008 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3009 /* 3010 * Program the multicast hash table. 3011 */ 3012 for (i = 0; i < MCHASH_NWORDS; i++) { 3013 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 3014 mchash[i]); 3015 } 3016 } 3017 #undef FILTER_EMIT 3018 #undef MCHASH_NWORDS 3019 3020 /* 3021 * Re-enable the receiver filter. 3022 */ 3023 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3024 } 3025 3026 #if defined(DP83820) 3027 /* 3028 * sip_dp83820_mii_readreg: [mii interface function] 3029 * 3030 * Read a PHY register on the MII of the DP83820. 3031 */ 3032 int 3033 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 3034 { 3035 struct sip_softc *sc = (void *) self; 3036 3037 if (sc->sc_cfg & CFG_TBI_EN) { 3038 bus_addr_t tbireg; 3039 int rv; 3040 3041 if (phy != 0) 3042 return (0); 3043 3044 switch (reg) { 3045 case MII_BMCR: tbireg = SIP_TBICR; break; 3046 case MII_BMSR: tbireg = SIP_TBISR; break; 3047 case MII_ANAR: tbireg = SIP_TANAR; break; 3048 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3049 case MII_ANER: tbireg = SIP_TANER; break; 3050 case MII_EXTSR: 3051 /* 3052 * Don't even bother reading the TESR register. 3053 * The manual documents that the device has 3054 * 1000baseX full/half capability, but the 3055 * register itself seems read back 0 on some 3056 * boards. Just hard-code the result. 3057 */ 3058 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3059 3060 default: 3061 return (0); 3062 } 3063 3064 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3065 if (tbireg == SIP_TBISR) { 3066 /* LINK and ACOMP are switched! */ 3067 int val = rv; 3068 3069 rv = 0; 3070 if (val & TBISR_MR_LINK_STATUS) 3071 rv |= BMSR_LINK; 3072 if (val & TBISR_MR_AN_COMPLETE) 3073 rv |= BMSR_ACOMP; 3074 3075 /* 3076 * The manual claims this register reads back 0 3077 * on hard and soft reset. But we want to let 3078 * the gentbi driver know that we support auto- 3079 * negotiation, so hard-code this bit in the 3080 * result. 3081 */ 3082 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3083 } 3084 3085 return (rv); 3086 } 3087 3088 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3089 phy, reg)); 3090 } 3091 3092 /* 3093 * sip_dp83820_mii_writereg: [mii interface function] 3094 * 3095 * Write a PHY register on the MII of the DP83820. 3096 */ 3097 void 3098 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 3099 { 3100 struct sip_softc *sc = (void *) self; 3101 3102 if (sc->sc_cfg & CFG_TBI_EN) { 3103 bus_addr_t tbireg; 3104 3105 if (phy != 0) 3106 return; 3107 3108 switch (reg) { 3109 case MII_BMCR: tbireg = SIP_TBICR; break; 3110 case MII_ANAR: tbireg = SIP_TANAR; break; 3111 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3112 default: 3113 return; 3114 } 3115 3116 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3117 return; 3118 } 3119 3120 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3121 phy, reg, val); 3122 } 3123 3124 /* 3125 * sip_dp83820_mii_statchg: [mii interface function] 3126 * 3127 * Callback from MII layer when media changes. 3128 */ 3129 void 3130 SIP_DECL(dp83820_mii_statchg)(struct device *self) 3131 { 3132 struct sip_softc *sc = (struct sip_softc *) self; 3133 struct mii_data *mii = &sc->sc_mii; 3134 u_int32_t cfg, pcr; 3135 3136 /* 3137 * Get flow control negotiation result. 3138 */ 3139 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3140 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3141 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3142 mii->mii_media_active &= ~IFM_ETH_FMASK; 3143 } 3144 3145 /* 3146 * Update TXCFG for full-duplex operation. 3147 */ 3148 if ((mii->mii_media_active & IFM_FDX) != 0) 3149 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3150 else 3151 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3152 3153 /* 3154 * Update RXCFG for full-duplex or loopback. 3155 */ 3156 if ((mii->mii_media_active & IFM_FDX) != 0 || 3157 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3158 sc->sc_rxcfg |= RXCFG_ATX; 3159 else 3160 sc->sc_rxcfg &= ~RXCFG_ATX; 3161 3162 /* 3163 * Update CFG for MII/GMII. 3164 */ 3165 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3166 cfg = sc->sc_cfg | CFG_MODE_1000; 3167 else 3168 cfg = sc->sc_cfg; 3169 3170 /* 3171 * 802.3x flow control. 3172 */ 3173 pcr = 0; 3174 if (sc->sc_flowflags & IFM_FLOW) { 3175 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3176 pcr |= sc->sc_rx_flow_thresh; 3177 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3178 pcr |= PCR_PSEN | PCR_PS_MCAST; 3179 } 3180 3181 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3182 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3183 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3184 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3185 } 3186 #endif /* ! DP83820 */ 3187 3188 /* 3189 * sip_mii_bitbang_read: [mii bit-bang interface function] 3190 * 3191 * Read the MII serial port for the MII bit-bang module. 3192 */ 3193 u_int32_t 3194 SIP_DECL(mii_bitbang_read)(struct device *self) 3195 { 3196 struct sip_softc *sc = (void *) self; 3197 3198 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3199 } 3200 3201 /* 3202 * sip_mii_bitbang_write: [mii big-bang interface function] 3203 * 3204 * Write the MII serial port for the MII bit-bang module. 3205 */ 3206 void 3207 SIP_DECL(mii_bitbang_write)(struct device *self, u_int32_t val) 3208 { 3209 struct sip_softc *sc = (void *) self; 3210 3211 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3212 } 3213 3214 #ifndef DP83820 3215 /* 3216 * sip_sis900_mii_readreg: [mii interface function] 3217 * 3218 * Read a PHY register on the MII. 3219 */ 3220 int 3221 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 3222 { 3223 struct sip_softc *sc = (struct sip_softc *) self; 3224 u_int32_t enphy; 3225 3226 /* 3227 * The PHY of recent SiS chipsets is accessed through bitbang 3228 * operations. 3229 */ 3230 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3231 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3232 phy, reg)); 3233 3234 #ifndef SIS900_MII_RESTRICT 3235 /* 3236 * The SiS 900 has only an internal PHY on the MII. Only allow 3237 * MII address 0. 3238 */ 3239 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3240 return (0); 3241 #endif 3242 3243 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3244 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3245 ENPHY_RWCMD | ENPHY_ACCESS); 3246 do { 3247 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3248 } while (enphy & ENPHY_ACCESS); 3249 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3250 } 3251 3252 /* 3253 * sip_sis900_mii_writereg: [mii interface function] 3254 * 3255 * Write a PHY register on the MII. 3256 */ 3257 void 3258 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 3259 { 3260 struct sip_softc *sc = (struct sip_softc *) self; 3261 u_int32_t enphy; 3262 3263 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3264 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3265 phy, reg, val); 3266 return; 3267 } 3268 3269 #ifndef SIS900_MII_RESTRICT 3270 /* 3271 * The SiS 900 has only an internal PHY on the MII. Only allow 3272 * MII address 0. 3273 */ 3274 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3275 return; 3276 #endif 3277 3278 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3279 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3280 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3281 do { 3282 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3283 } while (enphy & ENPHY_ACCESS); 3284 } 3285 3286 /* 3287 * sip_sis900_mii_statchg: [mii interface function] 3288 * 3289 * Callback from MII layer when media changes. 3290 */ 3291 void 3292 SIP_DECL(sis900_mii_statchg)(struct device *self) 3293 { 3294 struct sip_softc *sc = (struct sip_softc *) self; 3295 struct mii_data *mii = &sc->sc_mii; 3296 u_int32_t flowctl; 3297 3298 /* 3299 * Get flow control negotiation result. 3300 */ 3301 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3302 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3303 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3304 mii->mii_media_active &= ~IFM_ETH_FMASK; 3305 } 3306 3307 /* 3308 * Update TXCFG for full-duplex operation. 3309 */ 3310 if ((mii->mii_media_active & IFM_FDX) != 0) 3311 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3312 else 3313 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3314 3315 /* 3316 * Update RXCFG for full-duplex or loopback. 3317 */ 3318 if ((mii->mii_media_active & IFM_FDX) != 0 || 3319 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3320 sc->sc_rxcfg |= RXCFG_ATX; 3321 else 3322 sc->sc_rxcfg &= ~RXCFG_ATX; 3323 3324 /* 3325 * Update IMR for use of 802.3x flow control. 3326 */ 3327 if (sc->sc_flowflags & IFM_FLOW) { 3328 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3329 flowctl = FLOWCTL_FLOWEN; 3330 } else { 3331 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3332 flowctl = 0; 3333 } 3334 3335 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3336 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3337 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3338 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3339 } 3340 3341 /* 3342 * sip_dp83815_mii_readreg: [mii interface function] 3343 * 3344 * Read a PHY register on the MII. 3345 */ 3346 int 3347 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 3348 { 3349 struct sip_softc *sc = (struct sip_softc *) self; 3350 u_int32_t val; 3351 3352 /* 3353 * The DP83815 only has an internal PHY. Only allow 3354 * MII address 0. 3355 */ 3356 if (phy != 0) 3357 return (0); 3358 3359 /* 3360 * Apparently, after a reset, the DP83815 can take a while 3361 * to respond. During this recovery period, the BMSR returns 3362 * a value of 0. Catch this -- it's not supposed to happen 3363 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3364 * PHY to come back to life. 3365 * 3366 * This works out because the BMSR is the first register 3367 * read during the PHY probe process. 3368 */ 3369 do { 3370 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3371 } while (reg == MII_BMSR && val == 0); 3372 3373 return (val & 0xffff); 3374 } 3375 3376 /* 3377 * sip_dp83815_mii_writereg: [mii interface function] 3378 * 3379 * Write a PHY register to the MII. 3380 */ 3381 void 3382 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3383 { 3384 struct sip_softc *sc = (struct sip_softc *) self; 3385 3386 /* 3387 * The DP83815 only has an internal PHY. Only allow 3388 * MII address 0. 3389 */ 3390 if (phy != 0) 3391 return; 3392 3393 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3394 } 3395 3396 /* 3397 * sip_dp83815_mii_statchg: [mii interface function] 3398 * 3399 * Callback from MII layer when media changes. 3400 */ 3401 void 3402 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3403 { 3404 struct sip_softc *sc = (struct sip_softc *) self; 3405 3406 /* 3407 * Update TXCFG for full-duplex operation. 3408 */ 3409 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3410 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3411 else 3412 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3413 3414 /* 3415 * Update RXCFG for full-duplex or loopback. 3416 */ 3417 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3418 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3419 sc->sc_rxcfg |= RXCFG_ATX; 3420 else 3421 sc->sc_rxcfg &= ~RXCFG_ATX; 3422 3423 /* 3424 * XXX 802.3x flow control. 3425 */ 3426 3427 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3428 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3429 3430 /* 3431 * Some DP83815s experience problems when used with short 3432 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3433 * sequence adjusts the DSP's signal attenuation to fix the 3434 * problem. 3435 */ 3436 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3437 uint32_t reg; 3438 3439 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3440 3441 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3442 reg &= 0x0fff; 3443 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3444 delay(100); 3445 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3446 reg &= 0x00ff; 3447 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3448 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3449 0x00e8); 3450 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3451 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3452 reg | 0x20); 3453 } 3454 3455 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3456 } 3457 } 3458 #endif /* DP83820 */ 3459 3460 #if defined(DP83820) 3461 void 3462 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3463 const struct pci_attach_args *pa, u_int8_t *enaddr) 3464 { 3465 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3466 u_int8_t cksum, *e, match; 3467 int i; 3468 3469 /* 3470 * EEPROM data format for the DP83820 can be found in 3471 * the DP83820 manual, section 4.2.4. 3472 */ 3473 3474 SIP_DECL(read_eeprom)(sc, 0, 3475 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3476 3477 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3478 match = ~(match - 1); 3479 3480 cksum = 0x55; 3481 e = (u_int8_t *) eeprom_data; 3482 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3483 cksum += *e++; 3484 3485 if (cksum != match) 3486 printf("%s: Checksum (%x) mismatch (%x)", 3487 sc->sc_dev.dv_xname, cksum, match); 3488 3489 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3490 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3491 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3492 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3493 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3494 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3495 } 3496 #else /* ! DP83820 */ 3497 static void 3498 SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc) 3499 { 3500 int i; 3501 3502 /* 3503 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3504 * a reason, but I don't know it. 3505 */ 3506 for (i = 0; i < 10; i++) 3507 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3508 } 3509 3510 void 3511 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3512 const struct pci_attach_args *pa, u_int8_t *enaddr) 3513 { 3514 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3515 3516 switch (sc->sc_rev) { 3517 case SIS_REV_630S: 3518 case SIS_REV_630E: 3519 case SIS_REV_630EA1: 3520 case SIS_REV_630ET: 3521 case SIS_REV_635: 3522 /* 3523 * The MAC address for the on-board Ethernet of 3524 * the SiS 630 chipset is in the NVRAM. Kick 3525 * the chip into re-loading it from NVRAM, and 3526 * read the MAC address out of the filter registers. 3527 */ 3528 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3529 3530 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3531 RFCR_RFADDR_NODE0); 3532 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3533 0xffff; 3534 3535 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3536 RFCR_RFADDR_NODE2); 3537 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3538 0xffff; 3539 3540 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3541 RFCR_RFADDR_NODE4); 3542 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3543 0xffff; 3544 break; 3545 3546 case SIS_REV_960: 3547 { 3548 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3549 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3550 3551 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3552 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3553 3554 int waittime, i; 3555 3556 /* Allow to read EEPROM from LAN. It is shared 3557 * between a 1394 controller and the NIC and each 3558 * time we access it, we need to set SIS_EECMD_REQ. 3559 */ 3560 SIS_SET_EROMAR(sc, EROMAR_REQ); 3561 3562 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3563 /* Force EEPROM to idle state. */ 3564 3565 /* 3566 * XXX-cube This is ugly. I'll look for docs about it. 3567 */ 3568 SIS_SET_EROMAR(sc, EROMAR_EECS); 3569 SIP_DECL(sis900_eeprom_delay)(sc); 3570 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3571 SIS_SET_EROMAR(sc, EROMAR_EESK); 3572 SIP_DECL(sis900_eeprom_delay)(sc); 3573 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3574 SIP_DECL(sis900_eeprom_delay)(sc); 3575 } 3576 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3577 SIP_DECL(sis900_eeprom_delay)(sc); 3578 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3579 3580 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3581 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3582 sizeof(myea) / sizeof(myea[0]), myea); 3583 break; 3584 } 3585 DELAY(1); 3586 } 3587 3588 /* 3589 * Set SIS_EECTL_CLK to high, so a other master 3590 * can operate on the i2c bus. 3591 */ 3592 SIS_SET_EROMAR(sc, EROMAR_EESK); 3593 3594 /* Refuse EEPROM access by LAN */ 3595 SIS_SET_EROMAR(sc, EROMAR_DONE); 3596 } break; 3597 3598 default: 3599 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3600 sizeof(myea) / sizeof(myea[0]), myea); 3601 } 3602 3603 enaddr[0] = myea[0] & 0xff; 3604 enaddr[1] = myea[0] >> 8; 3605 enaddr[2] = myea[1] & 0xff; 3606 enaddr[3] = myea[1] >> 8; 3607 enaddr[4] = myea[2] & 0xff; 3608 enaddr[5] = myea[2] >> 8; 3609 } 3610 3611 /* Table and macro to bit-reverse an octet. */ 3612 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3613 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3614 3615 void 3616 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3617 const struct pci_attach_args *pa, u_int8_t *enaddr) 3618 { 3619 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3620 u_int8_t cksum, *e, match; 3621 int i; 3622 3623 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3624 sizeof(eeprom_data[0]), eeprom_data); 3625 3626 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3627 match = ~(match - 1); 3628 3629 cksum = 0x55; 3630 e = (u_int8_t *) eeprom_data; 3631 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3632 cksum += *e++; 3633 } 3634 if (cksum != match) { 3635 printf("%s: Checksum (%x) mismatch (%x)", 3636 sc->sc_dev.dv_xname, cksum, match); 3637 } 3638 3639 /* 3640 * Unrolled because it makes slightly more sense this way. 3641 * The DP83815 stores the MAC address in bit 0 of word 6 3642 * through bit 15 of word 8. 3643 */ 3644 ea = &eeprom_data[6]; 3645 enaddr[0] = ((*ea & 0x1) << 7); 3646 ea++; 3647 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3648 enaddr[1] = ((*ea & 0x1FE) >> 1); 3649 enaddr[2] = ((*ea & 0x1) << 7); 3650 ea++; 3651 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3652 enaddr[3] = ((*ea & 0x1FE) >> 1); 3653 enaddr[4] = ((*ea & 0x1) << 7); 3654 ea++; 3655 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3656 enaddr[5] = ((*ea & 0x1FE) >> 1); 3657 3658 /* 3659 * In case that's not weird enough, we also need to reverse 3660 * the bits in each byte. This all actually makes more sense 3661 * if you think about the EEPROM storage as an array of bits 3662 * being shifted into bytes, but that's not how we're looking 3663 * at it here... 3664 */ 3665 for (i = 0; i < 6 ;i++) 3666 enaddr[i] = bbr(enaddr[i]); 3667 } 3668 #endif /* DP83820 */ 3669 3670 /* 3671 * sip_mediastatus: [ifmedia interface function] 3672 * 3673 * Get the current interface media status. 3674 */ 3675 void 3676 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3677 { 3678 struct sip_softc *sc = ifp->if_softc; 3679 3680 mii_pollstat(&sc->sc_mii); 3681 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3682 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3683 sc->sc_flowflags; 3684 } 3685 3686 /* 3687 * sip_mediachange: [ifmedia interface function] 3688 * 3689 * Set hardware to newly-selected media. 3690 */ 3691 int 3692 SIP_DECL(mediachange)(struct ifnet *ifp) 3693 { 3694 struct sip_softc *sc = ifp->if_softc; 3695 3696 if (ifp->if_flags & IFF_UP) 3697 mii_mediachg(&sc->sc_mii); 3698 return (0); 3699 } 3700
Indexes created Tue Sep 30 11:09:46 GMT 2025