if_sip.c revision 1.96
1 /* $NetBSD: if_sip.c,v 1.96 2004/10/30 18:09:22 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.96 2004/10/30 18:09:22 thorpej Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <machine/bus.h> 116 #include <machine/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/mii_bitbang.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/pci/if_sipreg.h> 128 129 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 130 #define SIP_DECL(x) __CONCAT(gsip_,x) 131 #else /* SiS900 and DP83815 */ 132 #define SIP_DECL(x) __CONCAT(sip_,x) 133 #endif 134 135 #define SIP_STR(x) __STRING(SIP_DECL(x)) 136 137 /* 138 * Transmit descriptor list size. This is arbitrary, but allocate 139 * enough descriptors for 128 pending transmissions, and 8 segments 140 * per packet (64 for DP83820 for jumbo frames). 141 * 142 * This MUST work out to a power of 2. 143 */ 144 #ifdef DP83820 145 #define SIP_NTXSEGS 64 146 #define SIP_NTXSEGS_ALLOC 16 147 #else 148 #define SIP_NTXSEGS 16 149 #define SIP_NTXSEGS_ALLOC 8 150 #endif 151 152 #define SIP_TXQUEUELEN 256 153 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 154 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 155 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 156 157 #if defined(DP83820) 158 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 159 #else 160 #define TX_DMAMAP_SIZE MCLBYTES 161 #endif 162 163 /* 164 * Receive descriptor list size. We have one Rx buffer per incoming 165 * packet, so this logic is a little simpler. 166 * 167 * Actually, on the DP83820, we allow the packet to consume more than 168 * one buffer, in order to support jumbo Ethernet frames. In that 169 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 170 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 171 * so we'd better be quick about handling receive interrupts. 172 */ 173 #if defined(DP83820) 174 #define SIP_NRXDESC 256 175 #else 176 #define SIP_NRXDESC 128 177 #endif /* DP83820 */ 178 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 179 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 180 181 /* 182 * Control structures are DMA'd to the SiS900 chip. We allocate them in 183 * a single clump that maps to a single DMA segment to make several things 184 * easier. 185 */ 186 struct sip_control_data { 187 /* 188 * The transmit descriptors. 189 */ 190 struct sip_desc scd_txdescs[SIP_NTXDESC]; 191 192 /* 193 * The receive descriptors. 194 */ 195 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 196 }; 197 198 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 199 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 200 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 201 202 /* 203 * Software state for transmit jobs. 204 */ 205 struct sip_txsoft { 206 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 207 bus_dmamap_t txs_dmamap; /* our DMA map */ 208 int txs_firstdesc; /* first descriptor in packet */ 209 int txs_lastdesc; /* last descriptor in packet */ 210 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 211 }; 212 213 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 214 215 /* 216 * Software state for receive jobs. 217 */ 218 struct sip_rxsoft { 219 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 220 bus_dmamap_t rxs_dmamap; /* our DMA map */ 221 }; 222 223 /* 224 * Software state per device. 225 */ 226 struct sip_softc { 227 struct device sc_dev; /* generic device information */ 228 bus_space_tag_t sc_st; /* bus space tag */ 229 bus_space_handle_t sc_sh; /* bus space handle */ 230 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 231 struct ethercom sc_ethercom; /* ethernet common data */ 232 void *sc_sdhook; /* shutdown hook */ 233 234 const struct sip_product *sc_model; /* which model are we? */ 235 int sc_rev; /* chip revision */ 236 237 void *sc_ih; /* interrupt cookie */ 238 239 struct mii_data sc_mii; /* MII/media information */ 240 241 struct callout sc_tick_ch; /* tick callout */ 242 243 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 244 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 245 246 /* 247 * Software state for transmit and receive descriptors. 248 */ 249 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 250 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 251 252 /* 253 * Control data structures. 254 */ 255 struct sip_control_data *sc_control_data; 256 #define sc_txdescs sc_control_data->scd_txdescs 257 #define sc_rxdescs sc_control_data->scd_rxdescs 258 259 #ifdef SIP_EVENT_COUNTERS 260 /* 261 * Event counters. 262 */ 263 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 264 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 265 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 266 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 267 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 268 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 269 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 270 struct evcnt sc_ev_rxpause; /* PAUSE received */ 271 #ifdef DP83820 272 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 273 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 274 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 275 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 276 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 277 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 278 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 279 #endif /* DP83820 */ 280 #endif /* SIP_EVENT_COUNTERS */ 281 282 u_int32_t sc_txcfg; /* prototype TXCFG register */ 283 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 284 u_int32_t sc_imr; /* prototype IMR register */ 285 u_int32_t sc_rfcr; /* prototype RFCR register */ 286 287 u_int32_t sc_cfg; /* prototype CFG register */ 288 289 #ifdef DP83820 290 u_int32_t sc_gpior; /* prototype GPIOR register */ 291 #endif /* DP83820 */ 292 293 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 294 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 295 296 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 297 298 int sc_flowflags; /* 802.3x flow control flags */ 299 #ifdef DP83820 300 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 301 #else 302 int sc_paused; /* paused indication */ 303 #endif 304 305 int sc_txfree; /* number of free Tx descriptors */ 306 int sc_txnext; /* next ready Tx descriptor */ 307 int sc_txwin; /* Tx descriptors since last intr */ 308 309 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 310 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 311 312 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 313 #if defined(DP83820) 314 int sc_rxdiscard; 315 int sc_rxlen; 316 struct mbuf *sc_rxhead; 317 struct mbuf *sc_rxtail; 318 struct mbuf **sc_rxtailp; 319 #endif /* DP83820 */ 320 321 #if NRND > 0 322 rndsource_element_t rnd_source; /* random source */ 323 #endif 324 }; 325 326 #ifdef DP83820 327 #define SIP_RXCHAIN_RESET(sc) \ 328 do { \ 329 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 330 *(sc)->sc_rxtailp = NULL; \ 331 (sc)->sc_rxlen = 0; \ 332 } while (/*CONSTCOND*/0) 333 334 #define SIP_RXCHAIN_LINK(sc, m) \ 335 do { \ 336 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 337 (sc)->sc_rxtailp = &(m)->m_next; \ 338 } while (/*CONSTCOND*/0) 339 #endif /* DP83820 */ 340 341 #ifdef SIP_EVENT_COUNTERS 342 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 343 #else 344 #define SIP_EVCNT_INCR(ev) /* nothing */ 345 #endif 346 347 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 348 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 349 350 #define SIP_CDTXSYNC(sc, x, n, ops) \ 351 do { \ 352 int __x, __n; \ 353 \ 354 __x = (x); \ 355 __n = (n); \ 356 \ 357 /* If it will wrap around, sync to the end of the ring. */ \ 358 if ((__x + __n) > SIP_NTXDESC) { \ 359 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 360 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 361 (SIP_NTXDESC - __x), (ops)); \ 362 __n -= (SIP_NTXDESC - __x); \ 363 __x = 0; \ 364 } \ 365 \ 366 /* Now sync whatever is left. */ \ 367 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 368 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 369 } while (0) 370 371 #define SIP_CDRXSYNC(sc, x, ops) \ 372 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 373 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 374 375 #ifdef DP83820 376 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 377 #define SIP_RXBUF_LEN (MCLBYTES - 8) 378 #else 379 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 380 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 381 #endif 382 #define SIP_INIT_RXDESC(sc, x) \ 383 do { \ 384 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 385 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 386 \ 387 __sipd->sipd_link = \ 388 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 389 __sipd->sipd_bufptr = \ 390 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 391 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 392 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 393 SIP_INIT_RXDESC_EXTSTS \ 394 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 395 } while (0) 396 397 #define SIP_CHIP_VERS(sc, v, p, r) \ 398 ((sc)->sc_model->sip_vendor == (v) && \ 399 (sc)->sc_model->sip_product == (p) && \ 400 (sc)->sc_rev == (r)) 401 402 #define SIP_CHIP_MODEL(sc, v, p) \ 403 ((sc)->sc_model->sip_vendor == (v) && \ 404 (sc)->sc_model->sip_product == (p)) 405 406 #if !defined(DP83820) 407 #define SIP_SIS900_REV(sc, rev) \ 408 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 409 #endif 410 411 #define SIP_TIMEOUT 1000 412 413 static void SIP_DECL(start)(struct ifnet *); 414 static void SIP_DECL(watchdog)(struct ifnet *); 415 static int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 416 static int SIP_DECL(init)(struct ifnet *); 417 static void SIP_DECL(stop)(struct ifnet *, int); 418 419 static void SIP_DECL(shutdown)(void *); 420 421 static void SIP_DECL(reset)(struct sip_softc *); 422 static void SIP_DECL(rxdrain)(struct sip_softc *); 423 static int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 424 static void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, 425 u_int16_t *); 426 static void SIP_DECL(tick)(void *); 427 428 #if !defined(DP83820) 429 static void SIP_DECL(sis900_set_filter)(struct sip_softc *); 430 #endif /* ! DP83820 */ 431 static void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 432 433 #if defined(DP83820) 434 static void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 435 const struct pci_attach_args *, u_int8_t *); 436 #else 437 static void SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc); 438 static void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 439 const struct pci_attach_args *, u_int8_t *); 440 static void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 441 const struct pci_attach_args *, u_int8_t *); 442 #endif /* DP83820 */ 443 444 static int SIP_DECL(intr)(void *); 445 static void SIP_DECL(txintr)(struct sip_softc *); 446 static void SIP_DECL(rxintr)(struct sip_softc *); 447 448 #if defined(DP83820) 449 static int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 450 static void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 451 static void SIP_DECL(dp83820_mii_statchg)(struct device *); 452 #else 453 static int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 454 static void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 455 static void SIP_DECL(sis900_mii_statchg)(struct device *); 456 457 static int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 458 static void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 459 static void SIP_DECL(dp83815_mii_statchg)(struct device *); 460 #endif /* DP83820 */ 461 462 static int SIP_DECL(mediachange)(struct ifnet *); 463 static void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 464 465 static int SIP_DECL(match)(struct device *, struct cfdata *, void *); 466 static void SIP_DECL(attach)(struct device *, struct device *, void *); 467 468 int SIP_DECL(copy_small) = 0; 469 470 #ifdef DP83820 471 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 472 gsip_match, gsip_attach, NULL, NULL); 473 #else 474 CFATTACH_DECL(sip, sizeof(struct sip_softc), 475 sip_match, sip_attach, NULL, NULL); 476 #endif 477 478 /* 479 * Descriptions of the variants of the SiS900. 480 */ 481 struct sip_variant { 482 int (*sipv_mii_readreg)(struct device *, int, int); 483 void (*sipv_mii_writereg)(struct device *, int, int, int); 484 void (*sipv_mii_statchg)(struct device *); 485 void (*sipv_set_filter)(struct sip_softc *); 486 void (*sipv_read_macaddr)(struct sip_softc *, 487 const struct pci_attach_args *, u_int8_t *); 488 }; 489 490 static u_int32_t SIP_DECL(mii_bitbang_read)(struct device *); 491 static void SIP_DECL(mii_bitbang_write)(struct device *, u_int32_t); 492 493 static const struct mii_bitbang_ops SIP_DECL(mii_bitbang_ops) = { 494 SIP_DECL(mii_bitbang_read), 495 SIP_DECL(mii_bitbang_write), 496 { 497 EROMAR_MDIO, /* MII_BIT_MDO */ 498 EROMAR_MDIO, /* MII_BIT_MDI */ 499 EROMAR_MDC, /* MII_BIT_MDC */ 500 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 501 0, /* MII_BIT_DIR_PHY_HOST */ 502 } 503 }; 504 505 #if defined(DP83820) 506 static const struct sip_variant SIP_DECL(variant_dp83820) = { 507 SIP_DECL(dp83820_mii_readreg), 508 SIP_DECL(dp83820_mii_writereg), 509 SIP_DECL(dp83820_mii_statchg), 510 SIP_DECL(dp83815_set_filter), 511 SIP_DECL(dp83820_read_macaddr), 512 }; 513 #else 514 static const struct sip_variant SIP_DECL(variant_sis900) = { 515 SIP_DECL(sis900_mii_readreg), 516 SIP_DECL(sis900_mii_writereg), 517 SIP_DECL(sis900_mii_statchg), 518 SIP_DECL(sis900_set_filter), 519 SIP_DECL(sis900_read_macaddr), 520 }; 521 522 static const struct sip_variant SIP_DECL(variant_dp83815) = { 523 SIP_DECL(dp83815_mii_readreg), 524 SIP_DECL(dp83815_mii_writereg), 525 SIP_DECL(dp83815_mii_statchg), 526 SIP_DECL(dp83815_set_filter), 527 SIP_DECL(dp83815_read_macaddr), 528 }; 529 #endif /* DP83820 */ 530 531 /* 532 * Devices supported by this driver. 533 */ 534 static const struct sip_product { 535 pci_vendor_id_t sip_vendor; 536 pci_product_id_t sip_product; 537 const char *sip_name; 538 const struct sip_variant *sip_variant; 539 } SIP_DECL(products)[] = { 540 #if defined(DP83820) 541 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 542 "NatSemi DP83820 Gigabit Ethernet", 543 &SIP_DECL(variant_dp83820) }, 544 #else 545 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 546 "SiS 900 10/100 Ethernet", 547 &SIP_DECL(variant_sis900) }, 548 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 549 "SiS 7016 10/100 Ethernet", 550 &SIP_DECL(variant_sis900) }, 551 552 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 553 "NatSemi DP83815 10/100 Ethernet", 554 &SIP_DECL(variant_dp83815) }, 555 #endif /* DP83820 */ 556 557 { 0, 0, 558 NULL, 559 NULL }, 560 }; 561 562 static const struct sip_product * 563 SIP_DECL(lookup)(const struct pci_attach_args *pa) 564 { 565 const struct sip_product *sip; 566 567 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 568 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 569 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 570 return (sip); 571 } 572 return (NULL); 573 } 574 575 #ifdef DP83820 576 /* 577 * I really hate stupid hardware vendors. There's a bit in the EEPROM 578 * which indicates if the card can do 64-bit data transfers. Unfortunately, 579 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 580 * which means we try to use 64-bit data transfers on those cards if we 581 * happen to be plugged into a 32-bit slot. 582 * 583 * What we do is use this table of cards known to be 64-bit cards. If 584 * you have a 64-bit card who's subsystem ID is not listed in this table, 585 * send the output of "pcictl dump ..." of the device to me so that your 586 * card will use the 64-bit data path when plugged into a 64-bit slot. 587 * 588 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 589 * June 30, 2002 590 */ 591 static int 592 SIP_DECL(check_64bit)(const struct pci_attach_args *pa) 593 { 594 static const struct { 595 pci_vendor_id_t c64_vendor; 596 pci_product_id_t c64_product; 597 } card64[] = { 598 /* Asante GigaNIX */ 599 { 0x128a, 0x0002 }, 600 601 /* Accton EN1407-T, Planex GN-1000TE */ 602 { 0x1113, 0x1407 }, 603 604 /* Netgear GA-621 */ 605 { 0x1385, 0x621a }, 606 607 /* SMC EZ Card */ 608 { 0x10b8, 0x9462 }, 609 610 { 0, 0} 611 }; 612 pcireg_t subsys; 613 int i; 614 615 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 616 617 for (i = 0; card64[i].c64_vendor != 0; i++) { 618 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 619 PCI_PRODUCT(subsys) == card64[i].c64_product) 620 return (1); 621 } 622 623 return (0); 624 } 625 #endif /* DP83820 */ 626 627 static int 628 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 629 { 630 struct pci_attach_args *pa = aux; 631 632 if (SIP_DECL(lookup)(pa) != NULL) 633 return (1); 634 635 return (0); 636 } 637 638 static void 639 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 640 { 641 struct sip_softc *sc = (struct sip_softc *) self; 642 struct pci_attach_args *pa = aux; 643 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 644 pci_chipset_tag_t pc = pa->pa_pc; 645 pci_intr_handle_t ih; 646 const char *intrstr = NULL; 647 bus_space_tag_t iot, memt; 648 bus_space_handle_t ioh, memh; 649 bus_dma_segment_t seg; 650 int ioh_valid, memh_valid; 651 int i, rseg, error; 652 const struct sip_product *sip; 653 pcireg_t pmode; 654 u_int8_t enaddr[ETHER_ADDR_LEN]; 655 int pmreg; 656 #ifdef DP83820 657 pcireg_t memtype; 658 u_int32_t reg; 659 #endif /* DP83820 */ 660 661 callout_init(&sc->sc_tick_ch); 662 663 sip = SIP_DECL(lookup)(pa); 664 if (sip == NULL) { 665 printf("\n"); 666 panic(SIP_STR(attach) ": impossible"); 667 } 668 sc->sc_rev = PCI_REVISION(pa->pa_class); 669 670 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 671 672 sc->sc_model = sip; 673 674 /* 675 * XXX Work-around broken PXE firmware on some boards. 676 * 677 * The DP83815 shares an address decoder with the MEM BAR 678 * and the ROM BAR. Make sure the ROM BAR is disabled, 679 * so that memory mapped access works. 680 */ 681 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 682 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 683 ~PCI_MAPREG_ROM_ENABLE); 684 685 /* 686 * Map the device. 687 */ 688 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 689 PCI_MAPREG_TYPE_IO, 0, 690 &iot, &ioh, NULL, NULL) == 0); 691 #ifdef DP83820 692 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 693 switch (memtype) { 694 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 695 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 696 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 697 memtype, 0, &memt, &memh, NULL, NULL) == 0); 698 break; 699 default: 700 memh_valid = 0; 701 } 702 #else 703 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 704 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 705 &memt, &memh, NULL, NULL) == 0); 706 #endif /* DP83820 */ 707 708 if (memh_valid) { 709 sc->sc_st = memt; 710 sc->sc_sh = memh; 711 } else if (ioh_valid) { 712 sc->sc_st = iot; 713 sc->sc_sh = ioh; 714 } else { 715 printf("%s: unable to map device registers\n", 716 sc->sc_dev.dv_xname); 717 return; 718 } 719 720 sc->sc_dmat = pa->pa_dmat; 721 722 /* 723 * Make sure bus mastering is enabled. Also make sure 724 * Write/Invalidate is enabled if we're allowed to use it. 725 */ 726 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 727 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 728 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 729 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 730 pmreg | PCI_COMMAND_MASTER_ENABLE); 731 732 /* Get it out of power save mode if needed. */ 733 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 734 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 735 PCI_PMCSR_STATE_MASK; 736 if (pmode == PCI_PMCSR_STATE_D3) { 737 /* 738 * The card has lost all configuration data in 739 * this state, so punt. 740 */ 741 printf("%s: unable to wake up from power state D3\n", 742 sc->sc_dev.dv_xname); 743 return; 744 } 745 if (pmode != PCI_PMCSR_STATE_D0) { 746 printf("%s: waking up from power state D%d\n", 747 sc->sc_dev.dv_xname, pmode); 748 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 749 PCI_PMCSR_STATE_D0); 750 } 751 } 752 753 /* 754 * Map and establish our interrupt. 755 */ 756 if (pci_intr_map(pa, &ih)) { 757 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 758 return; 759 } 760 intrstr = pci_intr_string(pc, ih); 761 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 762 if (sc->sc_ih == NULL) { 763 printf("%s: unable to establish interrupt", 764 sc->sc_dev.dv_xname); 765 if (intrstr != NULL) 766 printf(" at %s", intrstr); 767 printf("\n"); 768 return; 769 } 770 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 771 772 SIMPLEQ_INIT(&sc->sc_txfreeq); 773 SIMPLEQ_INIT(&sc->sc_txdirtyq); 774 775 /* 776 * Allocate the control data structures, and create and load the 777 * DMA map for it. 778 */ 779 if ((error = bus_dmamem_alloc(sc->sc_dmat, 780 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 781 0)) != 0) { 782 printf("%s: unable to allocate control data, error = %d\n", 783 sc->sc_dev.dv_xname, error); 784 goto fail_0; 785 } 786 787 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 788 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 789 BUS_DMA_COHERENT)) != 0) { 790 printf("%s: unable to map control data, error = %d\n", 791 sc->sc_dev.dv_xname, error); 792 goto fail_1; 793 } 794 795 if ((error = bus_dmamap_create(sc->sc_dmat, 796 sizeof(struct sip_control_data), 1, 797 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 798 printf("%s: unable to create control data DMA map, " 799 "error = %d\n", sc->sc_dev.dv_xname, error); 800 goto fail_2; 801 } 802 803 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 804 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 805 0)) != 0) { 806 printf("%s: unable to load control data DMA map, error = %d\n", 807 sc->sc_dev.dv_xname, error); 808 goto fail_3; 809 } 810 811 /* 812 * Create the transmit buffer DMA maps. 813 */ 814 for (i = 0; i < SIP_TXQUEUELEN; i++) { 815 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 816 SIP_NTXSEGS, MCLBYTES, 0, 0, 817 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 818 printf("%s: unable to create tx DMA map %d, " 819 "error = %d\n", sc->sc_dev.dv_xname, i, error); 820 goto fail_4; 821 } 822 } 823 824 /* 825 * Create the receive buffer DMA maps. 826 */ 827 for (i = 0; i < SIP_NRXDESC; i++) { 828 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 829 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 830 printf("%s: unable to create rx DMA map %d, " 831 "error = %d\n", sc->sc_dev.dv_xname, i, error); 832 goto fail_5; 833 } 834 sc->sc_rxsoft[i].rxs_mbuf = NULL; 835 } 836 837 /* 838 * Reset the chip to a known state. 839 */ 840 SIP_DECL(reset)(sc); 841 842 /* 843 * Read the Ethernet address from the EEPROM. This might 844 * also fetch other stuff from the EEPROM and stash it 845 * in the softc. 846 */ 847 sc->sc_cfg = 0; 848 #if !defined(DP83820) 849 if (SIP_SIS900_REV(sc,SIS_REV_635) || 850 SIP_SIS900_REV(sc,SIS_REV_900B)) 851 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 852 853 if (SIP_SIS900_REV(sc,SIS_REV_635) || 854 SIP_SIS900_REV(sc,SIS_REV_960) || 855 SIP_SIS900_REV(sc,SIS_REV_900B)) 856 sc->sc_cfg |= (bus_space_read_4(sc->sc_st, sc->sc_sh, 857 SIP_CFG) & CFG_EDBMASTEN); 858 #endif 859 860 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 861 862 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 863 ether_sprintf(enaddr)); 864 865 /* 866 * Initialize the configuration register: aggressive PCI 867 * bus request algorithm, default backoff, default OW timer, 868 * default parity error detection. 869 * 870 * NOTE: "Big endian mode" is useless on the SiS900 and 871 * friends -- it affects packet data, not descriptors. 872 */ 873 #ifdef DP83820 874 /* 875 * Cause the chip to load configuration data from the EEPROM. 876 */ 877 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 878 for (i = 0; i < 10000; i++) { 879 delay(10); 880 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 881 PTSCR_EELOAD_EN) == 0) 882 break; 883 } 884 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 885 PTSCR_EELOAD_EN) { 886 printf("%s: timeout loading configuration from EEPROM\n", 887 sc->sc_dev.dv_xname); 888 return; 889 } 890 891 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 892 893 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 894 if (reg & CFG_PCI64_DET) { 895 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 896 /* 897 * Check to see if this card is 64-bit. If so, enable 64-bit 898 * data transfers. 899 * 900 * We can't use the DATA64_EN bit in the EEPROM, because 901 * vendors of 32-bit cards fail to clear that bit in many 902 * cases (yet the card still detects that it's in a 64-bit 903 * slot; go figure). 904 */ 905 if (SIP_DECL(check_64bit)(pa)) { 906 sc->sc_cfg |= CFG_DATA64_EN; 907 printf(", using 64-bit data transfers"); 908 } 909 printf("\n"); 910 } 911 912 /* 913 * XXX Need some PCI flags indicating support for 914 * XXX 64-bit addressing. 915 */ 916 #if 0 917 if (reg & CFG_M64ADDR) 918 sc->sc_cfg |= CFG_M64ADDR; 919 if (reg & CFG_T64ADDR) 920 sc->sc_cfg |= CFG_T64ADDR; 921 #endif 922 923 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 924 const char *sep = ""; 925 printf("%s: using ", sc->sc_dev.dv_xname); 926 if (reg & CFG_EXT_125) { 927 sc->sc_cfg |= CFG_EXT_125; 928 printf("%s125MHz clock", sep); 929 sep = ", "; 930 } 931 if (reg & CFG_TBI_EN) { 932 sc->sc_cfg |= CFG_TBI_EN; 933 printf("%sten-bit interface", sep); 934 sep = ", "; 935 } 936 printf("\n"); 937 } 938 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 939 (reg & CFG_MRM_DIS) != 0) 940 sc->sc_cfg |= CFG_MRM_DIS; 941 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 942 (reg & CFG_MWI_DIS) != 0) 943 sc->sc_cfg |= CFG_MWI_DIS; 944 945 /* 946 * Use the extended descriptor format on the DP83820. This 947 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 948 * checksumming. 949 */ 950 sc->sc_cfg |= CFG_EXTSTS_EN; 951 #endif /* DP83820 */ 952 953 /* 954 * Initialize our media structures and probe the MII. 955 */ 956 sc->sc_mii.mii_ifp = ifp; 957 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 958 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 959 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 960 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, SIP_DECL(mediachange), 961 SIP_DECL(mediastatus)); 962 963 /* 964 * XXX We cannot handle flow control on the DP83815. 965 */ 966 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 967 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 968 MII_OFFSET_ANY, 0); 969 else 970 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 971 MII_OFFSET_ANY, MIIF_DOPAUSE); 972 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 973 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 974 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 975 } else 976 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 977 978 ifp = &sc->sc_ethercom.ec_if; 979 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 980 ifp->if_softc = sc; 981 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 982 ifp->if_ioctl = SIP_DECL(ioctl); 983 ifp->if_start = SIP_DECL(start); 984 ifp->if_watchdog = SIP_DECL(watchdog); 985 ifp->if_init = SIP_DECL(init); 986 ifp->if_stop = SIP_DECL(stop); 987 IFQ_SET_READY(&ifp->if_snd); 988 989 /* 990 * We can support 802.1Q VLAN-sized frames. 991 */ 992 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 993 994 #ifdef DP83820 995 /* 996 * And the DP83820 can do VLAN tagging in hardware, and 997 * support the jumbo Ethernet MTU. 998 */ 999 sc->sc_ethercom.ec_capabilities |= 1000 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1001 1002 /* 1003 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1004 * in hardware. 1005 */ 1006 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 1007 IFCAP_CSUM_UDPv4; 1008 #endif /* DP83820 */ 1009 1010 /* 1011 * Attach the interface. 1012 */ 1013 if_attach(ifp); 1014 ether_ifattach(ifp, enaddr); 1015 #if NRND > 0 1016 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1017 RND_TYPE_NET, 0); 1018 #endif 1019 1020 /* 1021 * The number of bytes that must be available in 1022 * the Tx FIFO before the bus master can DMA more 1023 * data into the FIFO. 1024 */ 1025 sc->sc_tx_fill_thresh = 64 / 32; 1026 1027 /* 1028 * Start at a drain threshold of 512 bytes. We will 1029 * increase it if a DMA underrun occurs. 1030 * 1031 * XXX The minimum value of this variable should be 1032 * tuned. We may be able to improve performance 1033 * by starting with a lower value. That, however, 1034 * may trash the first few outgoing packets if the 1035 * PCI bus is saturated. 1036 */ 1037 #ifdef DP83820 1038 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1039 #else 1040 sc->sc_tx_drain_thresh = 1504 / 32; 1041 #endif 1042 1043 /* 1044 * Initialize the Rx FIFO drain threshold. 1045 * 1046 * This is in units of 8 bytes. 1047 * 1048 * We should never set this value lower than 2; 14 bytes are 1049 * required to filter the packet. 1050 */ 1051 sc->sc_rx_drain_thresh = 128 / 8; 1052 1053 #ifdef SIP_EVENT_COUNTERS 1054 /* 1055 * Attach event counters. 1056 */ 1057 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1058 NULL, sc->sc_dev.dv_xname, "txsstall"); 1059 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1060 NULL, sc->sc_dev.dv_xname, "txdstall"); 1061 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1062 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1063 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1064 NULL, sc->sc_dev.dv_xname, "txdintr"); 1065 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1066 NULL, sc->sc_dev.dv_xname, "txiintr"); 1067 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1068 NULL, sc->sc_dev.dv_xname, "rxintr"); 1069 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1070 NULL, sc->sc_dev.dv_xname, "hiberr"); 1071 #ifndef DP83820 1072 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1073 NULL, sc->sc_dev.dv_xname, "rxpause"); 1074 #endif /* !DP83820 */ 1075 #ifdef DP83820 1076 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1077 NULL, sc->sc_dev.dv_xname, "rxpause"); 1078 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1079 NULL, sc->sc_dev.dv_xname, "txpause"); 1080 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1081 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1082 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1083 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1084 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1085 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1086 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1087 NULL, sc->sc_dev.dv_xname, "txipsum"); 1088 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1089 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1090 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1091 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1092 #endif /* DP83820 */ 1093 #endif /* SIP_EVENT_COUNTERS */ 1094 1095 /* 1096 * Make sure the interface is shutdown during reboot. 1097 */ 1098 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 1099 if (sc->sc_sdhook == NULL) 1100 printf("%s: WARNING: unable to establish shutdown hook\n", 1101 sc->sc_dev.dv_xname); 1102 return; 1103 1104 /* 1105 * Free any resources we've allocated during the failed attach 1106 * attempt. Do this in reverse order and fall through. 1107 */ 1108 fail_5: 1109 for (i = 0; i < SIP_NRXDESC; i++) { 1110 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1111 bus_dmamap_destroy(sc->sc_dmat, 1112 sc->sc_rxsoft[i].rxs_dmamap); 1113 } 1114 fail_4: 1115 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1116 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1117 bus_dmamap_destroy(sc->sc_dmat, 1118 sc->sc_txsoft[i].txs_dmamap); 1119 } 1120 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1121 fail_3: 1122 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1123 fail_2: 1124 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1125 sizeof(struct sip_control_data)); 1126 fail_1: 1127 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1128 fail_0: 1129 return; 1130 } 1131 1132 /* 1133 * sip_shutdown: 1134 * 1135 * Make sure the interface is stopped at reboot time. 1136 */ 1137 static void 1138 SIP_DECL(shutdown)(void *arg) 1139 { 1140 struct sip_softc *sc = arg; 1141 1142 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1143 } 1144 1145 /* 1146 * sip_start: [ifnet interface function] 1147 * 1148 * Start packet transmission on the interface. 1149 */ 1150 static void 1151 SIP_DECL(start)(struct ifnet *ifp) 1152 { 1153 struct sip_softc *sc = ifp->if_softc; 1154 struct mbuf *m0; 1155 #ifndef DP83820 1156 struct mbuf *m; 1157 #endif 1158 struct sip_txsoft *txs; 1159 bus_dmamap_t dmamap; 1160 int error, nexttx, lasttx, seg; 1161 int ofree = sc->sc_txfree; 1162 #if 0 1163 int firsttx = sc->sc_txnext; 1164 #endif 1165 #ifdef DP83820 1166 struct m_tag *mtag; 1167 u_int32_t extsts; 1168 #endif 1169 1170 #ifndef DP83820 1171 /* 1172 * If we've been told to pause, don't transmit any more packets. 1173 */ 1174 if (sc->sc_paused) 1175 ifp->if_flags |= IFF_OACTIVE; 1176 #endif 1177 1178 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1179 return; 1180 1181 /* 1182 * Loop through the send queue, setting up transmit descriptors 1183 * until we drain the queue, or use up all available transmit 1184 * descriptors. 1185 */ 1186 for (;;) { 1187 /* Get a work queue entry. */ 1188 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1189 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1190 break; 1191 } 1192 1193 /* 1194 * Grab a packet off the queue. 1195 */ 1196 IFQ_POLL(&ifp->if_snd, m0); 1197 if (m0 == NULL) 1198 break; 1199 #ifndef DP83820 1200 m = NULL; 1201 #endif 1202 1203 dmamap = txs->txs_dmamap; 1204 1205 #ifdef DP83820 1206 /* 1207 * Load the DMA map. If this fails, the packet either 1208 * didn't fit in the allotted number of segments, or we 1209 * were short on resources. For the too-many-segments 1210 * case, we simply report an error and drop the packet, 1211 * since we can't sanely copy a jumbo packet to a single 1212 * buffer. 1213 */ 1214 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1215 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1216 if (error) { 1217 if (error == EFBIG) { 1218 printf("%s: Tx packet consumes too many " 1219 "DMA segments, dropping...\n", 1220 sc->sc_dev.dv_xname); 1221 IFQ_DEQUEUE(&ifp->if_snd, m0); 1222 m_freem(m0); 1223 continue; 1224 } 1225 /* 1226 * Short on resources, just stop for now. 1227 */ 1228 break; 1229 } 1230 #else /* DP83820 */ 1231 /* 1232 * Load the DMA map. If this fails, the packet either 1233 * didn't fit in the alloted number of segments, or we 1234 * were short on resources. In this case, we'll copy 1235 * and try again. 1236 */ 1237 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1238 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1239 MGETHDR(m, M_DONTWAIT, MT_DATA); 1240 if (m == NULL) { 1241 printf("%s: unable to allocate Tx mbuf\n", 1242 sc->sc_dev.dv_xname); 1243 break; 1244 } 1245 if (m0->m_pkthdr.len > MHLEN) { 1246 MCLGET(m, M_DONTWAIT); 1247 if ((m->m_flags & M_EXT) == 0) { 1248 printf("%s: unable to allocate Tx " 1249 "cluster\n", sc->sc_dev.dv_xname); 1250 m_freem(m); 1251 break; 1252 } 1253 } 1254 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1255 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1256 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1257 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1258 if (error) { 1259 printf("%s: unable to load Tx buffer, " 1260 "error = %d\n", sc->sc_dev.dv_xname, error); 1261 break; 1262 } 1263 } 1264 #endif /* DP83820 */ 1265 1266 /* 1267 * Ensure we have enough descriptors free to describe 1268 * the packet. Note, we always reserve one descriptor 1269 * at the end of the ring as a termination point, to 1270 * prevent wrap-around. 1271 */ 1272 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1273 /* 1274 * Not enough free descriptors to transmit this 1275 * packet. We haven't committed anything yet, 1276 * so just unload the DMA map, put the packet 1277 * back on the queue, and punt. Notify the upper 1278 * layer that there are not more slots left. 1279 * 1280 * XXX We could allocate an mbuf and copy, but 1281 * XXX is it worth it? 1282 */ 1283 ifp->if_flags |= IFF_OACTIVE; 1284 bus_dmamap_unload(sc->sc_dmat, dmamap); 1285 #ifndef DP83820 1286 if (m != NULL) 1287 m_freem(m); 1288 #endif 1289 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1290 break; 1291 } 1292 1293 IFQ_DEQUEUE(&ifp->if_snd, m0); 1294 #ifndef DP83820 1295 if (m != NULL) { 1296 m_freem(m0); 1297 m0 = m; 1298 } 1299 #endif 1300 1301 /* 1302 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1303 */ 1304 1305 /* Sync the DMA map. */ 1306 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1307 BUS_DMASYNC_PREWRITE); 1308 1309 /* 1310 * Initialize the transmit descriptors. 1311 */ 1312 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1313 seg < dmamap->dm_nsegs; 1314 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1315 /* 1316 * If this is the first descriptor we're 1317 * enqueueing, don't set the OWN bit just 1318 * yet. That could cause a race condition. 1319 * We'll do it below. 1320 */ 1321 sc->sc_txdescs[nexttx].sipd_bufptr = 1322 htole32(dmamap->dm_segs[seg].ds_addr); 1323 sc->sc_txdescs[nexttx].sipd_cmdsts = 1324 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1325 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1326 #ifdef DP83820 1327 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1328 #endif /* DP83820 */ 1329 lasttx = nexttx; 1330 } 1331 1332 /* Clear the MORE bit on the last segment. */ 1333 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1334 1335 /* 1336 * If we're in the interrupt delay window, delay the 1337 * interrupt. 1338 */ 1339 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1340 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1341 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1342 htole32(CMDSTS_INTR); 1343 sc->sc_txwin = 0; 1344 } 1345 1346 #ifdef DP83820 1347 /* 1348 * If VLANs are enabled and the packet has a VLAN tag, set 1349 * up the descriptor to encapsulate the packet for us. 1350 * 1351 * This apparently has to be on the last descriptor of 1352 * the packet. 1353 */ 1354 if (sc->sc_ethercom.ec_nvlans != 0 && 1355 (mtag = m_tag_find(m0, PACKET_TAG_VLAN, NULL)) != NULL) { 1356 sc->sc_txdescs[lasttx].sipd_extsts |= 1357 htole32(EXTSTS_VPKT | 1358 (*(u_int *)(mtag + 1) & EXTSTS_VTCI)); 1359 } 1360 1361 /* 1362 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1363 * checksumming, set up the descriptor to do this work 1364 * for us. 1365 * 1366 * This apparently has to be on the first descriptor of 1367 * the packet. 1368 * 1369 * Byte-swap constants so the compiler can optimize. 1370 */ 1371 extsts = 0; 1372 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1373 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1374 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1375 extsts |= htole32(EXTSTS_IPPKT); 1376 } 1377 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1378 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1379 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1380 extsts |= htole32(EXTSTS_TCPPKT); 1381 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1382 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1383 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1384 extsts |= htole32(EXTSTS_UDPPKT); 1385 } 1386 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1387 #endif /* DP83820 */ 1388 1389 /* Sync the descriptors we're using. */ 1390 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1391 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1392 1393 /* 1394 * The entire packet is set up. Give the first descrptor 1395 * to the chip now. 1396 */ 1397 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1398 htole32(CMDSTS_OWN); 1399 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1400 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1401 1402 /* 1403 * Store a pointer to the packet so we can free it later, 1404 * and remember what txdirty will be once the packet is 1405 * done. 1406 */ 1407 txs->txs_mbuf = m0; 1408 txs->txs_firstdesc = sc->sc_txnext; 1409 txs->txs_lastdesc = lasttx; 1410 1411 /* Advance the tx pointer. */ 1412 sc->sc_txfree -= dmamap->dm_nsegs; 1413 sc->sc_txnext = nexttx; 1414 1415 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1416 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1417 1418 #if NBPFILTER > 0 1419 /* 1420 * Pass the packet to any BPF listeners. 1421 */ 1422 if (ifp->if_bpf) 1423 bpf_mtap(ifp->if_bpf, m0); 1424 #endif /* NBPFILTER > 0 */ 1425 } 1426 1427 if (txs == NULL || sc->sc_txfree == 0) { 1428 /* No more slots left; notify upper layer. */ 1429 ifp->if_flags |= IFF_OACTIVE; 1430 } 1431 1432 if (sc->sc_txfree != ofree) { 1433 /* 1434 * Start the transmit process. Note, the manual says 1435 * that if there are no pending transmissions in the 1436 * chip's internal queue (indicated by TXE being clear), 1437 * then the driver software must set the TXDP to the 1438 * first descriptor to be transmitted. However, if we 1439 * do this, it causes serious performance degredation on 1440 * the DP83820 under load, not setting TXDP doesn't seem 1441 * to adversely affect the SiS 900 or DP83815. 1442 * 1443 * Well, I guess it wouldn't be the first time a manual 1444 * has lied -- and they could be speaking of the NULL- 1445 * terminated descriptor list case, rather than OWN- 1446 * terminated rings. 1447 */ 1448 #if 0 1449 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1450 CR_TXE) == 0) { 1451 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1452 SIP_CDTXADDR(sc, firsttx)); 1453 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1454 } 1455 #else 1456 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1457 #endif 1458 1459 /* Set a watchdog timer in case the chip flakes out. */ 1460 #ifdef DP83820 1461 /* Gigabit autonegotiation takes 5 seconds. */ 1462 ifp->if_timer = 10; 1463 #else 1464 ifp->if_timer = 5; 1465 #endif 1466 } 1467 } 1468 1469 /* 1470 * sip_watchdog: [ifnet interface function] 1471 * 1472 * Watchdog timer handler. 1473 */ 1474 static void 1475 SIP_DECL(watchdog)(struct ifnet *ifp) 1476 { 1477 struct sip_softc *sc = ifp->if_softc; 1478 1479 /* 1480 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1481 * If we get a timeout, try and sweep up transmit descriptors. 1482 * If we manage to sweep them all up, ignore the lack of 1483 * interrupt. 1484 */ 1485 SIP_DECL(txintr)(sc); 1486 1487 if (sc->sc_txfree != SIP_NTXDESC) { 1488 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1489 ifp->if_oerrors++; 1490 1491 /* Reset the interface. */ 1492 (void) SIP_DECL(init)(ifp); 1493 } else if (ifp->if_flags & IFF_DEBUG) 1494 printf("%s: recovered from device timeout\n", 1495 sc->sc_dev.dv_xname); 1496 1497 /* Try to get more packets going. */ 1498 SIP_DECL(start)(ifp); 1499 } 1500 1501 /* 1502 * sip_ioctl: [ifnet interface function] 1503 * 1504 * Handle control requests from the operator. 1505 */ 1506 static int 1507 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1508 { 1509 struct sip_softc *sc = ifp->if_softc; 1510 struct ifreq *ifr = (struct ifreq *)data; 1511 int s, error; 1512 1513 s = splnet(); 1514 1515 switch (cmd) { 1516 case SIOCSIFMEDIA: 1517 /* Flow control requires full-duplex mode. */ 1518 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1519 (ifr->ifr_media & IFM_FDX) == 0) 1520 ifr->ifr_media &= ~IFM_ETH_FMASK; 1521 #ifdef DP83820 1522 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1523 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1524 /* We can do both TXPAUSE and RXPAUSE. */ 1525 ifr->ifr_media |= 1526 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1527 } 1528 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1529 } 1530 #else 1531 /* XXX */ 1532 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1533 ifr->ifr_media &= ~IFM_ETH_FMASK; 1534 1535 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1536 if (ifr->ifr_media & IFM_FLOW) { 1537 /* 1538 * Both TXPAUSE and RXPAUSE must be set. 1539 * (SiS900 and DP83815 don't have PAUSE_ASYM 1540 * feature.) 1541 * 1542 * XXX Can SiS900 and DP83815 send PAUSE? 1543 */ 1544 ifr->ifr_media |= 1545 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1546 } 1547 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1548 } 1549 #endif 1550 /* FALLTHROUGH */ 1551 case SIOCGIFMEDIA: 1552 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1553 break; 1554 1555 default: 1556 error = ether_ioctl(ifp, cmd, data); 1557 if (error == ENETRESET) { 1558 /* 1559 * Multicast list has changed; set the hardware filter 1560 * accordingly. 1561 */ 1562 if (ifp->if_flags & IFF_RUNNING) 1563 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1564 error = 0; 1565 } 1566 break; 1567 } 1568 1569 /* Try to get more packets going. */ 1570 SIP_DECL(start)(ifp); 1571 1572 splx(s); 1573 return (error); 1574 } 1575 1576 /* 1577 * sip_intr: 1578 * 1579 * Interrupt service routine. 1580 */ 1581 static int 1582 SIP_DECL(intr)(void *arg) 1583 { 1584 struct sip_softc *sc = arg; 1585 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1586 u_int32_t isr; 1587 int handled = 0; 1588 1589 /* Disable interrupts. */ 1590 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1591 1592 for (;;) { 1593 /* Reading clears interrupt. */ 1594 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1595 if ((isr & sc->sc_imr) == 0) 1596 break; 1597 1598 #if NRND > 0 1599 if (RND_ENABLED(&sc->rnd_source)) 1600 rnd_add_uint32(&sc->rnd_source, isr); 1601 #endif 1602 1603 handled = 1; 1604 1605 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1606 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1607 1608 /* Grab any new packets. */ 1609 SIP_DECL(rxintr)(sc); 1610 1611 if (isr & ISR_RXORN) { 1612 printf("%s: receive FIFO overrun\n", 1613 sc->sc_dev.dv_xname); 1614 1615 /* XXX adjust rx_drain_thresh? */ 1616 } 1617 1618 if (isr & ISR_RXIDLE) { 1619 printf("%s: receive ring overrun\n", 1620 sc->sc_dev.dv_xname); 1621 1622 /* Get the receive process going again. */ 1623 bus_space_write_4(sc->sc_st, sc->sc_sh, 1624 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1625 bus_space_write_4(sc->sc_st, sc->sc_sh, 1626 SIP_CR, CR_RXE); 1627 } 1628 } 1629 1630 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1631 #ifdef SIP_EVENT_COUNTERS 1632 if (isr & ISR_TXDESC) 1633 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1634 else if (isr & ISR_TXIDLE) 1635 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1636 #endif 1637 1638 /* Sweep up transmit descriptors. */ 1639 SIP_DECL(txintr)(sc); 1640 1641 if (isr & ISR_TXURN) { 1642 u_int32_t thresh; 1643 1644 printf("%s: transmit FIFO underrun", 1645 sc->sc_dev.dv_xname); 1646 1647 thresh = sc->sc_tx_drain_thresh + 1; 1648 if (thresh <= TXCFG_DRTH && 1649 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1650 (sc->sc_tx_fill_thresh * 32))) { 1651 printf("; increasing Tx drain " 1652 "threshold to %u bytes\n", 1653 thresh * 32); 1654 sc->sc_tx_drain_thresh = thresh; 1655 (void) SIP_DECL(init)(ifp); 1656 } else { 1657 (void) SIP_DECL(init)(ifp); 1658 printf("\n"); 1659 } 1660 } 1661 } 1662 1663 #if !defined(DP83820) 1664 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1665 if (isr & ISR_PAUSE_ST) { 1666 sc->sc_paused = 1; 1667 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1668 ifp->if_flags |= IFF_OACTIVE; 1669 } 1670 if (isr & ISR_PAUSE_END) { 1671 sc->sc_paused = 0; 1672 ifp->if_flags &= ~IFF_OACTIVE; 1673 } 1674 } 1675 #endif /* ! DP83820 */ 1676 1677 if (isr & ISR_HIBERR) { 1678 int want_init = 0; 1679 1680 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1681 1682 #define PRINTERR(bit, str) \ 1683 do { \ 1684 if ((isr & (bit)) != 0) { \ 1685 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1686 printf("%s: %s\n", \ 1687 sc->sc_dev.dv_xname, str); \ 1688 want_init = 1; \ 1689 } \ 1690 } while (/*CONSTCOND*/0) 1691 1692 PRINTERR(ISR_DPERR, "parity error"); 1693 PRINTERR(ISR_SSERR, "system error"); 1694 PRINTERR(ISR_RMABT, "master abort"); 1695 PRINTERR(ISR_RTABT, "target abort"); 1696 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1697 /* 1698 * Ignore: 1699 * Tx reset complete 1700 * Rx reset complete 1701 */ 1702 if (want_init) 1703 (void) SIP_DECL(init)(ifp); 1704 #undef PRINTERR 1705 } 1706 } 1707 1708 /* Re-enable interrupts. */ 1709 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1710 1711 /* Try to get more packets going. */ 1712 SIP_DECL(start)(ifp); 1713 1714 return (handled); 1715 } 1716 1717 /* 1718 * sip_txintr: 1719 * 1720 * Helper; handle transmit interrupts. 1721 */ 1722 static void 1723 SIP_DECL(txintr)(struct sip_softc *sc) 1724 { 1725 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1726 struct sip_txsoft *txs; 1727 u_int32_t cmdsts; 1728 1729 #ifndef DP83820 1730 if (sc->sc_paused == 0) 1731 #endif 1732 ifp->if_flags &= ~IFF_OACTIVE; 1733 1734 /* 1735 * Go through our Tx list and free mbufs for those 1736 * frames which have been transmitted. 1737 */ 1738 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1739 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1740 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1741 1742 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1743 if (cmdsts & CMDSTS_OWN) 1744 break; 1745 1746 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1747 1748 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1749 1750 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1751 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1752 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1753 m_freem(txs->txs_mbuf); 1754 txs->txs_mbuf = NULL; 1755 1756 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1757 1758 /* 1759 * Check for errors and collisions. 1760 */ 1761 if (cmdsts & 1762 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1763 ifp->if_oerrors++; 1764 if (cmdsts & CMDSTS_Tx_EC) 1765 ifp->if_collisions += 16; 1766 if (ifp->if_flags & IFF_DEBUG) { 1767 if (cmdsts & CMDSTS_Tx_ED) 1768 printf("%s: excessive deferral\n", 1769 sc->sc_dev.dv_xname); 1770 if (cmdsts & CMDSTS_Tx_EC) 1771 printf("%s: excessive collisions\n", 1772 sc->sc_dev.dv_xname); 1773 } 1774 } else { 1775 /* Packet was transmitted successfully. */ 1776 ifp->if_opackets++; 1777 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1778 } 1779 } 1780 1781 /* 1782 * If there are no more pending transmissions, cancel the watchdog 1783 * timer. 1784 */ 1785 if (txs == NULL) { 1786 ifp->if_timer = 0; 1787 sc->sc_txwin = 0; 1788 } 1789 } 1790 1791 #if defined(DP83820) 1792 /* 1793 * sip_rxintr: 1794 * 1795 * Helper; handle receive interrupts. 1796 */ 1797 static void 1798 SIP_DECL(rxintr)(struct sip_softc *sc) 1799 { 1800 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1801 struct sip_rxsoft *rxs; 1802 struct mbuf *m, *tailm; 1803 u_int32_t cmdsts, extsts; 1804 int i, len, frame_len; 1805 1806 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1807 rxs = &sc->sc_rxsoft[i]; 1808 1809 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1810 1811 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1812 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1813 1814 /* 1815 * NOTE: OWN is set if owned by _consumer_. We're the 1816 * consumer of the receive ring, so if the bit is clear, 1817 * we have processed all of the packets. 1818 */ 1819 if ((cmdsts & CMDSTS_OWN) == 0) { 1820 /* 1821 * We have processed all of the receive buffers. 1822 */ 1823 break; 1824 } 1825 1826 if (__predict_false(sc->sc_rxdiscard)) { 1827 SIP_INIT_RXDESC(sc, i); 1828 if ((cmdsts & CMDSTS_MORE) == 0) { 1829 /* Reset our state. */ 1830 sc->sc_rxdiscard = 0; 1831 } 1832 continue; 1833 } 1834 1835 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1836 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1837 1838 m = rxs->rxs_mbuf; 1839 1840 /* 1841 * Add a new receive buffer to the ring. 1842 */ 1843 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1844 /* 1845 * Failed, throw away what we've done so 1846 * far, and discard the rest of the packet. 1847 */ 1848 ifp->if_ierrors++; 1849 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1850 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1851 SIP_INIT_RXDESC(sc, i); 1852 if (cmdsts & CMDSTS_MORE) 1853 sc->sc_rxdiscard = 1; 1854 if (sc->sc_rxhead != NULL) 1855 m_freem(sc->sc_rxhead); 1856 SIP_RXCHAIN_RESET(sc); 1857 continue; 1858 } 1859 1860 SIP_RXCHAIN_LINK(sc, m); 1861 1862 /* 1863 * If this is not the end of the packet, keep 1864 * looking. 1865 */ 1866 if (cmdsts & CMDSTS_MORE) { 1867 sc->sc_rxlen += m->m_len; 1868 continue; 1869 } 1870 1871 /* 1872 * Okay, we have the entire packet now... 1873 */ 1874 *sc->sc_rxtailp = NULL; 1875 m = sc->sc_rxhead; 1876 tailm = sc->sc_rxtail; 1877 frame_len = sc->sc_rxlen; 1878 1879 SIP_RXCHAIN_RESET(sc); 1880 1881 /* 1882 * If an error occurred, update stats and drop the packet. 1883 */ 1884 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1885 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1886 ifp->if_ierrors++; 1887 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1888 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1889 /* Receive overrun handled elsewhere. */ 1890 printf("%s: receive descriptor error\n", 1891 sc->sc_dev.dv_xname); 1892 } 1893 #define PRINTERR(bit, str) \ 1894 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1895 (cmdsts & (bit)) != 0) \ 1896 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1897 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1898 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1899 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1900 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1901 #undef PRINTERR 1902 m_freem(m); 1903 continue; 1904 } 1905 1906 /* 1907 * No errors. 1908 * 1909 * Note, the DP83820 includes the CRC with 1910 * every packet. 1911 */ 1912 len = CMDSTS_SIZE(cmdsts); 1913 frame_len += len; 1914 tailm->m_len = len; 1915 1916 /* 1917 * If the packet is small enough to fit in a 1918 * single header mbuf, allocate one and copy 1919 * the data into it. This greatly reduces 1920 * memory consumption when we receive lots 1921 * of small packets. 1922 */ 1923 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1924 struct mbuf *nm; 1925 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1926 if (nm == NULL) { 1927 ifp->if_ierrors++; 1928 m_freem(m); 1929 continue; 1930 } 1931 nm->m_data += 2; 1932 nm->m_pkthdr.len = nm->m_len = len; 1933 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1934 m_freem(m); 1935 m = nm; 1936 } 1937 #ifndef __NO_STRICT_ALIGNMENT 1938 else { 1939 /* 1940 * The DP83820's receive buffers must be 4-byte 1941 * aligned. But this means that the data after 1942 * the Ethernet header is misaligned. To compensate, 1943 * we have artificially shortened the buffer size 1944 * in the descriptor, and we do an overlapping copy 1945 * of the data two bytes further in (in the first 1946 * buffer of the chain only). 1947 */ 1948 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1949 m->m_len); 1950 m->m_data += 2; 1951 } 1952 #endif /* ! __NO_STRICT_ALIGNMENT */ 1953 1954 /* 1955 * If VLANs are enabled, VLAN packets have been unwrapped 1956 * for us. Associate the tag with the packet. 1957 */ 1958 if (sc->sc_ethercom.ec_nvlans != 0 && 1959 (extsts & EXTSTS_VPKT) != 0) { 1960 struct m_tag *vtag; 1961 1962 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 1963 M_NOWAIT); 1964 if (vtag == NULL) { 1965 ifp->if_ierrors++; 1966 printf("%s: unable to allocate VLAN tag\n", 1967 sc->sc_dev.dv_xname); 1968 m_freem(m); 1969 continue; 1970 } 1971 1972 *(u_int *)(vtag + 1) = ntohs(extsts & EXTSTS_VTCI); 1973 } 1974 1975 /* 1976 * Set the incoming checksum information for the 1977 * packet. 1978 */ 1979 if ((extsts & EXTSTS_IPPKT) != 0) { 1980 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1981 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1982 if (extsts & EXTSTS_Rx_IPERR) 1983 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1984 if (extsts & EXTSTS_TCPPKT) { 1985 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1986 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1987 if (extsts & EXTSTS_Rx_TCPERR) 1988 m->m_pkthdr.csum_flags |= 1989 M_CSUM_TCP_UDP_BAD; 1990 } else if (extsts & EXTSTS_UDPPKT) { 1991 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1992 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1993 if (extsts & EXTSTS_Rx_UDPERR) 1994 m->m_pkthdr.csum_flags |= 1995 M_CSUM_TCP_UDP_BAD; 1996 } 1997 } 1998 1999 ifp->if_ipackets++; 2000 m->m_flags |= M_HASFCS; 2001 m->m_pkthdr.rcvif = ifp; 2002 m->m_pkthdr.len = frame_len; 2003 2004 #if NBPFILTER > 0 2005 /* 2006 * Pass this up to any BPF listeners, but only 2007 * pass if up the stack if it's for us. 2008 */ 2009 if (ifp->if_bpf) 2010 bpf_mtap(ifp->if_bpf, m); 2011 #endif /* NBPFILTER > 0 */ 2012 2013 /* Pass it on. */ 2014 (*ifp->if_input)(ifp, m); 2015 } 2016 2017 /* Update the receive pointer. */ 2018 sc->sc_rxptr = i; 2019 } 2020 #else /* ! DP83820 */ 2021 /* 2022 * sip_rxintr: 2023 * 2024 * Helper; handle receive interrupts. 2025 */ 2026 static void 2027 SIP_DECL(rxintr)(struct sip_softc *sc) 2028 { 2029 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2030 struct sip_rxsoft *rxs; 2031 struct mbuf *m; 2032 u_int32_t cmdsts; 2033 int i, len; 2034 2035 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 2036 rxs = &sc->sc_rxsoft[i]; 2037 2038 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2039 2040 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 2041 2042 /* 2043 * NOTE: OWN is set if owned by _consumer_. We're the 2044 * consumer of the receive ring, so if the bit is clear, 2045 * we have processed all of the packets. 2046 */ 2047 if ((cmdsts & CMDSTS_OWN) == 0) { 2048 /* 2049 * We have processed all of the receive buffers. 2050 */ 2051 break; 2052 } 2053 2054 /* 2055 * If any collisions were seen on the wire, count one. 2056 */ 2057 if (cmdsts & CMDSTS_Rx_COL) 2058 ifp->if_collisions++; 2059 2060 /* 2061 * If an error occurred, update stats, clear the status 2062 * word, and leave the packet buffer in place. It will 2063 * simply be reused the next time the ring comes around. 2064 */ 2065 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2066 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2067 ifp->if_ierrors++; 2068 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2069 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2070 /* Receive overrun handled elsewhere. */ 2071 printf("%s: receive descriptor error\n", 2072 sc->sc_dev.dv_xname); 2073 } 2074 #define PRINTERR(bit, str) \ 2075 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2076 (cmdsts & (bit)) != 0) \ 2077 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 2078 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2079 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2080 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2081 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2082 #undef PRINTERR 2083 SIP_INIT_RXDESC(sc, i); 2084 continue; 2085 } 2086 2087 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2088 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2089 2090 /* 2091 * No errors; receive the packet. Note, the SiS 900 2092 * includes the CRC with every packet. 2093 */ 2094 len = CMDSTS_SIZE(cmdsts); 2095 2096 #ifdef __NO_STRICT_ALIGNMENT 2097 /* 2098 * If the packet is small enough to fit in a 2099 * single header mbuf, allocate one and copy 2100 * the data into it. This greatly reduces 2101 * memory consumption when we receive lots 2102 * of small packets. 2103 * 2104 * Otherwise, we add a new buffer to the receive 2105 * chain. If this fails, we drop the packet and 2106 * recycle the old buffer. 2107 */ 2108 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 2109 MGETHDR(m, M_DONTWAIT, MT_DATA); 2110 if (m == NULL) 2111 goto dropit; 2112 memcpy(mtod(m, caddr_t), 2113 mtod(rxs->rxs_mbuf, caddr_t), len); 2114 SIP_INIT_RXDESC(sc, i); 2115 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2116 rxs->rxs_dmamap->dm_mapsize, 2117 BUS_DMASYNC_PREREAD); 2118 } else { 2119 m = rxs->rxs_mbuf; 2120 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 2121 dropit: 2122 ifp->if_ierrors++; 2123 SIP_INIT_RXDESC(sc, i); 2124 bus_dmamap_sync(sc->sc_dmat, 2125 rxs->rxs_dmamap, 0, 2126 rxs->rxs_dmamap->dm_mapsize, 2127 BUS_DMASYNC_PREREAD); 2128 continue; 2129 } 2130 } 2131 #else 2132 /* 2133 * The SiS 900's receive buffers must be 4-byte aligned. 2134 * But this means that the data after the Ethernet header 2135 * is misaligned. We must allocate a new buffer and 2136 * copy the data, shifted forward 2 bytes. 2137 */ 2138 MGETHDR(m, M_DONTWAIT, MT_DATA); 2139 if (m == NULL) { 2140 dropit: 2141 ifp->if_ierrors++; 2142 SIP_INIT_RXDESC(sc, i); 2143 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2144 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2145 continue; 2146 } 2147 if (len > (MHLEN - 2)) { 2148 MCLGET(m, M_DONTWAIT); 2149 if ((m->m_flags & M_EXT) == 0) { 2150 m_freem(m); 2151 goto dropit; 2152 } 2153 } 2154 m->m_data += 2; 2155 2156 /* 2157 * Note that we use clusters for incoming frames, so the 2158 * buffer is virtually contiguous. 2159 */ 2160 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 2161 2162 /* Allow the receive descriptor to continue using its mbuf. */ 2163 SIP_INIT_RXDESC(sc, i); 2164 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2165 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2166 #endif /* __NO_STRICT_ALIGNMENT */ 2167 2168 ifp->if_ipackets++; 2169 m->m_flags |= M_HASFCS; 2170 m->m_pkthdr.rcvif = ifp; 2171 m->m_pkthdr.len = m->m_len = len; 2172 2173 #if NBPFILTER > 0 2174 /* 2175 * Pass this up to any BPF listeners, but only 2176 * pass if up the stack if it's for us. 2177 */ 2178 if (ifp->if_bpf) 2179 bpf_mtap(ifp->if_bpf, m); 2180 #endif /* NBPFILTER > 0 */ 2181 2182 /* Pass it on. */ 2183 (*ifp->if_input)(ifp, m); 2184 } 2185 2186 /* Update the receive pointer. */ 2187 sc->sc_rxptr = i; 2188 } 2189 #endif /* DP83820 */ 2190 2191 /* 2192 * sip_tick: 2193 * 2194 * One second timer, used to tick the MII. 2195 */ 2196 static void 2197 SIP_DECL(tick)(void *arg) 2198 { 2199 struct sip_softc *sc = arg; 2200 int s; 2201 2202 s = splnet(); 2203 #ifdef DP83820 2204 #ifdef SIP_EVENT_COUNTERS 2205 /* Read PAUSE related counts from MIB registers. */ 2206 sc->sc_ev_rxpause.ev_count += 2207 bus_space_read_4(sc->sc_st, sc->sc_sh, 2208 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2209 sc->sc_ev_txpause.ev_count += 2210 bus_space_read_4(sc->sc_st, sc->sc_sh, 2211 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2212 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2213 #endif /* SIP_EVENT_COUNTERS */ 2214 #endif /* DP83820 */ 2215 mii_tick(&sc->sc_mii); 2216 splx(s); 2217 2218 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2219 } 2220 2221 /* 2222 * sip_reset: 2223 * 2224 * Perform a soft reset on the SiS 900. 2225 */ 2226 static void 2227 SIP_DECL(reset)(struct sip_softc *sc) 2228 { 2229 bus_space_tag_t st = sc->sc_st; 2230 bus_space_handle_t sh = sc->sc_sh; 2231 int i; 2232 2233 bus_space_write_4(st, sh, SIP_IER, 0); 2234 bus_space_write_4(st, sh, SIP_IMR, 0); 2235 bus_space_write_4(st, sh, SIP_RFCR, 0); 2236 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2237 2238 for (i = 0; i < SIP_TIMEOUT; i++) { 2239 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2240 break; 2241 delay(2); 2242 } 2243 2244 if (i == SIP_TIMEOUT) 2245 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2246 2247 delay(1000); 2248 2249 #ifdef DP83820 2250 /* 2251 * Set the general purpose I/O bits. Do it here in case we 2252 * need to have GPIO set up to talk to the media interface. 2253 */ 2254 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2255 delay(1000); 2256 #endif /* DP83820 */ 2257 } 2258 2259 /* 2260 * sip_init: [ ifnet interface function ] 2261 * 2262 * Initialize the interface. Must be called at splnet(). 2263 */ 2264 static int 2265 SIP_DECL(init)(struct ifnet *ifp) 2266 { 2267 struct sip_softc *sc = ifp->if_softc; 2268 bus_space_tag_t st = sc->sc_st; 2269 bus_space_handle_t sh = sc->sc_sh; 2270 struct sip_txsoft *txs; 2271 struct sip_rxsoft *rxs; 2272 struct sip_desc *sipd; 2273 #if defined(DP83820) 2274 u_int32_t reg; 2275 #endif 2276 int i, error = 0; 2277 2278 /* 2279 * Cancel any pending I/O. 2280 */ 2281 SIP_DECL(stop)(ifp, 0); 2282 2283 /* 2284 * Reset the chip to a known state. 2285 */ 2286 SIP_DECL(reset)(sc); 2287 2288 #if !defined(DP83820) 2289 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2290 /* 2291 * DP83815 manual, page 78: 2292 * 4.4 Recommended Registers Configuration 2293 * For optimum performance of the DP83815, version noted 2294 * as DP83815CVNG (SRR = 203h), the listed register 2295 * modifications must be followed in sequence... 2296 * 2297 * It's not clear if this should be 302h or 203h because that 2298 * chip name is listed as SRR 302h in the description of the 2299 * SRR register. However, my revision 302h DP83815 on the 2300 * Netgear FA311 purchased in 02/2001 needs these settings 2301 * to avoid tons of errors in AcceptPerfectMatch (non- 2302 * IFF_PROMISC) mode. I do not know if other revisions need 2303 * this set or not. [briggs -- 09 March 2001] 2304 * 2305 * Note that only the low-order 12 bits of 0xe4 are documented 2306 * and that this sets reserved bits in that register. 2307 */ 2308 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2309 2310 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2311 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2312 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2313 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2314 2315 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2316 } 2317 #endif /* ! DP83820 */ 2318 2319 /* 2320 * Initialize the transmit descriptor ring. 2321 */ 2322 for (i = 0; i < SIP_NTXDESC; i++) { 2323 sipd = &sc->sc_txdescs[i]; 2324 memset(sipd, 0, sizeof(struct sip_desc)); 2325 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2326 } 2327 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2328 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2329 sc->sc_txfree = SIP_NTXDESC; 2330 sc->sc_txnext = 0; 2331 sc->sc_txwin = 0; 2332 2333 /* 2334 * Initialize the transmit job descriptors. 2335 */ 2336 SIMPLEQ_INIT(&sc->sc_txfreeq); 2337 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2338 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2339 txs = &sc->sc_txsoft[i]; 2340 txs->txs_mbuf = NULL; 2341 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2342 } 2343 2344 /* 2345 * Initialize the receive descriptor and receive job 2346 * descriptor rings. 2347 */ 2348 for (i = 0; i < SIP_NRXDESC; i++) { 2349 rxs = &sc->sc_rxsoft[i]; 2350 if (rxs->rxs_mbuf == NULL) { 2351 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2352 printf("%s: unable to allocate or map rx " 2353 "buffer %d, error = %d\n", 2354 sc->sc_dev.dv_xname, i, error); 2355 /* 2356 * XXX Should attempt to run with fewer receive 2357 * XXX buffers instead of just failing. 2358 */ 2359 SIP_DECL(rxdrain)(sc); 2360 goto out; 2361 } 2362 } else 2363 SIP_INIT_RXDESC(sc, i); 2364 } 2365 sc->sc_rxptr = 0; 2366 #ifdef DP83820 2367 sc->sc_rxdiscard = 0; 2368 SIP_RXCHAIN_RESET(sc); 2369 #endif /* DP83820 */ 2370 2371 /* 2372 * Set the configuration register; it's already initialized 2373 * in sip_attach(). 2374 */ 2375 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2376 2377 /* 2378 * Initialize the prototype TXCFG register. 2379 */ 2380 #if defined(DP83820) 2381 sc->sc_txcfg = TXCFG_MXDMA_512; 2382 sc->sc_rxcfg = RXCFG_MXDMA_512; 2383 #else 2384 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2385 SIP_SIS900_REV(sc, SIS_REV_960) || 2386 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2387 (sc->sc_cfg & CFG_EDBMASTEN)) { 2388 sc->sc_txcfg = TXCFG_MXDMA_64; 2389 sc->sc_rxcfg = RXCFG_MXDMA_64; 2390 } else { 2391 sc->sc_txcfg = TXCFG_MXDMA_512; 2392 sc->sc_rxcfg = RXCFG_MXDMA_512; 2393 } 2394 #endif /* DP83820 */ 2395 2396 sc->sc_txcfg |= TXCFG_ATP | 2397 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2398 sc->sc_tx_drain_thresh; 2399 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2400 2401 /* 2402 * Initialize the receive drain threshold if we have never 2403 * done so. 2404 */ 2405 if (sc->sc_rx_drain_thresh == 0) { 2406 /* 2407 * XXX This value should be tuned. This is set to the 2408 * maximum of 248 bytes, and we may be able to improve 2409 * performance by decreasing it (although we should never 2410 * set this value lower than 2; 14 bytes are required to 2411 * filter the packet). 2412 */ 2413 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2414 } 2415 2416 /* 2417 * Initialize the prototype RXCFG register. 2418 */ 2419 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2420 #ifdef DP83820 2421 /* 2422 * Accept long packets (including FCS) so we can handle 2423 * 802.1q-tagged frames and jumbo frames properly. 2424 */ 2425 if (ifp->if_mtu > ETHERMTU || 2426 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2427 sc->sc_rxcfg |= RXCFG_ALP; 2428 2429 /* 2430 * Checksum offloading is disabled if the user selects an MTU 2431 * larger than 8109. (FreeBSD says 8152, but there is emperical 2432 * evidence that >8109 does not work on some boards, such as the 2433 * Planex GN-1000TE). 2434 */ 2435 if (ifp->if_mtu > 8109 && 2436 (ifp->if_capenable & 2437 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4))) { 2438 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2439 "disabled.\n", sc->sc_dev.dv_xname); 2440 ifp->if_capenable &= ~(IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4| 2441 IFCAP_CSUM_UDPv4); 2442 ifp->if_csum_flags_tx = 0; 2443 ifp->if_csum_flags_rx = 0; 2444 } 2445 #else 2446 /* 2447 * Accept packets >1518 bytes (including FCS) so we can handle 2448 * 802.1q-tagged frames properly. 2449 */ 2450 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2451 sc->sc_rxcfg |= RXCFG_ALP; 2452 #endif 2453 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2454 2455 #ifdef DP83820 2456 /* 2457 * Initialize the VLAN/IP receive control register. 2458 * We enable checksum computation on all incoming 2459 * packets, and do not reject packets w/ bad checksums. 2460 */ 2461 reg = 0; 2462 if (ifp->if_capenable & 2463 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2464 reg |= VRCR_IPEN; 2465 if (sc->sc_ethercom.ec_nvlans != 0) 2466 reg |= VRCR_VTDEN|VRCR_VTREN; 2467 bus_space_write_4(st, sh, SIP_VRCR, reg); 2468 2469 /* 2470 * Initialize the VLAN/IP transmit control register. 2471 * We enable outgoing checksum computation on a 2472 * per-packet basis. 2473 */ 2474 reg = 0; 2475 if (ifp->if_capenable & 2476 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2477 reg |= VTCR_PPCHK; 2478 if (sc->sc_ethercom.ec_nvlans != 0) 2479 reg |= VTCR_VPPTI; 2480 bus_space_write_4(st, sh, SIP_VTCR, reg); 2481 2482 /* 2483 * If we're using VLANs, initialize the VLAN data register. 2484 * To understand why we bswap the VLAN Ethertype, see section 2485 * 4.2.36 of the DP83820 manual. 2486 */ 2487 if (sc->sc_ethercom.ec_nvlans != 0) 2488 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2489 #endif /* DP83820 */ 2490 2491 /* 2492 * Give the transmit and receive rings to the chip. 2493 */ 2494 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2495 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2496 2497 /* 2498 * Initialize the interrupt mask. 2499 */ 2500 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2501 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2502 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2503 2504 /* Set up the receive filter. */ 2505 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2506 2507 #ifdef DP83820 2508 /* 2509 * Tune sc_rx_flow_thresh. 2510 * XXX "More than 8KB" is too short for jumbo frames. 2511 * XXX TODO: Threshold value should be user-settable. 2512 */ 2513 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2514 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2515 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2516 #endif 2517 2518 /* 2519 * Set the current media. Do this after initializing the prototype 2520 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2521 * control. 2522 */ 2523 mii_mediachg(&sc->sc_mii); 2524 2525 #ifdef DP83820 2526 /* 2527 * Set the interrupt hold-off timer to 100us. 2528 */ 2529 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2530 #endif 2531 2532 /* 2533 * Enable interrupts. 2534 */ 2535 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2536 2537 /* 2538 * Start the transmit and receive processes. 2539 */ 2540 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2541 2542 /* 2543 * Start the one second MII clock. 2544 */ 2545 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2546 2547 /* 2548 * ...all done! 2549 */ 2550 ifp->if_flags |= IFF_RUNNING; 2551 ifp->if_flags &= ~IFF_OACTIVE; 2552 2553 out: 2554 if (error) 2555 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2556 return (error); 2557 } 2558 2559 /* 2560 * sip_drain: 2561 * 2562 * Drain the receive queue. 2563 */ 2564 static void 2565 SIP_DECL(rxdrain)(struct sip_softc *sc) 2566 { 2567 struct sip_rxsoft *rxs; 2568 int i; 2569 2570 for (i = 0; i < SIP_NRXDESC; i++) { 2571 rxs = &sc->sc_rxsoft[i]; 2572 if (rxs->rxs_mbuf != NULL) { 2573 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2574 m_freem(rxs->rxs_mbuf); 2575 rxs->rxs_mbuf = NULL; 2576 } 2577 } 2578 } 2579 2580 /* 2581 * sip_stop: [ ifnet interface function ] 2582 * 2583 * Stop transmission on the interface. 2584 */ 2585 static void 2586 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2587 { 2588 struct sip_softc *sc = ifp->if_softc; 2589 bus_space_tag_t st = sc->sc_st; 2590 bus_space_handle_t sh = sc->sc_sh; 2591 struct sip_txsoft *txs; 2592 u_int32_t cmdsts = 0; /* DEBUG */ 2593 2594 /* 2595 * Stop the one second clock. 2596 */ 2597 callout_stop(&sc->sc_tick_ch); 2598 2599 /* Down the MII. */ 2600 mii_down(&sc->sc_mii); 2601 2602 /* 2603 * Disable interrupts. 2604 */ 2605 bus_space_write_4(st, sh, SIP_IER, 0); 2606 2607 /* 2608 * Stop receiver and transmitter. 2609 */ 2610 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2611 2612 /* 2613 * Release any queued transmit buffers. 2614 */ 2615 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2616 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2617 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2618 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2619 CMDSTS_INTR) == 0) 2620 printf("%s: sip_stop: last descriptor does not " 2621 "have INTR bit set\n", sc->sc_dev.dv_xname); 2622 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2623 #ifdef DIAGNOSTIC 2624 if (txs->txs_mbuf == NULL) { 2625 printf("%s: dirty txsoft with no mbuf chain\n", 2626 sc->sc_dev.dv_xname); 2627 panic("sip_stop"); 2628 } 2629 #endif 2630 cmdsts |= /* DEBUG */ 2631 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2632 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2633 m_freem(txs->txs_mbuf); 2634 txs->txs_mbuf = NULL; 2635 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2636 } 2637 2638 if (disable) 2639 SIP_DECL(rxdrain)(sc); 2640 2641 /* 2642 * Mark the interface down and cancel the watchdog timer. 2643 */ 2644 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2645 ifp->if_timer = 0; 2646 2647 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2648 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2649 printf("%s: sip_stop: no INTR bits set in dirty tx " 2650 "descriptors\n", sc->sc_dev.dv_xname); 2651 } 2652 2653 /* 2654 * sip_read_eeprom: 2655 * 2656 * Read data from the serial EEPROM. 2657 */ 2658 static void 2659 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2660 u_int16_t *data) 2661 { 2662 bus_space_tag_t st = sc->sc_st; 2663 bus_space_handle_t sh = sc->sc_sh; 2664 u_int16_t reg; 2665 int i, x; 2666 2667 for (i = 0; i < wordcnt; i++) { 2668 /* Send CHIP SELECT. */ 2669 reg = EROMAR_EECS; 2670 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2671 2672 /* Shift in the READ opcode. */ 2673 for (x = 3; x > 0; x--) { 2674 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2675 reg |= EROMAR_EEDI; 2676 else 2677 reg &= ~EROMAR_EEDI; 2678 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2679 bus_space_write_4(st, sh, SIP_EROMAR, 2680 reg | EROMAR_EESK); 2681 delay(4); 2682 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2683 delay(4); 2684 } 2685 2686 /* Shift in address. */ 2687 for (x = 6; x > 0; x--) { 2688 if ((word + i) & (1 << (x - 1))) 2689 reg |= EROMAR_EEDI; 2690 else 2691 reg &= ~EROMAR_EEDI; 2692 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2693 bus_space_write_4(st, sh, SIP_EROMAR, 2694 reg | EROMAR_EESK); 2695 delay(4); 2696 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2697 delay(4); 2698 } 2699 2700 /* Shift out data. */ 2701 reg = EROMAR_EECS; 2702 data[i] = 0; 2703 for (x = 16; x > 0; x--) { 2704 bus_space_write_4(st, sh, SIP_EROMAR, 2705 reg | EROMAR_EESK); 2706 delay(4); 2707 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2708 data[i] |= (1 << (x - 1)); 2709 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2710 delay(4); 2711 } 2712 2713 /* Clear CHIP SELECT. */ 2714 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2715 delay(4); 2716 } 2717 } 2718 2719 /* 2720 * sip_add_rxbuf: 2721 * 2722 * Add a receive buffer to the indicated descriptor. 2723 */ 2724 static int 2725 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2726 { 2727 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2728 struct mbuf *m; 2729 int error; 2730 2731 MGETHDR(m, M_DONTWAIT, MT_DATA); 2732 if (m == NULL) 2733 return (ENOBUFS); 2734 2735 MCLGET(m, M_DONTWAIT); 2736 if ((m->m_flags & M_EXT) == 0) { 2737 m_freem(m); 2738 return (ENOBUFS); 2739 } 2740 2741 #if defined(DP83820) 2742 m->m_len = SIP_RXBUF_LEN; 2743 #endif /* DP83820 */ 2744 2745 if (rxs->rxs_mbuf != NULL) 2746 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2747 2748 rxs->rxs_mbuf = m; 2749 2750 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2751 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2752 BUS_DMA_READ|BUS_DMA_NOWAIT); 2753 if (error) { 2754 printf("%s: can't load rx DMA map %d, error = %d\n", 2755 sc->sc_dev.dv_xname, idx, error); 2756 panic("sip_add_rxbuf"); /* XXX */ 2757 } 2758 2759 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2760 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2761 2762 SIP_INIT_RXDESC(sc, idx); 2763 2764 return (0); 2765 } 2766 2767 #if !defined(DP83820) 2768 /* 2769 * sip_sis900_set_filter: 2770 * 2771 * Set up the receive filter. 2772 */ 2773 static void 2774 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2775 { 2776 bus_space_tag_t st = sc->sc_st; 2777 bus_space_handle_t sh = sc->sc_sh; 2778 struct ethercom *ec = &sc->sc_ethercom; 2779 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2780 struct ether_multi *enm; 2781 u_int8_t *cp; 2782 struct ether_multistep step; 2783 u_int32_t crc, mchash[16]; 2784 2785 /* 2786 * Initialize the prototype RFCR. 2787 */ 2788 sc->sc_rfcr = RFCR_RFEN; 2789 if (ifp->if_flags & IFF_BROADCAST) 2790 sc->sc_rfcr |= RFCR_AAB; 2791 if (ifp->if_flags & IFF_PROMISC) { 2792 sc->sc_rfcr |= RFCR_AAP; 2793 goto allmulti; 2794 } 2795 2796 /* 2797 * Set up the multicast address filter by passing all multicast 2798 * addresses through a CRC generator, and then using the high-order 2799 * 6 bits as an index into the 128 bit multicast hash table (only 2800 * the lower 16 bits of each 32 bit multicast hash register are 2801 * valid). The high order bits select the register, while the 2802 * rest of the bits select the bit within the register. 2803 */ 2804 2805 memset(mchash, 0, sizeof(mchash)); 2806 2807 /* 2808 * SiS900 (at least SiS963) requires us to register the address of 2809 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 2810 */ 2811 crc = 0x0ed423f9; 2812 2813 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2814 SIP_SIS900_REV(sc, SIS_REV_960) || 2815 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2816 /* Just want the 8 most significant bits. */ 2817 crc >>= 24; 2818 } else { 2819 /* Just want the 7 most significant bits. */ 2820 crc >>= 25; 2821 } 2822 2823 /* Set the corresponding bit in the hash table. */ 2824 mchash[crc >> 4] |= 1 << (crc & 0xf); 2825 2826 ETHER_FIRST_MULTI(step, ec, enm); 2827 while (enm != NULL) { 2828 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2829 /* 2830 * We must listen to a range of multicast addresses. 2831 * For now, just accept all multicasts, rather than 2832 * trying to set only those filter bits needed to match 2833 * the range. (At this time, the only use of address 2834 * ranges is for IP multicast routing, for which the 2835 * range is big enough to require all bits set.) 2836 */ 2837 goto allmulti; 2838 } 2839 2840 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2841 2842 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2843 SIP_SIS900_REV(sc, SIS_REV_960) || 2844 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2845 /* Just want the 8 most significant bits. */ 2846 crc >>= 24; 2847 } else { 2848 /* Just want the 7 most significant bits. */ 2849 crc >>= 25; 2850 } 2851 2852 /* Set the corresponding bit in the hash table. */ 2853 mchash[crc >> 4] |= 1 << (crc & 0xf); 2854 2855 ETHER_NEXT_MULTI(step, enm); 2856 } 2857 2858 ifp->if_flags &= ~IFF_ALLMULTI; 2859 goto setit; 2860 2861 allmulti: 2862 ifp->if_flags |= IFF_ALLMULTI; 2863 sc->sc_rfcr |= RFCR_AAM; 2864 2865 setit: 2866 #define FILTER_EMIT(addr, data) \ 2867 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2868 delay(1); \ 2869 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2870 delay(1) 2871 2872 /* 2873 * Disable receive filter, and program the node address. 2874 */ 2875 cp = LLADDR(ifp->if_sadl); 2876 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2877 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2878 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2879 2880 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2881 /* 2882 * Program the multicast hash table. 2883 */ 2884 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2885 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2886 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2887 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2888 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2889 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2890 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2891 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2892 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2893 SIP_SIS900_REV(sc, SIS_REV_960) || 2894 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2895 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2896 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2897 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2898 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2899 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2900 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2901 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2902 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2903 } 2904 } 2905 #undef FILTER_EMIT 2906 2907 /* 2908 * Re-enable the receiver filter. 2909 */ 2910 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2911 } 2912 #endif /* ! DP83820 */ 2913 2914 /* 2915 * sip_dp83815_set_filter: 2916 * 2917 * Set up the receive filter. 2918 */ 2919 static void 2920 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2921 { 2922 bus_space_tag_t st = sc->sc_st; 2923 bus_space_handle_t sh = sc->sc_sh; 2924 struct ethercom *ec = &sc->sc_ethercom; 2925 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2926 struct ether_multi *enm; 2927 u_int8_t *cp; 2928 struct ether_multistep step; 2929 u_int32_t crc, hash, slot, bit; 2930 #ifdef DP83820 2931 #define MCHASH_NWORDS 128 2932 #else 2933 #define MCHASH_NWORDS 32 2934 #endif /* DP83820 */ 2935 u_int16_t mchash[MCHASH_NWORDS]; 2936 int i; 2937 2938 /* 2939 * Initialize the prototype RFCR. 2940 * Enable the receive filter, and accept on 2941 * Perfect (destination address) Match 2942 * If IFF_BROADCAST, also accept all broadcast packets. 2943 * If IFF_PROMISC, accept all unicast packets (and later, set 2944 * IFF_ALLMULTI and accept all multicast, too). 2945 */ 2946 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2947 if (ifp->if_flags & IFF_BROADCAST) 2948 sc->sc_rfcr |= RFCR_AAB; 2949 if (ifp->if_flags & IFF_PROMISC) { 2950 sc->sc_rfcr |= RFCR_AAP; 2951 goto allmulti; 2952 } 2953 2954 #ifdef DP83820 2955 /* 2956 * Set up the DP83820 multicast address filter by passing all multicast 2957 * addresses through a CRC generator, and then using the high-order 2958 * 11 bits as an index into the 2048 bit multicast hash table. The 2959 * high-order 7 bits select the slot, while the low-order 4 bits 2960 * select the bit within the slot. Note that only the low 16-bits 2961 * of each filter word are used, and there are 128 filter words. 2962 */ 2963 #else 2964 /* 2965 * Set up the DP83815 multicast address filter by passing all multicast 2966 * addresses through a CRC generator, and then using the high-order 2967 * 9 bits as an index into the 512 bit multicast hash table. The 2968 * high-order 5 bits select the slot, while the low-order 4 bits 2969 * select the bit within the slot. Note that only the low 16-bits 2970 * of each filter word are used, and there are 32 filter words. 2971 */ 2972 #endif /* DP83820 */ 2973 2974 memset(mchash, 0, sizeof(mchash)); 2975 2976 ifp->if_flags &= ~IFF_ALLMULTI; 2977 ETHER_FIRST_MULTI(step, ec, enm); 2978 if (enm == NULL) 2979 goto setit; 2980 while (enm != NULL) { 2981 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2982 /* 2983 * We must listen to a range of multicast addresses. 2984 * For now, just accept all multicasts, rather than 2985 * trying to set only those filter bits needed to match 2986 * the range. (At this time, the only use of address 2987 * ranges is for IP multicast routing, for which the 2988 * range is big enough to require all bits set.) 2989 */ 2990 goto allmulti; 2991 } 2992 2993 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2994 2995 #ifdef DP83820 2996 /* Just want the 11 most significant bits. */ 2997 hash = crc >> 21; 2998 #else 2999 /* Just want the 9 most significant bits. */ 3000 hash = crc >> 23; 3001 #endif /* DP83820 */ 3002 3003 slot = hash >> 4; 3004 bit = hash & 0xf; 3005 3006 /* Set the corresponding bit in the hash table. */ 3007 mchash[slot] |= 1 << bit; 3008 3009 ETHER_NEXT_MULTI(step, enm); 3010 } 3011 sc->sc_rfcr |= RFCR_MHEN; 3012 goto setit; 3013 3014 allmulti: 3015 ifp->if_flags |= IFF_ALLMULTI; 3016 sc->sc_rfcr |= RFCR_AAM; 3017 3018 setit: 3019 #define FILTER_EMIT(addr, data) \ 3020 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3021 delay(1); \ 3022 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3023 delay(1) 3024 3025 /* 3026 * Disable receive filter, and program the node address. 3027 */ 3028 cp = LLADDR(ifp->if_sadl); 3029 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3030 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3031 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3032 3033 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3034 /* 3035 * Program the multicast hash table. 3036 */ 3037 for (i = 0; i < MCHASH_NWORDS; i++) { 3038 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 3039 mchash[i]); 3040 } 3041 } 3042 #undef FILTER_EMIT 3043 #undef MCHASH_NWORDS 3044 3045 /* 3046 * Re-enable the receiver filter. 3047 */ 3048 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3049 } 3050 3051 #if defined(DP83820) 3052 /* 3053 * sip_dp83820_mii_readreg: [mii interface function] 3054 * 3055 * Read a PHY register on the MII of the DP83820. 3056 */ 3057 static int 3058 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 3059 { 3060 struct sip_softc *sc = (void *) self; 3061 3062 if (sc->sc_cfg & CFG_TBI_EN) { 3063 bus_addr_t tbireg; 3064 int rv; 3065 3066 if (phy != 0) 3067 return (0); 3068 3069 switch (reg) { 3070 case MII_BMCR: tbireg = SIP_TBICR; break; 3071 case MII_BMSR: tbireg = SIP_TBISR; break; 3072 case MII_ANAR: tbireg = SIP_TANAR; break; 3073 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3074 case MII_ANER: tbireg = SIP_TANER; break; 3075 case MII_EXTSR: 3076 /* 3077 * Don't even bother reading the TESR register. 3078 * The manual documents that the device has 3079 * 1000baseX full/half capability, but the 3080 * register itself seems read back 0 on some 3081 * boards. Just hard-code the result. 3082 */ 3083 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3084 3085 default: 3086 return (0); 3087 } 3088 3089 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3090 if (tbireg == SIP_TBISR) { 3091 /* LINK and ACOMP are switched! */ 3092 int val = rv; 3093 3094 rv = 0; 3095 if (val & TBISR_MR_LINK_STATUS) 3096 rv |= BMSR_LINK; 3097 if (val & TBISR_MR_AN_COMPLETE) 3098 rv |= BMSR_ACOMP; 3099 3100 /* 3101 * The manual claims this register reads back 0 3102 * on hard and soft reset. But we want to let 3103 * the gentbi driver know that we support auto- 3104 * negotiation, so hard-code this bit in the 3105 * result. 3106 */ 3107 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3108 } 3109 3110 return (rv); 3111 } 3112 3113 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3114 phy, reg)); 3115 } 3116 3117 /* 3118 * sip_dp83820_mii_writereg: [mii interface function] 3119 * 3120 * Write a PHY register on the MII of the DP83820. 3121 */ 3122 static void 3123 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 3124 { 3125 struct sip_softc *sc = (void *) self; 3126 3127 if (sc->sc_cfg & CFG_TBI_EN) { 3128 bus_addr_t tbireg; 3129 3130 if (phy != 0) 3131 return; 3132 3133 switch (reg) { 3134 case MII_BMCR: tbireg = SIP_TBICR; break; 3135 case MII_ANAR: tbireg = SIP_TANAR; break; 3136 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3137 default: 3138 return; 3139 } 3140 3141 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3142 return; 3143 } 3144 3145 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3146 phy, reg, val); 3147 } 3148 3149 /* 3150 * sip_dp83820_mii_statchg: [mii interface function] 3151 * 3152 * Callback from MII layer when media changes. 3153 */ 3154 static void 3155 SIP_DECL(dp83820_mii_statchg)(struct device *self) 3156 { 3157 struct sip_softc *sc = (struct sip_softc *) self; 3158 struct mii_data *mii = &sc->sc_mii; 3159 u_int32_t cfg, pcr; 3160 3161 /* 3162 * Get flow control negotiation result. 3163 */ 3164 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3165 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3166 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3167 mii->mii_media_active &= ~IFM_ETH_FMASK; 3168 } 3169 3170 /* 3171 * Update TXCFG for full-duplex operation. 3172 */ 3173 if ((mii->mii_media_active & IFM_FDX) != 0) 3174 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3175 else 3176 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3177 3178 /* 3179 * Update RXCFG for full-duplex or loopback. 3180 */ 3181 if ((mii->mii_media_active & IFM_FDX) != 0 || 3182 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3183 sc->sc_rxcfg |= RXCFG_ATX; 3184 else 3185 sc->sc_rxcfg &= ~RXCFG_ATX; 3186 3187 /* 3188 * Update CFG for MII/GMII. 3189 */ 3190 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3191 cfg = sc->sc_cfg | CFG_MODE_1000; 3192 else 3193 cfg = sc->sc_cfg; 3194 3195 /* 3196 * 802.3x flow control. 3197 */ 3198 pcr = 0; 3199 if (sc->sc_flowflags & IFM_FLOW) { 3200 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3201 pcr |= sc->sc_rx_flow_thresh; 3202 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3203 pcr |= PCR_PSEN | PCR_PS_MCAST; 3204 } 3205 3206 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3207 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3208 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3209 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3210 } 3211 #endif /* ! DP83820 */ 3212 3213 /* 3214 * sip_mii_bitbang_read: [mii bit-bang interface function] 3215 * 3216 * Read the MII serial port for the MII bit-bang module. 3217 */ 3218 static u_int32_t 3219 SIP_DECL(mii_bitbang_read)(struct device *self) 3220 { 3221 struct sip_softc *sc = (void *) self; 3222 3223 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3224 } 3225 3226 /* 3227 * sip_mii_bitbang_write: [mii big-bang interface function] 3228 * 3229 * Write the MII serial port for the MII bit-bang module. 3230 */ 3231 static void 3232 SIP_DECL(mii_bitbang_write)(struct device *self, u_int32_t val) 3233 { 3234 struct sip_softc *sc = (void *) self; 3235 3236 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3237 } 3238 3239 #ifndef DP83820 3240 /* 3241 * sip_sis900_mii_readreg: [mii interface function] 3242 * 3243 * Read a PHY register on the MII. 3244 */ 3245 static int 3246 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 3247 { 3248 struct sip_softc *sc = (struct sip_softc *) self; 3249 u_int32_t enphy; 3250 3251 /* 3252 * The PHY of recent SiS chipsets is accessed through bitbang 3253 * operations. 3254 */ 3255 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3256 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3257 phy, reg)); 3258 3259 #ifndef SIS900_MII_RESTRICT 3260 /* 3261 * The SiS 900 has only an internal PHY on the MII. Only allow 3262 * MII address 0. 3263 */ 3264 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3265 return (0); 3266 #endif 3267 3268 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3269 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3270 ENPHY_RWCMD | ENPHY_ACCESS); 3271 do { 3272 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3273 } while (enphy & ENPHY_ACCESS); 3274 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3275 } 3276 3277 /* 3278 * sip_sis900_mii_writereg: [mii interface function] 3279 * 3280 * Write a PHY register on the MII. 3281 */ 3282 static void 3283 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 3284 { 3285 struct sip_softc *sc = (struct sip_softc *) self; 3286 u_int32_t enphy; 3287 3288 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3289 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3290 phy, reg, val); 3291 return; 3292 } 3293 3294 #ifndef SIS900_MII_RESTRICT 3295 /* 3296 * The SiS 900 has only an internal PHY on the MII. Only allow 3297 * MII address 0. 3298 */ 3299 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3300 return; 3301 #endif 3302 3303 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3304 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3305 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3306 do { 3307 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3308 } while (enphy & ENPHY_ACCESS); 3309 } 3310 3311 /* 3312 * sip_sis900_mii_statchg: [mii interface function] 3313 * 3314 * Callback from MII layer when media changes. 3315 */ 3316 static void 3317 SIP_DECL(sis900_mii_statchg)(struct device *self) 3318 { 3319 struct sip_softc *sc = (struct sip_softc *) self; 3320 struct mii_data *mii = &sc->sc_mii; 3321 u_int32_t flowctl; 3322 3323 /* 3324 * Get flow control negotiation result. 3325 */ 3326 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3327 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3328 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3329 mii->mii_media_active &= ~IFM_ETH_FMASK; 3330 } 3331 3332 /* 3333 * Update TXCFG for full-duplex operation. 3334 */ 3335 if ((mii->mii_media_active & IFM_FDX) != 0) 3336 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3337 else 3338 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3339 3340 /* 3341 * Update RXCFG for full-duplex or loopback. 3342 */ 3343 if ((mii->mii_media_active & IFM_FDX) != 0 || 3344 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3345 sc->sc_rxcfg |= RXCFG_ATX; 3346 else 3347 sc->sc_rxcfg &= ~RXCFG_ATX; 3348 3349 /* 3350 * Update IMR for use of 802.3x flow control. 3351 */ 3352 if (sc->sc_flowflags & IFM_FLOW) { 3353 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3354 flowctl = FLOWCTL_FLOWEN; 3355 } else { 3356 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3357 flowctl = 0; 3358 } 3359 3360 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3361 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3362 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3363 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3364 } 3365 3366 /* 3367 * sip_dp83815_mii_readreg: [mii interface function] 3368 * 3369 * Read a PHY register on the MII. 3370 */ 3371 static int 3372 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 3373 { 3374 struct sip_softc *sc = (struct sip_softc *) self; 3375 u_int32_t val; 3376 3377 /* 3378 * The DP83815 only has an internal PHY. Only allow 3379 * MII address 0. 3380 */ 3381 if (phy != 0) 3382 return (0); 3383 3384 /* 3385 * Apparently, after a reset, the DP83815 can take a while 3386 * to respond. During this recovery period, the BMSR returns 3387 * a value of 0. Catch this -- it's not supposed to happen 3388 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3389 * PHY to come back to life. 3390 * 3391 * This works out because the BMSR is the first register 3392 * read during the PHY probe process. 3393 */ 3394 do { 3395 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3396 } while (reg == MII_BMSR && val == 0); 3397 3398 return (val & 0xffff); 3399 } 3400 3401 /* 3402 * sip_dp83815_mii_writereg: [mii interface function] 3403 * 3404 * Write a PHY register to the MII. 3405 */ 3406 static void 3407 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3408 { 3409 struct sip_softc *sc = (struct sip_softc *) self; 3410 3411 /* 3412 * The DP83815 only has an internal PHY. Only allow 3413 * MII address 0. 3414 */ 3415 if (phy != 0) 3416 return; 3417 3418 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3419 } 3420 3421 /* 3422 * sip_dp83815_mii_statchg: [mii interface function] 3423 * 3424 * Callback from MII layer when media changes. 3425 */ 3426 static void 3427 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3428 { 3429 struct sip_softc *sc = (struct sip_softc *) self; 3430 3431 /* 3432 * Update TXCFG for full-duplex operation. 3433 */ 3434 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3435 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3436 else 3437 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3438 3439 /* 3440 * Update RXCFG for full-duplex or loopback. 3441 */ 3442 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3443 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3444 sc->sc_rxcfg |= RXCFG_ATX; 3445 else 3446 sc->sc_rxcfg &= ~RXCFG_ATX; 3447 3448 /* 3449 * XXX 802.3x flow control. 3450 */ 3451 3452 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3453 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3454 3455 /* 3456 * Some DP83815s experience problems when used with short 3457 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3458 * sequence adjusts the DSP's signal attenuation to fix the 3459 * problem. 3460 */ 3461 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3462 uint32_t reg; 3463 3464 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3465 3466 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3467 reg &= 0x0fff; 3468 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3469 delay(100); 3470 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3471 reg &= 0x00ff; 3472 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3473 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3474 0x00e8); 3475 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3476 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3477 reg | 0x20); 3478 } 3479 3480 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3481 } 3482 } 3483 #endif /* DP83820 */ 3484 3485 #if defined(DP83820) 3486 static void 3487 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3488 const struct pci_attach_args *pa, u_int8_t *enaddr) 3489 { 3490 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3491 u_int8_t cksum, *e, match; 3492 int i; 3493 3494 /* 3495 * EEPROM data format for the DP83820 can be found in 3496 * the DP83820 manual, section 4.2.4. 3497 */ 3498 3499 SIP_DECL(read_eeprom)(sc, 0, 3500 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3501 3502 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3503 match = ~(match - 1); 3504 3505 cksum = 0x55; 3506 e = (u_int8_t *) eeprom_data; 3507 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3508 cksum += *e++; 3509 3510 if (cksum != match) 3511 printf("%s: Checksum (%x) mismatch (%x)", 3512 sc->sc_dev.dv_xname, cksum, match); 3513 3514 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3515 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3516 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3517 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3518 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3519 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3520 } 3521 #else /* ! DP83820 */ 3522 static void 3523 SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc) 3524 { 3525 int i; 3526 3527 /* 3528 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3529 * a reason, but I don't know it. 3530 */ 3531 for (i = 0; i < 10; i++) 3532 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3533 } 3534 3535 static void 3536 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3537 const struct pci_attach_args *pa, u_int8_t *enaddr) 3538 { 3539 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3540 3541 switch (sc->sc_rev) { 3542 case SIS_REV_630S: 3543 case SIS_REV_630E: 3544 case SIS_REV_630EA1: 3545 case SIS_REV_630ET: 3546 case SIS_REV_635: 3547 /* 3548 * The MAC address for the on-board Ethernet of 3549 * the SiS 630 chipset is in the NVRAM. Kick 3550 * the chip into re-loading it from NVRAM, and 3551 * read the MAC address out of the filter registers. 3552 */ 3553 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3554 3555 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3556 RFCR_RFADDR_NODE0); 3557 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3558 0xffff; 3559 3560 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3561 RFCR_RFADDR_NODE2); 3562 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3563 0xffff; 3564 3565 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3566 RFCR_RFADDR_NODE4); 3567 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3568 0xffff; 3569 break; 3570 3571 case SIS_REV_960: 3572 { 3573 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3574 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3575 3576 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3577 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3578 3579 int waittime, i; 3580 3581 /* Allow to read EEPROM from LAN. It is shared 3582 * between a 1394 controller and the NIC and each 3583 * time we access it, we need to set SIS_EECMD_REQ. 3584 */ 3585 SIS_SET_EROMAR(sc, EROMAR_REQ); 3586 3587 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3588 /* Force EEPROM to idle state. */ 3589 3590 /* 3591 * XXX-cube This is ugly. I'll look for docs about it. 3592 */ 3593 SIS_SET_EROMAR(sc, EROMAR_EECS); 3594 SIP_DECL(sis900_eeprom_delay)(sc); 3595 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3596 SIS_SET_EROMAR(sc, EROMAR_EESK); 3597 SIP_DECL(sis900_eeprom_delay)(sc); 3598 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3599 SIP_DECL(sis900_eeprom_delay)(sc); 3600 } 3601 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3602 SIP_DECL(sis900_eeprom_delay)(sc); 3603 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3604 3605 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3606 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3607 sizeof(myea) / sizeof(myea[0]), myea); 3608 break; 3609 } 3610 DELAY(1); 3611 } 3612 3613 /* 3614 * Set SIS_EECTL_CLK to high, so a other master 3615 * can operate on the i2c bus. 3616 */ 3617 SIS_SET_EROMAR(sc, EROMAR_EESK); 3618 3619 /* Refuse EEPROM access by LAN */ 3620 SIS_SET_EROMAR(sc, EROMAR_DONE); 3621 } break; 3622 3623 default: 3624 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3625 sizeof(myea) / sizeof(myea[0]), myea); 3626 } 3627 3628 enaddr[0] = myea[0] & 0xff; 3629 enaddr[1] = myea[0] >> 8; 3630 enaddr[2] = myea[1] & 0xff; 3631 enaddr[3] = myea[1] >> 8; 3632 enaddr[4] = myea[2] & 0xff; 3633 enaddr[5] = myea[2] >> 8; 3634 } 3635 3636 /* Table and macro to bit-reverse an octet. */ 3637 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3638 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3639 3640 static void 3641 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3642 const struct pci_attach_args *pa, u_int8_t *enaddr) 3643 { 3644 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3645 u_int8_t cksum, *e, match; 3646 int i; 3647 3648 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3649 sizeof(eeprom_data[0]), eeprom_data); 3650 3651 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3652 match = ~(match - 1); 3653 3654 cksum = 0x55; 3655 e = (u_int8_t *) eeprom_data; 3656 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3657 cksum += *e++; 3658 } 3659 if (cksum != match) { 3660 printf("%s: Checksum (%x) mismatch (%x)", 3661 sc->sc_dev.dv_xname, cksum, match); 3662 } 3663 3664 /* 3665 * Unrolled because it makes slightly more sense this way. 3666 * The DP83815 stores the MAC address in bit 0 of word 6 3667 * through bit 15 of word 8. 3668 */ 3669 ea = &eeprom_data[6]; 3670 enaddr[0] = ((*ea & 0x1) << 7); 3671 ea++; 3672 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3673 enaddr[1] = ((*ea & 0x1FE) >> 1); 3674 enaddr[2] = ((*ea & 0x1) << 7); 3675 ea++; 3676 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3677 enaddr[3] = ((*ea & 0x1FE) >> 1); 3678 enaddr[4] = ((*ea & 0x1) << 7); 3679 ea++; 3680 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3681 enaddr[5] = ((*ea & 0x1FE) >> 1); 3682 3683 /* 3684 * In case that's not weird enough, we also need to reverse 3685 * the bits in each byte. This all actually makes more sense 3686 * if you think about the EEPROM storage as an array of bits 3687 * being shifted into bytes, but that's not how we're looking 3688 * at it here... 3689 */ 3690 for (i = 0; i < 6 ;i++) 3691 enaddr[i] = bbr(enaddr[i]); 3692 } 3693 #endif /* DP83820 */ 3694 3695 /* 3696 * sip_mediastatus: [ifmedia interface function] 3697 * 3698 * Get the current interface media status. 3699 */ 3700 static void 3701 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3702 { 3703 struct sip_softc *sc = ifp->if_softc; 3704 3705 mii_pollstat(&sc->sc_mii); 3706 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3707 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3708 sc->sc_flowflags; 3709 } 3710 3711 /* 3712 * sip_mediachange: [ifmedia interface function] 3713 * 3714 * Set hardware to newly-selected media. 3715 */ 3716 static int 3717 SIP_DECL(mediachange)(struct ifnet *ifp) 3718 { 3719 struct sip_softc *sc = ifp->if_softc; 3720 3721 if (ifp->if_flags & IFF_UP) 3722 mii_mediachg(&sc->sc_mii); 3723 return (0); 3724 } 3725
Indexes created Tue Sep 30 11:09:46 GMT 2025