if_sip.c revision 1.98
1 /* $NetBSD: if_sip.c,v 1.98 2005/02/06 03:15:14 kim Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.98 2005/02/06 03:15:14 kim Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <machine/bus.h> 116 #include <machine/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/mii_bitbang.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/pci/if_sipreg.h> 128 129 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 130 #define SIP_DECL(x) __CONCAT(gsip_,x) 131 #else /* SiS900 and DP83815 */ 132 #define SIP_DECL(x) __CONCAT(sip_,x) 133 #endif 134 135 #define SIP_STR(x) __STRING(SIP_DECL(x)) 136 137 /* 138 * Transmit descriptor list size. This is arbitrary, but allocate 139 * enough descriptors for 128 pending transmissions, and 8 segments 140 * per packet (64 for DP83820 for jumbo frames). 141 * 142 * This MUST work out to a power of 2. 143 */ 144 #ifdef DP83820 145 #define SIP_NTXSEGS 64 146 #define SIP_NTXSEGS_ALLOC 16 147 #else 148 #define SIP_NTXSEGS 16 149 #define SIP_NTXSEGS_ALLOC 8 150 #endif 151 152 #define SIP_TXQUEUELEN 256 153 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 154 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 155 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 156 157 #if defined(DP83820) 158 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 159 #else 160 #define TX_DMAMAP_SIZE MCLBYTES 161 #endif 162 163 /* 164 * Receive descriptor list size. We have one Rx buffer per incoming 165 * packet, so this logic is a little simpler. 166 * 167 * Actually, on the DP83820, we allow the packet to consume more than 168 * one buffer, in order to support jumbo Ethernet frames. In that 169 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 170 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 171 * so we'd better be quick about handling receive interrupts. 172 */ 173 #if defined(DP83820) 174 #define SIP_NRXDESC 256 175 #else 176 #define SIP_NRXDESC 128 177 #endif /* DP83820 */ 178 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 179 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 180 181 /* 182 * Control structures are DMA'd to the SiS900 chip. We allocate them in 183 * a single clump that maps to a single DMA segment to make several things 184 * easier. 185 */ 186 struct sip_control_data { 187 /* 188 * The transmit descriptors. 189 */ 190 struct sip_desc scd_txdescs[SIP_NTXDESC]; 191 192 /* 193 * The receive descriptors. 194 */ 195 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 196 }; 197 198 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 199 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 200 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 201 202 /* 203 * Software state for transmit jobs. 204 */ 205 struct sip_txsoft { 206 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 207 bus_dmamap_t txs_dmamap; /* our DMA map */ 208 int txs_firstdesc; /* first descriptor in packet */ 209 int txs_lastdesc; /* last descriptor in packet */ 210 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 211 }; 212 213 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 214 215 /* 216 * Software state for receive jobs. 217 */ 218 struct sip_rxsoft { 219 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 220 bus_dmamap_t rxs_dmamap; /* our DMA map */ 221 }; 222 223 /* 224 * Software state per device. 225 */ 226 struct sip_softc { 227 struct device sc_dev; /* generic device information */ 228 bus_space_tag_t sc_st; /* bus space tag */ 229 bus_space_handle_t sc_sh; /* bus space handle */ 230 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 231 struct ethercom sc_ethercom; /* ethernet common data */ 232 void *sc_sdhook; /* shutdown hook */ 233 234 const struct sip_product *sc_model; /* which model are we? */ 235 int sc_rev; /* chip revision */ 236 237 void *sc_ih; /* interrupt cookie */ 238 239 struct mii_data sc_mii; /* MII/media information */ 240 241 struct callout sc_tick_ch; /* tick callout */ 242 243 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 244 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 245 246 /* 247 * Software state for transmit and receive descriptors. 248 */ 249 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 250 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 251 252 /* 253 * Control data structures. 254 */ 255 struct sip_control_data *sc_control_data; 256 #define sc_txdescs sc_control_data->scd_txdescs 257 #define sc_rxdescs sc_control_data->scd_rxdescs 258 259 #ifdef SIP_EVENT_COUNTERS 260 /* 261 * Event counters. 262 */ 263 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 264 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 265 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 266 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 267 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 268 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 269 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 270 struct evcnt sc_ev_rxpause; /* PAUSE received */ 271 #ifdef DP83820 272 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 273 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 274 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 275 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 276 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 277 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 278 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 279 #endif /* DP83820 */ 280 #endif /* SIP_EVENT_COUNTERS */ 281 282 u_int32_t sc_txcfg; /* prototype TXCFG register */ 283 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 284 u_int32_t sc_imr; /* prototype IMR register */ 285 u_int32_t sc_rfcr; /* prototype RFCR register */ 286 287 u_int32_t sc_cfg; /* prototype CFG register */ 288 289 #ifdef DP83820 290 u_int32_t sc_gpior; /* prototype GPIOR register */ 291 #endif /* DP83820 */ 292 293 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 294 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 295 296 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 297 298 int sc_flowflags; /* 802.3x flow control flags */ 299 #ifdef DP83820 300 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 301 #else 302 int sc_paused; /* paused indication */ 303 #endif 304 305 int sc_txfree; /* number of free Tx descriptors */ 306 int sc_txnext; /* next ready Tx descriptor */ 307 int sc_txwin; /* Tx descriptors since last intr */ 308 309 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 310 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 311 312 short sc_if_flags; 313 314 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 315 #if defined(DP83820) 316 int sc_rxdiscard; 317 int sc_rxlen; 318 struct mbuf *sc_rxhead; 319 struct mbuf *sc_rxtail; 320 struct mbuf **sc_rxtailp; 321 #endif /* DP83820 */ 322 323 #if NRND > 0 324 rndsource_element_t rnd_source; /* random source */ 325 #endif 326 }; 327 328 #ifdef DP83820 329 #define SIP_RXCHAIN_RESET(sc) \ 330 do { \ 331 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 332 *(sc)->sc_rxtailp = NULL; \ 333 (sc)->sc_rxlen = 0; \ 334 } while (/*CONSTCOND*/0) 335 336 #define SIP_RXCHAIN_LINK(sc, m) \ 337 do { \ 338 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 339 (sc)->sc_rxtailp = &(m)->m_next; \ 340 } while (/*CONSTCOND*/0) 341 #endif /* DP83820 */ 342 343 #ifdef SIP_EVENT_COUNTERS 344 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 345 #else 346 #define SIP_EVCNT_INCR(ev) /* nothing */ 347 #endif 348 349 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 350 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 351 352 #define SIP_CDTXSYNC(sc, x, n, ops) \ 353 do { \ 354 int __x, __n; \ 355 \ 356 __x = (x); \ 357 __n = (n); \ 358 \ 359 /* If it will wrap around, sync to the end of the ring. */ \ 360 if ((__x + __n) > SIP_NTXDESC) { \ 361 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 362 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 363 (SIP_NTXDESC - __x), (ops)); \ 364 __n -= (SIP_NTXDESC - __x); \ 365 __x = 0; \ 366 } \ 367 \ 368 /* Now sync whatever is left. */ \ 369 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 370 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 371 } while (0) 372 373 #define SIP_CDRXSYNC(sc, x, ops) \ 374 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 375 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 376 377 #ifdef DP83820 378 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 379 #define SIP_RXBUF_LEN (MCLBYTES - 8) 380 #else 381 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 382 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 383 #endif 384 #define SIP_INIT_RXDESC(sc, x) \ 385 do { \ 386 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 387 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 388 \ 389 __sipd->sipd_link = \ 390 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 391 __sipd->sipd_bufptr = \ 392 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 393 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 394 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 395 SIP_INIT_RXDESC_EXTSTS \ 396 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 397 } while (0) 398 399 #define SIP_CHIP_VERS(sc, v, p, r) \ 400 ((sc)->sc_model->sip_vendor == (v) && \ 401 (sc)->sc_model->sip_product == (p) && \ 402 (sc)->sc_rev == (r)) 403 404 #define SIP_CHIP_MODEL(sc, v, p) \ 405 ((sc)->sc_model->sip_vendor == (v) && \ 406 (sc)->sc_model->sip_product == (p)) 407 408 #if !defined(DP83820) 409 #define SIP_SIS900_REV(sc, rev) \ 410 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 411 #endif 412 413 #define SIP_TIMEOUT 1000 414 415 static void SIP_DECL(start)(struct ifnet *); 416 static void SIP_DECL(watchdog)(struct ifnet *); 417 static int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 418 static int SIP_DECL(init)(struct ifnet *); 419 static void SIP_DECL(stop)(struct ifnet *, int); 420 421 static void SIP_DECL(shutdown)(void *); 422 423 static void SIP_DECL(reset)(struct sip_softc *); 424 static void SIP_DECL(rxdrain)(struct sip_softc *); 425 static int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 426 static void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, 427 u_int16_t *); 428 static void SIP_DECL(tick)(void *); 429 430 #if !defined(DP83820) 431 static void SIP_DECL(sis900_set_filter)(struct sip_softc *); 432 #endif /* ! DP83820 */ 433 static void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 434 435 #if defined(DP83820) 436 static void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 437 const struct pci_attach_args *, u_int8_t *); 438 #else 439 static void SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc); 440 static void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 441 const struct pci_attach_args *, u_int8_t *); 442 static void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 443 const struct pci_attach_args *, u_int8_t *); 444 #endif /* DP83820 */ 445 446 static int SIP_DECL(intr)(void *); 447 static void SIP_DECL(txintr)(struct sip_softc *); 448 static void SIP_DECL(rxintr)(struct sip_softc *); 449 450 #if defined(DP83820) 451 static int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 452 static void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 453 static void SIP_DECL(dp83820_mii_statchg)(struct device *); 454 #else 455 static int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 456 static void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 457 static void SIP_DECL(sis900_mii_statchg)(struct device *); 458 459 static int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 460 static void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 461 static void SIP_DECL(dp83815_mii_statchg)(struct device *); 462 #endif /* DP83820 */ 463 464 static int SIP_DECL(mediachange)(struct ifnet *); 465 static void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 466 467 static int SIP_DECL(match)(struct device *, struct cfdata *, void *); 468 static void SIP_DECL(attach)(struct device *, struct device *, void *); 469 470 int SIP_DECL(copy_small) = 0; 471 472 #ifdef DP83820 473 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 474 gsip_match, gsip_attach, NULL, NULL); 475 #else 476 CFATTACH_DECL(sip, sizeof(struct sip_softc), 477 sip_match, sip_attach, NULL, NULL); 478 #endif 479 480 /* 481 * Descriptions of the variants of the SiS900. 482 */ 483 struct sip_variant { 484 int (*sipv_mii_readreg)(struct device *, int, int); 485 void (*sipv_mii_writereg)(struct device *, int, int, int); 486 void (*sipv_mii_statchg)(struct device *); 487 void (*sipv_set_filter)(struct sip_softc *); 488 void (*sipv_read_macaddr)(struct sip_softc *, 489 const struct pci_attach_args *, u_int8_t *); 490 }; 491 492 static u_int32_t SIP_DECL(mii_bitbang_read)(struct device *); 493 static void SIP_DECL(mii_bitbang_write)(struct device *, u_int32_t); 494 495 static const struct mii_bitbang_ops SIP_DECL(mii_bitbang_ops) = { 496 SIP_DECL(mii_bitbang_read), 497 SIP_DECL(mii_bitbang_write), 498 { 499 EROMAR_MDIO, /* MII_BIT_MDO */ 500 EROMAR_MDIO, /* MII_BIT_MDI */ 501 EROMAR_MDC, /* MII_BIT_MDC */ 502 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 503 0, /* MII_BIT_DIR_PHY_HOST */ 504 } 505 }; 506 507 #if defined(DP83820) 508 static const struct sip_variant SIP_DECL(variant_dp83820) = { 509 SIP_DECL(dp83820_mii_readreg), 510 SIP_DECL(dp83820_mii_writereg), 511 SIP_DECL(dp83820_mii_statchg), 512 SIP_DECL(dp83815_set_filter), 513 SIP_DECL(dp83820_read_macaddr), 514 }; 515 #else 516 static const struct sip_variant SIP_DECL(variant_sis900) = { 517 SIP_DECL(sis900_mii_readreg), 518 SIP_DECL(sis900_mii_writereg), 519 SIP_DECL(sis900_mii_statchg), 520 SIP_DECL(sis900_set_filter), 521 SIP_DECL(sis900_read_macaddr), 522 }; 523 524 static const struct sip_variant SIP_DECL(variant_dp83815) = { 525 SIP_DECL(dp83815_mii_readreg), 526 SIP_DECL(dp83815_mii_writereg), 527 SIP_DECL(dp83815_mii_statchg), 528 SIP_DECL(dp83815_set_filter), 529 SIP_DECL(dp83815_read_macaddr), 530 }; 531 #endif /* DP83820 */ 532 533 /* 534 * Devices supported by this driver. 535 */ 536 static const struct sip_product { 537 pci_vendor_id_t sip_vendor; 538 pci_product_id_t sip_product; 539 const char *sip_name; 540 const struct sip_variant *sip_variant; 541 } SIP_DECL(products)[] = { 542 #if defined(DP83820) 543 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 544 "NatSemi DP83820 Gigabit Ethernet", 545 &SIP_DECL(variant_dp83820) }, 546 #else 547 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 548 "SiS 900 10/100 Ethernet", 549 &SIP_DECL(variant_sis900) }, 550 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 551 "SiS 7016 10/100 Ethernet", 552 &SIP_DECL(variant_sis900) }, 553 554 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 555 "NatSemi DP83815 10/100 Ethernet", 556 &SIP_DECL(variant_dp83815) }, 557 #endif /* DP83820 */ 558 559 { 0, 0, 560 NULL, 561 NULL }, 562 }; 563 564 static const struct sip_product * 565 SIP_DECL(lookup)(const struct pci_attach_args *pa) 566 { 567 const struct sip_product *sip; 568 569 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 570 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 571 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 572 return (sip); 573 } 574 return (NULL); 575 } 576 577 #ifdef DP83820 578 /* 579 * I really hate stupid hardware vendors. There's a bit in the EEPROM 580 * which indicates if the card can do 64-bit data transfers. Unfortunately, 581 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 582 * which means we try to use 64-bit data transfers on those cards if we 583 * happen to be plugged into a 32-bit slot. 584 * 585 * What we do is use this table of cards known to be 64-bit cards. If 586 * you have a 64-bit card who's subsystem ID is not listed in this table, 587 * send the output of "pcictl dump ..." of the device to me so that your 588 * card will use the 64-bit data path when plugged into a 64-bit slot. 589 * 590 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 591 * June 30, 2002 592 */ 593 static int 594 SIP_DECL(check_64bit)(const struct pci_attach_args *pa) 595 { 596 static const struct { 597 pci_vendor_id_t c64_vendor; 598 pci_product_id_t c64_product; 599 } card64[] = { 600 /* Asante GigaNIX */ 601 { 0x128a, 0x0002 }, 602 603 /* Accton EN1407-T, Planex GN-1000TE */ 604 { 0x1113, 0x1407 }, 605 606 /* Netgear GA-621 */ 607 { 0x1385, 0x621a }, 608 609 /* SMC EZ Card */ 610 { 0x10b8, 0x9462 }, 611 612 { 0, 0} 613 }; 614 pcireg_t subsys; 615 int i; 616 617 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 618 619 for (i = 0; card64[i].c64_vendor != 0; i++) { 620 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 621 PCI_PRODUCT(subsys) == card64[i].c64_product) 622 return (1); 623 } 624 625 return (0); 626 } 627 #endif /* DP83820 */ 628 629 static int 630 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 631 { 632 struct pci_attach_args *pa = aux; 633 634 if (SIP_DECL(lookup)(pa) != NULL) 635 return (1); 636 637 return (0); 638 } 639 640 static void 641 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 642 { 643 struct sip_softc *sc = (struct sip_softc *) self; 644 struct pci_attach_args *pa = aux; 645 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 646 pci_chipset_tag_t pc = pa->pa_pc; 647 pci_intr_handle_t ih; 648 const char *intrstr = NULL; 649 bus_space_tag_t iot, memt; 650 bus_space_handle_t ioh, memh; 651 bus_dma_segment_t seg; 652 int ioh_valid, memh_valid; 653 int i, rseg, error; 654 const struct sip_product *sip; 655 pcireg_t pmode; 656 u_int8_t enaddr[ETHER_ADDR_LEN]; 657 int pmreg; 658 #ifdef DP83820 659 pcireg_t memtype; 660 u_int32_t reg; 661 #endif /* DP83820 */ 662 663 callout_init(&sc->sc_tick_ch); 664 665 sip = SIP_DECL(lookup)(pa); 666 if (sip == NULL) { 667 printf("\n"); 668 panic(SIP_STR(attach) ": impossible"); 669 } 670 sc->sc_rev = PCI_REVISION(pa->pa_class); 671 672 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 673 674 sc->sc_model = sip; 675 676 /* 677 * XXX Work-around broken PXE firmware on some boards. 678 * 679 * The DP83815 shares an address decoder with the MEM BAR 680 * and the ROM BAR. Make sure the ROM BAR is disabled, 681 * so that memory mapped access works. 682 */ 683 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 684 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 685 ~PCI_MAPREG_ROM_ENABLE); 686 687 /* 688 * Map the device. 689 */ 690 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 691 PCI_MAPREG_TYPE_IO, 0, 692 &iot, &ioh, NULL, NULL) == 0); 693 #ifdef DP83820 694 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 695 switch (memtype) { 696 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 697 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 698 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 699 memtype, 0, &memt, &memh, NULL, NULL) == 0); 700 break; 701 default: 702 memh_valid = 0; 703 } 704 #else 705 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 706 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 707 &memt, &memh, NULL, NULL) == 0); 708 #endif /* DP83820 */ 709 710 if (memh_valid) { 711 sc->sc_st = memt; 712 sc->sc_sh = memh; 713 } else if (ioh_valid) { 714 sc->sc_st = iot; 715 sc->sc_sh = ioh; 716 } else { 717 printf("%s: unable to map device registers\n", 718 sc->sc_dev.dv_xname); 719 return; 720 } 721 722 sc->sc_dmat = pa->pa_dmat; 723 724 /* 725 * Make sure bus mastering is enabled. Also make sure 726 * Write/Invalidate is enabled if we're allowed to use it. 727 */ 728 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 729 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 730 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 731 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 732 pmreg | PCI_COMMAND_MASTER_ENABLE); 733 734 /* Get it out of power save mode if needed. */ 735 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 736 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 737 PCI_PMCSR_STATE_MASK; 738 if (pmode == PCI_PMCSR_STATE_D3) { 739 /* 740 * The card has lost all configuration data in 741 * this state, so punt. 742 */ 743 printf("%s: unable to wake up from power state D3\n", 744 sc->sc_dev.dv_xname); 745 return; 746 } 747 if (pmode != PCI_PMCSR_STATE_D0) { 748 printf("%s: waking up from power state D%d\n", 749 sc->sc_dev.dv_xname, pmode); 750 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 751 PCI_PMCSR_STATE_D0); 752 } 753 } 754 755 /* 756 * Map and establish our interrupt. 757 */ 758 if (pci_intr_map(pa, &ih)) { 759 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 760 return; 761 } 762 intrstr = pci_intr_string(pc, ih); 763 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 764 if (sc->sc_ih == NULL) { 765 printf("%s: unable to establish interrupt", 766 sc->sc_dev.dv_xname); 767 if (intrstr != NULL) 768 printf(" at %s", intrstr); 769 printf("\n"); 770 return; 771 } 772 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 773 774 SIMPLEQ_INIT(&sc->sc_txfreeq); 775 SIMPLEQ_INIT(&sc->sc_txdirtyq); 776 777 /* 778 * Allocate the control data structures, and create and load the 779 * DMA map for it. 780 */ 781 if ((error = bus_dmamem_alloc(sc->sc_dmat, 782 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 783 0)) != 0) { 784 printf("%s: unable to allocate control data, error = %d\n", 785 sc->sc_dev.dv_xname, error); 786 goto fail_0; 787 } 788 789 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 790 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 791 BUS_DMA_COHERENT)) != 0) { 792 printf("%s: unable to map control data, error = %d\n", 793 sc->sc_dev.dv_xname, error); 794 goto fail_1; 795 } 796 797 if ((error = bus_dmamap_create(sc->sc_dmat, 798 sizeof(struct sip_control_data), 1, 799 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 800 printf("%s: unable to create control data DMA map, " 801 "error = %d\n", sc->sc_dev.dv_xname, error); 802 goto fail_2; 803 } 804 805 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 806 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 807 0)) != 0) { 808 printf("%s: unable to load control data DMA map, error = %d\n", 809 sc->sc_dev.dv_xname, error); 810 goto fail_3; 811 } 812 813 /* 814 * Create the transmit buffer DMA maps. 815 */ 816 for (i = 0; i < SIP_TXQUEUELEN; i++) { 817 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 818 SIP_NTXSEGS, MCLBYTES, 0, 0, 819 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 820 printf("%s: unable to create tx DMA map %d, " 821 "error = %d\n", sc->sc_dev.dv_xname, i, error); 822 goto fail_4; 823 } 824 } 825 826 /* 827 * Create the receive buffer DMA maps. 828 */ 829 for (i = 0; i < SIP_NRXDESC; i++) { 830 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 831 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 832 printf("%s: unable to create rx DMA map %d, " 833 "error = %d\n", sc->sc_dev.dv_xname, i, error); 834 goto fail_5; 835 } 836 sc->sc_rxsoft[i].rxs_mbuf = NULL; 837 } 838 839 /* 840 * Reset the chip to a known state. 841 */ 842 SIP_DECL(reset)(sc); 843 844 /* 845 * Read the Ethernet address from the EEPROM. This might 846 * also fetch other stuff from the EEPROM and stash it 847 * in the softc. 848 */ 849 sc->sc_cfg = 0; 850 #if !defined(DP83820) 851 if (SIP_SIS900_REV(sc,SIS_REV_635) || 852 SIP_SIS900_REV(sc,SIS_REV_900B)) 853 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 854 855 if (SIP_SIS900_REV(sc,SIS_REV_635) || 856 SIP_SIS900_REV(sc,SIS_REV_960) || 857 SIP_SIS900_REV(sc,SIS_REV_900B)) 858 sc->sc_cfg |= (bus_space_read_4(sc->sc_st, sc->sc_sh, 859 SIP_CFG) & CFG_EDBMASTEN); 860 #endif 861 862 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 863 864 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 865 ether_sprintf(enaddr)); 866 867 /* 868 * Initialize the configuration register: aggressive PCI 869 * bus request algorithm, default backoff, default OW timer, 870 * default parity error detection. 871 * 872 * NOTE: "Big endian mode" is useless on the SiS900 and 873 * friends -- it affects packet data, not descriptors. 874 */ 875 #ifdef DP83820 876 /* 877 * Cause the chip to load configuration data from the EEPROM. 878 */ 879 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 880 for (i = 0; i < 10000; i++) { 881 delay(10); 882 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 883 PTSCR_EELOAD_EN) == 0) 884 break; 885 } 886 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 887 PTSCR_EELOAD_EN) { 888 printf("%s: timeout loading configuration from EEPROM\n", 889 sc->sc_dev.dv_xname); 890 return; 891 } 892 893 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 894 895 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 896 if (reg & CFG_PCI64_DET) { 897 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 898 /* 899 * Check to see if this card is 64-bit. If so, enable 64-bit 900 * data transfers. 901 * 902 * We can't use the DATA64_EN bit in the EEPROM, because 903 * vendors of 32-bit cards fail to clear that bit in many 904 * cases (yet the card still detects that it's in a 64-bit 905 * slot; go figure). 906 */ 907 if (SIP_DECL(check_64bit)(pa)) { 908 sc->sc_cfg |= CFG_DATA64_EN; 909 printf(", using 64-bit data transfers"); 910 } 911 printf("\n"); 912 } 913 914 /* 915 * XXX Need some PCI flags indicating support for 916 * XXX 64-bit addressing. 917 */ 918 #if 0 919 if (reg & CFG_M64ADDR) 920 sc->sc_cfg |= CFG_M64ADDR; 921 if (reg & CFG_T64ADDR) 922 sc->sc_cfg |= CFG_T64ADDR; 923 #endif 924 925 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 926 const char *sep = ""; 927 printf("%s: using ", sc->sc_dev.dv_xname); 928 if (reg & CFG_EXT_125) { 929 sc->sc_cfg |= CFG_EXT_125; 930 printf("%s125MHz clock", sep); 931 sep = ", "; 932 } 933 if (reg & CFG_TBI_EN) { 934 sc->sc_cfg |= CFG_TBI_EN; 935 printf("%sten-bit interface", sep); 936 sep = ", "; 937 } 938 printf("\n"); 939 } 940 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 941 (reg & CFG_MRM_DIS) != 0) 942 sc->sc_cfg |= CFG_MRM_DIS; 943 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 944 (reg & CFG_MWI_DIS) != 0) 945 sc->sc_cfg |= CFG_MWI_DIS; 946 947 /* 948 * Use the extended descriptor format on the DP83820. This 949 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 950 * checksumming. 951 */ 952 sc->sc_cfg |= CFG_EXTSTS_EN; 953 #endif /* DP83820 */ 954 955 /* 956 * Initialize our media structures and probe the MII. 957 */ 958 sc->sc_mii.mii_ifp = ifp; 959 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 960 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 961 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 962 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, SIP_DECL(mediachange), 963 SIP_DECL(mediastatus)); 964 965 /* 966 * XXX We cannot handle flow control on the DP83815. 967 */ 968 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 969 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 970 MII_OFFSET_ANY, 0); 971 else 972 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 973 MII_OFFSET_ANY, MIIF_DOPAUSE); 974 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 975 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 976 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 977 } else 978 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 979 980 ifp = &sc->sc_ethercom.ec_if; 981 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 982 ifp->if_softc = sc; 983 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 984 sc->sc_if_flags = ifp->if_flags; 985 ifp->if_ioctl = SIP_DECL(ioctl); 986 ifp->if_start = SIP_DECL(start); 987 ifp->if_watchdog = SIP_DECL(watchdog); 988 ifp->if_init = SIP_DECL(init); 989 ifp->if_stop = SIP_DECL(stop); 990 IFQ_SET_READY(&ifp->if_snd); 991 992 /* 993 * We can support 802.1Q VLAN-sized frames. 994 */ 995 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 996 997 #ifdef DP83820 998 /* 999 * And the DP83820 can do VLAN tagging in hardware, and 1000 * support the jumbo Ethernet MTU. 1001 */ 1002 sc->sc_ethercom.ec_capabilities |= 1003 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1004 1005 /* 1006 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1007 * in hardware. 1008 */ 1009 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 1010 IFCAP_CSUM_UDPv4; 1011 #endif /* DP83820 */ 1012 1013 /* 1014 * Attach the interface. 1015 */ 1016 if_attach(ifp); 1017 ether_ifattach(ifp, enaddr); 1018 #if NRND > 0 1019 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1020 RND_TYPE_NET, 0); 1021 #endif 1022 1023 /* 1024 * The number of bytes that must be available in 1025 * the Tx FIFO before the bus master can DMA more 1026 * data into the FIFO. 1027 */ 1028 sc->sc_tx_fill_thresh = 64 / 32; 1029 1030 /* 1031 * Start at a drain threshold of 512 bytes. We will 1032 * increase it if a DMA underrun occurs. 1033 * 1034 * XXX The minimum value of this variable should be 1035 * tuned. We may be able to improve performance 1036 * by starting with a lower value. That, however, 1037 * may trash the first few outgoing packets if the 1038 * PCI bus is saturated. 1039 */ 1040 #ifdef DP83820 1041 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1042 #else 1043 sc->sc_tx_drain_thresh = 1504 / 32; 1044 #endif 1045 1046 /* 1047 * Initialize the Rx FIFO drain threshold. 1048 * 1049 * This is in units of 8 bytes. 1050 * 1051 * We should never set this value lower than 2; 14 bytes are 1052 * required to filter the packet. 1053 */ 1054 sc->sc_rx_drain_thresh = 128 / 8; 1055 1056 #ifdef SIP_EVENT_COUNTERS 1057 /* 1058 * Attach event counters. 1059 */ 1060 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1061 NULL, sc->sc_dev.dv_xname, "txsstall"); 1062 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1063 NULL, sc->sc_dev.dv_xname, "txdstall"); 1064 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1065 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1066 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1067 NULL, sc->sc_dev.dv_xname, "txdintr"); 1068 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1069 NULL, sc->sc_dev.dv_xname, "txiintr"); 1070 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1071 NULL, sc->sc_dev.dv_xname, "rxintr"); 1072 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1073 NULL, sc->sc_dev.dv_xname, "hiberr"); 1074 #ifndef DP83820 1075 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1076 NULL, sc->sc_dev.dv_xname, "rxpause"); 1077 #endif /* !DP83820 */ 1078 #ifdef DP83820 1079 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1080 NULL, sc->sc_dev.dv_xname, "rxpause"); 1081 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1082 NULL, sc->sc_dev.dv_xname, "txpause"); 1083 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1084 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1085 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1086 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1087 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1088 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1089 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1090 NULL, sc->sc_dev.dv_xname, "txipsum"); 1091 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1092 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1093 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1094 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1095 #endif /* DP83820 */ 1096 #endif /* SIP_EVENT_COUNTERS */ 1097 1098 /* 1099 * Make sure the interface is shutdown during reboot. 1100 */ 1101 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 1102 if (sc->sc_sdhook == NULL) 1103 printf("%s: WARNING: unable to establish shutdown hook\n", 1104 sc->sc_dev.dv_xname); 1105 return; 1106 1107 /* 1108 * Free any resources we've allocated during the failed attach 1109 * attempt. Do this in reverse order and fall through. 1110 */ 1111 fail_5: 1112 for (i = 0; i < SIP_NRXDESC; i++) { 1113 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1114 bus_dmamap_destroy(sc->sc_dmat, 1115 sc->sc_rxsoft[i].rxs_dmamap); 1116 } 1117 fail_4: 1118 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1119 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1120 bus_dmamap_destroy(sc->sc_dmat, 1121 sc->sc_txsoft[i].txs_dmamap); 1122 } 1123 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1124 fail_3: 1125 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1126 fail_2: 1127 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1128 sizeof(struct sip_control_data)); 1129 fail_1: 1130 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1131 fail_0: 1132 return; 1133 } 1134 1135 /* 1136 * sip_shutdown: 1137 * 1138 * Make sure the interface is stopped at reboot time. 1139 */ 1140 static void 1141 SIP_DECL(shutdown)(void *arg) 1142 { 1143 struct sip_softc *sc = arg; 1144 1145 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1146 } 1147 1148 /* 1149 * sip_start: [ifnet interface function] 1150 * 1151 * Start packet transmission on the interface. 1152 */ 1153 static void 1154 SIP_DECL(start)(struct ifnet *ifp) 1155 { 1156 struct sip_softc *sc = ifp->if_softc; 1157 struct mbuf *m0; 1158 #ifndef DP83820 1159 struct mbuf *m; 1160 #endif 1161 struct sip_txsoft *txs; 1162 bus_dmamap_t dmamap; 1163 int error, nexttx, lasttx, seg; 1164 int ofree = sc->sc_txfree; 1165 #if 0 1166 int firsttx = sc->sc_txnext; 1167 #endif 1168 #ifdef DP83820 1169 struct m_tag *mtag; 1170 u_int32_t extsts; 1171 #endif 1172 1173 #ifndef DP83820 1174 /* 1175 * If we've been told to pause, don't transmit any more packets. 1176 */ 1177 if (sc->sc_paused) 1178 ifp->if_flags |= IFF_OACTIVE; 1179 #endif 1180 1181 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1182 return; 1183 1184 /* 1185 * Loop through the send queue, setting up transmit descriptors 1186 * until we drain the queue, or use up all available transmit 1187 * descriptors. 1188 */ 1189 for (;;) { 1190 /* Get a work queue entry. */ 1191 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1192 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1193 break; 1194 } 1195 1196 /* 1197 * Grab a packet off the queue. 1198 */ 1199 IFQ_POLL(&ifp->if_snd, m0); 1200 if (m0 == NULL) 1201 break; 1202 #ifndef DP83820 1203 m = NULL; 1204 #endif 1205 1206 dmamap = txs->txs_dmamap; 1207 1208 #ifdef DP83820 1209 /* 1210 * Load the DMA map. If this fails, the packet either 1211 * didn't fit in the allotted number of segments, or we 1212 * were short on resources. For the too-many-segments 1213 * case, we simply report an error and drop the packet, 1214 * since we can't sanely copy a jumbo packet to a single 1215 * buffer. 1216 */ 1217 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1218 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1219 if (error) { 1220 if (error == EFBIG) { 1221 printf("%s: Tx packet consumes too many " 1222 "DMA segments, dropping...\n", 1223 sc->sc_dev.dv_xname); 1224 IFQ_DEQUEUE(&ifp->if_snd, m0); 1225 m_freem(m0); 1226 continue; 1227 } 1228 /* 1229 * Short on resources, just stop for now. 1230 */ 1231 break; 1232 } 1233 #else /* DP83820 */ 1234 /* 1235 * Load the DMA map. If this fails, the packet either 1236 * didn't fit in the alloted number of segments, or we 1237 * were short on resources. In this case, we'll copy 1238 * and try again. 1239 */ 1240 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1241 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1242 MGETHDR(m, M_DONTWAIT, MT_DATA); 1243 if (m == NULL) { 1244 printf("%s: unable to allocate Tx mbuf\n", 1245 sc->sc_dev.dv_xname); 1246 break; 1247 } 1248 if (m0->m_pkthdr.len > MHLEN) { 1249 MCLGET(m, M_DONTWAIT); 1250 if ((m->m_flags & M_EXT) == 0) { 1251 printf("%s: unable to allocate Tx " 1252 "cluster\n", sc->sc_dev.dv_xname); 1253 m_freem(m); 1254 break; 1255 } 1256 } 1257 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1258 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1259 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1260 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1261 if (error) { 1262 printf("%s: unable to load Tx buffer, " 1263 "error = %d\n", sc->sc_dev.dv_xname, error); 1264 break; 1265 } 1266 } 1267 #endif /* DP83820 */ 1268 1269 /* 1270 * Ensure we have enough descriptors free to describe 1271 * the packet. Note, we always reserve one descriptor 1272 * at the end of the ring as a termination point, to 1273 * prevent wrap-around. 1274 */ 1275 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1276 /* 1277 * Not enough free descriptors to transmit this 1278 * packet. We haven't committed anything yet, 1279 * so just unload the DMA map, put the packet 1280 * back on the queue, and punt. Notify the upper 1281 * layer that there are not more slots left. 1282 * 1283 * XXX We could allocate an mbuf and copy, but 1284 * XXX is it worth it? 1285 */ 1286 ifp->if_flags |= IFF_OACTIVE; 1287 bus_dmamap_unload(sc->sc_dmat, dmamap); 1288 #ifndef DP83820 1289 if (m != NULL) 1290 m_freem(m); 1291 #endif 1292 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1293 break; 1294 } 1295 1296 IFQ_DEQUEUE(&ifp->if_snd, m0); 1297 #ifndef DP83820 1298 if (m != NULL) { 1299 m_freem(m0); 1300 m0 = m; 1301 } 1302 #endif 1303 1304 /* 1305 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1306 */ 1307 1308 /* Sync the DMA map. */ 1309 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1310 BUS_DMASYNC_PREWRITE); 1311 1312 /* 1313 * Initialize the transmit descriptors. 1314 */ 1315 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1316 seg < dmamap->dm_nsegs; 1317 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1318 /* 1319 * If this is the first descriptor we're 1320 * enqueueing, don't set the OWN bit just 1321 * yet. That could cause a race condition. 1322 * We'll do it below. 1323 */ 1324 sc->sc_txdescs[nexttx].sipd_bufptr = 1325 htole32(dmamap->dm_segs[seg].ds_addr); 1326 sc->sc_txdescs[nexttx].sipd_cmdsts = 1327 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1328 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1329 #ifdef DP83820 1330 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1331 #endif /* DP83820 */ 1332 lasttx = nexttx; 1333 } 1334 1335 /* Clear the MORE bit on the last segment. */ 1336 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1337 1338 /* 1339 * If we're in the interrupt delay window, delay the 1340 * interrupt. 1341 */ 1342 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1343 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1344 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1345 htole32(CMDSTS_INTR); 1346 sc->sc_txwin = 0; 1347 } 1348 1349 #ifdef DP83820 1350 /* 1351 * If VLANs are enabled and the packet has a VLAN tag, set 1352 * up the descriptor to encapsulate the packet for us. 1353 * 1354 * This apparently has to be on the last descriptor of 1355 * the packet. 1356 */ 1357 if (sc->sc_ethercom.ec_nvlans != 0 && 1358 (mtag = m_tag_find(m0, PACKET_TAG_VLAN, NULL)) != NULL) { 1359 sc->sc_txdescs[lasttx].sipd_extsts |= 1360 htole32(EXTSTS_VPKT | 1361 (*(u_int *)(mtag + 1) & EXTSTS_VTCI)); 1362 } 1363 1364 /* 1365 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1366 * checksumming, set up the descriptor to do this work 1367 * for us. 1368 * 1369 * This apparently has to be on the first descriptor of 1370 * the packet. 1371 * 1372 * Byte-swap constants so the compiler can optimize. 1373 */ 1374 extsts = 0; 1375 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1376 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1377 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1378 extsts |= htole32(EXTSTS_IPPKT); 1379 } 1380 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1381 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1382 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1383 extsts |= htole32(EXTSTS_TCPPKT); 1384 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1385 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1386 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1387 extsts |= htole32(EXTSTS_UDPPKT); 1388 } 1389 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1390 #endif /* DP83820 */ 1391 1392 /* Sync the descriptors we're using. */ 1393 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1394 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1395 1396 /* 1397 * The entire packet is set up. Give the first descrptor 1398 * to the chip now. 1399 */ 1400 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1401 htole32(CMDSTS_OWN); 1402 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1403 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1404 1405 /* 1406 * Store a pointer to the packet so we can free it later, 1407 * and remember what txdirty will be once the packet is 1408 * done. 1409 */ 1410 txs->txs_mbuf = m0; 1411 txs->txs_firstdesc = sc->sc_txnext; 1412 txs->txs_lastdesc = lasttx; 1413 1414 /* Advance the tx pointer. */ 1415 sc->sc_txfree -= dmamap->dm_nsegs; 1416 sc->sc_txnext = nexttx; 1417 1418 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1419 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1420 1421 #if NBPFILTER > 0 1422 /* 1423 * Pass the packet to any BPF listeners. 1424 */ 1425 if (ifp->if_bpf) 1426 bpf_mtap(ifp->if_bpf, m0); 1427 #endif /* NBPFILTER > 0 */ 1428 } 1429 1430 if (txs == NULL || sc->sc_txfree == 0) { 1431 /* No more slots left; notify upper layer. */ 1432 ifp->if_flags |= IFF_OACTIVE; 1433 } 1434 1435 if (sc->sc_txfree != ofree) { 1436 /* 1437 * Start the transmit process. Note, the manual says 1438 * that if there are no pending transmissions in the 1439 * chip's internal queue (indicated by TXE being clear), 1440 * then the driver software must set the TXDP to the 1441 * first descriptor to be transmitted. However, if we 1442 * do this, it causes serious performance degredation on 1443 * the DP83820 under load, not setting TXDP doesn't seem 1444 * to adversely affect the SiS 900 or DP83815. 1445 * 1446 * Well, I guess it wouldn't be the first time a manual 1447 * has lied -- and they could be speaking of the NULL- 1448 * terminated descriptor list case, rather than OWN- 1449 * terminated rings. 1450 */ 1451 #if 0 1452 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1453 CR_TXE) == 0) { 1454 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1455 SIP_CDTXADDR(sc, firsttx)); 1456 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1457 } 1458 #else 1459 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1460 #endif 1461 1462 /* Set a watchdog timer in case the chip flakes out. */ 1463 #ifdef DP83820 1464 /* Gigabit autonegotiation takes 5 seconds. */ 1465 ifp->if_timer = 10; 1466 #else 1467 ifp->if_timer = 5; 1468 #endif 1469 } 1470 } 1471 1472 /* 1473 * sip_watchdog: [ifnet interface function] 1474 * 1475 * Watchdog timer handler. 1476 */ 1477 static void 1478 SIP_DECL(watchdog)(struct ifnet *ifp) 1479 { 1480 struct sip_softc *sc = ifp->if_softc; 1481 1482 /* 1483 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1484 * If we get a timeout, try and sweep up transmit descriptors. 1485 * If we manage to sweep them all up, ignore the lack of 1486 * interrupt. 1487 */ 1488 SIP_DECL(txintr)(sc); 1489 1490 if (sc->sc_txfree != SIP_NTXDESC) { 1491 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1492 ifp->if_oerrors++; 1493 1494 /* Reset the interface. */ 1495 (void) SIP_DECL(init)(ifp); 1496 } else if (ifp->if_flags & IFF_DEBUG) 1497 printf("%s: recovered from device timeout\n", 1498 sc->sc_dev.dv_xname); 1499 1500 /* Try to get more packets going. */ 1501 SIP_DECL(start)(ifp); 1502 } 1503 1504 /* 1505 * sip_ioctl: [ifnet interface function] 1506 * 1507 * Handle control requests from the operator. 1508 */ 1509 static int 1510 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1511 { 1512 struct sip_softc *sc = ifp->if_softc; 1513 struct ifreq *ifr = (struct ifreq *)data; 1514 int s, error; 1515 1516 s = splnet(); 1517 1518 switch (cmd) { 1519 case SIOCSIFMEDIA: 1520 /* Flow control requires full-duplex mode. */ 1521 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1522 (ifr->ifr_media & IFM_FDX) == 0) 1523 ifr->ifr_media &= ~IFM_ETH_FMASK; 1524 #ifdef DP83820 1525 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1526 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1527 /* We can do both TXPAUSE and RXPAUSE. */ 1528 ifr->ifr_media |= 1529 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1530 } 1531 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1532 } 1533 #else 1534 /* XXX */ 1535 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1536 ifr->ifr_media &= ~IFM_ETH_FMASK; 1537 1538 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1539 if (ifr->ifr_media & IFM_FLOW) { 1540 /* 1541 * Both TXPAUSE and RXPAUSE must be set. 1542 * (SiS900 and DP83815 don't have PAUSE_ASYM 1543 * feature.) 1544 * 1545 * XXX Can SiS900 and DP83815 send PAUSE? 1546 */ 1547 ifr->ifr_media |= 1548 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1549 } 1550 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1551 } 1552 #endif 1553 /* FALLTHROUGH */ 1554 case SIOCGIFMEDIA: 1555 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1556 break; 1557 case SIOCSIFFLAGS: 1558 /* If the interface is up and running, only modify the receive 1559 * filter when setting promiscuous or debug mode. Otherwise 1560 * fall through to ether_ioctl, which will reset the chip. 1561 */ 1562 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 1563 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 1564 == (IFF_UP|IFF_RUNNING)) 1565 && ((ifp->if_flags & (~RESETIGN)) 1566 == (sc->sc_if_flags & (~RESETIGN)))) { 1567 /* Set up the receive filter. */ 1568 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1569 break; 1570 #undef RESETIGN 1571 } 1572 /* FALLTHROUGH */ 1573 default: 1574 error = ether_ioctl(ifp, cmd, data); 1575 if (error == ENETRESET) { 1576 /* 1577 * Multicast list has changed; set the hardware filter 1578 * accordingly. 1579 */ 1580 if (ifp->if_flags & IFF_RUNNING) 1581 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1582 error = 0; 1583 } 1584 break; 1585 } 1586 1587 /* Try to get more packets going. */ 1588 SIP_DECL(start)(ifp); 1589 1590 sc->sc_if_flags = ifp->if_flags; 1591 splx(s); 1592 return (error); 1593 } 1594 1595 /* 1596 * sip_intr: 1597 * 1598 * Interrupt service routine. 1599 */ 1600 static int 1601 SIP_DECL(intr)(void *arg) 1602 { 1603 struct sip_softc *sc = arg; 1604 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1605 u_int32_t isr; 1606 int handled = 0; 1607 1608 /* Disable interrupts. */ 1609 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1610 1611 for (;;) { 1612 /* Reading clears interrupt. */ 1613 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1614 if ((isr & sc->sc_imr) == 0) 1615 break; 1616 1617 #if NRND > 0 1618 if (RND_ENABLED(&sc->rnd_source)) 1619 rnd_add_uint32(&sc->rnd_source, isr); 1620 #endif 1621 1622 handled = 1; 1623 1624 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1625 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1626 1627 /* Grab any new packets. */ 1628 SIP_DECL(rxintr)(sc); 1629 1630 if (isr & ISR_RXORN) { 1631 printf("%s: receive FIFO overrun\n", 1632 sc->sc_dev.dv_xname); 1633 1634 /* XXX adjust rx_drain_thresh? */ 1635 } 1636 1637 if (isr & ISR_RXIDLE) { 1638 printf("%s: receive ring overrun\n", 1639 sc->sc_dev.dv_xname); 1640 1641 /* Get the receive process going again. */ 1642 bus_space_write_4(sc->sc_st, sc->sc_sh, 1643 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1644 bus_space_write_4(sc->sc_st, sc->sc_sh, 1645 SIP_CR, CR_RXE); 1646 } 1647 } 1648 1649 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1650 #ifdef SIP_EVENT_COUNTERS 1651 if (isr & ISR_TXDESC) 1652 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1653 else if (isr & ISR_TXIDLE) 1654 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1655 #endif 1656 1657 /* Sweep up transmit descriptors. */ 1658 SIP_DECL(txintr)(sc); 1659 1660 if (isr & ISR_TXURN) { 1661 u_int32_t thresh; 1662 1663 printf("%s: transmit FIFO underrun", 1664 sc->sc_dev.dv_xname); 1665 1666 thresh = sc->sc_tx_drain_thresh + 1; 1667 if (thresh <= TXCFG_DRTH && 1668 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1669 (sc->sc_tx_fill_thresh * 32))) { 1670 printf("; increasing Tx drain " 1671 "threshold to %u bytes\n", 1672 thresh * 32); 1673 sc->sc_tx_drain_thresh = thresh; 1674 (void) SIP_DECL(init)(ifp); 1675 } else { 1676 (void) SIP_DECL(init)(ifp); 1677 printf("\n"); 1678 } 1679 } 1680 } 1681 1682 #if !defined(DP83820) 1683 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1684 if (isr & ISR_PAUSE_ST) { 1685 sc->sc_paused = 1; 1686 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1687 ifp->if_flags |= IFF_OACTIVE; 1688 } 1689 if (isr & ISR_PAUSE_END) { 1690 sc->sc_paused = 0; 1691 ifp->if_flags &= ~IFF_OACTIVE; 1692 } 1693 } 1694 #endif /* ! DP83820 */ 1695 1696 if (isr & ISR_HIBERR) { 1697 int want_init = 0; 1698 1699 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1700 1701 #define PRINTERR(bit, str) \ 1702 do { \ 1703 if ((isr & (bit)) != 0) { \ 1704 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1705 printf("%s: %s\n", \ 1706 sc->sc_dev.dv_xname, str); \ 1707 want_init = 1; \ 1708 } \ 1709 } while (/*CONSTCOND*/0) 1710 1711 PRINTERR(ISR_DPERR, "parity error"); 1712 PRINTERR(ISR_SSERR, "system error"); 1713 PRINTERR(ISR_RMABT, "master abort"); 1714 PRINTERR(ISR_RTABT, "target abort"); 1715 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1716 /* 1717 * Ignore: 1718 * Tx reset complete 1719 * Rx reset complete 1720 */ 1721 if (want_init) 1722 (void) SIP_DECL(init)(ifp); 1723 #undef PRINTERR 1724 } 1725 } 1726 1727 /* Re-enable interrupts. */ 1728 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1729 1730 /* Try to get more packets going. */ 1731 SIP_DECL(start)(ifp); 1732 1733 return (handled); 1734 } 1735 1736 /* 1737 * sip_txintr: 1738 * 1739 * Helper; handle transmit interrupts. 1740 */ 1741 static void 1742 SIP_DECL(txintr)(struct sip_softc *sc) 1743 { 1744 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1745 struct sip_txsoft *txs; 1746 u_int32_t cmdsts; 1747 1748 #ifndef DP83820 1749 if (sc->sc_paused == 0) 1750 #endif 1751 ifp->if_flags &= ~IFF_OACTIVE; 1752 1753 /* 1754 * Go through our Tx list and free mbufs for those 1755 * frames which have been transmitted. 1756 */ 1757 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1758 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1759 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1760 1761 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1762 if (cmdsts & CMDSTS_OWN) 1763 break; 1764 1765 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1766 1767 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1768 1769 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1770 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1771 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1772 m_freem(txs->txs_mbuf); 1773 txs->txs_mbuf = NULL; 1774 1775 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1776 1777 /* 1778 * Check for errors and collisions. 1779 */ 1780 if (cmdsts & 1781 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1782 ifp->if_oerrors++; 1783 if (cmdsts & CMDSTS_Tx_EC) 1784 ifp->if_collisions += 16; 1785 if (ifp->if_flags & IFF_DEBUG) { 1786 if (cmdsts & CMDSTS_Tx_ED) 1787 printf("%s: excessive deferral\n", 1788 sc->sc_dev.dv_xname); 1789 if (cmdsts & CMDSTS_Tx_EC) 1790 printf("%s: excessive collisions\n", 1791 sc->sc_dev.dv_xname); 1792 } 1793 } else { 1794 /* Packet was transmitted successfully. */ 1795 ifp->if_opackets++; 1796 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1797 } 1798 } 1799 1800 /* 1801 * If there are no more pending transmissions, cancel the watchdog 1802 * timer. 1803 */ 1804 if (txs == NULL) { 1805 ifp->if_timer = 0; 1806 sc->sc_txwin = 0; 1807 } 1808 } 1809 1810 #if defined(DP83820) 1811 /* 1812 * sip_rxintr: 1813 * 1814 * Helper; handle receive interrupts. 1815 */ 1816 static void 1817 SIP_DECL(rxintr)(struct sip_softc *sc) 1818 { 1819 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1820 struct sip_rxsoft *rxs; 1821 struct mbuf *m; 1822 u_int32_t cmdsts, extsts; 1823 int i, len; 1824 1825 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1826 rxs = &sc->sc_rxsoft[i]; 1827 1828 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1829 1830 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1831 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1832 len = CMDSTS_SIZE(cmdsts); 1833 1834 /* 1835 * NOTE: OWN is set if owned by _consumer_. We're the 1836 * consumer of the receive ring, so if the bit is clear, 1837 * we have processed all of the packets. 1838 */ 1839 if ((cmdsts & CMDSTS_OWN) == 0) { 1840 /* 1841 * We have processed all of the receive buffers. 1842 */ 1843 break; 1844 } 1845 1846 if (__predict_false(sc->sc_rxdiscard)) { 1847 SIP_INIT_RXDESC(sc, i); 1848 if ((cmdsts & CMDSTS_MORE) == 0) { 1849 /* Reset our state. */ 1850 sc->sc_rxdiscard = 0; 1851 } 1852 continue; 1853 } 1854 1855 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1856 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1857 1858 m = rxs->rxs_mbuf; 1859 1860 /* 1861 * Add a new receive buffer to the ring. 1862 */ 1863 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1864 /* 1865 * Failed, throw away what we've done so 1866 * far, and discard the rest of the packet. 1867 */ 1868 ifp->if_ierrors++; 1869 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1870 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1871 SIP_INIT_RXDESC(sc, i); 1872 if (cmdsts & CMDSTS_MORE) 1873 sc->sc_rxdiscard = 1; 1874 if (sc->sc_rxhead != NULL) 1875 m_freem(sc->sc_rxhead); 1876 SIP_RXCHAIN_RESET(sc); 1877 continue; 1878 } 1879 1880 SIP_RXCHAIN_LINK(sc, m); 1881 1882 m->m_len = len; 1883 1884 /* 1885 * If this is not the end of the packet, keep 1886 * looking. 1887 */ 1888 if (cmdsts & CMDSTS_MORE) { 1889 sc->sc_rxlen += len; 1890 continue; 1891 } 1892 1893 /* 1894 * Okay, we have the entire packet now. The chip includes 1895 * the FCS, so we need to trim it. 1896 */ 1897 m->m_len -= ETHER_CRC_LEN; 1898 1899 *sc->sc_rxtailp = NULL; 1900 m = sc->sc_rxhead; 1901 len = m->m_len + sc->sc_rxlen; 1902 1903 SIP_RXCHAIN_RESET(sc); 1904 1905 /* 1906 * If an error occurred, update stats and drop the packet. 1907 */ 1908 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1909 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1910 ifp->if_ierrors++; 1911 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1912 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1913 /* Receive overrun handled elsewhere. */ 1914 printf("%s: receive descriptor error\n", 1915 sc->sc_dev.dv_xname); 1916 } 1917 #define PRINTERR(bit, str) \ 1918 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1919 (cmdsts & (bit)) != 0) \ 1920 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1921 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1922 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1923 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1924 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1925 #undef PRINTERR 1926 m_freem(m); 1927 continue; 1928 } 1929 1930 /* 1931 * If the packet is small enough to fit in a 1932 * single header mbuf, allocate one and copy 1933 * the data into it. This greatly reduces 1934 * memory consumption when we receive lots 1935 * of small packets. 1936 */ 1937 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1938 struct mbuf *nm; 1939 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1940 if (nm == NULL) { 1941 ifp->if_ierrors++; 1942 m_freem(m); 1943 continue; 1944 } 1945 nm->m_data += 2; 1946 nm->m_pkthdr.len = nm->m_len = len; 1947 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1948 m_freem(m); 1949 m = nm; 1950 } 1951 #ifndef __NO_STRICT_ALIGNMENT 1952 else { 1953 /* 1954 * The DP83820's receive buffers must be 4-byte 1955 * aligned. But this means that the data after 1956 * the Ethernet header is misaligned. To compensate, 1957 * we have artificially shortened the buffer size 1958 * in the descriptor, and we do an overlapping copy 1959 * of the data two bytes further in (in the first 1960 * buffer of the chain only). 1961 */ 1962 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1963 m->m_len); 1964 m->m_data += 2; 1965 } 1966 #endif /* ! __NO_STRICT_ALIGNMENT */ 1967 1968 /* 1969 * If VLANs are enabled, VLAN packets have been unwrapped 1970 * for us. Associate the tag with the packet. 1971 */ 1972 if (sc->sc_ethercom.ec_nvlans != 0 && 1973 (extsts & EXTSTS_VPKT) != 0) { 1974 struct m_tag *vtag; 1975 1976 vtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 1977 M_NOWAIT); 1978 if (vtag == NULL) { 1979 ifp->if_ierrors++; 1980 printf("%s: unable to allocate VLAN tag\n", 1981 sc->sc_dev.dv_xname); 1982 m_freem(m); 1983 continue; 1984 } 1985 1986 *(u_int *)(vtag + 1) = ntohs(extsts & EXTSTS_VTCI); 1987 } 1988 1989 /* 1990 * Set the incoming checksum information for the 1991 * packet. 1992 */ 1993 if ((extsts & EXTSTS_IPPKT) != 0) { 1994 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1995 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1996 if (extsts & EXTSTS_Rx_IPERR) 1997 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1998 if (extsts & EXTSTS_TCPPKT) { 1999 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2000 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2001 if (extsts & EXTSTS_Rx_TCPERR) 2002 m->m_pkthdr.csum_flags |= 2003 M_CSUM_TCP_UDP_BAD; 2004 } else if (extsts & EXTSTS_UDPPKT) { 2005 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2006 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2007 if (extsts & EXTSTS_Rx_UDPERR) 2008 m->m_pkthdr.csum_flags |= 2009 M_CSUM_TCP_UDP_BAD; 2010 } 2011 } 2012 2013 ifp->if_ipackets++; 2014 m->m_pkthdr.rcvif = ifp; 2015 m->m_pkthdr.len = len; 2016 2017 #if NBPFILTER > 0 2018 /* 2019 * Pass this up to any BPF listeners, but only 2020 * pass if up the stack if it's for us. 2021 */ 2022 if (ifp->if_bpf) 2023 bpf_mtap(ifp->if_bpf, m); 2024 #endif /* NBPFILTER > 0 */ 2025 2026 /* Pass it on. */ 2027 (*ifp->if_input)(ifp, m); 2028 } 2029 2030 /* Update the receive pointer. */ 2031 sc->sc_rxptr = i; 2032 } 2033 #else /* ! DP83820 */ 2034 /* 2035 * sip_rxintr: 2036 * 2037 * Helper; handle receive interrupts. 2038 */ 2039 static void 2040 SIP_DECL(rxintr)(struct sip_softc *sc) 2041 { 2042 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2043 struct sip_rxsoft *rxs; 2044 struct mbuf *m; 2045 u_int32_t cmdsts; 2046 int i, len; 2047 2048 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 2049 rxs = &sc->sc_rxsoft[i]; 2050 2051 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2052 2053 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 2054 2055 /* 2056 * NOTE: OWN is set if owned by _consumer_. We're the 2057 * consumer of the receive ring, so if the bit is clear, 2058 * we have processed all of the packets. 2059 */ 2060 if ((cmdsts & CMDSTS_OWN) == 0) { 2061 /* 2062 * We have processed all of the receive buffers. 2063 */ 2064 break; 2065 } 2066 2067 /* 2068 * If any collisions were seen on the wire, count one. 2069 */ 2070 if (cmdsts & CMDSTS_Rx_COL) 2071 ifp->if_collisions++; 2072 2073 /* 2074 * If an error occurred, update stats, clear the status 2075 * word, and leave the packet buffer in place. It will 2076 * simply be reused the next time the ring comes around. 2077 */ 2078 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2079 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2080 ifp->if_ierrors++; 2081 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2082 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2083 /* Receive overrun handled elsewhere. */ 2084 printf("%s: receive descriptor error\n", 2085 sc->sc_dev.dv_xname); 2086 } 2087 #define PRINTERR(bit, str) \ 2088 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2089 (cmdsts & (bit)) != 0) \ 2090 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 2091 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2092 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2093 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2094 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2095 #undef PRINTERR 2096 SIP_INIT_RXDESC(sc, i); 2097 continue; 2098 } 2099 2100 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2101 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2102 2103 /* 2104 * No errors; receive the packet. Note, the SiS 900 2105 * includes the CRC with every packet. 2106 */ 2107 len = CMDSTS_SIZE(cmdsts) - ETHER_CRC_LEN; 2108 2109 #ifdef __NO_STRICT_ALIGNMENT 2110 /* 2111 * If the packet is small enough to fit in a 2112 * single header mbuf, allocate one and copy 2113 * the data into it. This greatly reduces 2114 * memory consumption when we receive lots 2115 * of small packets. 2116 * 2117 * Otherwise, we add a new buffer to the receive 2118 * chain. If this fails, we drop the packet and 2119 * recycle the old buffer. 2120 */ 2121 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 2122 MGETHDR(m, M_DONTWAIT, MT_DATA); 2123 if (m == NULL) 2124 goto dropit; 2125 memcpy(mtod(m, caddr_t), 2126 mtod(rxs->rxs_mbuf, caddr_t), len); 2127 SIP_INIT_RXDESC(sc, i); 2128 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2129 rxs->rxs_dmamap->dm_mapsize, 2130 BUS_DMASYNC_PREREAD); 2131 } else { 2132 m = rxs->rxs_mbuf; 2133 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 2134 dropit: 2135 ifp->if_ierrors++; 2136 SIP_INIT_RXDESC(sc, i); 2137 bus_dmamap_sync(sc->sc_dmat, 2138 rxs->rxs_dmamap, 0, 2139 rxs->rxs_dmamap->dm_mapsize, 2140 BUS_DMASYNC_PREREAD); 2141 continue; 2142 } 2143 } 2144 #else 2145 /* 2146 * The SiS 900's receive buffers must be 4-byte aligned. 2147 * But this means that the data after the Ethernet header 2148 * is misaligned. We must allocate a new buffer and 2149 * copy the data, shifted forward 2 bytes. 2150 */ 2151 MGETHDR(m, M_DONTWAIT, MT_DATA); 2152 if (m == NULL) { 2153 dropit: 2154 ifp->if_ierrors++; 2155 SIP_INIT_RXDESC(sc, i); 2156 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2157 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2158 continue; 2159 } 2160 if (len > (MHLEN - 2)) { 2161 MCLGET(m, M_DONTWAIT); 2162 if ((m->m_flags & M_EXT) == 0) { 2163 m_freem(m); 2164 goto dropit; 2165 } 2166 } 2167 m->m_data += 2; 2168 2169 /* 2170 * Note that we use clusters for incoming frames, so the 2171 * buffer is virtually contiguous. 2172 */ 2173 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 2174 2175 /* Allow the receive descriptor to continue using its mbuf. */ 2176 SIP_INIT_RXDESC(sc, i); 2177 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2178 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2179 #endif /* __NO_STRICT_ALIGNMENT */ 2180 2181 ifp->if_ipackets++; 2182 m->m_pkthdr.rcvif = ifp; 2183 m->m_pkthdr.len = m->m_len = len; 2184 2185 #if NBPFILTER > 0 2186 /* 2187 * Pass this up to any BPF listeners, but only 2188 * pass if up the stack if it's for us. 2189 */ 2190 if (ifp->if_bpf) 2191 bpf_mtap(ifp->if_bpf, m); 2192 #endif /* NBPFILTER > 0 */ 2193 2194 /* Pass it on. */ 2195 (*ifp->if_input)(ifp, m); 2196 } 2197 2198 /* Update the receive pointer. */ 2199 sc->sc_rxptr = i; 2200 } 2201 #endif /* DP83820 */ 2202 2203 /* 2204 * sip_tick: 2205 * 2206 * One second timer, used to tick the MII. 2207 */ 2208 static void 2209 SIP_DECL(tick)(void *arg) 2210 { 2211 struct sip_softc *sc = arg; 2212 int s; 2213 2214 s = splnet(); 2215 #ifdef DP83820 2216 #ifdef SIP_EVENT_COUNTERS 2217 /* Read PAUSE related counts from MIB registers. */ 2218 sc->sc_ev_rxpause.ev_count += 2219 bus_space_read_4(sc->sc_st, sc->sc_sh, 2220 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2221 sc->sc_ev_txpause.ev_count += 2222 bus_space_read_4(sc->sc_st, sc->sc_sh, 2223 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2224 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2225 #endif /* SIP_EVENT_COUNTERS */ 2226 #endif /* DP83820 */ 2227 mii_tick(&sc->sc_mii); 2228 splx(s); 2229 2230 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2231 } 2232 2233 /* 2234 * sip_reset: 2235 * 2236 * Perform a soft reset on the SiS 900. 2237 */ 2238 static void 2239 SIP_DECL(reset)(struct sip_softc *sc) 2240 { 2241 bus_space_tag_t st = sc->sc_st; 2242 bus_space_handle_t sh = sc->sc_sh; 2243 int i; 2244 2245 bus_space_write_4(st, sh, SIP_IER, 0); 2246 bus_space_write_4(st, sh, SIP_IMR, 0); 2247 bus_space_write_4(st, sh, SIP_RFCR, 0); 2248 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2249 2250 for (i = 0; i < SIP_TIMEOUT; i++) { 2251 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2252 break; 2253 delay(2); 2254 } 2255 2256 if (i == SIP_TIMEOUT) 2257 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2258 2259 delay(1000); 2260 2261 #ifdef DP83820 2262 /* 2263 * Set the general purpose I/O bits. Do it here in case we 2264 * need to have GPIO set up to talk to the media interface. 2265 */ 2266 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2267 delay(1000); 2268 #endif /* DP83820 */ 2269 } 2270 2271 /* 2272 * sip_init: [ ifnet interface function ] 2273 * 2274 * Initialize the interface. Must be called at splnet(). 2275 */ 2276 static int 2277 SIP_DECL(init)(struct ifnet *ifp) 2278 { 2279 struct sip_softc *sc = ifp->if_softc; 2280 bus_space_tag_t st = sc->sc_st; 2281 bus_space_handle_t sh = sc->sc_sh; 2282 struct sip_txsoft *txs; 2283 struct sip_rxsoft *rxs; 2284 struct sip_desc *sipd; 2285 #if defined(DP83820) 2286 u_int32_t reg; 2287 #endif 2288 int i, error = 0; 2289 2290 /* 2291 * Cancel any pending I/O. 2292 */ 2293 SIP_DECL(stop)(ifp, 0); 2294 2295 /* 2296 * Reset the chip to a known state. 2297 */ 2298 SIP_DECL(reset)(sc); 2299 2300 #if !defined(DP83820) 2301 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2302 /* 2303 * DP83815 manual, page 78: 2304 * 4.4 Recommended Registers Configuration 2305 * For optimum performance of the DP83815, version noted 2306 * as DP83815CVNG (SRR = 203h), the listed register 2307 * modifications must be followed in sequence... 2308 * 2309 * It's not clear if this should be 302h or 203h because that 2310 * chip name is listed as SRR 302h in the description of the 2311 * SRR register. However, my revision 302h DP83815 on the 2312 * Netgear FA311 purchased in 02/2001 needs these settings 2313 * to avoid tons of errors in AcceptPerfectMatch (non- 2314 * IFF_PROMISC) mode. I do not know if other revisions need 2315 * this set or not. [briggs -- 09 March 2001] 2316 * 2317 * Note that only the low-order 12 bits of 0xe4 are documented 2318 * and that this sets reserved bits in that register. 2319 */ 2320 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2321 2322 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2323 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2324 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2325 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2326 2327 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2328 } 2329 #endif /* ! DP83820 */ 2330 2331 /* 2332 * Initialize the transmit descriptor ring. 2333 */ 2334 for (i = 0; i < SIP_NTXDESC; i++) { 2335 sipd = &sc->sc_txdescs[i]; 2336 memset(sipd, 0, sizeof(struct sip_desc)); 2337 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2338 } 2339 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2340 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2341 sc->sc_txfree = SIP_NTXDESC; 2342 sc->sc_txnext = 0; 2343 sc->sc_txwin = 0; 2344 2345 /* 2346 * Initialize the transmit job descriptors. 2347 */ 2348 SIMPLEQ_INIT(&sc->sc_txfreeq); 2349 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2350 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2351 txs = &sc->sc_txsoft[i]; 2352 txs->txs_mbuf = NULL; 2353 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2354 } 2355 2356 /* 2357 * Initialize the receive descriptor and receive job 2358 * descriptor rings. 2359 */ 2360 for (i = 0; i < SIP_NRXDESC; i++) { 2361 rxs = &sc->sc_rxsoft[i]; 2362 if (rxs->rxs_mbuf == NULL) { 2363 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2364 printf("%s: unable to allocate or map rx " 2365 "buffer %d, error = %d\n", 2366 sc->sc_dev.dv_xname, i, error); 2367 /* 2368 * XXX Should attempt to run with fewer receive 2369 * XXX buffers instead of just failing. 2370 */ 2371 SIP_DECL(rxdrain)(sc); 2372 goto out; 2373 } 2374 } else 2375 SIP_INIT_RXDESC(sc, i); 2376 } 2377 sc->sc_rxptr = 0; 2378 #ifdef DP83820 2379 sc->sc_rxdiscard = 0; 2380 SIP_RXCHAIN_RESET(sc); 2381 #endif /* DP83820 */ 2382 2383 /* 2384 * Set the configuration register; it's already initialized 2385 * in sip_attach(). 2386 */ 2387 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2388 2389 /* 2390 * Initialize the prototype TXCFG register. 2391 */ 2392 #if defined(DP83820) 2393 sc->sc_txcfg = TXCFG_MXDMA_512; 2394 sc->sc_rxcfg = RXCFG_MXDMA_512; 2395 #else 2396 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2397 SIP_SIS900_REV(sc, SIS_REV_960) || 2398 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2399 (sc->sc_cfg & CFG_EDBMASTEN)) { 2400 sc->sc_txcfg = TXCFG_MXDMA_64; 2401 sc->sc_rxcfg = RXCFG_MXDMA_64; 2402 } else { 2403 sc->sc_txcfg = TXCFG_MXDMA_512; 2404 sc->sc_rxcfg = RXCFG_MXDMA_512; 2405 } 2406 #endif /* DP83820 */ 2407 2408 sc->sc_txcfg |= TXCFG_ATP | 2409 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2410 sc->sc_tx_drain_thresh; 2411 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2412 2413 /* 2414 * Initialize the receive drain threshold if we have never 2415 * done so. 2416 */ 2417 if (sc->sc_rx_drain_thresh == 0) { 2418 /* 2419 * XXX This value should be tuned. This is set to the 2420 * maximum of 248 bytes, and we may be able to improve 2421 * performance by decreasing it (although we should never 2422 * set this value lower than 2; 14 bytes are required to 2423 * filter the packet). 2424 */ 2425 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2426 } 2427 2428 /* 2429 * Initialize the prototype RXCFG register. 2430 */ 2431 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2432 #ifdef DP83820 2433 /* 2434 * Accept long packets (including FCS) so we can handle 2435 * 802.1q-tagged frames and jumbo frames properly. 2436 */ 2437 if (ifp->if_mtu > ETHERMTU || 2438 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2439 sc->sc_rxcfg |= RXCFG_ALP; 2440 2441 /* 2442 * Checksum offloading is disabled if the user selects an MTU 2443 * larger than 8109. (FreeBSD says 8152, but there is emperical 2444 * evidence that >8109 does not work on some boards, such as the 2445 * Planex GN-1000TE). 2446 */ 2447 if (ifp->if_mtu > 8109 && 2448 (ifp->if_capenable & 2449 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4))) { 2450 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2451 "disabled.\n", sc->sc_dev.dv_xname); 2452 ifp->if_capenable &= ~(IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4| 2453 IFCAP_CSUM_UDPv4); 2454 ifp->if_csum_flags_tx = 0; 2455 ifp->if_csum_flags_rx = 0; 2456 } 2457 #else 2458 /* 2459 * Accept packets >1518 bytes (including FCS) so we can handle 2460 * 802.1q-tagged frames properly. 2461 */ 2462 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2463 sc->sc_rxcfg |= RXCFG_ALP; 2464 #endif 2465 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2466 2467 #ifdef DP83820 2468 /* 2469 * Initialize the VLAN/IP receive control register. 2470 * We enable checksum computation on all incoming 2471 * packets, and do not reject packets w/ bad checksums. 2472 */ 2473 reg = 0; 2474 if (ifp->if_capenable & 2475 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2476 reg |= VRCR_IPEN; 2477 if (sc->sc_ethercom.ec_nvlans != 0) 2478 reg |= VRCR_VTDEN|VRCR_VTREN; 2479 bus_space_write_4(st, sh, SIP_VRCR, reg); 2480 2481 /* 2482 * Initialize the VLAN/IP transmit control register. 2483 * We enable outgoing checksum computation on a 2484 * per-packet basis. 2485 */ 2486 reg = 0; 2487 if (ifp->if_capenable & 2488 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2489 reg |= VTCR_PPCHK; 2490 if (sc->sc_ethercom.ec_nvlans != 0) 2491 reg |= VTCR_VPPTI; 2492 bus_space_write_4(st, sh, SIP_VTCR, reg); 2493 2494 /* 2495 * If we're using VLANs, initialize the VLAN data register. 2496 * To understand why we bswap the VLAN Ethertype, see section 2497 * 4.2.36 of the DP83820 manual. 2498 */ 2499 if (sc->sc_ethercom.ec_nvlans != 0) 2500 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2501 #endif /* DP83820 */ 2502 2503 /* 2504 * Give the transmit and receive rings to the chip. 2505 */ 2506 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2507 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2508 2509 /* 2510 * Initialize the interrupt mask. 2511 */ 2512 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2513 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2514 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2515 2516 /* Set up the receive filter. */ 2517 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2518 2519 #ifdef DP83820 2520 /* 2521 * Tune sc_rx_flow_thresh. 2522 * XXX "More than 8KB" is too short for jumbo frames. 2523 * XXX TODO: Threshold value should be user-settable. 2524 */ 2525 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2526 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2527 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2528 #endif 2529 2530 /* 2531 * Set the current media. Do this after initializing the prototype 2532 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2533 * control. 2534 */ 2535 mii_mediachg(&sc->sc_mii); 2536 2537 #ifdef DP83820 2538 /* 2539 * Set the interrupt hold-off timer to 100us. 2540 */ 2541 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2542 #endif 2543 2544 /* 2545 * Enable interrupts. 2546 */ 2547 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2548 2549 /* 2550 * Start the transmit and receive processes. 2551 */ 2552 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2553 2554 /* 2555 * Start the one second MII clock. 2556 */ 2557 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2558 2559 /* 2560 * ...all done! 2561 */ 2562 ifp->if_flags |= IFF_RUNNING; 2563 ifp->if_flags &= ~IFF_OACTIVE; 2564 sc->sc_if_flags = ifp->if_flags; 2565 2566 out: 2567 if (error) 2568 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2569 return (error); 2570 } 2571 2572 /* 2573 * sip_drain: 2574 * 2575 * Drain the receive queue. 2576 */ 2577 static void 2578 SIP_DECL(rxdrain)(struct sip_softc *sc) 2579 { 2580 struct sip_rxsoft *rxs; 2581 int i; 2582 2583 for (i = 0; i < SIP_NRXDESC; i++) { 2584 rxs = &sc->sc_rxsoft[i]; 2585 if (rxs->rxs_mbuf != NULL) { 2586 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2587 m_freem(rxs->rxs_mbuf); 2588 rxs->rxs_mbuf = NULL; 2589 } 2590 } 2591 } 2592 2593 /* 2594 * sip_stop: [ ifnet interface function ] 2595 * 2596 * Stop transmission on the interface. 2597 */ 2598 static void 2599 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2600 { 2601 struct sip_softc *sc = ifp->if_softc; 2602 bus_space_tag_t st = sc->sc_st; 2603 bus_space_handle_t sh = sc->sc_sh; 2604 struct sip_txsoft *txs; 2605 u_int32_t cmdsts = 0; /* DEBUG */ 2606 2607 /* 2608 * Stop the one second clock. 2609 */ 2610 callout_stop(&sc->sc_tick_ch); 2611 2612 /* Down the MII. */ 2613 mii_down(&sc->sc_mii); 2614 2615 /* 2616 * Disable interrupts. 2617 */ 2618 bus_space_write_4(st, sh, SIP_IER, 0); 2619 2620 /* 2621 * Stop receiver and transmitter. 2622 */ 2623 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2624 2625 /* 2626 * Release any queued transmit buffers. 2627 */ 2628 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2629 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2630 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2631 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2632 CMDSTS_INTR) == 0) 2633 printf("%s: sip_stop: last descriptor does not " 2634 "have INTR bit set\n", sc->sc_dev.dv_xname); 2635 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2636 #ifdef DIAGNOSTIC 2637 if (txs->txs_mbuf == NULL) { 2638 printf("%s: dirty txsoft with no mbuf chain\n", 2639 sc->sc_dev.dv_xname); 2640 panic("sip_stop"); 2641 } 2642 #endif 2643 cmdsts |= /* DEBUG */ 2644 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2645 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2646 m_freem(txs->txs_mbuf); 2647 txs->txs_mbuf = NULL; 2648 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2649 } 2650 2651 if (disable) 2652 SIP_DECL(rxdrain)(sc); 2653 2654 /* 2655 * Mark the interface down and cancel the watchdog timer. 2656 */ 2657 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2658 ifp->if_timer = 0; 2659 2660 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2661 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2662 printf("%s: sip_stop: no INTR bits set in dirty tx " 2663 "descriptors\n", sc->sc_dev.dv_xname); 2664 } 2665 2666 /* 2667 * sip_read_eeprom: 2668 * 2669 * Read data from the serial EEPROM. 2670 */ 2671 static void 2672 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2673 u_int16_t *data) 2674 { 2675 bus_space_tag_t st = sc->sc_st; 2676 bus_space_handle_t sh = sc->sc_sh; 2677 u_int16_t reg; 2678 int i, x; 2679 2680 for (i = 0; i < wordcnt; i++) { 2681 /* Send CHIP SELECT. */ 2682 reg = EROMAR_EECS; 2683 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2684 2685 /* Shift in the READ opcode. */ 2686 for (x = 3; x > 0; x--) { 2687 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2688 reg |= EROMAR_EEDI; 2689 else 2690 reg &= ~EROMAR_EEDI; 2691 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2692 bus_space_write_4(st, sh, SIP_EROMAR, 2693 reg | EROMAR_EESK); 2694 delay(4); 2695 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2696 delay(4); 2697 } 2698 2699 /* Shift in address. */ 2700 for (x = 6; x > 0; x--) { 2701 if ((word + i) & (1 << (x - 1))) 2702 reg |= EROMAR_EEDI; 2703 else 2704 reg &= ~EROMAR_EEDI; 2705 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2706 bus_space_write_4(st, sh, SIP_EROMAR, 2707 reg | EROMAR_EESK); 2708 delay(4); 2709 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2710 delay(4); 2711 } 2712 2713 /* Shift out data. */ 2714 reg = EROMAR_EECS; 2715 data[i] = 0; 2716 for (x = 16; x > 0; x--) { 2717 bus_space_write_4(st, sh, SIP_EROMAR, 2718 reg | EROMAR_EESK); 2719 delay(4); 2720 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2721 data[i] |= (1 << (x - 1)); 2722 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2723 delay(4); 2724 } 2725 2726 /* Clear CHIP SELECT. */ 2727 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2728 delay(4); 2729 } 2730 } 2731 2732 /* 2733 * sip_add_rxbuf: 2734 * 2735 * Add a receive buffer to the indicated descriptor. 2736 */ 2737 static int 2738 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2739 { 2740 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2741 struct mbuf *m; 2742 int error; 2743 2744 MGETHDR(m, M_DONTWAIT, MT_DATA); 2745 if (m == NULL) 2746 return (ENOBUFS); 2747 2748 MCLGET(m, M_DONTWAIT); 2749 if ((m->m_flags & M_EXT) == 0) { 2750 m_freem(m); 2751 return (ENOBUFS); 2752 } 2753 2754 #if defined(DP83820) 2755 m->m_len = SIP_RXBUF_LEN; 2756 #endif /* DP83820 */ 2757 2758 if (rxs->rxs_mbuf != NULL) 2759 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2760 2761 rxs->rxs_mbuf = m; 2762 2763 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2764 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2765 BUS_DMA_READ|BUS_DMA_NOWAIT); 2766 if (error) { 2767 printf("%s: can't load rx DMA map %d, error = %d\n", 2768 sc->sc_dev.dv_xname, idx, error); 2769 panic("sip_add_rxbuf"); /* XXX */ 2770 } 2771 2772 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2773 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2774 2775 SIP_INIT_RXDESC(sc, idx); 2776 2777 return (0); 2778 } 2779 2780 #if !defined(DP83820) 2781 /* 2782 * sip_sis900_set_filter: 2783 * 2784 * Set up the receive filter. 2785 */ 2786 static void 2787 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2788 { 2789 bus_space_tag_t st = sc->sc_st; 2790 bus_space_handle_t sh = sc->sc_sh; 2791 struct ethercom *ec = &sc->sc_ethercom; 2792 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2793 struct ether_multi *enm; 2794 u_int8_t *cp; 2795 struct ether_multistep step; 2796 u_int32_t crc, mchash[16]; 2797 2798 /* 2799 * Initialize the prototype RFCR. 2800 */ 2801 sc->sc_rfcr = RFCR_RFEN; 2802 if (ifp->if_flags & IFF_BROADCAST) 2803 sc->sc_rfcr |= RFCR_AAB; 2804 if (ifp->if_flags & IFF_PROMISC) { 2805 sc->sc_rfcr |= RFCR_AAP; 2806 goto allmulti; 2807 } 2808 2809 /* 2810 * Set up the multicast address filter by passing all multicast 2811 * addresses through a CRC generator, and then using the high-order 2812 * 6 bits as an index into the 128 bit multicast hash table (only 2813 * the lower 16 bits of each 32 bit multicast hash register are 2814 * valid). The high order bits select the register, while the 2815 * rest of the bits select the bit within the register. 2816 */ 2817 2818 memset(mchash, 0, sizeof(mchash)); 2819 2820 /* 2821 * SiS900 (at least SiS963) requires us to register the address of 2822 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 2823 */ 2824 crc = 0x0ed423f9; 2825 2826 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2827 SIP_SIS900_REV(sc, SIS_REV_960) || 2828 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2829 /* Just want the 8 most significant bits. */ 2830 crc >>= 24; 2831 } else { 2832 /* Just want the 7 most significant bits. */ 2833 crc >>= 25; 2834 } 2835 2836 /* Set the corresponding bit in the hash table. */ 2837 mchash[crc >> 4] |= 1 << (crc & 0xf); 2838 2839 ETHER_FIRST_MULTI(step, ec, enm); 2840 while (enm != NULL) { 2841 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2842 /* 2843 * We must listen to a range of multicast addresses. 2844 * For now, just accept all multicasts, rather than 2845 * trying to set only those filter bits needed to match 2846 * the range. (At this time, the only use of address 2847 * ranges is for IP multicast routing, for which the 2848 * range is big enough to require all bits set.) 2849 */ 2850 goto allmulti; 2851 } 2852 2853 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2854 2855 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2856 SIP_SIS900_REV(sc, SIS_REV_960) || 2857 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2858 /* Just want the 8 most significant bits. */ 2859 crc >>= 24; 2860 } else { 2861 /* Just want the 7 most significant bits. */ 2862 crc >>= 25; 2863 } 2864 2865 /* Set the corresponding bit in the hash table. */ 2866 mchash[crc >> 4] |= 1 << (crc & 0xf); 2867 2868 ETHER_NEXT_MULTI(step, enm); 2869 } 2870 2871 ifp->if_flags &= ~IFF_ALLMULTI; 2872 goto setit; 2873 2874 allmulti: 2875 ifp->if_flags |= IFF_ALLMULTI; 2876 sc->sc_rfcr |= RFCR_AAM; 2877 2878 setit: 2879 #define FILTER_EMIT(addr, data) \ 2880 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2881 delay(1); \ 2882 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2883 delay(1) 2884 2885 /* 2886 * Disable receive filter, and program the node address. 2887 */ 2888 cp = LLADDR(ifp->if_sadl); 2889 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2890 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2891 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2892 2893 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2894 /* 2895 * Program the multicast hash table. 2896 */ 2897 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2898 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2899 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2900 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2901 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2902 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2903 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2904 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2905 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2906 SIP_SIS900_REV(sc, SIS_REV_960) || 2907 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2908 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2909 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2910 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2911 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2912 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2913 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2914 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2915 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2916 } 2917 } 2918 #undef FILTER_EMIT 2919 2920 /* 2921 * Re-enable the receiver filter. 2922 */ 2923 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2924 } 2925 #endif /* ! DP83820 */ 2926 2927 /* 2928 * sip_dp83815_set_filter: 2929 * 2930 * Set up the receive filter. 2931 */ 2932 static void 2933 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2934 { 2935 bus_space_tag_t st = sc->sc_st; 2936 bus_space_handle_t sh = sc->sc_sh; 2937 struct ethercom *ec = &sc->sc_ethercom; 2938 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2939 struct ether_multi *enm; 2940 u_int8_t *cp; 2941 struct ether_multistep step; 2942 u_int32_t crc, hash, slot, bit; 2943 #ifdef DP83820 2944 #define MCHASH_NWORDS 128 2945 #else 2946 #define MCHASH_NWORDS 32 2947 #endif /* DP83820 */ 2948 u_int16_t mchash[MCHASH_NWORDS]; 2949 int i; 2950 2951 /* 2952 * Initialize the prototype RFCR. 2953 * Enable the receive filter, and accept on 2954 * Perfect (destination address) Match 2955 * If IFF_BROADCAST, also accept all broadcast packets. 2956 * If IFF_PROMISC, accept all unicast packets (and later, set 2957 * IFF_ALLMULTI and accept all multicast, too). 2958 */ 2959 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2960 if (ifp->if_flags & IFF_BROADCAST) 2961 sc->sc_rfcr |= RFCR_AAB; 2962 if (ifp->if_flags & IFF_PROMISC) { 2963 sc->sc_rfcr |= RFCR_AAP; 2964 goto allmulti; 2965 } 2966 2967 #ifdef DP83820 2968 /* 2969 * Set up the DP83820 multicast address filter by passing all multicast 2970 * addresses through a CRC generator, and then using the high-order 2971 * 11 bits as an index into the 2048 bit multicast hash table. The 2972 * high-order 7 bits select the slot, while the low-order 4 bits 2973 * select the bit within the slot. Note that only the low 16-bits 2974 * of each filter word are used, and there are 128 filter words. 2975 */ 2976 #else 2977 /* 2978 * Set up the DP83815 multicast address filter by passing all multicast 2979 * addresses through a CRC generator, and then using the high-order 2980 * 9 bits as an index into the 512 bit multicast hash table. The 2981 * high-order 5 bits select the slot, while the low-order 4 bits 2982 * select the bit within the slot. Note that only the low 16-bits 2983 * of each filter word are used, and there are 32 filter words. 2984 */ 2985 #endif /* DP83820 */ 2986 2987 memset(mchash, 0, sizeof(mchash)); 2988 2989 ifp->if_flags &= ~IFF_ALLMULTI; 2990 ETHER_FIRST_MULTI(step, ec, enm); 2991 if (enm == NULL) 2992 goto setit; 2993 while (enm != NULL) { 2994 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2995 /* 2996 * We must listen to a range of multicast addresses. 2997 * For now, just accept all multicasts, rather than 2998 * trying to set only those filter bits needed to match 2999 * the range. (At this time, the only use of address 3000 * ranges is for IP multicast routing, for which the 3001 * range is big enough to require all bits set.) 3002 */ 3003 goto allmulti; 3004 } 3005 3006 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3007 3008 #ifdef DP83820 3009 /* Just want the 11 most significant bits. */ 3010 hash = crc >> 21; 3011 #else 3012 /* Just want the 9 most significant bits. */ 3013 hash = crc >> 23; 3014 #endif /* DP83820 */ 3015 3016 slot = hash >> 4; 3017 bit = hash & 0xf; 3018 3019 /* Set the corresponding bit in the hash table. */ 3020 mchash[slot] |= 1 << bit; 3021 3022 ETHER_NEXT_MULTI(step, enm); 3023 } 3024 sc->sc_rfcr |= RFCR_MHEN; 3025 goto setit; 3026 3027 allmulti: 3028 ifp->if_flags |= IFF_ALLMULTI; 3029 sc->sc_rfcr |= RFCR_AAM; 3030 3031 setit: 3032 #define FILTER_EMIT(addr, data) \ 3033 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3034 delay(1); \ 3035 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3036 delay(1) 3037 3038 /* 3039 * Disable receive filter, and program the node address. 3040 */ 3041 cp = LLADDR(ifp->if_sadl); 3042 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3043 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3044 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3045 3046 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3047 /* 3048 * Program the multicast hash table. 3049 */ 3050 for (i = 0; i < MCHASH_NWORDS; i++) { 3051 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 3052 mchash[i]); 3053 } 3054 } 3055 #undef FILTER_EMIT 3056 #undef MCHASH_NWORDS 3057 3058 /* 3059 * Re-enable the receiver filter. 3060 */ 3061 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3062 } 3063 3064 #if defined(DP83820) 3065 /* 3066 * sip_dp83820_mii_readreg: [mii interface function] 3067 * 3068 * Read a PHY register on the MII of the DP83820. 3069 */ 3070 static int 3071 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 3072 { 3073 struct sip_softc *sc = (void *) self; 3074 3075 if (sc->sc_cfg & CFG_TBI_EN) { 3076 bus_addr_t tbireg; 3077 int rv; 3078 3079 if (phy != 0) 3080 return (0); 3081 3082 switch (reg) { 3083 case MII_BMCR: tbireg = SIP_TBICR; break; 3084 case MII_BMSR: tbireg = SIP_TBISR; break; 3085 case MII_ANAR: tbireg = SIP_TANAR; break; 3086 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3087 case MII_ANER: tbireg = SIP_TANER; break; 3088 case MII_EXTSR: 3089 /* 3090 * Don't even bother reading the TESR register. 3091 * The manual documents that the device has 3092 * 1000baseX full/half capability, but the 3093 * register itself seems read back 0 on some 3094 * boards. Just hard-code the result. 3095 */ 3096 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3097 3098 default: 3099 return (0); 3100 } 3101 3102 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3103 if (tbireg == SIP_TBISR) { 3104 /* LINK and ACOMP are switched! */ 3105 int val = rv; 3106 3107 rv = 0; 3108 if (val & TBISR_MR_LINK_STATUS) 3109 rv |= BMSR_LINK; 3110 if (val & TBISR_MR_AN_COMPLETE) 3111 rv |= BMSR_ACOMP; 3112 3113 /* 3114 * The manual claims this register reads back 0 3115 * on hard and soft reset. But we want to let 3116 * the gentbi driver know that we support auto- 3117 * negotiation, so hard-code this bit in the 3118 * result. 3119 */ 3120 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3121 } 3122 3123 return (rv); 3124 } 3125 3126 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3127 phy, reg)); 3128 } 3129 3130 /* 3131 * sip_dp83820_mii_writereg: [mii interface function] 3132 * 3133 * Write a PHY register on the MII of the DP83820. 3134 */ 3135 static void 3136 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 3137 { 3138 struct sip_softc *sc = (void *) self; 3139 3140 if (sc->sc_cfg & CFG_TBI_EN) { 3141 bus_addr_t tbireg; 3142 3143 if (phy != 0) 3144 return; 3145 3146 switch (reg) { 3147 case MII_BMCR: tbireg = SIP_TBICR; break; 3148 case MII_ANAR: tbireg = SIP_TANAR; break; 3149 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3150 default: 3151 return; 3152 } 3153 3154 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3155 return; 3156 } 3157 3158 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3159 phy, reg, val); 3160 } 3161 3162 /* 3163 * sip_dp83820_mii_statchg: [mii interface function] 3164 * 3165 * Callback from MII layer when media changes. 3166 */ 3167 static void 3168 SIP_DECL(dp83820_mii_statchg)(struct device *self) 3169 { 3170 struct sip_softc *sc = (struct sip_softc *) self; 3171 struct mii_data *mii = &sc->sc_mii; 3172 u_int32_t cfg, pcr; 3173 3174 /* 3175 * Get flow control negotiation result. 3176 */ 3177 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3178 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3179 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3180 mii->mii_media_active &= ~IFM_ETH_FMASK; 3181 } 3182 3183 /* 3184 * Update TXCFG for full-duplex operation. 3185 */ 3186 if ((mii->mii_media_active & IFM_FDX) != 0) 3187 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3188 else 3189 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3190 3191 /* 3192 * Update RXCFG for full-duplex or loopback. 3193 */ 3194 if ((mii->mii_media_active & IFM_FDX) != 0 || 3195 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3196 sc->sc_rxcfg |= RXCFG_ATX; 3197 else 3198 sc->sc_rxcfg &= ~RXCFG_ATX; 3199 3200 /* 3201 * Update CFG for MII/GMII. 3202 */ 3203 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3204 cfg = sc->sc_cfg | CFG_MODE_1000; 3205 else 3206 cfg = sc->sc_cfg; 3207 3208 /* 3209 * 802.3x flow control. 3210 */ 3211 pcr = 0; 3212 if (sc->sc_flowflags & IFM_FLOW) { 3213 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3214 pcr |= sc->sc_rx_flow_thresh; 3215 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3216 pcr |= PCR_PSEN | PCR_PS_MCAST; 3217 } 3218 3219 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3220 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3221 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3222 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3223 } 3224 #endif /* ! DP83820 */ 3225 3226 /* 3227 * sip_mii_bitbang_read: [mii bit-bang interface function] 3228 * 3229 * Read the MII serial port for the MII bit-bang module. 3230 */ 3231 static u_int32_t 3232 SIP_DECL(mii_bitbang_read)(struct device *self) 3233 { 3234 struct sip_softc *sc = (void *) self; 3235 3236 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3237 } 3238 3239 /* 3240 * sip_mii_bitbang_write: [mii big-bang interface function] 3241 * 3242 * Write the MII serial port for the MII bit-bang module. 3243 */ 3244 static void 3245 SIP_DECL(mii_bitbang_write)(struct device *self, u_int32_t val) 3246 { 3247 struct sip_softc *sc = (void *) self; 3248 3249 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3250 } 3251 3252 #ifndef DP83820 3253 /* 3254 * sip_sis900_mii_readreg: [mii interface function] 3255 * 3256 * Read a PHY register on the MII. 3257 */ 3258 static int 3259 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 3260 { 3261 struct sip_softc *sc = (struct sip_softc *) self; 3262 u_int32_t enphy; 3263 3264 /* 3265 * The PHY of recent SiS chipsets is accessed through bitbang 3266 * operations. 3267 */ 3268 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3269 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3270 phy, reg)); 3271 3272 #ifndef SIS900_MII_RESTRICT 3273 /* 3274 * The SiS 900 has only an internal PHY on the MII. Only allow 3275 * MII address 0. 3276 */ 3277 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3278 return (0); 3279 #endif 3280 3281 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3282 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3283 ENPHY_RWCMD | ENPHY_ACCESS); 3284 do { 3285 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3286 } while (enphy & ENPHY_ACCESS); 3287 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3288 } 3289 3290 /* 3291 * sip_sis900_mii_writereg: [mii interface function] 3292 * 3293 * Write a PHY register on the MII. 3294 */ 3295 static void 3296 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 3297 { 3298 struct sip_softc *sc = (struct sip_softc *) self; 3299 u_int32_t enphy; 3300 3301 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3302 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3303 phy, reg, val); 3304 return; 3305 } 3306 3307 #ifndef SIS900_MII_RESTRICT 3308 /* 3309 * The SiS 900 has only an internal PHY on the MII. Only allow 3310 * MII address 0. 3311 */ 3312 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3313 return; 3314 #endif 3315 3316 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3317 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3318 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3319 do { 3320 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3321 } while (enphy & ENPHY_ACCESS); 3322 } 3323 3324 /* 3325 * sip_sis900_mii_statchg: [mii interface function] 3326 * 3327 * Callback from MII layer when media changes. 3328 */ 3329 static void 3330 SIP_DECL(sis900_mii_statchg)(struct device *self) 3331 { 3332 struct sip_softc *sc = (struct sip_softc *) self; 3333 struct mii_data *mii = &sc->sc_mii; 3334 u_int32_t flowctl; 3335 3336 /* 3337 * Get flow control negotiation result. 3338 */ 3339 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3340 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3341 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3342 mii->mii_media_active &= ~IFM_ETH_FMASK; 3343 } 3344 3345 /* 3346 * Update TXCFG for full-duplex operation. 3347 */ 3348 if ((mii->mii_media_active & IFM_FDX) != 0) 3349 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3350 else 3351 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3352 3353 /* 3354 * Update RXCFG for full-duplex or loopback. 3355 */ 3356 if ((mii->mii_media_active & IFM_FDX) != 0 || 3357 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3358 sc->sc_rxcfg |= RXCFG_ATX; 3359 else 3360 sc->sc_rxcfg &= ~RXCFG_ATX; 3361 3362 /* 3363 * Update IMR for use of 802.3x flow control. 3364 */ 3365 if (sc->sc_flowflags & IFM_FLOW) { 3366 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3367 flowctl = FLOWCTL_FLOWEN; 3368 } else { 3369 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3370 flowctl = 0; 3371 } 3372 3373 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3374 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3375 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3376 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3377 } 3378 3379 /* 3380 * sip_dp83815_mii_readreg: [mii interface function] 3381 * 3382 * Read a PHY register on the MII. 3383 */ 3384 static int 3385 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 3386 { 3387 struct sip_softc *sc = (struct sip_softc *) self; 3388 u_int32_t val; 3389 3390 /* 3391 * The DP83815 only has an internal PHY. Only allow 3392 * MII address 0. 3393 */ 3394 if (phy != 0) 3395 return (0); 3396 3397 /* 3398 * Apparently, after a reset, the DP83815 can take a while 3399 * to respond. During this recovery period, the BMSR returns 3400 * a value of 0. Catch this -- it's not supposed to happen 3401 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3402 * PHY to come back to life. 3403 * 3404 * This works out because the BMSR is the first register 3405 * read during the PHY probe process. 3406 */ 3407 do { 3408 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3409 } while (reg == MII_BMSR && val == 0); 3410 3411 return (val & 0xffff); 3412 } 3413 3414 /* 3415 * sip_dp83815_mii_writereg: [mii interface function] 3416 * 3417 * Write a PHY register to the MII. 3418 */ 3419 static void 3420 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3421 { 3422 struct sip_softc *sc = (struct sip_softc *) self; 3423 3424 /* 3425 * The DP83815 only has an internal PHY. Only allow 3426 * MII address 0. 3427 */ 3428 if (phy != 0) 3429 return; 3430 3431 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3432 } 3433 3434 /* 3435 * sip_dp83815_mii_statchg: [mii interface function] 3436 * 3437 * Callback from MII layer when media changes. 3438 */ 3439 static void 3440 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3441 { 3442 struct sip_softc *sc = (struct sip_softc *) self; 3443 3444 /* 3445 * Update TXCFG for full-duplex operation. 3446 */ 3447 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3448 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3449 else 3450 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3451 3452 /* 3453 * Update RXCFG for full-duplex or loopback. 3454 */ 3455 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3456 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3457 sc->sc_rxcfg |= RXCFG_ATX; 3458 else 3459 sc->sc_rxcfg &= ~RXCFG_ATX; 3460 3461 /* 3462 * XXX 802.3x flow control. 3463 */ 3464 3465 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3466 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3467 3468 /* 3469 * Some DP83815s experience problems when used with short 3470 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3471 * sequence adjusts the DSP's signal attenuation to fix the 3472 * problem. 3473 */ 3474 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3475 uint32_t reg; 3476 3477 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3478 3479 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3480 reg &= 0x0fff; 3481 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3482 delay(100); 3483 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3484 reg &= 0x00ff; 3485 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3486 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3487 0x00e8); 3488 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3489 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3490 reg | 0x20); 3491 } 3492 3493 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3494 } 3495 } 3496 #endif /* DP83820 */ 3497 3498 #if defined(DP83820) 3499 static void 3500 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3501 const struct pci_attach_args *pa, u_int8_t *enaddr) 3502 { 3503 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3504 u_int8_t cksum, *e, match; 3505 int i; 3506 3507 /* 3508 * EEPROM data format for the DP83820 can be found in 3509 * the DP83820 manual, section 4.2.4. 3510 */ 3511 3512 SIP_DECL(read_eeprom)(sc, 0, 3513 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3514 3515 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3516 match = ~(match - 1); 3517 3518 cksum = 0x55; 3519 e = (u_int8_t *) eeprom_data; 3520 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3521 cksum += *e++; 3522 3523 if (cksum != match) 3524 printf("%s: Checksum (%x) mismatch (%x)", 3525 sc->sc_dev.dv_xname, cksum, match); 3526 3527 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3528 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3529 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3530 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3531 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3532 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3533 } 3534 #else /* ! DP83820 */ 3535 static void 3536 SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc) 3537 { 3538 int i; 3539 3540 /* 3541 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3542 * a reason, but I don't know it. 3543 */ 3544 for (i = 0; i < 10; i++) 3545 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3546 } 3547 3548 static void 3549 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3550 const struct pci_attach_args *pa, u_int8_t *enaddr) 3551 { 3552 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3553 3554 switch (sc->sc_rev) { 3555 case SIS_REV_630S: 3556 case SIS_REV_630E: 3557 case SIS_REV_630EA1: 3558 case SIS_REV_630ET: 3559 case SIS_REV_635: 3560 /* 3561 * The MAC address for the on-board Ethernet of 3562 * the SiS 630 chipset is in the NVRAM. Kick 3563 * the chip into re-loading it from NVRAM, and 3564 * read the MAC address out of the filter registers. 3565 */ 3566 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3567 3568 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3569 RFCR_RFADDR_NODE0); 3570 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3571 0xffff; 3572 3573 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3574 RFCR_RFADDR_NODE2); 3575 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3576 0xffff; 3577 3578 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3579 RFCR_RFADDR_NODE4); 3580 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3581 0xffff; 3582 break; 3583 3584 case SIS_REV_960: 3585 { 3586 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3587 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3588 3589 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3590 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3591 3592 int waittime, i; 3593 3594 /* Allow to read EEPROM from LAN. It is shared 3595 * between a 1394 controller and the NIC and each 3596 * time we access it, we need to set SIS_EECMD_REQ. 3597 */ 3598 SIS_SET_EROMAR(sc, EROMAR_REQ); 3599 3600 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3601 /* Force EEPROM to idle state. */ 3602 3603 /* 3604 * XXX-cube This is ugly. I'll look for docs about it. 3605 */ 3606 SIS_SET_EROMAR(sc, EROMAR_EECS); 3607 SIP_DECL(sis900_eeprom_delay)(sc); 3608 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3609 SIS_SET_EROMAR(sc, EROMAR_EESK); 3610 SIP_DECL(sis900_eeprom_delay)(sc); 3611 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3612 SIP_DECL(sis900_eeprom_delay)(sc); 3613 } 3614 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3615 SIP_DECL(sis900_eeprom_delay)(sc); 3616 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3617 3618 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3619 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3620 sizeof(myea) / sizeof(myea[0]), myea); 3621 break; 3622 } 3623 DELAY(1); 3624 } 3625 3626 /* 3627 * Set SIS_EECTL_CLK to high, so a other master 3628 * can operate on the i2c bus. 3629 */ 3630 SIS_SET_EROMAR(sc, EROMAR_EESK); 3631 3632 /* Refuse EEPROM access by LAN */ 3633 SIS_SET_EROMAR(sc, EROMAR_DONE); 3634 } break; 3635 3636 default: 3637 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3638 sizeof(myea) / sizeof(myea[0]), myea); 3639 } 3640 3641 enaddr[0] = myea[0] & 0xff; 3642 enaddr[1] = myea[0] >> 8; 3643 enaddr[2] = myea[1] & 0xff; 3644 enaddr[3] = myea[1] >> 8; 3645 enaddr[4] = myea[2] & 0xff; 3646 enaddr[5] = myea[2] >> 8; 3647 } 3648 3649 /* Table and macro to bit-reverse an octet. */ 3650 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3651 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3652 3653 static void 3654 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3655 const struct pci_attach_args *pa, u_int8_t *enaddr) 3656 { 3657 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3658 u_int8_t cksum, *e, match; 3659 int i; 3660 3661 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3662 sizeof(eeprom_data[0]), eeprom_data); 3663 3664 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3665 match = ~(match - 1); 3666 3667 cksum = 0x55; 3668 e = (u_int8_t *) eeprom_data; 3669 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3670 cksum += *e++; 3671 } 3672 if (cksum != match) { 3673 printf("%s: Checksum (%x) mismatch (%x)", 3674 sc->sc_dev.dv_xname, cksum, match); 3675 } 3676 3677 /* 3678 * Unrolled because it makes slightly more sense this way. 3679 * The DP83815 stores the MAC address in bit 0 of word 6 3680 * through bit 15 of word 8. 3681 */ 3682 ea = &eeprom_data[6]; 3683 enaddr[0] = ((*ea & 0x1) << 7); 3684 ea++; 3685 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3686 enaddr[1] = ((*ea & 0x1FE) >> 1); 3687 enaddr[2] = ((*ea & 0x1) << 7); 3688 ea++; 3689 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3690 enaddr[3] = ((*ea & 0x1FE) >> 1); 3691 enaddr[4] = ((*ea & 0x1) << 7); 3692 ea++; 3693 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3694 enaddr[5] = ((*ea & 0x1FE) >> 1); 3695 3696 /* 3697 * In case that's not weird enough, we also need to reverse 3698 * the bits in each byte. This all actually makes more sense 3699 * if you think about the EEPROM storage as an array of bits 3700 * being shifted into bytes, but that's not how we're looking 3701 * at it here... 3702 */ 3703 for (i = 0; i < 6 ;i++) 3704 enaddr[i] = bbr(enaddr[i]); 3705 } 3706 #endif /* DP83820 */ 3707 3708 /* 3709 * sip_mediastatus: [ifmedia interface function] 3710 * 3711 * Get the current interface media status. 3712 */ 3713 static void 3714 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3715 { 3716 struct sip_softc *sc = ifp->if_softc; 3717 3718 mii_pollstat(&sc->sc_mii); 3719 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3720 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3721 sc->sc_flowflags; 3722 } 3723 3724 /* 3725 * sip_mediachange: [ifmedia interface function] 3726 * 3727 * Set hardware to newly-selected media. 3728 */ 3729 static int 3730 SIP_DECL(mediachange)(struct ifnet *ifp) 3731 { 3732 struct sip_softc *sc = ifp->if_softc; 3733 3734 if (ifp->if_flags & IFF_UP) 3735 mii_mediachg(&sc->sc_mii); 3736 return (0); 3737 } 3738
Indexes created Tue Sep 30 11:09:46 GMT 2025