if_sipreg.h revision 1.21
1 /* $NetBSD: if_sipreg.h,v 1.21 2020/03/08 02:44:12 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999 Network Computer, Inc. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of Network Computer, Inc. nor the names of its 45 * contributors may be used to endorse or promote products derived 46 * from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 #ifndef _DEV_PCI_IF_SIPREG_H_ 62 #define _DEV_PCI_IF_SIPREG_H_ 63 64 /* 65 * Register description for the Silicon Integrated Systems SiS 900, 66 * SiS 7016, National Semiconductor DP83815 10/100, and National 67 * Semiconduction DP83820 10/100/1000 PCI Ethernet controller. 68 * 69 * Written by Jason R. Thorpe for Network Computer, Inc. 70 */ 71 72 /* 73 * Transmit FIFO size. Used to compute the transmit drain threshold. 74 * 75 * On the SiS 900, the transmit FIFO is arranged as a 512 32-bit memory 76 * array. 77 * 78 * On the DP83820, we have an 8KB transmit FIFO. 79 */ 80 #define DP83820_SIP_TXFIFO_SIZE 8192 81 #define OTHER_SIP_TXFIFO_SIZE (512 * 4) 82 83 /* 84 * The SiS900 uses a single descriptor format for both transmit 85 * and receive descriptor chains. 86 * 87 * Note the DP83820 can use 64-bit DMA addresses for link and bufptr. 88 * Note also that the buffer pointer and command/status words are in 89 * the opposite order on the DP83820 to facilitate 64-bit DMA addresses. 90 * 91 * For transmit, buffers need not be aligned. For receive, buffers 92 * must be aligned to 4-byte (8-byte on DP83820) boundaries. 93 */ 94 #define SIP_DESC_LINK 0 /* link to next descriptor */ 95 #define SIP_DESC_CMDSTS 1 /* ccommand/status */ 96 #define SIP_DESC_BUFPTR 2 /* pointer to DMA segment */ 97 98 #define GSIP_DESC_LINK 0 99 #define GSIP_DESC_BUFPTR 1 100 #define GSIP_DESC_CMDSTS 2 101 #define GSIP_DESC_EXTSTS 3 /* extended status */ 102 103 #define GSIP64_DESC_LINK_LO 0 104 #define GSIP64_DESC_LINK_HI 1 105 #define GSIP64_DESC_BUFPTR_LO 2 106 #define GSIP64_DESC_BUFPTR_HI 3 107 #define GSIP64_DESC_CMDSTS 4 108 #define GSIP64_DESC_EXTSTS 5 109 110 #define SIP_NDESC_WORDS 6 111 112 struct sip_desc { 113 uint32_t sipd_words[SIP_NDESC_WORDS]; 114 }; 115 116 /* 117 * CMDSTS bits common to transmit and receive. 118 */ 119 #define CMDSTS_OWN 0x80000000 /* owned by consumer */ 120 #define CMDSTS_MORE 0x40000000 /* more descriptors */ 121 #define CMDSTS_INTR 0x20000000 /* interrupt when ownership changes */ 122 #define CMDSTS_SUPCRC 0x10000000 /* suppress CRC */ 123 #define CMDSTS_OK 0x08000000 /* packet ok */ 124 #define DP83820_CMDSTS_SIZE_MASK 0x0000ffff /* packet size */ 125 #define OTHER_CMDSTS_SIZE_MASK 0x000007ff /* packet size */ 126 127 #define CMDSTS_SIZE(sc, x) ((x) & sc->sc_bits.b_cmdsts_size_mask) 128 129 /* 130 * CMDSTS bits for transmit. 131 */ 132 #define CMDSTS_Tx_TXA 0x04000000 /* transmit abort */ 133 #define CMDSTS_Tx_TFU 0x02000000 /* transmit FIFO underrun */ 134 #define CMDSTS_Tx_CRS 0x01000000 /* carrier sense lost */ 135 #define CMDSTS_Tx_TD 0x00800000 /* transmit deferred */ 136 #define CMDSTS_Tx_ED 0x00400000 /* excessive deferral */ 137 #define CMDSTS_Tx_OWC 0x00200000 /* out of window collision */ 138 #define CMDSTS_Tx_EC 0x00100000 /* excessive collisions */ 139 #define CMDSTS_Tx_CCNT 0x000f0000 /* collision count */ 140 141 #define CMDSTS_COLLISIONS(x) (((x) & CMDSTS_Tx_CCNT) >> 16) 142 143 /* 144 * CMDSTS bits for receive. 145 */ 146 #define CMDSTS_Rx_RXA 0x04000000 /* receive abort */ 147 #define CMDSTS_Rx_RXO 0x02000000 /* receive overrun */ 148 #define CMDSTS_Rx_DEST 0x01800000 /* destination class */ 149 #define CMDSTS_Rx_LONG 0x00400000 /* packet too long */ 150 #define CMDSTS_Rx_RUNT 0x00200000 /* runt packet */ 151 #define CMDSTS_Rx_ISE 0x00100000 /* invalid symbol error */ 152 #define CMDSTS_Rx_CRCE 0x00080000 /* CRC error */ 153 #define CMDSTS_Rx_FAE 0x00040000 /* frame alignment error */ 154 #define CMDSTS_Rx_LBP 0x00020000 /* loopback packet */ 155 /* #ifdef DP83820 */ 156 #define CMDSTS_Rx_IRL 0x00010000 /* in-range length error */ 157 /* #else */ 158 #define CMDSTS_Rx_COL 0x00010000 /* collision activity */ 159 /* #endif DP83820 */ 160 161 #define CMDSTS_Rx_DEST_REJ 0x00000000 /* packet rejected */ 162 #define CMDSTS_Rx_DEST_STA 0x00800000 /* matched station address */ 163 #define CMDSTS_Rx_DEST_MUL 0x01000000 /* multicast address */ 164 #define CMDSTS_Rx_DEST_BRD 0x01800000 /* broadcast address */ 165 166 /* 167 * EXTSTS bits. 168 */ 169 #define EXTSTS_Rx_UDPERR 0x00400000 /* UDP checksum error */ 170 #define EXTSTS_UDPPKT 0x00200000 /* perform UDP checksum */ 171 #define EXTSTS_Rx_TCPERR 0x00100000 /* TCP checksum error */ 172 #define EXTSTS_TCPPKT 0x00080000 /* perform TCP checksum */ 173 #define EXTSTS_Rx_IPERR 0x00040000 /* IP header checksum error */ 174 #define EXTSTS_IPPKT 0x00020000 /* perform IP header checksum */ 175 #define EXTSTS_VPKT 0x00010000 /* insert VLAN tag */ 176 #define EXTSTS_VTCI 0x0000ffff /* VLAN tag control information */ 177 178 /* 179 * PCI Configuration space registers. 180 */ 181 #define SIP_PCI_CFGIOA (PCI_MAPREG_START + 0x00) 182 183 #define SIP_PCI_CFGMA (PCI_MAPREG_START + 0x04) 184 185 /* DP83820 only */ 186 #define SIP_PCI_CFGMA1 (PCI_MAPREG_START + 0x08) 187 188 #define SIP_PCI_CFGEROMA 0x30 /* expansion ROM address */ 189 190 #define SIP_PCI_CFGPMC 0x40 /* power management cap. */ 191 192 #define SIP_PCI_CFGPMCSR 0x44 /* power management ctl. */ 193 194 /* 195 * MAC Operation Registers 196 */ 197 #define SIP_CR 0x00 /* command register */ 198 199 /* DP83820 only */ 200 #define CR_RXPRI3 0x00010000 /* Rx priority queue select */ 201 #define CR_RXPRI2 0x00008000 /* Rx priority queue select */ 202 #define CR_RXPRI1 0x00004000 /* Rx priority queue select */ 203 #define CR_RXPRI0 0x00002000 /* Rx priority queue select */ 204 #define CR_TXPRI3 0x00001000 /* Tx priority queue select */ 205 #define CR_TXPRI2 0x00000800 /* Tx priority queue select */ 206 #define CR_TXPRI1 0x00000400 /* Tx priority queue select */ 207 #define CR_TXPRI0 0x00000200 /* Tx priority queue select */ 208 209 #define CR_RLD 0x00000400 /* reload from NVRAM */ 210 #define CR_RST 0x00000100 /* software reset */ 211 #define CR_SWI 0x00000080 /* software interrupt */ 212 #define CR_RXR 0x00000020 /* receiver reset */ 213 #define CR_TXR 0x00000010 /* transmit reset */ 214 #define CR_RXD 0x00000008 /* receiver disable */ 215 #define CR_RXE 0x00000004 /* receiver enable */ 216 #define CR_TXD 0x00000002 /* transmit disable */ 217 #define CR_TXE 0x00000001 /* transmit enable */ 218 219 #define SIP_CFG 0x04 /* configuration register */ 220 #define CFG_LNKSTS 0x80000000 /* link status (83815) */ 221 /* #ifdef DP83820 */ 222 #define CFG_SPEED1000 0x40000000 /* 1000Mb/s input pin */ 223 #define CFG83820_SPEED100 0x20000000 /* 100Mb/s input pin */ 224 #define CFG_DUPSTS 0x10000000 /* full-duplex status */ 225 #define CFG_TBI_EN 0x01000000 /* ten-bit interface enable */ 226 #define CFG_MODE_1000 0x00400000 /* 1000Mb/s mode enable */ 227 #define CFG_PINT_DUP 0x00100000 /* interrupt on PHY DUP change */ 228 #define CFG_PINT_LNK 0x00080000 /* interrupt on PHY LNK change */ 229 #define CFG_PINT_SPD 0x00040000 /* interrupt on PHY SPD change */ 230 #define CFG_TMRTEST 0x00020000 /* timer test mode */ 231 #define CFG_MRM_DIS 0x00010000 /* MRM disable */ 232 #define CFG_MWI_DIS 0x00008000 /* MWI disable */ 233 #define CFG_T64ADDR 0x00004000 /* target 64-bit addressing enable */ 234 #define CFG_PCI64_DET 0x00002000 /* 64-bit PCI bus detected */ 235 #define CFG_DATA64_EN 0x00001000 /* 64-bit data enable */ 236 #define CFG_M64ADDR 0x00000800 /* master 64-bit addressing enable */ 237 /* #else */ 238 #define CFG83815_SPEED100 0x40000000 /* 100Mb/s (83815) */ 239 #define CFG_FDUP 0x20000000 /* full duplex (83815) */ 240 #define CFG_POL 0x10000000 /* 10Mb/s polarity (83815) */ 241 #define CFG_ANEG_DN 0x08000000 /* autonegotiation done (83815) */ 242 #define CFG_PHY_CFG 0x00fc0000 /* PHY configuration (83815) */ 243 #define CFG_PINT_ACEN 0x00020000 /* PHY interrupt auto clear (83815) */ 244 #define CFG_PAUSE_ADV 0x00010000 /* pause advertise (83815) */ 245 #define CFG_ANEG_SEL 0x0000e000 /* autonegotiation select (83815) */ 246 /* #endif DP83820 */ 247 #define CFG_PHY_RST 0x00000400 /* PHY reset (83815) */ 248 #define CFG_PHY_DIS 0x00000200 /* PHY disable (83815) */ 249 /* #ifdef DP83820 */ 250 #define CFG_EXTSTS_EN 0x00000100 /* extended status enable */ 251 /* #else */ 252 #define CFG_EUPHCOMP 0x00000100 /* 83810 descriptor compat (83815) */ 253 /* #endif DP83820 */ 254 #define CFG_EDBMASTEN 0x00002000 /* 635,900B ?? from linux driver */ 255 #define CFG_RNDCNT 0x00000400 /* 635,900B ?? from linux driver */ 256 #define CFG_FAIRBO 0x00000200 /* 635,900B ?? from linux driver */ 257 #define CFG_REQALG 0x00000080 /* PCI bus request alg. */ 258 #define CFG_SB 0x00000040 /* single backoff */ 259 #define CFG_POW 0x00000020 /* program out of window timer */ 260 #define CFG_EXD 0x00000010 /* excessive defferal timer disable */ 261 #define CFG_PESEL 0x00000008 /* parity error detection action */ 262 /* #ifdef DP83820 */ 263 #define CFG_BROM_DIS 0x00000004 /* boot ROM disable */ 264 #define CFG_EXT_125 0x00000002 /* external 125MHz reference select */ 265 /* #endif DP83820 */ 266 #define CFG_BEM 0x00000001 /* big-endian mode */ 267 268 #define SIP_EROMAR 0x08 /* EEPROM access register */ 269 #define EROMAR_REQ 0x00000400 /* SiS 96x specific */ 270 #define EROMAR_DONE 0x00000200 /* SiS 96x specific */ 271 #define EROMAR_GNT 0x00000100 /* SiS 96x specific */ 272 #define EROMAR_MDC 0x00000040 /* MII clock */ 273 #define EROMAR_MDDIR 0x00000020 /* MII direction (1 == MAC->PHY) */ 274 #define EROMAR_MDIO 0x00000010 /* MII data */ 275 #define EROMAR_EECS 0x00000008 /* chip select */ 276 #define EROMAR_EESK 0x00000004 /* clock */ 277 #define EROMAR_EEDO 0x00000002 /* data out */ 278 #define EROMAR_EEDI 0x00000001 /* data in */ 279 280 #define SIP_PTSCR 0x0c /* PCI test control register */ 281 #define PTSCR_RBIST_RST 0x00002000 /* SRAM BIST reset */ 282 #define PTSCR_RBIST_EN 0x00000400 /* SRAM BIST enable */ 283 #define PTSCR_RBIST_DONE 0x00000200 /* SRAM BIST done */ 284 #define PTSCR_RBIST_RX1FAIL 0x00000100 /* Rx status FIFO BIST fail */ 285 #define PTSCR_RBIST_RX0FAIL 0x00000080 /* Rx data FIFO BIST fail */ 286 #define PTSCR_RBIST_TX0FAIL 0x00000020 /* Tx data FIFO BIST fail */ 287 #define PTSCR_RBIST_HFFAIL 0x00000010 /* hash filter BIST fail */ 288 #define PTSCR_RBIST_RXFAIL 0x00000008 /* Rx filter BIST failed */ 289 #define PTSCR_EELOAD_EN 0x00000004 /* EEPROM load initiate */ 290 #define PTSCR_EEBIST_EN 0x00000002 /* EEPROM BIST enable */ 291 #define PTSCR_EEBIST_FAIL 0x00000001 /* EEPROM BIST failed */ 292 #define PTSCR_DIS_TEST 0x40000000 /* discard timer test mode */ 293 #define PTSCR_EROM_TACC 0x0f000000 /* boot rom access time */ 294 #define PTSCR_TRRAMADR 0x001ff000 /* TX/RX RAM address */ 295 #define PTSCR_BMTEN 0x00000200 /* bus master test enable */ 296 #define PTSCR_RRTMEN 0x00000080 /* receive RAM test mode enable */ 297 #define PTSCR_TRTMEN 0x00000040 /* transmit RAM test mode enable */ 298 #define PTSCR_SRTMEN 0x00000020 /* status RAM test mode enable */ 299 #define PTSCR_SRAMADR 0x0000001f /* status RAM address */ 300 301 #define SIP_ISR 0x10 /* interrupt status register */ 302 /* DP83820 only */ 303 #define ISR_TXDESC3 0x40000000 /* Tx queue 3 */ 304 #define ISR_TXDESC2 0x20000000 /* Tx queue 2 */ 305 #define ISR_TXDESC1 0x10000000 /* Tx queue 1 */ 306 #define ISR_TXDESC0 0x08000000 /* Tx queue 0 */ 307 #define ISR_RXDESC3 0x04000000 /* Rx queue 3 */ 308 #define ISR_RXDESC2 0x02000000 /* Rx queue 2 */ 309 #define ISR_RXDESC1 0x01000000 /* Rx queue 1 */ 310 #define ISR_RXDESC0 0x00800000 /* Rx queue 0 */ 311 312 /* non-DP83820 only */ 313 #define ISR_WAKEEVT 0x10000000 /* wake up event */ 314 315 #if 0 316 #ifdef DP83820 317 #define ISR_TXRCMP 0x00400000 /* transmit reset complete */ 318 #define ISR_RXRCMP 0x00200000 /* receive reset complete */ 319 #define ISR_DPERR 0x00100000 /* detected parity error */ 320 #define ISR_SSERR 0x00080000 /* signalled system error */ 321 #define ISR_RMABT 0x00040000 /* received master abort */ 322 #define ISR_RTABT 0x00020000 /* received target abort */ 323 #else 324 #define ISR_TXRCMP 0x02000000 /* transmit reset complete */ 325 #define ISR_RXRCMP 0x01000000 /* receive reset complete */ 326 #define ISR_DPERR 0x00800000 /* detected parity error */ 327 #define ISR_SSERR 0x00400000 /* signalled system error */ 328 #define ISR_RMABT 0x00200000 /* received master abort */ 329 #define ISR_RTABT 0x00100000 /* received target abort */ 330 #endif /* DP83820 */ 331 #endif /* 0 */ 332 333 /* SiS 900 only */ 334 #define ISR_PAUSE_END 0x08000000 /* end of transmission pause */ 335 #define ISR_PAUSE_ST 0x04000000 /* start of transmission pause */ 336 337 #define ISR_RXSOVR 0x00010000 /* Rx status FIFO overrun */ 338 #define ISR_HIBERR 0x00008000 /* high bits error set */ 339 340 /* DP83820 only */ 341 #define ISR_PHY 0x00004000 /* PHY interrupt */ 342 #define ISR_PME 0x00002000 /* power management event */ 343 344 #define ISR_SWI 0x00001000 /* software interrupt */ 345 346 /* DP83820 only */ 347 #define ISR_MIB 0x00000800 /* MIB service */ 348 349 #define ISR_TXURN 0x00000400 /* Tx underrun */ 350 #define ISR_TXIDLE 0x00000200 /* Tx idle */ 351 #define ISR_TXERR 0x00000100 /* Tx error */ 352 #define ISR_TXDESC 0x00000080 /* Tx descriptor interrupt */ 353 #define ISR_TXOK 0x00000040 /* Tx okay */ 354 #define ISR_RXORN 0x00000020 /* Rx overrun */ 355 #define ISR_RXIDLE 0x00000010 /* Rx idle */ 356 #define ISR_RXEARLY 0x00000008 /* Rx early */ 357 #define ISR_RXERR 0x00000004 /* Rx error */ 358 #define ISR_RXDESC 0x00000002 /* Rx descriptor interrupt */ 359 #define ISR_RXOK 0x00000001 /* Rx okay */ 360 361 #define SIP_IMR 0x14 /* interrupt mask register */ 362 /* See bits in SIP_ISR */ 363 364 #define SIP_IER 0x18 /* interrupt enable register */ 365 #define IER_IE 0x00000001 /* master interrupt enable */ 366 367 /* #ifdef DP83820 */ 368 #define SIP_IHR 0x1c /* interrupt hold-off register */ 369 #define IHR_IHCTL 0x00000100 /* interrupt hold-off control */ 370 #define IHR_IH 0x000000ff /* interrupt hold-off timer (100us) */ 371 /* #else */ 372 #define SIP_ENPHY 0x1c /* enhanced PHY access register */ 373 #define ENPHY_PHYDATA 0xffff0000 /* PHY data */ 374 #define ENPHY_DATA_SHIFT 16 375 #define ENPHY_PHYADDR 0x0000f800 /* PHY number (7016 only) */ 376 #define ENPHY_PHYADDR_SHIFT 11 377 #define ENPHY_REGADDR 0x000007c0 /* PHY register */ 378 #define ENPHY_REGADDR_SHIFT 6 379 #define ENPHY_RWCMD 0x00000020 /* 1 == read, 0 == write */ 380 #define ENPHY_ACCESS 0x00000010 /* PHY access enable */ 381 /* #endif DP83820 */ 382 383 #define SIP_TXDP 0x20 /* transmit descriptor pointer reg */ 384 385 /* DP83820 only */ 386 #define SIP_TXDP_HI 0x24 /* transmit descriptor pointer (high) reg */ 387 388 #define DP83820_SIP_TXCFG 0x28 /* transmit configuration register */ 389 #define OTHER_SIP_TXCFG 0x24 /* transmit configuration register */ 390 391 #define TXCFG_CSI 0x80000000 /* carrier sense ignore */ 392 #define TXCFG_HBI 0x40000000 /* heartbeat ignore */ 393 #define TXCFG_MLB 0x20000000 /* MAC loopback */ 394 #define TXCFG_ATP 0x10000000 /* automatic transmit padding */ 395 #define TXCFG_MXDMA 0x00700000 /* max DMA burst size */ 396 397 /* DP83820 only */ 398 #define TXCFG_ECRETRY 0x008000000 /* excessive collision retry enable */ 399 #define TXCFG_BRST_DIS 0x00080000 /* 1000Mb/s burst disable */ 400 401 /* DP83820 only */ 402 #define TXCFG_MXDMA_1024 0x00000000 /* 1024 bytes */ 403 #if 0 404 #ifdef DP83820 405 #define TXCFG_MXDMA_8 0x00100000 /* 8 bytes */ 406 #define TXCFG_MXDMA_16 0x00200000 /* 16 bytes */ 407 #define TXCFG_MXDMA_32 0x00300000 /* 32 bytes */ 408 #define TXCFG_MXDMA_64 0x00400000 /* 64 bytes */ 409 #define TXCFG_MXDMA_128 0x00500000 /* 128 bytes */ 410 #define TXCFG_MXDMA_256 0x00600000 /* 256 bytes */ 411 #define TXCFG_MXDMA_512 0x00700000 /* 512 bytes */ 412 #define TXCFG_FLTH_MASK 0x0000ff00 /* Fx fill threshold */ 413 #define TXCFG_DRTH_MASK 0x000000ff /* Tx drain threshold */ 414 #else 415 #define TXCFG_MXDMA_512 0x00000000 /* 512 bytes */ 416 #define TXCFG_MXDMA_8 0x00200000 /* 8 bytes */ 417 #define TXCFG_MXDMA_16 0x00300000 /* 16 bytes */ 418 #define TXCFG_MXDMA_32 0x00400000 /* 32 bytes */ 419 #define TXCFG_MXDMA_64 0x00500000 /* 64 bytes */ 420 #define TXCFG_MXDMA_128 0x00600000 /* 128 bytes */ 421 #define TXCFG_MXDMA_256 0x00700000 /* 256 bytes */ 422 #define TXCFG_FLTH_MASK 0x00003f00 /* Tx fill threshold */ 423 #define TXCFG_DRTH_MASK 0x0000003f /* Tx drain threshold */ 424 #endif /* DP83820 */ 425 #endif /* 0 */ 426 427 /* non-DP83820 only */ 428 #define TXCFG_MXDMA_4 0x00100000 /* 4 bytes */ 429 430 #define SIP_GPIOR 0x2c /* general purpose i/o register */ 431 #define GPIOR_GP5_IN 0x00004000 /* GP 5 in */ 432 #define GPIOR_GP4_IN 0x00002000 /* GP 4 in */ 433 #define GPIOR_GP3_IN 0x00001000 /* GP 3 in */ 434 #define GPIOR_GP2_IN 0x00000800 /* GP 2 in */ 435 #define GPIOR_GP1_IN 0x00000400 /* GP 1 in */ 436 #define GPIOR_GP5_OE 0x00000200 /* GP 5 out enable */ 437 #define GPIOR_GP4_OE 0x00000100 /* GP 4 out enable */ 438 #define GPIOR_GP3_OE 0x00000080 /* GP 3 out enable */ 439 #define GPIOR_GP2_OE 0x00000040 /* GP 2 out enable */ 440 #define GPIOR_GP1_OE 0x00000020 /* GP 1 out enable */ 441 #define GPIOR_GP5_OUT 0x00000010 /* GP 5 out */ 442 #define GPIOR_GP4_OUT 0x00000008 /* GP 4 out */ 443 #define GPIOR_GP3_OUT 0x00000004 /* GP 3 out */ 444 #define GPIOR_GP2_OUT 0x00000002 /* GP 2 out */ 445 #define GPIOR_GP1_OUT 0x00000001 /* GP 1 out */ 446 447 #define SIP_RXDP 0x30 /* receive descriptor pointer reg */ 448 449 /* DP83820 only */ 450 #define SIP_RXDP_HI 0x34 /* receive descriptor pointer (high) reg */ 451 452 #define DP83820_SIP_RXCFG 0x38 /* receive configuration register */ 453 #define OTHER_SIP_RXCFG 0x34 /* receive configuration register */ 454 #define RXCFG_AEP 0x80000000 /* accept error packets */ 455 #define RXCFG_ARP 0x40000000 /* accept runt packets */ 456 /* DP83820 only */ 457 #define RXCFG_STRIPCRC 0x20000000 /* strip CRC */ 458 459 #define RXCFG_ATX 0x10000000 /* accept transmit packets */ 460 #define RXCFG_ALP 0x08000000 /* accept long packets */ 461 462 /* DP83820 only */ 463 #define RXCFG_AIRL 0x04000000 /* accept in-range length err packets */ 464 465 #define RXCFG_MXDMA 0x00700000 /* max DMA burst size */ 466 467 /* DP83820 only */ 468 #define RXCFG_MXDMA_1024 0x00000000 /* 1024 bytes */ 469 470 #if 0 471 #ifdef DP83820 472 #define RXCFG_MXDMA_8 0x00100000 /* 8 bytes */ 473 #define RXCFG_MXDMA_16 0x00200000 /* 16 bytes */ 474 #define RXCFG_MXDMA_32 0x00300000 /* 32 bytes */ 475 #define RXCFG_MXDMA_64 0x00400000 /* 64 bytes */ 476 #define RXCFG_MXDMA_128 0x00500000 /* 128 bytes */ 477 #define RXCFG_MXDMA_256 0x00600000 /* 256 bytes */ 478 #define RXCFG_MXDMA_512 0x00700000 /* 512 bytes */ 479 #else 480 #define RXCFG_MXDMA_512 0x00000000 /* 512 bytes */ 481 #define RXCFG_MXDMA_8 0x00200000 /* 8 bytes */ 482 #define RXCFG_MXDMA_16 0x00300000 /* 16 bytes */ 483 #define RXCFG_MXDMA_32 0x00400000 /* 32 bytes */ 484 #define RXCFG_MXDMA_64 0x00500000 /* 64 bytes */ 485 #define RXCFG_MXDMA_128 0x00600000 /* 128 bytes */ 486 #define RXCFG_MXDMA_256 0x00700000 /* 256 bytes */ 487 #endif /* DP83820 */ 488 #endif /* 0 */ 489 490 /* non-DP83820 only */ 491 #define RXCFG_MXDMA_4 0x00100000 /* 4 bytes */ 492 #define RXCFG_DRTH_MASK 0x0000003e 493 494 /* DP83820 only */ 495 #define SIP_PQCR 0x3c /* priority queueing control register */ 496 #define PQCR_RXPQ_4 0x0000000c /* 4 Rx queues */ 497 #define PQCR_RXPQ_3 0x00000008 /* 3 Rx queues */ 498 #define PQCR_RXPQ_2 0x00000004 /* 2 Rx queues */ 499 #define PQCR_TXFAIR 0x00000002 /* Tx fairness enable */ 500 #define PQCR_TXPQEN 0x00000001 /* Tx priority queueing enable */ 501 502 /* DP83815 only */ 503 #define SIP83815_NS_CCSR 0x3c /* CLKRUN control/status register (83815) */ 504 #define CCSR_PMESTS 0x00008000 /* PME status */ 505 #define CCSR_PMEEN 0x00000100 /* PME enable */ 506 #define CCSR_CLKRUN_EN 0x00000001 /* clkrun enable */ 507 508 /* SiS 900 only */ 509 #define SIP_FLOWCTL 0x38 /* flow control register */ 510 #define FLOWCTL_PAUSE 0x00000002 /* PAUSE flag */ 511 #define FLOWCTL_FLOWEN 0x00000001 /* enable flow control */ 512 513 #define SIP_NS_WCSR 0x40 /* WoL control/status register (83815/83820) */ 514 515 #define SIP_NS_PCR 0x44 /* pause control/status reg (83815/83820) */ 516 #define PCR_PSEN 0x80000000 /* pause enable */ 517 #define PCR_PS_MCAST 0x40000000 /* pause on multicast */ 518 #define PCR_PS_DA 0x20000000 /* pause on DA */ 519 #define PCR_PS_ACT 0x10000000 /* pause active */ 520 #define PCR_PS_RCVD 0x08000000 /* pause packet received */ 521 /* #ifdef DP83820 */ 522 #define PCR_PS_STHI_8 0x03000000 /* Status FIFO Hi Threshold (8packets) */ 523 #define PCR_PS_STHI_4 0x02000000 /* Status FIFO Hi Threshold (4packets) */ 524 #define PCR_PS_STHI_2 0x01000000 /* Status FIFO Hi Threshold (2packets) */ 525 #define PCR_PS_STHI_0 0x00000000 /* Status FIFO Hi Threshold (disable) */ 526 #define PCR_PS_STLO_8 0x00c00000 /* Status FIFO Lo Threshold (8packets) */ 527 #define PCR_PS_STLO_4 0x00800000 /* Status FIFO Lo Threshold (4packets) */ 528 #define PCR_PS_STLO_2 0x00400000 /* Status FIFO Lo Threshold (2packets) */ 529 #define PCR_PS_STLO_0 0x00000000 /* Status FIFO Lo Threshold (disable) */ 530 #define PCR_PS_FFHI_8 0x00300000 /* Data FIFO Hi Threshold (8Kbyte) */ 531 #define PCR_PS_FFHI_4 0x00200000 /* Data FIFO Hi Threshold (4Kbyte) */ 532 #define PCR_PS_FFHI_2 0x00100000 /* Data FIFO Hi Threshold (2Kbyte) */ 533 #define PCR_PS_FFHI_0 0x00000000 /* Data FIFO Hi Threshold (disable) */ 534 #define PCR_PS_FFLO_8 0x000c0000 /* Data FIFO Lo Threshold (8Kbyte) */ 535 #define PCR_PS_FFLO_4 0x00080000 /* Data FIFO Lo Threshold (4Kbyte) */ 536 #define PCR_PS_FFLO_2 0x00040000 /* Data FIFO Lo Threshold (2Kbyte) */ 537 #define PCR_PS_FFLO_0 0x00000000 /* Data FIFO Lo Threshold (disable) */ 538 #define PCR_PS_TX 0x00020000 /* Transmit PAUSE frame manually */ 539 /* #else */ 540 #define PCR_PSNEG 0x00200000 /* Pause Negoticated (83815) */ 541 #define PCR_MLD_EN 0x00010000 /* Manual Load Enable (83815) */ 542 /* #endif DP83820 */ 543 #define PCR_PAUSE_CNT_MASK 0x0000ffff /* pause count mask */ 544 #define PCR_PAUSE_CNT 65535 /* pause count (512bit-time) */ 545 546 #define SIP_RFCR 0x48 /* receive filter control register */ 547 #define RFCR_RFEN 0x80000000 /* Rx filter enable */ 548 #define RFCR_AAB 0x40000000 /* accept all broadcast */ 549 #define RFCR_AAM 0x20000000 /* accept all multicast */ 550 #define RFCR_AAP 0x10000000 /* accept all physical */ 551 #define RFCR_APM 0x08000000 /* accept perfect match (83815) */ 552 #define RFCR_APAT 0x07800000 /* accept pattern match (83815) */ 553 #define RFCR_AARP 0x00400000 /* accept ARP (83815) */ 554 #define RFCR_MHEN 0x00200000 /* multicast hash enable (83815) */ 555 #define RFCR_UHEN 0x00100000 /* unicast hash enable (83815) */ 556 #define RFCR_ULM 0x00080000 /* U/L bit mask (83815) */ 557 #define RFCR_NS_RFADDR 0x000003ff /* Rx filter ext reg address (83815) */ 558 #define RFCR_RFADDR 0x000f0000 /* Rx filter address */ 559 #define RFCR_RFADDR_NODE0 0x00000000 /* node address 1, 0 */ 560 #define RFCR_RFADDR_NODE2 0x00010000 /* node address 3, 2 */ 561 #define RFCR_RFADDR_NODE4 0x00020000 /* node address 5, 4 */ 562 #define RFCR_RFADDR_MC0 0x00040000 /* multicast hash word 0 */ 563 #define RFCR_RFADDR_MC1 0x00050000 /* multicast hash word 1 */ 564 #define RFCR_RFADDR_MC2 0x00060000 /* multicast hash word 2 */ 565 #define RFCR_RFADDR_MC3 0x00070000 /* multicast hash word 3 */ 566 #define RFCR_RFADDR_MC4 0x00080000 /* multicast hash word 4 */ 567 #define RFCR_RFADDR_MC5 0x00090000 /* multicast hash word 5 */ 568 #define RFCR_RFADDR_MC6 0x000a0000 /* multicast hash word 6 */ 569 #define RFCR_RFADDR_MC7 0x000b0000 /* multicast hash word 7 */ 570 /* For SiS900B and 635/735 only */ 571 #define RFCR_RFADDR_MC8 0x000c0000 /* multicast hash word 8 */ 572 #define RFCR_RFADDR_MC9 0x000d0000 /* multicast hash word 9 */ 573 #define RFCR_RFADDR_MC10 0x000e0000 /* multicast hash word 10 */ 574 #define RFCR_RFADDR_MC11 0x000f0000 /* multicast hash word 11 */ 575 #define RFCR_RFADDR_MC12 0x00100000 /* multicast hash word 12 */ 576 #define RFCR_RFADDR_MC13 0x00110000 /* multicast hash word 13 */ 577 #define RFCR_RFADDR_MC14 0x00120000 /* multicast hash word 14 */ 578 #define RFCR_RFADDR_MC15 0x00130000 /* multicast hash word 15 */ 579 580 #define RFCR_NS_RFADDR_PMATCH0 0x0000 /* perfect match octets 1-0 */ 581 #define RFCR_NS_RFADDR_PMATCH2 0x0002 /* perfect match octets 3-2 */ 582 #define RFCR_NS_RFADDR_PMATCH4 0x0004 /* perfect match octets 5-4 */ 583 #define RFCR_NS_RFADDR_PCOUNT 0x0006 /* pattern count */ 584 585 /* DP83820 only */ 586 #define RFCR_NS_RFADDR_PCOUNT2 0x0008 /* pattern count 2, 3 */ 587 #define RFCR_NS_RFADDR_SOPAS0 0x000a /* SecureOn 0, 1 */ 588 #define RFCR_NS_RFADDR_SOPAS2 0x000c /* SecureOn 2, 3 */ 589 #define RFCR_NS_RFADDR_SOPAS4 0x000e /* SecureOn 4, 5 */ 590 #define RFCR_NS_RFADDR_PATMEM 0x0200 /* pattern memory */ 591 592 #define DP83820_RFCR_NS_RFADDR_FILTMEM 0x0100 /* hash memory */ 593 #define OTHER_RFCR_NS_RFADDR_FILTMEM 0x0200 /* filter memory (hash/pattern) */ 594 595 #define SIP_RFDR 0x4c /* receive filter data register */ 596 #define RFDR_BMASK 0x00030000 /* byte mask (83815) */ 597 #define RFDR_DATA 0x0000ffff /* data bits */ 598 599 #define SIP_NS_BRAR 0x50 /* boot rom address (83815) */ 600 #define BRAR_AUTOINC 0x80000000 /* autoincrement */ 601 #define BRAR_ADDR 0x0000ffff /* address */ 602 603 #define SIP_NS_BRDR 0x54 /* boot rom data (83815) */ 604 605 #define SIP_NS_SRR 0x58 /* silicon revision register (83815) */ 606 /* #ifdef DP83820 */ 607 #define SRR_REV_B 0x00000103 608 /* #else */ 609 #define SRR_REV_A 0x00000101 610 #define SRR_REV_B_1 0x00000200 611 #define SRR_REV_B_2 0x00000201 612 #define SRR_REV_B_3 0x00000203 613 #define SRR_REV_C_1 0x00000300 614 #define SRR_REV_C_2 0x00000302 615 /* #endif DP83820 */ 616 617 #define SIP_NS_MIBC 0x5c /* mib control register (83815) */ 618 #define MIBC_MIBS 0x00000008 /* mib counter strobe */ 619 #define MIBC_ACLR 0x00000004 /* clear all counters */ 620 #define MIBC_FRZ 0x00000002 /* freeze all counters */ 621 #define MIBC_WRN 0x00000001 /* warning test indicator */ 622 623 #define SIP_NS_MIB(mibreg) /* mib data registers (83815) */ \ 624 (0x60 + (mibreg)) 625 #define MIB_RXErroredPkts 0x00 626 #define MIB_RXFCSErrors 0x04 627 #define MIB_RXMsdPktErrors 0x08 628 #define MIB_RXFAErrors 0x0c 629 #define MIB_RXSymbolErrors 0x10 630 #define MIB_RXFrameTooLong 0x14 631 /* #ifdef DP83820 */ 632 #define MIB_RXIRLErrors 0x18 633 #define MIB_RXBadOpcodes 0x1c 634 #define MIB_RXPauseFrames 0x20 635 #define MIB_TXPauseFrames 0x24 636 #define MIB_TXSQEErrors 0x28 637 /* #else */ 638 #define MIB_RXTXSQEErrors 0x18 639 /* #endif DP83820 */ 640 641 /* 83815 only */ 642 #define SIP_NS_PHY(miireg) /* PHY registers (83815) */ \ 643 (0x80 + ((miireg) << 2)) 644 645 /* #ifdef DP83820 */ 646 #define SIP_TXDP1 0xa0 /* transmit descriptor pointer (pri 1) */ 647 648 #define SIP_TXDP2 0xa4 /* transmit descriptor pointer (pri 2) */ 649 650 #define SIP_TXDP3 0xa8 /* transmit descriptor pointer (pri 3) */ 651 652 #define SIP_RXDP1 0xb0 /* receive descriptor pointer (pri 1) */ 653 654 #define SIP_RXDP2 0xb4 /* receive descriptor pointer (pri 2) */ 655 656 #define SIP_RXDP3 0xb8 /* receive descriptor pointer (pri 3) */ 657 658 #define SIP_VRCR 0xbc /* VLAN/IP receive control register */ 659 #define VRCR_RUDPE 0x00000080 /* reject UDP checksum errors */ 660 #define VRCR_RTCPE 0x00000040 /* reject TCP checksum errors */ 661 #define VRCR_RIPE 0x00000020 /* reject IP checksum errors */ 662 #define VRCR_IPEN 0x00000010 /* IP checksum enable */ 663 #define VRCR_DUTF 0x00000008 /* discard untagged frames */ 664 #define VRCR_DVTF 0x00000004 /* discard VLAN tagged frames */ 665 #define VRCR_VTREN 0x00000002 /* VLAN tag removal enable */ 666 #define VRCR_VTDEN 0x00000001 /* VLAN tag detection enable */ 667 668 #define SIP_VTCR 0xc0 /* VLAN/IP transmit control register */ 669 #define VTCR_PPCHK 0x00000008 /* per-packet checksum generation */ 670 #define VTCR_GCHK 0x00000004 /* global checksum generation */ 671 #define VTCR_VPPTI 0x00000002 /* VLAN per-packet tag insertion */ 672 #define VTCR_VGTI 0x00000001 /* VLAN global tag insertion */ 673 674 #define SIP_VDR 0xc4 /* VLAN data register */ 675 #define VDR_VTCI 0xffff0000 /* VLAN tag control information */ 676 #define VDR_VTYPE 0x0000ffff /* VLAN type field */ 677 678 #define SIP83820_NS_CCSR 0xcc /* CLKRUN control/status register (83820) */ 679 #if 0 680 #define CCSR_PMESTS 0x00008000 /* PME status */ 681 #define CCSR_PMEEN 0x00000100 /* PME enable */ 682 #define CCSR_CLKRUN_EN 0x00000001 /* clkrun enable */ 683 #endif 684 685 #define SIP_TBICR 0xe0 /* TBI control register */ 686 #define TBICR_MR_LOOPBACK 0x00004000 /* TBI PCS loopback enable */ 687 #define TBICR_MR_AN_ENABLE 0x00001000 /* TBI autonegotiation enable */ 688 #define TBICR_MR_RESTART_AN 0x00000200 /* restart TBI autoneogtiation */ 689 690 #define SIP_TBISR 0xe4 /* TBI status register */ 691 #define TBISR_MR_LINK_STATUS 0x00000020 /* TBI link status */ 692 #define TBISR_MR_AN_COMPLETE 0x00000004 /* TBI autonegotiation complete */ 693 694 #define SIP_TANAR 0xe8 /* TBI autoneg adv. register */ 695 #define TANAR_NP 0x00008000 /* next page exchange required */ 696 #define TANAR_RF2 0x00002000 /* remote fault 2 */ 697 #define TANAR_RF1 0x00001000 /* remote fault 1 */ 698 #define TANAR_PS2 0x00000100 /* pause encoding 2 */ 699 #define TANAR_PS1 0x00000080 /* pause encoding 1 */ 700 #define TANAR_HALF_DUP 0x00000040 /* adv. half duplex */ 701 #define TANAR_FULL_DUP 0x00000020 /* adv. full duplex */ 702 703 #define SIP_TANLPAR 0xec /* TBI autoneg link partner ability register */ 704 /* See TANAR bits */ 705 706 #define SIP_TANER 0xf0 /* TBI autoneg expansion register */ 707 #define TANER_NPA 0x00000004 /* we support next page function */ 708 #define TANER_PR 0x00000002 /* page received from link partner */ 709 710 #define SIP_TESR 0xf4 /* TBI extended status register */ 711 #define TESR_1000FDX 0x00008000 /* we support 1000base FDX */ 712 #define TESR_1000HDX 0x00004000 /* we support 1000base HDX */ 713 /* #else */ 714 #define SIP_PMCTL 0xb0 /* power management control register */ 715 #define PMCTL_GATECLK 0x80000000 /* gate dual clock enable */ 716 #define PMCTL_WAKEALL 0x40000000 /* wake on all Rx OK */ 717 #define PMCTL_FRM3ACS 0x04000000 /* 3rd wake-up frame access */ 718 #define PMCTL_FRM2ACS 0x02000000 /* 2nd wake-up frame access */ 719 #define PMCTL_FRM1ACS 0x01000000 /* 1st wake-up frame access */ 720 #define PMCTL_FRM3EN 0x00400000 /* 3rd wake-up frame match enable */ 721 #define PMCTL_FRM2EN 0x00200000 /* 2nd wake-up frame match enable */ 722 #define PMCTL_FRM1EN 0x00100000 /* 1st wake-up frame match enable */ 723 #define PMCTL_ALGORITHM 0x00000800 /* Magic Packet match algorithm */ 724 #define PMCTL_MAGICPKT 0x00000400 /* Magic Packet match enable */ 725 #define PMCTL_LINKON 0x00000002 /* link on monitor enable */ 726 #define PMCTL_LINKLOSS 0x00000001 /* link loss monitor enable */ 727 728 #define SIP_PMEVT 0xb4 /* power management wake-up evnt reg */ 729 #define PMEVT_ALLFRMMAT 0x40000000 /* receive packet ok */ 730 #define PMEVT_FRM3MAT 0x04000000 /* match 3rd wake-up frame */ 731 #define PMEVT_FRM2MAT 0x02000000 /* match 2nd wake-up frame */ 732 #define PMEVT_FRM1MAT 0x01000000 /* match 1st wake-up frame */ 733 #define PMEVT_MAGICPKT 0x00000400 /* Magic Packet */ 734 #define PMEVT_ONEVT 0x00000002 /* link on event */ 735 #define PMEVT_LOSSEVT 0x00000001 /* link loss event */ 736 737 #define SIP_WAKECRC 0xbc /* wake-up frame CRC register */ 738 739 #define SIP_WAKEMASK0 0xc0 /* wake-up frame mask registers */ 740 #define SIP_WAKEMASK1 0xc4 741 #define SIP_WAKEMASK2 0xc8 742 #define SIP_WAKEMASK3 0xcc 743 #define SIP_WAKEMASK4 0xe0 744 #define SIP_WAKEMASK5 0xe4 745 #define SIP_WAKEMASK6 0xe8 746 #define SIP_WAKEMASK7 0xec 747 /* #endif DP83820 */ 748 749 /* 750 * Revision codes for the SiS 630 chipset built-in Ethernet. 751 */ 752 #define SIS_REV_900B 0x03 753 #define SIS_REV_630E 0x81 754 #define SIS_REV_630S 0x82 755 #define SIS_REV_630EA1 0x83 756 #define SIS_REV_630ET 0x84 757 #define SIS_REV_635 0x90 /* same for 735 (745?) */ 758 #define SIS_REV_960 0x91 759 760 /* 761 * MII operations for recent SiS chipsets 762 */ 763 #define SIS_MII_STARTDELIM 0x01 764 #define SIS_MII_READOP 0x02 765 #define SIS_MII_WRITEOP 0x01 766 #define SIS_MII_TURNAROUND 0x02 767 768 /* 769 * Serial EEPROM opcodes, including the start bit. 770 */ 771 #define SIP_EEPROM_OPC_ERASE 0x04 772 #define SIP_EEPROM_OPC_WRITE 0x05 773 #define SIP_EEPROM_OPC_READ 0x06 774 775 /* 776 * Serial EEPROM address map (byte address) for the SiS900. 777 */ 778 #define SIP_EEPROM_SIGNATURE 0x00 /* SiS 900 signature */ 779 #define SIP_EEPROM_MASK 0x02 /* `enable' mask */ 780 #define SIP_EEPROM_VENDOR_ID 0x04 /* PCI vendor ID */ 781 #define SIP_EEPROM_DEVICE_ID 0x06 /* PCI device ID */ 782 #define SIP_EEPROM_SUBVENDOR_ID 0x08 /* PCI subvendor ID */ 783 #define SIP_EEPROM_SUBSYSTEM_ID 0x0a /* PCI subsystem ID */ 784 #define SIP_EEPROM_PMC 0x0c /* PCI power management capabilities */ 785 #define SIP_EEPROM_reserved 0x0e /* reserved */ 786 #define SIP_EEPROM_ETHERNET_ID0 0x10 /* Ethernet address 0, 1 */ 787 #define SIP_EEPROM_ETHERNET_ID1 0x12 /* Ethernet address 2, 3 */ 788 #define SIP_EEPROM_ETHERNET_ID2 0x14 /* Ethernet address 4, 5 */ 789 #define SIP_EEPROM_CHECKSUM 0x16 /* checksum */ 790 791 /* 792 * Serial EEPROM data (byte addresses) for the DP83815. 793 */ 794 #define SIP_DP83815_EEPROM_CHECKSUM 0x16 /* checksum */ 795 #define SIP_DP83815_EEPROM_LENGTH 0x18 /* length of EEPROM data */ 796 797 /* 798 * Serial EEPROM data (byte addresses) for the DP83820. 799 */ 800 #define SIP_DP83820_EEPROM_SUBSYSTEM_ID 0x00 /* PCI subsystem ID */ 801 #define SIP_DP83820_EEPROM_SUBVENDOR_ID 0x02 /* PCI subvendor ID */ 802 #define SIP_DP83820_EEPROM_CFGINT 0x04 /* PCI INT [31:16] */ 803 #define SIP_DP83820_EEPROM_CONFIG0 0x06 /* configuration word 0 */ 804 #define SIP_DP83820_EEPROM_CONFIG1 0x08 /* configuration word 1 */ 805 #define SIP_DP83820_EEPROM_CONFIG2 0x0a /* configuration word 2 */ 806 #define SIP_DP83820_EEPROM_CONFIG3 0x0c /* configuration word 3 */ 807 #define SIP_DP83820_EEPROM_SOPAS0 0x0e /* SecureOn [47:32] */ 808 #define SIP_DP83820_EEPROM_SOPAS1 0x10 /* SecureOn [31:16] */ 809 #define SIP_DP83820_EEPROM_SOPAS2 0x12 /* SecureOn [15:0] */ 810 #define SIP_DP83820_EEPROM_PMATCH0 0x14 /* MAC [47:32] */ 811 #define SIP_DP83820_EEPROM_PMATCH1 0x16 /* MAC [31:16] */ 812 #define SIP_DP83820_EEPROM_PMATCH2 0x18 /* MAC [15:0] */ 813 #define SIP_DP83820_EEPROM_CHECKSUM 0x1a /* checksum */ 814 #define SIP_DP83820_EEPROM_LENGTH 0x1c /* length of EEPROM data */ 815 816 #define DP83820_CONFIG2_CFG_EXT_125 (1U << 0) 817 #define DP83820_CONFIG2_CFG_M64ADDR (1U << 1) 818 #define DP83820_CONFIG2_CFG_DATA64_EN (1U << 2) 819 #define DP83820_CONFIG2_CFG_T64ADDR (1U << 3) 820 #define DP83820_CONFIG2_CFG_MWI_DIS (1U << 4) 821 #define DP83820_CONFIG2_CFG_MRM_DIS (1U << 5) 822 #define DP83820_CONFIG2_CFG_MODE_1000 (1U << 7) 823 #define DP83820_CONFIG2_CFG_TBI_EN (1U << 9) 824 825 #endif /* _DEV_PCI_IF_SIPREG_H_ */ 826
Indexes created Sat Sep 27 14:09:57 GMT 2025