if_sipreg.h revision 1.7
1 /* $NetBSD: if_sipreg.h,v 1.7 2001/05/18 02:03:54 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 #ifndef _DEV_PCI_IF_SIPREG_H_ 69 #define _DEV_PCI_IF_SIPREG_H_ 70 71 /* 72 * Register description for the Silicon Integrated Systems SiS 900, 73 * SiS 7016, National Semiconductor DP83815 10/100, and National 74 * Semiconduction DP83820 10/100/1000 PCI Ethernet controller. 75 * 76 * Written by Jason R. Thorpe for Network Computer, Inc. 77 */ 78 79 /* 80 * Transmit FIFO size. Used to compute the transmit drain threshold. 81 * 82 * The transmit FIFO is arranged as a 512 32-bit memory array. 83 */ 84 #define SIP_TXFIFO_SIZE (512 * 4) 85 86 /* 87 * The SiS900 uses a single descriptor format for both transmit 88 * and receive descriptor chains. 89 * 90 * Note the DP83820 can use 64-bit DMA addresses for link and bufptr. 91 * However, we do not yet support that. 92 * 93 * For transmit, buffers need not be aligned. For receive, buffers 94 * must be aligned to 4-byte (8-byte on DP83820) boundaries. 95 */ 96 struct sip_desc { 97 #ifdef DP83820 98 u_int32_t sipd_link; /* link to next descriptor */ 99 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 100 u_int32_t sipd_cmdsts; /* command/status word */ 101 u_int32_t sipd_extsts; /* extended status */ 102 #else 103 u_int32_t sipd_link; /* link to next descriptor */ 104 u_int32_t sipd_cmdsts; /* command/status word */ 105 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 106 #endif /* DP83820 */ 107 }; 108 109 /* 110 * CMDSTS bits common to transmit and receive. 111 */ 112 #define CMDSTS_OWN 0x80000000 /* owned by consumer */ 113 #define CMDSTS_MORE 0x40000000 /* more descriptors */ 114 #define CMDSTS_INTR 0x20000000 /* interrupt when ownership changes */ 115 #define CMDSTS_SUPCRC 0x10000000 /* suppress CRC */ 116 #define CMDSTS_OK 0x08000000 /* packet ok */ 117 #ifdef DP83820 118 #define CMDSTS_SIZE_MASK 0x0000ffff /* packet size */ 119 #else 120 #define CMDSTS_SIZE_MASK 0x000007ff /* packet size */ 121 #endif /* DP83820 */ 122 123 #define CMDSTS_SIZE(x) ((x) & CMDSTS_SIZE_MASK) 124 125 /* 126 * CMDSTS bits for transmit. 127 */ 128 #define CMDSTS_Tx_TXA 0x04000000 /* transmit abort */ 129 #define CMDSTS_Tx_TFU 0x02000000 /* transmit FIFO underrun */ 130 #define CMDSTS_Tx_CRS 0x01000000 /* carrier sense lost */ 131 #define CMDSTS_Tx_TD 0x00800000 /* transmit deferred */ 132 #define CMDSTS_Tx_ED 0x00400000 /* excessive deferral */ 133 #define CMDSTS_Tx_OWC 0x00200000 /* out of window collision */ 134 #define CMDSTS_Tx_EC 0x00100000 /* excessive collisions */ 135 #define CMDSTS_Tx_CCNT 0x000f0000 /* collision count */ 136 137 #define CMDSTS_COLLISIONS(x) (((x) & CMDSTS_Tx_CCNT) >> 16) 138 139 /* 140 * CMDSTS bits for receive. 141 */ 142 #define CMDSTS_Rx_RXA 0x04000000 /* receive abort */ 143 #define CMDSTS_Rx_RXO 0x02000000 /* receive overrun */ 144 #define CMDSTS_Rx_DEST 0x01800000 /* destination class */ 145 #define CMDSTS_Rx_LONG 0x00400000 /* packet too long */ 146 #define CMDSTS_Rx_RUNT 0x00200000 /* runt packet */ 147 #define CMDSTS_Rx_ISE 0x00100000 /* invalid symbol error */ 148 #define CMDSTS_Rx_CRCE 0x00080000 /* CRC error */ 149 #define CMDSTS_Rx_FAE 0x00040000 /* frame alignment error */ 150 #define CMDSTS_Rx_LBP 0x00020000 /* loopback packet */ 151 #ifdef DP83820 152 #define CMDSTS_Rx_IRL 0x00010000 /* in-range length error */ 153 #else 154 #define CMDSTS_Rx_COL 0x00010000 /* collision activity */ 155 #endif /* DP83820 */ 156 157 #define CMDSTS_Rx_DEST_REJ 0x00000000 /* packet rejected */ 158 #define CMDSTS_Rx_DEST_STA 0x00800000 /* matched station address */ 159 #define CMDSTS_Rx_DEST_MUL 0x01000000 /* multicast address */ 160 #define CMDSTS_Rx_DEST_BRD 0x01800000 /* broadcast address */ 161 162 #ifdef DP83820 163 /* 164 * EXTSTS bits. 165 */ 166 #define EXTSTS_Rx_UDPERR 0x00400000 /* UDP checksum error */ 167 #define EXTSTS_UDPPKT 0x00200000 /* perform UDP checksum */ 168 #define EXTSTS_Rx_TCPERR 0x00100000 /* TCP checksum error */ 169 #define EXTSTS_TCPPKT 0x00080000 /* perform TCP checksum */ 170 #define EXTSTS_Rx_IPERR 0x00040000 /* IP header checksum error */ 171 #define EXTSTS_IPPKT 0x00020000 /* perform IP header checksum */ 172 #define EXTSTS_VPKT 0x00010000 /* insert VLAN tag */ 173 #define EXTSTS_VTCI 0x0000ffff /* VLAN tag control information */ 174 #endif /* DP83820 */ 175 176 /* 177 * PCI Configuration space registers. 178 */ 179 #define SIP_PCI_CFGIOA (PCI_MAPREG_START + 0x00) 180 181 #define SIP_PCI_CFGMA (PCI_MAPREG_START + 0x04) 182 183 #ifdef DP83820 184 #define SIP_PCI_CFGMA1 (PCI_MAPREG_START + 0x08) 185 #endif /* DP83820 */ 186 187 #define SIP_PCI_CFGEROMA 0x30 /* expansion ROM address */ 188 189 #define SIP_PCI_CFGPMC 0x40 /* power management cap. */ 190 191 #define SIP_PCI_CFGPMCSR 0x44 /* power management ctl. */ 192 193 /* 194 * MAC Operation Registers 195 */ 196 #define SIP_CR 0x00 /* command register */ 197 #ifdef DP83820 198 #define CR_RXPRI3 0x00010000 /* Rx priority queue select */ 199 #define CR_RXPRI2 0x00008000 /* Rx priority queue select */ 200 #define CR_RXPRI1 0x00004000 /* Rx priority queue select */ 201 #define CR_RXPRI0 0x00002000 /* Rx priority queue select */ 202 #define CR_TXPRI3 0x00001000 /* Tx priority queue select */ 203 #define CR_TXPRI2 0x00000800 /* Tx priority queue select */ 204 #define CR_TXPRI1 0x00000400 /* Tx priority queue select */ 205 #define CR_TXPRI0 0x00000200 /* Tx priority queue select */ 206 #endif /* DP83820 */ 207 #define CR_RST 0x00000100 /* software reset */ 208 #define CR_SWI 0x00000080 /* software interrupt */ 209 #define CR_RXR 0x00000020 /* receiver reset */ 210 #define CR_TXR 0x00000010 /* transmit reset */ 211 #define CR_RXD 0x00000008 /* receiver disable */ 212 #define CR_RXE 0x00000004 /* receiver enable */ 213 #define CR_TXD 0x00000002 /* transmit disable */ 214 #define CR_TXE 0x00000001 /* transmit enable */ 215 216 #define SIP_CFG 0x04 /* configuration register */ 217 #define CFG_LNKSTS 0x80000000 /* link status (83815) */ 218 #ifdef DP83820 219 #define CFG_SPEED1000 0x40000000 /* 1000Mb/s input pin */ 220 #define CFG_SPEED100 0x20000000 /* 100Mb/s input pin */ 221 #define CFG_DUPSTS 0x10000000 /* full-duplex status */ 222 #define CFG_TBI_EN 0x01000000 /* ten-bit interface enable */ 223 #define CFG_MODE_1000 0x00400000 /* 1000Mb/s mode enable */ 224 #define CFG_PINT_DUP 0x00100000 /* interrupt on PHY DUP change */ 225 #define CFG_PINT_LNK 0x00080000 /* interrupt on PHY LNK change */ 226 #define CFG_PINT_SPD 0x00040000 /* interrupt on PHY SPD change */ 227 #define CFG_TMRTEST 0x00020000 /* timer test mode */ 228 #define CFG_MRM_DIS 0x00010000 /* MRM disable */ 229 #define CFG_MWI_DIS 0x00008000 /* MWI disable */ 230 #define CFG_T64ADDR 0x00004000 /* target 64-bit addressing enable */ 231 #define CFG_PCI64_DET 0x00002000 /* 64-bit PCI bus detected */ 232 #define CFG_DATA64_EN 0x00001000 /* 64-bit data enable */ 233 #define CFG_M64ADDR 0x00000800 /* master 64-bit addressing enable */ 234 #else 235 #define CFG_SPEED100 0x40000000 /* 100Mb/s (83815) */ 236 #define CFG_FDUP 0x20000000 /* full duplex (83815) */ 237 #define CFG_POL 0x10000000 /* 10Mb/s polarity (83815) */ 238 #define CFG_ANEG_DN 0x08000000 /* autonegotiation done (83815) */ 239 #define CFG_PHY_CFG 0x00fc0000 /* PHY configuration (83815) */ 240 #define CFG_PINT_ACEN 0x00020000 /* PHY interrupt auto clear (83815) */ 241 #define CFG_PAUSE_ADV 0x00010000 /* pause advertise (83815) */ 242 #define CFG_ANEG_SEL 0x0000e000 /* autonegotiation select (83815) */ 243 #endif /* DP83820 */ 244 #define CFG_PHY_RST 0x00000400 /* PHY reset (83815) */ 245 #define CFG_PHY_DIS 0x00000200 /* PHY disable (83815) */ 246 #ifdef DP83820 247 #define CFG_EXTSTS_EN 0x00000100 /* extended status enable */ 248 #else 249 #define CFG_EUPHCOMP 0x00000100 /* 83810 descriptor compat (83815) */ 250 #endif /* DP83820 */ 251 #define CFG_REQALG 0x00000080 /* PCI bus request alg. */ 252 #define CFG_SB 0x00000040 /* single backoff */ 253 #define CFG_POW 0x00000020 /* program out of window timer */ 254 #define CFG_EXD 0x00000010 /* excessive defferal timer disable */ 255 #define CFG_PESEL 0x00000008 /* parity error detection action */ 256 #ifdef DP83820 257 #define CFG_BROM_DIS 0x00000004 /* boot ROM disable */ 258 #define CFG_EXT_125 0x00000002 /* external 125MHz reference select */ 259 #endif /* DP83820 */ 260 #define CFG_BEM 0x00000001 /* big-endian mode */ 261 262 #define SIP_EROMAR 0x08 /* EEPROM access register */ 263 #ifdef DP83820 264 #define EROMAR_MDC 0x00000040 /* MII clock */ 265 #define EROMAR_MDDIR 0x00000020 /* MII direction (1 == MAC->PHY) */ 266 #define EROMAR_MDIO 0x00000010 /* MII data */ 267 #endif /* DP83820 */ 268 #define EROMAR_EECS 0x00000008 /* chip select */ 269 #define EROMAR_EESK 0x00000004 /* clock */ 270 #define EROMAR_EEDO 0x00000002 /* data out */ 271 #define EROMAR_EEDI 0x00000001 /* data in */ 272 273 #define SIP_PTSCR 0x0c /* PCI test control register */ 274 #ifdef DP83820 275 #define PTSCR_RBIST_RST 0x00002000 /* SRAM BIST reset */ 276 #define PTSCR_RBIST_EN 0x00000400 /* SRAM BIST enable */ 277 #define PTSCR_RBIST_DONE 0x00000200 /* SRAM BIST done */ 278 #define PTSCR_RBIST_RX1FAIL 0x00000100 /* Rx status FIFO BIST fail */ 279 #define PTSCR_RBIST_RX0FAIL 0x00000080 /* Rx data FIFO BIST fail */ 280 #define PTSCR_RBIST_TX0FAIL 0x00000020 /* Tx data FIFO BIST fail */ 281 #define PTSCR_RBIST_HFFAIL 0x00000010 /* hash filter BIST fail */ 282 #define PTSCR_RBIST_RXFAIL 0x00000008 /* Rx filter BIST failed */ 283 #define PTSCR_EELOAD_EN 0x00000004 /* EEPROM load initiate */ 284 #define PTSCR_EEBIST_EN 0x00000002 /* EEPROM BIST enable */ 285 #define PTSCR_EEBIST_FAIL 0x00000001 /* EEPROM BIST failed */ 286 #else 287 #define PTSCR_DIS_TEST 0x40000000 /* discard timer test mode */ 288 #define PTSCR_EROM_TACC 0x0f000000 /* boot rom access time */ 289 #define PTSCR_TRRAMADR 0x001ff000 /* TX/RX RAM address */ 290 #define PTSCR_BMTEN 0x00000200 /* bus master test enable */ 291 #define PTSCR_RRTMEN 0x00000080 /* receive RAM test mode enable */ 292 #define PTSCR_TRTMEN 0x00000040 /* transmit RAM test mode enable */ 293 #define PTSCR_SRTMEN 0x00000020 /* status RAM test mode enable */ 294 #define PTSCR_SRAMADR 0x0000001f /* status RAM address */ 295 #endif /* DP83820 */ 296 297 #define SIP_ISR 0x10 /* interrupt status register */ 298 #ifdef DP83820 299 #define ISR_TXDESC3 0x40000000 /* Tx queue 3 */ 300 #define ISR_TXDESC2 0x20000000 /* Tx queue 2 */ 301 #define ISR_TXDESC1 0x10000000 /* Tx queue 1 */ 302 #define ISR_TXDESC0 0x08000000 /* Tx queue 0 */ 303 #define ISR_RXDESC3 0x04000000 /* Rx queue 3 */ 304 #define ISR_RXDESC2 0x02000000 /* Rx queue 2 */ 305 #define ISR_RXDESC1 0x01000000 /* Rx queue 1 */ 306 #define ISR_RXDESC0 0x00800000 /* Rx queue 0 */ 307 #define ISR_TXRCMP 0x00400000 /* transmit reset complete */ 308 #define ISR_RXRCMP 0x00200000 /* receive reset complete */ 309 #define ISR_DPERR 0x00100000 /* detected parity error */ 310 #define ISR_SSERR 0x00080000 /* signalled system error */ 311 #define ISR_RMABT 0x00040000 /* received master abort */ 312 #define ISR_RTABT 0x00020000 /* received target abort */ 313 #else 314 #define ISR_WAKEEVT 0x10000000 /* wake up event */ 315 #define ISR_PAUSE_END 0x08000000 /* end of transmission pause */ 316 #define ISR_PAUSE_ST 0x04000000 /* start of transmission pause */ 317 #define ISR_TXRCMP 0x02000000 /* transmit reset complete */ 318 #define ISR_RXRCMP 0x01000000 /* receive reset complete */ 319 #define ISR_DPERR 0x00800000 /* detected parity error */ 320 #define ISR_SSERR 0x00400000 /* signalled system error */ 321 #define ISR_RMABT 0x00200000 /* received master abort */ 322 #define ISR_RTABT 0x00100000 /* received target abort */ 323 #endif /* DP83820 */ 324 #define ISR_RXSOVR 0x00010000 /* Rx status FIFO overrun */ 325 #define ISR_HIBERR 0x00008000 /* high bits error set */ 326 #ifdef DP83820 327 #define ISR_PHY 0x00004000 /* PHY interrupt */ 328 #define ISR_PME 0x00002000 /* power management event */ 329 #endif /* DP83820 */ 330 #define ISR_SWI 0x00001000 /* software interrupt */ 331 #ifdef DP83820 332 #define ISR_MIB 0x00000800 /* MIB service */ 333 #endif /* DP83820 */ 334 #define ISR_TXURN 0x00000400 /* Tx underrun */ 335 #define ISR_TXIDLE 0x00000200 /* Tx idle */ 336 #define ISR_TXERR 0x00000100 /* Tx error */ 337 #define ISR_TXDESC 0x00000080 /* Tx descriptor interrupt */ 338 #define ISR_TXOK 0x00000040 /* Tx okay */ 339 #define ISR_RXORN 0x00000020 /* Rx overrun */ 340 #define ISR_RXIDLE 0x00000010 /* Rx idle */ 341 #define ISR_RXEARLY 0x00000008 /* Rx early */ 342 #define ISR_RXERR 0x00000004 /* Rx error */ 343 #define ISR_RXDESC 0x00000002 /* Rx descriptor interrupt */ 344 #define ISR_RXOK 0x00000001 /* Rx okay */ 345 346 #define SIP_IMR 0x14 /* interrupt mask register */ 347 /* See bits in SIP_ISR */ 348 349 #define SIP_IER 0x18 /* interrupt enable register */ 350 #define IER_IE 0x00000001 /* master interrupt enable */ 351 352 #ifdef DP83820 353 #define SIP_IHR 0x1c /* interrupt hold-off register */ 354 #define IHR_IHCTL 0x00000100 /* interrupt hold-off control */ 355 #define IHR_IH 0x000000ff /* interrupt hold-off timer (100us) */ 356 #else 357 #define SIP_ENPHY 0x1c /* enhanced PHY access register */ 358 #define ENPHY_PHYDATA 0xffff0000 /* PHY data */ 359 #define ENPHY_DATA_SHIFT 16 360 #define ENPHY_PHYADDR 0x0000f800 /* PHY number (7016 only) */ 361 #define ENPHY_PHYADDR_SHIFT 11 362 #define ENPHY_REGADDR 0x000007c0 /* PHY register */ 363 #define ENPHY_REGADDR_SHIFT 6 364 #define ENPHY_RWCMD 0x00000020 /* 1 == read, 0 == write */ 365 #define ENPHY_ACCESS 0x00000010 /* PHY access enable */ 366 #endif /* DP83820 */ 367 368 #define SIP_TXDP 0x20 /* transmit descriptor pointer reg */ 369 370 #ifdef DP83820 371 #define SIP_TXDP_HI 0x24 /* transmit descriptor pointer (high) reg */ 372 #endif /* DP83820 */ 373 374 #ifdef DP83820 375 #define SIP_TXCFG 0x28 /* transmit configuration register */ 376 #else 377 #define SIP_TXCFG 0x24 /* transmit configuration register */ 378 #endif /* DP83820 */ 379 #define TXCFG_CSI 0x80000000 /* carrier sense ignore */ 380 #define TXCFG_HBI 0x40000000 /* heartbeat ignore */ 381 #define TXCFG_MLB 0x20000000 /* MAC loopback */ 382 #define TXCFG_ATP 0x10000000 /* automatic transmit padding */ 383 #ifdef DP83820 384 #define TXCFG_ECRETRY 0x008000000 /* excessive collision retry enable */ 385 #define TXCFG_MXDMA 0x00700000 /* max DMA burst size */ 386 #define TXCFG_MXDMA_1024 0x00000000 /* 1024 bytes */ 387 #define TXCFG_MXDMA_8 0x00100000 /* 8 bytes */ 388 #define TXCFG_MXDMA_16 0x00200000 /* 16 bytes */ 389 #define TXCFG_MXDMA_32 0x00300000 /* 32 bytes */ 390 #define TXCFG_MXDMA_64 0x00400000 /* 64 bytes */ 391 #define TXCFG_MXDMA_128 0x00500000 /* 128 bytes */ 392 #define TXCFG_MXDMA_256 0x00600000 /* 256 bytes */ 393 #define TXCFG_MXDMA_512 0x00700000 /* 512 bytes */ 394 #define TXCFG_BRST_DIS 0x00080000 /* 1000Mb/s burst disable */ 395 #define TXCFG_FLTH 0x0000ff00 /* Fx fill threshold */ 396 #define TXCFG_FLTH_SHIFT 8 397 #define TXCFG_DRTH 0x000000ff /* Tx drain threshold */ 398 #else 399 #define TXCFG_MXDMA 0x00700000 /* max DMA burst size */ 400 #define TXCFG_MXDMA_512 0x00000000 /* 512 bytes */ 401 #define TXCFG_MXDMA_4 0x00100000 /* 4 bytes */ 402 #define TXCFG_MXDMA_8 0x00200000 /* 8 bytes */ 403 #define TXCFG_MXDMA_16 0x00300000 /* 16 bytes */ 404 #define TXCFG_MXDMA_32 0x00400000 /* 32 bytes */ 405 #define TXCFG_MXDMA_64 0x00500000 /* 64 bytes */ 406 #define TXCFG_MXDMA_128 0x00600000 /* 128 bytes */ 407 #define TXCFG_MXDMA_256 0x00700000 /* 256 bytes */ 408 #define TXCFG_FLTH 0x00003f00 /* Tx fill threshold */ 409 #define TXCFG_FLTH_SHIFT 8 410 #define TXCFG_DRTH 0x0000003f /* Tx drain threshold */ 411 #endif /* DP83820 */ 412 413 #ifdef DP83820 414 #define SIP_GPIOR 0x2c /* general purpose i/o register */ 415 #define GPIOR_GP5_IN 0x00004000 /* GP 5 in */ 416 #define GPIOR_GP4_IN 0x00002000 /* GP 4 in */ 417 #define GPIOR_GP3_IN 0x00001000 /* GP 3 in */ 418 #define GPIOR_GP2_IN 0x00000800 /* GP 2 in */ 419 #define GPIOR_GP1_IN 0x00000400 /* GP 1 in */ 420 #define GPIOR_GP5_OE 0x00000200 /* GP 5 out enable */ 421 #define GPIOR_GP4_OE 0x00000100 /* GP 4 out enable */ 422 #define GPIOR_GP3_OE 0x00000080 /* GP 3 out enable */ 423 #define GPIOR_GP2_OE 0x00000040 /* GP 2 out enable */ 424 #define GPIOR_GP1_OE 0x00000020 /* GP 1 out enable */ 425 #define GPIOR_GP5_OUT 0x00000010 /* GP 5 out */ 426 #define GPIOR_GP4_OUT 0x00000008 /* GP 4 out */ 427 #define GPIOR_GP3_OUT 0x00000004 /* GP 3 out */ 428 #define GPIOR_GP2_OUT 0x00000002 /* GP 2 out */ 429 #define GPIOR_GP1_OUT 0x00000001 /* GP 1 out */ 430 #endif /* DP83820 */ 431 432 #define SIP_RXDP 0x30 /* receive descriptor pointer reg */ 433 434 #ifdef DP83820 435 #define SIP_RXDP_HI 0x34 /* receive descriptor pointer (high) reg */ 436 #endif /* DP83820 */ 437 438 #ifdef DP83820 439 #define SIP_RXCFG 0x38 /* receive configuration register */ 440 #else 441 #define SIP_RXCFG 0x34 /* receive configuration register */ 442 #endif 443 #define RXCFG_AEP 0x80000000 /* accept error packets */ 444 #define RXCFG_ARP 0x40000000 /* accept runt packets */ 445 #ifdef DP83820 446 #define RXCFG_STRIPCRC 0x20000000 /* strip CRC */ 447 #endif /* DP83820 */ 448 #define RXCFG_ATX 0x10000000 /* accept transmit packets */ 449 #define RXCFG_AJAB 0x08000000 /* accept jabber packets */ 450 #ifdef DP83820 451 #define RXCFG_AIRL 0x04000000 /* accept in-range length err packets */ 452 #define RXCFG_MXDMA 0x00700000 /* max DMA burst size */ 453 #define RXCFG_MXDMA_1024 0x00000000 /* 1024 bytes */ 454 #define RXCFG_MXDMA_8 0x00100000 /* 8 bytes */ 455 #define RXCFG_MXDMA_16 0x00200000 /* 16 bytes */ 456 #define RXCFG_MXDMA_32 0x00300000 /* 32 bytes */ 457 #define RXCFG_MXDMA_64 0x00400000 /* 64 bytes */ 458 #define RXCFG_MXDMA_128 0x00500000 /* 128 bytes */ 459 #define RXCFG_MXDMA_256 0x00600000 /* 256 bytes */ 460 #define RXCFG_MXDMA_512 0x00700000 /* 512 bytes */ 461 #else 462 #define RXCFG_MXDMA 0x00700000 /* max DMA burst size */ 463 #define RXCFG_MXDMA_512 0x00000000 /* 512 bytes */ 464 #define RXCFG_MXDMA_4 0x00100000 /* 4 bytes */ 465 #define RXCFG_MXDMA_8 0x00200000 /* 8 bytes */ 466 #define RXCFG_MXDMA_16 0x00300000 /* 16 bytes */ 467 #define RXCFG_MXDMA_32 0x00400000 /* 32 bytes */ 468 #define RXCFG_MXDMA_64 0x00500000 /* 64 bytes */ 469 #define RXCFG_MXDMA_128 0x00600000 /* 128 bytes */ 470 #define RXCFG_MXDMA_256 0x00700000 /* 256 bytes */ 471 #endif /* DP83820 */ 472 #define RXCFG_DRTH 0x0000003e 473 #define RXCFG_DRTH_SHIFT 1 474 475 #ifdef DP83820 476 #define SIP_PQCR 0x3c /* priority queueing control register */ 477 #define PQCR_RXPQ_4 0x0000000c /* 4 Rx queues */ 478 #define PQCR_RXPQ_3 0x00000008 /* 3 Rx queues */ 479 #define PQCR_RXPQ_2 0x00000004 /* 2 Rx queues */ 480 #define PQCR_TXFAIR 0x00000002 /* Tx fairness enable */ 481 #define PQCR_TXPQEN 0x00000001 /* Tx priority queueing enable */ 482 #else 483 #define SIP_FLOWCTL 0x38 /* flow control register */ 484 #define FLOWCTL_PAUSE 0x00000002 /* PAUSE flag */ 485 #define FLOWCTL_FLOWEN 0x00000001 /* enable flow control */ 486 487 #define SIP_NS_CCSR 0x3c /* CLKRUN control/status register (83815) */ 488 #define CCSR_PMESTS 0x00008000 /* PME status */ 489 #define CCSR_PMEEN 0x00000100 /* PME enable */ 490 #define CCSR_CLKRUN_EN 0x00000001 /* clkrun enable */ 491 #endif /* DP83820 */ 492 493 #define SIP_NS_WCSR 0x40 /* WoL control/status register (83815) */ 494 495 #define SIP_NS_PCR 0x44 /* pause control/status register (83815) */ 496 497 #define SIP_RFCR 0x48 /* receive filter control register */ 498 #define RFCR_RFEN 0x80000000 /* Rx filter enable */ 499 #define RFCR_AAB 0x40000000 /* accept all broadcast */ 500 #define RFCR_AAM 0x20000000 /* accept all multicast */ 501 #define RFCR_AAP 0x10000000 /* accept all physical */ 502 #define RFCR_APM 0x08000000 /* accept perfect match (83815) */ 503 #define RFCR_APAT 0x07800000 /* accept pattern match (83815) */ 504 #define RFCR_AARP 0x00400000 /* accept ARP (83815) */ 505 #define RFCR_MHEN 0x00200000 /* multicast hash enable (83815) */ 506 #define RFCR_UHEN 0x00100000 /* unicast hash enable (83815) */ 507 #define RFCR_ULM 0x00080000 /* U/L bit mask (83815) */ 508 #define RFCR_NS_RFADDR 0x000003ff /* Rx filter ext reg address (83815) */ 509 #define RFCR_RFADDR 0x000f0000 /* Rx filter address */ 510 #define RFCR_RFADDR_NODE0 0x00000000 /* node address 1, 0 */ 511 #define RFCR_RFADDR_NODE2 0x00010000 /* node address 3, 2 */ 512 #define RFCR_RFADDR_NODE4 0x00020000 /* node address 5, 4 */ 513 #define RFCR_RFADDR_MC0 0x00040000 /* multicast hash word 0 */ 514 #define RFCR_RFADDR_MC1 0x00050000 /* multicast hash word 1 */ 515 #define RFCR_RFADDR_MC2 0x00060000 /* multicast hash word 2 */ 516 #define RFCR_RFADDR_MC3 0x00070000 /* multicast hash word 3 */ 517 #define RFCR_RFADDR_MC4 0x00080000 /* multicast hash word 4 */ 518 #define RFCR_RFADDR_MC5 0x00090000 /* multicast hash word 5 */ 519 #define RFCR_RFADDR_MC6 0x000a0000 /* multicast hash word 6 */ 520 #define RFCR_RFADDR_MC7 0x000b0000 /* multicast hash word 7 */ 521 522 #define RFCR_NS_RFADDR_PMATCH0 0x0000 /* perfect match octets 1-0 */ 523 #define RFCR_NS_RFADDR_PMATCH2 0x0002 /* perfect match octets 3-2 */ 524 #define RFCR_NS_RFADDR_PMATCH4 0x0004 /* perfect match octets 5-4 */ 525 #define RFCR_NS_RFADDR_PCOUNT 0x0006 /* pattern count */ 526 #ifdef DP83820 527 #define RFCR_NS_RFADDR_PCOUNT2 0x0008 /* pattern count 2, 3 */ 528 #define RFCR_NS_RFADDR_SOPAS0 0x000a /* SecureOn 0, 1 */ 529 #define RFCR_NS_RFADDR_SOPAS2 0x000c /* SecureOn 2, 3 */ 530 #define RFCR_NS_RFADDR_SOPAS4 0x000e /* SecureOn 4, 5 */ 531 #define RFCR_NS_RFADDR_FILTMEM 0x0100 /* hash memory */ 532 #define RFCR_NS_RFADDR_PATMEM 0x0200 /* pattern memory */ 533 #else 534 #define RFCR_NS_RFADDR_FILTMEM 0x0200 /* filter memory (hash/pattern) */ 535 #endif /* DP83820 */ 536 537 #define SIP_RFDR 0x4c /* receive filter data register */ 538 #define RFDR_BMASK 0x00030000 /* byte mask (83815) */ 539 #define RFDR_DATA 0x0000ffff /* data bits */ 540 541 #define SIP_NS_BRAR 0x50 /* boot rom address (83815) */ 542 #define BRAR_AUTOINC 0x80000000 /* autoincrement */ 543 #define BRAR_ADDR 0x0000ffff /* address */ 544 545 #define SIP_NS_BRDR 0x54 /* boot rom data (83815) */ 546 547 #define SIP_NS_SRR 0x58 /* silicon revision register (83815) */ 548 #ifdef DP83820 549 #define SRR_REV_B 0x00000103 550 #else 551 #define SRR_REV_A 0x00000101 552 #define SRR_REV_B_1 0x00000200 553 #define SRR_REV_B_2 0x00000201 554 #define SRR_REV_B_3 0x00000203 555 #define SRR_REV_C_1 0x00000300 556 #define SRR_REV_C_2 0x00000302 557 #endif /* DP83820 */ 558 559 #define SIP_NS_MIBC 0x5c /* mib control register (83815) */ 560 #define MIBC_MIBS 0x00000008 /* mib counter strobe */ 561 #define MIBC_ACLR 0x00000004 /* clear all counters */ 562 #define MIBC_FRZ 0x00000002 /* freeze all counters */ 563 #define MIBC_WRN 0x00000001 /* warning test indicator */ 564 565 #define SIP_NS_MIB(mibreg) /* mib data registers (83815) */ \ 566 (0x60 + (mibreg)) 567 #define MIB_RXErroredPkts 0x00 568 #define MIB_RXFCSErrors 0x04 569 #define MIB_RXMsdPktErrors 0x08 570 #define MIB_RXFAErrors 0x0c 571 #define MIB_RXSymbolErrors 0x10 572 #define MIB_RXFrameTooLong 0x14 573 #ifdef DP83820 574 #define MIB_RXIRLErrors 0x18 575 #define MIB_RXBadOpcodes 0x1c 576 #define MIB_RXPauseFrames 0x20 577 #define MIB_TXPauseFrames 0x24 578 #define MIB_TXSQEErrors 0x28 579 #else 580 #define MIB_RXTXSQEErrors 0x18 581 #endif /* DP83820 */ 582 583 #ifndef DP83820 584 #define SIP_NS_PHY(miireg) /* PHY registers (83815) */ \ 585 (0x80 + ((miireg) << 2)) 586 #endif 587 588 #ifdef DP83820 589 #define SIP_TXDP1 0xa0 /* transmit descriptor pointer (pri 1) */ 590 591 #define SIP_TXDP2 0xa4 /* transmit descriptor pointer (pri 2) */ 592 593 #define SIP_TXDP3 0xa8 /* transmit descriptor pointer (pri 3) */ 594 595 #define SIP_RXDP1 0xb0 /* receive descriptor pointer (pri 1) */ 596 597 #define SIP_RXDP2 0xb4 /* receive descriptor pointer (pri 2) */ 598 599 #define SIP_RXDP3 0xb8 /* receive descriptor pointer (pri 3) */ 600 601 #define SIP_VRCR 0xbc /* VLAN/IP receive control register */ 602 #define VRCR_RUDPE 0x00000080 /* reject UDP checksum errors */ 603 #define VRCR_RTCPE 0x00000040 /* reject TCP checksum errors */ 604 #define VRCR_RIPE 0x00000020 /* reject IP checksum errors */ 605 #define VRCR_IPEN 0x00000010 /* IP checksum enable */ 606 #define VRCR_DUTF 0x00000008 /* discard untagged frames */ 607 #define VRCR_DVTF 0x00000004 /* discard VLAN tagged frames */ 608 #define VRCR_VTREN 0x00000002 /* VLAN tag removal enable */ 609 #define VRCR_VTDEN 0x00000001 /* VLAN tag detection enable */ 610 611 #define SIP_VTCR 0xc0 /* VLAN/IP transmit control register */ 612 #define VTCR_PPCHK 0x00000008 /* per-packet checksum generation */ 613 #define VTCR_GCHK 0x00000004 /* global checksum generation */ 614 #define VTCR_VPPTI 0x00000002 /* VLAN per-packet tag insertion */ 615 #define VTCR_VGTI 0x00000001 /* VLAN global tag insertion */ 616 617 #define SIP_VDR 0xc4 /* VLAN data register */ 618 #define VDR_VTCI 0xffff0000 /* VLAN tag control information */ 619 #define VDR_VTYPE 0x0000ffff /* VLAN type field */ 620 621 #define SIP_NS_CCSR 0xcc /* CLKRUN control/status register (83815) */ 622 #define CCSR_PMESTS 0x00008000 /* PME status */ 623 #define CCSR_PMEEN 0x00000100 /* PME enable */ 624 #define CCSR_CLKRUN_EN 0x00000001 /* clkrun enable */ 625 626 #define SIP_TBICR 0xe0 /* TBI control register */ 627 #define TBICR_MR_LOOPBACK 0x00004000 /* TBI PCS loopback enable */ 628 #define TBICR_MR_AN_ENABLE 0x00001000 /* TBI autonegotiation enable */ 629 #define TBICR_MR_RESTART_AN 0x00000200 /* restart TBI autoneogtiation */ 630 631 #define SIP_TBISR 0xe4 /* TBI status register */ 632 #define TBISR_MR_LINK_STATUS 0x00000020 /* TBI link status */ 633 #define TBISR_MR_AN_COMPLETE 0x00000004 /* TBI autonegotiation complete */ 634 635 #define SIP_TANAR 0xe8 /* TBI autoneg adv. register */ 636 #define TANAR_NP 0x00008000 /* next page exchange required */ 637 #define TANAR_RF2 0x00002000 /* remote fault 2 */ 638 #define TANAR_RF1 0x00001000 /* remote fault 1 */ 639 #define TANAR_PS2 0x00000100 /* pause encoding 2 */ 640 #define TANAR_PS1 0x00000080 /* pause encoding 1 */ 641 #define TANAR_HALF_DUP 0x00000040 /* adv. half duplex */ 642 #define TANAR_FULL_DUP 0x00000020 /* adv. full duplex */ 643 644 #define SIP_TANLPAR 0xec /* TBI autoneg link partner ability register */ 645 /* See TANAR bits */ 646 647 #define SIP_TANER 0xf0 /* TBI autoneg expansion register */ 648 #define TANER_NPA 0x00000004 /* we support next page function */ 649 #define TANER_PR 0x00000002 /* page received from link partner */ 650 651 #define SIP_TESR 0xf4 /* TBI extended status register */ 652 #define TESR_1000FDX 0x00008000 /* we support 1000base FDX */ 653 #define TESR_1000HDX 0x00004000 /* we support 1000base HDX */ 654 #else 655 #define SIP_PMCTL 0xb0 /* power management control register */ 656 #define PMCTL_GATECLK 0x80000000 /* gate dual clock enable */ 657 #define PMCTL_WAKEALL 0x40000000 /* wake on all Rx OK */ 658 #define PMCTL_FRM3ACS 0x04000000 /* 3rd wake-up frame access */ 659 #define PMCTL_FRM2ACS 0x02000000 /* 2nd wake-up frame access */ 660 #define PMCTL_FRM1ACS 0x01000000 /* 1st wake-up frame access */ 661 #define PMCTL_FRM3EN 0x00400000 /* 3rd wake-up frame match enable */ 662 #define PMCTL_FRM2EN 0x00200000 /* 2nd wake-up frame match enable */ 663 #define PMCTL_FRM1EN 0x00100000 /* 1st wake-up frame match enable */ 664 #define PMCTL_ALGORITHM 0x00000800 /* Magic Packet match algorithm */ 665 #define PMCTL_MAGICPKT 0x00000400 /* Magic Packet match enable */ 666 #define PMCTL_LINKON 0x00000002 /* link on monitor enable */ 667 #define PMCTL_LINKLOSS 0x00000001 /* link loss monitor enable */ 668 669 #define SIP_PMEVT 0xb4 /* power management wake-up evnt reg */ 670 #define PMEVT_ALLFRMMAT 0x40000000 /* receive packet ok */ 671 #define PMEVT_FRM3MAT 0x04000000 /* match 3rd wake-up frame */ 672 #define PMEVT_FRM2MAT 0x02000000 /* match 2nd wake-up frame */ 673 #define PMEVT_FRM1MAT 0x01000000 /* match 1st wake-up frame */ 674 #define PMEVT_MAGICPKT 0x00000400 /* Magic Packet */ 675 #define PMEVT_ONEVT 0x00000002 /* link on event */ 676 #define PMEVT_LOSSEVT 0x00000001 /* link loss event */ 677 678 #define SIP_WAKECRC 0xbc /* wake-up frame CRC register */ 679 680 #define SIP_WAKEMASK0 0xc0 /* wake-up frame mask registers */ 681 #define SIP_WAKEMASK1 0xc4 682 #define SIP_WAKEMASK2 0xc8 683 #define SIP_WAKEMASK3 0xcc 684 #define SIP_WAKEMASK4 0xe0 685 #define SIP_WAKEMASK5 0xe4 686 #define SIP_WAKEMASK6 0xe8 687 #define SIP_WAKEMASK7 0xec 688 #endif /* DP83820 */ 689 690 /* 691 * Serial EEPROM opcodes, including the start bit. 692 */ 693 #define SIP_EEPROM_OPC_ERASE 0x04 694 #define SIP_EEPROM_OPC_WRITE 0x05 695 #define SIP_EEPROM_OPC_READ 0x06 696 697 /* 698 * Serial EEPROM address map (byte address) for the SiS900. 699 */ 700 #define SIP_EEPROM_SIGNATURE 0x00 /* SiS 900 signature */ 701 #define SIP_EEPROM_MASK 0x02 /* `enable' mask */ 702 #define SIP_EEPROM_VENDOR_ID 0x04 /* PCI vendor ID */ 703 #define SIP_EEPROM_DEVICE_ID 0x06 /* PCI device ID */ 704 #define SIP_EEPROM_SUBVENDOR_ID 0x08 /* PCI subvendor ID */ 705 #define SIP_EEPROM_SUBSYSTEM_ID 0x0a /* PCI subsystem ID */ 706 #define SIP_EEPROM_PMC 0x0c /* PCI power management capabilities */ 707 #define SIP_EEPROM_reserved 0x0e /* reserved */ 708 #define SIP_EEPROM_ETHERNET_ID0 0x10 /* Ethernet address 0, 1 */ 709 #define SIP_EEPROM_ETHERNET_ID1 0x12 /* Ethernet address 2, 3 */ 710 #define SIP_EEPROM_ETHERNET_ID2 0x14 /* Ethernet address 4, 5 */ 711 #define SIP_EEPROM_CHECKSUM 0x16 /* checksum */ 712 713 /* 714 * Serial EEPROM data (byte addresses) for the DP83815. 715 */ 716 #define SIP_DP83815_EEPROM_CHECKSUM 0x16 /* checksum */ 717 #define SIP_DP83815_EEPROM_LENGTH 0x18 /* length of EEPROM data */ 718 719 /* 720 * Serial EEPROM data (byte addresses) for the DP83820. 721 */ 722 #define SIP_DP83820_EEPROM_SUBSYSTEM_ID 0x00 /* PCI subsystem ID */ 723 #define SIP_DP83820_EEPROM_SUBVENDOR_ID 0x02 /* PCI subvendor ID */ 724 #define SIP_DP83820_EEPROM_CFGINT 0x04 /* PCI INT [31:16] */ 725 #define SIP_DP83820_EEPROM_SOPAS0 0x0e /* SecureOn [47:32] */ 726 #define SIP_DP83820_EEPROM_SOPAS1 0x10 /* SecureOn [31:16] */ 727 #define SIP_DP83820_EEPROM_SOPAS2 0x12 /* SecureOn [15:0] */ 728 #define SIP_DP83820_EEPROM_PMATCH0 0x14 /* MAC [47:32] */ 729 #define SIP_DP83820_EEPROM_PMATCH1 0x16 /* MAC [31:16] */ 730 #define SIP_DP83820_EEPROM_PMATCH2 0x18 /* MAC [15:0] */ 731 #define SIP_DP83820_EEPROM_CHECKSUM 0x1a /* checksum */ 732 #define SIP_DP83820_EEPROM_LENGTH 0x1c /* length of EEPROM data */ 733 734 #endif /* _DEV_PCI_IF_SIPREG_H_ */ 735
Indexes created Wed Sep 24 14:09:57 GMT 2025