if_sk.c revision 1.10.2.10
1 1.10.2.10 christos /* $NetBSD: if_sk.c,v 1.10.2.10 2005/12/11 10:28:58 christos Exp $ */ 2 1.10.2.2 skrll 3 1.10.2.2 skrll /*- 4 1.10.2.2 skrll * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 1.10.2.2 skrll * All rights reserved. 6 1.10.2.2 skrll * 7 1.10.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.10.2.2 skrll * modification, are permitted provided that the following conditions 9 1.10.2.2 skrll * are met: 10 1.10.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.10.2.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.10.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.10.2.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.10.2.2 skrll * documentation and/or other materials provided with the distribution. 15 1.10.2.2 skrll * 3. All advertising materials mentioning features or use of this software 16 1.10.2.2 skrll * must display the following acknowledgement: 17 1.10.2.2 skrll * This product includes software developed by the NetBSD 18 1.10.2.2 skrll * Foundation, Inc. and its contributors. 19 1.10.2.2 skrll * 4. Neither the name of The NetBSD Foundation nor the names of its 20 1.10.2.2 skrll * contributors may be used to endorse or promote products derived 21 1.10.2.2 skrll * from this software without specific prior written permission. 22 1.10.2.2 skrll * 23 1.10.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 1.10.2.2 skrll * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 1.10.2.2 skrll * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 1.10.2.2 skrll * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 1.10.2.2 skrll * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 1.10.2.2 skrll * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 1.10.2.2 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 1.10.2.2 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 1.10.2.2 skrll * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 1.10.2.2 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 1.10.2.2 skrll * POSSIBILITY OF SUCH DAMAGE. 34 1.10.2.2 skrll */ 35 1.10.2.2 skrll 36 1.10.2.2 skrll /* $OpenBSD: if_sk.c,v 1.33 2003/08/12 05:23:06 nate Exp $ */ 37 1.10.2.2 skrll 38 1.10.2.2 skrll /* 39 1.10.2.2 skrll * Copyright (c) 1997, 1998, 1999, 2000 40 1.10.2.2 skrll * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 41 1.10.2.2 skrll * 42 1.10.2.2 skrll * Redistribution and use in source and binary forms, with or without 43 1.10.2.2 skrll * modification, are permitted provided that the following conditions 44 1.10.2.2 skrll * are met: 45 1.10.2.2 skrll * 1. Redistributions of source code must retain the above copyright 46 1.10.2.2 skrll * notice, this list of conditions and the following disclaimer. 47 1.10.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 48 1.10.2.2 skrll * notice, this list of conditions and the following disclaimer in the 49 1.10.2.2 skrll * documentation and/or other materials provided with the distribution. 50 1.10.2.2 skrll * 3. All advertising materials mentioning features or use of this software 51 1.10.2.2 skrll * must display the following acknowledgement: 52 1.10.2.2 skrll * This product includes software developed by Bill Paul. 53 1.10.2.2 skrll * 4. Neither the name of the author nor the names of any co-contributors 54 1.10.2.2 skrll * may be used to endorse or promote products derived from this software 55 1.10.2.2 skrll * without specific prior written permission. 56 1.10.2.2 skrll * 57 1.10.2.2 skrll * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 58 1.10.2.2 skrll * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 1.10.2.2 skrll * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 1.10.2.2 skrll * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 61 1.10.2.2 skrll * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 1.10.2.2 skrll * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 1.10.2.2 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 1.10.2.2 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 1.10.2.2 skrll * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 1.10.2.2 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 67 1.10.2.2 skrll * THE POSSIBILITY OF SUCH DAMAGE. 68 1.10.2.2 skrll * 69 1.10.2.2 skrll * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 70 1.10.2.2 skrll */ 71 1.10.2.2 skrll 72 1.10.2.2 skrll /* 73 1.10.2.2 skrll * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 74 1.10.2.2 skrll * 75 1.10.2.2 skrll * Permission to use, copy, modify, and distribute this software for any 76 1.10.2.2 skrll * purpose with or without fee is hereby granted, provided that the above 77 1.10.2.2 skrll * copyright notice and this permission notice appear in all copies. 78 1.10.2.2 skrll * 79 1.10.2.2 skrll * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 80 1.10.2.2 skrll * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 81 1.10.2.2 skrll * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 82 1.10.2.2 skrll * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 83 1.10.2.2 skrll * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 84 1.10.2.2 skrll * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 85 1.10.2.2 skrll * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 86 1.10.2.2 skrll */ 87 1.10.2.2 skrll 88 1.10.2.2 skrll /* 89 1.10.2.2 skrll * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 90 1.10.2.2 skrll * the SK-984x series adapters, both single port and dual port. 91 1.10.2.2 skrll * References: 92 1.10.2.2 skrll * The XaQti XMAC II datasheet, 93 1.10.2.2 skrll * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 1.10.2.2 skrll * The SysKonnect GEnesis manual, http://www.syskonnect.com 95 1.10.2.2 skrll * 96 1.10.2.2 skrll * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 97 1.10.2.2 skrll * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 98 1.10.2.2 skrll * convenience to others until Vitesse corrects this problem: 99 1.10.2.2 skrll * 100 1.10.2.2 skrll * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 101 1.10.2.2 skrll * 102 1.10.2.2 skrll * Written by Bill Paul <wpaul (at) ee.columbia.edu> 103 1.10.2.2 skrll * Department of Electrical Engineering 104 1.10.2.2 skrll * Columbia University, New York City 105 1.10.2.2 skrll */ 106 1.10.2.2 skrll 107 1.10.2.2 skrll /* 108 1.10.2.2 skrll * The SysKonnect gigabit ethernet adapters consist of two main 109 1.10.2.2 skrll * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 110 1.10.2.2 skrll * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 111 1.10.2.2 skrll * components and a PHY while the GEnesis controller provides a PCI 112 1.10.2.2 skrll * interface with DMA support. Each card may have between 512K and 113 1.10.2.2 skrll * 2MB of SRAM on board depending on the configuration. 114 1.10.2.2 skrll * 115 1.10.2.2 skrll * The SysKonnect GEnesis controller can have either one or two XMAC 116 1.10.2.2 skrll * chips connected to it, allowing single or dual port NIC configurations. 117 1.10.2.2 skrll * SysKonnect has the distinction of being the only vendor on the market 118 1.10.2.2 skrll * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 119 1.10.2.2 skrll * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 120 1.10.2.2 skrll * XMAC registers. This driver takes advantage of these features to allow 121 1.10.2.2 skrll * both XMACs to operate as independent interfaces. 122 1.10.2.2 skrll */ 123 1.10.2.8 skrll 124 1.10.2.2 skrll #include "bpfilter.h" 125 1.10.2.2 skrll 126 1.10.2.2 skrll #include <sys/param.h> 127 1.10.2.2 skrll #include <sys/systm.h> 128 1.10.2.2 skrll #include <sys/sockio.h> 129 1.10.2.2 skrll #include <sys/mbuf.h> 130 1.10.2.2 skrll #include <sys/malloc.h> 131 1.10.2.2 skrll #include <sys/kernel.h> 132 1.10.2.2 skrll #include <sys/socket.h> 133 1.10.2.2 skrll #include <sys/device.h> 134 1.10.2.2 skrll #include <sys/queue.h> 135 1.10.2.2 skrll #include <sys/callout.h> 136 1.10.2.2 skrll 137 1.10.2.2 skrll #include <net/if.h> 138 1.10.2.2 skrll #include <net/if_dl.h> 139 1.10.2.2 skrll #include <net/if_types.h> 140 1.10.2.2 skrll 141 1.10.2.2 skrll #ifdef INET 142 1.10.2.2 skrll #include <netinet/in.h> 143 1.10.2.2 skrll #include <netinet/in_systm.h> 144 1.10.2.2 skrll #include <netinet/in_var.h> 145 1.10.2.2 skrll #include <netinet/ip.h> 146 1.10.2.2 skrll #include <netinet/if_ether.h> 147 1.10.2.2 skrll #endif 148 1.10.2.2 skrll 149 1.10.2.2 skrll #include <net/if_media.h> 150 1.10.2.2 skrll 151 1.10.2.2 skrll #if NBPFILTER > 0 152 1.10.2.2 skrll #include <net/bpf.h> 153 1.10.2.2 skrll #endif 154 1.10.2.2 skrll 155 1.10.2.2 skrll #include <dev/mii/mii.h> 156 1.10.2.2 skrll #include <dev/mii/miivar.h> 157 1.10.2.2 skrll #include <dev/mii/brgphyreg.h> 158 1.10.2.2 skrll 159 1.10.2.2 skrll #include <dev/pci/pcireg.h> 160 1.10.2.2 skrll #include <dev/pci/pcivar.h> 161 1.10.2.2 skrll #include <dev/pci/pcidevs.h> 162 1.10.2.2 skrll 163 1.10.2.2 skrll #define SK_VERBOSE 164 1.10.2.2 skrll /* #define SK_USEIOSPACE */ 165 1.10.2.2 skrll 166 1.10.2.2 skrll #include <dev/pci/if_skreg.h> 167 1.10.2.2 skrll #include <dev/pci/if_skvar.h> 168 1.10.2.2 skrll 169 1.10.2.2 skrll int skc_probe(struct device *, struct cfdata *, void *); 170 1.10.2.2 skrll void skc_attach(struct device *, struct device *self, void *aux); 171 1.10.2.2 skrll int sk_probe(struct device *, struct cfdata *, void *); 172 1.10.2.2 skrll void sk_attach(struct device *, struct device *self, void *aux); 173 1.10.2.2 skrll int skcprint(void *, const char *); 174 1.10.2.2 skrll int sk_intr(void *); 175 1.10.2.2 skrll void sk_intr_bcom(struct sk_if_softc *); 176 1.10.2.2 skrll void sk_intr_xmac(struct sk_if_softc *); 177 1.10.2.2 skrll void sk_intr_yukon(struct sk_if_softc *); 178 1.10.2.2 skrll void sk_rxeof(struct sk_if_softc *); 179 1.10.2.2 skrll void sk_txeof(struct sk_if_softc *); 180 1.10.2.2 skrll int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 181 1.10.2.2 skrll void sk_start(struct ifnet *); 182 1.10.2.2 skrll int sk_ioctl(struct ifnet *, u_long, caddr_t); 183 1.10.2.2 skrll int sk_init(struct ifnet *); 184 1.10.2.2 skrll void sk_init_xmac(struct sk_if_softc *); 185 1.10.2.2 skrll void sk_init_yukon(struct sk_if_softc *); 186 1.10.2.2 skrll void sk_stop(struct ifnet *, int); 187 1.10.2.2 skrll void sk_watchdog(struct ifnet *); 188 1.10.2.2 skrll void sk_shutdown(void *); 189 1.10.2.2 skrll int sk_ifmedia_upd(struct ifnet *); 190 1.10.2.2 skrll void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 191 1.10.2.2 skrll void sk_reset(struct sk_softc *); 192 1.10.2.2 skrll int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 193 1.10.2.2 skrll int sk_init_rx_ring(struct sk_if_softc *); 194 1.10.2.2 skrll int sk_init_tx_ring(struct sk_if_softc *); 195 1.10.2.2 skrll u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 196 1.10.2.2 skrll void sk_vpd_read_res(struct sk_softc *, 197 1.10.2.2 skrll struct vpd_res *, int); 198 1.10.2.2 skrll void sk_vpd_read(struct sk_softc *); 199 1.10.2.2 skrll 200 1.10.2.2 skrll int sk_xmac_miibus_readreg(struct device *, int, int); 201 1.10.2.2 skrll void sk_xmac_miibus_writereg(struct device *, int, int, int); 202 1.10.2.2 skrll void sk_xmac_miibus_statchg(struct device *); 203 1.10.2.2 skrll 204 1.10.2.2 skrll int sk_marv_miibus_readreg(struct device *, int, int); 205 1.10.2.2 skrll void sk_marv_miibus_writereg(struct device *, int, int, int); 206 1.10.2.2 skrll void sk_marv_miibus_statchg(struct device *); 207 1.10.2.2 skrll 208 1.10.2.2 skrll u_int32_t sk_xmac_hash(caddr_t); 209 1.10.2.2 skrll u_int32_t sk_yukon_hash(caddr_t); 210 1.10.2.2 skrll void sk_setfilt(struct sk_if_softc *, caddr_t, int); 211 1.10.2.2 skrll void sk_setmulti(struct sk_if_softc *); 212 1.10.2.2 skrll void sk_tick(void *); 213 1.10.2.2 skrll 214 1.10.2.2 skrll /* #define SK_DEBUG 2 */ 215 1.10.2.2 skrll #ifdef SK_DEBUG 216 1.10.2.2 skrll #define DPRINTF(x) if (skdebug) printf x 217 1.10.2.2 skrll #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 218 1.10.2.2 skrll int skdebug = SK_DEBUG; 219 1.10.2.2 skrll 220 1.10.2.2 skrll void sk_dump_txdesc(struct sk_tx_desc *, int); 221 1.10.2.2 skrll void sk_dump_mbuf(struct mbuf *); 222 1.10.2.2 skrll void sk_dump_bytes(const char *, int); 223 1.10.2.2 skrll #else 224 1.10.2.2 skrll #define DPRINTF(x) 225 1.10.2.2 skrll #define DPRINTFN(n,x) 226 1.10.2.2 skrll #endif 227 1.10.2.2 skrll 228 1.10.2.2 skrll #define SK_SETBIT(sc, reg, x) \ 229 1.10.2.2 skrll CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 230 1.10.2.2 skrll 231 1.10.2.2 skrll #define SK_CLRBIT(sc, reg, x) \ 232 1.10.2.2 skrll CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 233 1.10.2.2 skrll 234 1.10.2.2 skrll #define SK_WIN_SETBIT_4(sc, reg, x) \ 235 1.10.2.2 skrll sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 236 1.10.2.2 skrll 237 1.10.2.2 skrll #define SK_WIN_CLRBIT_4(sc, reg, x) \ 238 1.10.2.2 skrll sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 239 1.10.2.2 skrll 240 1.10.2.2 skrll #define SK_WIN_SETBIT_2(sc, reg, x) \ 241 1.10.2.2 skrll sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 242 1.10.2.2 skrll 243 1.10.2.2 skrll #define SK_WIN_CLRBIT_2(sc, reg, x) \ 244 1.10.2.2 skrll sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 245 1.10.2.2 skrll 246 1.10.2.2 skrll /* supported device vendors */ 247 1.10.2.8 skrll static const struct sk_product { 248 1.10.2.2 skrll pci_vendor_id_t sk_vendor; 249 1.10.2.2 skrll pci_product_id_t sk_product; 250 1.10.2.2 skrll } sk_products[] = { 251 1.10.2.2 skrll { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 252 1.10.2.2 skrll { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 253 1.10.2.2 skrll { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 254 1.10.2.2 skrll { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 255 1.10.2.2 skrll { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 256 1.10.2.2 skrll { PCI_VENDOR_GALILEO, PCI_PRODUCT_GALILEO_SKNET, }, 257 1.10.2.7 skrll { PCI_VENDOR_GALILEO, PCI_PRODUCT_GALILEO_BELKIN, }, 258 1.10.2.2 skrll { 0, 0, } 259 1.10.2.2 skrll }; 260 1.10.2.2 skrll 261 1.10.2.10 christos #define SK_LINKSYS_EG1032_SUBID 0x00151737 262 1.10.2.10 christos 263 1.10.2.2 skrll static inline u_int32_t 264 1.10.2.2 skrll sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 265 1.10.2.2 skrll { 266 1.10.2.2 skrll #ifdef SK_USEIOSPACE 267 1.10.2.2 skrll CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 268 1.10.2.2 skrll return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 269 1.10.2.2 skrll #else 270 1.10.2.2 skrll return CSR_READ_4(sc, reg); 271 1.10.2.2 skrll #endif 272 1.10.2.2 skrll } 273 1.10.2.2 skrll 274 1.10.2.2 skrll static inline u_int16_t 275 1.10.2.2 skrll sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 276 1.10.2.2 skrll { 277 1.10.2.2 skrll #ifdef SK_USEIOSPACE 278 1.10.2.2 skrll CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 279 1.10.2.2 skrll return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 280 1.10.2.2 skrll #else 281 1.10.2.2 skrll return CSR_READ_2(sc, reg); 282 1.10.2.2 skrll #endif 283 1.10.2.2 skrll } 284 1.10.2.2 skrll 285 1.10.2.2 skrll static inline u_int8_t 286 1.10.2.2 skrll sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 287 1.10.2.2 skrll { 288 1.10.2.2 skrll #ifdef SK_USEIOSPACE 289 1.10.2.2 skrll CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 290 1.10.2.2 skrll return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 291 1.10.2.2 skrll #else 292 1.10.2.2 skrll return CSR_READ_1(sc, reg); 293 1.10.2.2 skrll #endif 294 1.10.2.2 skrll } 295 1.10.2.2 skrll 296 1.10.2.2 skrll static inline void 297 1.10.2.2 skrll sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 298 1.10.2.2 skrll { 299 1.10.2.2 skrll #ifdef SK_USEIOSPACE 300 1.10.2.2 skrll CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 301 1.10.2.2 skrll CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 302 1.10.2.2 skrll #else 303 1.10.2.2 skrll CSR_WRITE_4(sc, reg, x); 304 1.10.2.2 skrll #endif 305 1.10.2.2 skrll } 306 1.10.2.2 skrll 307 1.10.2.2 skrll static inline void 308 1.10.2.2 skrll sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 309 1.10.2.2 skrll { 310 1.10.2.2 skrll #ifdef SK_USEIOSPACE 311 1.10.2.2 skrll CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 312 1.10.2.2 skrll CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 313 1.10.2.2 skrll #else 314 1.10.2.2 skrll CSR_WRITE_2(sc, reg, x); 315 1.10.2.2 skrll #endif 316 1.10.2.2 skrll } 317 1.10.2.2 skrll 318 1.10.2.2 skrll static inline void 319 1.10.2.2 skrll sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 320 1.10.2.2 skrll { 321 1.10.2.2 skrll #ifdef SK_USEIOSPACE 322 1.10.2.2 skrll CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 323 1.10.2.2 skrll CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 324 1.10.2.2 skrll #else 325 1.10.2.2 skrll CSR_WRITE_1(sc, reg, x); 326 1.10.2.2 skrll #endif 327 1.10.2.2 skrll } 328 1.10.2.2 skrll 329 1.10.2.2 skrll /* 330 1.10.2.2 skrll * The VPD EEPROM contains Vital Product Data, as suggested in 331 1.10.2.2 skrll * the PCI 2.1 specification. The VPD data is separared into areas 332 1.10.2.2 skrll * denoted by resource IDs. The SysKonnect VPD contains an ID string 333 1.10.2.2 skrll * resource (the name of the adapter), a read-only area resource 334 1.10.2.2 skrll * containing various key/data fields and a read/write area which 335 1.10.2.2 skrll * can be used to store asset management information or log messages. 336 1.10.2.2 skrll * We read the ID string and read-only into buffers attached to 337 1.10.2.2 skrll * the controller softc structure for later use. At the moment, 338 1.10.2.2 skrll * we only use the ID string during sk_attach(). 339 1.10.2.2 skrll */ 340 1.10.2.2 skrll u_int8_t 341 1.10.2.2 skrll sk_vpd_readbyte(struct sk_softc *sc, int addr) 342 1.10.2.2 skrll { 343 1.10.2.2 skrll int i; 344 1.10.2.2 skrll 345 1.10.2.2 skrll sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 346 1.10.2.2 skrll for (i = 0; i < SK_TIMEOUT; i++) { 347 1.10.2.2 skrll DELAY(1); 348 1.10.2.2 skrll if (sk_win_read_2(sc, 349 1.10.2.2 skrll SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 350 1.10.2.2 skrll break; 351 1.10.2.2 skrll } 352 1.10.2.2 skrll 353 1.10.2.2 skrll if (i == SK_TIMEOUT) 354 1.10.2.2 skrll return(0); 355 1.10.2.2 skrll 356 1.10.2.2 skrll return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 357 1.10.2.2 skrll } 358 1.10.2.2 skrll 359 1.10.2.2 skrll void 360 1.10.2.2 skrll sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 361 1.10.2.2 skrll { 362 1.10.2.2 skrll int i; 363 1.10.2.2 skrll u_int8_t *ptr; 364 1.10.2.2 skrll 365 1.10.2.2 skrll ptr = (u_int8_t *)res; 366 1.10.2.2 skrll for (i = 0; i < sizeof(struct vpd_res); i++) 367 1.10.2.2 skrll ptr[i] = sk_vpd_readbyte(sc, i + addr); 368 1.10.2.2 skrll } 369 1.10.2.2 skrll 370 1.10.2.2 skrll void 371 1.10.2.2 skrll sk_vpd_read(struct sk_softc *sc) 372 1.10.2.2 skrll { 373 1.10.2.2 skrll int pos = 0, i; 374 1.10.2.2 skrll struct vpd_res res; 375 1.10.2.2 skrll 376 1.10.2.2 skrll if (sc->sk_vpd_prodname != NULL) 377 1.10.2.2 skrll free(sc->sk_vpd_prodname, M_DEVBUF); 378 1.10.2.2 skrll if (sc->sk_vpd_readonly != NULL) 379 1.10.2.2 skrll free(sc->sk_vpd_readonly, M_DEVBUF); 380 1.10.2.2 skrll sc->sk_vpd_prodname = NULL; 381 1.10.2.2 skrll sc->sk_vpd_readonly = NULL; 382 1.10.2.2 skrll 383 1.10.2.2 skrll sk_vpd_read_res(sc, &res, pos); 384 1.10.2.2 skrll 385 1.10.2.2 skrll if (res.vr_id != VPD_RES_ID) { 386 1.10.2.2 skrll printf("%s: bad VPD resource id: expected %x got %x\n", 387 1.10.2.2 skrll sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 388 1.10.2.2 skrll return; 389 1.10.2.2 skrll } 390 1.10.2.2 skrll 391 1.10.2.2 skrll pos += sizeof(res); 392 1.10.2.2 skrll sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 393 1.10.2.2 skrll if (sc->sk_vpd_prodname == NULL) 394 1.10.2.2 skrll panic("sk_vpd_read"); 395 1.10.2.2 skrll for (i = 0; i < res.vr_len; i++) 396 1.10.2.2 skrll sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 397 1.10.2.2 skrll sc->sk_vpd_prodname[i] = '\0'; 398 1.10.2.2 skrll pos += i; 399 1.10.2.2 skrll 400 1.10.2.2 skrll sk_vpd_read_res(sc, &res, pos); 401 1.10.2.2 skrll 402 1.10.2.2 skrll if (res.vr_id != VPD_RES_READ) { 403 1.10.2.2 skrll printf("%s: bad VPD resource id: expected %x got %x\n", 404 1.10.2.2 skrll sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 405 1.10.2.2 skrll return; 406 1.10.2.2 skrll } 407 1.10.2.2 skrll 408 1.10.2.2 skrll pos += sizeof(res); 409 1.10.2.2 skrll sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 410 1.10.2.2 skrll if (sc->sk_vpd_readonly == NULL) 411 1.10.2.2 skrll panic("sk_vpd_read"); 412 1.10.2.5 skrll for (i = 0; i < res.vr_len ; i++) 413 1.10.2.2 skrll sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 414 1.10.2.2 skrll } 415 1.10.2.2 skrll 416 1.10.2.2 skrll int 417 1.10.2.2 skrll sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 418 1.10.2.2 skrll { 419 1.10.2.2 skrll struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 420 1.10.2.2 skrll int i; 421 1.10.2.2 skrll 422 1.10.2.2 skrll DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 423 1.10.2.2 skrll 424 1.10.2.2 skrll if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 425 1.10.2.2 skrll return(0); 426 1.10.2.2 skrll 427 1.10.2.2 skrll SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 428 1.10.2.2 skrll SK_XM_READ_2(sc_if, XM_PHY_DATA); 429 1.10.2.2 skrll if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 430 1.10.2.2 skrll for (i = 0; i < SK_TIMEOUT; i++) { 431 1.10.2.2 skrll DELAY(1); 432 1.10.2.2 skrll if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 433 1.10.2.2 skrll XM_MMUCMD_PHYDATARDY) 434 1.10.2.2 skrll break; 435 1.10.2.2 skrll } 436 1.10.2.2 skrll 437 1.10.2.2 skrll if (i == SK_TIMEOUT) { 438 1.10.2.2 skrll printf("%s: phy failed to come ready\n", 439 1.10.2.2 skrll sc_if->sk_dev.dv_xname); 440 1.10.2.2 skrll return(0); 441 1.10.2.2 skrll } 442 1.10.2.2 skrll } 443 1.10.2.2 skrll DELAY(1); 444 1.10.2.2 skrll return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 445 1.10.2.2 skrll } 446 1.10.2.2 skrll 447 1.10.2.2 skrll void 448 1.10.2.2 skrll sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 449 1.10.2.2 skrll { 450 1.10.2.2 skrll struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 451 1.10.2.2 skrll int i; 452 1.10.2.2 skrll 453 1.10.2.2 skrll DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 454 1.10.2.2 skrll 455 1.10.2.2 skrll SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 456 1.10.2.2 skrll for (i = 0; i < SK_TIMEOUT; i++) { 457 1.10.2.2 skrll if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 458 1.10.2.2 skrll break; 459 1.10.2.2 skrll } 460 1.10.2.2 skrll 461 1.10.2.2 skrll if (i == SK_TIMEOUT) { 462 1.10.2.2 skrll printf("%s: phy failed to come ready\n", 463 1.10.2.2 skrll sc_if->sk_dev.dv_xname); 464 1.10.2.2 skrll return; 465 1.10.2.2 skrll } 466 1.10.2.2 skrll 467 1.10.2.2 skrll SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 468 1.10.2.2 skrll for (i = 0; i < SK_TIMEOUT; i++) { 469 1.10.2.2 skrll DELAY(1); 470 1.10.2.2 skrll if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 471 1.10.2.2 skrll break; 472 1.10.2.2 skrll } 473 1.10.2.2 skrll 474 1.10.2.2 skrll if (i == SK_TIMEOUT) 475 1.10.2.2 skrll printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 476 1.10.2.2 skrll } 477 1.10.2.2 skrll 478 1.10.2.2 skrll void 479 1.10.2.2 skrll sk_xmac_miibus_statchg(struct device *dev) 480 1.10.2.2 skrll { 481 1.10.2.2 skrll struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 482 1.10.2.2 skrll struct mii_data *mii = &sc_if->sk_mii; 483 1.10.2.2 skrll 484 1.10.2.2 skrll DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 485 1.10.2.2 skrll 486 1.10.2.2 skrll /* 487 1.10.2.2 skrll * If this is a GMII PHY, manually set the XMAC's 488 1.10.2.2 skrll * duplex mode accordingly. 489 1.10.2.2 skrll */ 490 1.10.2.2 skrll if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 491 1.10.2.2 skrll if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 492 1.10.2.2 skrll SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 493 1.10.2.2 skrll } else { 494 1.10.2.2 skrll SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 495 1.10.2.2 skrll } 496 1.10.2.2 skrll } 497 1.10.2.2 skrll } 498 1.10.2.2 skrll 499 1.10.2.2 skrll int 500 1.10.2.2 skrll sk_marv_miibus_readreg(dev, phy, reg) 501 1.10.2.2 skrll struct device *dev; 502 1.10.2.2 skrll int phy, reg; 503 1.10.2.2 skrll { 504 1.10.2.2 skrll struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 505 1.10.2.2 skrll u_int16_t val; 506 1.10.2.2 skrll int i; 507 1.10.2.2 skrll 508 1.10.2.2 skrll if (phy != 0 || 509 1.10.2.2 skrll (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 510 1.10.2.2 skrll sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 511 1.10.2.2 skrll DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 512 1.10.2.2 skrll phy, reg)); 513 1.10.2.2 skrll return(0); 514 1.10.2.2 skrll } 515 1.10.2.2 skrll 516 1.10.2.2 skrll SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 517 1.10.2.2 skrll YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 518 1.10.2.8 skrll 519 1.10.2.2 skrll for (i = 0; i < SK_TIMEOUT; i++) { 520 1.10.2.2 skrll DELAY(1); 521 1.10.2.2 skrll val = SK_YU_READ_2(sc_if, YUKON_SMICR); 522 1.10.2.2 skrll if (val & YU_SMICR_READ_VALID) 523 1.10.2.2 skrll break; 524 1.10.2.2 skrll } 525 1.10.2.2 skrll 526 1.10.2.2 skrll if (i == SK_TIMEOUT) { 527 1.10.2.2 skrll printf("%s: phy failed to come ready\n", 528 1.10.2.2 skrll sc_if->sk_dev.dv_xname); 529 1.10.2.2 skrll return 0; 530 1.10.2.2 skrll } 531 1.10.2.8 skrll 532 1.10.2.2 skrll DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 533 1.10.2.2 skrll SK_TIMEOUT)); 534 1.10.2.2 skrll 535 1.10.2.2 skrll val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 536 1.10.2.2 skrll 537 1.10.2.2 skrll DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 538 1.10.2.2 skrll phy, reg, val)); 539 1.10.2.2 skrll 540 1.10.2.2 skrll return val; 541 1.10.2.2 skrll } 542 1.10.2.2 skrll 543 1.10.2.2 skrll void 544 1.10.2.2 skrll sk_marv_miibus_writereg(dev, phy, reg, val) 545 1.10.2.2 skrll struct device *dev; 546 1.10.2.2 skrll int phy, reg, val; 547 1.10.2.2 skrll { 548 1.10.2.2 skrll struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 549 1.10.2.2 skrll int i; 550 1.10.2.2 skrll 551 1.10.2.2 skrll DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 552 1.10.2.2 skrll phy, reg, val)); 553 1.10.2.2 skrll 554 1.10.2.2 skrll SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 555 1.10.2.2 skrll SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 556 1.10.2.2 skrll YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 557 1.10.2.2 skrll 558 1.10.2.2 skrll for (i = 0; i < SK_TIMEOUT; i++) { 559 1.10.2.2 skrll DELAY(1); 560 1.10.2.2 skrll if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 561 1.10.2.2 skrll break; 562 1.10.2.2 skrll } 563 1.10.2.2 skrll } 564 1.10.2.2 skrll 565 1.10.2.2 skrll void 566 1.10.2.2 skrll sk_marv_miibus_statchg(dev) 567 1.10.2.2 skrll struct device *dev; 568 1.10.2.2 skrll { 569 1.10.2.2 skrll DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 570 1.10.2.2 skrll SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 571 1.10.2.2 skrll } 572 1.10.2.2 skrll 573 1.10.2.2 skrll #define SK_HASH_BITS 6 574 1.10.2.2 skrll 575 1.10.2.2 skrll u_int32_t 576 1.10.2.2 skrll sk_xmac_hash(caddr_t addr) 577 1.10.2.2 skrll { 578 1.10.2.2 skrll u_int32_t crc; 579 1.10.2.2 skrll 580 1.10.2.2 skrll crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 581 1.10.2.8 skrll crc = ~crc & ((1<< SK_HASH_BITS) - 1); 582 1.10.2.2 skrll DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 583 1.10.2.2 skrll return (crc); 584 1.10.2.2 skrll } 585 1.10.2.2 skrll 586 1.10.2.2 skrll u_int32_t 587 1.10.2.2 skrll sk_yukon_hash(caddr_t addr) 588 1.10.2.2 skrll { 589 1.10.2.2 skrll u_int32_t crc; 590 1.10.2.2 skrll 591 1.10.2.2 skrll crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 592 1.10.2.2 skrll crc &= ((1 << SK_HASH_BITS) - 1); 593 1.10.2.2 skrll DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 594 1.10.2.2 skrll return (crc); 595 1.10.2.2 skrll } 596 1.10.2.2 skrll 597 1.10.2.2 skrll void 598 1.10.2.2 skrll sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 599 1.10.2.2 skrll { 600 1.10.2.2 skrll int base = XM_RXFILT_ENTRY(slot); 601 1.10.2.2 skrll 602 1.10.2.2 skrll SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 603 1.10.2.2 skrll SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 604 1.10.2.2 skrll SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 605 1.10.2.2 skrll } 606 1.10.2.2 skrll 607 1.10.2.2 skrll void 608 1.10.2.2 skrll sk_setmulti(struct sk_if_softc *sc_if) 609 1.10.2.2 skrll { 610 1.10.2.2 skrll struct sk_softc *sc = sc_if->sk_softc; 611 1.10.2.2 skrll struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 612 1.10.2.2 skrll u_int32_t hashes[2] = { 0, 0 }; 613 1.10.2.2 skrll int h = 0, i; 614 1.10.2.2 skrll struct ethercom *ec = &sc_if->sk_ethercom; 615 1.10.2.2 skrll struct ether_multi *enm; 616 1.10.2.2 skrll struct ether_multistep step; 617 1.10.2.2 skrll u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 618 1.10.2.2 skrll 619 1.10.2.2 skrll /* First, zot all the existing filters. */ 620 1.10.2.2 skrll switch(sc->sk_type) { 621 1.10.2.2 skrll case SK_GENESIS: 622 1.10.2.2 skrll for (i = 1; i < XM_RXFILT_MAX; i++) 623 1.10.2.2 skrll sk_setfilt(sc_if, (caddr_t)&dummy, i); 624 1.10.2.2 skrll 625 1.10.2.2 skrll SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 626 1.10.2.2 skrll SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 627 1.10.2.2 skrll break; 628 1.10.2.2 skrll case SK_YUKON: 629 1.10.2.5 skrll case SK_YUKON_LITE: 630 1.10.2.5 skrll case SK_YUKON_LP: 631 1.10.2.2 skrll SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 632 1.10.2.2 skrll SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 633 1.10.2.2 skrll SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 634 1.10.2.2 skrll SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 635 1.10.2.2 skrll break; 636 1.10.2.2 skrll } 637 1.10.2.2 skrll 638 1.10.2.2 skrll /* Now program new ones. */ 639 1.10.2.2 skrll allmulti: 640 1.10.2.2 skrll if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 641 1.10.2.2 skrll hashes[0] = 0xFFFFFFFF; 642 1.10.2.2 skrll hashes[1] = 0xFFFFFFFF; 643 1.10.2.2 skrll } else { 644 1.10.2.2 skrll i = 1; 645 1.10.2.2 skrll /* First find the tail of the list. */ 646 1.10.2.2 skrll ETHER_FIRST_MULTI(step, ec, enm); 647 1.10.2.2 skrll while (enm != NULL) { 648 1.10.2.2 skrll if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 649 1.10.2.2 skrll ETHER_ADDR_LEN)) { 650 1.10.2.2 skrll ifp->if_flags |= IFF_ALLMULTI; 651 1.10.2.2 skrll goto allmulti; 652 1.10.2.2 skrll } 653 1.10.2.2 skrll DPRINTFN(2,("multicast address %s\n", 654 1.10.2.2 skrll ether_sprintf(enm->enm_addrlo))); 655 1.10.2.2 skrll /* 656 1.10.2.2 skrll * Program the first XM_RXFILT_MAX multicast groups 657 1.10.2.2 skrll * into the perfect filter. For all others, 658 1.10.2.2 skrll * use the hash table. 659 1.10.2.2 skrll */ 660 1.10.2.2 skrll if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 661 1.10.2.2 skrll sk_setfilt(sc_if, enm->enm_addrlo, i); 662 1.10.2.2 skrll i++; 663 1.10.2.2 skrll } 664 1.10.2.2 skrll else { 665 1.10.2.2 skrll switch (sc->sk_type) { 666 1.10.2.2 skrll case SK_GENESIS: 667 1.10.2.2 skrll h = sk_xmac_hash(enm->enm_addrlo); 668 1.10.2.2 skrll break; 669 1.10.2.2 skrll case SK_YUKON: 670 1.10.2.5 skrll case SK_YUKON_LITE: 671 1.10.2.5 skrll case SK_YUKON_LP: 672 1.10.2.2 skrll h = sk_yukon_hash(enm->enm_addrlo); 673 1.10.2.2 skrll break; 674 1.10.2.2 skrll } 675 1.10.2.2 skrll if (h < 32) 676 1.10.2.2 skrll hashes[0] |= (1 << h); 677 1.10.2.2 skrll else 678 1.10.2.2 skrll hashes[1] |= (1 << (h - 32)); 679 1.10.2.2 skrll } 680 1.10.2.2 skrll 681 1.10.2.2 skrll ETHER_NEXT_MULTI(step, enm); 682 1.10.2.2 skrll } 683 1.10.2.2 skrll } 684 1.10.2.2 skrll 685 1.10.2.2 skrll switch(sc->sk_type) { 686 1.10.2.2 skrll case SK_GENESIS: 687 1.10.2.2 skrll SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 688 1.10.2.2 skrll XM_MODE_RX_USE_PERFECT); 689 1.10.2.2 skrll SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 690 1.10.2.2 skrll SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 691 1.10.2.2 skrll break; 692 1.10.2.2 skrll case SK_YUKON: 693 1.10.2.5 skrll case SK_YUKON_LITE: 694 1.10.2.5 skrll case SK_YUKON_LP: 695 1.10.2.2 skrll SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 696 1.10.2.2 skrll SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 697 1.10.2.2 skrll SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 698 1.10.2.2 skrll SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 699 1.10.2.2 skrll break; 700 1.10.2.2 skrll } 701 1.10.2.2 skrll } 702 1.10.2.2 skrll 703 1.10.2.2 skrll int 704 1.10.2.2 skrll sk_init_rx_ring(struct sk_if_softc *sc_if) 705 1.10.2.2 skrll { 706 1.10.2.2 skrll struct sk_chain_data *cd = &sc_if->sk_cdata; 707 1.10.2.2 skrll struct sk_ring_data *rd = sc_if->sk_rdata; 708 1.10.2.2 skrll int i; 709 1.10.2.2 skrll 710 1.10.2.2 skrll bzero((char *)rd->sk_rx_ring, 711 1.10.2.2 skrll sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 712 1.10.2.2 skrll 713 1.10.2.2 skrll for (i = 0; i < SK_RX_RING_CNT; i++) { 714 1.10.2.2 skrll cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 715 1.10.2.2 skrll if (i == (SK_RX_RING_CNT - 1)) { 716 1.10.2.2 skrll cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 717 1.10.2.2 skrll rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if, 0); 718 1.10.2.2 skrll } else { 719 1.10.2.2 skrll cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 720 1.10.2.2 skrll rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if,i+1); 721 1.10.2.2 skrll } 722 1.10.2.2 skrll } 723 1.10.2.2 skrll 724 1.10.2.2 skrll for (i = 0; i < SK_RX_RING_CNT; i++) { 725 1.10.2.2 skrll if (sk_newbuf(sc_if, i, NULL, NULL) == ENOBUFS) { 726 1.10.2.2 skrll printf("%s: failed alloc of %dth mbuf\n", 727 1.10.2.2 skrll sc_if->sk_dev.dv_xname, i); 728 1.10.2.2 skrll return(ENOBUFS); 729 1.10.2.2 skrll } 730 1.10.2.2 skrll } 731 1.10.2.2 skrll sc_if->sk_cdata.sk_rx_prod = 0; 732 1.10.2.2 skrll sc_if->sk_cdata.sk_rx_cons = 0; 733 1.10.2.2 skrll 734 1.10.2.2 skrll return(0); 735 1.10.2.2 skrll } 736 1.10.2.2 skrll 737 1.10.2.2 skrll int 738 1.10.2.2 skrll sk_init_tx_ring(struct sk_if_softc *sc_if) 739 1.10.2.2 skrll { 740 1.10.2.2 skrll struct sk_chain_data *cd = &sc_if->sk_cdata; 741 1.10.2.2 skrll struct sk_ring_data *rd = sc_if->sk_rdata; 742 1.10.2.2 skrll int i; 743 1.10.2.2 skrll 744 1.10.2.2 skrll bzero((char *)sc_if->sk_rdata->sk_tx_ring, 745 1.10.2.2 skrll sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 746 1.10.2.2 skrll 747 1.10.2.2 skrll for (i = 0; i < SK_TX_RING_CNT; i++) { 748 1.10.2.2 skrll cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 749 1.10.2.2 skrll if (i == (SK_TX_RING_CNT - 1)) { 750 1.10.2.2 skrll cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 751 1.10.2.2 skrll rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if, 0); 752 1.10.2.2 skrll } else { 753 1.10.2.2 skrll cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 754 1.10.2.2 skrll rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if,i+1); 755 1.10.2.2 skrll } 756 1.10.2.2 skrll } 757 1.10.2.2 skrll 758 1.10.2.2 skrll sc_if->sk_cdata.sk_tx_prod = 0; 759 1.10.2.2 skrll sc_if->sk_cdata.sk_tx_cons = 0; 760 1.10.2.2 skrll sc_if->sk_cdata.sk_tx_cnt = 0; 761 1.10.2.2 skrll 762 1.10.2.2 skrll SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 763 1.10.2.2 skrll BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 764 1.10.2.2 skrll 765 1.10.2.2 skrll return (0); 766 1.10.2.2 skrll } 767 1.10.2.2 skrll 768 1.10.2.2 skrll int 769 1.10.2.2 skrll sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 770 1.10.2.2 skrll bus_dmamap_t dmamap) 771 1.10.2.2 skrll { 772 1.10.2.2 skrll struct sk_softc *sc = sc_if->sk_softc; 773 1.10.2.2 skrll struct mbuf *m_new = NULL; 774 1.10.2.2 skrll struct sk_chain *c; 775 1.10.2.2 skrll struct sk_rx_desc *r; 776 1.10.2.2 skrll 777 1.10.2.2 skrll if (dmamap == NULL) { 778 1.10.2.2 skrll /* if (m) panic() */ 779 1.10.2.2 skrll 780 1.10.2.2 skrll if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, MCLBYTES, 781 1.10.2.2 skrll 0, BUS_DMA_NOWAIT, &dmamap)) { 782 1.10.2.2 skrll printf("%s: can't create recv map\n", 783 1.10.2.2 skrll sc_if->sk_dev.dv_xname); 784 1.10.2.2 skrll return(ENOMEM); 785 1.10.2.2 skrll } 786 1.10.2.2 skrll } else if (m == NULL) 787 1.10.2.2 skrll bus_dmamap_unload(sc->sc_dmatag, dmamap); 788 1.10.2.2 skrll 789 1.10.2.2 skrll sc_if->sk_cdata.sk_rx_map[i] = dmamap; 790 1.10.2.2 skrll 791 1.10.2.2 skrll if (m == NULL) { 792 1.10.2.2 skrll MGETHDR(m_new, M_DONTWAIT, MT_DATA); 793 1.10.2.2 skrll if (m_new == NULL) { 794 1.10.2.2 skrll printf("%s: no memory for rx list -- " 795 1.10.2.2 skrll "packet dropped!\n", sc_if->sk_dev.dv_xname); 796 1.10.2.2 skrll return(ENOBUFS); 797 1.10.2.2 skrll } 798 1.10.2.2 skrll 799 1.10.2.2 skrll /* Allocate the jumbo buffer */ 800 1.10.2.2 skrll MCLGET(m_new, M_DONTWAIT); 801 1.10.2.2 skrll if (!(m_new->m_flags & M_EXT)) { 802 1.10.2.2 skrll m_freem(m_new); 803 1.10.2.2 skrll return (ENOBUFS); 804 1.10.2.2 skrll } 805 1.10.2.2 skrll 806 1.10.2.2 skrll m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 807 1.10.2.2 skrll 808 1.10.2.2 skrll m_adj(m_new, ETHER_ALIGN); 809 1.10.2.2 skrll 810 1.10.2.2 skrll if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m_new, 811 1.10.2.2 skrll BUS_DMA_NOWAIT)) 812 1.10.2.2 skrll return(ENOBUFS); 813 1.10.2.2 skrll } else { 814 1.10.2.2 skrll /* 815 1.10.2.2 skrll * We're re-using a previously allocated mbuf; 816 1.10.2.2 skrll * be sure to re-init pointers and lengths to 817 1.10.2.2 skrll * default values. 818 1.10.2.2 skrll */ 819 1.10.2.2 skrll m_new = m; 820 1.10.2.2 skrll m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 821 1.10.2.2 skrll m_adj(m_new, ETHER_ALIGN); 822 1.10.2.2 skrll m_new->m_data = m_new->m_ext.ext_buf; 823 1.10.2.2 skrll } 824 1.10.2.2 skrll 825 1.10.2.2 skrll c = &sc_if->sk_cdata.sk_rx_chain[i]; 826 1.10.2.2 skrll r = c->sk_desc; 827 1.10.2.2 skrll c->sk_mbuf = m_new; 828 1.10.2.2 skrll r->sk_data_lo = dmamap->dm_segs[0].ds_addr; 829 1.10.2.2 skrll r->sk_ctl = dmamap->dm_segs[0].ds_len | SK_RXSTAT; 830 1.10.2.2 skrll 831 1.10.2.2 skrll SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 832 1.10.2.2 skrll 833 1.10.2.2 skrll return(0); 834 1.10.2.2 skrll } 835 1.10.2.2 skrll 836 1.10.2.2 skrll /* 837 1.10.2.2 skrll * Set media options. 838 1.10.2.2 skrll */ 839 1.10.2.2 skrll int 840 1.10.2.2 skrll sk_ifmedia_upd(struct ifnet *ifp) 841 1.10.2.2 skrll { 842 1.10.2.2 skrll struct sk_if_softc *sc_if = ifp->if_softc; 843 1.10.2.2 skrll 844 1.10.2.2 skrll (void) sk_init(ifp); 845 1.10.2.2 skrll mii_mediachg(&sc_if->sk_mii); 846 1.10.2.2 skrll return(0); 847 1.10.2.2 skrll } 848 1.10.2.2 skrll 849 1.10.2.2 skrll /* 850 1.10.2.2 skrll * Report current media status. 851 1.10.2.2 skrll */ 852 1.10.2.2 skrll void 853 1.10.2.2 skrll sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 854 1.10.2.2 skrll { 855 1.10.2.2 skrll struct sk_if_softc *sc_if = ifp->if_softc; 856 1.10.2.2 skrll 857 1.10.2.2 skrll mii_pollstat(&sc_if->sk_mii); 858 1.10.2.2 skrll ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 859 1.10.2.2 skrll ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 860 1.10.2.2 skrll } 861 1.10.2.2 skrll 862 1.10.2.2 skrll int 863 1.10.2.2 skrll sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 864 1.10.2.2 skrll { 865 1.10.2.2 skrll struct sk_if_softc *sc_if = ifp->if_softc; 866 1.10.2.2 skrll struct sk_softc *sc = sc_if->sk_softc; 867 1.10.2.2 skrll struct ifreq *ifr = (struct ifreq *) data; 868 1.10.2.2 skrll /* struct ifaddr *ifa = (struct ifaddr *) data; */ 869 1.10.2.2 skrll struct mii_data *mii; 870 1.10.2.2 skrll int s, error = 0; 871 1.10.2.2 skrll 872 1.10.2.2 skrll /* DPRINTFN(2, ("sk_ioctl\n")); */ 873 1.10.2.2 skrll 874 1.10.2.2 skrll s = splnet(); 875 1.10.2.2 skrll 876 1.10.2.2 skrll switch(command) { 877 1.10.2.2 skrll 878 1.10.2.2 skrll case SIOCSIFFLAGS: 879 1.10.2.2 skrll DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 880 1.10.2.2 skrll if (ifp->if_flags & IFF_UP) { 881 1.10.2.2 skrll if (ifp->if_flags & IFF_RUNNING && 882 1.10.2.2 skrll ifp->if_flags & IFF_PROMISC && 883 1.10.2.2 skrll !(sc_if->sk_if_flags & IFF_PROMISC)) { 884 1.10.2.2 skrll switch(sc->sk_type) { 885 1.10.2.2 skrll case SK_GENESIS: 886 1.10.2.2 skrll SK_XM_SETBIT_4(sc_if, XM_MODE, 887 1.10.2.2 skrll XM_MODE_RX_PROMISC); 888 1.10.2.2 skrll break; 889 1.10.2.2 skrll case SK_YUKON: 890 1.10.2.5 skrll case SK_YUKON_LITE: 891 1.10.2.5 skrll case SK_YUKON_LP: 892 1.10.2.2 skrll SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 893 1.10.2.2 skrll YU_RCR_UFLEN | YU_RCR_MUFLEN); 894 1.10.2.2 skrll break; 895 1.10.2.2 skrll } 896 1.10.2.2 skrll sk_setmulti(sc_if); 897 1.10.2.2 skrll } else if (ifp->if_flags & IFF_RUNNING && 898 1.10.2.2 skrll !(ifp->if_flags & IFF_PROMISC) && 899 1.10.2.2 skrll sc_if->sk_if_flags & IFF_PROMISC) { 900 1.10.2.2 skrll switch(sc->sk_type) { 901 1.10.2.2 skrll case SK_GENESIS: 902 1.10.2.2 skrll SK_XM_CLRBIT_4(sc_if, XM_MODE, 903 1.10.2.2 skrll XM_MODE_RX_PROMISC); 904 1.10.2.2 skrll break; 905 1.10.2.2 skrll case SK_YUKON: 906 1.10.2.5 skrll case SK_YUKON_LITE: 907 1.10.2.5 skrll case SK_YUKON_LP: 908 1.10.2.2 skrll SK_YU_SETBIT_2(sc_if, YUKON_RCR, 909 1.10.2.2 skrll YU_RCR_UFLEN | YU_RCR_MUFLEN); 910 1.10.2.2 skrll break; 911 1.10.2.2 skrll } 912 1.10.2.2 skrll 913 1.10.2.2 skrll sk_setmulti(sc_if); 914 1.10.2.2 skrll } else 915 1.10.2.2 skrll (void) sk_init(ifp); 916 1.10.2.2 skrll } else { 917 1.10.2.2 skrll if (ifp->if_flags & IFF_RUNNING) 918 1.10.2.2 skrll sk_stop(ifp,0); 919 1.10.2.2 skrll } 920 1.10.2.2 skrll sc_if->sk_if_flags = ifp->if_flags; 921 1.10.2.2 skrll error = 0; 922 1.10.2.2 skrll break; 923 1.10.2.2 skrll 924 1.10.2.2 skrll case SIOCGIFMEDIA: 925 1.10.2.2 skrll case SIOCSIFMEDIA: 926 1.10.2.2 skrll DPRINTFN(2, ("sk_ioctl MEDIA\n")); 927 1.10.2.2 skrll mii = &sc_if->sk_mii; 928 1.10.2.2 skrll error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 929 1.10.2.2 skrll break; 930 1.10.2.2 skrll default: 931 1.10.2.2 skrll DPRINTFN(2, ("sk_ioctl ETHER\n")); 932 1.10.2.2 skrll error = ether_ioctl(ifp, command, data); 933 1.10.2.2 skrll 934 1.10.2.2 skrll if ( error == ENETRESET) { 935 1.10.2.6 skrll if (ifp->if_flags & IFF_RUNNING) { 936 1.10.2.6 skrll sk_setmulti(sc_if); 937 1.10.2.6 skrll DPRINTFN(2, ("sk_ioctl setmulti called\n")); 938 1.10.2.6 skrll } 939 1.10.2.2 skrll error = 0; 940 1.10.2.2 skrll } else if ( error ) { 941 1.10.2.2 skrll splx(s); 942 1.10.2.2 skrll return error; 943 1.10.2.2 skrll } 944 1.10.2.2 skrll break; 945 1.10.2.2 skrll } 946 1.10.2.2 skrll 947 1.10.2.2 skrll splx(s); 948 1.10.2.2 skrll return(error); 949 1.10.2.2 skrll } 950 1.10.2.2 skrll 951 1.10.2.2 skrll /* 952 1.10.2.2 skrll * Lookup: Check the PCI vendor and device, and return a pointer to 953 1.10.2.2 skrll * The structure if the IDs match against our list. 954 1.10.2.2 skrll */ 955 1.10.2.2 skrll 956 1.10.2.2 skrll static const struct sk_product * 957 1.10.2.2 skrll sk_lookup(const struct pci_attach_args *pa) 958 1.10.2.2 skrll { 959 1.10.2.2 skrll const struct sk_product *psk; 960 1.10.2.8 skrll 961 1.10.2.2 skrll for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 962 1.10.2.2 skrll if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 963 1.10.2.2 skrll PCI_PRODUCT(pa->pa_id) == psk->sk_product) 964 1.10.2.2 skrll return (psk); 965 1.10.2.2 skrll } 966 1.10.2.2 skrll return (NULL); 967 1.10.2.2 skrll } 968 1.10.2.2 skrll 969 1.10.2.2 skrll /* 970 1.10.2.2 skrll * Probe for a SysKonnect GEnesis chip. 971 1.10.2.2 skrll */ 972 1.10.2.2 skrll 973 1.10.2.2 skrll int 974 1.10.2.2 skrll skc_probe(struct device *parent, struct cfdata *match, void *aux) 975 1.10.2.2 skrll { 976 1.10.2.2 skrll struct pci_attach_args *pa = (struct pci_attach_args *)aux; 977 1.10.2.2 skrll const struct sk_product *psk; 978 1.10.2.10 christos pcireg_t subid; 979 1.10.2.10 christos 980 1.10.2.10 christos subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 981 1.10.2.10 christos 982 1.10.2.10 christos /* special-case Linksys EG1032, since rev 3 uses re(4) */ 983 1.10.2.10 christos if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 984 1.10.2.10 christos PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 985 1.10.2.10 christos subid == SK_LINKSYS_EG1032_SUBID) 986 1.10.2.10 christos return(1); 987 1.10.2.8 skrll 988 1.10.2.2 skrll if ((psk = sk_lookup(pa))) { 989 1.10.2.2 skrll return(1); 990 1.10.2.2 skrll } 991 1.10.2.2 skrll return(0); 992 1.10.2.2 skrll } 993 1.10.2.2 skrll 994 1.10.2.2 skrll /* 995 1.10.2.2 skrll * Force the GEnesis into reset, then bring it out of reset. 996 1.10.2.2 skrll */ 997 1.10.2.2 skrll void sk_reset(struct sk_softc *sc) 998 1.10.2.2 skrll { 999 1.10.2.2 skrll DPRINTFN(2, ("sk_reset\n")); 1000 1.10.2.2 skrll 1001 1.10.2.2 skrll CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1002 1.10.2.2 skrll CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1003 1.10.2.5 skrll if (SK_YUKON_FAMILY(sc->sk_type)) 1004 1.10.2.2 skrll CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1005 1.10.2.2 skrll 1006 1.10.2.2 skrll DELAY(1000); 1007 1.10.2.2 skrll CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1008 1.10.2.2 skrll DELAY(2); 1009 1.10.2.2 skrll CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1010 1.10.2.5 skrll if (SK_YUKON_FAMILY(sc->sk_type)) 1011 1.10.2.2 skrll CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1012 1.10.2.2 skrll 1013 1.10.2.2 skrll DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1014 1.10.2.2 skrll DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1015 1.10.2.2 skrll CSR_READ_2(sc, SK_LINK_CTRL))); 1016 1.10.2.2 skrll 1017 1.10.2.2 skrll if (sc->sk_type == SK_GENESIS) { 1018 1.10.2.2 skrll /* Configure packet arbiter */ 1019 1.10.2.2 skrll sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1020 1.10.2.2 skrll sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1021 1.10.2.2 skrll sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1022 1.10.2.2 skrll sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1023 1.10.2.2 skrll sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1024 1.10.2.2 skrll } 1025 1.10.2.2 skrll 1026 1.10.2.2 skrll /* Enable RAM interface */ 1027 1.10.2.2 skrll sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1028 1.10.2.2 skrll 1029 1.10.2.2 skrll /* 1030 1.10.2.2 skrll * Configure interrupt moderation. The moderation timer 1031 1.10.2.2 skrll * defers interrupts specified in the interrupt moderation 1032 1.10.2.2 skrll * timer mask based on the timeout specified in the interrupt 1033 1.10.2.2 skrll * moderation timer init register. Each bit in the timer 1034 1.10.2.2 skrll * register represents 18.825ns, so to specify a timeout in 1035 1.10.2.2 skrll * microseconds, we have to multiply by 54. 1036 1.10.2.2 skrll */ 1037 1.10.2.5 skrll sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(100)); 1038 1.10.2.2 skrll sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1039 1.10.2.2 skrll SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1040 1.10.2.2 skrll sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1041 1.10.2.2 skrll } 1042 1.10.2.2 skrll 1043 1.10.2.2 skrll int 1044 1.10.2.2 skrll sk_probe(struct device *parent, struct cfdata *match, void *aux) 1045 1.10.2.2 skrll { 1046 1.10.2.2 skrll struct skc_attach_args *sa = aux; 1047 1.10.2.2 skrll 1048 1.10.2.2 skrll if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1049 1.10.2.2 skrll return(0); 1050 1.10.2.2 skrll 1051 1.10.2.2 skrll return (1); 1052 1.10.2.2 skrll } 1053 1.10.2.2 skrll 1054 1.10.2.2 skrll /* 1055 1.10.2.2 skrll * Each XMAC chip is attached as a separate logical IP interface. 1056 1.10.2.2 skrll * Single port cards will have only one logical interface of course. 1057 1.10.2.2 skrll */ 1058 1.10.2.2 skrll void 1059 1.10.2.2 skrll sk_attach(struct device *parent, struct device *self, void *aux) 1060 1.10.2.2 skrll { 1061 1.10.2.2 skrll struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1062 1.10.2.2 skrll struct sk_softc *sc = (struct sk_softc *)parent; 1063 1.10.2.2 skrll struct skc_attach_args *sa = aux; 1064 1.10.2.2 skrll struct sk_txmap_entry *entry; 1065 1.10.2.2 skrll struct ifnet *ifp; 1066 1.10.2.2 skrll bus_dma_segment_t seg; 1067 1.10.2.2 skrll bus_dmamap_t dmamap; 1068 1.10.2.2 skrll caddr_t kva; 1069 1.10.2.2 skrll int i, rseg; 1070 1.10.2.2 skrll 1071 1.10.2.2 skrll sc_if->sk_port = sa->skc_port; 1072 1.10.2.2 skrll sc_if->sk_softc = sc; 1073 1.10.2.2 skrll sc->sk_if[sa->skc_port] = sc_if; 1074 1.10.2.2 skrll 1075 1.10.2.2 skrll if (sa->skc_port == SK_PORT_A) 1076 1.10.2.2 skrll sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1077 1.10.2.2 skrll if (sa->skc_port == SK_PORT_B) 1078 1.10.2.2 skrll sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1079 1.10.2.2 skrll 1080 1.10.2.2 skrll DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1081 1.10.2.2 skrll 1082 1.10.2.2 skrll /* 1083 1.10.2.2 skrll * Get station address for this interface. Note that 1084 1.10.2.2 skrll * dual port cards actually come with three station 1085 1.10.2.2 skrll * addresses: one for each port, plus an extra. The 1086 1.10.2.2 skrll * extra one is used by the SysKonnect driver software 1087 1.10.2.2 skrll * as a 'virtual' station address for when both ports 1088 1.10.2.2 skrll * are operating in failover mode. Currently we don't 1089 1.10.2.2 skrll * use this extra address. 1090 1.10.2.2 skrll */ 1091 1.10.2.2 skrll for (i = 0; i < ETHER_ADDR_LEN; i++) 1092 1.10.2.2 skrll sc_if->sk_enaddr[i] = 1093 1.10.2.2 skrll sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1094 1.10.2.2 skrll 1095 1.10.2.2 skrll 1096 1.10.2.2 skrll aprint_normal(": Ethernet address %s\n", 1097 1.10.2.2 skrll ether_sprintf(sc_if->sk_enaddr)); 1098 1.10.2.2 skrll 1099 1.10.2.2 skrll /* 1100 1.10.2.2 skrll * Set up RAM buffer addresses. The NIC will have a certain 1101 1.10.2.2 skrll * amount of SRAM on it, somewhere between 512K and 2MB. We 1102 1.10.2.2 skrll * need to divide this up a) between the transmitter and 1103 1.10.2.2 skrll * receiver and b) between the two XMACs, if this is a 1104 1.10.2.2 skrll * dual port NIC. Our algotithm is to divide up the memory 1105 1.10.2.2 skrll * evenly so that everyone gets a fair share. 1106 1.10.2.2 skrll */ 1107 1.10.2.2 skrll if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1108 1.10.2.2 skrll u_int32_t chunk, val; 1109 1.10.2.2 skrll 1110 1.10.2.2 skrll chunk = sc->sk_ramsize / 2; 1111 1.10.2.2 skrll val = sc->sk_rboff / sizeof(u_int64_t); 1112 1.10.2.2 skrll sc_if->sk_rx_ramstart = val; 1113 1.10.2.2 skrll val += (chunk / sizeof(u_int64_t)); 1114 1.10.2.2 skrll sc_if->sk_rx_ramend = val - 1; 1115 1.10.2.2 skrll sc_if->sk_tx_ramstart = val; 1116 1.10.2.2 skrll val += (chunk / sizeof(u_int64_t)); 1117 1.10.2.2 skrll sc_if->sk_tx_ramend = val - 1; 1118 1.10.2.2 skrll } else { 1119 1.10.2.2 skrll u_int32_t chunk, val; 1120 1.10.2.2 skrll 1121 1.10.2.2 skrll chunk = sc->sk_ramsize / 4; 1122 1.10.2.2 skrll val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1123 1.10.2.2 skrll sizeof(u_int64_t); 1124 1.10.2.2 skrll sc_if->sk_rx_ramstart = val; 1125 1.10.2.2 skrll val += (chunk / sizeof(u_int64_t)); 1126 1.10.2.2 skrll sc_if->sk_rx_ramend = val - 1; 1127 1.10.2.2 skrll sc_if->sk_tx_ramstart = val; 1128 1.10.2.2 skrll val += (chunk / sizeof(u_int64_t)); 1129 1.10.2.2 skrll sc_if->sk_tx_ramend = val - 1; 1130 1.10.2.2 skrll } 1131 1.10.2.2 skrll 1132 1.10.2.2 skrll DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1133 1.10.2.2 skrll " tx_ramstart=%#x tx_ramend=%#x\n", 1134 1.10.2.2 skrll sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1135 1.10.2.2 skrll sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1136 1.10.2.2 skrll 1137 1.10.2.2 skrll /* Read and save PHY type and set PHY address */ 1138 1.10.2.2 skrll sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1139 1.10.2.2 skrll switch (sc_if->sk_phytype) { 1140 1.10.2.2 skrll case SK_PHYTYPE_XMAC: 1141 1.10.2.2 skrll sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1142 1.10.2.2 skrll break; 1143 1.10.2.2 skrll case SK_PHYTYPE_BCOM: 1144 1.10.2.2 skrll sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1145 1.10.2.2 skrll break; 1146 1.10.2.2 skrll case SK_PHYTYPE_MARV_COPPER: 1147 1.10.2.2 skrll sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1148 1.10.2.2 skrll break; 1149 1.10.2.2 skrll default: 1150 1.10.2.2 skrll aprint_error("%s: unsupported PHY type: %d\n", 1151 1.10.2.2 skrll sc->sk_dev.dv_xname, sc_if->sk_phytype); 1152 1.10.2.2 skrll return; 1153 1.10.2.2 skrll } 1154 1.10.2.2 skrll 1155 1.10.2.2 skrll /* Allocate the descriptor queues. */ 1156 1.10.2.2 skrll if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1157 1.10.2.2 skrll PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1158 1.10.2.2 skrll aprint_error("%s: can't alloc rx buffers\n", 1159 1.10.2.2 skrll sc->sk_dev.dv_xname); 1160 1.10.2.2 skrll goto fail; 1161 1.10.2.2 skrll } 1162 1.10.2.2 skrll if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1163 1.10.2.2 skrll sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1164 1.10.2.2 skrll aprint_error("%s: can't map dma buffers (%lu bytes)\n", 1165 1.10.2.2 skrll sc_if->sk_dev.dv_xname, 1166 1.10.2.2 skrll (u_long) sizeof(struct sk_ring_data)); 1167 1.10.2.2 skrll bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1168 1.10.2.2 skrll goto fail; 1169 1.10.2.2 skrll } 1170 1.10.2.2 skrll if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1171 1.10.2.2 skrll sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1172 1.10.2.2 skrll &sc_if->sk_ring_map)) { 1173 1.10.2.2 skrll aprint_error("%s: can't create dma map\n", 1174 1.10.2.2 skrll sc_if->sk_dev.dv_xname); 1175 1.10.2.2 skrll bus_dmamem_unmap(sc->sc_dmatag, kva, 1176 1.10.2.2 skrll sizeof(struct sk_ring_data)); 1177 1.10.2.2 skrll bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1178 1.10.2.2 skrll goto fail; 1179 1.10.2.2 skrll } 1180 1.10.2.2 skrll if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1181 1.10.2.2 skrll sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1182 1.10.2.2 skrll aprint_error("%s: can't load dma map\n", 1183 1.10.2.2 skrll sc_if->sk_dev.dv_xname); 1184 1.10.2.2 skrll bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1185 1.10.2.2 skrll bus_dmamem_unmap(sc->sc_dmatag, kva, 1186 1.10.2.2 skrll sizeof(struct sk_ring_data)); 1187 1.10.2.2 skrll bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1188 1.10.2.2 skrll goto fail; 1189 1.10.2.2 skrll } 1190 1.10.2.2 skrll 1191 1.10.2.2 skrll for (i = 0; i < SK_RX_RING_CNT; i++) 1192 1.10.2.2 skrll sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1193 1.10.2.2 skrll 1194 1.10.2.5 skrll SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1195 1.10.2.2 skrll for (i = 0; i < SK_TX_RING_CNT; i++) { 1196 1.10.2.2 skrll sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1197 1.10.2.2 skrll 1198 1.10.2.2 skrll if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, SK_NTXSEG, 1199 1.10.2.2 skrll MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap)) { 1200 1.10.2.2 skrll aprint_error("%s: Can't create TX dmamap\n", 1201 1.10.2.2 skrll sc_if->sk_dev.dv_xname); 1202 1.10.2.2 skrll bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1203 1.10.2.2 skrll bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1204 1.10.2.2 skrll bus_dmamem_unmap(sc->sc_dmatag, kva, 1205 1.10.2.2 skrll sizeof(struct sk_ring_data)); 1206 1.10.2.2 skrll bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1207 1.10.2.2 skrll goto fail; 1208 1.10.2.2 skrll } 1209 1.10.2.2 skrll 1210 1.10.2.2 skrll entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1211 1.10.2.2 skrll if (!entry) { 1212 1.10.2.2 skrll aprint_error("%s: Can't alloc txmap entry\n", 1213 1.10.2.2 skrll sc_if->sk_dev.dv_xname); 1214 1.10.2.2 skrll bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1215 1.10.2.2 skrll bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1216 1.10.2.2 skrll bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1217 1.10.2.2 skrll bus_dmamem_unmap(sc->sc_dmatag, kva, 1218 1.10.2.2 skrll sizeof(struct sk_ring_data)); 1219 1.10.2.2 skrll bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1220 1.10.2.2 skrll goto fail; 1221 1.10.2.2 skrll } 1222 1.10.2.2 skrll entry->dmamap = dmamap; 1223 1.10.2.5 skrll SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1224 1.10.2.2 skrll } 1225 1.10.2.2 skrll 1226 1.10.2.2 skrll sc_if->sk_rdata = (struct sk_ring_data *)kva; 1227 1.10.2.2 skrll bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1228 1.10.2.2 skrll 1229 1.10.2.2 skrll /* XXX TLS It's not clear what's wrong with the Jumbo MTU 1230 1.10.2.2 skrll XXX TLS support in this driver, so we don't enable it. */ 1231 1.10.2.2 skrll 1232 1.10.2.2 skrll sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1233 1.10.2.2 skrll 1234 1.10.2.2 skrll ifp = &sc_if->sk_ethercom.ec_if; 1235 1.10.2.2 skrll ifp->if_softc = sc_if; 1236 1.10.2.2 skrll ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1237 1.10.2.2 skrll ifp->if_ioctl = sk_ioctl; 1238 1.10.2.2 skrll ifp->if_start = sk_start; 1239 1.10.2.2 skrll ifp->if_stop = sk_stop; 1240 1.10.2.2 skrll ifp->if_init = sk_init; 1241 1.10.2.2 skrll ifp->if_watchdog = sk_watchdog; 1242 1.10.2.2 skrll ifp->if_capabilities = 0; 1243 1.10.2.2 skrll IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1244 1.10.2.2 skrll IFQ_SET_READY(&ifp->if_snd); 1245 1.10.2.2 skrll strcpy(ifp->if_xname, sc_if->sk_dev.dv_xname); 1246 1.10.2.2 skrll 1247 1.10.2.2 skrll /* 1248 1.10.2.2 skrll * Do miibus setup. 1249 1.10.2.2 skrll */ 1250 1.10.2.2 skrll switch (sc->sk_type) { 1251 1.10.2.2 skrll case SK_GENESIS: 1252 1.10.2.2 skrll sk_init_xmac(sc_if); 1253 1.10.2.2 skrll break; 1254 1.10.2.2 skrll case SK_YUKON: 1255 1.10.2.5 skrll case SK_YUKON_LITE: 1256 1.10.2.5 skrll case SK_YUKON_LP: 1257 1.10.2.2 skrll sk_init_yukon(sc_if); 1258 1.10.2.2 skrll break; 1259 1.10.2.2 skrll default: 1260 1.10.2.2 skrll panic("%s: unknown device type %d", sc->sk_dev.dv_xname, 1261 1.10.2.2 skrll sc->sk_type); 1262 1.10.2.2 skrll } 1263 1.10.2.2 skrll 1264 1.10.2.2 skrll DPRINTFN(2, ("sk_attach: 1\n")); 1265 1.10.2.2 skrll 1266 1.10.2.2 skrll sc_if->sk_mii.mii_ifp = ifp; 1267 1.10.2.2 skrll switch (sc->sk_type) { 1268 1.10.2.2 skrll case SK_GENESIS: 1269 1.10.2.2 skrll sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1270 1.10.2.2 skrll sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1271 1.10.2.2 skrll sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1272 1.10.2.2 skrll break; 1273 1.10.2.2 skrll case SK_YUKON: 1274 1.10.2.5 skrll case SK_YUKON_LITE: 1275 1.10.2.5 skrll case SK_YUKON_LP: 1276 1.10.2.2 skrll sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1277 1.10.2.2 skrll sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1278 1.10.2.2 skrll sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1279 1.10.2.2 skrll break; 1280 1.10.2.2 skrll } 1281 1.10.2.2 skrll 1282 1.10.2.2 skrll ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1283 1.10.2.2 skrll sk_ifmedia_upd, sk_ifmedia_sts); 1284 1.10.2.2 skrll mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1285 1.10.2.2 skrll MII_OFFSET_ANY, 0); 1286 1.10.2.2 skrll if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1287 1.10.2.2 skrll printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1288 1.10.2.2 skrll ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1289 1.10.2.2 skrll 0, NULL); 1290 1.10.2.2 skrll ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1291 1.10.2.2 skrll } 1292 1.10.2.2 skrll else 1293 1.10.2.2 skrll ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1294 1.10.2.2 skrll 1295 1.10.2.2 skrll callout_init(&sc_if->sk_tick_ch); 1296 1.10.2.2 skrll callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1297 1.10.2.2 skrll 1298 1.10.2.2 skrll DPRINTFN(2, ("sk_attach: 1\n")); 1299 1.10.2.2 skrll 1300 1.10.2.2 skrll /* 1301 1.10.2.2 skrll * Call MI attach routines. 1302 1.10.2.2 skrll */ 1303 1.10.2.2 skrll if_attach(ifp); 1304 1.10.2.2 skrll 1305 1.10.2.2 skrll ether_ifattach(ifp, sc_if->sk_enaddr); 1306 1.10.2.2 skrll 1307 1.10.2.2 skrll #if NRND > 0 1308 1.10.2.2 skrll rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1309 1.10.2.2 skrll RND_TYPE_NET, 0); 1310 1.10.2.2 skrll #endif 1311 1.10.2.2 skrll 1312 1.10.2.2 skrll DPRINTFN(2, ("sk_attach: end\n")); 1313 1.10.2.2 skrll 1314 1.10.2.2 skrll return; 1315 1.10.2.2 skrll 1316 1.10.2.2 skrll fail: 1317 1.10.2.2 skrll sc->sk_if[sa->skc_port] = NULL; 1318 1.10.2.2 skrll } 1319 1.10.2.2 skrll 1320 1.10.2.2 skrll int 1321 1.10.2.2 skrll skcprint(void *aux, const char *pnp) 1322 1.10.2.2 skrll { 1323 1.10.2.2 skrll struct skc_attach_args *sa = aux; 1324 1.10.2.2 skrll 1325 1.10.2.2 skrll if (pnp) 1326 1.10.2.2 skrll aprint_normal("sk port %c at %s", 1327 1.10.2.2 skrll (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1328 1.10.2.2 skrll else 1329 1.10.2.2 skrll aprint_normal(" port %c", 1330 1.10.2.2 skrll (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1331 1.10.2.2 skrll return (UNCONF); 1332 1.10.2.2 skrll } 1333 1.10.2.2 skrll 1334 1.10.2.2 skrll /* 1335 1.10.2.2 skrll * Attach the interface. Allocate softc structures, do ifmedia 1336 1.10.2.2 skrll * setup and ethernet/BPF attach. 1337 1.10.2.2 skrll */ 1338 1.10.2.2 skrll void 1339 1.10.2.2 skrll skc_attach(struct device *parent, struct device *self, void *aux) 1340 1.10.2.2 skrll { 1341 1.10.2.2 skrll struct sk_softc *sc = (struct sk_softc *)self; 1342 1.10.2.2 skrll struct pci_attach_args *pa = aux; 1343 1.10.2.2 skrll struct skc_attach_args skca; 1344 1.10.2.2 skrll pci_chipset_tag_t pc = pa->pa_pc; 1345 1.10.2.2 skrll pcireg_t memtype; 1346 1.10.2.2 skrll pci_intr_handle_t ih; 1347 1.10.2.2 skrll const char *intrstr = NULL; 1348 1.10.2.2 skrll bus_addr_t iobase; 1349 1.10.2.2 skrll bus_size_t iosize; 1350 1.10.2.2 skrll int s; 1351 1.10.2.2 skrll u_int32_t command; 1352 1.10.2.9 skrll const char *revstr; 1353 1.10.2.2 skrll 1354 1.10.2.2 skrll DPRINTFN(2, ("begin skc_attach\n")); 1355 1.10.2.2 skrll 1356 1.10.2.2 skrll s = splnet(); 1357 1.10.2.2 skrll 1358 1.10.2.2 skrll /* 1359 1.10.2.2 skrll * Handle power management nonsense. 1360 1.10.2.2 skrll */ 1361 1.10.2.2 skrll command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1362 1.10.2.2 skrll 1363 1.10.2.2 skrll if (command == 0x01) { 1364 1.10.2.2 skrll command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1365 1.10.2.2 skrll if (command & SK_PSTATE_MASK) { 1366 1.10.2.9 skrll u_int32_t xiobase, membase, irq; 1367 1.10.2.2 skrll 1368 1.10.2.2 skrll /* Save important PCI config data. */ 1369 1.10.2.9 skrll xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1370 1.10.2.2 skrll membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1371 1.10.2.2 skrll irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1372 1.10.2.2 skrll 1373 1.10.2.2 skrll /* Reset the power state. */ 1374 1.10.2.2 skrll aprint_normal("%s chip is in D%d power mode " 1375 1.10.2.2 skrll "-- setting to D0\n", sc->sk_dev.dv_xname, 1376 1.10.2.2 skrll command & SK_PSTATE_MASK); 1377 1.10.2.2 skrll command &= 0xFFFFFFFC; 1378 1.10.2.2 skrll pci_conf_write(pc, pa->pa_tag, 1379 1.10.2.2 skrll SK_PCI_PWRMGMTCTRL, command); 1380 1.10.2.2 skrll 1381 1.10.2.2 skrll /* Restore PCI config data. */ 1382 1.10.2.9 skrll pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1383 1.10.2.2 skrll pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1384 1.10.2.2 skrll pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1385 1.10.2.2 skrll } 1386 1.10.2.2 skrll } 1387 1.10.2.2 skrll 1388 1.10.2.2 skrll /* 1389 1.10.2.2 skrll * Map control/status registers. 1390 1.10.2.2 skrll */ 1391 1.10.2.2 skrll command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1392 1.10.2.2 skrll command |= PCI_COMMAND_IO_ENABLE | 1393 1.10.2.2 skrll PCI_COMMAND_MEM_ENABLE | 1394 1.10.2.2 skrll PCI_COMMAND_MASTER_ENABLE; 1395 1.10.2.2 skrll pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1396 1.10.2.2 skrll command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1397 1.10.2.2 skrll 1398 1.10.2.2 skrll #ifdef SK_USEIOSPACE 1399 1.10.2.2 skrll if (!(command & PCI_COMMAND_IO_ENABLE)) { 1400 1.10.2.2 skrll aprint_error(": failed to enable I/O ports!\n"); 1401 1.10.2.2 skrll goto fail; 1402 1.10.2.2 skrll } 1403 1.10.2.2 skrll /* 1404 1.10.2.2 skrll * Map control/status registers. 1405 1.10.2.2 skrll */ 1406 1.10.2.2 skrll if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1407 1.10.2.2 skrll &iobase, &iosize)) { 1408 1.10.2.2 skrll aprint_error(": can't find i/o space\n"); 1409 1.10.2.2 skrll goto fail; 1410 1.10.2.2 skrll } 1411 1.10.2.2 skrll #else 1412 1.10.2.2 skrll if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1413 1.10.2.2 skrll aprint_error(": failed to enable memory mapping!\n"); 1414 1.10.2.2 skrll goto fail; 1415 1.10.2.2 skrll } 1416 1.10.2.2 skrll memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1417 1.10.2.2 skrll switch (memtype) { 1418 1.10.2.2 skrll case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1419 1.10.2.2 skrll case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1420 1.10.2.2 skrll if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1421 1.10.2.2 skrll memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1422 1.10.2.2 skrll &iobase, &iosize) == 0) 1423 1.10.2.2 skrll break; 1424 1.10.2.2 skrll default: 1425 1.10.2.2 skrll aprint_error("%s: can't find mem space\n", 1426 1.10.2.2 skrll sc->sk_dev.dv_xname); 1427 1.10.2.2 skrll return; 1428 1.10.2.2 skrll } 1429 1.10.2.2 skrll 1430 1.10.2.2 skrll DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1431 1.10.2.2 skrll #endif 1432 1.10.2.2 skrll sc->sc_dmatag = pa->pa_dmat; 1433 1.10.2.2 skrll 1434 1.10.2.5 skrll sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1435 1.10.2.5 skrll sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1436 1.10.2.5 skrll 1437 1.10.2.5 skrll /* bail out here if chip is not recognized */ 1438 1.10.2.5 skrll if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1439 1.10.2.5 skrll aprint_error("%s: unknown chip type\n",sc->sk_dev.dv_xname); 1440 1.10.2.5 skrll goto fail; 1441 1.10.2.5 skrll } 1442 1.10.2.2 skrll DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1443 1.10.2.2 skrll 1444 1.10.2.2 skrll /* Allocate interrupt */ 1445 1.10.2.2 skrll if (pci_intr_map(pa, &ih)) { 1446 1.10.2.2 skrll aprint_error(": couldn't map interrupt\n"); 1447 1.10.2.2 skrll goto fail; 1448 1.10.2.2 skrll } 1449 1.10.2.2 skrll 1450 1.10.2.2 skrll intrstr = pci_intr_string(pc, ih); 1451 1.10.2.2 skrll sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1452 1.10.2.2 skrll if (sc->sk_intrhand == NULL) { 1453 1.10.2.2 skrll aprint_error(": couldn't establish interrupt"); 1454 1.10.2.2 skrll if (intrstr != NULL) 1455 1.10.2.2 skrll aprint_normal(" at %s", intrstr); 1456 1.10.2.2 skrll goto fail; 1457 1.10.2.2 skrll } 1458 1.10.2.2 skrll aprint_normal(": %s\n", intrstr); 1459 1.10.2.2 skrll 1460 1.10.2.2 skrll /* Reset the adapter. */ 1461 1.10.2.2 skrll sk_reset(sc); 1462 1.10.2.2 skrll 1463 1.10.2.2 skrll /* Read and save vital product data from EEPROM. */ 1464 1.10.2.2 skrll sk_vpd_read(sc); 1465 1.10.2.2 skrll 1466 1.10.2.2 skrll if (sc->sk_type == SK_GENESIS) { 1467 1.10.2.2 skrll u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1468 1.10.2.2 skrll /* Read and save RAM size and RAMbuffer offset */ 1469 1.10.2.2 skrll switch(val) { 1470 1.10.2.2 skrll case SK_RAMSIZE_512K_64: 1471 1.10.2.2 skrll sc->sk_ramsize = 0x80000; 1472 1.10.2.2 skrll sc->sk_rboff = SK_RBOFF_0; 1473 1.10.2.2 skrll break; 1474 1.10.2.2 skrll case SK_RAMSIZE_1024K_64: 1475 1.10.2.2 skrll sc->sk_ramsize = 0x100000; 1476 1.10.2.2 skrll sc->sk_rboff = SK_RBOFF_80000; 1477 1.10.2.2 skrll break; 1478 1.10.2.2 skrll case SK_RAMSIZE_1024K_128: 1479 1.10.2.2 skrll sc->sk_ramsize = 0x100000; 1480 1.10.2.2 skrll sc->sk_rboff = SK_RBOFF_0; 1481 1.10.2.2 skrll break; 1482 1.10.2.2 skrll case SK_RAMSIZE_2048K_128: 1483 1.10.2.2 skrll sc->sk_ramsize = 0x200000; 1484 1.10.2.2 skrll sc->sk_rboff = SK_RBOFF_0; 1485 1.10.2.2 skrll break; 1486 1.10.2.2 skrll default: 1487 1.10.2.2 skrll aprint_error("%s: unknown ram size: %d\n", 1488 1.10.2.2 skrll sc->sk_dev.dv_xname, val); 1489 1.10.2.2 skrll goto fail; 1490 1.10.2.2 skrll break; 1491 1.10.2.2 skrll } 1492 1.10.2.2 skrll 1493 1.10.2.2 skrll DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1494 1.10.2.2 skrll sc->sk_ramsize, sc->sk_ramsize / 1024, 1495 1.10.2.2 skrll sc->sk_rboff)); 1496 1.10.2.2 skrll } else { 1497 1.10.2.5 skrll u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1498 1.10.2.5 skrll sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1499 1.10.2.2 skrll sc->sk_rboff = SK_RBOFF_0; 1500 1.10.2.2 skrll 1501 1.10.2.2 skrll DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1502 1.10.2.2 skrll sc->sk_ramsize / 1024, sc->sk_ramsize, 1503 1.10.2.2 skrll sc->sk_rboff)); 1504 1.10.2.2 skrll } 1505 1.10.2.2 skrll 1506 1.10.2.2 skrll /* Read and save physical media type */ 1507 1.10.2.2 skrll switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1508 1.10.2.2 skrll case SK_PMD_1000BASESX: 1509 1.10.2.2 skrll sc->sk_pmd = IFM_1000_SX; 1510 1.10.2.2 skrll break; 1511 1.10.2.2 skrll case SK_PMD_1000BASELX: 1512 1.10.2.2 skrll sc->sk_pmd = IFM_1000_LX; 1513 1.10.2.2 skrll break; 1514 1.10.2.2 skrll case SK_PMD_1000BASECX: 1515 1.10.2.2 skrll sc->sk_pmd = IFM_1000_CX; 1516 1.10.2.2 skrll break; 1517 1.10.2.2 skrll case SK_PMD_1000BASETX: 1518 1.10.2.2 skrll sc->sk_pmd = IFM_1000_T; 1519 1.10.2.2 skrll break; 1520 1.10.2.2 skrll default: 1521 1.10.2.2 skrll aprint_error("%s: unknown media type: 0x%x\n", 1522 1.10.2.2 skrll sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1523 1.10.2.2 skrll goto fail; 1524 1.10.2.2 skrll } 1525 1.10.2.2 skrll 1526 1.10.2.5 skrll /* determine whether to name it with vpd or just make it up */ 1527 1.10.2.5 skrll /* Marvell Yukon VPD's can freqently be bogus */ 1528 1.10.2.5 skrll 1529 1.10.2.5 skrll switch (pa->pa_id) { 1530 1.10.2.5 skrll case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1531 1.10.2.5 skrll PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1532 1.10.2.5 skrll case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1533 1.10.2.5 skrll case PCI_PRODUCT_3COM_3C940: 1534 1.10.2.5 skrll case PCI_PRODUCT_DLINK_DGE530T: 1535 1.10.2.5 skrll case PCI_PRODUCT_LINKSYS_EG1032: 1536 1.10.2.5 skrll case PCI_PRODUCT_LINKSYS_EG1064: 1537 1.10.2.5 skrll case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1538 1.10.2.5 skrll PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1539 1.10.2.5 skrll case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1540 1.10.2.5 skrll case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1541 1.10.2.5 skrll case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1542 1.10.2.5 skrll case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1543 1.10.2.5 skrll sc->sk_name = sc->sk_vpd_prodname; 1544 1.10.2.5 skrll break; 1545 1.10.2.5 skrll case PCI_ID_CODE(PCI_VENDOR_GALILEO,PCI_PRODUCT_GALILEO_SKNET): 1546 1.10.2.5 skrll /* whoops yukon vpd prodname bears no resemblance to reality */ 1547 1.10.2.5 skrll switch (sc->sk_type) { 1548 1.10.2.5 skrll case SK_GENESIS: 1549 1.10.2.5 skrll sc->sk_name = sc->sk_vpd_prodname; 1550 1.10.2.5 skrll break; 1551 1.10.2.5 skrll case SK_YUKON: 1552 1.10.2.5 skrll sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1553 1.10.2.5 skrll break; 1554 1.10.2.5 skrll case SK_YUKON_LITE: 1555 1.10.2.5 skrll sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1556 1.10.2.5 skrll break; 1557 1.10.2.5 skrll case SK_YUKON_LP: 1558 1.10.2.5 skrll sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1559 1.10.2.5 skrll break; 1560 1.10.2.5 skrll default: 1561 1.10.2.5 skrll sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1562 1.10.2.5 skrll } 1563 1.10.2.5 skrll 1564 1.10.2.5 skrll /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1565 1.10.2.5 skrll 1566 1.10.2.5 skrll if ( sc->sk_type == SK_YUKON ) { 1567 1.10.2.5 skrll uint32_t flashaddr; 1568 1.10.2.5 skrll uint8_t testbyte; 1569 1.10.2.8 skrll 1570 1.10.2.5 skrll flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1571 1.10.2.8 skrll 1572 1.10.2.5 skrll /* test Flash-Address Register */ 1573 1.10.2.5 skrll sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1574 1.10.2.5 skrll testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1575 1.10.2.8 skrll 1576 1.10.2.5 skrll if (testbyte != 0) { 1577 1.10.2.5 skrll /* this is yukon lite Rev. A0 */ 1578 1.10.2.5 skrll sc->sk_type = SK_YUKON_LITE; 1579 1.10.2.5 skrll sc->sk_rev = SK_YUKON_LITE_REV_A0; 1580 1.10.2.5 skrll /* restore Flash-Address Register */ 1581 1.10.2.5 skrll sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1582 1.10.2.5 skrll } 1583 1.10.2.5 skrll } 1584 1.10.2.5 skrll break; 1585 1.10.2.7 skrll case PCI_ID_CODE(PCI_VENDOR_GALILEO,PCI_PRODUCT_GALILEO_BELKIN): 1586 1.10.2.7 skrll sc->sk_name = sc->sk_vpd_prodname; 1587 1.10.2.7 skrll break; 1588 1.10.2.5 skrll default: 1589 1.10.2.5 skrll sc->sk_name = "Unkown Marvell"; 1590 1.10.2.5 skrll } 1591 1.10.2.5 skrll 1592 1.10.2.8 skrll 1593 1.10.2.5 skrll if ( sc->sk_type == SK_YUKON_LITE ) { 1594 1.10.2.5 skrll switch (sc->sk_rev) { 1595 1.10.2.5 skrll case SK_YUKON_LITE_REV_A0: 1596 1.10.2.5 skrll revstr = "A0"; 1597 1.10.2.5 skrll break; 1598 1.10.2.5 skrll case SK_YUKON_LITE_REV_A1: 1599 1.10.2.5 skrll revstr = "A1"; 1600 1.10.2.5 skrll break; 1601 1.10.2.5 skrll case SK_YUKON_LITE_REV_A3: 1602 1.10.2.5 skrll revstr = "A3"; 1603 1.10.2.5 skrll break; 1604 1.10.2.5 skrll default: 1605 1.10.2.5 skrll revstr = ""; 1606 1.10.2.5 skrll } 1607 1.10.2.5 skrll } else { 1608 1.10.2.5 skrll revstr = ""; 1609 1.10.2.5 skrll } 1610 1.10.2.5 skrll 1611 1.10.2.2 skrll /* Announce the product name. */ 1612 1.10.2.5 skrll aprint_normal("%s: %s rev. %s(0x%x)\n", sc->sk_dev.dv_xname, 1613 1.10.2.5 skrll sc->sk_name, revstr, sc->sk_rev); 1614 1.10.2.2 skrll 1615 1.10.2.2 skrll skca.skc_port = SK_PORT_A; 1616 1.10.2.2 skrll (void)config_found(&sc->sk_dev, &skca, skcprint); 1617 1.10.2.2 skrll 1618 1.10.2.2 skrll if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1619 1.10.2.2 skrll skca.skc_port = SK_PORT_B; 1620 1.10.2.2 skrll (void)config_found(&sc->sk_dev, &skca, skcprint); 1621 1.10.2.2 skrll } 1622 1.10.2.2 skrll 1623 1.10.2.2 skrll /* Turn on the 'driver is loaded' LED. */ 1624 1.10.2.2 skrll CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1625 1.10.2.2 skrll 1626 1.10.2.2 skrll fail: 1627 1.10.2.2 skrll splx(s); 1628 1.10.2.2 skrll } 1629 1.10.2.2 skrll 1630 1.10.2.2 skrll int 1631 1.10.2.2 skrll sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1632 1.10.2.2 skrll { 1633 1.10.2.2 skrll struct sk_softc *sc = sc_if->sk_softc; 1634 1.10.2.2 skrll struct sk_tx_desc *f = NULL; 1635 1.10.2.2 skrll u_int32_t frag, cur, cnt = 0; 1636 1.10.2.2 skrll int i; 1637 1.10.2.2 skrll struct sk_txmap_entry *entry; 1638 1.10.2.2 skrll bus_dmamap_t txmap; 1639 1.10.2.2 skrll 1640 1.10.2.2 skrll DPRINTFN(3, ("sk_encap\n")); 1641 1.10.2.2 skrll 1642 1.10.2.5 skrll entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1643 1.10.2.2 skrll if (entry == NULL) { 1644 1.10.2.2 skrll DPRINTFN(3, ("sk_encap: no txmap available\n")); 1645 1.10.2.2 skrll return ENOBUFS; 1646 1.10.2.2 skrll } 1647 1.10.2.2 skrll txmap = entry->dmamap; 1648 1.10.2.2 skrll 1649 1.10.2.2 skrll cur = frag = *txidx; 1650 1.10.2.2 skrll 1651 1.10.2.2 skrll #ifdef SK_DEBUG 1652 1.10.2.2 skrll if (skdebug >= 3) 1653 1.10.2.2 skrll sk_dump_mbuf(m_head); 1654 1.10.2.2 skrll #endif 1655 1.10.2.2 skrll 1656 1.10.2.2 skrll /* 1657 1.10.2.2 skrll * Start packing the mbufs in this chain into 1658 1.10.2.2 skrll * the fragment pointers. Stop when we run out 1659 1.10.2.2 skrll * of fragments or hit the end of the mbuf chain. 1660 1.10.2.2 skrll */ 1661 1.10.2.2 skrll if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1662 1.10.2.2 skrll BUS_DMA_NOWAIT)) { 1663 1.10.2.2 skrll DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1664 1.10.2.2 skrll return(ENOBUFS); 1665 1.10.2.2 skrll } 1666 1.10.2.2 skrll 1667 1.10.2.2 skrll DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1668 1.10.2.2 skrll 1669 1.10.2.2 skrll /* Sync the DMA map. */ 1670 1.10.2.2 skrll bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1671 1.10.2.2 skrll BUS_DMASYNC_PREWRITE); 1672 1.10.2.2 skrll 1673 1.10.2.2 skrll for (i = 0; i < txmap->dm_nsegs; i++) { 1674 1.10.2.2 skrll if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1675 1.10.2.2 skrll DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1676 1.10.2.2 skrll return(ENOBUFS); 1677 1.10.2.2 skrll } 1678 1.10.2.2 skrll f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1679 1.10.2.2 skrll f->sk_data_lo = txmap->dm_segs[i].ds_addr; 1680 1.10.2.2 skrll f->sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1681 1.10.2.2 skrll if (cnt == 0) 1682 1.10.2.2 skrll f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1683 1.10.2.2 skrll else 1684 1.10.2.2 skrll f->sk_ctl |= SK_TXCTL_OWN; 1685 1.10.2.2 skrll 1686 1.10.2.2 skrll cur = frag; 1687 1.10.2.2 skrll SK_INC(frag, SK_TX_RING_CNT); 1688 1.10.2.2 skrll cnt++; 1689 1.10.2.2 skrll } 1690 1.10.2.2 skrll 1691 1.10.2.2 skrll sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1692 1.10.2.5 skrll SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1693 1.10.2.5 skrll 1694 1.10.2.2 skrll sc_if->sk_cdata.sk_tx_map[cur] = entry; 1695 1.10.2.2 skrll sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1696 1.10.2.2 skrll SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1697 1.10.2.2 skrll 1698 1.10.2.2 skrll /* Sync descriptors before handing to chip */ 1699 1.10.2.2 skrll SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1700 1.10.2.2 skrll BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1701 1.10.2.2 skrll 1702 1.10.2.2 skrll sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1703 1.10.2.2 skrll 1704 1.10.2.2 skrll /* Sync first descriptor to hand it off */ 1705 1.10.2.2 skrll SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1706 1.10.2.2 skrll 1707 1.10.2.2 skrll sc_if->sk_cdata.sk_tx_cnt += cnt; 1708 1.10.2.2 skrll 1709 1.10.2.2 skrll #ifdef SK_DEBUG 1710 1.10.2.2 skrll if (skdebug >= 3) { 1711 1.10.2.2 skrll struct sk_tx_desc *desc; 1712 1.10.2.2 skrll u_int32_t idx; 1713 1.10.2.2 skrll for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1714 1.10.2.2 skrll desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1715 1.10.2.2 skrll sk_dump_txdesc(desc, idx); 1716 1.10.2.2 skrll } 1717 1.10.2.2 skrll } 1718 1.10.2.2 skrll #endif 1719 1.10.2.2 skrll 1720 1.10.2.2 skrll *txidx = frag; 1721 1.10.2.2 skrll 1722 1.10.2.2 skrll DPRINTFN(3, ("sk_encap: completed successfully\n")); 1723 1.10.2.2 skrll 1724 1.10.2.2 skrll return(0); 1725 1.10.2.2 skrll } 1726 1.10.2.2 skrll 1727 1.10.2.2 skrll void 1728 1.10.2.2 skrll sk_start(struct ifnet *ifp) 1729 1.10.2.2 skrll { 1730 1.10.2.2 skrll struct sk_if_softc *sc_if = ifp->if_softc; 1731 1.10.2.2 skrll struct sk_softc *sc = sc_if->sk_softc; 1732 1.10.2.2 skrll struct mbuf *m_head = NULL; 1733 1.10.2.2 skrll u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1734 1.10.2.2 skrll int pkts = 0; 1735 1.10.2.2 skrll 1736 1.10.2.2 skrll DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1737 1.10.2.2 skrll sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1738 1.10.2.2 skrll 1739 1.10.2.2 skrll while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1740 1.10.2.2 skrll 1741 1.10.2.2 skrll IFQ_POLL(&ifp->if_snd, m_head); 1742 1.10.2.2 skrll if (m_head == NULL) 1743 1.10.2.2 skrll break; 1744 1.10.2.2 skrll 1745 1.10.2.2 skrll /* 1746 1.10.2.2 skrll * Pack the data into the transmit ring. If we 1747 1.10.2.2 skrll * don't have room, set the OACTIVE flag and wait 1748 1.10.2.2 skrll * for the NIC to drain the ring. 1749 1.10.2.2 skrll */ 1750 1.10.2.2 skrll if (sk_encap(sc_if, m_head, &idx)) { 1751 1.10.2.2 skrll ifp->if_flags |= IFF_OACTIVE; 1752 1.10.2.2 skrll break; 1753 1.10.2.2 skrll } 1754 1.10.2.2 skrll 1755 1.10.2.2 skrll /* now we are committed to transmit the packet */ 1756 1.10.2.2 skrll IFQ_DEQUEUE(&ifp->if_snd, m_head); 1757 1.10.2.2 skrll pkts++; 1758 1.10.2.2 skrll 1759 1.10.2.2 skrll /* 1760 1.10.2.2 skrll * If there's a BPF listener, bounce a copy of this frame 1761 1.10.2.2 skrll * to him. 1762 1.10.2.2 skrll */ 1763 1.10.2.2 skrll #if NBPFILTER > 0 1764 1.10.2.2 skrll if (ifp->if_bpf) 1765 1.10.2.2 skrll bpf_mtap(ifp->if_bpf, m_head); 1766 1.10.2.2 skrll #endif 1767 1.10.2.2 skrll } 1768 1.10.2.2 skrll if (pkts == 0) 1769 1.10.2.2 skrll return; 1770 1.10.2.2 skrll 1771 1.10.2.2 skrll /* Transmit */ 1772 1.10.2.10 christos if (idx != sc_if->sk_cdata.sk_tx_prod) { 1773 1.10.2.10 christos sc_if->sk_cdata.sk_tx_prod = idx; 1774 1.10.2.10 christos CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1775 1.10.2.2 skrll 1776 1.10.2.10 christos /* Set a timeout in case the chip goes out to lunch. */ 1777 1.10.2.10 christos ifp->if_timer = 5; 1778 1.10.2.10 christos } 1779 1.10.2.2 skrll } 1780 1.10.2.2 skrll 1781 1.10.2.2 skrll 1782 1.10.2.2 skrll void 1783 1.10.2.2 skrll sk_watchdog(struct ifnet *ifp) 1784 1.10.2.2 skrll { 1785 1.10.2.2 skrll struct sk_if_softc *sc_if = ifp->if_softc; 1786 1.10.2.2 skrll 1787 1.10.2.2 skrll printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1788 1.10.2.2 skrll (void) sk_init(ifp); 1789 1.10.2.2 skrll } 1790 1.10.2.2 skrll 1791 1.10.2.2 skrll void 1792 1.10.2.2 skrll sk_shutdown(void * v) 1793 1.10.2.2 skrll { 1794 1.10.2.2 skrll struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 1795 1.10.2.2 skrll struct sk_softc *sc = sc_if->sk_softc; 1796 1.10.2.2 skrll struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1797 1.10.2.2 skrll 1798 1.10.2.2 skrll DPRINTFN(2, ("sk_shutdown\n")); 1799 1.10.2.2 skrll sk_stop(ifp,1); 1800 1.10.2.2 skrll 1801 1.10.2.2 skrll /* Turn off the 'driver is loaded' LED. */ 1802 1.10.2.2 skrll CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1803 1.10.2.2 skrll 1804 1.10.2.2 skrll /* 1805 1.10.2.2 skrll * Reset the GEnesis controller. Doing this should also 1806 1.10.2.2 skrll * assert the resets on the attached XMAC(s). 1807 1.10.2.2 skrll */ 1808 1.10.2.2 skrll sk_reset(sc); 1809 1.10.2.2 skrll } 1810 1.10.2.2 skrll 1811 1.10.2.2 skrll void 1812 1.10.2.2 skrll sk_rxeof(struct sk_if_softc *sc_if) 1813 1.10.2.2 skrll { 1814 1.10.2.2 skrll struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1815 1.10.2.2 skrll struct mbuf *m; 1816 1.10.2.2 skrll struct sk_chain *cur_rx; 1817 1.10.2.2 skrll struct sk_rx_desc *cur_desc; 1818 1.10.2.2 skrll int i, cur, total_len = 0; 1819 1.10.2.2 skrll u_int32_t rxstat; 1820 1.10.2.2 skrll bus_dmamap_t dmamap; 1821 1.10.2.2 skrll 1822 1.10.2.2 skrll i = sc_if->sk_cdata.sk_rx_prod; 1823 1.10.2.2 skrll 1824 1.10.2.2 skrll DPRINTFN(3, ("sk_rxeof %d\n", i)); 1825 1.10.2.2 skrll 1826 1.10.2.2 skrll for (;;) { 1827 1.10.2.2 skrll cur = i; 1828 1.10.2.2 skrll 1829 1.10.2.2 skrll /* Sync the descriptor */ 1830 1.10.2.2 skrll SK_CDRXSYNC(sc_if, cur, 1831 1.10.2.2 skrll BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1832 1.10.2.2 skrll 1833 1.10.2.2 skrll if (sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl & SK_RXCTL_OWN) { 1834 1.10.2.2 skrll /* Invalidate the descriptor -- it's not ready yet */ 1835 1.10.2.2 skrll SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 1836 1.10.2.2 skrll sc_if->sk_cdata.sk_rx_prod = i; 1837 1.10.2.2 skrll break; 1838 1.10.2.2 skrll } 1839 1.10.2.2 skrll 1840 1.10.2.2 skrll cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1841 1.10.2.2 skrll cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 1842 1.10.2.2 skrll dmamap = sc_if->sk_cdata.sk_rx_map[cur]; 1843 1.10.2.2 skrll 1844 1.10.2.2 skrll bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1845 1.10.2.2 skrll dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1846 1.10.2.2 skrll 1847 1.10.2.2 skrll rxstat = cur_desc->sk_xmac_rxstat; 1848 1.10.2.2 skrll m = cur_rx->sk_mbuf; 1849 1.10.2.2 skrll cur_rx->sk_mbuf = NULL; 1850 1.10.2.2 skrll total_len = SK_RXBYTES(cur_desc->sk_ctl); 1851 1.10.2.2 skrll 1852 1.10.2.2 skrll sc_if->sk_cdata.sk_rx_map[cur] = 0; 1853 1.10.2.2 skrll 1854 1.10.2.2 skrll SK_INC(i, SK_RX_RING_CNT); 1855 1.10.2.2 skrll 1856 1.10.2.2 skrll if (rxstat & XM_RXSTAT_ERRFRAME) { 1857 1.10.2.2 skrll ifp->if_ierrors++; 1858 1.10.2.2 skrll sk_newbuf(sc_if, cur, m, dmamap); 1859 1.10.2.2 skrll continue; 1860 1.10.2.2 skrll } 1861 1.10.2.2 skrll 1862 1.10.2.2 skrll /* 1863 1.10.2.2 skrll * Try to allocate a new jumbo buffer. If that 1864 1.10.2.2 skrll * fails, copy the packet to mbufs and put the 1865 1.10.2.2 skrll * jumbo buffer back in the ring so it can be 1866 1.10.2.2 skrll * re-used. If allocating mbufs fails, then we 1867 1.10.2.2 skrll * have to drop the packet. 1868 1.10.2.2 skrll */ 1869 1.10.2.2 skrll if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1870 1.10.2.2 skrll struct mbuf *m0; 1871 1.10.2.2 skrll m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1872 1.10.2.2 skrll total_len + ETHER_ALIGN, 0, ifp, NULL); 1873 1.10.2.2 skrll sk_newbuf(sc_if, cur, m, dmamap); 1874 1.10.2.2 skrll if (m0 == NULL) { 1875 1.10.2.2 skrll printf("%s: no receive buffers " 1876 1.10.2.2 skrll "available -- packet dropped!\n", 1877 1.10.2.2 skrll sc_if->sk_dev.dv_xname); 1878 1.10.2.2 skrll ifp->if_ierrors++; 1879 1.10.2.2 skrll continue; 1880 1.10.2.2 skrll } 1881 1.10.2.2 skrll m_adj(m0, ETHER_ALIGN); 1882 1.10.2.2 skrll m = m0; 1883 1.10.2.2 skrll } else { 1884 1.10.2.2 skrll m->m_pkthdr.rcvif = ifp; 1885 1.10.2.2 skrll m->m_pkthdr.len = m->m_len = total_len; 1886 1.10.2.2 skrll } 1887 1.10.2.2 skrll 1888 1.10.2.2 skrll ifp->if_ipackets++; 1889 1.10.2.2 skrll 1890 1.10.2.2 skrll #if NBPFILTER > 0 1891 1.10.2.2 skrll if (ifp->if_bpf) 1892 1.10.2.2 skrll bpf_mtap(ifp->if_bpf, m); 1893 1.10.2.2 skrll #endif 1894 1.10.2.2 skrll /* pass it on. */ 1895 1.10.2.2 skrll (*ifp->if_input)(ifp, m); 1896 1.10.2.2 skrll } 1897 1.10.2.2 skrll } 1898 1.10.2.2 skrll 1899 1.10.2.2 skrll void 1900 1.10.2.2 skrll sk_txeof(struct sk_if_softc *sc_if) 1901 1.10.2.2 skrll { 1902 1.10.2.2 skrll struct sk_softc *sc = sc_if->sk_softc; 1903 1.10.2.10 christos struct sk_tx_desc *cur_tx; 1904 1.10.2.2 skrll struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1905 1.10.2.2 skrll u_int32_t idx; 1906 1.10.2.2 skrll struct sk_txmap_entry *entry; 1907 1.10.2.2 skrll 1908 1.10.2.2 skrll DPRINTFN(3, ("sk_txeof\n")); 1909 1.10.2.2 skrll 1910 1.10.2.2 skrll /* 1911 1.10.2.2 skrll * Go through our tx ring and free mbufs for those 1912 1.10.2.2 skrll * frames that have been sent. 1913 1.10.2.2 skrll */ 1914 1.10.2.2 skrll idx = sc_if->sk_cdata.sk_tx_cons; 1915 1.10.2.2 skrll while(idx != sc_if->sk_cdata.sk_tx_prod) { 1916 1.10.2.2 skrll SK_CDTXSYNC(sc_if, idx, 1, 1917 1.10.2.2 skrll BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1918 1.10.2.2 skrll 1919 1.10.2.2 skrll cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1920 1.10.2.2 skrll #ifdef SK_DEBUG 1921 1.10.2.2 skrll if (skdebug >= 3) 1922 1.10.2.2 skrll sk_dump_txdesc(cur_tx, idx); 1923 1.10.2.2 skrll #endif 1924 1.10.2.2 skrll if (cur_tx->sk_ctl & SK_TXCTL_OWN) { 1925 1.10.2.2 skrll SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 1926 1.10.2.2 skrll break; 1927 1.10.2.2 skrll } 1928 1.10.2.2 skrll if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1929 1.10.2.2 skrll ifp->if_opackets++; 1930 1.10.2.2 skrll if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1931 1.10.2.2 skrll entry = sc_if->sk_cdata.sk_tx_map[idx]; 1932 1.10.2.2 skrll 1933 1.10.2.2 skrll m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1934 1.10.2.2 skrll sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1935 1.10.2.2 skrll 1936 1.10.2.2 skrll bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1937 1.10.2.2 skrll entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1938 1.10.2.2 skrll 1939 1.10.2.2 skrll bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1940 1.10.2.5 skrll SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1941 1.10.2.2 skrll link); 1942 1.10.2.2 skrll sc_if->sk_cdata.sk_tx_map[idx] = NULL; 1943 1.10.2.2 skrll } 1944 1.10.2.2 skrll sc_if->sk_cdata.sk_tx_cnt--; 1945 1.10.2.2 skrll SK_INC(idx, SK_TX_RING_CNT); 1946 1.10.2.2 skrll } 1947 1.10.2.2 skrll if (sc_if->sk_cdata.sk_tx_cnt == 0) 1948 1.10.2.2 skrll ifp->if_timer = 0; 1949 1.10.2.5 skrll else /* nudge chip to keep tx ring moving */ 1950 1.10.2.5 skrll CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1951 1.10.2.2 skrll 1952 1.10.2.10 christos if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 1953 1.10.2.2 skrll ifp->if_flags &= ~IFF_OACTIVE; 1954 1.10.2.10 christos 1955 1.10.2.10 christos sc_if->sk_cdata.sk_tx_cons = idx; 1956 1.10.2.2 skrll } 1957 1.10.2.2 skrll 1958 1.10.2.2 skrll void 1959 1.10.2.2 skrll sk_tick(void *xsc_if) 1960 1.10.2.2 skrll { 1961 1.10.2.2 skrll struct sk_if_softc *sc_if = xsc_if; 1962 1.10.2.2 skrll struct mii_data *mii = &sc_if->sk_mii; 1963 1.10.2.2 skrll struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1964 1.10.2.2 skrll int i; 1965 1.10.2.2 skrll 1966 1.10.2.2 skrll DPRINTFN(3, ("sk_tick\n")); 1967 1.10.2.2 skrll 1968 1.10.2.2 skrll if (!(ifp->if_flags & IFF_UP)) 1969 1.10.2.2 skrll return; 1970 1.10.2.2 skrll 1971 1.10.2.2 skrll if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1972 1.10.2.2 skrll sk_intr_bcom(sc_if); 1973 1.10.2.2 skrll return; 1974 1.10.2.2 skrll } 1975 1.10.2.2 skrll 1976 1.10.2.2 skrll /* 1977 1.10.2.2 skrll * According to SysKonnect, the correct way to verify that 1978 1.10.2.2 skrll * the link has come back up is to poll bit 0 of the GPIO 1979 1.10.2.2 skrll * register three times. This pin has the signal from the 1980 1.10.2.2 skrll * link sync pin connected to it; if we read the same link 1981 1.10.2.2 skrll * state 3 times in a row, we know the link is up. 1982 1.10.2.2 skrll */ 1983 1.10.2.2 skrll for (i = 0; i < 3; i++) { 1984 1.10.2.2 skrll if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1985 1.10.2.2 skrll break; 1986 1.10.2.2 skrll } 1987 1.10.2.2 skrll 1988 1.10.2.2 skrll if (i != 3) { 1989 1.10.2.2 skrll callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 1990 1.10.2.2 skrll return; 1991 1.10.2.2 skrll } 1992 1.10.2.2 skrll 1993 1.10.2.2 skrll /* Turn the GP0 interrupt back on. */ 1994 1.10.2.2 skrll SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1995 1.10.2.2 skrll SK_XM_READ_2(sc_if, XM_ISR); 1996 1.10.2.2 skrll mii_tick(mii); 1997 1.10.2.2 skrll mii_pollstat(mii); 1998 1.10.2.2 skrll callout_stop(&sc_if->sk_tick_ch); 1999 1.10.2.2 skrll } 2000 1.10.2.2 skrll 2001 1.10.2.2 skrll void 2002 1.10.2.2 skrll sk_intr_bcom(struct sk_if_softc *sc_if) 2003 1.10.2.2 skrll { 2004 1.10.2.2 skrll struct mii_data *mii = &sc_if->sk_mii; 2005 1.10.2.2 skrll struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2006 1.10.2.2 skrll int status; 2007 1.10.2.2 skrll 2008 1.10.2.2 skrll 2009 1.10.2.2 skrll DPRINTFN(3, ("sk_intr_bcom\n")); 2010 1.10.2.2 skrll 2011 1.10.2.2 skrll SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2012 1.10.2.2 skrll 2013 1.10.2.2 skrll /* 2014 1.10.2.2 skrll * Read the PHY interrupt register to make sure 2015 1.10.2.2 skrll * we clear any pending interrupts. 2016 1.10.2.2 skrll */ 2017 1.10.2.2 skrll status = sk_xmac_miibus_readreg((struct device *)sc_if, 2018 1.10.2.2 skrll SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2019 1.10.2.2 skrll 2020 1.10.2.2 skrll if (!(ifp->if_flags & IFF_RUNNING)) { 2021 1.10.2.2 skrll sk_init_xmac(sc_if); 2022 1.10.2.2 skrll return; 2023 1.10.2.2 skrll } 2024 1.10.2.2 skrll 2025 1.10.2.2 skrll if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2026 1.10.2.2 skrll int lstat; 2027 1.10.2.2 skrll lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 2028 1.10.2.2 skrll SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2029 1.10.2.2 skrll 2030 1.10.2.2 skrll if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2031 1.10.2.2 skrll mii_mediachg(mii); 2032 1.10.2.2 skrll /* Turn off the link LED. */ 2033 1.10.2.2 skrll SK_IF_WRITE_1(sc_if, 0, 2034 1.10.2.2 skrll SK_LINKLED1_CTL, SK_LINKLED_OFF); 2035 1.10.2.2 skrll sc_if->sk_link = 0; 2036 1.10.2.2 skrll } else if (status & BRGPHY_ISR_LNK_CHG) { 2037 1.10.2.2 skrll sk_xmac_miibus_writereg((struct device *)sc_if, 2038 1.10.2.2 skrll SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2039 1.10.2.2 skrll mii_tick(mii); 2040 1.10.2.2 skrll sc_if->sk_link = 1; 2041 1.10.2.2 skrll /* Turn on the link LED. */ 2042 1.10.2.2 skrll SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2043 1.10.2.2 skrll SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2044 1.10.2.2 skrll SK_LINKLED_BLINK_OFF); 2045 1.10.2.2 skrll mii_pollstat(mii); 2046 1.10.2.2 skrll } else { 2047 1.10.2.2 skrll mii_tick(mii); 2048 1.10.2.2 skrll callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2049 1.10.2.2 skrll } 2050 1.10.2.2 skrll } 2051 1.10.2.2 skrll 2052 1.10.2.2 skrll SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2053 1.10.2.2 skrll } 2054 1.10.2.2 skrll 2055 1.10.2.2 skrll void 2056 1.10.2.2 skrll sk_intr_xmac(struct sk_if_softc *sc_if) 2057 1.10.2.2 skrll { 2058 1.10.2.2 skrll u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2059 1.10.2.2 skrll 2060 1.10.2.2 skrll DPRINTFN(3, ("sk_intr_xmac\n")); 2061 1.10.2.2 skrll 2062 1.10.2.2 skrll if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2063 1.10.2.2 skrll if (status & XM_ISR_GP0_SET) { 2064 1.10.2.2 skrll SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2065 1.10.2.2 skrll callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2066 1.10.2.2 skrll } 2067 1.10.2.2 skrll 2068 1.10.2.2 skrll if (status & XM_ISR_AUTONEG_DONE) { 2069 1.10.2.2 skrll callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2070 1.10.2.2 skrll } 2071 1.10.2.2 skrll } 2072 1.10.2.2 skrll 2073 1.10.2.2 skrll if (status & XM_IMR_TX_UNDERRUN) 2074 1.10.2.2 skrll SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2075 1.10.2.2 skrll 2076 1.10.2.2 skrll if (status & XM_IMR_RX_OVERRUN) 2077 1.10.2.2 skrll SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2078 1.10.2.2 skrll } 2079 1.10.2.2 skrll 2080 1.10.2.2 skrll void 2081 1.10.2.2 skrll sk_intr_yukon(sc_if) 2082 1.10.2.2 skrll struct sk_if_softc *sc_if; 2083 1.10.2.2 skrll { 2084 1.10.2.2 skrll int status; 2085 1.10.2.2 skrll 2086 1.10.2.2 skrll status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2087 1.10.2.2 skrll 2088 1.10.2.2 skrll DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2089 1.10.2.2 skrll } 2090 1.10.2.2 skrll 2091 1.10.2.2 skrll int 2092 1.10.2.2 skrll sk_intr(void *xsc) 2093 1.10.2.2 skrll { 2094 1.10.2.2 skrll struct sk_softc *sc = xsc; 2095 1.10.2.2 skrll struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2096 1.10.2.2 skrll struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2097 1.10.2.2 skrll struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2098 1.10.2.2 skrll u_int32_t status; 2099 1.10.2.2 skrll int claimed = 0; 2100 1.10.2.2 skrll 2101 1.10.2.2 skrll if (sc_if0 != NULL) 2102 1.10.2.2 skrll ifp0 = &sc_if0->sk_ethercom.ec_if; 2103 1.10.2.2 skrll if (sc_if1 != NULL) 2104 1.10.2.2 skrll ifp1 = &sc_if1->sk_ethercom.ec_if; 2105 1.10.2.2 skrll 2106 1.10.2.2 skrll for (;;) { 2107 1.10.2.2 skrll status = CSR_READ_4(sc, SK_ISSR); 2108 1.10.2.2 skrll DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2109 1.10.2.2 skrll 2110 1.10.2.2 skrll if (!(status & sc->sk_intrmask)) 2111 1.10.2.2 skrll break; 2112 1.10.2.2 skrll 2113 1.10.2.2 skrll claimed = 1; 2114 1.10.2.2 skrll 2115 1.10.2.2 skrll /* Handle receive interrupts first. */ 2116 1.10.2.2 skrll if (status & SK_ISR_RX1_EOF) { 2117 1.10.2.2 skrll sk_rxeof(sc_if0); 2118 1.10.2.2 skrll CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2119 1.10.2.2 skrll SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2120 1.10.2.2 skrll } 2121 1.10.2.2 skrll if (status & SK_ISR_RX2_EOF) { 2122 1.10.2.2 skrll sk_rxeof(sc_if1); 2123 1.10.2.2 skrll CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2124 1.10.2.2 skrll SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2125 1.10.2.2 skrll } 2126 1.10.2.2 skrll 2127 1.10.2.2 skrll /* Then transmit interrupts. */ 2128 1.10.2.2 skrll if (status & SK_ISR_TX1_S_EOF) { 2129 1.10.2.2 skrll sk_txeof(sc_if0); 2130 1.10.2.2 skrll CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2131 1.10.2.2 skrll SK_TXBMU_CLR_IRQ_EOF); 2132 1.10.2.2 skrll } 2133 1.10.2.2 skrll if (status & SK_ISR_TX2_S_EOF) { 2134 1.10.2.2 skrll sk_txeof(sc_if1); 2135 1.10.2.2 skrll CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2136 1.10.2.2 skrll SK_TXBMU_CLR_IRQ_EOF); 2137 1.10.2.2 skrll } 2138 1.10.2.2 skrll 2139 1.10.2.2 skrll /* Then MAC interrupts. */ 2140 1.10.2.2 skrll if (status & SK_ISR_MAC1 && (ifp0->if_flags & IFF_RUNNING)) { 2141 1.10.2.2 skrll if (sc->sk_type == SK_GENESIS) 2142 1.10.2.2 skrll sk_intr_xmac(sc_if0); 2143 1.10.2.2 skrll else 2144 1.10.2.2 skrll sk_intr_yukon(sc_if0); 2145 1.10.2.2 skrll } 2146 1.10.2.2 skrll 2147 1.10.2.2 skrll if (status & SK_ISR_MAC2 && (ifp1->if_flags & IFF_RUNNING)) { 2148 1.10.2.2 skrll if (sc->sk_type == SK_GENESIS) 2149 1.10.2.2 skrll sk_intr_xmac(sc_if1); 2150 1.10.2.2 skrll else 2151 1.10.2.2 skrll sk_intr_yukon(sc_if1); 2152 1.10.2.2 skrll 2153 1.10.2.2 skrll } 2154 1.10.2.2 skrll 2155 1.10.2.2 skrll if (status & SK_ISR_EXTERNAL_REG) { 2156 1.10.2.2 skrll if (ifp0 != NULL && 2157 1.10.2.2 skrll sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2158 1.10.2.2 skrll sk_intr_bcom(sc_if0); 2159 1.10.2.2 skrll 2160 1.10.2.2 skrll if (ifp1 != NULL && 2161 1.10.2.2 skrll sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2162 1.10.2.2 skrll sk_intr_bcom(sc_if1); 2163 1.10.2.2 skrll } 2164 1.10.2.2 skrll } 2165 1.10.2.2 skrll 2166 1.10.2.2 skrll CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2167 1.10.2.2 skrll 2168 1.10.2.2 skrll if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2169 1.10.2.2 skrll sk_start(ifp0); 2170 1.10.2.2 skrll if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2171 1.10.2.2 skrll sk_start(ifp1); 2172 1.10.2.2 skrll 2173 1.10.2.2 skrll return (claimed); 2174 1.10.2.2 skrll } 2175 1.10.2.2 skrll 2176 1.10.2.2 skrll void 2177 1.10.2.2 skrll sk_init_xmac(struct sk_if_softc *sc_if) 2178 1.10.2.2 skrll { 2179 1.10.2.2 skrll struct sk_softc *sc = sc_if->sk_softc; 2180 1.10.2.2 skrll struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2181 1.10.2.2 skrll static const struct sk_bcom_hack bhack[] = { 2182 1.10.2.2 skrll { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2183 1.10.2.2 skrll { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2184 1.10.2.2 skrll { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2185 1.10.2.2 skrll { 0, 0 } }; 2186 1.10.2.2 skrll 2187 1.10.2.2 skrll DPRINTFN(1, ("sk_init_xmac\n")); 2188 1.10.2.2 skrll 2189 1.10.2.2 skrll /* Unreset the XMAC. */ 2190 1.10.2.2 skrll SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2191 1.10.2.2 skrll DELAY(1000); 2192 1.10.2.2 skrll 2193 1.10.2.2 skrll /* Reset the XMAC's internal state. */ 2194 1.10.2.2 skrll SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2195 1.10.2.2 skrll 2196 1.10.2.2 skrll /* Save the XMAC II revision */ 2197 1.10.2.2 skrll sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2198 1.10.2.2 skrll 2199 1.10.2.2 skrll /* 2200 1.10.2.2 skrll * Perform additional initialization for external PHYs, 2201 1.10.2.2 skrll * namely for the 1000baseTX cards that use the XMAC's 2202 1.10.2.2 skrll * GMII mode. 2203 1.10.2.2 skrll */ 2204 1.10.2.2 skrll if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2205 1.10.2.2 skrll int i = 0; 2206 1.10.2.2 skrll u_int32_t val; 2207 1.10.2.2 skrll 2208 1.10.2.2 skrll /* Take PHY out of reset. */ 2209 1.10.2.2 skrll val = sk_win_read_4(sc, SK_GPIO); 2210 1.10.2.2 skrll if (sc_if->sk_port == SK_PORT_A) 2211 1.10.2.2 skrll val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2212 1.10.2.2 skrll else 2213 1.10.2.2 skrll val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2214 1.10.2.2 skrll sk_win_write_4(sc, SK_GPIO, val); 2215 1.10.2.2 skrll 2216 1.10.2.2 skrll /* Enable GMII mode on the XMAC. */ 2217 1.10.2.2 skrll SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2218 1.10.2.2 skrll 2219 1.10.2.2 skrll sk_xmac_miibus_writereg((struct device *)sc_if, 2220 1.10.2.2 skrll SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2221 1.10.2.2 skrll DELAY(10000); 2222 1.10.2.2 skrll sk_xmac_miibus_writereg((struct device *)sc_if, 2223 1.10.2.2 skrll SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2224 1.10.2.2 skrll 2225 1.10.2.2 skrll /* 2226 1.10.2.2 skrll * Early versions of the BCM5400 apparently have 2227 1.10.2.2 skrll * a bug that requires them to have their reserved 2228 1.10.2.2 skrll * registers initialized to some magic values. I don't 2229 1.10.2.2 skrll * know what the numbers do, I'm just the messenger. 2230 1.10.2.2 skrll */ 2231 1.10.2.2 skrll if (sk_xmac_miibus_readreg((struct device *)sc_if, 2232 1.10.2.2 skrll SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2233 1.10.2.2 skrll while(bhack[i].reg) { 2234 1.10.2.2 skrll sk_xmac_miibus_writereg((struct device *)sc_if, 2235 1.10.2.2 skrll SK_PHYADDR_BCOM, bhack[i].reg, 2236 1.10.2.2 skrll bhack[i].val); 2237 1.10.2.2 skrll i++; 2238 1.10.2.2 skrll } 2239 1.10.2.2 skrll } 2240 1.10.2.2 skrll } 2241 1.10.2.2 skrll 2242 1.10.2.2 skrll /* Set station address */ 2243 1.10.2.2 skrll SK_XM_WRITE_2(sc_if, XM_PAR0, 2244 1.10.2.2 skrll *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2245 1.10.2.2 skrll SK_XM_WRITE_2(sc_if, XM_PAR1, 2246 1.10.2.2 skrll *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2247 1.10.2.2 skrll SK_XM_WRITE_2(sc_if, XM_PAR2, 2248 1.10.2.2 skrll *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2249 1.10.2.2 skrll SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2250 1.10.2.2 skrll 2251 1.10.2.2 skrll if (ifp->if_flags & IFF_PROMISC) { 2252 1.10.2.2 skrll SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2253 1.10.2.2 skrll } else { 2254 1.10.2.2 skrll SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2255 1.10.2.2 skrll } 2256 1.10.2.2 skrll 2257 1.10.2.2 skrll if (ifp->if_flags & IFF_BROADCAST) { 2258 1.10.2.2 skrll SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2259 1.10.2.2 skrll } else { 2260 1.10.2.2 skrll SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2261 1.10.2.2 skrll } 2262 1.10.2.2 skrll 2263 1.10.2.2 skrll /* We don't need the FCS appended to the packet. */ 2264 1.10.2.2 skrll SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2265 1.10.2.2 skrll 2266 1.10.2.2 skrll /* We want short frames padded to 60 bytes. */ 2267 1.10.2.2 skrll SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2268 1.10.2.2 skrll 2269 1.10.2.2 skrll /* 2270 1.10.2.2 skrll * Enable the reception of all error frames. This is is 2271 1.10.2.2 skrll * a necessary evil due to the design of the XMAC. The 2272 1.10.2.2 skrll * XMAC's receive FIFO is only 8K in size, however jumbo 2273 1.10.2.2 skrll * frames can be up to 9000 bytes in length. When bad 2274 1.10.2.2 skrll * frame filtering is enabled, the XMAC's RX FIFO operates 2275 1.10.2.2 skrll * in 'store and forward' mode. For this to work, the 2276 1.10.2.2 skrll * entire frame has to fit into the FIFO, but that means 2277 1.10.2.2 skrll * that jumbo frames larger than 8192 bytes will be 2278 1.10.2.2 skrll * truncated. Disabling all bad frame filtering causes 2279 1.10.2.2 skrll * the RX FIFO to operate in streaming mode, in which 2280 1.10.2.2 skrll * case the XMAC will start transfering frames out of the 2281 1.10.2.2 skrll * RX FIFO as soon as the FIFO threshold is reached. 2282 1.10.2.2 skrll */ 2283 1.10.2.2 skrll SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2284 1.10.2.2 skrll XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2285 1.10.2.2 skrll XM_MODE_RX_INRANGELEN); 2286 1.10.2.2 skrll 2287 1.10.2.2 skrll if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2288 1.10.2.2 skrll SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2289 1.10.2.2 skrll else 2290 1.10.2.2 skrll SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2291 1.10.2.2 skrll 2292 1.10.2.2 skrll /* 2293 1.10.2.2 skrll * Bump up the transmit threshold. This helps hold off transmit 2294 1.10.2.2 skrll * underruns when we're blasting traffic from both ports at once. 2295 1.10.2.2 skrll */ 2296 1.10.2.2 skrll SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2297 1.10.2.2 skrll 2298 1.10.2.2 skrll /* Set multicast filter */ 2299 1.10.2.2 skrll sk_setmulti(sc_if); 2300 1.10.2.2 skrll 2301 1.10.2.2 skrll /* Clear and enable interrupts */ 2302 1.10.2.2 skrll SK_XM_READ_2(sc_if, XM_ISR); 2303 1.10.2.2 skrll if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2304 1.10.2.2 skrll SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2305 1.10.2.2 skrll else 2306 1.10.2.2 skrll SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2307 1.10.2.2 skrll 2308 1.10.2.2 skrll /* Configure MAC arbiter */ 2309 1.10.2.2 skrll switch(sc_if->sk_xmac_rev) { 2310 1.10.2.2 skrll case XM_XMAC_REV_B2: 2311 1.10.2.2 skrll sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2312 1.10.2.2 skrll sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2313 1.10.2.2 skrll sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2314 1.10.2.2 skrll sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2315 1.10.2.2 skrll sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2316 1.10.2.2 skrll sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2317 1.10.2.2 skrll sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2318 1.10.2.2 skrll sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2319 1.10.2.2 skrll sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2320 1.10.2.2 skrll break; 2321 1.10.2.2 skrll case XM_XMAC_REV_C1: 2322 1.10.2.2 skrll sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2323 1.10.2.2 skrll sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2324 1.10.2.2 skrll sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2325 1.10.2.2 skrll sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2326 1.10.2.2 skrll sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2327 1.10.2.2 skrll sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2328 1.10.2.2 skrll sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2329 1.10.2.2 skrll sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2330 1.10.2.2 skrll sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2331 1.10.2.2 skrll break; 2332 1.10.2.2 skrll default: 2333 1.10.2.2 skrll break; 2334 1.10.2.2 skrll } 2335 1.10.2.2 skrll sk_win_write_2(sc, SK_MACARB_CTL, 2336 1.10.2.2 skrll SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2337 1.10.2.2 skrll 2338 1.10.2.2 skrll sc_if->sk_link = 1; 2339 1.10.2.2 skrll } 2340 1.10.2.2 skrll 2341 1.10.2.2 skrll void sk_init_yukon(sc_if) 2342 1.10.2.2 skrll struct sk_if_softc *sc_if; 2343 1.10.2.2 skrll { 2344 1.10.2.2 skrll u_int32_t /*mac, */phy; 2345 1.10.2.2 skrll u_int16_t reg; 2346 1.10.2.9 skrll struct sk_softc *sc; 2347 1.10.2.2 skrll int i; 2348 1.10.2.2 skrll 2349 1.10.2.2 skrll DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2350 1.10.2.2 skrll CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2351 1.10.2.2 skrll 2352 1.10.2.9 skrll sc = sc_if->sk_softc; 2353 1.10.2.9 skrll if (sc->sk_type == SK_YUKON_LITE && 2354 1.10.2.9 skrll sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2355 1.10.2.9 skrll /* Take PHY out of reset. */ 2356 1.10.2.9 skrll sk_win_write_4(sc, SK_GPIO, 2357 1.10.2.9 skrll (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2358 1.10.2.9 skrll } 2359 1.10.2.9 skrll 2360 1.10.2.9 skrll 2361 1.10.2.2 skrll /* GMAC and GPHY Reset */ 2362 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2363 1.10.2.2 skrll 2364 1.10.2.2 skrll DPRINTFN(6, ("sk_init_yukon: 1\n")); 2365 1.10.2.2 skrll 2366 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2367 1.10.2.2 skrll DELAY(1000); 2368 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2369 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2370 1.10.2.2 skrll DELAY(1000); 2371 1.10.2.2 skrll 2372 1.10.2.2 skrll 2373 1.10.2.2 skrll DPRINTFN(6, ("sk_init_yukon: 2\n")); 2374 1.10.2.2 skrll 2375 1.10.2.2 skrll phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2376 1.10.2.2 skrll SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2377 1.10.2.2 skrll 2378 1.10.2.2 skrll switch(sc_if->sk_softc->sk_pmd) { 2379 1.10.2.2 skrll case IFM_1000_SX: 2380 1.10.2.2 skrll case IFM_1000_LX: 2381 1.10.2.2 skrll phy |= SK_GPHY_FIBER; 2382 1.10.2.2 skrll break; 2383 1.10.2.2 skrll 2384 1.10.2.2 skrll case IFM_1000_CX: 2385 1.10.2.2 skrll case IFM_1000_T: 2386 1.10.2.2 skrll phy |= SK_GPHY_COPPER; 2387 1.10.2.2 skrll break; 2388 1.10.2.2 skrll } 2389 1.10.2.2 skrll 2390 1.10.2.2 skrll DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2391 1.10.2.2 skrll 2392 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2393 1.10.2.2 skrll DELAY(1000); 2394 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2395 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2396 1.10.2.2 skrll SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2397 1.10.2.2 skrll 2398 1.10.2.2 skrll DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2399 1.10.2.2 skrll SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2400 1.10.2.2 skrll 2401 1.10.2.2 skrll DPRINTFN(6, ("sk_init_yukon: 3\n")); 2402 1.10.2.2 skrll 2403 1.10.2.2 skrll /* unused read of the interrupt source register */ 2404 1.10.2.2 skrll DPRINTFN(6, ("sk_init_yukon: 4\n")); 2405 1.10.2.2 skrll SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2406 1.10.2.2 skrll 2407 1.10.2.2 skrll DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2408 1.10.2.2 skrll reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2409 1.10.2.2 skrll DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2410 1.10.2.2 skrll 2411 1.10.2.2 skrll /* MIB Counter Clear Mode set */ 2412 1.10.2.2 skrll reg |= YU_PAR_MIB_CLR; 2413 1.10.2.2 skrll DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2414 1.10.2.2 skrll DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2415 1.10.2.2 skrll SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2416 1.10.2.8 skrll 2417 1.10.2.2 skrll /* MIB Counter Clear Mode clear */ 2418 1.10.2.2 skrll DPRINTFN(6, ("sk_init_yukon: 5\n")); 2419 1.10.2.2 skrll reg &= ~YU_PAR_MIB_CLR; 2420 1.10.2.2 skrll SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2421 1.10.2.2 skrll 2422 1.10.2.2 skrll /* receive control reg */ 2423 1.10.2.2 skrll DPRINTFN(6, ("sk_init_yukon: 7\n")); 2424 1.10.2.2 skrll SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2425 1.10.2.2 skrll YU_RCR_CRCR); 2426 1.10.2.2 skrll 2427 1.10.2.2 skrll /* transmit parameter register */ 2428 1.10.2.2 skrll DPRINTFN(6, ("sk_init_yukon: 8\n")); 2429 1.10.2.2 skrll SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2430 1.10.2.2 skrll YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2431 1.10.2.2 skrll 2432 1.10.2.2 skrll /* serial mode register */ 2433 1.10.2.2 skrll DPRINTFN(6, ("sk_init_yukon: 9\n")); 2434 1.10.2.2 skrll SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2435 1.10.2.2 skrll YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e)); 2436 1.10.2.2 skrll 2437 1.10.2.2 skrll DPRINTFN(6, ("sk_init_yukon: 10\n")); 2438 1.10.2.2 skrll /* Setup Yukon's address */ 2439 1.10.2.2 skrll for (i = 0; i < 3; i++) { 2440 1.10.2.2 skrll /* Write Source Address 1 (unicast filter) */ 2441 1.10.2.8 skrll SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2442 1.10.2.2 skrll sc_if->sk_enaddr[i * 2] | 2443 1.10.2.2 skrll sc_if->sk_enaddr[i * 2 + 1] << 8); 2444 1.10.2.2 skrll } 2445 1.10.2.2 skrll 2446 1.10.2.2 skrll for (i = 0; i < 3; i++) { 2447 1.10.2.2 skrll reg = sk_win_read_2(sc_if->sk_softc, 2448 1.10.2.2 skrll SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2449 1.10.2.2 skrll SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2450 1.10.2.2 skrll } 2451 1.10.2.2 skrll 2452 1.10.2.2 skrll /* Set multicast filter */ 2453 1.10.2.2 skrll DPRINTFN(6, ("sk_init_yukon: 11\n")); 2454 1.10.2.2 skrll sk_setmulti(sc_if); 2455 1.10.2.2 skrll 2456 1.10.2.2 skrll /* enable interrupt mask for counter overflows */ 2457 1.10.2.2 skrll DPRINTFN(6, ("sk_init_yukon: 12\n")); 2458 1.10.2.2 skrll SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2459 1.10.2.2 skrll SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2460 1.10.2.2 skrll SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2461 1.10.2.2 skrll 2462 1.10.2.2 skrll /* Configure RX MAC FIFO */ 2463 1.10.2.2 skrll SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2464 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2465 1.10.2.8 skrll 2466 1.10.2.2 skrll /* Configure TX MAC FIFO */ 2467 1.10.2.2 skrll SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2468 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2469 1.10.2.8 skrll 2470 1.10.2.2 skrll DPRINTFN(6, ("sk_init_yukon: end\n")); 2471 1.10.2.2 skrll } 2472 1.10.2.2 skrll 2473 1.10.2.2 skrll /* 2474 1.10.2.2 skrll * Note that to properly initialize any part of the GEnesis chip, 2475 1.10.2.2 skrll * you first have to take it out of reset mode. 2476 1.10.2.2 skrll */ 2477 1.10.2.2 skrll int 2478 1.10.2.2 skrll sk_init(struct ifnet *ifp) 2479 1.10.2.2 skrll { 2480 1.10.2.2 skrll struct sk_if_softc *sc_if = ifp->if_softc; 2481 1.10.2.2 skrll struct sk_softc *sc = sc_if->sk_softc; 2482 1.10.2.2 skrll struct mii_data *mii = &sc_if->sk_mii; 2483 1.10.2.2 skrll int s; 2484 1.10.2.2 skrll 2485 1.10.2.2 skrll DPRINTFN(1, ("sk_init\n")); 2486 1.10.2.2 skrll 2487 1.10.2.2 skrll s = splnet(); 2488 1.10.2.2 skrll 2489 1.10.2.9 skrll if (ifp->if_flags & IFF_RUNNING) { 2490 1.10.2.9 skrll splx(s); 2491 1.10.2.9 skrll return 0; 2492 1.10.2.9 skrll } 2493 1.10.2.9 skrll 2494 1.10.2.2 skrll /* Cancel pending I/O and free all RX/TX buffers. */ 2495 1.10.2.2 skrll sk_stop(ifp,0); 2496 1.10.2.2 skrll 2497 1.10.2.2 skrll if (sc->sk_type == SK_GENESIS) { 2498 1.10.2.2 skrll /* Configure LINK_SYNC LED */ 2499 1.10.2.2 skrll SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2500 1.10.2.2 skrll SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2501 1.10.2.2 skrll SK_LINKLED_LINKSYNC_ON); 2502 1.10.2.2 skrll 2503 1.10.2.2 skrll /* Configure RX LED */ 2504 1.10.2.2 skrll SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2505 1.10.2.2 skrll SK_RXLEDCTL_COUNTER_START); 2506 1.10.2.8 skrll 2507 1.10.2.2 skrll /* Configure TX LED */ 2508 1.10.2.2 skrll SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2509 1.10.2.2 skrll SK_TXLEDCTL_COUNTER_START); 2510 1.10.2.2 skrll } 2511 1.10.2.2 skrll 2512 1.10.2.2 skrll /* Configure I2C registers */ 2513 1.10.2.2 skrll 2514 1.10.2.2 skrll /* Configure XMAC(s) */ 2515 1.10.2.2 skrll switch (sc->sk_type) { 2516 1.10.2.2 skrll case SK_GENESIS: 2517 1.10.2.2 skrll sk_init_xmac(sc_if); 2518 1.10.2.2 skrll break; 2519 1.10.2.2 skrll case SK_YUKON: 2520 1.10.2.5 skrll case SK_YUKON_LITE: 2521 1.10.2.5 skrll case SK_YUKON_LP: 2522 1.10.2.2 skrll sk_init_yukon(sc_if); 2523 1.10.2.2 skrll break; 2524 1.10.2.2 skrll } 2525 1.10.2.2 skrll mii_mediachg(mii); 2526 1.10.2.2 skrll 2527 1.10.2.2 skrll if (sc->sk_type == SK_GENESIS) { 2528 1.10.2.2 skrll /* Configure MAC FIFOs */ 2529 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2530 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2531 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2532 1.10.2.8 skrll 2533 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2534 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2535 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2536 1.10.2.2 skrll } 2537 1.10.2.2 skrll 2538 1.10.2.2 skrll /* Configure transmit arbiter(s) */ 2539 1.10.2.2 skrll SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2540 1.10.2.2 skrll SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2541 1.10.2.2 skrll 2542 1.10.2.2 skrll /* Configure RAMbuffers */ 2543 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2544 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2545 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2546 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2547 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2548 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2549 1.10.2.2 skrll 2550 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2551 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2552 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2553 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2554 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2555 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2556 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2557 1.10.2.2 skrll 2558 1.10.2.2 skrll /* Configure BMUs */ 2559 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2560 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2561 1.10.2.2 skrll SK_RX_RING_ADDR(sc_if, 0)); 2562 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2563 1.10.2.2 skrll 2564 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2565 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2566 1.10.2.2 skrll SK_TX_RING_ADDR(sc_if, 0)); 2567 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2568 1.10.2.2 skrll 2569 1.10.2.2 skrll /* Init descriptors */ 2570 1.10.2.2 skrll if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2571 1.10.2.2 skrll printf("%s: initialization failed: no " 2572 1.10.2.2 skrll "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2573 1.10.2.2 skrll sk_stop(ifp,0); 2574 1.10.2.2 skrll splx(s); 2575 1.10.2.2 skrll return(ENOBUFS); 2576 1.10.2.2 skrll } 2577 1.10.2.2 skrll 2578 1.10.2.2 skrll if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2579 1.10.2.2 skrll printf("%s: initialization failed: no " 2580 1.10.2.2 skrll "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2581 1.10.2.2 skrll sk_stop(ifp,0); 2582 1.10.2.2 skrll splx(s); 2583 1.10.2.2 skrll return(ENOBUFS); 2584 1.10.2.2 skrll } 2585 1.10.2.2 skrll 2586 1.10.2.2 skrll /* Configure interrupt handling */ 2587 1.10.2.2 skrll CSR_READ_4(sc, SK_ISSR); 2588 1.10.2.2 skrll if (sc_if->sk_port == SK_PORT_A) 2589 1.10.2.2 skrll sc->sk_intrmask |= SK_INTRS1; 2590 1.10.2.2 skrll else 2591 1.10.2.2 skrll sc->sk_intrmask |= SK_INTRS2; 2592 1.10.2.2 skrll 2593 1.10.2.2 skrll sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2594 1.10.2.2 skrll 2595 1.10.2.2 skrll CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2596 1.10.2.2 skrll 2597 1.10.2.2 skrll /* Start BMUs. */ 2598 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2599 1.10.2.2 skrll 2600 1.10.2.2 skrll if (sc->sk_type == SK_GENESIS) { 2601 1.10.2.2 skrll /* Enable XMACs TX and RX state machines */ 2602 1.10.2.2 skrll SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2603 1.10.2.2 skrll SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2604 1.10.2.2 skrll XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2605 1.10.2.2 skrll } 2606 1.10.2.2 skrll 2607 1.10.2.5 skrll if (SK_YUKON_FAMILY(sc->sk_type)) { 2608 1.10.2.2 skrll u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2609 1.10.2.2 skrll reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2610 1.10.2.2 skrll reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2611 1.10.2.2 skrll SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2612 1.10.2.2 skrll } 2613 1.10.2.2 skrll 2614 1.10.2.2 skrll 2615 1.10.2.2 skrll ifp->if_flags |= IFF_RUNNING; 2616 1.10.2.2 skrll ifp->if_flags &= ~IFF_OACTIVE; 2617 1.10.2.2 skrll 2618 1.10.2.2 skrll splx(s); 2619 1.10.2.2 skrll return(0); 2620 1.10.2.2 skrll } 2621 1.10.2.2 skrll 2622 1.10.2.2 skrll void 2623 1.10.2.2 skrll sk_stop(struct ifnet *ifp, int disable) 2624 1.10.2.2 skrll { 2625 1.10.2.2 skrll struct sk_if_softc *sc_if = ifp->if_softc; 2626 1.10.2.2 skrll struct sk_softc *sc = sc_if->sk_softc; 2627 1.10.2.2 skrll int i; 2628 1.10.2.2 skrll 2629 1.10.2.2 skrll DPRINTFN(1, ("sk_stop\n")); 2630 1.10.2.2 skrll 2631 1.10.2.2 skrll callout_stop(&sc_if->sk_tick_ch); 2632 1.10.2.2 skrll 2633 1.10.2.2 skrll if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2634 1.10.2.2 skrll u_int32_t val; 2635 1.10.2.2 skrll 2636 1.10.2.2 skrll /* Put PHY back into reset. */ 2637 1.10.2.2 skrll val = sk_win_read_4(sc, SK_GPIO); 2638 1.10.2.2 skrll if (sc_if->sk_port == SK_PORT_A) { 2639 1.10.2.2 skrll val |= SK_GPIO_DIR0; 2640 1.10.2.2 skrll val &= ~SK_GPIO_DAT0; 2641 1.10.2.2 skrll } else { 2642 1.10.2.2 skrll val |= SK_GPIO_DIR2; 2643 1.10.2.2 skrll val &= ~SK_GPIO_DAT2; 2644 1.10.2.2 skrll } 2645 1.10.2.2 skrll sk_win_write_4(sc, SK_GPIO, val); 2646 1.10.2.2 skrll } 2647 1.10.2.2 skrll 2648 1.10.2.2 skrll /* Turn off various components of this interface. */ 2649 1.10.2.2 skrll SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2650 1.10.2.2 skrll switch (sc->sk_type) { 2651 1.10.2.2 skrll case SK_GENESIS: 2652 1.10.2.2 skrll SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2653 1.10.2.2 skrll SK_TXMACCTL_XMAC_RESET); 2654 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2655 1.10.2.2 skrll break; 2656 1.10.2.2 skrll case SK_YUKON: 2657 1.10.2.5 skrll case SK_YUKON_LITE: 2658 1.10.2.5 skrll case SK_YUKON_LP: 2659 1.10.2.2 skrll SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2660 1.10.2.2 skrll SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2661 1.10.2.2 skrll break; 2662 1.10.2.2 skrll } 2663 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2664 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2665 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2666 1.10.2.2 skrll SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2667 1.10.2.2 skrll SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2668 1.10.2.2 skrll SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2669 1.10.2.2 skrll SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2670 1.10.2.2 skrll SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2671 1.10.2.2 skrll SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2672 1.10.2.2 skrll 2673 1.10.2.2 skrll /* Disable interrupts */ 2674 1.10.2.2 skrll if (sc_if->sk_port == SK_PORT_A) 2675 1.10.2.2 skrll sc->sk_intrmask &= ~SK_INTRS1; 2676 1.10.2.2 skrll else 2677 1.10.2.2 skrll sc->sk_intrmask &= ~SK_INTRS2; 2678 1.10.2.2 skrll CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2679 1.10.2.2 skrll 2680 1.10.2.2 skrll SK_XM_READ_2(sc_if, XM_ISR); 2681 1.10.2.2 skrll SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2682 1.10.2.2 skrll 2683 1.10.2.2 skrll /* Free RX and TX mbufs still in the queues. */ 2684 1.10.2.2 skrll for (i = 0; i < SK_RX_RING_CNT; i++) { 2685 1.10.2.2 skrll if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2686 1.10.2.2 skrll m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2687 1.10.2.2 skrll sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2688 1.10.2.2 skrll } 2689 1.10.2.2 skrll } 2690 1.10.2.2 skrll 2691 1.10.2.2 skrll for (i = 0; i < SK_TX_RING_CNT; i++) { 2692 1.10.2.2 skrll if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2693 1.10.2.2 skrll m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2694 1.10.2.2 skrll sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2695 1.10.2.2 skrll } 2696 1.10.2.2 skrll } 2697 1.10.2.2 skrll 2698 1.10.2.2 skrll ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2699 1.10.2.2 skrll } 2700 1.10.2.2 skrll 2701 1.10.2.2 skrll CFATTACH_DECL(skc,sizeof(struct sk_softc), skc_probe, skc_attach, NULL, NULL); 2702 1.10.2.2 skrll 2703 1.10.2.2 skrll /* 2704 1.10.2.2 skrll struct cfdriver skc_cd = { 2705 1.10.2.2 skrll 0, "skc", DV_DULL 2706 1.10.2.2 skrll }; 2707 1.10.2.2 skrll */ 2708 1.10.2.2 skrll 2709 1.10.2.2 skrll CFATTACH_DECL(sk,sizeof(struct sk_if_softc), sk_probe, sk_attach, NULL, NULL); 2710 1.10.2.2 skrll 2711 1.10.2.2 skrll /* 2712 1.10.2.2 skrll struct cfdriver sk_cd = { 2713 1.10.2.2 skrll 0, "sk", DV_IFNET 2714 1.10.2.2 skrll }; 2715 1.10.2.2 skrll */ 2716 1.10.2.2 skrll 2717 1.10.2.2 skrll #ifdef SK_DEBUG 2718 1.10.2.2 skrll void 2719 1.10.2.2 skrll sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2720 1.10.2.2 skrll { 2721 1.10.2.2 skrll #define DESC_PRINT(X) \ 2722 1.10.2.2 skrll if (desc->X) \ 2723 1.10.2.2 skrll printf("txdesc[%d]." #X "=%#x\n", \ 2724 1.10.2.2 skrll idx, desc->X); 2725 1.10.2.2 skrll 2726 1.10.2.2 skrll DESC_PRINT(sk_ctl); 2727 1.10.2.2 skrll DESC_PRINT(sk_next); 2728 1.10.2.2 skrll DESC_PRINT(sk_data_lo); 2729 1.10.2.2 skrll DESC_PRINT(sk_data_hi); 2730 1.10.2.2 skrll DESC_PRINT(sk_xmac_txstat); 2731 1.10.2.2 skrll DESC_PRINT(sk_rsvd0); 2732 1.10.2.2 skrll DESC_PRINT(sk_csum_startval); 2733 1.10.2.2 skrll DESC_PRINT(sk_csum_startpos); 2734 1.10.2.2 skrll DESC_PRINT(sk_csum_writepos); 2735 1.10.2.2 skrll DESC_PRINT(sk_rsvd1); 2736 1.10.2.2 skrll #undef PRINT 2737 1.10.2.2 skrll } 2738 1.10.2.2 skrll 2739 1.10.2.2 skrll void 2740 1.10.2.2 skrll sk_dump_bytes(const char *data, int len) 2741 1.10.2.2 skrll { 2742 1.10.2.2 skrll int c, i, j; 2743 1.10.2.2 skrll 2744 1.10.2.2 skrll for (i = 0; i < len; i += 16) { 2745 1.10.2.2 skrll printf("%08x ", i); 2746 1.10.2.2 skrll c = len - i; 2747 1.10.2.2 skrll if (c > 16) c = 16; 2748 1.10.2.2 skrll 2749 1.10.2.2 skrll for (j = 0; j < c; j++) { 2750 1.10.2.2 skrll printf("%02x ", data[i + j] & 0xff); 2751 1.10.2.2 skrll if ((j & 0xf) == 7 && j > 0) 2752 1.10.2.2 skrll printf(" "); 2753 1.10.2.2 skrll } 2754 1.10.2.8 skrll 2755 1.10.2.2 skrll for (; j < 16; j++) 2756 1.10.2.2 skrll printf(" "); 2757 1.10.2.2 skrll printf(" "); 2758 1.10.2.2 skrll 2759 1.10.2.2 skrll for (j = 0; j < c; j++) { 2760 1.10.2.2 skrll int ch = data[i + j] & 0xff; 2761 1.10.2.2 skrll printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2762 1.10.2.2 skrll } 2763 1.10.2.8 skrll 2764 1.10.2.2 skrll printf("\n"); 2765 1.10.2.8 skrll 2766 1.10.2.2 skrll if (c < 16) 2767 1.10.2.2 skrll break; 2768 1.10.2.2 skrll } 2769 1.10.2.2 skrll } 2770 1.10.2.2 skrll 2771 1.10.2.2 skrll void 2772 1.10.2.2 skrll sk_dump_mbuf(struct mbuf *m) 2773 1.10.2.2 skrll { 2774 1.10.2.2 skrll int count = m->m_pkthdr.len; 2775 1.10.2.2 skrll 2776 1.10.2.2 skrll printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2777 1.10.2.2 skrll 2778 1.10.2.2 skrll while (count > 0 && m) { 2779 1.10.2.2 skrll printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2780 1.10.2.2 skrll m, m->m_data, m->m_len); 2781 1.10.2.2 skrll sk_dump_bytes(mtod(m, char *), m->m_len); 2782 1.10.2.2 skrll 2783 1.10.2.2 skrll count -= m->m_len; 2784 1.10.2.2 skrll m = m->m_next; 2785 1.10.2.2 skrll } 2786 1.10.2.2 skrll } 2787 1.10.2.2 skrll #endif 2788
Indexes created Wed Oct 15 16:09:53 GMT 2025