if_sk.c revision 1.100
1 /* $NetBSD: if_sk.c,v 1.100 2019/06/03 15:49:04 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 30 31 /* 32 * Copyright (c) 1997, 1998, 1999, 2000 33 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by Bill Paul. 46 * 4. Neither the name of the author nor the names of any co-contributors 47 * may be used to endorse or promote products derived from this software 48 * without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 51 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 53 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 60 * THE POSSIBILITY OF SUCH DAMAGE. 61 * 62 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 63 */ 64 65 /* 66 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 67 * 68 * Permission to use, copy, modify, and distribute this software for any 69 * purpose with or without fee is hereby granted, provided that the above 70 * copyright notice and this permission notice appear in all copies. 71 * 72 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 73 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 74 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 75 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 76 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 77 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 78 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 79 */ 80 81 /* 82 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 83 * the SK-984x series adapters, both single port and dual port. 84 * References: 85 * The XaQti XMAC II datasheet, 86 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 87 * The SysKonnect GEnesis manual, http://www.syskonnect.com 88 * 89 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 90 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 91 * convenience to others until Vitesse corrects this problem: 92 * 93 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * 95 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 96 * Department of Electrical Engineering 97 * Columbia University, New York City 98 */ 99 100 /* 101 * The SysKonnect gigabit ethernet adapters consist of two main 102 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 103 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 104 * components and a PHY while the GEnesis controller provides a PCI 105 * interface with DMA support. Each card may have between 512K and 106 * 2MB of SRAM on board depending on the configuration. 107 * 108 * The SysKonnect GEnesis controller can have either one or two XMAC 109 * chips connected to it, allowing single or dual port NIC configurations. 110 * SysKonnect has the distinction of being the only vendor on the market 111 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 112 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 113 * XMAC registers. This driver takes advantage of these features to allow 114 * both XMACs to operate as independent interfaces. 115 */ 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: if_sk.c,v 1.100 2019/06/03 15:49:04 msaitoh Exp $"); 119 120 #include <sys/param.h> 121 #include <sys/systm.h> 122 #include <sys/sockio.h> 123 #include <sys/mbuf.h> 124 #include <sys/malloc.h> 125 #include <sys/mutex.h> 126 #include <sys/kernel.h> 127 #include <sys/socket.h> 128 #include <sys/device.h> 129 #include <sys/queue.h> 130 #include <sys/callout.h> 131 #include <sys/sysctl.h> 132 #include <sys/endian.h> 133 134 #include <net/if.h> 135 #include <net/if_dl.h> 136 #include <net/if_types.h> 137 138 #include <net/if_media.h> 139 140 #include <net/bpf.h> 141 #include <sys/rndsource.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 #include <dev/mii/brgphyreg.h> 146 147 #include <dev/pci/pcireg.h> 148 #include <dev/pci/pcivar.h> 149 #include <dev/pci/pcidevs.h> 150 151 /* #define SK_USEIOSPACE */ 152 153 #include <dev/pci/if_skreg.h> 154 #include <dev/pci/if_skvar.h> 155 156 int skc_probe(device_t, cfdata_t, void *); 157 void skc_attach(device_t, device_t, void *); 158 int sk_probe(device_t, cfdata_t, void *); 159 void sk_attach(device_t, device_t, void *); 160 int skcprint(void *, const char *); 161 int sk_intr(void *); 162 void sk_intr_bcom(struct sk_if_softc *); 163 void sk_intr_xmac(struct sk_if_softc *); 164 void sk_intr_yukon(struct sk_if_softc *); 165 void sk_rxeof(struct sk_if_softc *); 166 void sk_txeof(struct sk_if_softc *); 167 int sk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *); 168 void sk_start(struct ifnet *); 169 int sk_ioctl(struct ifnet *, u_long, void *); 170 int sk_init(struct ifnet *); 171 void sk_unreset_xmac(struct sk_if_softc *); 172 void sk_init_xmac(struct sk_if_softc *); 173 void sk_unreset_yukon(struct sk_if_softc *); 174 void sk_init_yukon(struct sk_if_softc *); 175 void sk_stop(struct ifnet *, int); 176 void sk_watchdog(struct ifnet *); 177 void sk_shutdown(void *); 178 int sk_ifmedia_upd(struct ifnet *); 179 void sk_reset(struct sk_softc *); 180 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 181 int sk_alloc_jumbo_mem(struct sk_if_softc *); 182 void sk_free_jumbo_mem(struct sk_if_softc *); 183 void *sk_jalloc(struct sk_if_softc *); 184 void sk_jfree(struct mbuf *, void *, size_t, void *); 185 int sk_init_rx_ring(struct sk_if_softc *); 186 int sk_init_tx_ring(struct sk_if_softc *); 187 uint8_t sk_vpd_readbyte(struct sk_softc *, int); 188 void sk_vpd_read_res(struct sk_softc *, 189 struct vpd_res *, int); 190 void sk_vpd_read(struct sk_softc *); 191 192 void sk_update_int_mod(struct sk_softc *); 193 194 int sk_xmac_miibus_readreg(device_t, int, int, uint16_t *); 195 int sk_xmac_miibus_writereg(device_t, int, int, uint16_t); 196 void sk_xmac_miibus_statchg(struct ifnet *); 197 198 int sk_marv_miibus_readreg(device_t, int, int, uint16_t *); 199 int sk_marv_miibus_writereg(device_t, int, int, uint16_t); 200 void sk_marv_miibus_statchg(struct ifnet *); 201 202 uint32_t sk_xmac_hash(void *); 203 uint32_t sk_yukon_hash(void *); 204 void sk_setfilt(struct sk_if_softc *, void *, int); 205 void sk_setmulti(struct sk_if_softc *); 206 void sk_tick(void *); 207 208 static bool skc_suspend(device_t, const pmf_qual_t *); 209 static bool skc_resume(device_t, const pmf_qual_t *); 210 static bool sk_resume(device_t dv, const pmf_qual_t *); 211 212 /* #define SK_DEBUG 2 */ 213 #ifdef SK_DEBUG 214 #define DPRINTF(x) if (skdebug) printf x 215 #define DPRINTFN(n, x) if (skdebug >= (n)) printf x 216 int skdebug = SK_DEBUG; 217 218 void sk_dump_txdesc(struct sk_tx_desc *, int); 219 void sk_dump_mbuf(struct mbuf *); 220 void sk_dump_bytes(const char *, int); 221 #else 222 #define DPRINTF(x) 223 #define DPRINTFN(n, x) 224 #endif 225 226 static int sk_sysctl_handler(SYSCTLFN_PROTO); 227 static int sk_root_num; 228 229 /* supported device vendors */ 230 /* PCI_PRODUCT_DLINK_DGE560T_2 might belong in if_msk instead */ 231 static const struct sk_product { 232 pci_vendor_id_t sk_vendor; 233 pci_product_id_t sk_product; 234 } sk_products[] = { 235 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 236 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 237 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 238 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 239 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 240 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 241 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 242 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 243 { 0, 0, } 244 }; 245 246 #define SK_LINKSYS_EG1032_SUBID 0x00151737 247 248 static inline uint32_t 249 sk_win_read_4(struct sk_softc *sc, uint32_t reg) 250 { 251 #ifdef SK_USEIOSPACE 252 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 253 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 254 #else 255 return CSR_READ_4(sc, reg); 256 #endif 257 } 258 259 static inline uint16_t 260 sk_win_read_2(struct sk_softc *sc, uint32_t reg) 261 { 262 #ifdef SK_USEIOSPACE 263 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 264 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 265 #else 266 return CSR_READ_2(sc, reg); 267 #endif 268 } 269 270 static inline uint8_t 271 sk_win_read_1(struct sk_softc *sc, uint32_t reg) 272 { 273 #ifdef SK_USEIOSPACE 274 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 275 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 276 #else 277 return CSR_READ_1(sc, reg); 278 #endif 279 } 280 281 static inline void 282 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x) 283 { 284 #ifdef SK_USEIOSPACE 285 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 286 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 287 #else 288 CSR_WRITE_4(sc, reg, x); 289 #endif 290 } 291 292 static inline void 293 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x) 294 { 295 #ifdef SK_USEIOSPACE 296 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 297 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 298 #else 299 CSR_WRITE_2(sc, reg, x); 300 #endif 301 } 302 303 static inline void 304 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x) 305 { 306 #ifdef SK_USEIOSPACE 307 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 308 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 309 #else 310 CSR_WRITE_1(sc, reg, x); 311 #endif 312 } 313 314 /* 315 * The VPD EEPROM contains Vital Product Data, as suggested in 316 * the PCI 2.1 specification. The VPD data is separared into areas 317 * denoted by resource IDs. The SysKonnect VPD contains an ID string 318 * resource (the name of the adapter), a read-only area resource 319 * containing various key/data fields and a read/write area which 320 * can be used to store asset management information or log messages. 321 * We read the ID string and read-only into buffers attached to 322 * the controller softc structure for later use. At the moment, 323 * we only use the ID string during sk_attach(). 324 */ 325 uint8_t 326 sk_vpd_readbyte(struct sk_softc *sc, int addr) 327 { 328 int i; 329 330 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 331 for (i = 0; i < SK_TIMEOUT; i++) { 332 DELAY(1); 333 if (sk_win_read_2(sc, 334 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 335 break; 336 } 337 338 if (i == SK_TIMEOUT) 339 return 0; 340 341 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 342 } 343 344 void 345 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 346 { 347 int i; 348 uint8_t *ptr; 349 350 ptr = (uint8_t *)res; 351 for (i = 0; i < sizeof(struct vpd_res); i++) 352 ptr[i] = sk_vpd_readbyte(sc, i + addr); 353 } 354 355 void 356 sk_vpd_read(struct sk_softc *sc) 357 { 358 int pos = 0, i; 359 struct vpd_res res; 360 361 if (sc->sk_vpd_prodname != NULL) 362 free(sc->sk_vpd_prodname, M_DEVBUF); 363 if (sc->sk_vpd_readonly != NULL) 364 free(sc->sk_vpd_readonly, M_DEVBUF); 365 sc->sk_vpd_prodname = NULL; 366 sc->sk_vpd_readonly = NULL; 367 368 sk_vpd_read_res(sc, &res, pos); 369 370 if (res.vr_id != VPD_RES_ID) { 371 aprint_error_dev(sc->sk_dev, 372 "bad VPD resource id: expected %x got %x\n", 373 VPD_RES_ID, res.vr_id); 374 return; 375 } 376 377 pos += sizeof(res); 378 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 379 if (sc->sk_vpd_prodname == NULL) 380 panic("sk_vpd_read"); 381 for (i = 0; i < res.vr_len; i++) 382 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 383 sc->sk_vpd_prodname[i] = '\0'; 384 pos += i; 385 386 sk_vpd_read_res(sc, &res, pos); 387 388 if (res.vr_id != VPD_RES_READ) { 389 aprint_error_dev(sc->sk_dev, 390 "bad VPD resource id: expected %x got %x\n", 391 VPD_RES_READ, res.vr_id); 392 return; 393 } 394 395 pos += sizeof(res); 396 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 397 if (sc->sk_vpd_readonly == NULL) 398 panic("sk_vpd_read"); 399 for (i = 0; i < res.vr_len ; i++) 400 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 401 } 402 403 int 404 sk_xmac_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 405 { 406 struct sk_if_softc *sc_if = device_private(dev); 407 int i; 408 409 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 410 411 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 412 return -1; 413 414 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 415 SK_XM_READ_2(sc_if, XM_PHY_DATA); 416 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 417 for (i = 0; i < SK_TIMEOUT; i++) { 418 DELAY(1); 419 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 420 XM_MMUCMD_PHYDATARDY) 421 break; 422 } 423 424 if (i == SK_TIMEOUT) { 425 aprint_error_dev(sc_if->sk_dev, 426 "phy failed to come ready\n"); 427 return ETIMEDOUT; 428 } 429 } 430 DELAY(1); 431 *val = SK_XM_READ_2(sc_if, XM_PHY_DATA); 432 return 0; 433 } 434 435 int 436 sk_xmac_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 437 { 438 struct sk_if_softc *sc_if = device_private(dev); 439 int i; 440 441 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 442 443 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 444 for (i = 0; i < SK_TIMEOUT; i++) { 445 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 446 break; 447 } 448 449 if (i == SK_TIMEOUT) { 450 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 451 return ETIMEDOUT; 452 } 453 454 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 455 for (i = 0; i < SK_TIMEOUT; i++) { 456 DELAY(1); 457 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 458 break; 459 } 460 461 if (i == SK_TIMEOUT) { 462 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 463 return ETIMEDOUT; 464 } 465 466 return 0; 467 } 468 469 void 470 sk_xmac_miibus_statchg(struct ifnet *ifp) 471 { 472 struct sk_if_softc *sc_if = ifp->if_softc; 473 struct mii_data *mii = &sc_if->sk_mii; 474 475 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 476 477 /* 478 * If this is a GMII PHY, manually set the XMAC's 479 * duplex mode accordingly. 480 */ 481 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 482 if ((mii->mii_media_active & IFM_FDX) != 0) 483 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 484 else 485 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 486 } 487 } 488 489 int 490 sk_marv_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 491 { 492 struct sk_if_softc *sc_if = device_private(dev); 493 uint16_t data; 494 int i; 495 496 if (phy != 0 || 497 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 498 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 499 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 500 phy, reg)); 501 return -1; 502 } 503 504 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 505 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 506 507 for (i = 0; i < SK_TIMEOUT; i++) { 508 DELAY(1); 509 data = SK_YU_READ_2(sc_if, YUKON_SMICR); 510 if (data & YU_SMICR_READ_VALID) 511 break; 512 } 513 514 if (i == SK_TIMEOUT) { 515 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 516 return ETIMEDOUT; 517 } 518 519 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 520 SK_TIMEOUT)); 521 522 *val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 523 524 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#hx\n", 525 phy, reg, *val)); 526 527 return 0; 528 } 529 530 int 531 sk_marv_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 532 { 533 struct sk_if_softc *sc_if = device_private(dev); 534 int i; 535 536 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#hx\n", 537 phy, reg, val)); 538 539 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 540 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 541 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 542 543 for (i = 0; i < SK_TIMEOUT; i++) { 544 DELAY(1); 545 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 546 break; 547 } 548 549 if (i == SK_TIMEOUT) { 550 printf("%s: phy write timed out\n", 551 device_xname(sc_if->sk_dev)); 552 return ETIMEDOUT; 553 } 554 555 return 0; 556 } 557 558 void 559 sk_marv_miibus_statchg(struct ifnet *ifp) 560 { 561 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 562 SK_YU_READ_2(((struct sk_if_softc *)ifp->if_softc), 563 YUKON_GPCR))); 564 } 565 566 uint32_t 567 sk_xmac_hash(void *addr) 568 { 569 uint32_t crc; 570 571 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 572 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 573 DPRINTFN(2,("multicast hash for %s is %x\n", ether_sprintf(addr),crc)); 574 return crc; 575 } 576 577 uint32_t 578 sk_yukon_hash(void *addr) 579 { 580 uint32_t crc; 581 582 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 583 crc &= ((1 << SK_HASH_BITS) - 1); 584 DPRINTFN(2,("multicast hash for %s is %x\n", ether_sprintf(addr),crc)); 585 return crc; 586 } 587 588 void 589 sk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 590 { 591 char *addr = addrv; 592 int base = XM_RXFILT_ENTRY(slot); 593 594 SK_XM_WRITE_2(sc_if, base, *(uint16_t *)(&addr[0])); 595 SK_XM_WRITE_2(sc_if, base + 2, *(uint16_t *)(&addr[2])); 596 SK_XM_WRITE_2(sc_if, base + 4, *(uint16_t *)(&addr[4])); 597 } 598 599 void 600 sk_setmulti(struct sk_if_softc *sc_if) 601 { 602 struct sk_softc *sc = sc_if->sk_softc; 603 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 604 uint32_t hashes[2] = { 0, 0 }; 605 int h = 0, i; 606 struct ethercom *ec = &sc_if->sk_ethercom; 607 struct ether_multi *enm; 608 struct ether_multistep step; 609 uint8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 610 611 /* First, zot all the existing filters. */ 612 switch (sc->sk_type) { 613 case SK_GENESIS: 614 for (i = 1; i < XM_RXFILT_MAX; i++) 615 sk_setfilt(sc_if, (void *)&dummy, i); 616 617 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 618 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 619 break; 620 case SK_YUKON: 621 case SK_YUKON_LITE: 622 case SK_YUKON_LP: 623 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 624 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 625 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 626 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 627 break; 628 } 629 630 /* Now program new ones. */ 631 allmulti: 632 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 633 hashes[0] = 0xFFFFFFFF; 634 hashes[1] = 0xFFFFFFFF; 635 } else { 636 i = 1; 637 /* First find the tail of the list. */ 638 ETHER_LOCK(ec); 639 ETHER_FIRST_MULTI(step, ec, enm); 640 while (enm != NULL) { 641 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 642 ETHER_ADDR_LEN)) { 643 ifp->if_flags |= IFF_ALLMULTI; 644 ETHER_UNLOCK(ec); 645 goto allmulti; 646 } 647 DPRINTFN(2,("multicast address %s\n", 648 ether_sprintf(enm->enm_addrlo))); 649 /* 650 * Program the first XM_RXFILT_MAX multicast groups 651 * into the perfect filter. For all others, 652 * use the hash table. 653 */ 654 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 655 sk_setfilt(sc_if, enm->enm_addrlo, i); 656 i++; 657 } 658 else { 659 switch (sc->sk_type) { 660 case SK_GENESIS: 661 h = sk_xmac_hash(enm->enm_addrlo); 662 break; 663 case SK_YUKON: 664 case SK_YUKON_LITE: 665 case SK_YUKON_LP: 666 h = sk_yukon_hash(enm->enm_addrlo); 667 break; 668 } 669 if (h < 32) 670 hashes[0] |= (1 << h); 671 else 672 hashes[1] |= (1 << (h - 32)); 673 } 674 675 ETHER_NEXT_MULTI(step, enm); 676 } 677 ETHER_UNLOCK(ec); 678 } 679 680 switch (sc->sk_type) { 681 case SK_GENESIS: 682 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH | 683 XM_MODE_RX_USE_PERFECT); 684 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 685 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 686 break; 687 case SK_YUKON: 688 case SK_YUKON_LITE: 689 case SK_YUKON_LP: 690 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 691 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 692 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 693 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 694 break; 695 } 696 } 697 698 int 699 sk_init_rx_ring(struct sk_if_softc *sc_if) 700 { 701 struct sk_chain_data *cd = &sc_if->sk_cdata; 702 struct sk_ring_data *rd = sc_if->sk_rdata; 703 int i; 704 705 memset((char *)rd->sk_rx_ring, 0, 706 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 707 708 for (i = 0; i < SK_RX_RING_CNT; i++) { 709 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 710 if (i == (SK_RX_RING_CNT - 1)) { 711 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 712 rd->sk_rx_ring[i].sk_next = 713 htole32(SK_RX_RING_ADDR(sc_if, 0)); 714 } else { 715 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 716 rd->sk_rx_ring[i].sk_next = 717 htole32(SK_RX_RING_ADDR(sc_if, i+1)); 718 } 719 } 720 721 for (i = 0; i < SK_RX_RING_CNT; i++) { 722 if (sk_newbuf(sc_if, i, NULL, 723 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 724 aprint_error_dev(sc_if->sk_dev, 725 "failed alloc of %dth mbuf\n", i); 726 return ENOBUFS; 727 } 728 } 729 sc_if->sk_cdata.sk_rx_prod = 0; 730 sc_if->sk_cdata.sk_rx_cons = 0; 731 732 return 0; 733 } 734 735 int 736 sk_init_tx_ring(struct sk_if_softc *sc_if) 737 { 738 struct sk_chain_data *cd = &sc_if->sk_cdata; 739 struct sk_ring_data *rd = sc_if->sk_rdata; 740 int i; 741 742 memset(sc_if->sk_rdata->sk_tx_ring, 0, 743 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 744 745 for (i = 0; i < SK_TX_RING_CNT; i++) { 746 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 747 if (i == (SK_TX_RING_CNT - 1)) { 748 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 749 rd->sk_tx_ring[i].sk_next = 750 htole32(SK_TX_RING_ADDR(sc_if, 0)); 751 } else { 752 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 753 rd->sk_tx_ring[i].sk_next = 754 htole32(SK_TX_RING_ADDR(sc_if, i+1)); 755 } 756 } 757 758 sc_if->sk_cdata.sk_tx_prod = 0; 759 sc_if->sk_cdata.sk_tx_cons = 0; 760 sc_if->sk_cdata.sk_tx_cnt = 0; 761 762 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 763 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 764 765 return 0; 766 } 767 768 int 769 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 770 bus_dmamap_t dmamap) 771 { 772 struct mbuf *m_new = NULL; 773 struct sk_chain *c; 774 struct sk_rx_desc *r; 775 776 if (m == NULL) { 777 void *buf = NULL; 778 779 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 780 if (m_new == NULL) { 781 aprint_error_dev(sc_if->sk_dev, 782 "no memory for rx list -- packet dropped!\n"); 783 return ENOBUFS; 784 } 785 786 /* Allocate the jumbo buffer */ 787 buf = sk_jalloc(sc_if); 788 if (buf == NULL) { 789 m_freem(m_new); 790 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 791 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 792 return ENOBUFS; 793 } 794 795 /* Attach the buffer to the mbuf */ 796 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 797 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 798 799 } else { 800 /* 801 * We're re-using a previously allocated mbuf; 802 * be sure to re-init pointers and lengths to 803 * default values. 804 */ 805 m_new = m; 806 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 807 m_new->m_data = m_new->m_ext.ext_buf; 808 } 809 m_adj(m_new, ETHER_ALIGN); 810 811 c = &sc_if->sk_cdata.sk_rx_chain[i]; 812 r = c->sk_desc; 813 c->sk_mbuf = m_new; 814 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 815 (((vaddr_t)m_new->m_data 816 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 817 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 818 819 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 820 821 return 0; 822 } 823 824 /* 825 * Memory management for jumbo frames. 826 */ 827 828 int 829 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 830 { 831 struct sk_softc *sc = sc_if->sk_softc; 832 char *ptr, *kva; 833 bus_dma_segment_t seg; 834 int i, rseg, state, error; 835 struct sk_jpool_entry *entry; 836 837 state = error = 0; 838 839 /* Grab a big chunk o' storage. */ 840 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 841 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 842 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 843 return ENOBUFS; 844 } 845 846 state = 1; 847 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, (void **)&kva, 848 BUS_DMA_NOWAIT)) { 849 aprint_error_dev(sc->sk_dev, 850 "can't map dma buffers (%d bytes)\n", 851 SK_JMEM); 852 error = ENOBUFS; 853 goto out; 854 } 855 856 state = 2; 857 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 858 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 859 aprint_error_dev(sc->sk_dev, "can't create dma map\n"); 860 error = ENOBUFS; 861 goto out; 862 } 863 864 state = 3; 865 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 866 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 867 aprint_error_dev(sc->sk_dev, "can't load dma map\n"); 868 error = ENOBUFS; 869 goto out; 870 } 871 872 state = 4; 873 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 874 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 875 876 LIST_INIT(&sc_if->sk_jfree_listhead); 877 LIST_INIT(&sc_if->sk_jinuse_listhead); 878 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 879 880 /* 881 * Now divide it up into 9K pieces and save the addresses 882 * in an array. 883 */ 884 ptr = sc_if->sk_cdata.sk_jumbo_buf; 885 for (i = 0; i < SK_JSLOTS; i++) { 886 sc_if->sk_cdata.sk_jslots[i] = ptr; 887 ptr += SK_JLEN; 888 entry = malloc(sizeof(struct sk_jpool_entry), 889 M_DEVBUF, M_NOWAIT); 890 if (entry == NULL) { 891 aprint_error_dev(sc->sk_dev, 892 "no memory for jumbo buffer queue!\n"); 893 error = ENOBUFS; 894 goto out; 895 } 896 entry->slot = i; 897 if (i) 898 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 899 entry, jpool_entries); 900 else 901 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 902 entry, jpool_entries); 903 } 904 out: 905 if (error != 0) { 906 switch (state) { 907 case 4: 908 bus_dmamap_unload(sc->sc_dmatag, 909 sc_if->sk_cdata.sk_rx_jumbo_map); 910 /* FALLTHROUGH */ 911 case 3: 912 bus_dmamap_destroy(sc->sc_dmatag, 913 sc_if->sk_cdata.sk_rx_jumbo_map); 914 /* FALLTHROUGH */ 915 case 2: 916 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 917 /* FALLTHROUGH */ 918 case 1: 919 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 920 break; 921 default: 922 break; 923 } 924 } 925 926 return error; 927 } 928 929 /* 930 * Allocate a jumbo buffer. 931 */ 932 void * 933 sk_jalloc(struct sk_if_softc *sc_if) 934 { 935 struct sk_jpool_entry *entry; 936 937 mutex_enter(&sc_if->sk_jpool_mtx); 938 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 939 940 if (entry == NULL) { 941 mutex_exit(&sc_if->sk_jpool_mtx); 942 return NULL; 943 } 944 945 LIST_REMOVE(entry, jpool_entries); 946 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 947 mutex_exit(&sc_if->sk_jpool_mtx); 948 return sc_if->sk_cdata.sk_jslots[entry->slot]; 949 } 950 951 /* 952 * Release a jumbo buffer. 953 */ 954 void 955 sk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 956 { 957 struct sk_jpool_entry *entry; 958 struct sk_if_softc *sc; 959 int i; 960 961 /* Extract the softc struct pointer. */ 962 sc = (struct sk_if_softc *)arg; 963 964 if (sc == NULL) 965 panic("sk_jfree: can't find softc pointer!"); 966 967 /* calculate the slot this buffer belongs to */ 968 969 i = ((vaddr_t)buf 970 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 971 972 if ((i < 0) || (i >= SK_JSLOTS)) 973 panic("sk_jfree: asked to free buffer that we don't manage!"); 974 975 mutex_enter(&sc->sk_jpool_mtx); 976 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 977 if (entry == NULL) 978 panic("sk_jfree: buffer not in use!"); 979 entry->slot = i; 980 LIST_REMOVE(entry, jpool_entries); 981 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 982 mutex_exit(&sc->sk_jpool_mtx); 983 984 if (__predict_true(m != NULL)) 985 pool_cache_put(mb_cache, m); 986 } 987 988 /* 989 * Set media options. 990 */ 991 int 992 sk_ifmedia_upd(struct ifnet *ifp) 993 { 994 struct sk_if_softc *sc_if = ifp->if_softc; 995 int rc; 996 997 (void) sk_init(ifp); 998 if ((rc = mii_mediachg(&sc_if->sk_mii)) == ENXIO) 999 return 0; 1000 return rc; 1001 } 1002 1003 static void 1004 sk_promisc(struct sk_if_softc *sc_if, int on) 1005 { 1006 struct sk_softc *sc = sc_if->sk_softc; 1007 switch (sc->sk_type) { 1008 case SK_GENESIS: 1009 if (on) 1010 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1011 else 1012 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1013 break; 1014 case SK_YUKON: 1015 case SK_YUKON_LITE: 1016 case SK_YUKON_LP: 1017 if (on) 1018 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1019 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1020 else 1021 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1022 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1023 break; 1024 default: 1025 aprint_error_dev(sc_if->sk_dev, "Can't set promisc for %d\n", 1026 sc->sk_type); 1027 break; 1028 } 1029 } 1030 1031 int 1032 sk_ioctl(struct ifnet *ifp, u_long command, void *data) 1033 { 1034 struct sk_if_softc *sc_if = ifp->if_softc; 1035 int s, error = 0; 1036 1037 /* DPRINTFN(2, ("sk_ioctl\n")); */ 1038 1039 s = splnet(); 1040 1041 switch (command) { 1042 1043 case SIOCSIFFLAGS: 1044 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1045 if ((error = ifioctl_common(ifp, command, data)) != 0) 1046 break; 1047 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 1048 case IFF_RUNNING: 1049 sk_stop(ifp, 1); 1050 break; 1051 case IFF_UP: 1052 sk_init(ifp); 1053 break; 1054 case IFF_UP | IFF_RUNNING: 1055 if ((ifp->if_flags ^ sc_if->sk_if_flags) == IFF_PROMISC) { 1056 sk_promisc(sc_if, ifp->if_flags & IFF_PROMISC); 1057 sk_setmulti(sc_if); 1058 } else 1059 sk_init(ifp); 1060 break; 1061 } 1062 sc_if->sk_if_flags = ifp->if_flags; 1063 error = 0; 1064 break; 1065 1066 default: 1067 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1068 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1069 break; 1070 1071 error = 0; 1072 1073 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1074 ; 1075 else if (ifp->if_flags & IFF_RUNNING) { 1076 sk_setmulti(sc_if); 1077 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1078 } 1079 break; 1080 } 1081 1082 splx(s); 1083 return error; 1084 } 1085 1086 void 1087 sk_update_int_mod(struct sk_softc *sc) 1088 { 1089 uint32_t imtimer_ticks; 1090 1091 /* 1092 * Configure interrupt moderation. The moderation timer 1093 * defers interrupts specified in the interrupt moderation 1094 * timer mask based on the timeout specified in the interrupt 1095 * moderation timer init register. Each bit in the timer 1096 * register represents one tick, so to specify a timeout in 1097 * microseconds, we have to multiply by the correct number of 1098 * ticks-per-microsecond. 1099 */ 1100 switch (sc->sk_type) { 1101 case SK_GENESIS: 1102 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1103 break; 1104 case SK_YUKON_EC: 1105 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1106 break; 1107 default: 1108 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1109 } 1110 aprint_verbose_dev(sc->sk_dev, "interrupt moderation is %d us\n", 1111 sc->sk_int_mod); 1112 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1113 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF | SK_ISR_TX2_S_EOF | 1114 SK_ISR_RX1_EOF | SK_ISR_RX2_EOF); 1115 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1116 sc->sk_int_mod_pending = 0; 1117 } 1118 1119 /* 1120 * Lookup: Check the PCI vendor and device, and return a pointer to 1121 * The structure if the IDs match against our list. 1122 */ 1123 1124 static const struct sk_product * 1125 sk_lookup(const struct pci_attach_args *pa) 1126 { 1127 const struct sk_product *psk; 1128 1129 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1130 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1131 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1132 return psk; 1133 } 1134 return NULL; 1135 } 1136 1137 /* 1138 * Probe for a SysKonnect GEnesis chip. 1139 */ 1140 1141 int 1142 skc_probe(device_t parent, cfdata_t match, void *aux) 1143 { 1144 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1145 const struct sk_product *psk; 1146 pcireg_t subid; 1147 1148 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1149 1150 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1151 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1152 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1153 subid == SK_LINKSYS_EG1032_SUBID) 1154 return 1; 1155 1156 if ((psk = sk_lookup(pa))) { 1157 return 1; 1158 } 1159 return 0; 1160 } 1161 1162 /* 1163 * Force the GEnesis into reset, then bring it out of reset. 1164 */ 1165 void 1166 sk_reset(struct sk_softc *sc) 1167 { 1168 DPRINTFN(2, ("sk_reset\n")); 1169 1170 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1171 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1172 if (SK_YUKON_FAMILY(sc->sk_type)) 1173 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1174 1175 DELAY(1000); 1176 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1177 DELAY(2); 1178 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1179 if (SK_YUKON_FAMILY(sc->sk_type)) 1180 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1181 1182 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1183 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1184 CSR_READ_2(sc, SK_LINK_CTRL))); 1185 1186 if (sc->sk_type == SK_GENESIS) { 1187 /* Configure packet arbiter */ 1188 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1189 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1190 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1191 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1192 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1193 } 1194 1195 /* Enable RAM interface */ 1196 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1197 1198 sk_update_int_mod(sc); 1199 } 1200 1201 int 1202 sk_probe(device_t parent, cfdata_t match, void *aux) 1203 { 1204 struct skc_attach_args *sa = aux; 1205 1206 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1207 return 0; 1208 1209 return 1; 1210 } 1211 1212 /* 1213 * Each XMAC chip is attached as a separate logical IP interface. 1214 * Single port cards will have only one logical interface of course. 1215 */ 1216 void 1217 sk_attach(device_t parent, device_t self, void *aux) 1218 { 1219 struct sk_if_softc *sc_if = device_private(self); 1220 struct mii_data *mii = &sc_if->sk_mii; 1221 struct sk_softc *sc = device_private(parent); 1222 struct skc_attach_args *sa = aux; 1223 struct sk_txmap_entry *entry; 1224 struct ifnet *ifp; 1225 bus_dma_segment_t seg; 1226 bus_dmamap_t dmamap; 1227 prop_data_t data; 1228 void *kva; 1229 int i, rseg; 1230 int mii_flags = 0; 1231 1232 aprint_naive("\n"); 1233 1234 sc_if->sk_dev = self; 1235 sc_if->sk_port = sa->skc_port; 1236 sc_if->sk_softc = sc; 1237 sc->sk_if[sa->skc_port] = sc_if; 1238 1239 if (sa->skc_port == SK_PORT_A) 1240 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1241 if (sa->skc_port == SK_PORT_B) 1242 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1243 1244 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1245 1246 /* 1247 * Get station address for this interface. Note that 1248 * dual port cards actually come with three station 1249 * addresses: one for each port, plus an extra. The 1250 * extra one is used by the SysKonnect driver software 1251 * as a 'virtual' station address for when both ports 1252 * are operating in failover mode. Currently we don't 1253 * use this extra address. 1254 */ 1255 data = prop_dictionary_get(device_properties(self), "mac-address"); 1256 if (data != NULL) { 1257 /* 1258 * Try to get the station address from device properties 1259 * first, in case the ROM is missing. 1260 */ 1261 KASSERT(prop_object_type(data) == PROP_TYPE_DATA); 1262 KASSERT(prop_data_size(data) == ETHER_ADDR_LEN); 1263 memcpy(sc_if->sk_enaddr, prop_data_data_nocopy(data), 1264 ETHER_ADDR_LEN); 1265 } else 1266 for (i = 0; i < ETHER_ADDR_LEN; i++) 1267 sc_if->sk_enaddr[i] = sk_win_read_1(sc, 1268 SK_MAC0_0 + (sa->skc_port * 8) + i); 1269 1270 aprint_normal(": Ethernet address %s\n", 1271 ether_sprintf(sc_if->sk_enaddr)); 1272 1273 /* 1274 * Set up RAM buffer addresses. The NIC will have a certain 1275 * amount of SRAM on it, somewhere between 512K and 2MB. We 1276 * need to divide this up a) between the transmitter and 1277 * receiver and b) between the two XMACs, if this is a 1278 * dual port NIC. Our algorithm is to divide up the memory 1279 * evenly so that everyone gets a fair share. 1280 */ 1281 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1282 uint32_t chunk, val; 1283 1284 chunk = sc->sk_ramsize / 2; 1285 val = sc->sk_rboff / sizeof(uint64_t); 1286 sc_if->sk_rx_ramstart = val; 1287 val += (chunk / sizeof(uint64_t)); 1288 sc_if->sk_rx_ramend = val - 1; 1289 sc_if->sk_tx_ramstart = val; 1290 val += (chunk / sizeof(uint64_t)); 1291 sc_if->sk_tx_ramend = val - 1; 1292 } else { 1293 uint32_t chunk, val; 1294 1295 chunk = sc->sk_ramsize / 4; 1296 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1297 sizeof(uint64_t); 1298 sc_if->sk_rx_ramstart = val; 1299 val += (chunk / sizeof(uint64_t)); 1300 sc_if->sk_rx_ramend = val - 1; 1301 sc_if->sk_tx_ramstart = val; 1302 val += (chunk / sizeof(uint64_t)); 1303 sc_if->sk_tx_ramend = val - 1; 1304 } 1305 1306 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1307 " tx_ramstart=%#x tx_ramend=%#x\n", 1308 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1309 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1310 1311 /* Read and save PHY type and set PHY address */ 1312 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1313 switch (sc_if->sk_phytype) { 1314 case SK_PHYTYPE_XMAC: 1315 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1316 break; 1317 case SK_PHYTYPE_BCOM: 1318 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1319 break; 1320 case SK_PHYTYPE_MARV_COPPER: 1321 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1322 break; 1323 default: 1324 aprint_error_dev(sc->sk_dev, "unsupported PHY type: %d\n", 1325 sc_if->sk_phytype); 1326 return; 1327 } 1328 1329 /* Allocate the descriptor queues. */ 1330 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1331 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1332 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 1333 goto fail; 1334 } 1335 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1336 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1337 aprint_error_dev(sc_if->sk_dev, 1338 "can't map dma buffers (%lu bytes)\n", 1339 (u_long) sizeof(struct sk_ring_data)); 1340 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1341 goto fail; 1342 } 1343 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1344 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1345 &sc_if->sk_ring_map)) { 1346 aprint_error_dev(sc_if->sk_dev, "can't create dma map\n"); 1347 bus_dmamem_unmap(sc->sc_dmatag, kva, 1348 sizeof(struct sk_ring_data)); 1349 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1350 goto fail; 1351 } 1352 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1353 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1354 aprint_error_dev(sc_if->sk_dev, "can't load dma map\n"); 1355 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1356 bus_dmamem_unmap(sc->sc_dmatag, kva, 1357 sizeof(struct sk_ring_data)); 1358 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1359 goto fail; 1360 } 1361 1362 for (i = 0; i < SK_RX_RING_CNT; i++) 1363 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1364 1365 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1366 for (i = 0; i < SK_TX_RING_CNT; i++) { 1367 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1368 1369 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1370 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1371 aprint_error_dev(sc_if->sk_dev, 1372 "Can't create TX dmamap\n"); 1373 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1374 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1375 bus_dmamem_unmap(sc->sc_dmatag, kva, 1376 sizeof(struct sk_ring_data)); 1377 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1378 goto fail; 1379 } 1380 1381 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1382 if (!entry) { 1383 aprint_error_dev(sc_if->sk_dev, 1384 "Can't alloc txmap entry\n"); 1385 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1386 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1387 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1388 bus_dmamem_unmap(sc->sc_dmatag, kva, 1389 sizeof(struct sk_ring_data)); 1390 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1391 goto fail; 1392 } 1393 entry->dmamap = dmamap; 1394 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1395 } 1396 1397 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1398 memset(sc_if->sk_rdata, 0, sizeof(struct sk_ring_data)); 1399 1400 ifp = &sc_if->sk_ethercom.ec_if; 1401 /* Try to allocate memory for jumbo buffers. */ 1402 if (sk_alloc_jumbo_mem(sc_if)) { 1403 aprint_error("%s: jumbo buffer allocation failed\n", 1404 ifp->if_xname); 1405 goto fail; 1406 } 1407 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1408 | ETHERCAP_JUMBO_MTU; 1409 1410 ifp->if_softc = sc_if; 1411 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1412 ifp->if_ioctl = sk_ioctl; 1413 ifp->if_start = sk_start; 1414 ifp->if_stop = sk_stop; 1415 ifp->if_init = sk_init; 1416 ifp->if_watchdog = sk_watchdog; 1417 ifp->if_capabilities = 0; 1418 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1419 IFQ_SET_READY(&ifp->if_snd); 1420 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1421 1422 /* 1423 * Do miibus setup. 1424 */ 1425 switch (sc->sk_type) { 1426 case SK_GENESIS: 1427 sk_unreset_xmac(sc_if); 1428 break; 1429 case SK_YUKON: 1430 case SK_YUKON_LITE: 1431 case SK_YUKON_LP: 1432 sk_unreset_yukon(sc_if); 1433 break; 1434 default: 1435 aprint_error_dev(sc->sk_dev, "unknown device type %d\n", 1436 sc->sk_type); 1437 goto fail; 1438 } 1439 1440 DPRINTFN(2, ("sk_attach: 1\n")); 1441 1442 mii->mii_ifp = ifp; 1443 switch (sc->sk_type) { 1444 case SK_GENESIS: 1445 mii->mii_readreg = sk_xmac_miibus_readreg; 1446 mii->mii_writereg = sk_xmac_miibus_writereg; 1447 mii->mii_statchg = sk_xmac_miibus_statchg; 1448 break; 1449 case SK_YUKON: 1450 case SK_YUKON_LITE: 1451 case SK_YUKON_LP: 1452 mii->mii_readreg = sk_marv_miibus_readreg; 1453 mii->mii_writereg = sk_marv_miibus_writereg; 1454 mii->mii_statchg = sk_marv_miibus_statchg; 1455 mii_flags = MIIF_DOPAUSE; 1456 break; 1457 } 1458 1459 sc_if->sk_ethercom.ec_mii = mii; 1460 ifmedia_init(&mii->mii_media, 0, sk_ifmedia_upd, ether_mediastatus); 1461 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 1462 MII_OFFSET_ANY, mii_flags); 1463 if (LIST_EMPTY(&mii->mii_phys)) { 1464 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1465 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 1466 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 1467 } else 1468 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1469 1470 callout_init(&sc_if->sk_tick_ch, 0); 1471 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 1472 1473 DPRINTFN(2, ("sk_attach: 1\n")); 1474 1475 /* 1476 * Call MI attach routines. 1477 */ 1478 if_attach(ifp); 1479 if_deferred_start_init(ifp, NULL); 1480 1481 ether_ifattach(ifp, sc_if->sk_enaddr); 1482 1483 if (sc->rnd_attached++ == 0) { 1484 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1485 RND_TYPE_NET, RND_FLAG_DEFAULT); 1486 } 1487 1488 if (pmf_device_register(self, NULL, sk_resume)) 1489 pmf_class_network_register(self, ifp); 1490 else 1491 aprint_error_dev(self, "couldn't establish power handler\n"); 1492 1493 DPRINTFN(2, ("sk_attach: end\n")); 1494 1495 return; 1496 1497 fail: 1498 sc->sk_if[sa->skc_port] = NULL; 1499 } 1500 1501 int 1502 skcprint(void *aux, const char *pnp) 1503 { 1504 struct skc_attach_args *sa = aux; 1505 1506 if (pnp) 1507 aprint_normal("sk port %c at %s", 1508 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1509 else 1510 aprint_normal(" port %c", 1511 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1512 return UNCONF; 1513 } 1514 1515 /* 1516 * Attach the interface. Allocate softc structures, do ifmedia 1517 * setup and ethernet/BPF attach. 1518 */ 1519 void 1520 skc_attach(device_t parent, device_t self, void *aux) 1521 { 1522 struct sk_softc *sc = device_private(self); 1523 struct pci_attach_args *pa = aux; 1524 struct skc_attach_args skca; 1525 pci_chipset_tag_t pc = pa->pa_pc; 1526 #ifndef SK_USEIOSPACE 1527 pcireg_t memtype; 1528 #endif 1529 pci_intr_handle_t ih; 1530 const char *intrstr = NULL; 1531 bus_addr_t iobase; 1532 bus_size_t iosize; 1533 int rc, sk_nodenum; 1534 uint32_t command; 1535 const char *revstr; 1536 const struct sysctlnode *node; 1537 char intrbuf[PCI_INTRSTR_LEN]; 1538 1539 sc->sk_dev = self; 1540 aprint_naive("\n"); 1541 1542 DPRINTFN(2, ("begin skc_attach\n")); 1543 1544 /* 1545 * Handle power management nonsense. 1546 */ 1547 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1548 1549 if (command == 0x01) { 1550 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1551 if (command & SK_PSTATE_MASK) { 1552 uint32_t xiobase, membase, irq; 1553 1554 /* Save important PCI config data. */ 1555 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1556 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1557 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1558 1559 /* Reset the power state. */ 1560 aprint_normal_dev(sc->sk_dev, 1561 "chip is in D%d power mode -- setting to D0\n", 1562 command & SK_PSTATE_MASK); 1563 command &= 0xFFFFFFFC; 1564 pci_conf_write(pc, pa->pa_tag, 1565 SK_PCI_PWRMGMTCTRL, command); 1566 1567 /* Restore PCI config data. */ 1568 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1569 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1570 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1571 } 1572 } 1573 1574 /* 1575 * The firmware might have configured the interface to revert the 1576 * byte order in all descriptors. Make that undone. 1577 */ 1578 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_OURREG2); 1579 if (command & SK_REG2_REV_DESC) 1580 pci_conf_write(pc, pa->pa_tag, SK_PCI_OURREG2, 1581 command & ~SK_REG2_REV_DESC); 1582 1583 /* 1584 * Map control/status registers. 1585 */ 1586 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1587 command |= PCI_COMMAND_IO_ENABLE | 1588 PCI_COMMAND_MEM_ENABLE | 1589 PCI_COMMAND_MASTER_ENABLE; 1590 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1591 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1592 1593 #ifdef SK_USEIOSPACE 1594 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1595 aprint_error(": failed to enable I/O ports!\n"); 1596 return; 1597 } 1598 /* 1599 * Map control/status registers. 1600 */ 1601 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1602 &sc->sk_btag, &sc->sk_bhandle, 1603 &iobase, &iosize)) { 1604 aprint_error(": can't find i/o space\n"); 1605 return; 1606 } 1607 #else 1608 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1609 aprint_error(": failed to enable memory mapping!\n"); 1610 return; 1611 } 1612 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1613 switch (memtype) { 1614 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1615 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1616 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1617 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1618 &iobase, &iosize) == 0) 1619 break; 1620 /* FALLTHROUGH */ 1621 default: 1622 aprint_error_dev(sc->sk_dev, "can't find mem space\n"); 1623 return; 1624 } 1625 1626 DPRINTFN(2, ("skc_attach: iobase=%#" PRIxPADDR ", iosize=%zx\n", 1627 iobase, iosize)); 1628 #endif 1629 sc->sc_dmatag = pa->pa_dmat; 1630 1631 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1632 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1633 1634 /* bail out here if chip is not recognized */ 1635 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1636 aprint_error_dev(sc->sk_dev, "unknown chip type\n"); 1637 goto fail; 1638 } 1639 if (SK_IS_YUKON2(sc)) { 1640 aprint_error_dev(sc->sk_dev, 1641 "Does not support Yukon2--try msk(4).\n"); 1642 goto fail; 1643 } 1644 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1645 1646 /* Allocate interrupt */ 1647 if (pci_intr_map(pa, &ih)) { 1648 aprint_error(": couldn't map interrupt\n"); 1649 goto fail; 1650 } 1651 1652 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1653 sc->sk_intrhand = pci_intr_establish_xname(pc, ih, IPL_NET, sk_intr, 1654 sc, device_xname(sc->sk_dev)); 1655 if (sc->sk_intrhand == NULL) { 1656 aprint_error(": couldn't establish interrupt"); 1657 if (intrstr != NULL) 1658 aprint_error(" at %s", intrstr); 1659 aprint_error("\n"); 1660 goto fail; 1661 } 1662 aprint_normal(": %s\n", intrstr); 1663 1664 /* Reset the adapter. */ 1665 sk_reset(sc); 1666 1667 /* Read and save vital product data from EEPROM. */ 1668 sk_vpd_read(sc); 1669 1670 if (sc->sk_type == SK_GENESIS) { 1671 uint8_t val = sk_win_read_1(sc, SK_EPROM0); 1672 /* Read and save RAM size and RAMbuffer offset */ 1673 switch (val) { 1674 case SK_RAMSIZE_512K_64: 1675 sc->sk_ramsize = 0x80000; 1676 sc->sk_rboff = SK_RBOFF_0; 1677 break; 1678 case SK_RAMSIZE_1024K_64: 1679 sc->sk_ramsize = 0x100000; 1680 sc->sk_rboff = SK_RBOFF_80000; 1681 break; 1682 case SK_RAMSIZE_1024K_128: 1683 sc->sk_ramsize = 0x100000; 1684 sc->sk_rboff = SK_RBOFF_0; 1685 break; 1686 case SK_RAMSIZE_2048K_128: 1687 sc->sk_ramsize = 0x200000; 1688 sc->sk_rboff = SK_RBOFF_0; 1689 break; 1690 default: 1691 aprint_error_dev(sc->sk_dev, "unknown ram size: %d\n", 1692 val); 1693 goto fail_1; 1694 break; 1695 } 1696 1697 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1698 sc->sk_ramsize, sc->sk_ramsize / 1024, 1699 sc->sk_rboff)); 1700 } else { 1701 uint8_t val = sk_win_read_1(sc, SK_EPROM0); 1702 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1703 sc->sk_rboff = SK_RBOFF_0; 1704 1705 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1706 sc->sk_ramsize / 1024, sc->sk_ramsize, 1707 sc->sk_rboff)); 1708 } 1709 1710 /* Read and save physical media type */ 1711 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1712 case SK_PMD_1000BASESX: 1713 sc->sk_pmd = IFM_1000_SX; 1714 break; 1715 case SK_PMD_1000BASELX: 1716 sc->sk_pmd = IFM_1000_LX; 1717 break; 1718 case SK_PMD_1000BASECX: 1719 sc->sk_pmd = IFM_1000_CX; 1720 break; 1721 case SK_PMD_1000BASETX: 1722 case SK_PMD_1000BASETX_ALT: 1723 sc->sk_pmd = IFM_1000_T; 1724 break; 1725 default: 1726 aprint_error_dev(sc->sk_dev, "unknown media type: 0x%x\n", 1727 sk_win_read_1(sc, SK_PMDTYPE)); 1728 goto fail_1; 1729 } 1730 1731 /* determine whether to name it with vpd or just make it up */ 1732 /* Marvell Yukon VPD's can freqently be bogus */ 1733 1734 switch (pa->pa_id) { 1735 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1736 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1737 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1738 case PCI_PRODUCT_3COM_3C940: 1739 case PCI_PRODUCT_DLINK_DGE530T: 1740 case PCI_PRODUCT_DLINK_DGE560T: 1741 case PCI_PRODUCT_DLINK_DGE560T_2: 1742 case PCI_PRODUCT_LINKSYS_EG1032: 1743 case PCI_PRODUCT_LINKSYS_EG1064: 1744 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1745 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1746 case PCI_ID_CODE(PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940): 1747 case PCI_ID_CODE(PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T): 1748 case PCI_ID_CODE(PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T): 1749 case PCI_ID_CODE(PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2): 1750 case PCI_ID_CODE(PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032): 1751 case PCI_ID_CODE(PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064): 1752 sc->sk_name = sc->sk_vpd_prodname; 1753 break; 1754 case PCI_ID_CODE(PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET): 1755 /* whoops yukon vpd prodname bears no resemblance to reality */ 1756 switch (sc->sk_type) { 1757 case SK_GENESIS: 1758 sc->sk_name = sc->sk_vpd_prodname; 1759 break; 1760 case SK_YUKON: 1761 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1762 break; 1763 case SK_YUKON_LITE: 1764 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1765 break; 1766 case SK_YUKON_LP: 1767 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1768 break; 1769 default: 1770 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1771 } 1772 1773 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1774 1775 if ( sc->sk_type == SK_YUKON ) { 1776 uint32_t flashaddr; 1777 uint8_t testbyte; 1778 1779 flashaddr = sk_win_read_4(sc, SK_EP_ADDR); 1780 1781 /* test Flash-Address Register */ 1782 sk_win_write_1(sc, SK_EP_ADDR+3, 0xff); 1783 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1784 1785 if (testbyte != 0) { 1786 /* this is yukon lite Rev. A0 */ 1787 sc->sk_type = SK_YUKON_LITE; 1788 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1789 /* restore Flash-Address Register */ 1790 sk_win_write_4(sc, SK_EP_ADDR, flashaddr); 1791 } 1792 } 1793 break; 1794 case PCI_ID_CODE(PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN): 1795 sc->sk_name = sc->sk_vpd_prodname; 1796 break; 1797 default: 1798 sc->sk_name = "Unknown Marvell"; 1799 } 1800 1801 1802 if ( sc->sk_type == SK_YUKON_LITE ) { 1803 switch (sc->sk_rev) { 1804 case SK_YUKON_LITE_REV_A0: 1805 revstr = "A0"; 1806 break; 1807 case SK_YUKON_LITE_REV_A1: 1808 revstr = "A1"; 1809 break; 1810 case SK_YUKON_LITE_REV_A3: 1811 revstr = "A3"; 1812 break; 1813 default: 1814 revstr = ""; 1815 } 1816 } else { 1817 revstr = ""; 1818 } 1819 1820 /* Announce the product name. */ 1821 aprint_normal_dev(sc->sk_dev, "%s rev. %s(0x%x)\n", 1822 sc->sk_name, revstr, sc->sk_rev); 1823 1824 skca.skc_port = SK_PORT_A; 1825 (void)config_found(sc->sk_dev, &skca, skcprint); 1826 1827 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1828 skca.skc_port = SK_PORT_B; 1829 (void)config_found(sc->sk_dev, &skca, skcprint); 1830 } 1831 1832 /* Turn on the 'driver is loaded' LED. */ 1833 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1834 1835 /* skc sysctl setup */ 1836 1837 sc->sk_int_mod = SK_IM_DEFAULT; 1838 sc->sk_int_mod_pending = 0; 1839 1840 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1841 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1842 SYSCTL_DESCR("skc per-controller controls"), 1843 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1844 CTL_EOL)) != 0) { 1845 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1846 goto fail_1; 1847 } 1848 1849 sk_nodenum = node->sysctl_num; 1850 1851 /* interrupt moderation time in usecs */ 1852 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1853 CTLFLAG_READWRITE, 1854 CTLTYPE_INT, "int_mod", 1855 SYSCTL_DESCR("sk interrupt moderation timer"), 1856 sk_sysctl_handler, 0, (void *)sc, 1857 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1858 CTL_EOL)) != 0) { 1859 aprint_normal_dev(sc->sk_dev, 1860 "couldn't create int_mod sysctl node\n"); 1861 goto fail_1; 1862 } 1863 1864 if (!pmf_device_register(self, skc_suspend, skc_resume)) 1865 aprint_error_dev(self, "couldn't establish power handler\n"); 1866 1867 return; 1868 1869 fail_1: 1870 pci_intr_disestablish(pc, sc->sk_intrhand); 1871 fail: 1872 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1873 } 1874 1875 int 1876 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx) 1877 { 1878 struct sk_softc *sc = sc_if->sk_softc; 1879 struct sk_tx_desc *f = NULL; 1880 uint32_t frag, cur, cnt = 0, sk_ctl; 1881 int i; 1882 struct sk_txmap_entry *entry; 1883 bus_dmamap_t txmap; 1884 1885 DPRINTFN(3, ("sk_encap\n")); 1886 1887 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1888 if (entry == NULL) { 1889 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1890 return ENOBUFS; 1891 } 1892 txmap = entry->dmamap; 1893 1894 cur = frag = *txidx; 1895 1896 #ifdef SK_DEBUG 1897 if (skdebug >= 3) 1898 sk_dump_mbuf(m_head); 1899 #endif 1900 1901 /* 1902 * Start packing the mbufs in this chain into 1903 * the fragment pointers. Stop when we run out 1904 * of fragments or hit the end of the mbuf chain. 1905 */ 1906 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1907 BUS_DMA_NOWAIT)) { 1908 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1909 return ENOBUFS; 1910 } 1911 1912 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1913 1914 /* Sync the DMA map. */ 1915 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1916 BUS_DMASYNC_PREWRITE); 1917 1918 for (i = 0; i < txmap->dm_nsegs; i++) { 1919 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1920 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1921 return ENOBUFS; 1922 } 1923 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1924 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1925 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1926 if (cnt == 0) 1927 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1928 else 1929 sk_ctl |= SK_TXCTL_OWN; 1930 f->sk_ctl = htole32(sk_ctl); 1931 cur = frag; 1932 SK_INC(frag, SK_TX_RING_CNT); 1933 cnt++; 1934 } 1935 1936 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1937 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1938 1939 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1940 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1941 htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR); 1942 1943 /* Sync descriptors before handing to chip */ 1944 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1945 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1946 1947 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1948 htole32(SK_TXCTL_OWN); 1949 1950 /* Sync first descriptor to hand it off */ 1951 SK_CDTXSYNC(sc_if, *txidx, 1, 1952 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1953 1954 sc_if->sk_cdata.sk_tx_cnt += cnt; 1955 1956 #ifdef SK_DEBUG 1957 if (skdebug >= 3) { 1958 struct sk_tx_desc *desc; 1959 uint32_t idx; 1960 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1961 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1962 sk_dump_txdesc(desc, idx); 1963 } 1964 } 1965 #endif 1966 1967 *txidx = frag; 1968 1969 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1970 1971 return 0; 1972 } 1973 1974 void 1975 sk_start(struct ifnet *ifp) 1976 { 1977 struct sk_if_softc *sc_if = ifp->if_softc; 1978 struct sk_softc *sc = sc_if->sk_softc; 1979 struct mbuf *m_head = NULL; 1980 uint32_t idx = sc_if->sk_cdata.sk_tx_prod; 1981 int pkts = 0; 1982 1983 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1984 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1985 1986 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1987 IFQ_POLL(&ifp->if_snd, m_head); 1988 if (m_head == NULL) 1989 break; 1990 1991 /* 1992 * Pack the data into the transmit ring. If we 1993 * don't have room, set the OACTIVE flag and wait 1994 * for the NIC to drain the ring. 1995 */ 1996 if (sk_encap(sc_if, m_head, &idx)) { 1997 ifp->if_flags |= IFF_OACTIVE; 1998 break; 1999 } 2000 2001 /* now we are committed to transmit the packet */ 2002 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2003 pkts++; 2004 2005 /* 2006 * If there's a BPF listener, bounce a copy of this frame 2007 * to him. 2008 */ 2009 bpf_mtap(ifp, m_head, BPF_D_OUT); 2010 } 2011 if (pkts == 0) 2012 return; 2013 2014 /* Transmit */ 2015 if (idx != sc_if->sk_cdata.sk_tx_prod) { 2016 sc_if->sk_cdata.sk_tx_prod = idx; 2017 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2018 2019 /* Set a timeout in case the chip goes out to lunch. */ 2020 ifp->if_timer = 5; 2021 } 2022 } 2023 2024 2025 void 2026 sk_watchdog(struct ifnet *ifp) 2027 { 2028 struct sk_if_softc *sc_if = ifp->if_softc; 2029 2030 /* 2031 * Reclaim first as there is a possibility of losing Tx completion 2032 * interrupts. 2033 */ 2034 sk_txeof(sc_if); 2035 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 2036 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 2037 2038 ifp->if_oerrors++; 2039 2040 sk_init(ifp); 2041 } 2042 } 2043 2044 void 2045 sk_shutdown(void *v) 2046 { 2047 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 2048 struct sk_softc *sc = sc_if->sk_softc; 2049 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2050 2051 DPRINTFN(2, ("sk_shutdown\n")); 2052 sk_stop(ifp, 1); 2053 2054 /* Turn off the 'driver is loaded' LED. */ 2055 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2056 2057 /* 2058 * Reset the GEnesis controller. Doing this should also 2059 * assert the resets on the attached XMAC(s). 2060 */ 2061 sk_reset(sc); 2062 } 2063 2064 void 2065 sk_rxeof(struct sk_if_softc *sc_if) 2066 { 2067 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2068 struct mbuf *m; 2069 struct sk_chain *cur_rx; 2070 struct sk_rx_desc *cur_desc; 2071 int i, cur, total_len = 0; 2072 uint32_t rxstat, sk_ctl; 2073 bus_dmamap_t dmamap; 2074 2075 i = sc_if->sk_cdata.sk_rx_prod; 2076 2077 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2078 2079 for (;;) { 2080 cur = i; 2081 2082 /* Sync the descriptor */ 2083 SK_CDRXSYNC(sc_if, cur, 2084 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2085 2086 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2087 if (sk_ctl & SK_RXCTL_OWN) { 2088 /* Invalidate the descriptor -- it's not ready yet */ 2089 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2090 sc_if->sk_cdata.sk_rx_prod = i; 2091 break; 2092 } 2093 2094 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2095 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2096 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2097 2098 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2099 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2100 2101 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2102 m = cur_rx->sk_mbuf; 2103 cur_rx->sk_mbuf = NULL; 2104 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2105 2106 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2107 2108 SK_INC(i, SK_RX_RING_CNT); 2109 2110 if (rxstat & XM_RXSTAT_ERRFRAME) { 2111 ifp->if_ierrors++; 2112 sk_newbuf(sc_if, cur, m, dmamap); 2113 continue; 2114 } 2115 2116 /* 2117 * Try to allocate a new jumbo buffer. If that 2118 * fails, copy the packet to mbufs and put the 2119 * jumbo buffer back in the ring so it can be 2120 * re-used. If allocating mbufs fails, then we 2121 * have to drop the packet. 2122 */ 2123 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2124 struct mbuf *m0; 2125 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2126 total_len + ETHER_ALIGN, 0, ifp); 2127 sk_newbuf(sc_if, cur, m, dmamap); 2128 if (m0 == NULL) { 2129 aprint_error_dev(sc_if->sk_dev, "no receive " 2130 "buffers available -- packet dropped!\n"); 2131 ifp->if_ierrors++; 2132 continue; 2133 } 2134 m_adj(m0, ETHER_ALIGN); 2135 m = m0; 2136 } else { 2137 m_set_rcvif(m, ifp); 2138 m->m_pkthdr.len = m->m_len = total_len; 2139 } 2140 2141 /* pass it on. */ 2142 if_percpuq_enqueue(ifp->if_percpuq, m); 2143 } 2144 } 2145 2146 void 2147 sk_txeof(struct sk_if_softc *sc_if) 2148 { 2149 struct sk_softc *sc = sc_if->sk_softc; 2150 struct sk_tx_desc *cur_tx; 2151 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2152 uint32_t idx, sk_ctl; 2153 struct sk_txmap_entry *entry; 2154 2155 DPRINTFN(3, ("sk_txeof\n")); 2156 2157 /* 2158 * Go through our tx ring and free mbufs for those 2159 * frames that have been sent. 2160 */ 2161 idx = sc_if->sk_cdata.sk_tx_cons; 2162 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2163 SK_CDTXSYNC(sc_if, idx, 1, 2164 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2165 2166 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2167 sk_ctl = le32toh(cur_tx->sk_ctl); 2168 #ifdef SK_DEBUG 2169 if (skdebug >= 3) 2170 sk_dump_txdesc(cur_tx, idx); 2171 #endif 2172 if (sk_ctl & SK_TXCTL_OWN) { 2173 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2174 break; 2175 } 2176 if (sk_ctl & SK_TXCTL_LASTFRAG) 2177 ifp->if_opackets++; 2178 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2179 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2180 2181 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2182 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2183 2184 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2185 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2186 2187 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2188 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2189 link); 2190 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2191 } 2192 sc_if->sk_cdata.sk_tx_cnt--; 2193 SK_INC(idx, SK_TX_RING_CNT); 2194 } 2195 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2196 ifp->if_timer = 0; 2197 else /* nudge chip to keep tx ring moving */ 2198 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2199 2200 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2201 ifp->if_flags &= ~IFF_OACTIVE; 2202 2203 sc_if->sk_cdata.sk_tx_cons = idx; 2204 } 2205 2206 void 2207 sk_tick(void *xsc_if) 2208 { 2209 struct sk_if_softc *sc_if = xsc_if; 2210 struct mii_data *mii = &sc_if->sk_mii; 2211 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2212 int i; 2213 2214 DPRINTFN(3, ("sk_tick\n")); 2215 2216 if (!(ifp->if_flags & IFF_UP)) 2217 return; 2218 2219 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2220 sk_intr_bcom(sc_if); 2221 return; 2222 } 2223 2224 /* 2225 * According to SysKonnect, the correct way to verify that 2226 * the link has come back up is to poll bit 0 of the GPIO 2227 * register three times. This pin has the signal from the 2228 * link sync pin connected to it; if we read the same link 2229 * state 3 times in a row, we know the link is up. 2230 */ 2231 for (i = 0; i < 3; i++) { 2232 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2233 break; 2234 } 2235 2236 if (i != 3) { 2237 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2238 return; 2239 } 2240 2241 /* Turn the GP0 interrupt back on. */ 2242 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2243 SK_XM_READ_2(sc_if, XM_ISR); 2244 mii_tick(mii); 2245 if (ifp->if_link_state != LINK_STATE_UP) 2246 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2247 else 2248 callout_stop(&sc_if->sk_tick_ch); 2249 } 2250 2251 void 2252 sk_intr_bcom(struct sk_if_softc *sc_if) 2253 { 2254 struct mii_data *mii = &sc_if->sk_mii; 2255 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2256 uint16_t status; 2257 2258 2259 DPRINTFN(3, ("sk_intr_bcom\n")); 2260 2261 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB); 2262 2263 /* 2264 * Read the PHY interrupt register to make sure 2265 * we clear any pending interrupts. 2266 */ 2267 sk_xmac_miibus_readreg(sc_if->sk_dev, 2268 SK_PHYADDR_BCOM, BRGPHY_MII_ISR, &status); 2269 2270 if (!(ifp->if_flags & IFF_RUNNING)) { 2271 sk_init_xmac(sc_if); 2272 return; 2273 } 2274 2275 if (status & (BRGPHY_ISR_LNK_CHG | BRGPHY_ISR_AN_PR)) { 2276 uint16_t lstat; 2277 sk_xmac_miibus_readreg(sc_if->sk_dev, 2278 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS, &lstat); 2279 2280 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2281 (void)mii_mediachg(mii); 2282 /* Turn off the link LED. */ 2283 SK_IF_WRITE_1(sc_if, 0, 2284 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2285 sc_if->sk_link = 0; 2286 } else if (status & BRGPHY_ISR_LNK_CHG) { 2287 sk_xmac_miibus_writereg(sc_if->sk_dev, 2288 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2289 mii_tick(mii); 2290 sc_if->sk_link = 1; 2291 /* Turn on the link LED. */ 2292 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2293 SK_LINKLED_ON | SK_LINKLED_LINKSYNC_OFF | 2294 SK_LINKLED_BLINK_OFF); 2295 mii_pollstat(mii); 2296 } else { 2297 mii_tick(mii); 2298 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2299 } 2300 } 2301 2302 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB); 2303 } 2304 2305 void 2306 sk_intr_xmac(struct sk_if_softc *sc_if) 2307 { 2308 uint16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2309 2310 DPRINTFN(3, ("sk_intr_xmac\n")); 2311 2312 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2313 if (status & XM_ISR_GP0_SET) { 2314 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2315 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2316 } 2317 2318 if (status & XM_ISR_AUTONEG_DONE) { 2319 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2320 } 2321 } 2322 2323 if (status & XM_IMR_TX_UNDERRUN) 2324 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2325 2326 if (status & XM_IMR_RX_OVERRUN) 2327 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2328 } 2329 2330 void 2331 sk_intr_yukon(struct sk_if_softc *sc_if) 2332 { 2333 #ifdef SK_DEBUG 2334 int status; 2335 2336 status = 2337 #endif 2338 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2339 2340 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2341 } 2342 2343 int 2344 sk_intr(void *xsc) 2345 { 2346 struct sk_softc *sc = xsc; 2347 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2348 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2349 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2350 uint32_t status; 2351 int claimed = 0; 2352 2353 if (sc_if0 != NULL) 2354 ifp0 = &sc_if0->sk_ethercom.ec_if; 2355 if (sc_if1 != NULL) 2356 ifp1 = &sc_if1->sk_ethercom.ec_if; 2357 2358 for (;;) { 2359 status = CSR_READ_4(sc, SK_ISSR); 2360 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2361 2362 if (!(status & sc->sk_intrmask)) 2363 break; 2364 2365 claimed = 1; 2366 2367 /* Handle receive interrupts first. */ 2368 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2369 sk_rxeof(sc_if0); 2370 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2371 SK_RXBMU_CLR_IRQ_EOF | SK_RXBMU_RX_START); 2372 } 2373 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2374 sk_rxeof(sc_if1); 2375 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2376 SK_RXBMU_CLR_IRQ_EOF | SK_RXBMU_RX_START); 2377 } 2378 2379 /* Then transmit interrupts. */ 2380 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2381 sk_txeof(sc_if0); 2382 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2383 SK_TXBMU_CLR_IRQ_EOF); 2384 } 2385 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2386 sk_txeof(sc_if1); 2387 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2388 SK_TXBMU_CLR_IRQ_EOF); 2389 } 2390 2391 /* Then MAC interrupts. */ 2392 if (sc_if0 && (status & SK_ISR_MAC1) && 2393 (ifp0->if_flags & IFF_RUNNING)) { 2394 if (sc->sk_type == SK_GENESIS) 2395 sk_intr_xmac(sc_if0); 2396 else 2397 sk_intr_yukon(sc_if0); 2398 } 2399 2400 if (sc_if1 && (status & SK_ISR_MAC2) && 2401 (ifp1->if_flags & IFF_RUNNING)) { 2402 if (sc->sk_type == SK_GENESIS) 2403 sk_intr_xmac(sc_if1); 2404 else 2405 sk_intr_yukon(sc_if1); 2406 2407 } 2408 2409 if (status & SK_ISR_EXTERNAL_REG) { 2410 if (sc_if0 != NULL && 2411 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2412 sk_intr_bcom(sc_if0); 2413 2414 if (sc_if1 != NULL && 2415 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2416 sk_intr_bcom(sc_if1); 2417 } 2418 } 2419 2420 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2421 2422 if (ifp0 != NULL) 2423 if_schedule_deferred_start(ifp0); 2424 if (ifp1 != NULL) 2425 if_schedule_deferred_start(ifp1); 2426 2427 KASSERT(sc->rnd_attached > 0); 2428 rnd_add_uint32(&sc->rnd_source, status); 2429 2430 if (sc->sk_int_mod_pending) 2431 sk_update_int_mod(sc); 2432 2433 return claimed; 2434 } 2435 2436 void 2437 sk_unreset_xmac(struct sk_if_softc *sc_if) 2438 { 2439 struct sk_softc *sc = sc_if->sk_softc; 2440 static const struct sk_bcom_hack bhack[] = { 2441 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2442 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2443 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2444 { 0, 0 } }; 2445 2446 DPRINTFN(1, ("sk_unreset_xmac\n")); 2447 2448 /* Unreset the XMAC. */ 2449 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2450 DELAY(1000); 2451 2452 /* Reset the XMAC's internal state. */ 2453 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2454 2455 /* Save the XMAC II revision */ 2456 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2457 2458 /* 2459 * Perform additional initialization for external PHYs, 2460 * namely for the 1000baseTX cards that use the XMAC's 2461 * GMII mode. 2462 */ 2463 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2464 int i = 0; 2465 uint32_t val; 2466 uint16_t phyval; 2467 2468 /* Take PHY out of reset. */ 2469 val = sk_win_read_4(sc, SK_GPIO); 2470 if (sc_if->sk_port == SK_PORT_A) 2471 val |= SK_GPIO_DIR0 | SK_GPIO_DAT0; 2472 else 2473 val |= SK_GPIO_DIR2 | SK_GPIO_DAT2; 2474 sk_win_write_4(sc, SK_GPIO, val); 2475 2476 /* Enable GMII mode on the XMAC. */ 2477 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2478 2479 sk_xmac_miibus_writereg(sc_if->sk_dev, 2480 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2481 DELAY(10000); 2482 sk_xmac_miibus_writereg(sc_if->sk_dev, 2483 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2484 2485 /* 2486 * Early versions of the BCM5400 apparently have 2487 * a bug that requires them to have their reserved 2488 * registers initialized to some magic values. I don't 2489 * know what the numbers do, I'm just the messenger. 2490 */ 2491 sk_xmac_miibus_readreg(sc_if->sk_dev, 2492 SK_PHYADDR_BCOM, 0x03, &phyval); 2493 if (phyval == 0x6041) { 2494 while (bhack[i].reg) { 2495 sk_xmac_miibus_writereg(sc_if->sk_dev, 2496 SK_PHYADDR_BCOM, bhack[i].reg, 2497 bhack[i].val); 2498 i++; 2499 } 2500 } 2501 } 2502 } 2503 2504 void 2505 sk_init_xmac(struct sk_if_softc *sc_if) 2506 { 2507 struct sk_softc *sc = sc_if->sk_softc; 2508 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2509 2510 sk_unreset_xmac(sc_if); 2511 2512 /* Set station address */ 2513 SK_XM_WRITE_2(sc_if, XM_PAR0, 2514 *(uint16_t *)(&sc_if->sk_enaddr[0])); 2515 SK_XM_WRITE_2(sc_if, XM_PAR1, 2516 *(uint16_t *)(&sc_if->sk_enaddr[2])); 2517 SK_XM_WRITE_2(sc_if, XM_PAR2, 2518 *(uint16_t *)(&sc_if->sk_enaddr[4])); 2519 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2520 2521 if (ifp->if_flags & IFF_PROMISC) 2522 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2523 else 2524 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2525 2526 if (ifp->if_flags & IFF_BROADCAST) 2527 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2528 else 2529 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2530 2531 /* We don't need the FCS appended to the packet. */ 2532 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2533 2534 /* We want short frames padded to 60 bytes. */ 2535 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2536 2537 /* 2538 * Enable the reception of all error frames. This is is 2539 * a necessary evil due to the design of the XMAC. The 2540 * XMAC's receive FIFO is only 8K in size, however jumbo 2541 * frames can be up to 9000 bytes in length. When bad 2542 * frame filtering is enabled, the XMAC's RX FIFO operates 2543 * in 'store and forward' mode. For this to work, the 2544 * entire frame has to fit into the FIFO, but that means 2545 * that jumbo frames larger than 8192 bytes will be 2546 * truncated. Disabling all bad frame filtering causes 2547 * the RX FIFO to operate in streaming mode, in which 2548 * case the XMAC will start transfering frames out of the 2549 * RX FIFO as soon as the FIFO threshold is reached. 2550 */ 2551 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES | 2552 XM_MODE_RX_GIANTS | XM_MODE_RX_RUNTS | XM_MODE_RX_CRCERRS | 2553 XM_MODE_RX_INRANGELEN); 2554 2555 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2556 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2557 else 2558 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2559 2560 /* 2561 * Bump up the transmit threshold. This helps hold off transmit 2562 * underruns when we're blasting traffic from both ports at once. 2563 */ 2564 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2565 2566 /* Set multicast filter */ 2567 sk_setmulti(sc_if); 2568 2569 /* Clear and enable interrupts */ 2570 SK_XM_READ_2(sc_if, XM_ISR); 2571 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2572 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2573 else 2574 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2575 2576 /* Configure MAC arbiter */ 2577 switch (sc_if->sk_xmac_rev) { 2578 case XM_XMAC_REV_B2: 2579 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2580 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2581 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2582 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2583 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2584 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2585 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2586 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2587 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2588 break; 2589 case XM_XMAC_REV_C1: 2590 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2591 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2592 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2593 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2594 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2595 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2596 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2597 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2598 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2599 break; 2600 default: 2601 break; 2602 } 2603 sk_win_write_2(sc, SK_MACARB_CTL, 2604 SK_MACARBCTL_UNRESET | SK_MACARBCTL_FASTOE_OFF); 2605 2606 sc_if->sk_link = 1; 2607 } 2608 2609 void 2610 sk_unreset_yukon(struct sk_if_softc *sc_if) 2611 { 2612 uint32_t /*mac, */phy; 2613 struct sk_softc *sc; 2614 2615 DPRINTFN(1, ("sk_unreset_yukon: start: sk_csr=%#x\n", 2616 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2617 2618 sc = sc_if->sk_softc; 2619 if (sc->sk_type == SK_YUKON_LITE && 2620 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2621 /* Take PHY out of reset. */ 2622 sk_win_write_4(sc, SK_GPIO, 2623 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) 2624 & ~SK_GPIO_DAT9); 2625 } 2626 2627 /* GMAC and GPHY Reset */ 2628 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2629 2630 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2631 2632 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2633 DELAY(1000); 2634 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2635 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2636 DELAY(1000); 2637 2638 2639 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2640 2641 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2642 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2643 2644 switch (sc_if->sk_softc->sk_pmd) { 2645 case IFM_1000_SX: 2646 case IFM_1000_LX: 2647 phy |= SK_GPHY_FIBER; 2648 break; 2649 2650 case IFM_1000_CX: 2651 case IFM_1000_T: 2652 phy |= SK_GPHY_COPPER; 2653 break; 2654 } 2655 2656 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2657 2658 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2659 DELAY(1000); 2660 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2661 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2662 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2663 2664 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2665 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2666 } 2667 2668 void 2669 sk_init_yukon(struct sk_if_softc *sc_if) 2670 { 2671 uint16_t reg; 2672 int i; 2673 2674 DPRINTFN(1, ("sk_init_yukon: start\n")); 2675 sk_unreset_yukon(sc_if); 2676 2677 /* unused read of the interrupt source register */ 2678 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2679 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2680 2681 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2682 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2683 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2684 2685 /* MIB Counter Clear Mode set */ 2686 reg |= YU_PAR_MIB_CLR; 2687 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2688 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2689 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2690 2691 /* MIB Counter Clear Mode clear */ 2692 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2693 reg &= ~YU_PAR_MIB_CLR; 2694 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2695 2696 /* receive control reg */ 2697 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2698 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2699 YU_RCR_CRCR); 2700 2701 /* transmit parameter register */ 2702 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2703 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2704 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a)); 2705 2706 /* serial mode register */ 2707 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2708 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2709 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2710 YU_SMR_IPG_DATA(0x1e)); 2711 2712 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2713 /* Setup Yukon's address */ 2714 for (i = 0; i < 3; i++) { 2715 /* Write Source Address 1 (unicast filter) */ 2716 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2717 sc_if->sk_enaddr[i * 2] | 2718 sc_if->sk_enaddr[i * 2 + 1] << 8); 2719 } 2720 2721 for (i = 0; i < 3; i++) { 2722 reg = sk_win_read_2(sc_if->sk_softc, 2723 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2724 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2725 } 2726 2727 /* Set multicast filter */ 2728 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2729 sk_setmulti(sc_if); 2730 2731 /* enable interrupt mask for counter overflows */ 2732 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2733 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2734 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2735 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2736 2737 /* Configure RX MAC FIFO */ 2738 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2739 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2740 2741 /* Configure TX MAC FIFO */ 2742 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2743 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2744 2745 DPRINTFN(6, ("sk_init_yukon: end\n")); 2746 } 2747 2748 /* 2749 * Note that to properly initialize any part of the GEnesis chip, 2750 * you first have to take it out of reset mode. 2751 */ 2752 int 2753 sk_init(struct ifnet *ifp) 2754 { 2755 struct sk_if_softc *sc_if = ifp->if_softc; 2756 struct sk_softc *sc = sc_if->sk_softc; 2757 struct mii_data *mii = &sc_if->sk_mii; 2758 int rc = 0, s; 2759 uint32_t imr, imtimer_ticks; 2760 2761 DPRINTFN(1, ("sk_init\n")); 2762 2763 s = splnet(); 2764 2765 if (ifp->if_flags & IFF_RUNNING) { 2766 splx(s); 2767 return 0; 2768 } 2769 2770 /* Cancel pending I/O and free all RX/TX buffers. */ 2771 sk_stop(ifp, 0); 2772 2773 if (sc->sk_type == SK_GENESIS) { 2774 /* Configure LINK_SYNC LED */ 2775 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2776 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2777 SK_LINKLED_LINKSYNC_ON); 2778 2779 /* Configure RX LED */ 2780 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2781 SK_RXLEDCTL_COUNTER_START); 2782 2783 /* Configure TX LED */ 2784 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2785 SK_TXLEDCTL_COUNTER_START); 2786 } 2787 2788 /* Configure I2C registers */ 2789 2790 /* Configure XMAC(s) */ 2791 switch (sc->sk_type) { 2792 case SK_GENESIS: 2793 sk_init_xmac(sc_if); 2794 break; 2795 case SK_YUKON: 2796 case SK_YUKON_LITE: 2797 case SK_YUKON_LP: 2798 sk_init_yukon(sc_if); 2799 break; 2800 } 2801 if ((rc = mii_mediachg(mii)) == ENXIO) 2802 rc = 0; 2803 else if (rc != 0) 2804 goto out; 2805 2806 if (sc->sk_type == SK_GENESIS) { 2807 /* Configure MAC FIFOs */ 2808 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2809 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2810 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2811 2812 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2813 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2814 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2815 } 2816 2817 /* Configure transmit arbiter(s) */ 2818 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2819 SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON); 2820 2821 /* Configure RAMbuffers */ 2822 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2823 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2824 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2825 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2826 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2827 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2828 2829 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2830 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2831 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2832 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2833 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2834 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2835 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2836 2837 /* Configure BMUs */ 2838 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2839 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2840 SK_RX_RING_ADDR(sc_if, 0)); 2841 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2842 2843 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2844 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2845 SK_TX_RING_ADDR(sc_if, 0)); 2846 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2847 2848 /* Init descriptors */ 2849 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2850 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2851 "memory for rx buffers\n"); 2852 sk_stop(ifp, 0); 2853 splx(s); 2854 return ENOBUFS; 2855 } 2856 2857 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2858 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2859 "memory for tx buffers\n"); 2860 sk_stop(ifp, 0); 2861 splx(s); 2862 return ENOBUFS; 2863 } 2864 2865 /* Set interrupt moderation if changed via sysctl. */ 2866 switch (sc->sk_type) { 2867 case SK_GENESIS: 2868 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2869 break; 2870 case SK_YUKON_EC: 2871 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2872 break; 2873 default: 2874 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2875 } 2876 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2877 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2878 sk_win_write_4(sc, SK_IMTIMERINIT, 2879 SK_IM_USECS(sc->sk_int_mod)); 2880 aprint_verbose_dev(sc->sk_dev, 2881 "interrupt moderation is %d us\n", sc->sk_int_mod); 2882 } 2883 2884 /* Configure interrupt handling */ 2885 CSR_READ_4(sc, SK_ISSR); 2886 if (sc_if->sk_port == SK_PORT_A) 2887 sc->sk_intrmask |= SK_INTRS1; 2888 else 2889 sc->sk_intrmask |= SK_INTRS2; 2890 2891 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2892 2893 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2894 2895 /* Start BMUs. */ 2896 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2897 2898 if (sc->sk_type == SK_GENESIS) { 2899 /* Enable XMACs TX and RX state machines */ 2900 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2901 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2902 XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB); 2903 } 2904 2905 if (SK_YUKON_FAMILY(sc->sk_type)) { 2906 uint16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2907 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2908 #if 0 2909 /* XXX disable 100Mbps and full duplex mode? */ 2910 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN); 2911 #endif 2912 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2913 } 2914 2915 2916 ifp->if_flags |= IFF_RUNNING; 2917 ifp->if_flags &= ~IFF_OACTIVE; 2918 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2919 2920 out: 2921 splx(s); 2922 return rc; 2923 } 2924 2925 void 2926 sk_stop(struct ifnet *ifp, int disable) 2927 { 2928 struct sk_if_softc *sc_if = ifp->if_softc; 2929 struct sk_softc *sc = sc_if->sk_softc; 2930 int i; 2931 2932 DPRINTFN(1, ("sk_stop\n")); 2933 2934 callout_stop(&sc_if->sk_tick_ch); 2935 2936 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2937 uint32_t val; 2938 2939 /* Put PHY back into reset. */ 2940 val = sk_win_read_4(sc, SK_GPIO); 2941 if (sc_if->sk_port == SK_PORT_A) { 2942 val |= SK_GPIO_DIR0; 2943 val &= ~SK_GPIO_DAT0; 2944 } else { 2945 val |= SK_GPIO_DIR2; 2946 val &= ~SK_GPIO_DAT2; 2947 } 2948 sk_win_write_4(sc, SK_GPIO, val); 2949 } 2950 2951 /* Turn off various components of this interface. */ 2952 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2953 switch (sc->sk_type) { 2954 case SK_GENESIS: 2955 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2956 SK_TXMACCTL_XMAC_RESET); 2957 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2958 break; 2959 case SK_YUKON: 2960 case SK_YUKON_LITE: 2961 case SK_YUKON_LP: 2962 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2963 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2964 break; 2965 } 2966 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2967 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET |SK_RBCTL_OFF); 2968 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2969 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2970 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2971 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2972 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2973 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2974 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2975 2976 /* Disable interrupts */ 2977 if (sc_if->sk_port == SK_PORT_A) 2978 sc->sk_intrmask &= ~SK_INTRS1; 2979 else 2980 sc->sk_intrmask &= ~SK_INTRS2; 2981 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2982 2983 SK_XM_READ_2(sc_if, XM_ISR); 2984 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2985 2986 /* Free RX and TX mbufs still in the queues. */ 2987 for (i = 0; i < SK_RX_RING_CNT; i++) { 2988 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2989 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2990 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2991 } 2992 } 2993 2994 for (i = 0; i < SK_TX_RING_CNT; i++) { 2995 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2996 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2997 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2998 } 2999 } 3000 3001 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3002 } 3003 3004 /* Power Management Framework */ 3005 3006 static bool 3007 skc_suspend(device_t dv, const pmf_qual_t *qual) 3008 { 3009 struct sk_softc *sc = device_private(dv); 3010 3011 DPRINTFN(2, ("skc_suspend\n")); 3012 3013 /* Turn off the driver is loaded LED */ 3014 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 3015 3016 return true; 3017 } 3018 3019 static bool 3020 skc_resume(device_t dv, const pmf_qual_t *qual) 3021 { 3022 struct sk_softc *sc = device_private(dv); 3023 3024 DPRINTFN(2, ("skc_resume\n")); 3025 3026 sk_reset(sc); 3027 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 3028 3029 return true; 3030 } 3031 3032 static bool 3033 sk_resume(device_t dv, const pmf_qual_t *qual) 3034 { 3035 struct sk_if_softc *sc_if = device_private(dv); 3036 3037 sk_init_yukon(sc_if); 3038 return true; 3039 } 3040 3041 CFATTACH_DECL_NEW(skc, sizeof(struct sk_softc), 3042 skc_probe, skc_attach, NULL, NULL); 3043 3044 CFATTACH_DECL_NEW(sk, sizeof(struct sk_if_softc), 3045 sk_probe, sk_attach, NULL, NULL); 3046 3047 #ifdef SK_DEBUG 3048 void 3049 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 3050 { 3051 #define DESC_PRINT(X) \ 3052 if (X) \ 3053 printf("txdesc[%d]." #X "=%#x\n", \ 3054 idx, X); 3055 3056 DESC_PRINT(le32toh(desc->sk_ctl)); 3057 DESC_PRINT(le32toh(desc->sk_next)); 3058 DESC_PRINT(le32toh(desc->sk_data_lo)); 3059 DESC_PRINT(le32toh(desc->sk_data_hi)); 3060 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 3061 DESC_PRINT(le16toh(desc->sk_rsvd0)); 3062 DESC_PRINT(le16toh(desc->sk_csum_startval)); 3063 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 3064 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 3065 DESC_PRINT(le16toh(desc->sk_rsvd1)); 3066 #undef PRINT 3067 } 3068 3069 void 3070 sk_dump_bytes(const char *data, int len) 3071 { 3072 int c, i, j; 3073 3074 for (i = 0; i < len; i += 16) { 3075 printf("%08x ", i); 3076 c = len - i; 3077 if (c > 16) c = 16; 3078 3079 for (j = 0; j < c; j++) { 3080 printf("%02x ", data[i + j] & 0xff); 3081 if ((j & 0xf) == 7 && j > 0) 3082 printf(" "); 3083 } 3084 3085 for (; j < 16; j++) 3086 printf(" "); 3087 printf(" "); 3088 3089 for (j = 0; j < c; j++) { 3090 int ch = data[i + j] & 0xff; 3091 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 3092 } 3093 3094 printf("\n"); 3095 3096 if (c < 16) 3097 break; 3098 } 3099 } 3100 3101 void 3102 sk_dump_mbuf(struct mbuf *m) 3103 { 3104 int count = m->m_pkthdr.len; 3105 3106 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3107 3108 while (count > 0 && m) { 3109 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3110 m, m->m_data, m->m_len); 3111 sk_dump_bytes(mtod(m, char *), m->m_len); 3112 3113 count -= m->m_len; 3114 m = m->m_next; 3115 } 3116 } 3117 #endif 3118 3119 static int 3120 sk_sysctl_handler(SYSCTLFN_ARGS) 3121 { 3122 int error, t; 3123 struct sysctlnode node; 3124 struct sk_softc *sc; 3125 3126 node = *rnode; 3127 sc = node.sysctl_data; 3128 t = sc->sk_int_mod; 3129 node.sysctl_data = &t; 3130 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3131 if (error || newp == NULL) 3132 return error; 3133 3134 if (t < SK_IM_MIN || t > SK_IM_MAX) 3135 return EINVAL; 3136 3137 /* update the softc with sysctl-changed value, and mark 3138 for hardware update */ 3139 sc->sk_int_mod = t; 3140 sc->sk_int_mod_pending = 1; 3141 return 0; 3142 } 3143 3144 /* 3145 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3146 * set up in skc_attach() 3147 */ 3148 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3149 { 3150 int rc; 3151 const struct sysctlnode *node; 3152 3153 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3154 0, CTLTYPE_NODE, "sk", 3155 SYSCTL_DESCR("sk interface controls"), 3156 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3157 goto err; 3158 } 3159 3160 sk_root_num = node->sysctl_num; 3161 return; 3162 3163 err: 3164 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3165 } 3166
Indexes created Tue Sep 23 07:09:52 GMT 2025