if_sk.c revision 1.101
1 /* $NetBSD: if_sk.c,v 1.101 2019/11/10 21:16:36 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 30 31 /* 32 * Copyright (c) 1997, 1998, 1999, 2000 33 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by Bill Paul. 46 * 4. Neither the name of the author nor the names of any co-contributors 47 * may be used to endorse or promote products derived from this software 48 * without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 51 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 53 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 60 * THE POSSIBILITY OF SUCH DAMAGE. 61 * 62 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 63 */ 64 65 /* 66 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 67 * 68 * Permission to use, copy, modify, and distribute this software for any 69 * purpose with or without fee is hereby granted, provided that the above 70 * copyright notice and this permission notice appear in all copies. 71 * 72 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 73 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 74 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 75 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 76 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 77 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 78 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 79 */ 80 81 /* 82 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 83 * the SK-984x series adapters, both single port and dual port. 84 * References: 85 * The XaQti XMAC II datasheet, 86 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 87 * The SysKonnect GEnesis manual, http://www.syskonnect.com 88 * 89 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 90 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 91 * convenience to others until Vitesse corrects this problem: 92 * 93 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * 95 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 96 * Department of Electrical Engineering 97 * Columbia University, New York City 98 */ 99 100 /* 101 * The SysKonnect gigabit ethernet adapters consist of two main 102 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 103 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 104 * components and a PHY while the GEnesis controller provides a PCI 105 * interface with DMA support. Each card may have between 512K and 106 * 2MB of SRAM on board depending on the configuration. 107 * 108 * The SysKonnect GEnesis controller can have either one or two XMAC 109 * chips connected to it, allowing single or dual port NIC configurations. 110 * SysKonnect has the distinction of being the only vendor on the market 111 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 112 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 113 * XMAC registers. This driver takes advantage of these features to allow 114 * both XMACs to operate as independent interfaces. 115 */ 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: if_sk.c,v 1.101 2019/11/10 21:16:36 chs Exp $"); 119 120 #include <sys/param.h> 121 #include <sys/systm.h> 122 #include <sys/sockio.h> 123 #include <sys/mbuf.h> 124 #include <sys/malloc.h> 125 #include <sys/mutex.h> 126 #include <sys/kernel.h> 127 #include <sys/socket.h> 128 #include <sys/device.h> 129 #include <sys/queue.h> 130 #include <sys/callout.h> 131 #include <sys/sysctl.h> 132 #include <sys/endian.h> 133 134 #include <net/if.h> 135 #include <net/if_dl.h> 136 #include <net/if_types.h> 137 138 #include <net/if_media.h> 139 140 #include <net/bpf.h> 141 #include <sys/rndsource.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 #include <dev/mii/brgphyreg.h> 146 147 #include <dev/pci/pcireg.h> 148 #include <dev/pci/pcivar.h> 149 #include <dev/pci/pcidevs.h> 150 151 /* #define SK_USEIOSPACE */ 152 153 #include <dev/pci/if_skreg.h> 154 #include <dev/pci/if_skvar.h> 155 156 int skc_probe(device_t, cfdata_t, void *); 157 void skc_attach(device_t, device_t, void *); 158 int sk_probe(device_t, cfdata_t, void *); 159 void sk_attach(device_t, device_t, void *); 160 int skcprint(void *, const char *); 161 int sk_intr(void *); 162 void sk_intr_bcom(struct sk_if_softc *); 163 void sk_intr_xmac(struct sk_if_softc *); 164 void sk_intr_yukon(struct sk_if_softc *); 165 void sk_rxeof(struct sk_if_softc *); 166 void sk_txeof(struct sk_if_softc *); 167 int sk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *); 168 void sk_start(struct ifnet *); 169 int sk_ioctl(struct ifnet *, u_long, void *); 170 int sk_init(struct ifnet *); 171 void sk_unreset_xmac(struct sk_if_softc *); 172 void sk_init_xmac(struct sk_if_softc *); 173 void sk_unreset_yukon(struct sk_if_softc *); 174 void sk_init_yukon(struct sk_if_softc *); 175 void sk_stop(struct ifnet *, int); 176 void sk_watchdog(struct ifnet *); 177 void sk_shutdown(void *); 178 int sk_ifmedia_upd(struct ifnet *); 179 void sk_reset(struct sk_softc *); 180 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 181 int sk_alloc_jumbo_mem(struct sk_if_softc *); 182 void sk_free_jumbo_mem(struct sk_if_softc *); 183 void *sk_jalloc(struct sk_if_softc *); 184 void sk_jfree(struct mbuf *, void *, size_t, void *); 185 int sk_init_rx_ring(struct sk_if_softc *); 186 int sk_init_tx_ring(struct sk_if_softc *); 187 uint8_t sk_vpd_readbyte(struct sk_softc *, int); 188 void sk_vpd_read_res(struct sk_softc *, 189 struct vpd_res *, int); 190 void sk_vpd_read(struct sk_softc *); 191 192 void sk_update_int_mod(struct sk_softc *); 193 194 int sk_xmac_miibus_readreg(device_t, int, int, uint16_t *); 195 int sk_xmac_miibus_writereg(device_t, int, int, uint16_t); 196 void sk_xmac_miibus_statchg(struct ifnet *); 197 198 int sk_marv_miibus_readreg(device_t, int, int, uint16_t *); 199 int sk_marv_miibus_writereg(device_t, int, int, uint16_t); 200 void sk_marv_miibus_statchg(struct ifnet *); 201 202 uint32_t sk_xmac_hash(void *); 203 uint32_t sk_yukon_hash(void *); 204 void sk_setfilt(struct sk_if_softc *, void *, int); 205 void sk_setmulti(struct sk_if_softc *); 206 void sk_tick(void *); 207 208 static bool skc_suspend(device_t, const pmf_qual_t *); 209 static bool skc_resume(device_t, const pmf_qual_t *); 210 static bool sk_resume(device_t dv, const pmf_qual_t *); 211 212 /* #define SK_DEBUG 2 */ 213 #ifdef SK_DEBUG 214 #define DPRINTF(x) if (skdebug) printf x 215 #define DPRINTFN(n, x) if (skdebug >= (n)) printf x 216 int skdebug = SK_DEBUG; 217 218 void sk_dump_txdesc(struct sk_tx_desc *, int); 219 void sk_dump_mbuf(struct mbuf *); 220 void sk_dump_bytes(const char *, int); 221 #else 222 #define DPRINTF(x) 223 #define DPRINTFN(n, x) 224 #endif 225 226 static int sk_sysctl_handler(SYSCTLFN_PROTO); 227 static int sk_root_num; 228 229 /* supported device vendors */ 230 /* PCI_PRODUCT_DLINK_DGE560T_2 might belong in if_msk instead */ 231 static const struct sk_product { 232 pci_vendor_id_t sk_vendor; 233 pci_product_id_t sk_product; 234 } sk_products[] = { 235 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 236 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 237 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 238 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 239 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 240 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 241 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 242 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 243 { 0, 0, } 244 }; 245 246 #define SK_LINKSYS_EG1032_SUBID 0x00151737 247 248 static inline uint32_t 249 sk_win_read_4(struct sk_softc *sc, uint32_t reg) 250 { 251 #ifdef SK_USEIOSPACE 252 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 253 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 254 #else 255 return CSR_READ_4(sc, reg); 256 #endif 257 } 258 259 static inline uint16_t 260 sk_win_read_2(struct sk_softc *sc, uint32_t reg) 261 { 262 #ifdef SK_USEIOSPACE 263 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 264 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 265 #else 266 return CSR_READ_2(sc, reg); 267 #endif 268 } 269 270 static inline uint8_t 271 sk_win_read_1(struct sk_softc *sc, uint32_t reg) 272 { 273 #ifdef SK_USEIOSPACE 274 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 275 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 276 #else 277 return CSR_READ_1(sc, reg); 278 #endif 279 } 280 281 static inline void 282 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x) 283 { 284 #ifdef SK_USEIOSPACE 285 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 286 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 287 #else 288 CSR_WRITE_4(sc, reg, x); 289 #endif 290 } 291 292 static inline void 293 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x) 294 { 295 #ifdef SK_USEIOSPACE 296 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 297 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 298 #else 299 CSR_WRITE_2(sc, reg, x); 300 #endif 301 } 302 303 static inline void 304 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x) 305 { 306 #ifdef SK_USEIOSPACE 307 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 308 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 309 #else 310 CSR_WRITE_1(sc, reg, x); 311 #endif 312 } 313 314 /* 315 * The VPD EEPROM contains Vital Product Data, as suggested in 316 * the PCI 2.1 specification. The VPD data is separared into areas 317 * denoted by resource IDs. The SysKonnect VPD contains an ID string 318 * resource (the name of the adapter), a read-only area resource 319 * containing various key/data fields and a read/write area which 320 * can be used to store asset management information or log messages. 321 * We read the ID string and read-only into buffers attached to 322 * the controller softc structure for later use. At the moment, 323 * we only use the ID string during sk_attach(). 324 */ 325 uint8_t 326 sk_vpd_readbyte(struct sk_softc *sc, int addr) 327 { 328 int i; 329 330 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 331 for (i = 0; i < SK_TIMEOUT; i++) { 332 DELAY(1); 333 if (sk_win_read_2(sc, 334 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 335 break; 336 } 337 338 if (i == SK_TIMEOUT) 339 return 0; 340 341 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 342 } 343 344 void 345 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 346 { 347 int i; 348 uint8_t *ptr; 349 350 ptr = (uint8_t *)res; 351 for (i = 0; i < sizeof(struct vpd_res); i++) 352 ptr[i] = sk_vpd_readbyte(sc, i + addr); 353 } 354 355 void 356 sk_vpd_read(struct sk_softc *sc) 357 { 358 int pos = 0, i; 359 struct vpd_res res; 360 361 if (sc->sk_vpd_prodname != NULL) 362 free(sc->sk_vpd_prodname, M_DEVBUF); 363 if (sc->sk_vpd_readonly != NULL) 364 free(sc->sk_vpd_readonly, M_DEVBUF); 365 sc->sk_vpd_prodname = NULL; 366 sc->sk_vpd_readonly = NULL; 367 368 sk_vpd_read_res(sc, &res, pos); 369 370 if (res.vr_id != VPD_RES_ID) { 371 aprint_error_dev(sc->sk_dev, 372 "bad VPD resource id: expected %x got %x\n", 373 VPD_RES_ID, res.vr_id); 374 return; 375 } 376 377 pos += sizeof(res); 378 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_WAITOK); 379 for (i = 0; i < res.vr_len; i++) 380 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 381 sc->sk_vpd_prodname[i] = '\0'; 382 pos += i; 383 384 sk_vpd_read_res(sc, &res, pos); 385 386 if (res.vr_id != VPD_RES_READ) { 387 aprint_error_dev(sc->sk_dev, 388 "bad VPD resource id: expected %x got %x\n", 389 VPD_RES_READ, res.vr_id); 390 return; 391 } 392 393 pos += sizeof(res); 394 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_WAITOK); 395 for (i = 0; i < res.vr_len ; i++) 396 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 397 } 398 399 int 400 sk_xmac_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 401 { 402 struct sk_if_softc *sc_if = device_private(dev); 403 int i; 404 405 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 406 407 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 408 return -1; 409 410 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 411 SK_XM_READ_2(sc_if, XM_PHY_DATA); 412 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 413 for (i = 0; i < SK_TIMEOUT; i++) { 414 DELAY(1); 415 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 416 XM_MMUCMD_PHYDATARDY) 417 break; 418 } 419 420 if (i == SK_TIMEOUT) { 421 aprint_error_dev(sc_if->sk_dev, 422 "phy failed to come ready\n"); 423 return ETIMEDOUT; 424 } 425 } 426 DELAY(1); 427 *val = SK_XM_READ_2(sc_if, XM_PHY_DATA); 428 return 0; 429 } 430 431 int 432 sk_xmac_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 433 { 434 struct sk_if_softc *sc_if = device_private(dev); 435 int i; 436 437 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 438 439 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 440 for (i = 0; i < SK_TIMEOUT; i++) { 441 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 442 break; 443 } 444 445 if (i == SK_TIMEOUT) { 446 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 447 return ETIMEDOUT; 448 } 449 450 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 451 for (i = 0; i < SK_TIMEOUT; i++) { 452 DELAY(1); 453 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 454 break; 455 } 456 457 if (i == SK_TIMEOUT) { 458 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 459 return ETIMEDOUT; 460 } 461 462 return 0; 463 } 464 465 void 466 sk_xmac_miibus_statchg(struct ifnet *ifp) 467 { 468 struct sk_if_softc *sc_if = ifp->if_softc; 469 struct mii_data *mii = &sc_if->sk_mii; 470 471 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 472 473 /* 474 * If this is a GMII PHY, manually set the XMAC's 475 * duplex mode accordingly. 476 */ 477 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 478 if ((mii->mii_media_active & IFM_FDX) != 0) 479 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 480 else 481 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 482 } 483 } 484 485 int 486 sk_marv_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 487 { 488 struct sk_if_softc *sc_if = device_private(dev); 489 uint16_t data; 490 int i; 491 492 if (phy != 0 || 493 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 494 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 495 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 496 phy, reg)); 497 return -1; 498 } 499 500 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 501 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 502 503 for (i = 0; i < SK_TIMEOUT; i++) { 504 DELAY(1); 505 data = SK_YU_READ_2(sc_if, YUKON_SMICR); 506 if (data & YU_SMICR_READ_VALID) 507 break; 508 } 509 510 if (i == SK_TIMEOUT) { 511 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 512 return ETIMEDOUT; 513 } 514 515 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 516 SK_TIMEOUT)); 517 518 *val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 519 520 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#hx\n", 521 phy, reg, *val)); 522 523 return 0; 524 } 525 526 int 527 sk_marv_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 528 { 529 struct sk_if_softc *sc_if = device_private(dev); 530 int i; 531 532 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#hx\n", 533 phy, reg, val)); 534 535 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 536 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 537 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 538 539 for (i = 0; i < SK_TIMEOUT; i++) { 540 DELAY(1); 541 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 542 break; 543 } 544 545 if (i == SK_TIMEOUT) { 546 printf("%s: phy write timed out\n", 547 device_xname(sc_if->sk_dev)); 548 return ETIMEDOUT; 549 } 550 551 return 0; 552 } 553 554 void 555 sk_marv_miibus_statchg(struct ifnet *ifp) 556 { 557 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 558 SK_YU_READ_2(((struct sk_if_softc *)ifp->if_softc), 559 YUKON_GPCR))); 560 } 561 562 uint32_t 563 sk_xmac_hash(void *addr) 564 { 565 uint32_t crc; 566 567 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 568 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 569 DPRINTFN(2,("multicast hash for %s is %x\n", ether_sprintf(addr),crc)); 570 return crc; 571 } 572 573 uint32_t 574 sk_yukon_hash(void *addr) 575 { 576 uint32_t crc; 577 578 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 579 crc &= ((1 << SK_HASH_BITS) - 1); 580 DPRINTFN(2,("multicast hash for %s is %x\n", ether_sprintf(addr),crc)); 581 return crc; 582 } 583 584 void 585 sk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 586 { 587 char *addr = addrv; 588 int base = XM_RXFILT_ENTRY(slot); 589 590 SK_XM_WRITE_2(sc_if, base, *(uint16_t *)(&addr[0])); 591 SK_XM_WRITE_2(sc_if, base + 2, *(uint16_t *)(&addr[2])); 592 SK_XM_WRITE_2(sc_if, base + 4, *(uint16_t *)(&addr[4])); 593 } 594 595 void 596 sk_setmulti(struct sk_if_softc *sc_if) 597 { 598 struct sk_softc *sc = sc_if->sk_softc; 599 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 600 uint32_t hashes[2] = { 0, 0 }; 601 int h = 0, i; 602 struct ethercom *ec = &sc_if->sk_ethercom; 603 struct ether_multi *enm; 604 struct ether_multistep step; 605 uint8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 606 607 /* First, zot all the existing filters. */ 608 switch (sc->sk_type) { 609 case SK_GENESIS: 610 for (i = 1; i < XM_RXFILT_MAX; i++) 611 sk_setfilt(sc_if, (void *)&dummy, i); 612 613 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 614 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 615 break; 616 case SK_YUKON: 617 case SK_YUKON_LITE: 618 case SK_YUKON_LP: 619 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 620 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 621 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 622 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 623 break; 624 } 625 626 /* Now program new ones. */ 627 allmulti: 628 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 629 hashes[0] = 0xFFFFFFFF; 630 hashes[1] = 0xFFFFFFFF; 631 } else { 632 i = 1; 633 /* First find the tail of the list. */ 634 ETHER_LOCK(ec); 635 ETHER_FIRST_MULTI(step, ec, enm); 636 while (enm != NULL) { 637 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 638 ETHER_ADDR_LEN)) { 639 ifp->if_flags |= IFF_ALLMULTI; 640 ETHER_UNLOCK(ec); 641 goto allmulti; 642 } 643 DPRINTFN(2,("multicast address %s\n", 644 ether_sprintf(enm->enm_addrlo))); 645 /* 646 * Program the first XM_RXFILT_MAX multicast groups 647 * into the perfect filter. For all others, 648 * use the hash table. 649 */ 650 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 651 sk_setfilt(sc_if, enm->enm_addrlo, i); 652 i++; 653 } 654 else { 655 switch (sc->sk_type) { 656 case SK_GENESIS: 657 h = sk_xmac_hash(enm->enm_addrlo); 658 break; 659 case SK_YUKON: 660 case SK_YUKON_LITE: 661 case SK_YUKON_LP: 662 h = sk_yukon_hash(enm->enm_addrlo); 663 break; 664 } 665 if (h < 32) 666 hashes[0] |= (1 << h); 667 else 668 hashes[1] |= (1 << (h - 32)); 669 } 670 671 ETHER_NEXT_MULTI(step, enm); 672 } 673 ETHER_UNLOCK(ec); 674 } 675 676 switch (sc->sk_type) { 677 case SK_GENESIS: 678 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH | 679 XM_MODE_RX_USE_PERFECT); 680 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 681 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 682 break; 683 case SK_YUKON: 684 case SK_YUKON_LITE: 685 case SK_YUKON_LP: 686 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 687 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 688 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 689 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 690 break; 691 } 692 } 693 694 int 695 sk_init_rx_ring(struct sk_if_softc *sc_if) 696 { 697 struct sk_chain_data *cd = &sc_if->sk_cdata; 698 struct sk_ring_data *rd = sc_if->sk_rdata; 699 int i; 700 701 memset((char *)rd->sk_rx_ring, 0, 702 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 703 704 for (i = 0; i < SK_RX_RING_CNT; i++) { 705 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 706 if (i == (SK_RX_RING_CNT - 1)) { 707 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 708 rd->sk_rx_ring[i].sk_next = 709 htole32(SK_RX_RING_ADDR(sc_if, 0)); 710 } else { 711 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 712 rd->sk_rx_ring[i].sk_next = 713 htole32(SK_RX_RING_ADDR(sc_if, i+1)); 714 } 715 } 716 717 for (i = 0; i < SK_RX_RING_CNT; i++) { 718 if (sk_newbuf(sc_if, i, NULL, 719 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 720 aprint_error_dev(sc_if->sk_dev, 721 "failed alloc of %dth mbuf\n", i); 722 return ENOBUFS; 723 } 724 } 725 sc_if->sk_cdata.sk_rx_prod = 0; 726 sc_if->sk_cdata.sk_rx_cons = 0; 727 728 return 0; 729 } 730 731 int 732 sk_init_tx_ring(struct sk_if_softc *sc_if) 733 { 734 struct sk_chain_data *cd = &sc_if->sk_cdata; 735 struct sk_ring_data *rd = sc_if->sk_rdata; 736 int i; 737 738 memset(sc_if->sk_rdata->sk_tx_ring, 0, 739 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 740 741 for (i = 0; i < SK_TX_RING_CNT; i++) { 742 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 743 if (i == (SK_TX_RING_CNT - 1)) { 744 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 745 rd->sk_tx_ring[i].sk_next = 746 htole32(SK_TX_RING_ADDR(sc_if, 0)); 747 } else { 748 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 749 rd->sk_tx_ring[i].sk_next = 750 htole32(SK_TX_RING_ADDR(sc_if, i+1)); 751 } 752 } 753 754 sc_if->sk_cdata.sk_tx_prod = 0; 755 sc_if->sk_cdata.sk_tx_cons = 0; 756 sc_if->sk_cdata.sk_tx_cnt = 0; 757 758 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 759 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 760 761 return 0; 762 } 763 764 int 765 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 766 bus_dmamap_t dmamap) 767 { 768 struct mbuf *m_new = NULL; 769 struct sk_chain *c; 770 struct sk_rx_desc *r; 771 772 if (m == NULL) { 773 void *buf = NULL; 774 775 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 776 if (m_new == NULL) { 777 aprint_error_dev(sc_if->sk_dev, 778 "no memory for rx list -- packet dropped!\n"); 779 return ENOBUFS; 780 } 781 782 /* Allocate the jumbo buffer */ 783 buf = sk_jalloc(sc_if); 784 if (buf == NULL) { 785 m_freem(m_new); 786 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 787 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 788 return ENOBUFS; 789 } 790 791 /* Attach the buffer to the mbuf */ 792 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 793 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 794 795 } else { 796 /* 797 * We're re-using a previously allocated mbuf; 798 * be sure to re-init pointers and lengths to 799 * default values. 800 */ 801 m_new = m; 802 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 803 m_new->m_data = m_new->m_ext.ext_buf; 804 } 805 m_adj(m_new, ETHER_ALIGN); 806 807 c = &sc_if->sk_cdata.sk_rx_chain[i]; 808 r = c->sk_desc; 809 c->sk_mbuf = m_new; 810 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 811 (((vaddr_t)m_new->m_data 812 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 813 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 814 815 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 816 817 return 0; 818 } 819 820 /* 821 * Memory management for jumbo frames. 822 */ 823 824 int 825 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 826 { 827 struct sk_softc *sc = sc_if->sk_softc; 828 char *ptr, *kva; 829 bus_dma_segment_t seg; 830 int i, rseg, state, error; 831 struct sk_jpool_entry *entry; 832 833 state = error = 0; 834 835 /* Grab a big chunk o' storage. */ 836 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 837 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 838 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 839 return ENOBUFS; 840 } 841 842 state = 1; 843 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, (void **)&kva, 844 BUS_DMA_NOWAIT)) { 845 aprint_error_dev(sc->sk_dev, 846 "can't map dma buffers (%d bytes)\n", 847 SK_JMEM); 848 error = ENOBUFS; 849 goto out; 850 } 851 852 state = 2; 853 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 854 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 855 aprint_error_dev(sc->sk_dev, "can't create dma map\n"); 856 error = ENOBUFS; 857 goto out; 858 } 859 860 state = 3; 861 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 862 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 863 aprint_error_dev(sc->sk_dev, "can't load dma map\n"); 864 error = ENOBUFS; 865 goto out; 866 } 867 868 state = 4; 869 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 870 DPRINTFN(1,("sk_jumbo_buf = 0x%p\n", sc_if->sk_cdata.sk_jumbo_buf)); 871 872 LIST_INIT(&sc_if->sk_jfree_listhead); 873 LIST_INIT(&sc_if->sk_jinuse_listhead); 874 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 875 876 /* 877 * Now divide it up into 9K pieces and save the addresses 878 * in an array. 879 */ 880 ptr = sc_if->sk_cdata.sk_jumbo_buf; 881 for (i = 0; i < SK_JSLOTS; i++) { 882 sc_if->sk_cdata.sk_jslots[i] = ptr; 883 ptr += SK_JLEN; 884 entry = malloc(sizeof(struct sk_jpool_entry), 885 M_DEVBUF, M_WAITOK); 886 entry->slot = i; 887 if (i) 888 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 889 entry, jpool_entries); 890 else 891 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 892 entry, jpool_entries); 893 } 894 out: 895 if (error != 0) { 896 switch (state) { 897 case 4: 898 bus_dmamap_unload(sc->sc_dmatag, 899 sc_if->sk_cdata.sk_rx_jumbo_map); 900 /* FALLTHROUGH */ 901 case 3: 902 bus_dmamap_destroy(sc->sc_dmatag, 903 sc_if->sk_cdata.sk_rx_jumbo_map); 904 /* FALLTHROUGH */ 905 case 2: 906 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 907 /* FALLTHROUGH */ 908 case 1: 909 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 910 break; 911 default: 912 break; 913 } 914 } 915 916 return error; 917 } 918 919 /* 920 * Allocate a jumbo buffer. 921 */ 922 void * 923 sk_jalloc(struct sk_if_softc *sc_if) 924 { 925 struct sk_jpool_entry *entry; 926 927 mutex_enter(&sc_if->sk_jpool_mtx); 928 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 929 930 if (entry == NULL) { 931 mutex_exit(&sc_if->sk_jpool_mtx); 932 return NULL; 933 } 934 935 LIST_REMOVE(entry, jpool_entries); 936 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 937 mutex_exit(&sc_if->sk_jpool_mtx); 938 return sc_if->sk_cdata.sk_jslots[entry->slot]; 939 } 940 941 /* 942 * Release a jumbo buffer. 943 */ 944 void 945 sk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 946 { 947 struct sk_jpool_entry *entry; 948 struct sk_if_softc *sc; 949 int i; 950 951 /* Extract the softc struct pointer. */ 952 sc = (struct sk_if_softc *)arg; 953 954 if (sc == NULL) 955 panic("sk_jfree: can't find softc pointer!"); 956 957 /* calculate the slot this buffer belongs to */ 958 959 i = ((vaddr_t)buf 960 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 961 962 if ((i < 0) || (i >= SK_JSLOTS)) 963 panic("sk_jfree: asked to free buffer that we don't manage!"); 964 965 mutex_enter(&sc->sk_jpool_mtx); 966 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 967 if (entry == NULL) 968 panic("sk_jfree: buffer not in use!"); 969 entry->slot = i; 970 LIST_REMOVE(entry, jpool_entries); 971 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 972 mutex_exit(&sc->sk_jpool_mtx); 973 974 if (__predict_true(m != NULL)) 975 pool_cache_put(mb_cache, m); 976 } 977 978 /* 979 * Set media options. 980 */ 981 int 982 sk_ifmedia_upd(struct ifnet *ifp) 983 { 984 struct sk_if_softc *sc_if = ifp->if_softc; 985 int rc; 986 987 (void) sk_init(ifp); 988 if ((rc = mii_mediachg(&sc_if->sk_mii)) == ENXIO) 989 return 0; 990 return rc; 991 } 992 993 static void 994 sk_promisc(struct sk_if_softc *sc_if, int on) 995 { 996 struct sk_softc *sc = sc_if->sk_softc; 997 switch (sc->sk_type) { 998 case SK_GENESIS: 999 if (on) 1000 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1001 else 1002 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1003 break; 1004 case SK_YUKON: 1005 case SK_YUKON_LITE: 1006 case SK_YUKON_LP: 1007 if (on) 1008 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1009 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1010 else 1011 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1012 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1013 break; 1014 default: 1015 aprint_error_dev(sc_if->sk_dev, "Can't set promisc for %d\n", 1016 sc->sk_type); 1017 break; 1018 } 1019 } 1020 1021 int 1022 sk_ioctl(struct ifnet *ifp, u_long command, void *data) 1023 { 1024 struct sk_if_softc *sc_if = ifp->if_softc; 1025 int s, error = 0; 1026 1027 /* DPRINTFN(2, ("sk_ioctl\n")); */ 1028 1029 s = splnet(); 1030 1031 switch (command) { 1032 1033 case SIOCSIFFLAGS: 1034 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1035 if ((error = ifioctl_common(ifp, command, data)) != 0) 1036 break; 1037 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 1038 case IFF_RUNNING: 1039 sk_stop(ifp, 1); 1040 break; 1041 case IFF_UP: 1042 sk_init(ifp); 1043 break; 1044 case IFF_UP | IFF_RUNNING: 1045 if ((ifp->if_flags ^ sc_if->sk_if_flags) == IFF_PROMISC) { 1046 sk_promisc(sc_if, ifp->if_flags & IFF_PROMISC); 1047 sk_setmulti(sc_if); 1048 } else 1049 sk_init(ifp); 1050 break; 1051 } 1052 sc_if->sk_if_flags = ifp->if_flags; 1053 error = 0; 1054 break; 1055 1056 default: 1057 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1058 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1059 break; 1060 1061 error = 0; 1062 1063 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1064 ; 1065 else if (ifp->if_flags & IFF_RUNNING) { 1066 sk_setmulti(sc_if); 1067 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1068 } 1069 break; 1070 } 1071 1072 splx(s); 1073 return error; 1074 } 1075 1076 void 1077 sk_update_int_mod(struct sk_softc *sc) 1078 { 1079 uint32_t imtimer_ticks; 1080 1081 /* 1082 * Configure interrupt moderation. The moderation timer 1083 * defers interrupts specified in the interrupt moderation 1084 * timer mask based on the timeout specified in the interrupt 1085 * moderation timer init register. Each bit in the timer 1086 * register represents one tick, so to specify a timeout in 1087 * microseconds, we have to multiply by the correct number of 1088 * ticks-per-microsecond. 1089 */ 1090 switch (sc->sk_type) { 1091 case SK_GENESIS: 1092 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1093 break; 1094 case SK_YUKON_EC: 1095 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1096 break; 1097 default: 1098 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1099 } 1100 aprint_verbose_dev(sc->sk_dev, "interrupt moderation is %d us\n", 1101 sc->sk_int_mod); 1102 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1103 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF | SK_ISR_TX2_S_EOF | 1104 SK_ISR_RX1_EOF | SK_ISR_RX2_EOF); 1105 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1106 sc->sk_int_mod_pending = 0; 1107 } 1108 1109 /* 1110 * Lookup: Check the PCI vendor and device, and return a pointer to 1111 * The structure if the IDs match against our list. 1112 */ 1113 1114 static const struct sk_product * 1115 sk_lookup(const struct pci_attach_args *pa) 1116 { 1117 const struct sk_product *psk; 1118 1119 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1120 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1121 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1122 return psk; 1123 } 1124 return NULL; 1125 } 1126 1127 /* 1128 * Probe for a SysKonnect GEnesis chip. 1129 */ 1130 1131 int 1132 skc_probe(device_t parent, cfdata_t match, void *aux) 1133 { 1134 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1135 const struct sk_product *psk; 1136 pcireg_t subid; 1137 1138 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1139 1140 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1141 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1142 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1143 subid == SK_LINKSYS_EG1032_SUBID) 1144 return 1; 1145 1146 if ((psk = sk_lookup(pa))) { 1147 return 1; 1148 } 1149 return 0; 1150 } 1151 1152 /* 1153 * Force the GEnesis into reset, then bring it out of reset. 1154 */ 1155 void 1156 sk_reset(struct sk_softc *sc) 1157 { 1158 DPRINTFN(2, ("sk_reset\n")); 1159 1160 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1161 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1162 if (SK_YUKON_FAMILY(sc->sk_type)) 1163 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1164 1165 DELAY(1000); 1166 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1167 DELAY(2); 1168 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1169 if (SK_YUKON_FAMILY(sc->sk_type)) 1170 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1171 1172 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1173 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1174 CSR_READ_2(sc, SK_LINK_CTRL))); 1175 1176 if (sc->sk_type == SK_GENESIS) { 1177 /* Configure packet arbiter */ 1178 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1179 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1180 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1181 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1182 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1183 } 1184 1185 /* Enable RAM interface */ 1186 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1187 1188 sk_update_int_mod(sc); 1189 } 1190 1191 int 1192 sk_probe(device_t parent, cfdata_t match, void *aux) 1193 { 1194 struct skc_attach_args *sa = aux; 1195 1196 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1197 return 0; 1198 1199 return 1; 1200 } 1201 1202 /* 1203 * Each XMAC chip is attached as a separate logical IP interface. 1204 * Single port cards will have only one logical interface of course. 1205 */ 1206 void 1207 sk_attach(device_t parent, device_t self, void *aux) 1208 { 1209 struct sk_if_softc *sc_if = device_private(self); 1210 struct mii_data *mii = &sc_if->sk_mii; 1211 struct sk_softc *sc = device_private(parent); 1212 struct skc_attach_args *sa = aux; 1213 struct sk_txmap_entry *entry; 1214 struct ifnet *ifp; 1215 bus_dma_segment_t seg; 1216 bus_dmamap_t dmamap; 1217 prop_data_t data; 1218 void *kva; 1219 int i, rseg; 1220 int mii_flags = 0; 1221 1222 aprint_naive("\n"); 1223 1224 sc_if->sk_dev = self; 1225 sc_if->sk_port = sa->skc_port; 1226 sc_if->sk_softc = sc; 1227 sc->sk_if[sa->skc_port] = sc_if; 1228 1229 if (sa->skc_port == SK_PORT_A) 1230 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1231 if (sa->skc_port == SK_PORT_B) 1232 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1233 1234 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1235 1236 /* 1237 * Get station address for this interface. Note that 1238 * dual port cards actually come with three station 1239 * addresses: one for each port, plus an extra. The 1240 * extra one is used by the SysKonnect driver software 1241 * as a 'virtual' station address for when both ports 1242 * are operating in failover mode. Currently we don't 1243 * use this extra address. 1244 */ 1245 data = prop_dictionary_get(device_properties(self), "mac-address"); 1246 if (data != NULL) { 1247 /* 1248 * Try to get the station address from device properties 1249 * first, in case the ROM is missing. 1250 */ 1251 KASSERT(prop_object_type(data) == PROP_TYPE_DATA); 1252 KASSERT(prop_data_size(data) == ETHER_ADDR_LEN); 1253 memcpy(sc_if->sk_enaddr, prop_data_data_nocopy(data), 1254 ETHER_ADDR_LEN); 1255 } else 1256 for (i = 0; i < ETHER_ADDR_LEN; i++) 1257 sc_if->sk_enaddr[i] = sk_win_read_1(sc, 1258 SK_MAC0_0 + (sa->skc_port * 8) + i); 1259 1260 aprint_normal(": Ethernet address %s\n", 1261 ether_sprintf(sc_if->sk_enaddr)); 1262 1263 /* 1264 * Set up RAM buffer addresses. The NIC will have a certain 1265 * amount of SRAM on it, somewhere between 512K and 2MB. We 1266 * need to divide this up a) between the transmitter and 1267 * receiver and b) between the two XMACs, if this is a 1268 * dual port NIC. Our algorithm is to divide up the memory 1269 * evenly so that everyone gets a fair share. 1270 */ 1271 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1272 uint32_t chunk, val; 1273 1274 chunk = sc->sk_ramsize / 2; 1275 val = sc->sk_rboff / sizeof(uint64_t); 1276 sc_if->sk_rx_ramstart = val; 1277 val += (chunk / sizeof(uint64_t)); 1278 sc_if->sk_rx_ramend = val - 1; 1279 sc_if->sk_tx_ramstart = val; 1280 val += (chunk / sizeof(uint64_t)); 1281 sc_if->sk_tx_ramend = val - 1; 1282 } else { 1283 uint32_t chunk, val; 1284 1285 chunk = sc->sk_ramsize / 4; 1286 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1287 sizeof(uint64_t); 1288 sc_if->sk_rx_ramstart = val; 1289 val += (chunk / sizeof(uint64_t)); 1290 sc_if->sk_rx_ramend = val - 1; 1291 sc_if->sk_tx_ramstart = val; 1292 val += (chunk / sizeof(uint64_t)); 1293 sc_if->sk_tx_ramend = val - 1; 1294 } 1295 1296 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1297 " tx_ramstart=%#x tx_ramend=%#x\n", 1298 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1299 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1300 1301 /* Read and save PHY type and set PHY address */ 1302 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1303 switch (sc_if->sk_phytype) { 1304 case SK_PHYTYPE_XMAC: 1305 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1306 break; 1307 case SK_PHYTYPE_BCOM: 1308 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1309 break; 1310 case SK_PHYTYPE_MARV_COPPER: 1311 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1312 break; 1313 default: 1314 aprint_error_dev(sc->sk_dev, "unsupported PHY type: %d\n", 1315 sc_if->sk_phytype); 1316 return; 1317 } 1318 1319 /* Allocate the descriptor queues. */ 1320 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1321 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1322 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 1323 goto fail; 1324 } 1325 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1326 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1327 aprint_error_dev(sc_if->sk_dev, 1328 "can't map dma buffers (%lu bytes)\n", 1329 (u_long) sizeof(struct sk_ring_data)); 1330 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1331 goto fail; 1332 } 1333 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1334 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1335 &sc_if->sk_ring_map)) { 1336 aprint_error_dev(sc_if->sk_dev, "can't create dma map\n"); 1337 bus_dmamem_unmap(sc->sc_dmatag, kva, 1338 sizeof(struct sk_ring_data)); 1339 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1340 goto fail; 1341 } 1342 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1343 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1344 aprint_error_dev(sc_if->sk_dev, "can't load dma map\n"); 1345 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1346 bus_dmamem_unmap(sc->sc_dmatag, kva, 1347 sizeof(struct sk_ring_data)); 1348 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1349 goto fail; 1350 } 1351 1352 for (i = 0; i < SK_RX_RING_CNT; i++) 1353 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1354 1355 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1356 for (i = 0; i < SK_TX_RING_CNT; i++) { 1357 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1358 1359 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1360 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1361 aprint_error_dev(sc_if->sk_dev, 1362 "Can't create TX dmamap\n"); 1363 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1364 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1365 bus_dmamem_unmap(sc->sc_dmatag, kva, 1366 sizeof(struct sk_ring_data)); 1367 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1368 goto fail; 1369 } 1370 1371 entry = malloc(sizeof(*entry), M_DEVBUF, M_WAITOK); 1372 entry->dmamap = dmamap; 1373 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1374 } 1375 1376 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1377 memset(sc_if->sk_rdata, 0, sizeof(struct sk_ring_data)); 1378 1379 ifp = &sc_if->sk_ethercom.ec_if; 1380 /* Try to allocate memory for jumbo buffers. */ 1381 if (sk_alloc_jumbo_mem(sc_if)) { 1382 aprint_error("%s: jumbo buffer allocation failed\n", 1383 ifp->if_xname); 1384 goto fail; 1385 } 1386 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1387 | ETHERCAP_JUMBO_MTU; 1388 1389 ifp->if_softc = sc_if; 1390 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1391 ifp->if_ioctl = sk_ioctl; 1392 ifp->if_start = sk_start; 1393 ifp->if_stop = sk_stop; 1394 ifp->if_init = sk_init; 1395 ifp->if_watchdog = sk_watchdog; 1396 ifp->if_capabilities = 0; 1397 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1398 IFQ_SET_READY(&ifp->if_snd); 1399 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1400 1401 /* 1402 * Do miibus setup. 1403 */ 1404 switch (sc->sk_type) { 1405 case SK_GENESIS: 1406 sk_unreset_xmac(sc_if); 1407 break; 1408 case SK_YUKON: 1409 case SK_YUKON_LITE: 1410 case SK_YUKON_LP: 1411 sk_unreset_yukon(sc_if); 1412 break; 1413 default: 1414 aprint_error_dev(sc->sk_dev, "unknown device type %d\n", 1415 sc->sk_type); 1416 goto fail; 1417 } 1418 1419 DPRINTFN(2, ("sk_attach: 1\n")); 1420 1421 mii->mii_ifp = ifp; 1422 switch (sc->sk_type) { 1423 case SK_GENESIS: 1424 mii->mii_readreg = sk_xmac_miibus_readreg; 1425 mii->mii_writereg = sk_xmac_miibus_writereg; 1426 mii->mii_statchg = sk_xmac_miibus_statchg; 1427 break; 1428 case SK_YUKON: 1429 case SK_YUKON_LITE: 1430 case SK_YUKON_LP: 1431 mii->mii_readreg = sk_marv_miibus_readreg; 1432 mii->mii_writereg = sk_marv_miibus_writereg; 1433 mii->mii_statchg = sk_marv_miibus_statchg; 1434 mii_flags = MIIF_DOPAUSE; 1435 break; 1436 } 1437 1438 sc_if->sk_ethercom.ec_mii = mii; 1439 ifmedia_init(&mii->mii_media, 0, sk_ifmedia_upd, ether_mediastatus); 1440 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 1441 MII_OFFSET_ANY, mii_flags); 1442 if (LIST_EMPTY(&mii->mii_phys)) { 1443 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1444 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 1445 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 1446 } else 1447 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1448 1449 callout_init(&sc_if->sk_tick_ch, 0); 1450 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 1451 1452 DPRINTFN(2, ("sk_attach: 1\n")); 1453 1454 /* 1455 * Call MI attach routines. 1456 */ 1457 if_attach(ifp); 1458 if_deferred_start_init(ifp, NULL); 1459 1460 ether_ifattach(ifp, sc_if->sk_enaddr); 1461 1462 if (sc->rnd_attached++ == 0) { 1463 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1464 RND_TYPE_NET, RND_FLAG_DEFAULT); 1465 } 1466 1467 if (pmf_device_register(self, NULL, sk_resume)) 1468 pmf_class_network_register(self, ifp); 1469 else 1470 aprint_error_dev(self, "couldn't establish power handler\n"); 1471 1472 DPRINTFN(2, ("sk_attach: end\n")); 1473 1474 return; 1475 1476 fail: 1477 sc->sk_if[sa->skc_port] = NULL; 1478 } 1479 1480 int 1481 skcprint(void *aux, const char *pnp) 1482 { 1483 struct skc_attach_args *sa = aux; 1484 1485 if (pnp) 1486 aprint_normal("sk port %c at %s", 1487 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1488 else 1489 aprint_normal(" port %c", 1490 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1491 return UNCONF; 1492 } 1493 1494 /* 1495 * Attach the interface. Allocate softc structures, do ifmedia 1496 * setup and ethernet/BPF attach. 1497 */ 1498 void 1499 skc_attach(device_t parent, device_t self, void *aux) 1500 { 1501 struct sk_softc *sc = device_private(self); 1502 struct pci_attach_args *pa = aux; 1503 struct skc_attach_args skca; 1504 pci_chipset_tag_t pc = pa->pa_pc; 1505 #ifndef SK_USEIOSPACE 1506 pcireg_t memtype; 1507 #endif 1508 pci_intr_handle_t ih; 1509 const char *intrstr = NULL; 1510 bus_addr_t iobase; 1511 bus_size_t iosize; 1512 int rc, sk_nodenum; 1513 uint32_t command; 1514 const char *revstr; 1515 const struct sysctlnode *node; 1516 char intrbuf[PCI_INTRSTR_LEN]; 1517 1518 sc->sk_dev = self; 1519 aprint_naive("\n"); 1520 1521 DPRINTFN(2, ("begin skc_attach\n")); 1522 1523 /* 1524 * Handle power management nonsense. 1525 */ 1526 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1527 1528 if (command == 0x01) { 1529 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1530 if (command & SK_PSTATE_MASK) { 1531 uint32_t xiobase, membase, irq; 1532 1533 /* Save important PCI config data. */ 1534 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1535 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1536 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1537 1538 /* Reset the power state. */ 1539 aprint_normal_dev(sc->sk_dev, 1540 "chip is in D%d power mode -- setting to D0\n", 1541 command & SK_PSTATE_MASK); 1542 command &= 0xFFFFFFFC; 1543 pci_conf_write(pc, pa->pa_tag, 1544 SK_PCI_PWRMGMTCTRL, command); 1545 1546 /* Restore PCI config data. */ 1547 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1548 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1549 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1550 } 1551 } 1552 1553 /* 1554 * The firmware might have configured the interface to revert the 1555 * byte order in all descriptors. Make that undone. 1556 */ 1557 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_OURREG2); 1558 if (command & SK_REG2_REV_DESC) 1559 pci_conf_write(pc, pa->pa_tag, SK_PCI_OURREG2, 1560 command & ~SK_REG2_REV_DESC); 1561 1562 /* 1563 * Map control/status registers. 1564 */ 1565 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1566 command |= PCI_COMMAND_IO_ENABLE | 1567 PCI_COMMAND_MEM_ENABLE | 1568 PCI_COMMAND_MASTER_ENABLE; 1569 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1570 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1571 1572 #ifdef SK_USEIOSPACE 1573 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1574 aprint_error(": failed to enable I/O ports!\n"); 1575 return; 1576 } 1577 /* 1578 * Map control/status registers. 1579 */ 1580 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1581 &sc->sk_btag, &sc->sk_bhandle, 1582 &iobase, &iosize)) { 1583 aprint_error(": can't find i/o space\n"); 1584 return; 1585 } 1586 #else 1587 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1588 aprint_error(": failed to enable memory mapping!\n"); 1589 return; 1590 } 1591 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1592 switch (memtype) { 1593 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1594 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1595 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1596 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1597 &iobase, &iosize) == 0) 1598 break; 1599 /* FALLTHROUGH */ 1600 default: 1601 aprint_error_dev(sc->sk_dev, "can't find mem space\n"); 1602 return; 1603 } 1604 1605 DPRINTFN(2, ("skc_attach: iobase=%#" PRIxPADDR ", iosize=%zx\n", 1606 iobase, iosize)); 1607 #endif 1608 sc->sc_dmatag = pa->pa_dmat; 1609 1610 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1611 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1612 1613 /* bail out here if chip is not recognized */ 1614 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1615 aprint_error_dev(sc->sk_dev, "unknown chip type\n"); 1616 goto fail; 1617 } 1618 if (SK_IS_YUKON2(sc)) { 1619 aprint_error_dev(sc->sk_dev, 1620 "Does not support Yukon2--try msk(4).\n"); 1621 goto fail; 1622 } 1623 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1624 1625 /* Allocate interrupt */ 1626 if (pci_intr_map(pa, &ih)) { 1627 aprint_error(": couldn't map interrupt\n"); 1628 goto fail; 1629 } 1630 1631 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1632 sc->sk_intrhand = pci_intr_establish_xname(pc, ih, IPL_NET, sk_intr, 1633 sc, device_xname(sc->sk_dev)); 1634 if (sc->sk_intrhand == NULL) { 1635 aprint_error(": couldn't establish interrupt"); 1636 if (intrstr != NULL) 1637 aprint_error(" at %s", intrstr); 1638 aprint_error("\n"); 1639 goto fail; 1640 } 1641 aprint_normal(": %s\n", intrstr); 1642 1643 /* Reset the adapter. */ 1644 sk_reset(sc); 1645 1646 /* Read and save vital product data from EEPROM. */ 1647 sk_vpd_read(sc); 1648 1649 if (sc->sk_type == SK_GENESIS) { 1650 uint8_t val = sk_win_read_1(sc, SK_EPROM0); 1651 /* Read and save RAM size and RAMbuffer offset */ 1652 switch (val) { 1653 case SK_RAMSIZE_512K_64: 1654 sc->sk_ramsize = 0x80000; 1655 sc->sk_rboff = SK_RBOFF_0; 1656 break; 1657 case SK_RAMSIZE_1024K_64: 1658 sc->sk_ramsize = 0x100000; 1659 sc->sk_rboff = SK_RBOFF_80000; 1660 break; 1661 case SK_RAMSIZE_1024K_128: 1662 sc->sk_ramsize = 0x100000; 1663 sc->sk_rboff = SK_RBOFF_0; 1664 break; 1665 case SK_RAMSIZE_2048K_128: 1666 sc->sk_ramsize = 0x200000; 1667 sc->sk_rboff = SK_RBOFF_0; 1668 break; 1669 default: 1670 aprint_error_dev(sc->sk_dev, "unknown ram size: %d\n", 1671 val); 1672 goto fail_1; 1673 break; 1674 } 1675 1676 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1677 sc->sk_ramsize, sc->sk_ramsize / 1024, 1678 sc->sk_rboff)); 1679 } else { 1680 uint8_t val = sk_win_read_1(sc, SK_EPROM0); 1681 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1682 sc->sk_rboff = SK_RBOFF_0; 1683 1684 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1685 sc->sk_ramsize / 1024, sc->sk_ramsize, 1686 sc->sk_rboff)); 1687 } 1688 1689 /* Read and save physical media type */ 1690 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1691 case SK_PMD_1000BASESX: 1692 sc->sk_pmd = IFM_1000_SX; 1693 break; 1694 case SK_PMD_1000BASELX: 1695 sc->sk_pmd = IFM_1000_LX; 1696 break; 1697 case SK_PMD_1000BASECX: 1698 sc->sk_pmd = IFM_1000_CX; 1699 break; 1700 case SK_PMD_1000BASETX: 1701 case SK_PMD_1000BASETX_ALT: 1702 sc->sk_pmd = IFM_1000_T; 1703 break; 1704 default: 1705 aprint_error_dev(sc->sk_dev, "unknown media type: 0x%x\n", 1706 sk_win_read_1(sc, SK_PMDTYPE)); 1707 goto fail_1; 1708 } 1709 1710 /* determine whether to name it with vpd or just make it up */ 1711 /* Marvell Yukon VPD's can freqently be bogus */ 1712 1713 switch (pa->pa_id) { 1714 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1715 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1716 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1717 case PCI_PRODUCT_3COM_3C940: 1718 case PCI_PRODUCT_DLINK_DGE530T: 1719 case PCI_PRODUCT_DLINK_DGE560T: 1720 case PCI_PRODUCT_DLINK_DGE560T_2: 1721 case PCI_PRODUCT_LINKSYS_EG1032: 1722 case PCI_PRODUCT_LINKSYS_EG1064: 1723 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1724 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1725 case PCI_ID_CODE(PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940): 1726 case PCI_ID_CODE(PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T): 1727 case PCI_ID_CODE(PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T): 1728 case PCI_ID_CODE(PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2): 1729 case PCI_ID_CODE(PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032): 1730 case PCI_ID_CODE(PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064): 1731 sc->sk_name = sc->sk_vpd_prodname; 1732 break; 1733 case PCI_ID_CODE(PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET): 1734 /* whoops yukon vpd prodname bears no resemblance to reality */ 1735 switch (sc->sk_type) { 1736 case SK_GENESIS: 1737 sc->sk_name = sc->sk_vpd_prodname; 1738 break; 1739 case SK_YUKON: 1740 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1741 break; 1742 case SK_YUKON_LITE: 1743 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1744 break; 1745 case SK_YUKON_LP: 1746 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1747 break; 1748 default: 1749 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1750 } 1751 1752 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1753 1754 if ( sc->sk_type == SK_YUKON ) { 1755 uint32_t flashaddr; 1756 uint8_t testbyte; 1757 1758 flashaddr = sk_win_read_4(sc, SK_EP_ADDR); 1759 1760 /* test Flash-Address Register */ 1761 sk_win_write_1(sc, SK_EP_ADDR+3, 0xff); 1762 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1763 1764 if (testbyte != 0) { 1765 /* this is yukon lite Rev. A0 */ 1766 sc->sk_type = SK_YUKON_LITE; 1767 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1768 /* restore Flash-Address Register */ 1769 sk_win_write_4(sc, SK_EP_ADDR, flashaddr); 1770 } 1771 } 1772 break; 1773 case PCI_ID_CODE(PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN): 1774 sc->sk_name = sc->sk_vpd_prodname; 1775 break; 1776 default: 1777 sc->sk_name = "Unknown Marvell"; 1778 } 1779 1780 1781 if ( sc->sk_type == SK_YUKON_LITE ) { 1782 switch (sc->sk_rev) { 1783 case SK_YUKON_LITE_REV_A0: 1784 revstr = "A0"; 1785 break; 1786 case SK_YUKON_LITE_REV_A1: 1787 revstr = "A1"; 1788 break; 1789 case SK_YUKON_LITE_REV_A3: 1790 revstr = "A3"; 1791 break; 1792 default: 1793 revstr = ""; 1794 } 1795 } else { 1796 revstr = ""; 1797 } 1798 1799 /* Announce the product name. */ 1800 aprint_normal_dev(sc->sk_dev, "%s rev. %s(0x%x)\n", 1801 sc->sk_name, revstr, sc->sk_rev); 1802 1803 skca.skc_port = SK_PORT_A; 1804 (void)config_found(sc->sk_dev, &skca, skcprint); 1805 1806 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1807 skca.skc_port = SK_PORT_B; 1808 (void)config_found(sc->sk_dev, &skca, skcprint); 1809 } 1810 1811 /* Turn on the 'driver is loaded' LED. */ 1812 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1813 1814 /* skc sysctl setup */ 1815 1816 sc->sk_int_mod = SK_IM_DEFAULT; 1817 sc->sk_int_mod_pending = 0; 1818 1819 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1820 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1821 SYSCTL_DESCR("skc per-controller controls"), 1822 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1823 CTL_EOL)) != 0) { 1824 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1825 goto fail_1; 1826 } 1827 1828 sk_nodenum = node->sysctl_num; 1829 1830 /* interrupt moderation time in usecs */ 1831 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1832 CTLFLAG_READWRITE, 1833 CTLTYPE_INT, "int_mod", 1834 SYSCTL_DESCR("sk interrupt moderation timer"), 1835 sk_sysctl_handler, 0, (void *)sc, 1836 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1837 CTL_EOL)) != 0) { 1838 aprint_normal_dev(sc->sk_dev, 1839 "couldn't create int_mod sysctl node\n"); 1840 goto fail_1; 1841 } 1842 1843 if (!pmf_device_register(self, skc_suspend, skc_resume)) 1844 aprint_error_dev(self, "couldn't establish power handler\n"); 1845 1846 return; 1847 1848 fail_1: 1849 pci_intr_disestablish(pc, sc->sk_intrhand); 1850 fail: 1851 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1852 } 1853 1854 int 1855 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx) 1856 { 1857 struct sk_softc *sc = sc_if->sk_softc; 1858 struct sk_tx_desc *f = NULL; 1859 uint32_t frag, cur, cnt = 0, sk_ctl; 1860 int i; 1861 struct sk_txmap_entry *entry; 1862 bus_dmamap_t txmap; 1863 1864 DPRINTFN(3, ("sk_encap\n")); 1865 1866 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1867 if (entry == NULL) { 1868 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1869 return ENOBUFS; 1870 } 1871 txmap = entry->dmamap; 1872 1873 cur = frag = *txidx; 1874 1875 #ifdef SK_DEBUG 1876 if (skdebug >= 3) 1877 sk_dump_mbuf(m_head); 1878 #endif 1879 1880 /* 1881 * Start packing the mbufs in this chain into 1882 * the fragment pointers. Stop when we run out 1883 * of fragments or hit the end of the mbuf chain. 1884 */ 1885 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1886 BUS_DMA_NOWAIT)) { 1887 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1888 return ENOBUFS; 1889 } 1890 1891 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1892 1893 /* Sync the DMA map. */ 1894 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1895 BUS_DMASYNC_PREWRITE); 1896 1897 for (i = 0; i < txmap->dm_nsegs; i++) { 1898 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1899 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1900 return ENOBUFS; 1901 } 1902 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1903 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1904 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1905 if (cnt == 0) 1906 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1907 else 1908 sk_ctl |= SK_TXCTL_OWN; 1909 f->sk_ctl = htole32(sk_ctl); 1910 cur = frag; 1911 SK_INC(frag, SK_TX_RING_CNT); 1912 cnt++; 1913 } 1914 1915 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1916 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1917 1918 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1919 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1920 htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR); 1921 1922 /* Sync descriptors before handing to chip */ 1923 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1924 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1925 1926 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1927 htole32(SK_TXCTL_OWN); 1928 1929 /* Sync first descriptor to hand it off */ 1930 SK_CDTXSYNC(sc_if, *txidx, 1, 1931 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1932 1933 sc_if->sk_cdata.sk_tx_cnt += cnt; 1934 1935 #ifdef SK_DEBUG 1936 if (skdebug >= 3) { 1937 struct sk_tx_desc *desc; 1938 uint32_t idx; 1939 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1940 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1941 sk_dump_txdesc(desc, idx); 1942 } 1943 } 1944 #endif 1945 1946 *txidx = frag; 1947 1948 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1949 1950 return 0; 1951 } 1952 1953 void 1954 sk_start(struct ifnet *ifp) 1955 { 1956 struct sk_if_softc *sc_if = ifp->if_softc; 1957 struct sk_softc *sc = sc_if->sk_softc; 1958 struct mbuf *m_head = NULL; 1959 uint32_t idx = sc_if->sk_cdata.sk_tx_prod; 1960 int pkts = 0; 1961 1962 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1963 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1964 1965 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1966 IFQ_POLL(&ifp->if_snd, m_head); 1967 if (m_head == NULL) 1968 break; 1969 1970 /* 1971 * Pack the data into the transmit ring. If we 1972 * don't have room, set the OACTIVE flag and wait 1973 * for the NIC to drain the ring. 1974 */ 1975 if (sk_encap(sc_if, m_head, &idx)) { 1976 ifp->if_flags |= IFF_OACTIVE; 1977 break; 1978 } 1979 1980 /* now we are committed to transmit the packet */ 1981 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1982 pkts++; 1983 1984 /* 1985 * If there's a BPF listener, bounce a copy of this frame 1986 * to him. 1987 */ 1988 bpf_mtap(ifp, m_head, BPF_D_OUT); 1989 } 1990 if (pkts == 0) 1991 return; 1992 1993 /* Transmit */ 1994 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1995 sc_if->sk_cdata.sk_tx_prod = idx; 1996 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1997 1998 /* Set a timeout in case the chip goes out to lunch. */ 1999 ifp->if_timer = 5; 2000 } 2001 } 2002 2003 2004 void 2005 sk_watchdog(struct ifnet *ifp) 2006 { 2007 struct sk_if_softc *sc_if = ifp->if_softc; 2008 2009 /* 2010 * Reclaim first as there is a possibility of losing Tx completion 2011 * interrupts. 2012 */ 2013 sk_txeof(sc_if); 2014 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 2015 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 2016 2017 ifp->if_oerrors++; 2018 2019 sk_init(ifp); 2020 } 2021 } 2022 2023 void 2024 sk_shutdown(void *v) 2025 { 2026 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 2027 struct sk_softc *sc = sc_if->sk_softc; 2028 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2029 2030 DPRINTFN(2, ("sk_shutdown\n")); 2031 sk_stop(ifp, 1); 2032 2033 /* Turn off the 'driver is loaded' LED. */ 2034 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2035 2036 /* 2037 * Reset the GEnesis controller. Doing this should also 2038 * assert the resets on the attached XMAC(s). 2039 */ 2040 sk_reset(sc); 2041 } 2042 2043 void 2044 sk_rxeof(struct sk_if_softc *sc_if) 2045 { 2046 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2047 struct mbuf *m; 2048 struct sk_chain *cur_rx; 2049 struct sk_rx_desc *cur_desc; 2050 int i, cur, total_len = 0; 2051 uint32_t rxstat, sk_ctl; 2052 bus_dmamap_t dmamap; 2053 2054 i = sc_if->sk_cdata.sk_rx_prod; 2055 2056 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2057 2058 for (;;) { 2059 cur = i; 2060 2061 /* Sync the descriptor */ 2062 SK_CDRXSYNC(sc_if, cur, 2063 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2064 2065 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2066 if (sk_ctl & SK_RXCTL_OWN) { 2067 /* Invalidate the descriptor -- it's not ready yet */ 2068 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2069 sc_if->sk_cdata.sk_rx_prod = i; 2070 break; 2071 } 2072 2073 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2074 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2075 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2076 2077 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2078 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2079 2080 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2081 m = cur_rx->sk_mbuf; 2082 cur_rx->sk_mbuf = NULL; 2083 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2084 2085 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2086 2087 SK_INC(i, SK_RX_RING_CNT); 2088 2089 if (rxstat & XM_RXSTAT_ERRFRAME) { 2090 ifp->if_ierrors++; 2091 sk_newbuf(sc_if, cur, m, dmamap); 2092 continue; 2093 } 2094 2095 /* 2096 * Try to allocate a new jumbo buffer. If that 2097 * fails, copy the packet to mbufs and put the 2098 * jumbo buffer back in the ring so it can be 2099 * re-used. If allocating mbufs fails, then we 2100 * have to drop the packet. 2101 */ 2102 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2103 struct mbuf *m0; 2104 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2105 total_len + ETHER_ALIGN, 0, ifp); 2106 sk_newbuf(sc_if, cur, m, dmamap); 2107 if (m0 == NULL) { 2108 aprint_error_dev(sc_if->sk_dev, "no receive " 2109 "buffers available -- packet dropped!\n"); 2110 ifp->if_ierrors++; 2111 continue; 2112 } 2113 m_adj(m0, ETHER_ALIGN); 2114 m = m0; 2115 } else { 2116 m_set_rcvif(m, ifp); 2117 m->m_pkthdr.len = m->m_len = total_len; 2118 } 2119 2120 /* pass it on. */ 2121 if_percpuq_enqueue(ifp->if_percpuq, m); 2122 } 2123 } 2124 2125 void 2126 sk_txeof(struct sk_if_softc *sc_if) 2127 { 2128 struct sk_softc *sc = sc_if->sk_softc; 2129 struct sk_tx_desc *cur_tx; 2130 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2131 uint32_t idx, sk_ctl; 2132 struct sk_txmap_entry *entry; 2133 2134 DPRINTFN(3, ("sk_txeof\n")); 2135 2136 /* 2137 * Go through our tx ring and free mbufs for those 2138 * frames that have been sent. 2139 */ 2140 idx = sc_if->sk_cdata.sk_tx_cons; 2141 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2142 SK_CDTXSYNC(sc_if, idx, 1, 2143 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2144 2145 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2146 sk_ctl = le32toh(cur_tx->sk_ctl); 2147 #ifdef SK_DEBUG 2148 if (skdebug >= 3) 2149 sk_dump_txdesc(cur_tx, idx); 2150 #endif 2151 if (sk_ctl & SK_TXCTL_OWN) { 2152 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2153 break; 2154 } 2155 if (sk_ctl & SK_TXCTL_LASTFRAG) 2156 ifp->if_opackets++; 2157 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2158 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2159 2160 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2161 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2162 2163 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2164 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2165 2166 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2167 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2168 link); 2169 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2170 } 2171 sc_if->sk_cdata.sk_tx_cnt--; 2172 SK_INC(idx, SK_TX_RING_CNT); 2173 } 2174 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2175 ifp->if_timer = 0; 2176 else /* nudge chip to keep tx ring moving */ 2177 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2178 2179 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2180 ifp->if_flags &= ~IFF_OACTIVE; 2181 2182 sc_if->sk_cdata.sk_tx_cons = idx; 2183 } 2184 2185 void 2186 sk_tick(void *xsc_if) 2187 { 2188 struct sk_if_softc *sc_if = xsc_if; 2189 struct mii_data *mii = &sc_if->sk_mii; 2190 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2191 int i; 2192 2193 DPRINTFN(3, ("sk_tick\n")); 2194 2195 if (!(ifp->if_flags & IFF_UP)) 2196 return; 2197 2198 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2199 sk_intr_bcom(sc_if); 2200 return; 2201 } 2202 2203 /* 2204 * According to SysKonnect, the correct way to verify that 2205 * the link has come back up is to poll bit 0 of the GPIO 2206 * register three times. This pin has the signal from the 2207 * link sync pin connected to it; if we read the same link 2208 * state 3 times in a row, we know the link is up. 2209 */ 2210 for (i = 0; i < 3; i++) { 2211 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2212 break; 2213 } 2214 2215 if (i != 3) { 2216 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2217 return; 2218 } 2219 2220 /* Turn the GP0 interrupt back on. */ 2221 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2222 SK_XM_READ_2(sc_if, XM_ISR); 2223 mii_tick(mii); 2224 if (ifp->if_link_state != LINK_STATE_UP) 2225 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2226 else 2227 callout_stop(&sc_if->sk_tick_ch); 2228 } 2229 2230 void 2231 sk_intr_bcom(struct sk_if_softc *sc_if) 2232 { 2233 struct mii_data *mii = &sc_if->sk_mii; 2234 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2235 uint16_t status; 2236 2237 2238 DPRINTFN(3, ("sk_intr_bcom\n")); 2239 2240 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB); 2241 2242 /* 2243 * Read the PHY interrupt register to make sure 2244 * we clear any pending interrupts. 2245 */ 2246 sk_xmac_miibus_readreg(sc_if->sk_dev, 2247 SK_PHYADDR_BCOM, BRGPHY_MII_ISR, &status); 2248 2249 if (!(ifp->if_flags & IFF_RUNNING)) { 2250 sk_init_xmac(sc_if); 2251 return; 2252 } 2253 2254 if (status & (BRGPHY_ISR_LNK_CHG | BRGPHY_ISR_AN_PR)) { 2255 uint16_t lstat; 2256 sk_xmac_miibus_readreg(sc_if->sk_dev, 2257 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS, &lstat); 2258 2259 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2260 (void)mii_mediachg(mii); 2261 /* Turn off the link LED. */ 2262 SK_IF_WRITE_1(sc_if, 0, 2263 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2264 sc_if->sk_link = 0; 2265 } else if (status & BRGPHY_ISR_LNK_CHG) { 2266 sk_xmac_miibus_writereg(sc_if->sk_dev, 2267 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2268 mii_tick(mii); 2269 sc_if->sk_link = 1; 2270 /* Turn on the link LED. */ 2271 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2272 SK_LINKLED_ON | SK_LINKLED_LINKSYNC_OFF | 2273 SK_LINKLED_BLINK_OFF); 2274 mii_pollstat(mii); 2275 } else { 2276 mii_tick(mii); 2277 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2278 } 2279 } 2280 2281 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB); 2282 } 2283 2284 void 2285 sk_intr_xmac(struct sk_if_softc *sc_if) 2286 { 2287 uint16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2288 2289 DPRINTFN(3, ("sk_intr_xmac\n")); 2290 2291 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2292 if (status & XM_ISR_GP0_SET) { 2293 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2294 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2295 } 2296 2297 if (status & XM_ISR_AUTONEG_DONE) { 2298 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2299 } 2300 } 2301 2302 if (status & XM_IMR_TX_UNDERRUN) 2303 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2304 2305 if (status & XM_IMR_RX_OVERRUN) 2306 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2307 } 2308 2309 void 2310 sk_intr_yukon(struct sk_if_softc *sc_if) 2311 { 2312 #ifdef SK_DEBUG 2313 int status; 2314 2315 status = 2316 #endif 2317 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2318 2319 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2320 } 2321 2322 int 2323 sk_intr(void *xsc) 2324 { 2325 struct sk_softc *sc = xsc; 2326 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2327 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2328 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2329 uint32_t status; 2330 int claimed = 0; 2331 2332 if (sc_if0 != NULL) 2333 ifp0 = &sc_if0->sk_ethercom.ec_if; 2334 if (sc_if1 != NULL) 2335 ifp1 = &sc_if1->sk_ethercom.ec_if; 2336 2337 for (;;) { 2338 status = CSR_READ_4(sc, SK_ISSR); 2339 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2340 2341 if (!(status & sc->sk_intrmask)) 2342 break; 2343 2344 claimed = 1; 2345 2346 /* Handle receive interrupts first. */ 2347 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2348 sk_rxeof(sc_if0); 2349 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2350 SK_RXBMU_CLR_IRQ_EOF | SK_RXBMU_RX_START); 2351 } 2352 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2353 sk_rxeof(sc_if1); 2354 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2355 SK_RXBMU_CLR_IRQ_EOF | SK_RXBMU_RX_START); 2356 } 2357 2358 /* Then transmit interrupts. */ 2359 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2360 sk_txeof(sc_if0); 2361 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2362 SK_TXBMU_CLR_IRQ_EOF); 2363 } 2364 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2365 sk_txeof(sc_if1); 2366 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2367 SK_TXBMU_CLR_IRQ_EOF); 2368 } 2369 2370 /* Then MAC interrupts. */ 2371 if (sc_if0 && (status & SK_ISR_MAC1) && 2372 (ifp0->if_flags & IFF_RUNNING)) { 2373 if (sc->sk_type == SK_GENESIS) 2374 sk_intr_xmac(sc_if0); 2375 else 2376 sk_intr_yukon(sc_if0); 2377 } 2378 2379 if (sc_if1 && (status & SK_ISR_MAC2) && 2380 (ifp1->if_flags & IFF_RUNNING)) { 2381 if (sc->sk_type == SK_GENESIS) 2382 sk_intr_xmac(sc_if1); 2383 else 2384 sk_intr_yukon(sc_if1); 2385 2386 } 2387 2388 if (status & SK_ISR_EXTERNAL_REG) { 2389 if (sc_if0 != NULL && 2390 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2391 sk_intr_bcom(sc_if0); 2392 2393 if (sc_if1 != NULL && 2394 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2395 sk_intr_bcom(sc_if1); 2396 } 2397 } 2398 2399 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2400 2401 if (ifp0 != NULL) 2402 if_schedule_deferred_start(ifp0); 2403 if (ifp1 != NULL) 2404 if_schedule_deferred_start(ifp1); 2405 2406 KASSERT(sc->rnd_attached > 0); 2407 rnd_add_uint32(&sc->rnd_source, status); 2408 2409 if (sc->sk_int_mod_pending) 2410 sk_update_int_mod(sc); 2411 2412 return claimed; 2413 } 2414 2415 void 2416 sk_unreset_xmac(struct sk_if_softc *sc_if) 2417 { 2418 struct sk_softc *sc = sc_if->sk_softc; 2419 static const struct sk_bcom_hack bhack[] = { 2420 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2421 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2422 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2423 { 0, 0 } }; 2424 2425 DPRINTFN(1, ("sk_unreset_xmac\n")); 2426 2427 /* Unreset the XMAC. */ 2428 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2429 DELAY(1000); 2430 2431 /* Reset the XMAC's internal state. */ 2432 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2433 2434 /* Save the XMAC II revision */ 2435 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2436 2437 /* 2438 * Perform additional initialization for external PHYs, 2439 * namely for the 1000baseTX cards that use the XMAC's 2440 * GMII mode. 2441 */ 2442 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2443 int i = 0; 2444 uint32_t val; 2445 uint16_t phyval; 2446 2447 /* Take PHY out of reset. */ 2448 val = sk_win_read_4(sc, SK_GPIO); 2449 if (sc_if->sk_port == SK_PORT_A) 2450 val |= SK_GPIO_DIR0 | SK_GPIO_DAT0; 2451 else 2452 val |= SK_GPIO_DIR2 | SK_GPIO_DAT2; 2453 sk_win_write_4(sc, SK_GPIO, val); 2454 2455 /* Enable GMII mode on the XMAC. */ 2456 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2457 2458 sk_xmac_miibus_writereg(sc_if->sk_dev, 2459 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2460 DELAY(10000); 2461 sk_xmac_miibus_writereg(sc_if->sk_dev, 2462 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2463 2464 /* 2465 * Early versions of the BCM5400 apparently have 2466 * a bug that requires them to have their reserved 2467 * registers initialized to some magic values. I don't 2468 * know what the numbers do, I'm just the messenger. 2469 */ 2470 sk_xmac_miibus_readreg(sc_if->sk_dev, 2471 SK_PHYADDR_BCOM, 0x03, &phyval); 2472 if (phyval == 0x6041) { 2473 while (bhack[i].reg) { 2474 sk_xmac_miibus_writereg(sc_if->sk_dev, 2475 SK_PHYADDR_BCOM, bhack[i].reg, 2476 bhack[i].val); 2477 i++; 2478 } 2479 } 2480 } 2481 } 2482 2483 void 2484 sk_init_xmac(struct sk_if_softc *sc_if) 2485 { 2486 struct sk_softc *sc = sc_if->sk_softc; 2487 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2488 2489 sk_unreset_xmac(sc_if); 2490 2491 /* Set station address */ 2492 SK_XM_WRITE_2(sc_if, XM_PAR0, 2493 *(uint16_t *)(&sc_if->sk_enaddr[0])); 2494 SK_XM_WRITE_2(sc_if, XM_PAR1, 2495 *(uint16_t *)(&sc_if->sk_enaddr[2])); 2496 SK_XM_WRITE_2(sc_if, XM_PAR2, 2497 *(uint16_t *)(&sc_if->sk_enaddr[4])); 2498 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2499 2500 if (ifp->if_flags & IFF_PROMISC) 2501 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2502 else 2503 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2504 2505 if (ifp->if_flags & IFF_BROADCAST) 2506 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2507 else 2508 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2509 2510 /* We don't need the FCS appended to the packet. */ 2511 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2512 2513 /* We want short frames padded to 60 bytes. */ 2514 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2515 2516 /* 2517 * Enable the reception of all error frames. This is is 2518 * a necessary evil due to the design of the XMAC. The 2519 * XMAC's receive FIFO is only 8K in size, however jumbo 2520 * frames can be up to 9000 bytes in length. When bad 2521 * frame filtering is enabled, the XMAC's RX FIFO operates 2522 * in 'store and forward' mode. For this to work, the 2523 * entire frame has to fit into the FIFO, but that means 2524 * that jumbo frames larger than 8192 bytes will be 2525 * truncated. Disabling all bad frame filtering causes 2526 * the RX FIFO to operate in streaming mode, in which 2527 * case the XMAC will start transfering frames out of the 2528 * RX FIFO as soon as the FIFO threshold is reached. 2529 */ 2530 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES | 2531 XM_MODE_RX_GIANTS | XM_MODE_RX_RUNTS | XM_MODE_RX_CRCERRS | 2532 XM_MODE_RX_INRANGELEN); 2533 2534 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2535 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2536 else 2537 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2538 2539 /* 2540 * Bump up the transmit threshold. This helps hold off transmit 2541 * underruns when we're blasting traffic from both ports at once. 2542 */ 2543 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2544 2545 /* Set multicast filter */ 2546 sk_setmulti(sc_if); 2547 2548 /* Clear and enable interrupts */ 2549 SK_XM_READ_2(sc_if, XM_ISR); 2550 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2551 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2552 else 2553 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2554 2555 /* Configure MAC arbiter */ 2556 switch (sc_if->sk_xmac_rev) { 2557 case XM_XMAC_REV_B2: 2558 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2559 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2560 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2561 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2562 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2563 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2564 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2565 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2566 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2567 break; 2568 case XM_XMAC_REV_C1: 2569 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2570 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2571 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2572 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2573 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2574 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2575 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2576 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2577 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2578 break; 2579 default: 2580 break; 2581 } 2582 sk_win_write_2(sc, SK_MACARB_CTL, 2583 SK_MACARBCTL_UNRESET | SK_MACARBCTL_FASTOE_OFF); 2584 2585 sc_if->sk_link = 1; 2586 } 2587 2588 void 2589 sk_unreset_yukon(struct sk_if_softc *sc_if) 2590 { 2591 uint32_t /*mac, */phy; 2592 struct sk_softc *sc; 2593 2594 DPRINTFN(1, ("sk_unreset_yukon: start: sk_csr=%#x\n", 2595 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2596 2597 sc = sc_if->sk_softc; 2598 if (sc->sk_type == SK_YUKON_LITE && 2599 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2600 /* Take PHY out of reset. */ 2601 sk_win_write_4(sc, SK_GPIO, 2602 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) 2603 & ~SK_GPIO_DAT9); 2604 } 2605 2606 /* GMAC and GPHY Reset */ 2607 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2608 2609 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2610 2611 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2612 DELAY(1000); 2613 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2614 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2615 DELAY(1000); 2616 2617 2618 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2619 2620 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2621 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2622 2623 switch (sc_if->sk_softc->sk_pmd) { 2624 case IFM_1000_SX: 2625 case IFM_1000_LX: 2626 phy |= SK_GPHY_FIBER; 2627 break; 2628 2629 case IFM_1000_CX: 2630 case IFM_1000_T: 2631 phy |= SK_GPHY_COPPER; 2632 break; 2633 } 2634 2635 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2636 2637 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2638 DELAY(1000); 2639 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2640 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2641 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2642 2643 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2644 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2645 } 2646 2647 void 2648 sk_init_yukon(struct sk_if_softc *sc_if) 2649 { 2650 uint16_t reg; 2651 int i; 2652 2653 DPRINTFN(1, ("sk_init_yukon: start\n")); 2654 sk_unreset_yukon(sc_if); 2655 2656 /* unused read of the interrupt source register */ 2657 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2658 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2659 2660 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2661 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2662 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2663 2664 /* MIB Counter Clear Mode set */ 2665 reg |= YU_PAR_MIB_CLR; 2666 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2667 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2668 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2669 2670 /* MIB Counter Clear Mode clear */ 2671 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2672 reg &= ~YU_PAR_MIB_CLR; 2673 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2674 2675 /* receive control reg */ 2676 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2677 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2678 YU_RCR_CRCR); 2679 2680 /* transmit parameter register */ 2681 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2682 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2683 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a)); 2684 2685 /* serial mode register */ 2686 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2687 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2688 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2689 YU_SMR_IPG_DATA(0x1e)); 2690 2691 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2692 /* Setup Yukon's address */ 2693 for (i = 0; i < 3; i++) { 2694 /* Write Source Address 1 (unicast filter) */ 2695 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2696 sc_if->sk_enaddr[i * 2] | 2697 sc_if->sk_enaddr[i * 2 + 1] << 8); 2698 } 2699 2700 for (i = 0; i < 3; i++) { 2701 reg = sk_win_read_2(sc_if->sk_softc, 2702 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2703 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2704 } 2705 2706 /* Set multicast filter */ 2707 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2708 sk_setmulti(sc_if); 2709 2710 /* enable interrupt mask for counter overflows */ 2711 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2712 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2713 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2714 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2715 2716 /* Configure RX MAC FIFO */ 2717 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2718 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2719 2720 /* Configure TX MAC FIFO */ 2721 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2722 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2723 2724 DPRINTFN(6, ("sk_init_yukon: end\n")); 2725 } 2726 2727 /* 2728 * Note that to properly initialize any part of the GEnesis chip, 2729 * you first have to take it out of reset mode. 2730 */ 2731 int 2732 sk_init(struct ifnet *ifp) 2733 { 2734 struct sk_if_softc *sc_if = ifp->if_softc; 2735 struct sk_softc *sc = sc_if->sk_softc; 2736 struct mii_data *mii = &sc_if->sk_mii; 2737 int rc = 0, s; 2738 uint32_t imr, imtimer_ticks; 2739 2740 DPRINTFN(1, ("sk_init\n")); 2741 2742 s = splnet(); 2743 2744 if (ifp->if_flags & IFF_RUNNING) { 2745 splx(s); 2746 return 0; 2747 } 2748 2749 /* Cancel pending I/O and free all RX/TX buffers. */ 2750 sk_stop(ifp, 0); 2751 2752 if (sc->sk_type == SK_GENESIS) { 2753 /* Configure LINK_SYNC LED */ 2754 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2755 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2756 SK_LINKLED_LINKSYNC_ON); 2757 2758 /* Configure RX LED */ 2759 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2760 SK_RXLEDCTL_COUNTER_START); 2761 2762 /* Configure TX LED */ 2763 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2764 SK_TXLEDCTL_COUNTER_START); 2765 } 2766 2767 /* Configure I2C registers */ 2768 2769 /* Configure XMAC(s) */ 2770 switch (sc->sk_type) { 2771 case SK_GENESIS: 2772 sk_init_xmac(sc_if); 2773 break; 2774 case SK_YUKON: 2775 case SK_YUKON_LITE: 2776 case SK_YUKON_LP: 2777 sk_init_yukon(sc_if); 2778 break; 2779 } 2780 if ((rc = mii_mediachg(mii)) == ENXIO) 2781 rc = 0; 2782 else if (rc != 0) 2783 goto out; 2784 2785 if (sc->sk_type == SK_GENESIS) { 2786 /* Configure MAC FIFOs */ 2787 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2788 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2789 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2790 2791 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2792 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2793 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2794 } 2795 2796 /* Configure transmit arbiter(s) */ 2797 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2798 SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON); 2799 2800 /* Configure RAMbuffers */ 2801 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2802 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2803 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2804 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2805 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2806 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2807 2808 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2809 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2810 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2811 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2812 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2813 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2814 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2815 2816 /* Configure BMUs */ 2817 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2818 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2819 SK_RX_RING_ADDR(sc_if, 0)); 2820 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2821 2822 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2823 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2824 SK_TX_RING_ADDR(sc_if, 0)); 2825 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2826 2827 /* Init descriptors */ 2828 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2829 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2830 "memory for rx buffers\n"); 2831 sk_stop(ifp, 0); 2832 splx(s); 2833 return ENOBUFS; 2834 } 2835 2836 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2837 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2838 "memory for tx buffers\n"); 2839 sk_stop(ifp, 0); 2840 splx(s); 2841 return ENOBUFS; 2842 } 2843 2844 /* Set interrupt moderation if changed via sysctl. */ 2845 switch (sc->sk_type) { 2846 case SK_GENESIS: 2847 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2848 break; 2849 case SK_YUKON_EC: 2850 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2851 break; 2852 default: 2853 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2854 } 2855 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2856 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2857 sk_win_write_4(sc, SK_IMTIMERINIT, 2858 SK_IM_USECS(sc->sk_int_mod)); 2859 aprint_verbose_dev(sc->sk_dev, 2860 "interrupt moderation is %d us\n", sc->sk_int_mod); 2861 } 2862 2863 /* Configure interrupt handling */ 2864 CSR_READ_4(sc, SK_ISSR); 2865 if (sc_if->sk_port == SK_PORT_A) 2866 sc->sk_intrmask |= SK_INTRS1; 2867 else 2868 sc->sk_intrmask |= SK_INTRS2; 2869 2870 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2871 2872 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2873 2874 /* Start BMUs. */ 2875 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2876 2877 if (sc->sk_type == SK_GENESIS) { 2878 /* Enable XMACs TX and RX state machines */ 2879 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2880 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2881 XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB); 2882 } 2883 2884 if (SK_YUKON_FAMILY(sc->sk_type)) { 2885 uint16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2886 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2887 #if 0 2888 /* XXX disable 100Mbps and full duplex mode? */ 2889 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN); 2890 #endif 2891 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2892 } 2893 2894 2895 ifp->if_flags |= IFF_RUNNING; 2896 ifp->if_flags &= ~IFF_OACTIVE; 2897 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2898 2899 out: 2900 splx(s); 2901 return rc; 2902 } 2903 2904 void 2905 sk_stop(struct ifnet *ifp, int disable) 2906 { 2907 struct sk_if_softc *sc_if = ifp->if_softc; 2908 struct sk_softc *sc = sc_if->sk_softc; 2909 int i; 2910 2911 DPRINTFN(1, ("sk_stop\n")); 2912 2913 callout_stop(&sc_if->sk_tick_ch); 2914 2915 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2916 uint32_t val; 2917 2918 /* Put PHY back into reset. */ 2919 val = sk_win_read_4(sc, SK_GPIO); 2920 if (sc_if->sk_port == SK_PORT_A) { 2921 val |= SK_GPIO_DIR0; 2922 val &= ~SK_GPIO_DAT0; 2923 } else { 2924 val |= SK_GPIO_DIR2; 2925 val &= ~SK_GPIO_DAT2; 2926 } 2927 sk_win_write_4(sc, SK_GPIO, val); 2928 } 2929 2930 /* Turn off various components of this interface. */ 2931 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2932 switch (sc->sk_type) { 2933 case SK_GENESIS: 2934 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2935 SK_TXMACCTL_XMAC_RESET); 2936 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2937 break; 2938 case SK_YUKON: 2939 case SK_YUKON_LITE: 2940 case SK_YUKON_LP: 2941 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2942 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2943 break; 2944 } 2945 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2946 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET |SK_RBCTL_OFF); 2947 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2948 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2949 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2950 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2951 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2952 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2953 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2954 2955 /* Disable interrupts */ 2956 if (sc_if->sk_port == SK_PORT_A) 2957 sc->sk_intrmask &= ~SK_INTRS1; 2958 else 2959 sc->sk_intrmask &= ~SK_INTRS2; 2960 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2961 2962 SK_XM_READ_2(sc_if, XM_ISR); 2963 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2964 2965 /* Free RX and TX mbufs still in the queues. */ 2966 for (i = 0; i < SK_RX_RING_CNT; i++) { 2967 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2968 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2969 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2970 } 2971 } 2972 2973 for (i = 0; i < SK_TX_RING_CNT; i++) { 2974 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2975 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2976 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2977 } 2978 } 2979 2980 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2981 } 2982 2983 /* Power Management Framework */ 2984 2985 static bool 2986 skc_suspend(device_t dv, const pmf_qual_t *qual) 2987 { 2988 struct sk_softc *sc = device_private(dv); 2989 2990 DPRINTFN(2, ("skc_suspend\n")); 2991 2992 /* Turn off the driver is loaded LED */ 2993 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2994 2995 return true; 2996 } 2997 2998 static bool 2999 skc_resume(device_t dv, const pmf_qual_t *qual) 3000 { 3001 struct sk_softc *sc = device_private(dv); 3002 3003 DPRINTFN(2, ("skc_resume\n")); 3004 3005 sk_reset(sc); 3006 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 3007 3008 return true; 3009 } 3010 3011 static bool 3012 sk_resume(device_t dv, const pmf_qual_t *qual) 3013 { 3014 struct sk_if_softc *sc_if = device_private(dv); 3015 3016 sk_init_yukon(sc_if); 3017 return true; 3018 } 3019 3020 CFATTACH_DECL_NEW(skc, sizeof(struct sk_softc), 3021 skc_probe, skc_attach, NULL, NULL); 3022 3023 CFATTACH_DECL_NEW(sk, sizeof(struct sk_if_softc), 3024 sk_probe, sk_attach, NULL, NULL); 3025 3026 #ifdef SK_DEBUG 3027 void 3028 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 3029 { 3030 #define DESC_PRINT(X) \ 3031 if (X) \ 3032 printf("txdesc[%d]." #X "=%#x\n", \ 3033 idx, X); 3034 3035 DESC_PRINT(le32toh(desc->sk_ctl)); 3036 DESC_PRINT(le32toh(desc->sk_next)); 3037 DESC_PRINT(le32toh(desc->sk_data_lo)); 3038 DESC_PRINT(le32toh(desc->sk_data_hi)); 3039 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 3040 DESC_PRINT(le16toh(desc->sk_rsvd0)); 3041 DESC_PRINT(le16toh(desc->sk_csum_startval)); 3042 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 3043 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 3044 DESC_PRINT(le16toh(desc->sk_rsvd1)); 3045 #undef PRINT 3046 } 3047 3048 void 3049 sk_dump_bytes(const char *data, int len) 3050 { 3051 int c, i, j; 3052 3053 for (i = 0; i < len; i += 16) { 3054 printf("%08x ", i); 3055 c = len - i; 3056 if (c > 16) c = 16; 3057 3058 for (j = 0; j < c; j++) { 3059 printf("%02x ", data[i + j] & 0xff); 3060 if ((j & 0xf) == 7 && j > 0) 3061 printf(" "); 3062 } 3063 3064 for (; j < 16; j++) 3065 printf(" "); 3066 printf(" "); 3067 3068 for (j = 0; j < c; j++) { 3069 int ch = data[i + j] & 0xff; 3070 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 3071 } 3072 3073 printf("\n"); 3074 3075 if (c < 16) 3076 break; 3077 } 3078 } 3079 3080 void 3081 sk_dump_mbuf(struct mbuf *m) 3082 { 3083 int count = m->m_pkthdr.len; 3084 3085 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3086 3087 while (count > 0 && m) { 3088 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3089 m, m->m_data, m->m_len); 3090 sk_dump_bytes(mtod(m, char *), m->m_len); 3091 3092 count -= m->m_len; 3093 m = m->m_next; 3094 } 3095 } 3096 #endif 3097 3098 static int 3099 sk_sysctl_handler(SYSCTLFN_ARGS) 3100 { 3101 int error, t; 3102 struct sysctlnode node; 3103 struct sk_softc *sc; 3104 3105 node = *rnode; 3106 sc = node.sysctl_data; 3107 t = sc->sk_int_mod; 3108 node.sysctl_data = &t; 3109 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3110 if (error || newp == NULL) 3111 return error; 3112 3113 if (t < SK_IM_MIN || t > SK_IM_MAX) 3114 return EINVAL; 3115 3116 /* update the softc with sysctl-changed value, and mark 3117 for hardware update */ 3118 sc->sk_int_mod = t; 3119 sc->sk_int_mod_pending = 1; 3120 return 0; 3121 } 3122 3123 /* 3124 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3125 * set up in skc_attach() 3126 */ 3127 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3128 { 3129 int rc; 3130 const struct sysctlnode *node; 3131 3132 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3133 0, CTLTYPE_NODE, "sk", 3134 SYSCTL_DESCR("sk interface controls"), 3135 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3136 goto err; 3137 } 3138 3139 sk_root_num = node->sysctl_num; 3140 return; 3141 3142 err: 3143 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3144 } 3145
Indexes created Tue Sep 23 07:09:52 GMT 2025