if_sk.c revision 1.106
1 /* $NetBSD: if_sk.c,v 1.106 2020/07/02 09:07:10 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */ 30 31 /* 32 * Copyright (c) 1997, 1998, 1999, 2000 33 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 3. All advertising materials mentioning features or use of this software 44 * must display the following acknowledgement: 45 * This product includes software developed by Bill Paul. 46 * 4. Neither the name of the author nor the names of any co-contributors 47 * may be used to endorse or promote products derived from this software 48 * without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 51 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 53 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 60 * THE POSSIBILITY OF SUCH DAMAGE. 61 * 62 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 63 */ 64 65 /* 66 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 67 * 68 * Permission to use, copy, modify, and distribute this software for any 69 * purpose with or without fee is hereby granted, provided that the above 70 * copyright notice and this permission notice appear in all copies. 71 * 72 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 73 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 74 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 75 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 76 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 77 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 78 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 79 */ 80 81 /* 82 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 83 * the SK-984x series adapters, both single port and dual port. 84 * References: 85 * The XaQti XMAC II datasheet, 86 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 87 * The SysKonnect GEnesis manual, http://www.syskonnect.com 88 * 89 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 90 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 91 * convenience to others until Vitesse corrects this problem: 92 * 93 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * 95 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 96 * Department of Electrical Engineering 97 * Columbia University, New York City 98 */ 99 100 /* 101 * The SysKonnect gigabit ethernet adapters consist of two main 102 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 103 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 104 * components and a PHY while the GEnesis controller provides a PCI 105 * interface with DMA support. Each card may have between 512K and 106 * 2MB of SRAM on board depending on the configuration. 107 * 108 * The SysKonnect GEnesis controller can have either one or two XMAC 109 * chips connected to it, allowing single or dual port NIC configurations. 110 * SysKonnect has the distinction of being the only vendor on the market 111 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 112 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 113 * XMAC registers. This driver takes advantage of these features to allow 114 * both XMACs to operate as independent interfaces. 115 */ 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: if_sk.c,v 1.106 2020/07/02 09:07:10 msaitoh Exp $"); 119 120 #include <sys/param.h> 121 #include <sys/systm.h> 122 #include <sys/sockio.h> 123 #include <sys/mbuf.h> 124 #include <sys/malloc.h> 125 #include <sys/mutex.h> 126 #include <sys/kernel.h> 127 #include <sys/socket.h> 128 #include <sys/device.h> 129 #include <sys/queue.h> 130 #include <sys/callout.h> 131 #include <sys/sysctl.h> 132 #include <sys/endian.h> 133 134 #include <net/if.h> 135 #include <net/if_dl.h> 136 #include <net/if_types.h> 137 138 #include <net/if_media.h> 139 140 #include <net/bpf.h> 141 #include <sys/rndsource.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 #include <dev/mii/brgphyreg.h> 146 147 #include <dev/pci/pcireg.h> 148 #include <dev/pci/pcivar.h> 149 #include <dev/pci/pcidevs.h> 150 151 /* #define SK_USEIOSPACE */ 152 153 #include <dev/pci/if_skreg.h> 154 #include <dev/pci/if_skvar.h> 155 156 static int skc_probe(device_t, cfdata_t, void *); 157 static void skc_attach(device_t, device_t, void *); 158 static int sk_probe(device_t, cfdata_t, void *); 159 static void sk_attach(device_t, device_t, void *); 160 static int skcprint(void *, const char *); 161 static int sk_intr(void *); 162 static void sk_intr_bcom(struct sk_if_softc *); 163 static void sk_intr_xmac(struct sk_if_softc *); 164 static void sk_intr_yukon(struct sk_if_softc *); 165 static void sk_rxeof(struct sk_if_softc *); 166 static void sk_txeof(struct sk_if_softc *); 167 static int sk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *); 168 static void sk_start(struct ifnet *); 169 static int sk_ioctl(struct ifnet *, u_long, void *); 170 static int sk_init(struct ifnet *); 171 static void sk_unreset_xmac(struct sk_if_softc *); 172 static void sk_init_xmac(struct sk_if_softc *); 173 static void sk_unreset_yukon(struct sk_if_softc *); 174 static void sk_init_yukon(struct sk_if_softc *); 175 static void sk_stop(struct ifnet *, int); 176 static void sk_watchdog(struct ifnet *); 177 static int sk_ifmedia_upd(struct ifnet *); 178 static void sk_reset(struct sk_softc *); 179 static int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 180 static int sk_alloc_jumbo_mem(struct sk_if_softc *); 181 static void *sk_jalloc(struct sk_if_softc *); 182 static void sk_jfree(struct mbuf *, void *, size_t, void *); 183 static int sk_init_rx_ring(struct sk_if_softc *); 184 static int sk_init_tx_ring(struct sk_if_softc *); 185 static uint8_t sk_vpd_readbyte(struct sk_softc *, int); 186 static void sk_vpd_read_res(struct sk_softc *, struct vpd_res *, int); 187 static void sk_vpd_read(struct sk_softc *); 188 189 static void sk_update_int_mod(struct sk_softc *); 190 191 static int sk_xmac_miibus_readreg(device_t, int, int, uint16_t *); 192 static int sk_xmac_miibus_writereg(device_t, int, int, uint16_t); 193 static void sk_xmac_miibus_statchg(struct ifnet *); 194 195 static int sk_marv_miibus_readreg(device_t, int, int, uint16_t *); 196 static int sk_marv_miibus_writereg(device_t, int, int, uint16_t); 197 static void sk_marv_miibus_statchg(struct ifnet *); 198 199 static uint32_t sk_xmac_hash(void *); 200 static uint32_t sk_yukon_hash(void *); 201 static void sk_setfilt(struct sk_if_softc *, void *, int); 202 static void sk_setmulti(struct sk_if_softc *); 203 static void sk_tick(void *); 204 205 static bool skc_suspend(device_t, const pmf_qual_t *); 206 static bool skc_resume(device_t, const pmf_qual_t *); 207 static bool sk_resume(device_t dv, const pmf_qual_t *); 208 209 /* #define SK_DEBUG 2 */ 210 #ifdef SK_DEBUG 211 #define DPRINTF(x) if (skdebug) printf x 212 #define DPRINTFN(n, x) if (skdebug >= (n)) printf x 213 int skdebug = SK_DEBUG; 214 215 static void sk_dump_txdesc(struct sk_tx_desc *, int); 216 static void sk_dump_mbuf(struct mbuf *); 217 static void sk_dump_bytes(const char *, int); 218 #else 219 #define DPRINTF(x) 220 #define DPRINTFN(n, x) 221 #endif 222 223 static int sk_sysctl_handler(SYSCTLFN_PROTO); 224 static int sk_root_num; 225 226 /* supported device vendors */ 227 /* PCI_PRODUCT_DLINK_DGE560T_2 might belong in if_msk instead */ 228 static const struct sk_product { 229 pci_vendor_id_t sk_vendor; 230 pci_product_id_t sk_product; 231 } sk_products[] = { 232 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 233 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 234 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 235 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 236 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 237 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 238 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET, }, 239 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN, }, 240 { 0, 0, } 241 }; 242 243 #define SK_LINKSYS_EG1032_SUBID 0x00151737 244 245 static inline uint32_t 246 sk_win_read_4(struct sk_softc *sc, uint32_t reg) 247 { 248 #ifdef SK_USEIOSPACE 249 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 250 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 251 #else 252 return CSR_READ_4(sc, reg); 253 #endif 254 } 255 256 static inline uint16_t 257 sk_win_read_2(struct sk_softc *sc, uint32_t reg) 258 { 259 #ifdef SK_USEIOSPACE 260 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 261 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 262 #else 263 return CSR_READ_2(sc, reg); 264 #endif 265 } 266 267 static inline uint8_t 268 sk_win_read_1(struct sk_softc *sc, uint32_t reg) 269 { 270 #ifdef SK_USEIOSPACE 271 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 272 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 273 #else 274 return CSR_READ_1(sc, reg); 275 #endif 276 } 277 278 static inline void 279 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x) 280 { 281 #ifdef SK_USEIOSPACE 282 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 283 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 284 #else 285 CSR_WRITE_4(sc, reg, x); 286 #endif 287 } 288 289 static inline void 290 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x) 291 { 292 #ifdef SK_USEIOSPACE 293 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 294 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 295 #else 296 CSR_WRITE_2(sc, reg, x); 297 #endif 298 } 299 300 static inline void 301 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x) 302 { 303 #ifdef SK_USEIOSPACE 304 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 305 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 306 #else 307 CSR_WRITE_1(sc, reg, x); 308 #endif 309 } 310 311 /* 312 * The VPD EEPROM contains Vital Product Data, as suggested in 313 * the PCI 2.1 specification. The VPD data is separared into areas 314 * denoted by resource IDs. The SysKonnect VPD contains an ID string 315 * resource (the name of the adapter), a read-only area resource 316 * containing various key/data fields and a read/write area which 317 * can be used to store asset management information or log messages. 318 * We read the ID string and read-only into buffers attached to 319 * the controller softc structure for later use. At the moment, 320 * we only use the ID string during sk_attach(). 321 */ 322 static uint8_t 323 sk_vpd_readbyte(struct sk_softc *sc, int addr) 324 { 325 int i; 326 327 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 328 for (i = 0; i < SK_TIMEOUT; i++) { 329 DELAY(1); 330 if (sk_win_read_2(sc, 331 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 332 break; 333 } 334 335 if (i == SK_TIMEOUT) 336 return 0; 337 338 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)); 339 } 340 341 static void 342 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 343 { 344 int i; 345 uint8_t *ptr; 346 347 ptr = (uint8_t *)res; 348 for (i = 0; i < sizeof(struct vpd_res); i++) 349 ptr[i] = sk_vpd_readbyte(sc, i + addr); 350 } 351 352 static void 353 sk_vpd_read(struct sk_softc *sc) 354 { 355 int pos = 0, i; 356 struct vpd_res res; 357 358 if (sc->sk_vpd_prodname != NULL) 359 free(sc->sk_vpd_prodname, M_DEVBUF); 360 if (sc->sk_vpd_readonly != NULL) 361 free(sc->sk_vpd_readonly, M_DEVBUF); 362 sc->sk_vpd_prodname = NULL; 363 sc->sk_vpd_readonly = NULL; 364 365 sk_vpd_read_res(sc, &res, pos); 366 367 if (res.vr_id != VPD_RES_ID) { 368 aprint_error_dev(sc->sk_dev, 369 "bad VPD resource id: expected %x got %x\n", 370 VPD_RES_ID, res.vr_id); 371 return; 372 } 373 374 pos += sizeof(res); 375 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_WAITOK); 376 for (i = 0; i < res.vr_len; i++) 377 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 378 sc->sk_vpd_prodname[i] = '\0'; 379 pos += i; 380 381 sk_vpd_read_res(sc, &res, pos); 382 383 if (res.vr_id != VPD_RES_READ) { 384 aprint_error_dev(sc->sk_dev, 385 "bad VPD resource id: expected %x got %x\n", 386 VPD_RES_READ, res.vr_id); 387 return; 388 } 389 390 pos += sizeof(res); 391 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_WAITOK); 392 for (i = 0; i < res.vr_len ; i++) 393 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 394 } 395 396 static int 397 sk_xmac_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 398 { 399 struct sk_if_softc *sc_if = device_private(dev); 400 int i; 401 402 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 403 404 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 405 return -1; 406 407 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 408 SK_XM_READ_2(sc_if, XM_PHY_DATA); 409 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 410 for (i = 0; i < SK_TIMEOUT; i++) { 411 DELAY(1); 412 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 413 XM_MMUCMD_PHYDATARDY) 414 break; 415 } 416 417 if (i == SK_TIMEOUT) { 418 aprint_error_dev(sc_if->sk_dev, 419 "phy failed to come ready\n"); 420 return ETIMEDOUT; 421 } 422 } 423 DELAY(1); 424 *val = SK_XM_READ_2(sc_if, XM_PHY_DATA); 425 return 0; 426 } 427 428 static int 429 sk_xmac_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 430 { 431 struct sk_if_softc *sc_if = device_private(dev); 432 int i; 433 434 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 435 436 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 437 for (i = 0; i < SK_TIMEOUT; i++) { 438 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 439 break; 440 } 441 442 if (i == SK_TIMEOUT) { 443 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 444 return ETIMEDOUT; 445 } 446 447 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 448 for (i = 0; i < SK_TIMEOUT; i++) { 449 DELAY(1); 450 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 451 break; 452 } 453 454 if (i == SK_TIMEOUT) { 455 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n"); 456 return ETIMEDOUT; 457 } 458 459 return 0; 460 } 461 462 static void 463 sk_xmac_miibus_statchg(struct ifnet *ifp) 464 { 465 struct sk_if_softc *sc_if = ifp->if_softc; 466 struct mii_data *mii = &sc_if->sk_mii; 467 468 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 469 470 /* 471 * If this is a GMII PHY, manually set the XMAC's 472 * duplex mode accordingly. 473 */ 474 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 475 if ((mii->mii_media_active & IFM_FDX) != 0) 476 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 477 else 478 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 479 } 480 } 481 482 static int 483 sk_marv_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 484 { 485 struct sk_if_softc *sc_if = device_private(dev); 486 uint16_t data; 487 int i; 488 489 if (phy != 0 || 490 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 491 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 492 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 493 phy, reg)); 494 return -1; 495 } 496 497 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 498 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 499 500 for (i = 0; i < SK_TIMEOUT; i++) { 501 DELAY(1); 502 data = SK_YU_READ_2(sc_if, YUKON_SMICR); 503 if (data & YU_SMICR_READ_VALID) 504 break; 505 } 506 507 if (i == SK_TIMEOUT) { 508 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n"); 509 return ETIMEDOUT; 510 } 511 512 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 513 SK_TIMEOUT)); 514 515 *val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 516 517 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#hx\n", 518 phy, reg, *val)); 519 520 return 0; 521 } 522 523 static int 524 sk_marv_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 525 { 526 struct sk_if_softc *sc_if = device_private(dev); 527 int i; 528 529 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#hx\n", 530 phy, reg, val)); 531 532 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 533 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 534 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 535 536 for (i = 0; i < SK_TIMEOUT; i++) { 537 DELAY(1); 538 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)) 539 break; 540 } 541 542 if (i == SK_TIMEOUT) { 543 printf("%s: phy write timed out\n", 544 device_xname(sc_if->sk_dev)); 545 return ETIMEDOUT; 546 } 547 548 return 0; 549 } 550 551 static void 552 sk_marv_miibus_statchg(struct ifnet *ifp) 553 { 554 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 555 SK_YU_READ_2(((struct sk_if_softc *)ifp->if_softc), 556 YUKON_GPCR))); 557 } 558 559 static uint32_t 560 sk_xmac_hash(void *addr) 561 { 562 uint32_t crc; 563 564 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 565 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 566 DPRINTFN(2,("multicast hash for %s is %x\n", ether_sprintf(addr),crc)); 567 return crc; 568 } 569 570 static uint32_t 571 sk_yukon_hash(void *addr) 572 { 573 uint32_t crc; 574 575 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 576 crc &= ((1 << SK_HASH_BITS) - 1); 577 DPRINTFN(2,("multicast hash for %s is %x\n", ether_sprintf(addr),crc)); 578 return crc; 579 } 580 581 static void 582 sk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot) 583 { 584 char *addr = addrv; 585 int base = XM_RXFILT_ENTRY(slot); 586 587 SK_XM_WRITE_2(sc_if, base, *(uint16_t *)(&addr[0])); 588 SK_XM_WRITE_2(sc_if, base + 2, *(uint16_t *)(&addr[2])); 589 SK_XM_WRITE_2(sc_if, base + 4, *(uint16_t *)(&addr[4])); 590 } 591 592 static void 593 sk_setmulti(struct sk_if_softc *sc_if) 594 { 595 struct sk_softc *sc = sc_if->sk_softc; 596 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 597 uint32_t hashes[2] = { 0, 0 }; 598 int h = 0, i; 599 struct ethercom *ec = &sc_if->sk_ethercom; 600 struct ether_multi *enm; 601 struct ether_multistep step; 602 uint8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; 603 604 /* First, zot all the existing filters. */ 605 switch (sc->sk_type) { 606 case SK_GENESIS: 607 for (i = 1; i < XM_RXFILT_MAX; i++) 608 sk_setfilt(sc_if, (void *)&dummy, i); 609 610 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 611 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 612 break; 613 case SK_YUKON: 614 case SK_YUKON_LITE: 615 case SK_YUKON_LP: 616 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 617 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 618 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 619 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 620 break; 621 } 622 623 /* Now program new ones. */ 624 allmulti: 625 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 626 hashes[0] = 0xFFFFFFFF; 627 hashes[1] = 0xFFFFFFFF; 628 } else { 629 i = 1; 630 /* First find the tail of the list. */ 631 ETHER_LOCK(ec); 632 ETHER_FIRST_MULTI(step, ec, enm); 633 while (enm != NULL) { 634 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 635 ETHER_ADDR_LEN)) { 636 ifp->if_flags |= IFF_ALLMULTI; 637 ETHER_UNLOCK(ec); 638 goto allmulti; 639 } 640 DPRINTFN(2,("multicast address %s\n", 641 ether_sprintf(enm->enm_addrlo))); 642 /* 643 * Program the first XM_RXFILT_MAX multicast groups 644 * into the perfect filter. For all others, 645 * use the hash table. 646 */ 647 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 648 sk_setfilt(sc_if, enm->enm_addrlo, i); 649 i++; 650 } 651 else { 652 switch (sc->sk_type) { 653 case SK_GENESIS: 654 h = sk_xmac_hash(enm->enm_addrlo); 655 break; 656 case SK_YUKON: 657 case SK_YUKON_LITE: 658 case SK_YUKON_LP: 659 h = sk_yukon_hash(enm->enm_addrlo); 660 break; 661 } 662 if (h < 32) 663 hashes[0] |= (1 << h); 664 else 665 hashes[1] |= (1 << (h - 32)); 666 } 667 668 ETHER_NEXT_MULTI(step, enm); 669 } 670 ETHER_UNLOCK(ec); 671 } 672 673 switch (sc->sk_type) { 674 case SK_GENESIS: 675 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH | 676 XM_MODE_RX_USE_PERFECT); 677 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 678 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 679 break; 680 case SK_YUKON: 681 case SK_YUKON_LITE: 682 case SK_YUKON_LP: 683 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 684 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 685 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 686 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 687 break; 688 } 689 } 690 691 static int 692 sk_init_rx_ring(struct sk_if_softc *sc_if) 693 { 694 struct sk_chain_data *cd = &sc_if->sk_cdata; 695 struct sk_ring_data *rd = sc_if->sk_rdata; 696 int i; 697 698 memset((char *)rd->sk_rx_ring, 0, 699 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 700 701 for (i = 0; i < SK_RX_RING_CNT; i++) { 702 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 703 if (i == (SK_RX_RING_CNT - 1)) { 704 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 705 rd->sk_rx_ring[i].sk_next = 706 htole32(SK_RX_RING_ADDR(sc_if, 0)); 707 } else { 708 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 709 rd->sk_rx_ring[i].sk_next = 710 htole32(SK_RX_RING_ADDR(sc_if, i+1)); 711 } 712 } 713 714 for (i = 0; i < SK_RX_RING_CNT; i++) { 715 if (sk_newbuf(sc_if, i, NULL, 716 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) { 717 aprint_error_dev(sc_if->sk_dev, 718 "failed alloc of %dth mbuf\n", i); 719 return ENOBUFS; 720 } 721 } 722 sc_if->sk_cdata.sk_rx_prod = 0; 723 sc_if->sk_cdata.sk_rx_cons = 0; 724 725 return 0; 726 } 727 728 static int 729 sk_init_tx_ring(struct sk_if_softc *sc_if) 730 { 731 struct sk_chain_data *cd = &sc_if->sk_cdata; 732 struct sk_ring_data *rd = sc_if->sk_rdata; 733 int i; 734 735 memset(sc_if->sk_rdata->sk_tx_ring, 0, 736 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 737 738 for (i = 0; i < SK_TX_RING_CNT; i++) { 739 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 740 if (i == (SK_TX_RING_CNT - 1)) { 741 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 742 rd->sk_tx_ring[i].sk_next = 743 htole32(SK_TX_RING_ADDR(sc_if, 0)); 744 } else { 745 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 746 rd->sk_tx_ring[i].sk_next = 747 htole32(SK_TX_RING_ADDR(sc_if, i+1)); 748 } 749 } 750 751 sc_if->sk_cdata.sk_tx_prod = 0; 752 sc_if->sk_cdata.sk_tx_cons = 0; 753 sc_if->sk_cdata.sk_tx_cnt = 0; 754 755 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 756 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 757 758 return 0; 759 } 760 761 static int 762 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 763 bus_dmamap_t dmamap) 764 { 765 struct mbuf *m_new = NULL; 766 struct sk_chain *c; 767 struct sk_rx_desc *r; 768 769 if (m == NULL) { 770 void *buf = NULL; 771 772 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 773 if (m_new == NULL) { 774 aprint_error_dev(sc_if->sk_dev, 775 "no memory for rx list -- packet dropped!\n"); 776 return ENOBUFS; 777 } 778 779 /* Allocate the jumbo buffer */ 780 buf = sk_jalloc(sc_if); 781 if (buf == NULL) { 782 m_freem(m_new); 783 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 784 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname)); 785 return ENOBUFS; 786 } 787 788 /* Attach the buffer to the mbuf */ 789 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 790 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if); 791 792 } else { 793 /* 794 * We're re-using a previously allocated mbuf; 795 * be sure to re-init pointers and lengths to 796 * default values. 797 */ 798 m_new = m; 799 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN; 800 m_new->m_data = m_new->m_ext.ext_buf; 801 } 802 m_adj(m_new, ETHER_ALIGN); 803 804 c = &sc_if->sk_cdata.sk_rx_chain[i]; 805 r = c->sk_desc; 806 c->sk_mbuf = m_new; 807 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr + 808 (((vaddr_t)m_new->m_data 809 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf))); 810 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT); 811 812 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 813 814 return 0; 815 } 816 817 /* 818 * Memory management for jumbo frames. 819 */ 820 821 static int 822 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if) 823 { 824 struct sk_softc *sc = sc_if->sk_softc; 825 char *ptr, *kva; 826 bus_dma_segment_t seg; 827 int i, rseg, state, error; 828 struct sk_jpool_entry *entry; 829 830 state = error = 0; 831 832 /* Grab a big chunk o' storage. */ 833 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0, 834 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 835 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 836 return ENOBUFS; 837 } 838 839 state = 1; 840 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, (void **)&kva, 841 BUS_DMA_NOWAIT)) { 842 aprint_error_dev(sc->sk_dev, 843 "can't map dma buffers (%d bytes)\n", 844 SK_JMEM); 845 error = ENOBUFS; 846 goto out; 847 } 848 849 state = 2; 850 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0, 851 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) { 852 aprint_error_dev(sc->sk_dev, "can't create dma map\n"); 853 error = ENOBUFS; 854 goto out; 855 } 856 857 state = 3; 858 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map, 859 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) { 860 aprint_error_dev(sc->sk_dev, "can't load dma map\n"); 861 error = ENOBUFS; 862 goto out; 863 } 864 865 state = 4; 866 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva; 867 DPRINTFN(1,("sk_jumbo_buf = %p\n", sc_if->sk_cdata.sk_jumbo_buf)); 868 869 LIST_INIT(&sc_if->sk_jfree_listhead); 870 LIST_INIT(&sc_if->sk_jinuse_listhead); 871 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET); 872 873 /* 874 * Now divide it up into 9K pieces and save the addresses 875 * in an array. 876 */ 877 ptr = sc_if->sk_cdata.sk_jumbo_buf; 878 for (i = 0; i < SK_JSLOTS; i++) { 879 sc_if->sk_cdata.sk_jslots[i] = ptr; 880 ptr += SK_JLEN; 881 entry = malloc(sizeof(struct sk_jpool_entry), 882 M_DEVBUF, M_WAITOK); 883 entry->slot = i; 884 if (i) 885 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, 886 entry, jpool_entries); 887 else 888 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, 889 entry, jpool_entries); 890 } 891 out: 892 if (error != 0) { 893 switch (state) { 894 case 4: 895 bus_dmamap_unload(sc->sc_dmatag, 896 sc_if->sk_cdata.sk_rx_jumbo_map); 897 /* FALLTHROUGH */ 898 case 3: 899 bus_dmamap_destroy(sc->sc_dmatag, 900 sc_if->sk_cdata.sk_rx_jumbo_map); 901 /* FALLTHROUGH */ 902 case 2: 903 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM); 904 /* FALLTHROUGH */ 905 case 1: 906 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 907 break; 908 default: 909 break; 910 } 911 } 912 913 return error; 914 } 915 916 /* 917 * Allocate a jumbo buffer. 918 */ 919 static void * 920 sk_jalloc(struct sk_if_softc *sc_if) 921 { 922 struct sk_jpool_entry *entry; 923 924 mutex_enter(&sc_if->sk_jpool_mtx); 925 entry = LIST_FIRST(&sc_if->sk_jfree_listhead); 926 927 if (entry == NULL) { 928 mutex_exit(&sc_if->sk_jpool_mtx); 929 return NULL; 930 } 931 932 LIST_REMOVE(entry, jpool_entries); 933 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries); 934 mutex_exit(&sc_if->sk_jpool_mtx); 935 return sc_if->sk_cdata.sk_jslots[entry->slot]; 936 } 937 938 /* 939 * Release a jumbo buffer. 940 */ 941 static void 942 sk_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 943 { 944 struct sk_jpool_entry *entry; 945 struct sk_if_softc *sc; 946 int i; 947 948 /* Extract the softc struct pointer. */ 949 sc = (struct sk_if_softc *)arg; 950 951 if (sc == NULL) 952 panic("sk_jfree: can't find softc pointer!"); 953 954 /* calculate the slot this buffer belongs to */ 955 956 i = ((vaddr_t)buf 957 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN; 958 959 if ((i < 0) || (i >= SK_JSLOTS)) 960 panic("sk_jfree: asked to free buffer that we don't manage!"); 961 962 mutex_enter(&sc->sk_jpool_mtx); 963 entry = LIST_FIRST(&sc->sk_jinuse_listhead); 964 if (entry == NULL) 965 panic("sk_jfree: buffer not in use!"); 966 entry->slot = i; 967 LIST_REMOVE(entry, jpool_entries); 968 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries); 969 mutex_exit(&sc->sk_jpool_mtx); 970 971 if (__predict_true(m != NULL)) 972 pool_cache_put(mb_cache, m); 973 } 974 975 /* 976 * Set media options. 977 */ 978 static int 979 sk_ifmedia_upd(struct ifnet *ifp) 980 { 981 struct sk_if_softc *sc_if = ifp->if_softc; 982 int rc; 983 984 (void) sk_init(ifp); 985 if ((rc = mii_mediachg(&sc_if->sk_mii)) == ENXIO) 986 return 0; 987 return rc; 988 } 989 990 static void 991 sk_promisc(struct sk_if_softc *sc_if, int on) 992 { 993 struct sk_softc *sc = sc_if->sk_softc; 994 switch (sc->sk_type) { 995 case SK_GENESIS: 996 if (on) 997 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 998 else 999 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 1000 break; 1001 case SK_YUKON: 1002 case SK_YUKON_LITE: 1003 case SK_YUKON_LP: 1004 if (on) 1005 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 1006 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1007 else 1008 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 1009 YU_RCR_UFLEN | YU_RCR_MUFLEN); 1010 break; 1011 default: 1012 aprint_error_dev(sc_if->sk_dev, "Can't set promisc for %d\n", 1013 sc->sk_type); 1014 break; 1015 } 1016 } 1017 1018 static int 1019 sk_ioctl(struct ifnet *ifp, u_long command, void *data) 1020 { 1021 struct sk_if_softc *sc_if = ifp->if_softc; 1022 int s, error = 0; 1023 1024 /* DPRINTFN(2, ("sk_ioctl\n")); */ 1025 1026 s = splnet(); 1027 1028 switch (command) { 1029 1030 case SIOCSIFFLAGS: 1031 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 1032 if ((error = ifioctl_common(ifp, command, data)) != 0) 1033 break; 1034 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 1035 case IFF_RUNNING: 1036 sk_stop(ifp, 1); 1037 break; 1038 case IFF_UP: 1039 sk_init(ifp); 1040 break; 1041 case IFF_UP | IFF_RUNNING: 1042 if ((ifp->if_flags ^ sc_if->sk_if_flags) == IFF_PROMISC) { 1043 sk_promisc(sc_if, ifp->if_flags & IFF_PROMISC); 1044 sk_setmulti(sc_if); 1045 } else 1046 sk_init(ifp); 1047 break; 1048 } 1049 sc_if->sk_if_flags = ifp->if_flags; 1050 error = 0; 1051 break; 1052 1053 default: 1054 DPRINTFN(2, ("sk_ioctl ETHER\n")); 1055 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1056 break; 1057 1058 error = 0; 1059 1060 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1061 ; 1062 else if (ifp->if_flags & IFF_RUNNING) { 1063 sk_setmulti(sc_if); 1064 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 1065 } 1066 break; 1067 } 1068 1069 splx(s); 1070 return error; 1071 } 1072 1073 static void 1074 sk_update_int_mod(struct sk_softc *sc) 1075 { 1076 uint32_t imtimer_ticks; 1077 1078 /* 1079 * Configure interrupt moderation. The moderation timer 1080 * defers interrupts specified in the interrupt moderation 1081 * timer mask based on the timeout specified in the interrupt 1082 * moderation timer init register. Each bit in the timer 1083 * register represents one tick, so to specify a timeout in 1084 * microseconds, we have to multiply by the correct number of 1085 * ticks-per-microsecond. 1086 */ 1087 switch (sc->sk_type) { 1088 case SK_GENESIS: 1089 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 1090 break; 1091 case SK_YUKON_EC: 1092 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 1093 break; 1094 default: 1095 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 1096 } 1097 aprint_verbose_dev(sc->sk_dev, "interrupt moderation is %d us\n", 1098 sc->sk_int_mod); 1099 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 1100 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF | SK_ISR_TX2_S_EOF | 1101 SK_ISR_RX1_EOF | SK_ISR_RX2_EOF); 1102 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1103 sc->sk_int_mod_pending = 0; 1104 } 1105 1106 /* 1107 * Lookup: Check the PCI vendor and device, and return a pointer to 1108 * The structure if the IDs match against our list. 1109 */ 1110 1111 static const struct sk_product * 1112 sk_lookup(const struct pci_attach_args *pa) 1113 { 1114 const struct sk_product *psk; 1115 1116 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1117 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1118 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1119 return psk; 1120 } 1121 return NULL; 1122 } 1123 1124 /* 1125 * Probe for a SysKonnect GEnesis chip. 1126 */ 1127 1128 static int 1129 skc_probe(device_t parent, cfdata_t match, void *aux) 1130 { 1131 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1132 const struct sk_product *psk; 1133 pcireg_t subid; 1134 1135 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1136 1137 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1138 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1139 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1140 subid == SK_LINKSYS_EG1032_SUBID) 1141 return 1; 1142 1143 if ((psk = sk_lookup(pa))) { 1144 return 1; 1145 } 1146 return 0; 1147 } 1148 1149 /* 1150 * Force the GEnesis into reset, then bring it out of reset. 1151 */ 1152 static void 1153 sk_reset(struct sk_softc *sc) 1154 { 1155 DPRINTFN(2, ("sk_reset\n")); 1156 1157 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1158 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1159 if (SK_YUKON_FAMILY(sc->sk_type)) 1160 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1161 1162 DELAY(1000); 1163 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1164 DELAY(2); 1165 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1166 if (SK_YUKON_FAMILY(sc->sk_type)) 1167 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1168 1169 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1170 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1171 CSR_READ_2(sc, SK_LINK_CTRL))); 1172 1173 if (sc->sk_type == SK_GENESIS) { 1174 /* Configure packet arbiter */ 1175 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1176 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1177 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1178 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1179 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1180 } 1181 1182 /* Enable RAM interface */ 1183 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1184 1185 sk_update_int_mod(sc); 1186 } 1187 1188 static int 1189 sk_probe(device_t parent, cfdata_t match, void *aux) 1190 { 1191 struct skc_attach_args *sa = aux; 1192 1193 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1194 return 0; 1195 1196 return 1; 1197 } 1198 1199 /* 1200 * Each XMAC chip is attached as a separate logical IP interface. 1201 * Single port cards will have only one logical interface of course. 1202 */ 1203 static void 1204 sk_attach(device_t parent, device_t self, void *aux) 1205 { 1206 struct sk_if_softc *sc_if = device_private(self); 1207 struct mii_data *mii = &sc_if->sk_mii; 1208 struct sk_softc *sc = device_private(parent); 1209 struct skc_attach_args *sa = aux; 1210 struct sk_txmap_entry *entry; 1211 struct ifnet *ifp; 1212 bus_dma_segment_t seg; 1213 bus_dmamap_t dmamap; 1214 prop_data_t data; 1215 void *kva; 1216 int i, rseg; 1217 int mii_flags = 0; 1218 1219 aprint_naive("\n"); 1220 1221 sc_if->sk_dev = self; 1222 sc_if->sk_port = sa->skc_port; 1223 sc_if->sk_softc = sc; 1224 sc->sk_if[sa->skc_port] = sc_if; 1225 1226 if (sa->skc_port == SK_PORT_A) 1227 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1228 if (sa->skc_port == SK_PORT_B) 1229 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1230 1231 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1232 1233 /* 1234 * Get station address for this interface. Note that 1235 * dual port cards actually come with three station 1236 * addresses: one for each port, plus an extra. The 1237 * extra one is used by the SysKonnect driver software 1238 * as a 'virtual' station address for when both ports 1239 * are operating in failover mode. Currently we don't 1240 * use this extra address. 1241 */ 1242 data = prop_dictionary_get(device_properties(self), "mac-address"); 1243 if (data != NULL) { 1244 /* 1245 * Try to get the station address from device properties 1246 * first, in case the ROM is missing. 1247 */ 1248 KASSERT(prop_object_type(data) == PROP_TYPE_DATA); 1249 KASSERT(prop_data_size(data) == ETHER_ADDR_LEN); 1250 memcpy(sc_if->sk_enaddr, prop_data_value(data), 1251 ETHER_ADDR_LEN); 1252 } else 1253 for (i = 0; i < ETHER_ADDR_LEN; i++) 1254 sc_if->sk_enaddr[i] = sk_win_read_1(sc, 1255 SK_MAC0_0 + (sa->skc_port * 8) + i); 1256 1257 aprint_normal(": Ethernet address %s\n", 1258 ether_sprintf(sc_if->sk_enaddr)); 1259 1260 /* 1261 * Set up RAM buffer addresses. The NIC will have a certain 1262 * amount of SRAM on it, somewhere between 512K and 2MB. We 1263 * need to divide this up a) between the transmitter and 1264 * receiver and b) between the two XMACs, if this is a 1265 * dual port NIC. Our algorithm is to divide up the memory 1266 * evenly so that everyone gets a fair share. 1267 */ 1268 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1269 uint32_t chunk, val; 1270 1271 chunk = sc->sk_ramsize / 2; 1272 val = sc->sk_rboff / sizeof(uint64_t); 1273 sc_if->sk_rx_ramstart = val; 1274 val += (chunk / sizeof(uint64_t)); 1275 sc_if->sk_rx_ramend = val - 1; 1276 sc_if->sk_tx_ramstart = val; 1277 val += (chunk / sizeof(uint64_t)); 1278 sc_if->sk_tx_ramend = val - 1; 1279 } else { 1280 uint32_t chunk, val; 1281 1282 chunk = sc->sk_ramsize / 4; 1283 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1284 sizeof(uint64_t); 1285 sc_if->sk_rx_ramstart = val; 1286 val += (chunk / sizeof(uint64_t)); 1287 sc_if->sk_rx_ramend = val - 1; 1288 sc_if->sk_tx_ramstart = val; 1289 val += (chunk / sizeof(uint64_t)); 1290 sc_if->sk_tx_ramend = val - 1; 1291 } 1292 1293 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1294 " tx_ramstart=%#x tx_ramend=%#x\n", 1295 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1296 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1297 1298 /* Read and save PHY type and set PHY address */ 1299 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1300 switch (sc_if->sk_phytype) { 1301 case SK_PHYTYPE_XMAC: 1302 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1303 break; 1304 case SK_PHYTYPE_BCOM: 1305 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1306 break; 1307 case SK_PHYTYPE_MARV_COPPER: 1308 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1309 break; 1310 default: 1311 aprint_error_dev(sc->sk_dev, "unsupported PHY type: %d\n", 1312 sc_if->sk_phytype); 1313 return; 1314 } 1315 1316 /* Allocate the descriptor queues. */ 1317 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1318 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1319 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n"); 1320 goto fail; 1321 } 1322 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1323 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1324 aprint_error_dev(sc_if->sk_dev, 1325 "can't map dma buffers (%lu bytes)\n", 1326 (u_long) sizeof(struct sk_ring_data)); 1327 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1328 goto fail; 1329 } 1330 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1331 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1332 &sc_if->sk_ring_map)) { 1333 aprint_error_dev(sc_if->sk_dev, "can't create dma map\n"); 1334 bus_dmamem_unmap(sc->sc_dmatag, kva, 1335 sizeof(struct sk_ring_data)); 1336 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1337 goto fail; 1338 } 1339 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1340 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1341 aprint_error_dev(sc_if->sk_dev, "can't load dma map\n"); 1342 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1343 bus_dmamem_unmap(sc->sc_dmatag, kva, 1344 sizeof(struct sk_ring_data)); 1345 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1346 goto fail; 1347 } 1348 1349 for (i = 0; i < SK_RX_RING_CNT; i++) 1350 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1351 1352 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1353 for (i = 0; i < SK_TX_RING_CNT; i++) { 1354 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1355 1356 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG, 1357 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) { 1358 aprint_error_dev(sc_if->sk_dev, 1359 "Can't create TX dmamap\n"); 1360 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1361 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1362 bus_dmamem_unmap(sc->sc_dmatag, kva, 1363 sizeof(struct sk_ring_data)); 1364 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1365 goto fail; 1366 } 1367 1368 entry = malloc(sizeof(*entry), M_DEVBUF, M_WAITOK); 1369 entry->dmamap = dmamap; 1370 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1371 } 1372 1373 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1374 memset(sc_if->sk_rdata, 0, sizeof(struct sk_ring_data)); 1375 1376 ifp = &sc_if->sk_ethercom.ec_if; 1377 /* Try to allocate memory for jumbo buffers. */ 1378 if (sk_alloc_jumbo_mem(sc_if)) { 1379 aprint_error("%s: jumbo buffer allocation failed\n", 1380 ifp->if_xname); 1381 goto fail; 1382 } 1383 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU 1384 | ETHERCAP_JUMBO_MTU; 1385 1386 ifp->if_softc = sc_if; 1387 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1388 ifp->if_ioctl = sk_ioctl; 1389 ifp->if_start = sk_start; 1390 ifp->if_stop = sk_stop; 1391 ifp->if_init = sk_init; 1392 ifp->if_watchdog = sk_watchdog; 1393 ifp->if_capabilities = 0; 1394 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1395 IFQ_SET_READY(&ifp->if_snd); 1396 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ); 1397 1398 /* 1399 * Do miibus setup. 1400 */ 1401 switch (sc->sk_type) { 1402 case SK_GENESIS: 1403 sk_unreset_xmac(sc_if); 1404 break; 1405 case SK_YUKON: 1406 case SK_YUKON_LITE: 1407 case SK_YUKON_LP: 1408 sk_unreset_yukon(sc_if); 1409 break; 1410 default: 1411 aprint_error_dev(sc->sk_dev, "unknown device type %d\n", 1412 sc->sk_type); 1413 goto fail; 1414 } 1415 1416 DPRINTFN(2, ("sk_attach: 1\n")); 1417 1418 mii->mii_ifp = ifp; 1419 switch (sc->sk_type) { 1420 case SK_GENESIS: 1421 mii->mii_readreg = sk_xmac_miibus_readreg; 1422 mii->mii_writereg = sk_xmac_miibus_writereg; 1423 mii->mii_statchg = sk_xmac_miibus_statchg; 1424 break; 1425 case SK_YUKON: 1426 case SK_YUKON_LITE: 1427 case SK_YUKON_LP: 1428 mii->mii_readreg = sk_marv_miibus_readreg; 1429 mii->mii_writereg = sk_marv_miibus_writereg; 1430 mii->mii_statchg = sk_marv_miibus_statchg; 1431 mii_flags = MIIF_DOPAUSE; 1432 break; 1433 } 1434 1435 sc_if->sk_ethercom.ec_mii = mii; 1436 ifmedia_init(&mii->mii_media, 0, sk_ifmedia_upd, ether_mediastatus); 1437 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 1438 MII_OFFSET_ANY, mii_flags); 1439 if (LIST_EMPTY(&mii->mii_phys)) { 1440 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n"); 1441 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 1442 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 1443 } else 1444 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1445 1446 callout_init(&sc_if->sk_tick_ch, 0); 1447 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 1448 1449 DPRINTFN(2, ("sk_attach: 1\n")); 1450 1451 /* 1452 * Call MI attach routines. 1453 */ 1454 if_attach(ifp); 1455 if_deferred_start_init(ifp, NULL); 1456 1457 ether_ifattach(ifp, sc_if->sk_enaddr); 1458 1459 if (sc->rnd_attached++ == 0) { 1460 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev), 1461 RND_TYPE_NET, RND_FLAG_DEFAULT); 1462 } 1463 1464 if (pmf_device_register(self, NULL, sk_resume)) 1465 pmf_class_network_register(self, ifp); 1466 else 1467 aprint_error_dev(self, "couldn't establish power handler\n"); 1468 1469 DPRINTFN(2, ("sk_attach: end\n")); 1470 1471 return; 1472 1473 fail: 1474 sc->sk_if[sa->skc_port] = NULL; 1475 } 1476 1477 static int 1478 skcprint(void *aux, const char *pnp) 1479 { 1480 struct skc_attach_args *sa = aux; 1481 1482 if (pnp) 1483 aprint_normal("sk port %c at %s", 1484 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1485 else 1486 aprint_normal(" port %c", 1487 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1488 return UNCONF; 1489 } 1490 1491 /* 1492 * Attach the interface. Allocate softc structures, do ifmedia 1493 * setup and ethernet/BPF attach. 1494 */ 1495 static void 1496 skc_attach(device_t parent, device_t self, void *aux) 1497 { 1498 struct sk_softc *sc = device_private(self); 1499 struct pci_attach_args *pa = aux; 1500 struct skc_attach_args skca; 1501 pci_chipset_tag_t pc = pa->pa_pc; 1502 #ifndef SK_USEIOSPACE 1503 pcireg_t memtype; 1504 #endif 1505 pci_intr_handle_t ih; 1506 const char *intrstr = NULL; 1507 bus_addr_t iobase; 1508 bus_size_t iosize; 1509 int rc, sk_nodenum; 1510 uint32_t command; 1511 const char *revstr; 1512 const struct sysctlnode *node; 1513 char intrbuf[PCI_INTRSTR_LEN]; 1514 1515 sc->sk_dev = self; 1516 aprint_naive("\n"); 1517 1518 DPRINTFN(2, ("begin skc_attach\n")); 1519 1520 /* 1521 * Handle power management nonsense. 1522 */ 1523 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1524 1525 if (command == 0x01) { 1526 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1527 if (command & SK_PSTATE_MASK) { 1528 uint32_t xiobase, membase, irq; 1529 1530 /* Save important PCI config data. */ 1531 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1532 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1533 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1534 1535 /* Reset the power state. */ 1536 aprint_normal_dev(sc->sk_dev, 1537 "chip is in D%d power mode -- setting to D0\n", 1538 command & SK_PSTATE_MASK); 1539 command &= 0xFFFFFFFC; 1540 pci_conf_write(pc, pa->pa_tag, 1541 SK_PCI_PWRMGMTCTRL, command); 1542 1543 /* Restore PCI config data. */ 1544 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1545 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1546 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1547 } 1548 } 1549 1550 /* 1551 * The firmware might have configured the interface to revert the 1552 * byte order in all descriptors. Make that undone. 1553 */ 1554 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_OURREG2); 1555 if (command & SK_REG2_REV_DESC) 1556 pci_conf_write(pc, pa->pa_tag, SK_PCI_OURREG2, 1557 command & ~SK_REG2_REV_DESC); 1558 1559 /* 1560 * Map control/status registers. 1561 */ 1562 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1563 command |= PCI_COMMAND_IO_ENABLE | 1564 PCI_COMMAND_MEM_ENABLE | 1565 PCI_COMMAND_MASTER_ENABLE; 1566 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1567 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1568 1569 #ifdef SK_USEIOSPACE 1570 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1571 aprint_error(": failed to enable I/O ports!\n"); 1572 return; 1573 } 1574 /* 1575 * Map control/status registers. 1576 */ 1577 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1578 &sc->sk_btag, &sc->sk_bhandle, 1579 &iobase, &iosize)) { 1580 aprint_error(": can't find i/o space\n"); 1581 return; 1582 } 1583 #else 1584 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1585 aprint_error(": failed to enable memory mapping!\n"); 1586 return; 1587 } 1588 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1589 switch (memtype) { 1590 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1591 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1592 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1593 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1594 &iobase, &iosize) == 0) 1595 break; 1596 /* FALLTHROUGH */ 1597 default: 1598 aprint_error_dev(sc->sk_dev, "can't find mem space\n"); 1599 return; 1600 } 1601 1602 DPRINTFN(2, ("skc_attach: iobase=%#" PRIxPADDR ", iosize=%zx\n", 1603 iobase, iosize)); 1604 #endif 1605 sc->sc_dmatag = pa->pa_dmat; 1606 1607 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1608 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1609 1610 /* bail out here if chip is not recognized */ 1611 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1612 aprint_error_dev(sc->sk_dev, "unknown chip type\n"); 1613 goto fail; 1614 } 1615 if (SK_IS_YUKON2(sc)) { 1616 aprint_error_dev(sc->sk_dev, 1617 "Does not support Yukon2--try msk(4).\n"); 1618 goto fail; 1619 } 1620 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1621 1622 /* Allocate interrupt */ 1623 if (pci_intr_map(pa, &ih)) { 1624 aprint_error(": couldn't map interrupt\n"); 1625 goto fail; 1626 } 1627 1628 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1629 sc->sk_intrhand = pci_intr_establish_xname(pc, ih, IPL_NET, sk_intr, 1630 sc, device_xname(sc->sk_dev)); 1631 if (sc->sk_intrhand == NULL) { 1632 aprint_error(": couldn't establish interrupt"); 1633 if (intrstr != NULL) 1634 aprint_error(" at %s", intrstr); 1635 aprint_error("\n"); 1636 goto fail; 1637 } 1638 aprint_normal(": %s\n", intrstr); 1639 1640 /* Reset the adapter. */ 1641 sk_reset(sc); 1642 1643 /* Read and save vital product data from EEPROM. */ 1644 sk_vpd_read(sc); 1645 1646 if (sc->sk_type == SK_GENESIS) { 1647 uint8_t val = sk_win_read_1(sc, SK_EPROM0); 1648 /* Read and save RAM size and RAMbuffer offset */ 1649 switch (val) { 1650 case SK_RAMSIZE_512K_64: 1651 sc->sk_ramsize = 0x80000; 1652 sc->sk_rboff = SK_RBOFF_0; 1653 break; 1654 case SK_RAMSIZE_1024K_64: 1655 sc->sk_ramsize = 0x100000; 1656 sc->sk_rboff = SK_RBOFF_80000; 1657 break; 1658 case SK_RAMSIZE_1024K_128: 1659 sc->sk_ramsize = 0x100000; 1660 sc->sk_rboff = SK_RBOFF_0; 1661 break; 1662 case SK_RAMSIZE_2048K_128: 1663 sc->sk_ramsize = 0x200000; 1664 sc->sk_rboff = SK_RBOFF_0; 1665 break; 1666 default: 1667 aprint_error_dev(sc->sk_dev, "unknown ram size: %d\n", 1668 val); 1669 goto fail_1; 1670 break; 1671 } 1672 1673 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1674 sc->sk_ramsize, sc->sk_ramsize / 1024, 1675 sc->sk_rboff)); 1676 } else { 1677 uint8_t val = sk_win_read_1(sc, SK_EPROM0); 1678 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1679 sc->sk_rboff = SK_RBOFF_0; 1680 1681 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1682 sc->sk_ramsize / 1024, sc->sk_ramsize, 1683 sc->sk_rboff)); 1684 } 1685 1686 /* Read and save physical media type */ 1687 switch (sk_win_read_1(sc, SK_PMDTYPE)) { 1688 case SK_PMD_1000BASESX: 1689 sc->sk_pmd = IFM_1000_SX; 1690 break; 1691 case SK_PMD_1000BASELX: 1692 sc->sk_pmd = IFM_1000_LX; 1693 break; 1694 case SK_PMD_1000BASECX: 1695 sc->sk_pmd = IFM_1000_CX; 1696 break; 1697 case SK_PMD_1000BASETX: 1698 case SK_PMD_1000BASETX_ALT: 1699 sc->sk_pmd = IFM_1000_T; 1700 break; 1701 default: 1702 aprint_error_dev(sc->sk_dev, "unknown media type: 0x%x\n", 1703 sk_win_read_1(sc, SK_PMDTYPE)); 1704 goto fail_1; 1705 } 1706 1707 /* determine whether to name it with vpd or just make it up */ 1708 /* Marvell Yukon VPD's can freqently be bogus */ 1709 1710 switch (pa->pa_id) { 1711 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1712 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1713 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1714 case PCI_PRODUCT_3COM_3C940: 1715 case PCI_PRODUCT_DLINK_DGE530T: 1716 case PCI_PRODUCT_DLINK_DGE560T: 1717 case PCI_PRODUCT_DLINK_DGE560T_2: 1718 case PCI_PRODUCT_LINKSYS_EG1032: 1719 case PCI_PRODUCT_LINKSYS_EG1064: 1720 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1721 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1722 case PCI_ID_CODE(PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940): 1723 case PCI_ID_CODE(PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T): 1724 case PCI_ID_CODE(PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T): 1725 case PCI_ID_CODE(PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2): 1726 case PCI_ID_CODE(PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032): 1727 case PCI_ID_CODE(PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064): 1728 sc->sk_name = sc->sk_vpd_prodname; 1729 break; 1730 case PCI_ID_CODE(PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET): 1731 /* whoops yukon vpd prodname bears no resemblance to reality */ 1732 switch (sc->sk_type) { 1733 case SK_GENESIS: 1734 sc->sk_name = sc->sk_vpd_prodname; 1735 break; 1736 case SK_YUKON: 1737 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1738 break; 1739 case SK_YUKON_LITE: 1740 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1741 break; 1742 case SK_YUKON_LP: 1743 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1744 break; 1745 default: 1746 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1747 } 1748 1749 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1750 1751 if ( sc->sk_type == SK_YUKON ) { 1752 uint32_t flashaddr; 1753 uint8_t testbyte; 1754 1755 flashaddr = sk_win_read_4(sc, SK_EP_ADDR); 1756 1757 /* test Flash-Address Register */ 1758 sk_win_write_1(sc, SK_EP_ADDR+3, 0xff); 1759 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1760 1761 if (testbyte != 0) { 1762 /* this is yukon lite Rev. A0 */ 1763 sc->sk_type = SK_YUKON_LITE; 1764 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1765 /* restore Flash-Address Register */ 1766 sk_win_write_4(sc, SK_EP_ADDR, flashaddr); 1767 } 1768 } 1769 break; 1770 case PCI_ID_CODE(PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN): 1771 sc->sk_name = sc->sk_vpd_prodname; 1772 break; 1773 default: 1774 sc->sk_name = "Unknown Marvell"; 1775 } 1776 1777 1778 if ( sc->sk_type == SK_YUKON_LITE ) { 1779 switch (sc->sk_rev) { 1780 case SK_YUKON_LITE_REV_A0: 1781 revstr = "A0"; 1782 break; 1783 case SK_YUKON_LITE_REV_A1: 1784 revstr = "A1"; 1785 break; 1786 case SK_YUKON_LITE_REV_A3: 1787 revstr = "A3"; 1788 break; 1789 default: 1790 revstr = ""; 1791 } 1792 } else { 1793 revstr = ""; 1794 } 1795 1796 /* Announce the product name. */ 1797 aprint_normal_dev(sc->sk_dev, "%s rev. %s(0x%x)\n", 1798 sc->sk_name, revstr, sc->sk_rev); 1799 1800 skca.skc_port = SK_PORT_A; 1801 (void)config_found(sc->sk_dev, &skca, skcprint); 1802 1803 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1804 skca.skc_port = SK_PORT_B; 1805 (void)config_found(sc->sk_dev, &skca, skcprint); 1806 } 1807 1808 /* Turn on the 'driver is loaded' LED. */ 1809 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1810 1811 /* skc sysctl setup */ 1812 1813 sc->sk_int_mod = SK_IM_DEFAULT; 1814 sc->sk_int_mod_pending = 0; 1815 1816 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1817 0, CTLTYPE_NODE, device_xname(sc->sk_dev), 1818 SYSCTL_DESCR("skc per-controller controls"), 1819 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1820 CTL_EOL)) != 0) { 1821 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n"); 1822 goto fail_1; 1823 } 1824 1825 sk_nodenum = node->sysctl_num; 1826 1827 /* interrupt moderation time in usecs */ 1828 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1829 CTLFLAG_READWRITE, 1830 CTLTYPE_INT, "int_mod", 1831 SYSCTL_DESCR("sk interrupt moderation timer"), 1832 sk_sysctl_handler, 0, (void *)sc, 1833 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1834 CTL_EOL)) != 0) { 1835 aprint_normal_dev(sc->sk_dev, 1836 "couldn't create int_mod sysctl node\n"); 1837 goto fail_1; 1838 } 1839 1840 if (!pmf_device_register(self, skc_suspend, skc_resume)) 1841 aprint_error_dev(self, "couldn't establish power handler\n"); 1842 1843 return; 1844 1845 fail_1: 1846 pci_intr_disestablish(pc, sc->sk_intrhand); 1847 fail: 1848 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize); 1849 } 1850 1851 static int 1852 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx) 1853 { 1854 struct sk_softc *sc = sc_if->sk_softc; 1855 struct sk_tx_desc *f = NULL; 1856 uint32_t frag, cur, cnt = 0, sk_ctl; 1857 int i; 1858 struct sk_txmap_entry *entry; 1859 bus_dmamap_t txmap; 1860 1861 DPRINTFN(3, ("sk_encap\n")); 1862 1863 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1864 if (entry == NULL) { 1865 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1866 return ENOBUFS; 1867 } 1868 txmap = entry->dmamap; 1869 1870 cur = frag = *txidx; 1871 1872 #ifdef SK_DEBUG 1873 if (skdebug >= 3) 1874 sk_dump_mbuf(m_head); 1875 #endif 1876 1877 /* 1878 * Start packing the mbufs in this chain into 1879 * the fragment pointers. Stop when we run out 1880 * of fragments or hit the end of the mbuf chain. 1881 */ 1882 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1883 BUS_DMA_NOWAIT)) { 1884 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1885 return ENOBUFS; 1886 } 1887 1888 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1889 1890 /* Sync the DMA map. */ 1891 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1892 BUS_DMASYNC_PREWRITE); 1893 1894 for (i = 0; i < txmap->dm_nsegs; i++) { 1895 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1896 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1897 return ENOBUFS; 1898 } 1899 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1900 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr); 1901 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1902 if (cnt == 0) 1903 sk_ctl |= SK_TXCTL_FIRSTFRAG; 1904 else 1905 sk_ctl |= SK_TXCTL_OWN; 1906 f->sk_ctl = htole32(sk_ctl); 1907 cur = frag; 1908 SK_INC(frag, SK_TX_RING_CNT); 1909 cnt++; 1910 } 1911 1912 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1913 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1914 1915 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1916 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1917 htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR); 1918 1919 /* Sync descriptors before handing to chip */ 1920 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1921 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1922 1923 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= 1924 htole32(SK_TXCTL_OWN); 1925 1926 /* Sync first descriptor to hand it off */ 1927 SK_CDTXSYNC(sc_if, *txidx, 1, 1928 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1929 1930 sc_if->sk_cdata.sk_tx_cnt += cnt; 1931 1932 #ifdef SK_DEBUG 1933 if (skdebug >= 3) { 1934 struct sk_tx_desc *desc; 1935 uint32_t idx; 1936 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1937 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1938 sk_dump_txdesc(desc, idx); 1939 } 1940 } 1941 #endif 1942 1943 *txidx = frag; 1944 1945 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1946 1947 return 0; 1948 } 1949 1950 static void 1951 sk_start(struct ifnet *ifp) 1952 { 1953 struct sk_if_softc *sc_if = ifp->if_softc; 1954 struct sk_softc *sc = sc_if->sk_softc; 1955 struct mbuf *m_head = NULL; 1956 uint32_t idx = sc_if->sk_cdata.sk_tx_prod; 1957 int pkts = 0; 1958 1959 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1960 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1961 1962 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1963 IFQ_POLL(&ifp->if_snd, m_head); 1964 if (m_head == NULL) 1965 break; 1966 1967 /* 1968 * Pack the data into the transmit ring. If we 1969 * don't have room, set the OACTIVE flag and wait 1970 * for the NIC to drain the ring. 1971 */ 1972 if (sk_encap(sc_if, m_head, &idx)) { 1973 ifp->if_flags |= IFF_OACTIVE; 1974 break; 1975 } 1976 1977 /* now we are committed to transmit the packet */ 1978 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1979 pkts++; 1980 1981 /* 1982 * If there's a BPF listener, bounce a copy of this frame 1983 * to him. 1984 */ 1985 bpf_mtap(ifp, m_head, BPF_D_OUT); 1986 } 1987 if (pkts == 0) 1988 return; 1989 1990 /* Transmit */ 1991 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1992 sc_if->sk_cdata.sk_tx_prod = idx; 1993 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1994 1995 /* Set a timeout in case the chip goes out to lunch. */ 1996 ifp->if_timer = 5; 1997 } 1998 } 1999 2000 2001 static void 2002 sk_watchdog(struct ifnet *ifp) 2003 { 2004 struct sk_if_softc *sc_if = ifp->if_softc; 2005 2006 /* 2007 * Reclaim first as there is a possibility of losing Tx completion 2008 * interrupts. 2009 */ 2010 sk_txeof(sc_if); 2011 if (sc_if->sk_cdata.sk_tx_cnt != 0) { 2012 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n"); 2013 2014 if_statinc(ifp, if_oerrors); 2015 2016 sk_init(ifp); 2017 } 2018 } 2019 2020 #if 0 /* XXX XXX XXX UNUSED */ 2021 static void 2022 sk_shutdown(void *v) 2023 { 2024 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 2025 struct sk_softc *sc = sc_if->sk_softc; 2026 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2027 2028 DPRINTFN(2, ("sk_shutdown\n")); 2029 sk_stop(ifp, 1); 2030 2031 /* Turn off the 'driver is loaded' LED. */ 2032 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2033 2034 /* 2035 * Reset the GEnesis controller. Doing this should also 2036 * assert the resets on the attached XMAC(s). 2037 */ 2038 sk_reset(sc); 2039 } 2040 #endif 2041 2042 static void 2043 sk_rxeof(struct sk_if_softc *sc_if) 2044 { 2045 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2046 struct mbuf *m; 2047 struct sk_chain *cur_rx; 2048 struct sk_rx_desc *cur_desc; 2049 int i, cur, total_len = 0; 2050 uint32_t rxstat, sk_ctl; 2051 bus_dmamap_t dmamap; 2052 2053 i = sc_if->sk_cdata.sk_rx_prod; 2054 2055 DPRINTFN(3, ("sk_rxeof %d\n", i)); 2056 2057 for (;;) { 2058 cur = i; 2059 2060 /* Sync the descriptor */ 2061 SK_CDRXSYNC(sc_if, cur, 2062 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2063 2064 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl); 2065 if (sk_ctl & SK_RXCTL_OWN) { 2066 /* Invalidate the descriptor -- it's not ready yet */ 2067 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 2068 sc_if->sk_cdata.sk_rx_prod = i; 2069 break; 2070 } 2071 2072 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 2073 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 2074 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map; 2075 2076 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 2077 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2078 2079 rxstat = le32toh(cur_desc->sk_xmac_rxstat); 2080 m = cur_rx->sk_mbuf; 2081 cur_rx->sk_mbuf = NULL; 2082 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl)); 2083 2084 sc_if->sk_cdata.sk_rx_map[cur] = 0; 2085 2086 SK_INC(i, SK_RX_RING_CNT); 2087 2088 if (rxstat & XM_RXSTAT_ERRFRAME) { 2089 if_statinc(ifp, if_ierrors); 2090 sk_newbuf(sc_if, cur, m, dmamap); 2091 continue; 2092 } 2093 2094 /* 2095 * Try to allocate a new jumbo buffer. If that 2096 * fails, copy the packet to mbufs and put the 2097 * jumbo buffer back in the ring so it can be 2098 * re-used. If allocating mbufs fails, then we 2099 * have to drop the packet. 2100 */ 2101 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 2102 struct mbuf *m0; 2103 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2104 total_len + ETHER_ALIGN, 0, ifp); 2105 sk_newbuf(sc_if, cur, m, dmamap); 2106 if (m0 == NULL) { 2107 aprint_error_dev(sc_if->sk_dev, "no receive " 2108 "buffers available -- packet dropped!\n"); 2109 if_statinc(ifp, if_ierrors); 2110 continue; 2111 } 2112 m_adj(m0, ETHER_ALIGN); 2113 m = m0; 2114 } else { 2115 m_set_rcvif(m, ifp); 2116 m->m_pkthdr.len = m->m_len = total_len; 2117 } 2118 2119 /* pass it on. */ 2120 if_percpuq_enqueue(ifp->if_percpuq, m); 2121 } 2122 } 2123 2124 static void 2125 sk_txeof(struct sk_if_softc *sc_if) 2126 { 2127 struct sk_softc *sc = sc_if->sk_softc; 2128 struct sk_tx_desc *cur_tx; 2129 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2130 uint32_t idx, sk_ctl; 2131 struct sk_txmap_entry *entry; 2132 2133 DPRINTFN(3, ("sk_txeof\n")); 2134 2135 /* 2136 * Go through our tx ring and free mbufs for those 2137 * frames that have been sent. 2138 */ 2139 idx = sc_if->sk_cdata.sk_tx_cons; 2140 while (idx != sc_if->sk_cdata.sk_tx_prod) { 2141 SK_CDTXSYNC(sc_if, idx, 1, 2142 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2143 2144 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 2145 sk_ctl = le32toh(cur_tx->sk_ctl); 2146 #ifdef SK_DEBUG 2147 if (skdebug >= 3) 2148 sk_dump_txdesc(cur_tx, idx); 2149 #endif 2150 if (sk_ctl & SK_TXCTL_OWN) { 2151 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 2152 break; 2153 } 2154 if (sk_ctl & SK_TXCTL_LASTFRAG) 2155 if_statinc(ifp, if_opackets); 2156 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2157 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2158 2159 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2160 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2161 2162 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2163 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2164 2165 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2166 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2167 link); 2168 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2169 } 2170 sc_if->sk_cdata.sk_tx_cnt--; 2171 SK_INC(idx, SK_TX_RING_CNT); 2172 } 2173 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2174 ifp->if_timer = 0; 2175 else /* nudge chip to keep tx ring moving */ 2176 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2177 2178 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2179 ifp->if_flags &= ~IFF_OACTIVE; 2180 2181 sc_if->sk_cdata.sk_tx_cons = idx; 2182 } 2183 2184 static void 2185 sk_tick(void *xsc_if) 2186 { 2187 struct sk_if_softc *sc_if = xsc_if; 2188 struct mii_data *mii = &sc_if->sk_mii; 2189 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2190 int i; 2191 2192 DPRINTFN(3, ("sk_tick\n")); 2193 2194 if (!(ifp->if_flags & IFF_UP)) 2195 return; 2196 2197 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2198 sk_intr_bcom(sc_if); 2199 return; 2200 } 2201 2202 /* 2203 * According to SysKonnect, the correct way to verify that 2204 * the link has come back up is to poll bit 0 of the GPIO 2205 * register three times. This pin has the signal from the 2206 * link sync pin connected to it; if we read the same link 2207 * state 3 times in a row, we know the link is up. 2208 */ 2209 for (i = 0; i < 3; i++) { 2210 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2211 break; 2212 } 2213 2214 if (i != 3) { 2215 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2216 return; 2217 } 2218 2219 /* Turn the GP0 interrupt back on. */ 2220 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2221 SK_XM_READ_2(sc_if, XM_ISR); 2222 mii_tick(mii); 2223 if (ifp->if_link_state != LINK_STATE_UP) 2224 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2225 else 2226 callout_stop(&sc_if->sk_tick_ch); 2227 } 2228 2229 static void 2230 sk_intr_bcom(struct sk_if_softc *sc_if) 2231 { 2232 struct mii_data *mii = &sc_if->sk_mii; 2233 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2234 uint16_t status; 2235 2236 2237 DPRINTFN(3, ("sk_intr_bcom\n")); 2238 2239 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB); 2240 2241 /* 2242 * Read the PHY interrupt register to make sure 2243 * we clear any pending interrupts. 2244 */ 2245 sk_xmac_miibus_readreg(sc_if->sk_dev, 2246 SK_PHYADDR_BCOM, BRGPHY_MII_ISR, &status); 2247 2248 if (!(ifp->if_flags & IFF_RUNNING)) { 2249 sk_init_xmac(sc_if); 2250 return; 2251 } 2252 2253 if (status & (BRGPHY_ISR_LNK_CHG | BRGPHY_ISR_AN_PR)) { 2254 uint16_t lstat; 2255 sk_xmac_miibus_readreg(sc_if->sk_dev, 2256 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS, &lstat); 2257 2258 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2259 (void)mii_mediachg(mii); 2260 /* Turn off the link LED. */ 2261 SK_IF_WRITE_1(sc_if, 0, 2262 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2263 sc_if->sk_link = 0; 2264 } else if (status & BRGPHY_ISR_LNK_CHG) { 2265 sk_xmac_miibus_writereg(sc_if->sk_dev, 2266 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2267 mii_tick(mii); 2268 sc_if->sk_link = 1; 2269 /* Turn on the link LED. */ 2270 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2271 SK_LINKLED_ON | SK_LINKLED_LINKSYNC_OFF | 2272 SK_LINKLED_BLINK_OFF); 2273 mii_pollstat(mii); 2274 } else { 2275 mii_tick(mii); 2276 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2277 } 2278 } 2279 2280 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB); 2281 } 2282 2283 static void 2284 sk_intr_xmac(struct sk_if_softc *sc_if) 2285 { 2286 uint16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2287 2288 DPRINTFN(3, ("sk_intr_xmac\n")); 2289 2290 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2291 if (status & XM_ISR_GP0_SET) { 2292 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2293 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2294 } 2295 2296 if (status & XM_ISR_AUTONEG_DONE) { 2297 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2298 } 2299 } 2300 2301 if (status & XM_IMR_TX_UNDERRUN) 2302 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2303 2304 if (status & XM_IMR_RX_OVERRUN) 2305 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2306 } 2307 2308 static void 2309 sk_intr_yukon(struct sk_if_softc *sc_if) 2310 { 2311 #ifdef SK_DEBUG 2312 int status; 2313 2314 status = 2315 #endif 2316 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2317 2318 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2319 } 2320 2321 static int 2322 sk_intr(void *xsc) 2323 { 2324 struct sk_softc *sc = xsc; 2325 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2326 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2327 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2328 uint32_t status; 2329 int claimed = 0; 2330 2331 if (sc_if0 != NULL) 2332 ifp0 = &sc_if0->sk_ethercom.ec_if; 2333 if (sc_if1 != NULL) 2334 ifp1 = &sc_if1->sk_ethercom.ec_if; 2335 2336 for (;;) { 2337 status = CSR_READ_4(sc, SK_ISSR); 2338 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2339 2340 if (!(status & sc->sk_intrmask)) 2341 break; 2342 2343 claimed = 1; 2344 2345 /* Handle receive interrupts first. */ 2346 if (sc_if0 && (status & SK_ISR_RX1_EOF)) { 2347 sk_rxeof(sc_if0); 2348 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2349 SK_RXBMU_CLR_IRQ_EOF | SK_RXBMU_RX_START); 2350 } 2351 if (sc_if1 && (status & SK_ISR_RX2_EOF)) { 2352 sk_rxeof(sc_if1); 2353 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2354 SK_RXBMU_CLR_IRQ_EOF | SK_RXBMU_RX_START); 2355 } 2356 2357 /* Then transmit interrupts. */ 2358 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) { 2359 sk_txeof(sc_if0); 2360 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2361 SK_TXBMU_CLR_IRQ_EOF); 2362 } 2363 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) { 2364 sk_txeof(sc_if1); 2365 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2366 SK_TXBMU_CLR_IRQ_EOF); 2367 } 2368 2369 /* Then MAC interrupts. */ 2370 if (sc_if0 && (status & SK_ISR_MAC1) && 2371 (ifp0->if_flags & IFF_RUNNING)) { 2372 if (sc->sk_type == SK_GENESIS) 2373 sk_intr_xmac(sc_if0); 2374 else 2375 sk_intr_yukon(sc_if0); 2376 } 2377 2378 if (sc_if1 && (status & SK_ISR_MAC2) && 2379 (ifp1->if_flags & IFF_RUNNING)) { 2380 if (sc->sk_type == SK_GENESIS) 2381 sk_intr_xmac(sc_if1); 2382 else 2383 sk_intr_yukon(sc_if1); 2384 2385 } 2386 2387 if (status & SK_ISR_EXTERNAL_REG) { 2388 if (sc_if0 != NULL && 2389 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2390 sk_intr_bcom(sc_if0); 2391 2392 if (sc_if1 != NULL && 2393 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2394 sk_intr_bcom(sc_if1); 2395 } 2396 } 2397 2398 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2399 2400 if (ifp0 != NULL) 2401 if_schedule_deferred_start(ifp0); 2402 if (ifp1 != NULL) 2403 if_schedule_deferred_start(ifp1); 2404 2405 KASSERT(sc->rnd_attached > 0); 2406 rnd_add_uint32(&sc->rnd_source, status); 2407 2408 if (sc->sk_int_mod_pending) 2409 sk_update_int_mod(sc); 2410 2411 return claimed; 2412 } 2413 2414 static void 2415 sk_unreset_xmac(struct sk_if_softc *sc_if) 2416 { 2417 struct sk_softc *sc = sc_if->sk_softc; 2418 static const struct sk_bcom_hack bhack[] = { 2419 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2420 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2421 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2422 { 0, 0 } }; 2423 2424 DPRINTFN(1, ("sk_unreset_xmac\n")); 2425 2426 /* Unreset the XMAC. */ 2427 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2428 DELAY(1000); 2429 2430 /* Reset the XMAC's internal state. */ 2431 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2432 2433 /* Save the XMAC II revision */ 2434 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2435 2436 /* 2437 * Perform additional initialization for external PHYs, 2438 * namely for the 1000baseTX cards that use the XMAC's 2439 * GMII mode. 2440 */ 2441 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2442 int i = 0; 2443 uint32_t val; 2444 uint16_t phyval; 2445 2446 /* Take PHY out of reset. */ 2447 val = sk_win_read_4(sc, SK_GPIO); 2448 if (sc_if->sk_port == SK_PORT_A) 2449 val |= SK_GPIO_DIR0 | SK_GPIO_DAT0; 2450 else 2451 val |= SK_GPIO_DIR2 | SK_GPIO_DAT2; 2452 sk_win_write_4(sc, SK_GPIO, val); 2453 2454 /* Enable GMII mode on the XMAC. */ 2455 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2456 2457 sk_xmac_miibus_writereg(sc_if->sk_dev, 2458 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2459 DELAY(10000); 2460 sk_xmac_miibus_writereg(sc_if->sk_dev, 2461 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2462 2463 /* 2464 * Early versions of the BCM5400 apparently have 2465 * a bug that requires them to have their reserved 2466 * registers initialized to some magic values. I don't 2467 * know what the numbers do, I'm just the messenger. 2468 */ 2469 sk_xmac_miibus_readreg(sc_if->sk_dev, 2470 SK_PHYADDR_BCOM, 0x03, &phyval); 2471 if (phyval == 0x6041) { 2472 while (bhack[i].reg) { 2473 sk_xmac_miibus_writereg(sc_if->sk_dev, 2474 SK_PHYADDR_BCOM, bhack[i].reg, 2475 bhack[i].val); 2476 i++; 2477 } 2478 } 2479 } 2480 } 2481 2482 static void 2483 sk_init_xmac(struct sk_if_softc *sc_if) 2484 { 2485 struct sk_softc *sc = sc_if->sk_softc; 2486 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2487 2488 sk_unreset_xmac(sc_if); 2489 2490 /* Set station address */ 2491 SK_XM_WRITE_2(sc_if, XM_PAR0, 2492 *(uint16_t *)(&sc_if->sk_enaddr[0])); 2493 SK_XM_WRITE_2(sc_if, XM_PAR1, 2494 *(uint16_t *)(&sc_if->sk_enaddr[2])); 2495 SK_XM_WRITE_2(sc_if, XM_PAR2, 2496 *(uint16_t *)(&sc_if->sk_enaddr[4])); 2497 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2498 2499 if (ifp->if_flags & IFF_PROMISC) 2500 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2501 else 2502 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2503 2504 if (ifp->if_flags & IFF_BROADCAST) 2505 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2506 else 2507 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2508 2509 /* We don't need the FCS appended to the packet. */ 2510 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2511 2512 /* We want short frames padded to 60 bytes. */ 2513 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2514 2515 /* 2516 * Enable the reception of all error frames. This is 2517 * a necessary evil due to the design of the XMAC. The 2518 * XMAC's receive FIFO is only 8K in size, however jumbo 2519 * frames can be up to 9000 bytes in length. When bad 2520 * frame filtering is enabled, the XMAC's RX FIFO operates 2521 * in 'store and forward' mode. For this to work, the 2522 * entire frame has to fit into the FIFO, but that means 2523 * that jumbo frames larger than 8192 bytes will be 2524 * truncated. Disabling all bad frame filtering causes 2525 * the RX FIFO to operate in streaming mode, in which 2526 * case the XMAC will start transfering frames out of the 2527 * RX FIFO as soon as the FIFO threshold is reached. 2528 */ 2529 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES | 2530 XM_MODE_RX_GIANTS | XM_MODE_RX_RUNTS | XM_MODE_RX_CRCERRS | 2531 XM_MODE_RX_INRANGELEN); 2532 2533 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2534 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2535 else 2536 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2537 2538 /* 2539 * Bump up the transmit threshold. This helps hold off transmit 2540 * underruns when we're blasting traffic from both ports at once. 2541 */ 2542 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2543 2544 /* Set multicast filter */ 2545 sk_setmulti(sc_if); 2546 2547 /* Clear and enable interrupts */ 2548 SK_XM_READ_2(sc_if, XM_ISR); 2549 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2550 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2551 else 2552 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2553 2554 /* Configure MAC arbiter */ 2555 switch (sc_if->sk_xmac_rev) { 2556 case XM_XMAC_REV_B2: 2557 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2558 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2559 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2560 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2561 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2562 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2563 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2564 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2565 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2566 break; 2567 case XM_XMAC_REV_C1: 2568 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2569 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2570 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2571 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2572 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2573 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2574 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2575 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2576 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2577 break; 2578 default: 2579 break; 2580 } 2581 sk_win_write_2(sc, SK_MACARB_CTL, 2582 SK_MACARBCTL_UNRESET | SK_MACARBCTL_FASTOE_OFF); 2583 2584 sc_if->sk_link = 1; 2585 } 2586 2587 static void 2588 sk_unreset_yukon(struct sk_if_softc *sc_if) 2589 { 2590 uint32_t /*mac, */phy; 2591 struct sk_softc *sc; 2592 2593 DPRINTFN(1, ("sk_unreset_yukon: start: sk_csr=%#x\n", 2594 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2595 2596 sc = sc_if->sk_softc; 2597 if (sc->sk_type == SK_YUKON_LITE && 2598 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2599 /* Take PHY out of reset. */ 2600 sk_win_write_4(sc, SK_GPIO, 2601 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) 2602 & ~SK_GPIO_DAT9); 2603 } 2604 2605 /* GMAC and GPHY Reset */ 2606 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2607 2608 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2609 2610 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2611 DELAY(1000); 2612 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2613 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2614 DELAY(1000); 2615 2616 2617 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2618 2619 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2620 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2621 2622 switch (sc_if->sk_softc->sk_pmd) { 2623 case IFM_1000_SX: 2624 case IFM_1000_LX: 2625 phy |= SK_GPHY_FIBER; 2626 break; 2627 2628 case IFM_1000_CX: 2629 case IFM_1000_T: 2630 phy |= SK_GPHY_COPPER; 2631 break; 2632 } 2633 2634 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2635 2636 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2637 DELAY(1000); 2638 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2639 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2640 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2641 2642 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2643 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2644 } 2645 2646 static void 2647 sk_init_yukon(struct sk_if_softc *sc_if) 2648 { 2649 uint16_t reg; 2650 int i; 2651 2652 DPRINTFN(1, ("sk_init_yukon: start\n")); 2653 sk_unreset_yukon(sc_if); 2654 2655 /* unused read of the interrupt source register */ 2656 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2657 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2658 2659 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2660 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2661 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2662 2663 /* MIB Counter Clear Mode set */ 2664 reg |= YU_PAR_MIB_CLR; 2665 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2666 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2667 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2668 2669 /* MIB Counter Clear Mode clear */ 2670 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2671 reg &= ~YU_PAR_MIB_CLR; 2672 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2673 2674 /* receive control reg */ 2675 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2676 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2677 YU_RCR_CRCR); 2678 2679 /* transmit parameter register */ 2680 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2681 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2682 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a)); 2683 2684 /* serial mode register */ 2685 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2686 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2687 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | 2688 YU_SMR_IPG_DATA(0x1e)); 2689 2690 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2691 /* Setup Yukon's address */ 2692 for (i = 0; i < 3; i++) { 2693 /* Write Source Address 1 (unicast filter) */ 2694 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2695 sc_if->sk_enaddr[i * 2] | 2696 sc_if->sk_enaddr[i * 2 + 1] << 8); 2697 } 2698 2699 for (i = 0; i < 3; i++) { 2700 reg = sk_win_read_2(sc_if->sk_softc, 2701 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2702 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2703 } 2704 2705 /* Set multicast filter */ 2706 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2707 sk_setmulti(sc_if); 2708 2709 /* enable interrupt mask for counter overflows */ 2710 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2711 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2712 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2713 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2714 2715 /* Configure RX MAC FIFO */ 2716 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2717 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2718 2719 /* Configure TX MAC FIFO */ 2720 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2721 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2722 2723 DPRINTFN(6, ("sk_init_yukon: end\n")); 2724 } 2725 2726 /* 2727 * Note that to properly initialize any part of the GEnesis chip, 2728 * you first have to take it out of reset mode. 2729 */ 2730 static int 2731 sk_init(struct ifnet *ifp) 2732 { 2733 struct sk_if_softc *sc_if = ifp->if_softc; 2734 struct sk_softc *sc = sc_if->sk_softc; 2735 struct mii_data *mii = &sc_if->sk_mii; 2736 int rc = 0, s; 2737 uint32_t imr, imtimer_ticks; 2738 2739 DPRINTFN(1, ("sk_init\n")); 2740 2741 s = splnet(); 2742 2743 if (ifp->if_flags & IFF_RUNNING) { 2744 splx(s); 2745 return 0; 2746 } 2747 2748 /* Cancel pending I/O and free all RX/TX buffers. */ 2749 sk_stop(ifp, 0); 2750 2751 if (sc->sk_type == SK_GENESIS) { 2752 /* Configure LINK_SYNC LED */ 2753 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2754 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2755 SK_LINKLED_LINKSYNC_ON); 2756 2757 /* Configure RX LED */ 2758 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2759 SK_RXLEDCTL_COUNTER_START); 2760 2761 /* Configure TX LED */ 2762 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2763 SK_TXLEDCTL_COUNTER_START); 2764 } 2765 2766 /* Configure I2C registers */ 2767 2768 /* Configure XMAC(s) */ 2769 switch (sc->sk_type) { 2770 case SK_GENESIS: 2771 sk_init_xmac(sc_if); 2772 break; 2773 case SK_YUKON: 2774 case SK_YUKON_LITE: 2775 case SK_YUKON_LP: 2776 sk_init_yukon(sc_if); 2777 break; 2778 } 2779 if ((rc = mii_mediachg(mii)) == ENXIO) 2780 rc = 0; 2781 else if (rc != 0) 2782 goto out; 2783 2784 if (sc->sk_type == SK_GENESIS) { 2785 /* Configure MAC FIFOs */ 2786 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2787 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2788 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2789 2790 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2791 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2792 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2793 } 2794 2795 /* Configure transmit arbiter(s) */ 2796 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2797 SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON); 2798 2799 /* Configure RAMbuffers */ 2800 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2801 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2802 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2803 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2804 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2805 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2806 2807 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2808 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2809 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2810 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2811 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2812 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2813 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2814 2815 /* Configure BMUs */ 2816 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2817 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2818 SK_RX_RING_ADDR(sc_if, 0)); 2819 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2820 2821 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2822 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2823 SK_TX_RING_ADDR(sc_if, 0)); 2824 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2825 2826 /* Init descriptors */ 2827 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2828 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2829 "memory for rx buffers\n"); 2830 sk_stop(ifp, 0); 2831 splx(s); 2832 return ENOBUFS; 2833 } 2834 2835 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2836 aprint_error_dev(sc_if->sk_dev, "initialization failed: no " 2837 "memory for tx buffers\n"); 2838 sk_stop(ifp, 0); 2839 splx(s); 2840 return ENOBUFS; 2841 } 2842 2843 /* Set interrupt moderation if changed via sysctl. */ 2844 switch (sc->sk_type) { 2845 case SK_GENESIS: 2846 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2847 break; 2848 case SK_YUKON_EC: 2849 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2850 break; 2851 default: 2852 imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2853 } 2854 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2855 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2856 sk_win_write_4(sc, SK_IMTIMERINIT, 2857 SK_IM_USECS(sc->sk_int_mod)); 2858 aprint_verbose_dev(sc->sk_dev, 2859 "interrupt moderation is %d us\n", sc->sk_int_mod); 2860 } 2861 2862 /* Configure interrupt handling */ 2863 CSR_READ_4(sc, SK_ISSR); 2864 if (sc_if->sk_port == SK_PORT_A) 2865 sc->sk_intrmask |= SK_INTRS1; 2866 else 2867 sc->sk_intrmask |= SK_INTRS2; 2868 2869 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2870 2871 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2872 2873 /* Start BMUs. */ 2874 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2875 2876 if (sc->sk_type == SK_GENESIS) { 2877 /* Enable XMACs TX and RX state machines */ 2878 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2879 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2880 XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB); 2881 } 2882 2883 if (SK_YUKON_FAMILY(sc->sk_type)) { 2884 uint16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2885 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2886 #if 0 2887 /* XXX disable 100Mbps and full duplex mode? */ 2888 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN); 2889 #endif 2890 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2891 } 2892 2893 2894 ifp->if_flags |= IFF_RUNNING; 2895 ifp->if_flags &= ~IFF_OACTIVE; 2896 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2897 2898 out: 2899 splx(s); 2900 return rc; 2901 } 2902 2903 static void 2904 sk_stop(struct ifnet *ifp, int disable) 2905 { 2906 struct sk_if_softc *sc_if = ifp->if_softc; 2907 struct sk_softc *sc = sc_if->sk_softc; 2908 int i; 2909 2910 DPRINTFN(1, ("sk_stop\n")); 2911 2912 callout_stop(&sc_if->sk_tick_ch); 2913 2914 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2915 uint32_t val; 2916 2917 /* Put PHY back into reset. */ 2918 val = sk_win_read_4(sc, SK_GPIO); 2919 if (sc_if->sk_port == SK_PORT_A) { 2920 val |= SK_GPIO_DIR0; 2921 val &= ~SK_GPIO_DAT0; 2922 } else { 2923 val |= SK_GPIO_DIR2; 2924 val &= ~SK_GPIO_DAT2; 2925 } 2926 sk_win_write_4(sc, SK_GPIO, val); 2927 } 2928 2929 /* Turn off various components of this interface. */ 2930 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2931 switch (sc->sk_type) { 2932 case SK_GENESIS: 2933 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2934 SK_TXMACCTL_XMAC_RESET); 2935 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2936 break; 2937 case SK_YUKON: 2938 case SK_YUKON_LITE: 2939 case SK_YUKON_LP: 2940 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2941 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2942 break; 2943 } 2944 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2945 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET |SK_RBCTL_OFF); 2946 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2947 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2948 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2949 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2950 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2951 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2952 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2953 2954 /* Disable interrupts */ 2955 if (sc_if->sk_port == SK_PORT_A) 2956 sc->sk_intrmask &= ~SK_INTRS1; 2957 else 2958 sc->sk_intrmask &= ~SK_INTRS2; 2959 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2960 2961 SK_XM_READ_2(sc_if, XM_ISR); 2962 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2963 2964 /* Free RX and TX mbufs still in the queues. */ 2965 for (i = 0; i < SK_RX_RING_CNT; i++) { 2966 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2967 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2968 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2969 } 2970 } 2971 2972 for (i = 0; i < SK_TX_RING_CNT; i++) { 2973 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2974 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2975 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2976 } 2977 } 2978 2979 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2980 } 2981 2982 /* Power Management Framework */ 2983 2984 static bool 2985 skc_suspend(device_t dv, const pmf_qual_t *qual) 2986 { 2987 struct sk_softc *sc = device_private(dv); 2988 2989 DPRINTFN(2, ("skc_suspend\n")); 2990 2991 /* Turn off the driver is loaded LED */ 2992 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 2993 2994 return true; 2995 } 2996 2997 static bool 2998 skc_resume(device_t dv, const pmf_qual_t *qual) 2999 { 3000 struct sk_softc *sc = device_private(dv); 3001 3002 DPRINTFN(2, ("skc_resume\n")); 3003 3004 sk_reset(sc); 3005 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 3006 3007 return true; 3008 } 3009 3010 static bool 3011 sk_resume(device_t dv, const pmf_qual_t *qual) 3012 { 3013 struct sk_if_softc *sc_if = device_private(dv); 3014 3015 sk_init_yukon(sc_if); 3016 return true; 3017 } 3018 3019 CFATTACH_DECL_NEW(skc, sizeof(struct sk_softc), 3020 skc_probe, skc_attach, NULL, NULL); 3021 3022 CFATTACH_DECL_NEW(sk, sizeof(struct sk_if_softc), 3023 sk_probe, sk_attach, NULL, NULL); 3024 3025 #ifdef SK_DEBUG 3026 static void 3027 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 3028 { 3029 #define DESC_PRINT(X) \ 3030 if (X) \ 3031 printf("txdesc[%d]." #X "=%#x\n", \ 3032 idx, X); 3033 3034 DESC_PRINT(le32toh(desc->sk_ctl)); 3035 DESC_PRINT(le32toh(desc->sk_next)); 3036 DESC_PRINT(le32toh(desc->sk_data_lo)); 3037 DESC_PRINT(le32toh(desc->sk_data_hi)); 3038 DESC_PRINT(le32toh(desc->sk_xmac_txstat)); 3039 DESC_PRINT(le16toh(desc->sk_rsvd0)); 3040 DESC_PRINT(le16toh(desc->sk_csum_startval)); 3041 DESC_PRINT(le16toh(desc->sk_csum_startpos)); 3042 DESC_PRINT(le16toh(desc->sk_csum_writepos)); 3043 DESC_PRINT(le16toh(desc->sk_rsvd1)); 3044 #undef PRINT 3045 } 3046 3047 static void 3048 sk_dump_bytes(const char *data, int len) 3049 { 3050 int c, i, j; 3051 3052 for (i = 0; i < len; i += 16) { 3053 printf("%08x ", i); 3054 c = len - i; 3055 if (c > 16) c = 16; 3056 3057 for (j = 0; j < c; j++) { 3058 printf("%02x ", data[i + j] & 0xff); 3059 if ((j & 0xf) == 7 && j > 0) 3060 printf(" "); 3061 } 3062 3063 for (; j < 16; j++) 3064 printf(" "); 3065 printf(" "); 3066 3067 for (j = 0; j < c; j++) { 3068 int ch = data[i + j] & 0xff; 3069 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 3070 } 3071 3072 printf("\n"); 3073 3074 if (c < 16) 3075 break; 3076 } 3077 } 3078 3079 static void 3080 sk_dump_mbuf(struct mbuf *m) 3081 { 3082 int count = m->m_pkthdr.len; 3083 3084 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 3085 3086 while (count > 0 && m) { 3087 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 3088 m, m->m_data, m->m_len); 3089 sk_dump_bytes(mtod(m, char *), m->m_len); 3090 3091 count -= m->m_len; 3092 m = m->m_next; 3093 } 3094 } 3095 #endif 3096 3097 static int 3098 sk_sysctl_handler(SYSCTLFN_ARGS) 3099 { 3100 int error, t; 3101 struct sysctlnode node; 3102 struct sk_softc *sc; 3103 3104 node = *rnode; 3105 sc = node.sysctl_data; 3106 t = sc->sk_int_mod; 3107 node.sysctl_data = &t; 3108 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 3109 if (error || newp == NULL) 3110 return error; 3111 3112 if (t < SK_IM_MIN || t > SK_IM_MAX) 3113 return EINVAL; 3114 3115 /* update the softc with sysctl-changed value, and mark 3116 for hardware update */ 3117 sc->sk_int_mod = t; 3118 sc->sk_int_mod_pending = 1; 3119 return 0; 3120 } 3121 3122 /* 3123 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 3124 * set up in skc_attach() 3125 */ 3126 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 3127 { 3128 int rc; 3129 const struct sysctlnode *node; 3130 3131 if ((rc = sysctl_createv(clog, 0, NULL, &node, 3132 0, CTLTYPE_NODE, "sk", 3133 SYSCTL_DESCR("sk interface controls"), 3134 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 3135 goto err; 3136 } 3137 3138 sk_root_num = node->sysctl_num; 3139 return; 3140 3141 err: 3142 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 3143 } 3144
Indexes created Mon Sep 22 21:09:42 GMT 2025