if_sk.c revision 1.13
1 /* $NetBSD: if_sk.c,v 1.13 2005/01/23 03:06:07 fredb Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* $OpenBSD: if_sk.c,v 1.33 2003/08/12 05:23:06 nate Exp $ */ 37 38 /* 39 * Copyright (c) 1997, 1998, 1999, 2000 40 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Bill Paul. 53 * 4. Neither the name of the author nor the names of any co-contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 67 * THE POSSIBILITY OF SUCH DAMAGE. 68 * 69 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 70 */ 71 72 /* 73 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 74 * 75 * Permission to use, copy, modify, and distribute this software for any 76 * purpose with or without fee is hereby granted, provided that the above 77 * copyright notice and this permission notice appear in all copies. 78 * 79 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 80 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 81 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 82 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 83 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 84 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 85 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 86 */ 87 88 /* 89 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 90 * the SK-984x series adapters, both single port and dual port. 91 * References: 92 * The XaQti XMAC II datasheet, 93 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * The SysKonnect GEnesis manual, http://www.syskonnect.com 95 * 96 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 97 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 98 * convenience to others until Vitesse corrects this problem: 99 * 100 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 101 * 102 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 103 * Department of Electrical Engineering 104 * Columbia University, New York City 105 */ 106 107 /* 108 * The SysKonnect gigabit ethernet adapters consist of two main 109 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 110 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 111 * components and a PHY while the GEnesis controller provides a PCI 112 * interface with DMA support. Each card may have between 512K and 113 * 2MB of SRAM on board depending on the configuration. 114 * 115 * The SysKonnect GEnesis controller can have either one or two XMAC 116 * chips connected to it, allowing single or dual port NIC configurations. 117 * SysKonnect has the distinction of being the only vendor on the market 118 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 119 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 120 * XMAC registers. This driver takes advantage of these features to allow 121 * both XMACs to operate as independent interfaces. 122 */ 123 124 #include "bpfilter.h" 125 126 #include <sys/param.h> 127 #include <sys/systm.h> 128 #include <sys/sockio.h> 129 #include <sys/mbuf.h> 130 #include <sys/malloc.h> 131 #include <sys/kernel.h> 132 #include <sys/socket.h> 133 #include <sys/device.h> 134 #include <sys/queue.h> 135 #include <sys/callout.h> 136 137 #include <net/if.h> 138 #include <net/if_dl.h> 139 #include <net/if_types.h> 140 141 #ifdef INET 142 #include <netinet/in.h> 143 #include <netinet/in_systm.h> 144 #include <netinet/in_var.h> 145 #include <netinet/ip.h> 146 #include <netinet/if_ether.h> 147 #endif 148 149 #include <net/if_media.h> 150 151 #if NBPFILTER > 0 152 #include <net/bpf.h> 153 #endif 154 155 #include <dev/mii/mii.h> 156 #include <dev/mii/miivar.h> 157 #include <dev/mii/brgphyreg.h> 158 159 #include <dev/pci/pcireg.h> 160 #include <dev/pci/pcivar.h> 161 #include <dev/pci/pcidevs.h> 162 163 #define SK_VERBOSE 164 /* #define SK_USEIOSPACE */ 165 166 #include <dev/pci/if_skreg.h> 167 #include <dev/pci/if_skvar.h> 168 169 int skc_probe(struct device *, struct cfdata *, void *); 170 void skc_attach(struct device *, struct device *self, void *aux); 171 int sk_probe(struct device *, struct cfdata *, void *); 172 void sk_attach(struct device *, struct device *self, void *aux); 173 int skcprint(void *, const char *); 174 int sk_intr(void *); 175 void sk_intr_bcom(struct sk_if_softc *); 176 void sk_intr_xmac(struct sk_if_softc *); 177 void sk_intr_yukon(struct sk_if_softc *); 178 void sk_rxeof(struct sk_if_softc *); 179 void sk_txeof(struct sk_if_softc *); 180 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 181 void sk_start(struct ifnet *); 182 int sk_ioctl(struct ifnet *, u_long, caddr_t); 183 int sk_init(struct ifnet *); 184 void sk_init_xmac(struct sk_if_softc *); 185 void sk_init_yukon(struct sk_if_softc *); 186 void sk_stop(struct ifnet *, int); 187 void sk_watchdog(struct ifnet *); 188 void sk_shutdown(void *); 189 int sk_ifmedia_upd(struct ifnet *); 190 void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 191 void sk_reset(struct sk_softc *); 192 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 193 int sk_init_rx_ring(struct sk_if_softc *); 194 int sk_init_tx_ring(struct sk_if_softc *); 195 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 196 void sk_vpd_read_res(struct sk_softc *, 197 struct vpd_res *, int); 198 void sk_vpd_read(struct sk_softc *); 199 200 int sk_xmac_miibus_readreg(struct device *, int, int); 201 void sk_xmac_miibus_writereg(struct device *, int, int, int); 202 void sk_xmac_miibus_statchg(struct device *); 203 204 int sk_marv_miibus_readreg(struct device *, int, int); 205 void sk_marv_miibus_writereg(struct device *, int, int, int); 206 void sk_marv_miibus_statchg(struct device *); 207 208 u_int32_t sk_xmac_hash(caddr_t); 209 u_int32_t sk_yukon_hash(caddr_t); 210 void sk_setfilt(struct sk_if_softc *, caddr_t, int); 211 void sk_setmulti(struct sk_if_softc *); 212 void sk_tick(void *); 213 214 /* #define SK_DEBUG 2 */ 215 #ifdef SK_DEBUG 216 #define DPRINTF(x) if (skdebug) printf x 217 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 218 int skdebug = SK_DEBUG; 219 220 void sk_dump_txdesc(struct sk_tx_desc *, int); 221 void sk_dump_mbuf(struct mbuf *); 222 void sk_dump_bytes(const char *, int); 223 #else 224 #define DPRINTF(x) 225 #define DPRINTFN(n,x) 226 #endif 227 228 #define SK_SETBIT(sc, reg, x) \ 229 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 230 231 #define SK_CLRBIT(sc, reg, x) \ 232 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 233 234 #define SK_WIN_SETBIT_4(sc, reg, x) \ 235 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 236 237 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 238 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 239 240 #define SK_WIN_SETBIT_2(sc, reg, x) \ 241 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 242 243 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 244 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 245 246 /* supported device vendors */ 247 static const struct sk_product { 248 pci_vendor_id_t sk_vendor; 249 pci_product_id_t sk_product; 250 } sk_products[] = { 251 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 252 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 253 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, }, 254 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 255 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 256 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 257 { PCI_VENDOR_GALILEO, PCI_PRODUCT_GALILEO_SKNET, }, 258 { PCI_VENDOR_GALILEO, PCI_PRODUCT_GALILEO_BELKIN, }, 259 { 0, 0, } 260 }; 261 262 static inline u_int32_t 263 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 264 { 265 #ifdef SK_USEIOSPACE 266 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 267 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 268 #else 269 return CSR_READ_4(sc, reg); 270 #endif 271 } 272 273 static inline u_int16_t 274 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 275 { 276 #ifdef SK_USEIOSPACE 277 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 278 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 279 #else 280 return CSR_READ_2(sc, reg); 281 #endif 282 } 283 284 static inline u_int8_t 285 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 286 { 287 #ifdef SK_USEIOSPACE 288 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 289 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 290 #else 291 return CSR_READ_1(sc, reg); 292 #endif 293 } 294 295 static inline void 296 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 297 { 298 #ifdef SK_USEIOSPACE 299 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 300 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 301 #else 302 CSR_WRITE_4(sc, reg, x); 303 #endif 304 } 305 306 static inline void 307 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 308 { 309 #ifdef SK_USEIOSPACE 310 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 311 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 312 #else 313 CSR_WRITE_2(sc, reg, x); 314 #endif 315 } 316 317 static inline void 318 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 319 { 320 #ifdef SK_USEIOSPACE 321 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 322 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 323 #else 324 CSR_WRITE_1(sc, reg, x); 325 #endif 326 } 327 328 /* 329 * The VPD EEPROM contains Vital Product Data, as suggested in 330 * the PCI 2.1 specification. The VPD data is separared into areas 331 * denoted by resource IDs. The SysKonnect VPD contains an ID string 332 * resource (the name of the adapter), a read-only area resource 333 * containing various key/data fields and a read/write area which 334 * can be used to store asset management information or log messages. 335 * We read the ID string and read-only into buffers attached to 336 * the controller softc structure for later use. At the moment, 337 * we only use the ID string during sk_attach(). 338 */ 339 u_int8_t 340 sk_vpd_readbyte(struct sk_softc *sc, int addr) 341 { 342 int i; 343 344 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 345 for (i = 0; i < SK_TIMEOUT; i++) { 346 DELAY(1); 347 if (sk_win_read_2(sc, 348 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 349 break; 350 } 351 352 if (i == SK_TIMEOUT) 353 return(0); 354 355 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 356 } 357 358 void 359 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 360 { 361 int i; 362 u_int8_t *ptr; 363 364 ptr = (u_int8_t *)res; 365 for (i = 0; i < sizeof(struct vpd_res); i++) 366 ptr[i] = sk_vpd_readbyte(sc, i + addr); 367 } 368 369 void 370 sk_vpd_read(struct sk_softc *sc) 371 { 372 int pos = 0, i; 373 struct vpd_res res; 374 375 if (sc->sk_vpd_prodname != NULL) 376 free(sc->sk_vpd_prodname, M_DEVBUF); 377 if (sc->sk_vpd_readonly != NULL) 378 free(sc->sk_vpd_readonly, M_DEVBUF); 379 sc->sk_vpd_prodname = NULL; 380 sc->sk_vpd_readonly = NULL; 381 382 sk_vpd_read_res(sc, &res, pos); 383 384 if (res.vr_id != VPD_RES_ID) { 385 printf("%s: bad VPD resource id: expected %x got %x\n", 386 sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 387 return; 388 } 389 390 pos += sizeof(res); 391 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 392 if (sc->sk_vpd_prodname == NULL) 393 panic("sk_vpd_read"); 394 for (i = 0; i < res.vr_len; i++) 395 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 396 sc->sk_vpd_prodname[i] = '\0'; 397 pos += i; 398 399 sk_vpd_read_res(sc, &res, pos); 400 401 if (res.vr_id != VPD_RES_READ) { 402 printf("%s: bad VPD resource id: expected %x got %x\n", 403 sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 404 return; 405 } 406 407 pos += sizeof(res); 408 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 409 if (sc->sk_vpd_readonly == NULL) 410 panic("sk_vpd_read"); 411 for (i = 0; i < res.vr_len ; i++) 412 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 413 } 414 415 int 416 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 417 { 418 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 419 int i; 420 421 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 422 423 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 424 return(0); 425 426 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 427 SK_XM_READ_2(sc_if, XM_PHY_DATA); 428 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 429 for (i = 0; i < SK_TIMEOUT; i++) { 430 DELAY(1); 431 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 432 XM_MMUCMD_PHYDATARDY) 433 break; 434 } 435 436 if (i == SK_TIMEOUT) { 437 printf("%s: phy failed to come ready\n", 438 sc_if->sk_dev.dv_xname); 439 return(0); 440 } 441 } 442 DELAY(1); 443 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 444 } 445 446 void 447 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 448 { 449 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 450 int i; 451 452 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 453 454 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 455 for (i = 0; i < SK_TIMEOUT; i++) { 456 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 457 break; 458 } 459 460 if (i == SK_TIMEOUT) { 461 printf("%s: phy failed to come ready\n", 462 sc_if->sk_dev.dv_xname); 463 return; 464 } 465 466 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 467 for (i = 0; i < SK_TIMEOUT; i++) { 468 DELAY(1); 469 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 470 break; 471 } 472 473 if (i == SK_TIMEOUT) 474 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 475 } 476 477 void 478 sk_xmac_miibus_statchg(struct device *dev) 479 { 480 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 481 struct mii_data *mii = &sc_if->sk_mii; 482 483 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 484 485 /* 486 * If this is a GMII PHY, manually set the XMAC's 487 * duplex mode accordingly. 488 */ 489 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 490 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 491 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 492 } else { 493 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 494 } 495 } 496 } 497 498 int 499 sk_marv_miibus_readreg(dev, phy, reg) 500 struct device *dev; 501 int phy, reg; 502 { 503 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 504 u_int16_t val; 505 int i; 506 507 if (phy != 0 || 508 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 509 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 510 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 511 phy, reg)); 512 return(0); 513 } 514 515 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 516 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 517 518 for (i = 0; i < SK_TIMEOUT; i++) { 519 DELAY(1); 520 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 521 if (val & YU_SMICR_READ_VALID) 522 break; 523 } 524 525 if (i == SK_TIMEOUT) { 526 printf("%s: phy failed to come ready\n", 527 sc_if->sk_dev.dv_xname); 528 return 0; 529 } 530 531 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 532 SK_TIMEOUT)); 533 534 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 535 536 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 537 phy, reg, val)); 538 539 return val; 540 } 541 542 void 543 sk_marv_miibus_writereg(dev, phy, reg, val) 544 struct device *dev; 545 int phy, reg, val; 546 { 547 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 548 int i; 549 550 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 551 phy, reg, val)); 552 553 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 554 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 555 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 556 557 for (i = 0; i < SK_TIMEOUT; i++) { 558 DELAY(1); 559 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 560 break; 561 } 562 } 563 564 void 565 sk_marv_miibus_statchg(dev) 566 struct device *dev; 567 { 568 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 569 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 570 } 571 572 #define SK_HASH_BITS 6 573 574 u_int32_t 575 sk_xmac_hash(caddr_t addr) 576 { 577 u_int32_t crc; 578 579 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 580 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 581 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 582 return (crc); 583 } 584 585 u_int32_t 586 sk_yukon_hash(caddr_t addr) 587 { 588 u_int32_t crc; 589 590 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 591 crc &= ((1 << SK_HASH_BITS) - 1); 592 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 593 return (crc); 594 } 595 596 void 597 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 598 { 599 int base = XM_RXFILT_ENTRY(slot); 600 601 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 602 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 603 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 604 } 605 606 void 607 sk_setmulti(struct sk_if_softc *sc_if) 608 { 609 struct sk_softc *sc = sc_if->sk_softc; 610 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 611 u_int32_t hashes[2] = { 0, 0 }; 612 int h = 0, i; 613 struct ethercom *ec = &sc_if->sk_ethercom; 614 struct ether_multi *enm; 615 struct ether_multistep step; 616 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 617 618 /* First, zot all the existing filters. */ 619 switch(sc->sk_type) { 620 case SK_GENESIS: 621 for (i = 1; i < XM_RXFILT_MAX; i++) 622 sk_setfilt(sc_if, (caddr_t)&dummy, i); 623 624 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 625 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 626 break; 627 case SK_YUKON: 628 case SK_YUKON_LITE: 629 case SK_YUKON_LP: 630 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 631 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 632 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 633 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 634 break; 635 } 636 637 /* Now program new ones. */ 638 allmulti: 639 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 640 hashes[0] = 0xFFFFFFFF; 641 hashes[1] = 0xFFFFFFFF; 642 } else { 643 i = 1; 644 /* First find the tail of the list. */ 645 ETHER_FIRST_MULTI(step, ec, enm); 646 while (enm != NULL) { 647 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 648 ETHER_ADDR_LEN)) { 649 ifp->if_flags |= IFF_ALLMULTI; 650 goto allmulti; 651 } 652 DPRINTFN(2,("multicast address %s\n", 653 ether_sprintf(enm->enm_addrlo))); 654 /* 655 * Program the first XM_RXFILT_MAX multicast groups 656 * into the perfect filter. For all others, 657 * use the hash table. 658 */ 659 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 660 sk_setfilt(sc_if, enm->enm_addrlo, i); 661 i++; 662 } 663 else { 664 switch (sc->sk_type) { 665 case SK_GENESIS: 666 h = sk_xmac_hash(enm->enm_addrlo); 667 break; 668 case SK_YUKON: 669 case SK_YUKON_LITE: 670 case SK_YUKON_LP: 671 h = sk_yukon_hash(enm->enm_addrlo); 672 break; 673 } 674 if (h < 32) 675 hashes[0] |= (1 << h); 676 else 677 hashes[1] |= (1 << (h - 32)); 678 } 679 680 ETHER_NEXT_MULTI(step, enm); 681 } 682 } 683 684 switch(sc->sk_type) { 685 case SK_GENESIS: 686 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 687 XM_MODE_RX_USE_PERFECT); 688 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 689 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 690 break; 691 case SK_YUKON: 692 case SK_YUKON_LITE: 693 case SK_YUKON_LP: 694 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 695 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 696 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 697 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 698 break; 699 } 700 } 701 702 int 703 sk_init_rx_ring(struct sk_if_softc *sc_if) 704 { 705 struct sk_chain_data *cd = &sc_if->sk_cdata; 706 struct sk_ring_data *rd = sc_if->sk_rdata; 707 int i; 708 709 bzero((char *)rd->sk_rx_ring, 710 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 711 712 for (i = 0; i < SK_RX_RING_CNT; i++) { 713 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 714 if (i == (SK_RX_RING_CNT - 1)) { 715 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 716 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if, 0); 717 } else { 718 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 719 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if,i+1); 720 } 721 } 722 723 for (i = 0; i < SK_RX_RING_CNT; i++) { 724 if (sk_newbuf(sc_if, i, NULL, NULL) == ENOBUFS) { 725 printf("%s: failed alloc of %dth mbuf\n", 726 sc_if->sk_dev.dv_xname, i); 727 return(ENOBUFS); 728 } 729 } 730 sc_if->sk_cdata.sk_rx_prod = 0; 731 sc_if->sk_cdata.sk_rx_cons = 0; 732 733 return(0); 734 } 735 736 int 737 sk_init_tx_ring(struct sk_if_softc *sc_if) 738 { 739 struct sk_chain_data *cd = &sc_if->sk_cdata; 740 struct sk_ring_data *rd = sc_if->sk_rdata; 741 int i; 742 743 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 744 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 745 746 for (i = 0; i < SK_TX_RING_CNT; i++) { 747 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 748 if (i == (SK_TX_RING_CNT - 1)) { 749 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 750 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if, 0); 751 } else { 752 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 753 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if,i+1); 754 } 755 } 756 757 sc_if->sk_cdata.sk_tx_prod = 0; 758 sc_if->sk_cdata.sk_tx_cons = 0; 759 sc_if->sk_cdata.sk_tx_cnt = 0; 760 761 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 762 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 763 764 return (0); 765 } 766 767 int 768 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 769 bus_dmamap_t dmamap) 770 { 771 struct sk_softc *sc = sc_if->sk_softc; 772 struct mbuf *m_new = NULL; 773 struct sk_chain *c; 774 struct sk_rx_desc *r; 775 776 if (dmamap == NULL) { 777 /* if (m) panic() */ 778 779 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, MCLBYTES, 780 0, BUS_DMA_NOWAIT, &dmamap)) { 781 printf("%s: can't create recv map\n", 782 sc_if->sk_dev.dv_xname); 783 return(ENOMEM); 784 } 785 } else if (m == NULL) 786 bus_dmamap_unload(sc->sc_dmatag, dmamap); 787 788 sc_if->sk_cdata.sk_rx_map[i] = dmamap; 789 790 if (m == NULL) { 791 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 792 if (m_new == NULL) { 793 printf("%s: no memory for rx list -- " 794 "packet dropped!\n", sc_if->sk_dev.dv_xname); 795 return(ENOBUFS); 796 } 797 798 /* Allocate the jumbo buffer */ 799 MCLGET(m_new, M_DONTWAIT); 800 if (!(m_new->m_flags & M_EXT)) { 801 m_freem(m_new); 802 return (ENOBUFS); 803 } 804 805 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 806 807 m_adj(m_new, ETHER_ALIGN); 808 809 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m_new, 810 BUS_DMA_NOWAIT)) 811 return(ENOBUFS); 812 } else { 813 /* 814 * We're re-using a previously allocated mbuf; 815 * be sure to re-init pointers and lengths to 816 * default values. 817 */ 818 m_new = m; 819 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 820 m_adj(m_new, ETHER_ALIGN); 821 m_new->m_data = m_new->m_ext.ext_buf; 822 } 823 824 c = &sc_if->sk_cdata.sk_rx_chain[i]; 825 r = c->sk_desc; 826 c->sk_mbuf = m_new; 827 r->sk_data_lo = dmamap->dm_segs[0].ds_addr; 828 r->sk_ctl = dmamap->dm_segs[0].ds_len | SK_RXSTAT; 829 830 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 831 832 return(0); 833 } 834 835 /* 836 * Set media options. 837 */ 838 int 839 sk_ifmedia_upd(struct ifnet *ifp) 840 { 841 struct sk_if_softc *sc_if = ifp->if_softc; 842 843 (void) sk_init(ifp); 844 mii_mediachg(&sc_if->sk_mii); 845 return(0); 846 } 847 848 /* 849 * Report current media status. 850 */ 851 void 852 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 853 { 854 struct sk_if_softc *sc_if = ifp->if_softc; 855 856 mii_pollstat(&sc_if->sk_mii); 857 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 858 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 859 } 860 861 int 862 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 863 { 864 struct sk_if_softc *sc_if = ifp->if_softc; 865 struct sk_softc *sc = sc_if->sk_softc; 866 struct ifreq *ifr = (struct ifreq *) data; 867 /* struct ifaddr *ifa = (struct ifaddr *) data; */ 868 struct mii_data *mii; 869 int s, error = 0; 870 871 /* DPRINTFN(2, ("sk_ioctl\n")); */ 872 873 s = splnet(); 874 875 switch(command) { 876 877 case SIOCSIFFLAGS: 878 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 879 if (ifp->if_flags & IFF_UP) { 880 if (ifp->if_flags & IFF_RUNNING && 881 ifp->if_flags & IFF_PROMISC && 882 !(sc_if->sk_if_flags & IFF_PROMISC)) { 883 switch(sc->sk_type) { 884 case SK_GENESIS: 885 SK_XM_SETBIT_4(sc_if, XM_MODE, 886 XM_MODE_RX_PROMISC); 887 break; 888 case SK_YUKON: 889 case SK_YUKON_LITE: 890 case SK_YUKON_LP: 891 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 892 YU_RCR_UFLEN | YU_RCR_MUFLEN); 893 break; 894 } 895 sk_setmulti(sc_if); 896 } else if (ifp->if_flags & IFF_RUNNING && 897 !(ifp->if_flags & IFF_PROMISC) && 898 sc_if->sk_if_flags & IFF_PROMISC) { 899 switch(sc->sk_type) { 900 case SK_GENESIS: 901 SK_XM_CLRBIT_4(sc_if, XM_MODE, 902 XM_MODE_RX_PROMISC); 903 break; 904 case SK_YUKON: 905 case SK_YUKON_LITE: 906 case SK_YUKON_LP: 907 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 908 YU_RCR_UFLEN | YU_RCR_MUFLEN); 909 break; 910 } 911 912 sk_setmulti(sc_if); 913 } else 914 (void) sk_init(ifp); 915 } else { 916 if (ifp->if_flags & IFF_RUNNING) 917 sk_stop(ifp,0); 918 } 919 sc_if->sk_if_flags = ifp->if_flags; 920 error = 0; 921 break; 922 923 case SIOCGIFMEDIA: 924 case SIOCSIFMEDIA: 925 DPRINTFN(2, ("sk_ioctl MEDIA\n")); 926 mii = &sc_if->sk_mii; 927 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 928 break; 929 default: 930 DPRINTFN(2, ("sk_ioctl ETHER\n")); 931 error = ether_ioctl(ifp, command, data); 932 933 if ( error == ENETRESET) { 934 if (ifp->if_flags & IFF_RUNNING) { 935 sk_setmulti(sc_if); 936 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 937 } 938 error = 0; 939 } else if ( error ) { 940 splx(s); 941 return error; 942 } 943 break; 944 } 945 946 splx(s); 947 return(error); 948 } 949 950 /* 951 * Lookup: Check the PCI vendor and device, and return a pointer to 952 * The structure if the IDs match against our list. 953 */ 954 955 static const struct sk_product * 956 sk_lookup(const struct pci_attach_args *pa) 957 { 958 const struct sk_product *psk; 959 960 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 961 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 962 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 963 return (psk); 964 } 965 return (NULL); 966 } 967 968 /* 969 * Probe for a SysKonnect GEnesis chip. 970 */ 971 972 int 973 skc_probe(struct device *parent, struct cfdata *match, void *aux) 974 { 975 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 976 const struct sk_product *psk; 977 978 if ((psk = sk_lookup(pa))) { 979 return(1); 980 } 981 return(0); 982 } 983 984 /* 985 * Force the GEnesis into reset, then bring it out of reset. 986 */ 987 void sk_reset(struct sk_softc *sc) 988 { 989 DPRINTFN(2, ("sk_reset\n")); 990 991 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 992 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 993 if (SK_YUKON_FAMILY(sc->sk_type)) 994 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 995 996 DELAY(1000); 997 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 998 DELAY(2); 999 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1000 if (SK_YUKON_FAMILY(sc->sk_type)) 1001 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1002 1003 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1004 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1005 CSR_READ_2(sc, SK_LINK_CTRL))); 1006 1007 if (sc->sk_type == SK_GENESIS) { 1008 /* Configure packet arbiter */ 1009 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1010 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1011 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1012 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1013 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1014 } 1015 1016 /* Enable RAM interface */ 1017 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1018 1019 /* 1020 * Configure interrupt moderation. The moderation timer 1021 * defers interrupts specified in the interrupt moderation 1022 * timer mask based on the timeout specified in the interrupt 1023 * moderation timer init register. Each bit in the timer 1024 * register represents 18.825ns, so to specify a timeout in 1025 * microseconds, we have to multiply by 54. 1026 */ 1027 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(100)); 1028 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1029 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1030 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1031 } 1032 1033 int 1034 sk_probe(struct device *parent, struct cfdata *match, void *aux) 1035 { 1036 struct skc_attach_args *sa = aux; 1037 1038 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1039 return(0); 1040 1041 return (1); 1042 } 1043 1044 /* 1045 * Each XMAC chip is attached as a separate logical IP interface. 1046 * Single port cards will have only one logical interface of course. 1047 */ 1048 void 1049 sk_attach(struct device *parent, struct device *self, void *aux) 1050 { 1051 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1052 struct sk_softc *sc = (struct sk_softc *)parent; 1053 struct skc_attach_args *sa = aux; 1054 struct sk_txmap_entry *entry; 1055 struct ifnet *ifp; 1056 bus_dma_segment_t seg; 1057 bus_dmamap_t dmamap; 1058 caddr_t kva; 1059 int i, rseg; 1060 1061 sc_if->sk_port = sa->skc_port; 1062 sc_if->sk_softc = sc; 1063 sc->sk_if[sa->skc_port] = sc_if; 1064 1065 if (sa->skc_port == SK_PORT_A) 1066 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1067 if (sa->skc_port == SK_PORT_B) 1068 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1069 1070 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1071 1072 /* 1073 * Get station address for this interface. Note that 1074 * dual port cards actually come with three station 1075 * addresses: one for each port, plus an extra. The 1076 * extra one is used by the SysKonnect driver software 1077 * as a 'virtual' station address for when both ports 1078 * are operating in failover mode. Currently we don't 1079 * use this extra address. 1080 */ 1081 for (i = 0; i < ETHER_ADDR_LEN; i++) 1082 sc_if->sk_enaddr[i] = 1083 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1084 1085 1086 aprint_normal(": Ethernet address %s\n", 1087 ether_sprintf(sc_if->sk_enaddr)); 1088 1089 /* 1090 * Set up RAM buffer addresses. The NIC will have a certain 1091 * amount of SRAM on it, somewhere between 512K and 2MB. We 1092 * need to divide this up a) between the transmitter and 1093 * receiver and b) between the two XMACs, if this is a 1094 * dual port NIC. Our algotithm is to divide up the memory 1095 * evenly so that everyone gets a fair share. 1096 */ 1097 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1098 u_int32_t chunk, val; 1099 1100 chunk = sc->sk_ramsize / 2; 1101 val = sc->sk_rboff / sizeof(u_int64_t); 1102 sc_if->sk_rx_ramstart = val; 1103 val += (chunk / sizeof(u_int64_t)); 1104 sc_if->sk_rx_ramend = val - 1; 1105 sc_if->sk_tx_ramstart = val; 1106 val += (chunk / sizeof(u_int64_t)); 1107 sc_if->sk_tx_ramend = val - 1; 1108 } else { 1109 u_int32_t chunk, val; 1110 1111 chunk = sc->sk_ramsize / 4; 1112 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1113 sizeof(u_int64_t); 1114 sc_if->sk_rx_ramstart = val; 1115 val += (chunk / sizeof(u_int64_t)); 1116 sc_if->sk_rx_ramend = val - 1; 1117 sc_if->sk_tx_ramstart = val; 1118 val += (chunk / sizeof(u_int64_t)); 1119 sc_if->sk_tx_ramend = val - 1; 1120 } 1121 1122 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1123 " tx_ramstart=%#x tx_ramend=%#x\n", 1124 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1125 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1126 1127 /* Read and save PHY type and set PHY address */ 1128 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1129 switch (sc_if->sk_phytype) { 1130 case SK_PHYTYPE_XMAC: 1131 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1132 break; 1133 case SK_PHYTYPE_BCOM: 1134 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1135 break; 1136 case SK_PHYTYPE_MARV_COPPER: 1137 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1138 break; 1139 default: 1140 aprint_error("%s: unsupported PHY type: %d\n", 1141 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1142 return; 1143 } 1144 1145 /* Allocate the descriptor queues. */ 1146 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1147 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1148 aprint_error("%s: can't alloc rx buffers\n", 1149 sc->sk_dev.dv_xname); 1150 goto fail; 1151 } 1152 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1153 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1154 aprint_error("%s: can't map dma buffers (%lu bytes)\n", 1155 sc_if->sk_dev.dv_xname, 1156 (u_long) sizeof(struct sk_ring_data)); 1157 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1158 goto fail; 1159 } 1160 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1161 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1162 &sc_if->sk_ring_map)) { 1163 aprint_error("%s: can't create dma map\n", 1164 sc_if->sk_dev.dv_xname); 1165 bus_dmamem_unmap(sc->sc_dmatag, kva, 1166 sizeof(struct sk_ring_data)); 1167 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1168 goto fail; 1169 } 1170 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1171 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1172 aprint_error("%s: can't load dma map\n", 1173 sc_if->sk_dev.dv_xname); 1174 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1175 bus_dmamem_unmap(sc->sc_dmatag, kva, 1176 sizeof(struct sk_ring_data)); 1177 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1178 goto fail; 1179 } 1180 1181 for (i = 0; i < SK_RX_RING_CNT; i++) 1182 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1183 1184 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1185 for (i = 0; i < SK_TX_RING_CNT; i++) { 1186 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1187 1188 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, SK_NTXSEG, 1189 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap)) { 1190 aprint_error("%s: Can't create TX dmamap\n", 1191 sc_if->sk_dev.dv_xname); 1192 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1193 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1194 bus_dmamem_unmap(sc->sc_dmatag, kva, 1195 sizeof(struct sk_ring_data)); 1196 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1197 goto fail; 1198 } 1199 1200 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1201 if (!entry) { 1202 aprint_error("%s: Can't alloc txmap entry\n", 1203 sc_if->sk_dev.dv_xname); 1204 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1205 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1206 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1207 bus_dmamem_unmap(sc->sc_dmatag, kva, 1208 sizeof(struct sk_ring_data)); 1209 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1210 goto fail; 1211 } 1212 entry->dmamap = dmamap; 1213 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1214 } 1215 1216 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1217 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1218 1219 /* XXX TLS It's not clear what's wrong with the Jumbo MTU 1220 XXX TLS support in this driver, so we don't enable it. */ 1221 1222 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1223 1224 ifp = &sc_if->sk_ethercom.ec_if; 1225 ifp->if_softc = sc_if; 1226 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1227 ifp->if_ioctl = sk_ioctl; 1228 ifp->if_start = sk_start; 1229 ifp->if_stop = sk_stop; 1230 ifp->if_init = sk_init; 1231 ifp->if_watchdog = sk_watchdog; 1232 ifp->if_capabilities = 0; 1233 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1234 IFQ_SET_READY(&ifp->if_snd); 1235 strcpy(ifp->if_xname, sc_if->sk_dev.dv_xname); 1236 1237 /* 1238 * Do miibus setup. 1239 */ 1240 switch (sc->sk_type) { 1241 case SK_GENESIS: 1242 sk_init_xmac(sc_if); 1243 break; 1244 case SK_YUKON: 1245 case SK_YUKON_LITE: 1246 case SK_YUKON_LP: 1247 sk_init_yukon(sc_if); 1248 break; 1249 default: 1250 panic("%s: unknown device type %d", sc->sk_dev.dv_xname, 1251 sc->sk_type); 1252 } 1253 1254 DPRINTFN(2, ("sk_attach: 1\n")); 1255 1256 sc_if->sk_mii.mii_ifp = ifp; 1257 switch (sc->sk_type) { 1258 case SK_GENESIS: 1259 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1260 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1261 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1262 break; 1263 case SK_YUKON: 1264 case SK_YUKON_LITE: 1265 case SK_YUKON_LP: 1266 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1267 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1268 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1269 break; 1270 } 1271 1272 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1273 sk_ifmedia_upd, sk_ifmedia_sts); 1274 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1275 MII_OFFSET_ANY, 0); 1276 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1277 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1278 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1279 0, NULL); 1280 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1281 } 1282 else 1283 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1284 1285 callout_init(&sc_if->sk_tick_ch); 1286 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1287 1288 DPRINTFN(2, ("sk_attach: 1\n")); 1289 1290 /* 1291 * Call MI attach routines. 1292 */ 1293 if_attach(ifp); 1294 1295 ether_ifattach(ifp, sc_if->sk_enaddr); 1296 1297 #if NRND > 0 1298 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1299 RND_TYPE_NET, 0); 1300 #endif 1301 1302 DPRINTFN(2, ("sk_attach: end\n")); 1303 1304 return; 1305 1306 fail: 1307 sc->sk_if[sa->skc_port] = NULL; 1308 } 1309 1310 int 1311 skcprint(void *aux, const char *pnp) 1312 { 1313 struct skc_attach_args *sa = aux; 1314 1315 if (pnp) 1316 aprint_normal("sk port %c at %s", 1317 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1318 else 1319 aprint_normal(" port %c", 1320 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1321 return (UNCONF); 1322 } 1323 1324 /* 1325 * Attach the interface. Allocate softc structures, do ifmedia 1326 * setup and ethernet/BPF attach. 1327 */ 1328 void 1329 skc_attach(struct device *parent, struct device *self, void *aux) 1330 { 1331 struct sk_softc *sc = (struct sk_softc *)self; 1332 struct pci_attach_args *pa = aux; 1333 struct skc_attach_args skca; 1334 pci_chipset_tag_t pc = pa->pa_pc; 1335 pcireg_t memtype; 1336 pci_intr_handle_t ih; 1337 const char *intrstr = NULL; 1338 bus_addr_t iobase; 1339 bus_size_t iosize; 1340 int s; 1341 u_int32_t command; 1342 char *revstr; 1343 1344 DPRINTFN(2, ("begin skc_attach\n")); 1345 1346 s = splnet(); 1347 1348 /* 1349 * Handle power management nonsense. 1350 */ 1351 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1352 1353 if (command == 0x01) { 1354 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1355 if (command & SK_PSTATE_MASK) { 1356 u_int32_t iobase, membase, irq; 1357 1358 /* Save important PCI config data. */ 1359 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1360 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1361 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1362 1363 /* Reset the power state. */ 1364 aprint_normal("%s chip is in D%d power mode " 1365 "-- setting to D0\n", sc->sk_dev.dv_xname, 1366 command & SK_PSTATE_MASK); 1367 command &= 0xFFFFFFFC; 1368 pci_conf_write(pc, pa->pa_tag, 1369 SK_PCI_PWRMGMTCTRL, command); 1370 1371 /* Restore PCI config data. */ 1372 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1373 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1374 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1375 } 1376 } 1377 1378 /* 1379 * Map control/status registers. 1380 */ 1381 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1382 command |= PCI_COMMAND_IO_ENABLE | 1383 PCI_COMMAND_MEM_ENABLE | 1384 PCI_COMMAND_MASTER_ENABLE; 1385 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1386 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1387 1388 #ifdef SK_USEIOSPACE 1389 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1390 aprint_error(": failed to enable I/O ports!\n"); 1391 goto fail; 1392 } 1393 /* 1394 * Map control/status registers. 1395 */ 1396 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1397 &iobase, &iosize)) { 1398 aprint_error(": can't find i/o space\n"); 1399 goto fail; 1400 } 1401 #else 1402 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1403 aprint_error(": failed to enable memory mapping!\n"); 1404 goto fail; 1405 } 1406 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1407 switch (memtype) { 1408 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1409 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1410 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1411 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1412 &iobase, &iosize) == 0) 1413 break; 1414 default: 1415 aprint_error("%s: can't find mem space\n", 1416 sc->sk_dev.dv_xname); 1417 return; 1418 } 1419 1420 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1421 #endif 1422 sc->sc_dmatag = pa->pa_dmat; 1423 1424 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1425 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1426 1427 /* bail out here if chip is not recognized */ 1428 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1429 aprint_error("%s: unknown chip type\n",sc->sk_dev.dv_xname); 1430 goto fail; 1431 } 1432 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1433 1434 /* Allocate interrupt */ 1435 if (pci_intr_map(pa, &ih)) { 1436 aprint_error(": couldn't map interrupt\n"); 1437 goto fail; 1438 } 1439 1440 intrstr = pci_intr_string(pc, ih); 1441 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1442 if (sc->sk_intrhand == NULL) { 1443 aprint_error(": couldn't establish interrupt"); 1444 if (intrstr != NULL) 1445 aprint_normal(" at %s", intrstr); 1446 goto fail; 1447 } 1448 aprint_normal(": %s\n", intrstr); 1449 1450 /* Reset the adapter. */ 1451 sk_reset(sc); 1452 1453 /* Read and save vital product data from EEPROM. */ 1454 sk_vpd_read(sc); 1455 1456 if (sc->sk_type == SK_GENESIS) { 1457 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1458 /* Read and save RAM size and RAMbuffer offset */ 1459 switch(val) { 1460 case SK_RAMSIZE_512K_64: 1461 sc->sk_ramsize = 0x80000; 1462 sc->sk_rboff = SK_RBOFF_0; 1463 break; 1464 case SK_RAMSIZE_1024K_64: 1465 sc->sk_ramsize = 0x100000; 1466 sc->sk_rboff = SK_RBOFF_80000; 1467 break; 1468 case SK_RAMSIZE_1024K_128: 1469 sc->sk_ramsize = 0x100000; 1470 sc->sk_rboff = SK_RBOFF_0; 1471 break; 1472 case SK_RAMSIZE_2048K_128: 1473 sc->sk_ramsize = 0x200000; 1474 sc->sk_rboff = SK_RBOFF_0; 1475 break; 1476 default: 1477 aprint_error("%s: unknown ram size: %d\n", 1478 sc->sk_dev.dv_xname, val); 1479 goto fail; 1480 break; 1481 } 1482 1483 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1484 sc->sk_ramsize, sc->sk_ramsize / 1024, 1485 sc->sk_rboff)); 1486 } else { 1487 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1488 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1489 sc->sk_rboff = SK_RBOFF_0; 1490 1491 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1492 sc->sk_ramsize / 1024, sc->sk_ramsize, 1493 sc->sk_rboff)); 1494 } 1495 1496 /* Read and save physical media type */ 1497 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1498 case SK_PMD_1000BASESX: 1499 sc->sk_pmd = IFM_1000_SX; 1500 break; 1501 case SK_PMD_1000BASELX: 1502 sc->sk_pmd = IFM_1000_LX; 1503 break; 1504 case SK_PMD_1000BASECX: 1505 sc->sk_pmd = IFM_1000_CX; 1506 break; 1507 case SK_PMD_1000BASETX: 1508 sc->sk_pmd = IFM_1000_T; 1509 break; 1510 default: 1511 aprint_error("%s: unknown media type: 0x%x\n", 1512 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1513 goto fail; 1514 } 1515 1516 /* determine whether to name it with vpd or just make it up */ 1517 /* Marvell Yukon VPD's can freqently be bogus */ 1518 1519 switch (pa->pa_id) { 1520 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1521 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1522 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1523 case PCI_PRODUCT_3COM_3C940: 1524 case PCI_PRODUCT_DLINK_DGE530T: 1525 case PCI_PRODUCT_LINKSYS_EG1032: 1526 case PCI_PRODUCT_LINKSYS_EG1064: 1527 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1528 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1529 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1530 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1531 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1532 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1533 sc->sk_name = sc->sk_vpd_prodname; 1534 break; 1535 case PCI_ID_CODE(PCI_VENDOR_GALILEO,PCI_PRODUCT_GALILEO_SKNET): 1536 /* whoops yukon vpd prodname bears no resemblance to reality */ 1537 switch (sc->sk_type) { 1538 case SK_GENESIS: 1539 sc->sk_name = sc->sk_vpd_prodname; 1540 break; 1541 case SK_YUKON: 1542 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1543 break; 1544 case SK_YUKON_LITE: 1545 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1546 break; 1547 case SK_YUKON_LP: 1548 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1549 break; 1550 default: 1551 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1552 } 1553 1554 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1555 1556 if ( sc->sk_type == SK_YUKON ) { 1557 uint32_t flashaddr; 1558 uint8_t testbyte; 1559 1560 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1561 1562 /* test Flash-Address Register */ 1563 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1564 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1565 1566 if (testbyte != 0) { 1567 /* this is yukon lite Rev. A0 */ 1568 sc->sk_type = SK_YUKON_LITE; 1569 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1570 /* restore Flash-Address Register */ 1571 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1572 } 1573 } 1574 break; 1575 case PCI_ID_CODE(PCI_VENDOR_GALILEO,PCI_PRODUCT_GALILEO_BELKIN): 1576 sc->sk_name = sc->sk_vpd_prodname; 1577 break; 1578 default: 1579 sc->sk_name = "Unkown Marvell"; 1580 } 1581 1582 1583 if ( sc->sk_type == SK_YUKON_LITE ) { 1584 switch (sc->sk_rev) { 1585 case SK_YUKON_LITE_REV_A0: 1586 revstr = "A0"; 1587 break; 1588 case SK_YUKON_LITE_REV_A1: 1589 revstr = "A1"; 1590 break; 1591 case SK_YUKON_LITE_REV_A3: 1592 revstr = "A3"; 1593 break; 1594 default: 1595 revstr = ""; 1596 } 1597 } else { 1598 revstr = ""; 1599 } 1600 1601 /* Announce the product name. */ 1602 aprint_normal("%s: %s rev. %s(0x%x)\n", sc->sk_dev.dv_xname, 1603 sc->sk_name, revstr, sc->sk_rev); 1604 1605 skca.skc_port = SK_PORT_A; 1606 (void)config_found(&sc->sk_dev, &skca, skcprint); 1607 1608 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1609 skca.skc_port = SK_PORT_B; 1610 (void)config_found(&sc->sk_dev, &skca, skcprint); 1611 } 1612 1613 /* Turn on the 'driver is loaded' LED. */ 1614 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1615 1616 fail: 1617 splx(s); 1618 } 1619 1620 int 1621 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1622 { 1623 struct sk_softc *sc = sc_if->sk_softc; 1624 struct sk_tx_desc *f = NULL; 1625 u_int32_t frag, cur, cnt = 0; 1626 int i; 1627 struct sk_txmap_entry *entry; 1628 bus_dmamap_t txmap; 1629 1630 DPRINTFN(3, ("sk_encap\n")); 1631 1632 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1633 if (entry == NULL) { 1634 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1635 return ENOBUFS; 1636 } 1637 txmap = entry->dmamap; 1638 1639 cur = frag = *txidx; 1640 1641 #ifdef SK_DEBUG 1642 if (skdebug >= 3) 1643 sk_dump_mbuf(m_head); 1644 #endif 1645 1646 /* 1647 * Start packing the mbufs in this chain into 1648 * the fragment pointers. Stop when we run out 1649 * of fragments or hit the end of the mbuf chain. 1650 */ 1651 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1652 BUS_DMA_NOWAIT)) { 1653 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1654 return(ENOBUFS); 1655 } 1656 1657 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1658 1659 /* Sync the DMA map. */ 1660 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1661 BUS_DMASYNC_PREWRITE); 1662 1663 for (i = 0; i < txmap->dm_nsegs; i++) { 1664 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1665 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1666 return(ENOBUFS); 1667 } 1668 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1669 f->sk_data_lo = txmap->dm_segs[i].ds_addr; 1670 f->sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1671 if (cnt == 0) 1672 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1673 else 1674 f->sk_ctl |= SK_TXCTL_OWN; 1675 1676 cur = frag; 1677 SK_INC(frag, SK_TX_RING_CNT); 1678 cnt++; 1679 } 1680 1681 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1682 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1683 1684 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1685 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1686 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1687 1688 /* Sync descriptors before handing to chip */ 1689 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1690 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1691 1692 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1693 1694 /* Sync first descriptor to hand it off */ 1695 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1696 1697 sc_if->sk_cdata.sk_tx_cnt += cnt; 1698 1699 #ifdef SK_DEBUG 1700 if (skdebug >= 3) { 1701 struct sk_tx_desc *desc; 1702 u_int32_t idx; 1703 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1704 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1705 sk_dump_txdesc(desc, idx); 1706 } 1707 } 1708 #endif 1709 1710 *txidx = frag; 1711 1712 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1713 1714 return(0); 1715 } 1716 1717 void 1718 sk_start(struct ifnet *ifp) 1719 { 1720 struct sk_if_softc *sc_if = ifp->if_softc; 1721 struct sk_softc *sc = sc_if->sk_softc; 1722 struct mbuf *m_head = NULL; 1723 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1724 int pkts = 0; 1725 1726 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1727 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1728 1729 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1730 1731 IFQ_POLL(&ifp->if_snd, m_head); 1732 if (m_head == NULL) 1733 break; 1734 1735 /* 1736 * Pack the data into the transmit ring. If we 1737 * don't have room, set the OACTIVE flag and wait 1738 * for the NIC to drain the ring. 1739 */ 1740 if (sk_encap(sc_if, m_head, &idx)) { 1741 ifp->if_flags |= IFF_OACTIVE; 1742 break; 1743 } 1744 1745 /* now we are committed to transmit the packet */ 1746 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1747 pkts++; 1748 1749 /* 1750 * If there's a BPF listener, bounce a copy of this frame 1751 * to him. 1752 */ 1753 #if NBPFILTER > 0 1754 if (ifp->if_bpf) 1755 bpf_mtap(ifp->if_bpf, m_head); 1756 #endif 1757 } 1758 if (pkts == 0) 1759 return; 1760 1761 /* Transmit */ 1762 sc_if->sk_cdata.sk_tx_prod = idx; 1763 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1764 1765 /* Set a timeout in case the chip goes out to lunch. */ 1766 ifp->if_timer = 5; 1767 } 1768 1769 1770 void 1771 sk_watchdog(struct ifnet *ifp) 1772 { 1773 struct sk_if_softc *sc_if = ifp->if_softc; 1774 1775 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1776 (void) sk_init(ifp); 1777 } 1778 1779 void 1780 sk_shutdown(void * v) 1781 { 1782 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 1783 struct sk_softc *sc = sc_if->sk_softc; 1784 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1785 1786 DPRINTFN(2, ("sk_shutdown\n")); 1787 sk_stop(ifp,1); 1788 1789 /* Turn off the 'driver is loaded' LED. */ 1790 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1791 1792 /* 1793 * Reset the GEnesis controller. Doing this should also 1794 * assert the resets on the attached XMAC(s). 1795 */ 1796 sk_reset(sc); 1797 } 1798 1799 void 1800 sk_rxeof(struct sk_if_softc *sc_if) 1801 { 1802 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1803 struct mbuf *m; 1804 struct sk_chain *cur_rx; 1805 struct sk_rx_desc *cur_desc; 1806 int i, cur, total_len = 0; 1807 u_int32_t rxstat; 1808 bus_dmamap_t dmamap; 1809 1810 i = sc_if->sk_cdata.sk_rx_prod; 1811 1812 DPRINTFN(3, ("sk_rxeof %d\n", i)); 1813 1814 for (;;) { 1815 cur = i; 1816 1817 /* Sync the descriptor */ 1818 SK_CDRXSYNC(sc_if, cur, 1819 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1820 1821 if (sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl & SK_RXCTL_OWN) { 1822 /* Invalidate the descriptor -- it's not ready yet */ 1823 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 1824 sc_if->sk_cdata.sk_rx_prod = i; 1825 break; 1826 } 1827 1828 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1829 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 1830 dmamap = sc_if->sk_cdata.sk_rx_map[cur]; 1831 1832 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1833 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1834 1835 rxstat = cur_desc->sk_xmac_rxstat; 1836 m = cur_rx->sk_mbuf; 1837 cur_rx->sk_mbuf = NULL; 1838 total_len = SK_RXBYTES(cur_desc->sk_ctl); 1839 1840 sc_if->sk_cdata.sk_rx_map[cur] = 0; 1841 1842 SK_INC(i, SK_RX_RING_CNT); 1843 1844 if (rxstat & XM_RXSTAT_ERRFRAME) { 1845 ifp->if_ierrors++; 1846 sk_newbuf(sc_if, cur, m, dmamap); 1847 continue; 1848 } 1849 1850 /* 1851 * Try to allocate a new jumbo buffer. If that 1852 * fails, copy the packet to mbufs and put the 1853 * jumbo buffer back in the ring so it can be 1854 * re-used. If allocating mbufs fails, then we 1855 * have to drop the packet. 1856 */ 1857 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1858 struct mbuf *m0; 1859 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1860 total_len + ETHER_ALIGN, 0, ifp, NULL); 1861 sk_newbuf(sc_if, cur, m, dmamap); 1862 if (m0 == NULL) { 1863 printf("%s: no receive buffers " 1864 "available -- packet dropped!\n", 1865 sc_if->sk_dev.dv_xname); 1866 ifp->if_ierrors++; 1867 continue; 1868 } 1869 m_adj(m0, ETHER_ALIGN); 1870 m = m0; 1871 } else { 1872 m->m_pkthdr.rcvif = ifp; 1873 m->m_pkthdr.len = m->m_len = total_len; 1874 } 1875 1876 ifp->if_ipackets++; 1877 1878 #if NBPFILTER > 0 1879 if (ifp->if_bpf) 1880 bpf_mtap(ifp->if_bpf, m); 1881 #endif 1882 /* pass it on. */ 1883 (*ifp->if_input)(ifp, m); 1884 } 1885 } 1886 1887 void 1888 sk_txeof(struct sk_if_softc *sc_if) 1889 { 1890 struct sk_softc *sc = sc_if->sk_softc; 1891 struct sk_tx_desc *cur_tx = NULL; 1892 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1893 u_int32_t idx; 1894 struct sk_txmap_entry *entry; 1895 1896 DPRINTFN(3, ("sk_txeof\n")); 1897 1898 /* 1899 * Go through our tx ring and free mbufs for those 1900 * frames that have been sent. 1901 */ 1902 idx = sc_if->sk_cdata.sk_tx_cons; 1903 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1904 SK_CDTXSYNC(sc_if, idx, 1, 1905 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1906 1907 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1908 #ifdef SK_DEBUG 1909 if (skdebug >= 3) 1910 sk_dump_txdesc(cur_tx, idx); 1911 #endif 1912 if (cur_tx->sk_ctl & SK_TXCTL_OWN) { 1913 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 1914 break; 1915 } 1916 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1917 ifp->if_opackets++; 1918 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1919 entry = sc_if->sk_cdata.sk_tx_map[idx]; 1920 1921 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1922 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1923 1924 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1925 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1926 1927 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1928 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1929 link); 1930 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 1931 } 1932 sc_if->sk_cdata.sk_tx_cnt--; 1933 SK_INC(idx, SK_TX_RING_CNT); 1934 } 1935 if (sc_if->sk_cdata.sk_tx_cnt == 0) 1936 ifp->if_timer = 0; 1937 else /* nudge chip to keep tx ring moving */ 1938 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1939 1940 sc_if->sk_cdata.sk_tx_cons = idx; 1941 1942 if (cur_tx != NULL) 1943 ifp->if_flags &= ~IFF_OACTIVE; 1944 } 1945 1946 void 1947 sk_tick(void *xsc_if) 1948 { 1949 struct sk_if_softc *sc_if = xsc_if; 1950 struct mii_data *mii = &sc_if->sk_mii; 1951 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1952 int i; 1953 1954 DPRINTFN(3, ("sk_tick\n")); 1955 1956 if (!(ifp->if_flags & IFF_UP)) 1957 return; 1958 1959 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1960 sk_intr_bcom(sc_if); 1961 return; 1962 } 1963 1964 /* 1965 * According to SysKonnect, the correct way to verify that 1966 * the link has come back up is to poll bit 0 of the GPIO 1967 * register three times. This pin has the signal from the 1968 * link sync pin connected to it; if we read the same link 1969 * state 3 times in a row, we know the link is up. 1970 */ 1971 for (i = 0; i < 3; i++) { 1972 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1973 break; 1974 } 1975 1976 if (i != 3) { 1977 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 1978 return; 1979 } 1980 1981 /* Turn the GP0 interrupt back on. */ 1982 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1983 SK_XM_READ_2(sc_if, XM_ISR); 1984 mii_tick(mii); 1985 mii_pollstat(mii); 1986 callout_stop(&sc_if->sk_tick_ch); 1987 } 1988 1989 void 1990 sk_intr_bcom(struct sk_if_softc *sc_if) 1991 { 1992 struct mii_data *mii = &sc_if->sk_mii; 1993 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1994 int status; 1995 1996 1997 DPRINTFN(3, ("sk_intr_bcom\n")); 1998 1999 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2000 2001 /* 2002 * Read the PHY interrupt register to make sure 2003 * we clear any pending interrupts. 2004 */ 2005 status = sk_xmac_miibus_readreg((struct device *)sc_if, 2006 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2007 2008 if (!(ifp->if_flags & IFF_RUNNING)) { 2009 sk_init_xmac(sc_if); 2010 return; 2011 } 2012 2013 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2014 int lstat; 2015 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 2016 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2017 2018 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2019 mii_mediachg(mii); 2020 /* Turn off the link LED. */ 2021 SK_IF_WRITE_1(sc_if, 0, 2022 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2023 sc_if->sk_link = 0; 2024 } else if (status & BRGPHY_ISR_LNK_CHG) { 2025 sk_xmac_miibus_writereg((struct device *)sc_if, 2026 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2027 mii_tick(mii); 2028 sc_if->sk_link = 1; 2029 /* Turn on the link LED. */ 2030 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2031 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2032 SK_LINKLED_BLINK_OFF); 2033 mii_pollstat(mii); 2034 } else { 2035 mii_tick(mii); 2036 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2037 } 2038 } 2039 2040 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2041 } 2042 2043 void 2044 sk_intr_xmac(struct sk_if_softc *sc_if) 2045 { 2046 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2047 2048 DPRINTFN(3, ("sk_intr_xmac\n")); 2049 2050 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2051 if (status & XM_ISR_GP0_SET) { 2052 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2053 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2054 } 2055 2056 if (status & XM_ISR_AUTONEG_DONE) { 2057 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2058 } 2059 } 2060 2061 if (status & XM_IMR_TX_UNDERRUN) 2062 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2063 2064 if (status & XM_IMR_RX_OVERRUN) 2065 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2066 } 2067 2068 void 2069 sk_intr_yukon(sc_if) 2070 struct sk_if_softc *sc_if; 2071 { 2072 int status; 2073 2074 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2075 2076 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2077 } 2078 2079 int 2080 sk_intr(void *xsc) 2081 { 2082 struct sk_softc *sc = xsc; 2083 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2084 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2085 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2086 u_int32_t status; 2087 int claimed = 0; 2088 2089 if (sc_if0 != NULL) 2090 ifp0 = &sc_if0->sk_ethercom.ec_if; 2091 if (sc_if1 != NULL) 2092 ifp1 = &sc_if1->sk_ethercom.ec_if; 2093 2094 for (;;) { 2095 status = CSR_READ_4(sc, SK_ISSR); 2096 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2097 2098 if (!(status & sc->sk_intrmask)) 2099 break; 2100 2101 claimed = 1; 2102 2103 /* Handle receive interrupts first. */ 2104 if (status & SK_ISR_RX1_EOF) { 2105 sk_rxeof(sc_if0); 2106 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2107 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2108 } 2109 if (status & SK_ISR_RX2_EOF) { 2110 sk_rxeof(sc_if1); 2111 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2112 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2113 } 2114 2115 /* Then transmit interrupts. */ 2116 if (status & SK_ISR_TX1_S_EOF) { 2117 sk_txeof(sc_if0); 2118 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2119 SK_TXBMU_CLR_IRQ_EOF); 2120 } 2121 if (status & SK_ISR_TX2_S_EOF) { 2122 sk_txeof(sc_if1); 2123 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2124 SK_TXBMU_CLR_IRQ_EOF); 2125 } 2126 2127 /* Then MAC interrupts. */ 2128 if (status & SK_ISR_MAC1 && (ifp0->if_flags & IFF_RUNNING)) { 2129 if (sc->sk_type == SK_GENESIS) 2130 sk_intr_xmac(sc_if0); 2131 else 2132 sk_intr_yukon(sc_if0); 2133 } 2134 2135 if (status & SK_ISR_MAC2 && (ifp1->if_flags & IFF_RUNNING)) { 2136 if (sc->sk_type == SK_GENESIS) 2137 sk_intr_xmac(sc_if1); 2138 else 2139 sk_intr_yukon(sc_if1); 2140 2141 } 2142 2143 if (status & SK_ISR_EXTERNAL_REG) { 2144 if (ifp0 != NULL && 2145 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2146 sk_intr_bcom(sc_if0); 2147 2148 if (ifp1 != NULL && 2149 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2150 sk_intr_bcom(sc_if1); 2151 } 2152 } 2153 2154 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2155 2156 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2157 sk_start(ifp0); 2158 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2159 sk_start(ifp1); 2160 2161 return (claimed); 2162 } 2163 2164 void 2165 sk_init_xmac(struct sk_if_softc *sc_if) 2166 { 2167 struct sk_softc *sc = sc_if->sk_softc; 2168 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2169 static const struct sk_bcom_hack bhack[] = { 2170 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2171 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2172 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2173 { 0, 0 } }; 2174 2175 DPRINTFN(1, ("sk_init_xmac\n")); 2176 2177 /* Unreset the XMAC. */ 2178 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2179 DELAY(1000); 2180 2181 /* Reset the XMAC's internal state. */ 2182 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2183 2184 /* Save the XMAC II revision */ 2185 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2186 2187 /* 2188 * Perform additional initialization for external PHYs, 2189 * namely for the 1000baseTX cards that use the XMAC's 2190 * GMII mode. 2191 */ 2192 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2193 int i = 0; 2194 u_int32_t val; 2195 2196 /* Take PHY out of reset. */ 2197 val = sk_win_read_4(sc, SK_GPIO); 2198 if (sc_if->sk_port == SK_PORT_A) 2199 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2200 else 2201 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2202 sk_win_write_4(sc, SK_GPIO, val); 2203 2204 /* Enable GMII mode on the XMAC. */ 2205 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2206 2207 sk_xmac_miibus_writereg((struct device *)sc_if, 2208 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2209 DELAY(10000); 2210 sk_xmac_miibus_writereg((struct device *)sc_if, 2211 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2212 2213 /* 2214 * Early versions of the BCM5400 apparently have 2215 * a bug that requires them to have their reserved 2216 * registers initialized to some magic values. I don't 2217 * know what the numbers do, I'm just the messenger. 2218 */ 2219 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2220 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2221 while(bhack[i].reg) { 2222 sk_xmac_miibus_writereg((struct device *)sc_if, 2223 SK_PHYADDR_BCOM, bhack[i].reg, 2224 bhack[i].val); 2225 i++; 2226 } 2227 } 2228 } 2229 2230 /* Set station address */ 2231 SK_XM_WRITE_2(sc_if, XM_PAR0, 2232 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2233 SK_XM_WRITE_2(sc_if, XM_PAR1, 2234 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2235 SK_XM_WRITE_2(sc_if, XM_PAR2, 2236 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2237 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2238 2239 if (ifp->if_flags & IFF_PROMISC) { 2240 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2241 } else { 2242 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2243 } 2244 2245 if (ifp->if_flags & IFF_BROADCAST) { 2246 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2247 } else { 2248 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2249 } 2250 2251 /* We don't need the FCS appended to the packet. */ 2252 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2253 2254 /* We want short frames padded to 60 bytes. */ 2255 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2256 2257 /* 2258 * Enable the reception of all error frames. This is is 2259 * a necessary evil due to the design of the XMAC. The 2260 * XMAC's receive FIFO is only 8K in size, however jumbo 2261 * frames can be up to 9000 bytes in length. When bad 2262 * frame filtering is enabled, the XMAC's RX FIFO operates 2263 * in 'store and forward' mode. For this to work, the 2264 * entire frame has to fit into the FIFO, but that means 2265 * that jumbo frames larger than 8192 bytes will be 2266 * truncated. Disabling all bad frame filtering causes 2267 * the RX FIFO to operate in streaming mode, in which 2268 * case the XMAC will start transfering frames out of the 2269 * RX FIFO as soon as the FIFO threshold is reached. 2270 */ 2271 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2272 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2273 XM_MODE_RX_INRANGELEN); 2274 2275 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2276 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2277 else 2278 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2279 2280 /* 2281 * Bump up the transmit threshold. This helps hold off transmit 2282 * underruns when we're blasting traffic from both ports at once. 2283 */ 2284 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2285 2286 /* Set multicast filter */ 2287 sk_setmulti(sc_if); 2288 2289 /* Clear and enable interrupts */ 2290 SK_XM_READ_2(sc_if, XM_ISR); 2291 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2292 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2293 else 2294 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2295 2296 /* Configure MAC arbiter */ 2297 switch(sc_if->sk_xmac_rev) { 2298 case XM_XMAC_REV_B2: 2299 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2300 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2301 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2302 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2303 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2304 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2305 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2306 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2307 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2308 break; 2309 case XM_XMAC_REV_C1: 2310 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2311 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2312 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2313 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2314 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2315 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2316 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2317 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2318 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2319 break; 2320 default: 2321 break; 2322 } 2323 sk_win_write_2(sc, SK_MACARB_CTL, 2324 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2325 2326 sc_if->sk_link = 1; 2327 } 2328 2329 void sk_init_yukon(sc_if) 2330 struct sk_if_softc *sc_if; 2331 { 2332 u_int32_t /*mac, */phy; 2333 u_int16_t reg; 2334 int i; 2335 2336 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2337 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2338 2339 /* GMAC and GPHY Reset */ 2340 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2341 2342 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2343 2344 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2345 DELAY(1000); 2346 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2347 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2348 DELAY(1000); 2349 2350 2351 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2352 2353 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2354 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2355 2356 switch(sc_if->sk_softc->sk_pmd) { 2357 case IFM_1000_SX: 2358 case IFM_1000_LX: 2359 phy |= SK_GPHY_FIBER; 2360 break; 2361 2362 case IFM_1000_CX: 2363 case IFM_1000_T: 2364 phy |= SK_GPHY_COPPER; 2365 break; 2366 } 2367 2368 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2369 2370 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2371 DELAY(1000); 2372 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2373 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2374 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2375 2376 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2377 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2378 2379 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2380 2381 /* unused read of the interrupt source register */ 2382 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2383 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2384 2385 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2386 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2387 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2388 2389 /* MIB Counter Clear Mode set */ 2390 reg |= YU_PAR_MIB_CLR; 2391 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2392 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2393 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2394 2395 /* MIB Counter Clear Mode clear */ 2396 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2397 reg &= ~YU_PAR_MIB_CLR; 2398 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2399 2400 /* receive control reg */ 2401 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2402 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2403 YU_RCR_CRCR); 2404 2405 /* transmit parameter register */ 2406 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2407 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2408 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2409 2410 /* serial mode register */ 2411 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2412 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2413 YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e)); 2414 2415 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2416 /* Setup Yukon's address */ 2417 for (i = 0; i < 3; i++) { 2418 /* Write Source Address 1 (unicast filter) */ 2419 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2420 sc_if->sk_enaddr[i * 2] | 2421 sc_if->sk_enaddr[i * 2 + 1] << 8); 2422 } 2423 2424 for (i = 0; i < 3; i++) { 2425 reg = sk_win_read_2(sc_if->sk_softc, 2426 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2427 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2428 } 2429 2430 /* Set multicast filter */ 2431 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2432 sk_setmulti(sc_if); 2433 2434 /* enable interrupt mask for counter overflows */ 2435 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2436 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2437 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2438 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2439 2440 /* Configure RX MAC FIFO */ 2441 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2442 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2443 2444 /* Configure TX MAC FIFO */ 2445 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2446 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2447 2448 DPRINTFN(6, ("sk_init_yukon: end\n")); 2449 } 2450 2451 /* 2452 * Note that to properly initialize any part of the GEnesis chip, 2453 * you first have to take it out of reset mode. 2454 */ 2455 int 2456 sk_init(struct ifnet *ifp) 2457 { 2458 struct sk_if_softc *sc_if = ifp->if_softc; 2459 struct sk_softc *sc = sc_if->sk_softc; 2460 struct mii_data *mii = &sc_if->sk_mii; 2461 int s; 2462 2463 DPRINTFN(1, ("sk_init\n")); 2464 2465 s = splnet(); 2466 2467 /* Cancel pending I/O and free all RX/TX buffers. */ 2468 sk_stop(ifp,0); 2469 2470 if (sc->sk_type == SK_GENESIS) { 2471 /* Configure LINK_SYNC LED */ 2472 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2473 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2474 SK_LINKLED_LINKSYNC_ON); 2475 2476 /* Configure RX LED */ 2477 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2478 SK_RXLEDCTL_COUNTER_START); 2479 2480 /* Configure TX LED */ 2481 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2482 SK_TXLEDCTL_COUNTER_START); 2483 } 2484 2485 /* Configure I2C registers */ 2486 2487 /* Configure XMAC(s) */ 2488 switch (sc->sk_type) { 2489 case SK_GENESIS: 2490 sk_init_xmac(sc_if); 2491 break; 2492 case SK_YUKON: 2493 case SK_YUKON_LITE: 2494 case SK_YUKON_LP: 2495 sk_init_yukon(sc_if); 2496 break; 2497 } 2498 mii_mediachg(mii); 2499 2500 if (sc->sk_type == SK_GENESIS) { 2501 /* Configure MAC FIFOs */ 2502 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2503 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2504 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2505 2506 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2507 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2508 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2509 } 2510 2511 /* Configure transmit arbiter(s) */ 2512 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2513 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2514 2515 /* Configure RAMbuffers */ 2516 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2517 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2518 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2519 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2520 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2521 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2522 2523 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2524 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2525 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2526 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2527 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2528 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2529 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2530 2531 /* Configure BMUs */ 2532 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2533 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2534 SK_RX_RING_ADDR(sc_if, 0)); 2535 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2536 2537 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2538 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2539 SK_TX_RING_ADDR(sc_if, 0)); 2540 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2541 2542 /* Init descriptors */ 2543 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2544 printf("%s: initialization failed: no " 2545 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2546 sk_stop(ifp,0); 2547 splx(s); 2548 return(ENOBUFS); 2549 } 2550 2551 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2552 printf("%s: initialization failed: no " 2553 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2554 sk_stop(ifp,0); 2555 splx(s); 2556 return(ENOBUFS); 2557 } 2558 2559 /* Configure interrupt handling */ 2560 CSR_READ_4(sc, SK_ISSR); 2561 if (sc_if->sk_port == SK_PORT_A) 2562 sc->sk_intrmask |= SK_INTRS1; 2563 else 2564 sc->sk_intrmask |= SK_INTRS2; 2565 2566 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2567 2568 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2569 2570 /* Start BMUs. */ 2571 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2572 2573 if (sc->sk_type == SK_GENESIS) { 2574 /* Enable XMACs TX and RX state machines */ 2575 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2576 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2577 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2578 } 2579 2580 if (SK_YUKON_FAMILY(sc->sk_type)) { 2581 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2582 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2583 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2584 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2585 } 2586 2587 2588 ifp->if_flags |= IFF_RUNNING; 2589 ifp->if_flags &= ~IFF_OACTIVE; 2590 2591 splx(s); 2592 return(0); 2593 } 2594 2595 void 2596 sk_stop(struct ifnet *ifp, int disable) 2597 { 2598 struct sk_if_softc *sc_if = ifp->if_softc; 2599 struct sk_softc *sc = sc_if->sk_softc; 2600 int i; 2601 2602 DPRINTFN(1, ("sk_stop\n")); 2603 2604 callout_stop(&sc_if->sk_tick_ch); 2605 2606 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2607 u_int32_t val; 2608 2609 /* Put PHY back into reset. */ 2610 val = sk_win_read_4(sc, SK_GPIO); 2611 if (sc_if->sk_port == SK_PORT_A) { 2612 val |= SK_GPIO_DIR0; 2613 val &= ~SK_GPIO_DAT0; 2614 } else { 2615 val |= SK_GPIO_DIR2; 2616 val &= ~SK_GPIO_DAT2; 2617 } 2618 sk_win_write_4(sc, SK_GPIO, val); 2619 } 2620 2621 /* Turn off various components of this interface. */ 2622 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2623 switch (sc->sk_type) { 2624 case SK_GENESIS: 2625 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2626 SK_TXMACCTL_XMAC_RESET); 2627 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2628 break; 2629 case SK_YUKON: 2630 case SK_YUKON_LITE: 2631 case SK_YUKON_LP: 2632 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2633 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2634 break; 2635 } 2636 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2637 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2638 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2639 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2640 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2641 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2642 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2643 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2644 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2645 2646 /* Disable interrupts */ 2647 if (sc_if->sk_port == SK_PORT_A) 2648 sc->sk_intrmask &= ~SK_INTRS1; 2649 else 2650 sc->sk_intrmask &= ~SK_INTRS2; 2651 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2652 2653 SK_XM_READ_2(sc_if, XM_ISR); 2654 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2655 2656 /* Free RX and TX mbufs still in the queues. */ 2657 for (i = 0; i < SK_RX_RING_CNT; i++) { 2658 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2659 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2660 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2661 } 2662 } 2663 2664 for (i = 0; i < SK_TX_RING_CNT; i++) { 2665 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2666 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2667 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2668 } 2669 } 2670 2671 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2672 } 2673 2674 CFATTACH_DECL(skc,sizeof(struct sk_softc), skc_probe, skc_attach, NULL, NULL); 2675 2676 /* 2677 struct cfdriver skc_cd = { 2678 0, "skc", DV_DULL 2679 }; 2680 */ 2681 2682 CFATTACH_DECL(sk,sizeof(struct sk_if_softc), sk_probe, sk_attach, NULL, NULL); 2683 2684 /* 2685 struct cfdriver sk_cd = { 2686 0, "sk", DV_IFNET 2687 }; 2688 */ 2689 2690 #ifdef SK_DEBUG 2691 void 2692 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2693 { 2694 #define DESC_PRINT(X) \ 2695 if (desc->X) \ 2696 printf("txdesc[%d]." #X "=%#x\n", \ 2697 idx, desc->X); 2698 2699 DESC_PRINT(sk_ctl); 2700 DESC_PRINT(sk_next); 2701 DESC_PRINT(sk_data_lo); 2702 DESC_PRINT(sk_data_hi); 2703 DESC_PRINT(sk_xmac_txstat); 2704 DESC_PRINT(sk_rsvd0); 2705 DESC_PRINT(sk_csum_startval); 2706 DESC_PRINT(sk_csum_startpos); 2707 DESC_PRINT(sk_csum_writepos); 2708 DESC_PRINT(sk_rsvd1); 2709 #undef PRINT 2710 } 2711 2712 void 2713 sk_dump_bytes(const char *data, int len) 2714 { 2715 int c, i, j; 2716 2717 for (i = 0; i < len; i += 16) { 2718 printf("%08x ", i); 2719 c = len - i; 2720 if (c > 16) c = 16; 2721 2722 for (j = 0; j < c; j++) { 2723 printf("%02x ", data[i + j] & 0xff); 2724 if ((j & 0xf) == 7 && j > 0) 2725 printf(" "); 2726 } 2727 2728 for (; j < 16; j++) 2729 printf(" "); 2730 printf(" "); 2731 2732 for (j = 0; j < c; j++) { 2733 int ch = data[i + j] & 0xff; 2734 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2735 } 2736 2737 printf("\n"); 2738 2739 if (c < 16) 2740 break; 2741 } 2742 } 2743 2744 void 2745 sk_dump_mbuf(struct mbuf *m) 2746 { 2747 int count = m->m_pkthdr.len; 2748 2749 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2750 2751 while (count > 0 && m) { 2752 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2753 m, m->m_data, m->m_len); 2754 sk_dump_bytes(mtod(m, char *), m->m_len); 2755 2756 count -= m->m_len; 2757 m = m->m_next; 2758 } 2759 } 2760 #endif 2761
Indexes created Tue Sep 23 07:09:52 GMT 2025