if_sk.c revision 1.14.2.6
1 /* $NetBSD: if_sk.c,v 1.14.2.6 2006/06/04 08:53:50 tron Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* $OpenBSD: if_sk.c,v 1.33 2003/08/12 05:23:06 nate Exp $ */ 37 38 /* 39 * Copyright (c) 1997, 1998, 1999, 2000 40 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Bill Paul. 53 * 4. Neither the name of the author nor the names of any co-contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 67 * THE POSSIBILITY OF SUCH DAMAGE. 68 * 69 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 70 */ 71 72 /* 73 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 74 * 75 * Permission to use, copy, modify, and distribute this software for any 76 * purpose with or without fee is hereby granted, provided that the above 77 * copyright notice and this permission notice appear in all copies. 78 * 79 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 80 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 81 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 82 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 83 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 84 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 85 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 86 */ 87 88 /* 89 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 90 * the SK-984x series adapters, both single port and dual port. 91 * References: 92 * The XaQti XMAC II datasheet, 93 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * The SysKonnect GEnesis manual, http://www.syskonnect.com 95 * 96 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 97 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 98 * convenience to others until Vitesse corrects this problem: 99 * 100 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 101 * 102 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 103 * Department of Electrical Engineering 104 * Columbia University, New York City 105 */ 106 107 /* 108 * The SysKonnect gigabit ethernet adapters consist of two main 109 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 110 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 111 * components and a PHY while the GEnesis controller provides a PCI 112 * interface with DMA support. Each card may have between 512K and 113 * 2MB of SRAM on board depending on the configuration. 114 * 115 * The SysKonnect GEnesis controller can have either one or two XMAC 116 * chips connected to it, allowing single or dual port NIC configurations. 117 * SysKonnect has the distinction of being the only vendor on the market 118 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 119 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 120 * XMAC registers. This driver takes advantage of these features to allow 121 * both XMACs to operate as independent interfaces. 122 */ 123 124 #include "bpfilter.h" 125 #include "rnd.h" 126 127 #include <sys/param.h> 128 #include <sys/systm.h> 129 #include <sys/sockio.h> 130 #include <sys/mbuf.h> 131 #include <sys/malloc.h> 132 #include <sys/kernel.h> 133 #include <sys/socket.h> 134 #include <sys/device.h> 135 #include <sys/queue.h> 136 #include <sys/callout.h> 137 #include <sys/sysctl.h> 138 139 #include <net/if.h> 140 #include <net/if_dl.h> 141 #include <net/if_types.h> 142 143 #ifdef INET 144 #include <netinet/in.h> 145 #include <netinet/in_systm.h> 146 #include <netinet/in_var.h> 147 #include <netinet/ip.h> 148 #include <netinet/if_ether.h> 149 #endif 150 151 #include <net/if_media.h> 152 153 #if NBPFILTER > 0 154 #include <net/bpf.h> 155 #endif 156 #if NRND > 0 157 #include <sys/rnd.h> 158 #endif 159 160 #include <dev/mii/mii.h> 161 #include <dev/mii/miivar.h> 162 #include <dev/mii/brgphyreg.h> 163 164 #include <dev/pci/pcireg.h> 165 #include <dev/pci/pcivar.h> 166 #include <dev/pci/pcidevs.h> 167 168 #define SK_VERBOSE 169 /* #define SK_USEIOSPACE */ 170 171 #include <dev/pci/if_skreg.h> 172 #include <dev/pci/if_skvar.h> 173 174 int skc_probe(struct device *, struct cfdata *, void *); 175 void skc_attach(struct device *, struct device *self, void *aux); 176 int sk_probe(struct device *, struct cfdata *, void *); 177 void sk_attach(struct device *, struct device *self, void *aux); 178 int skcprint(void *, const char *); 179 int sk_intr(void *); 180 void sk_intr_bcom(struct sk_if_softc *); 181 void sk_intr_xmac(struct sk_if_softc *); 182 void sk_intr_yukon(struct sk_if_softc *); 183 void sk_rxeof(struct sk_if_softc *); 184 void sk_txeof(struct sk_if_softc *); 185 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 186 void sk_start(struct ifnet *); 187 int sk_ioctl(struct ifnet *, u_long, caddr_t); 188 int sk_init(struct ifnet *); 189 void sk_init_xmac(struct sk_if_softc *); 190 void sk_init_yukon(struct sk_if_softc *); 191 void sk_stop(struct ifnet *, int); 192 void sk_watchdog(struct ifnet *); 193 void sk_shutdown(void *); 194 int sk_ifmedia_upd(struct ifnet *); 195 void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 196 void sk_reset(struct sk_softc *); 197 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 198 int sk_init_rx_ring(struct sk_if_softc *); 199 int sk_init_tx_ring(struct sk_if_softc *); 200 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 201 void sk_vpd_read_res(struct sk_softc *, 202 struct vpd_res *, int); 203 void sk_vpd_read(struct sk_softc *); 204 205 void sk_update_int_mod(struct sk_softc *); 206 207 int sk_xmac_miibus_readreg(struct device *, int, int); 208 void sk_xmac_miibus_writereg(struct device *, int, int, int); 209 void sk_xmac_miibus_statchg(struct device *); 210 211 int sk_marv_miibus_readreg(struct device *, int, int); 212 void sk_marv_miibus_writereg(struct device *, int, int, int); 213 void sk_marv_miibus_statchg(struct device *); 214 215 u_int32_t sk_xmac_hash(caddr_t); 216 u_int32_t sk_yukon_hash(caddr_t); 217 void sk_setfilt(struct sk_if_softc *, caddr_t, int); 218 void sk_setmulti(struct sk_if_softc *); 219 void sk_tick(void *); 220 221 /* #define SK_DEBUG 2 */ 222 #ifdef SK_DEBUG 223 #define DPRINTF(x) if (skdebug) printf x 224 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 225 int skdebug = SK_DEBUG; 226 227 void sk_dump_txdesc(struct sk_tx_desc *, int); 228 void sk_dump_mbuf(struct mbuf *); 229 void sk_dump_bytes(const char *, int); 230 #else 231 #define DPRINTF(x) 232 #define DPRINTFN(n,x) 233 #endif 234 235 #define SK_SETBIT(sc, reg, x) \ 236 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 237 238 #define SK_CLRBIT(sc, reg, x) \ 239 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 240 241 #define SK_WIN_SETBIT_4(sc, reg, x) \ 242 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 243 244 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 245 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 246 247 #define SK_WIN_SETBIT_2(sc, reg, x) \ 248 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 249 250 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 251 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 252 253 static int sk_sysctl_handler(SYSCTLFN_PROTO); 254 static int sk_root_num; 255 256 /* supported device vendors */ 257 static const struct sk_product { 258 pci_vendor_id_t sk_vendor; 259 pci_product_id_t sk_product; 260 } sk_products[] = { 261 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 262 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 263 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T, }, 264 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2, }, 265 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 266 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 267 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 268 { PCI_VENDOR_GALILEO, PCI_PRODUCT_GALILEO_SKNET, }, 269 { PCI_VENDOR_GALILEO, PCI_PRODUCT_GALILEO_BELKIN, }, 270 { 0, 0, } 271 }; 272 273 #define SK_LINKSYS_EG1032_SUBID 0x00151737 274 275 static inline u_int32_t 276 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 277 { 278 #ifdef SK_USEIOSPACE 279 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 280 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 281 #else 282 return CSR_READ_4(sc, reg); 283 #endif 284 } 285 286 static inline u_int16_t 287 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 288 { 289 #ifdef SK_USEIOSPACE 290 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 291 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 292 #else 293 return CSR_READ_2(sc, reg); 294 #endif 295 } 296 297 static inline u_int8_t 298 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 299 { 300 #ifdef SK_USEIOSPACE 301 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 302 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 303 #else 304 return CSR_READ_1(sc, reg); 305 #endif 306 } 307 308 static inline void 309 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 310 { 311 #ifdef SK_USEIOSPACE 312 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 313 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 314 #else 315 CSR_WRITE_4(sc, reg, x); 316 #endif 317 } 318 319 static inline void 320 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 321 { 322 #ifdef SK_USEIOSPACE 323 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 324 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 325 #else 326 CSR_WRITE_2(sc, reg, x); 327 #endif 328 } 329 330 static inline void 331 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 332 { 333 #ifdef SK_USEIOSPACE 334 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 335 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 336 #else 337 CSR_WRITE_1(sc, reg, x); 338 #endif 339 } 340 341 /* 342 * The VPD EEPROM contains Vital Product Data, as suggested in 343 * the PCI 2.1 specification. The VPD data is separared into areas 344 * denoted by resource IDs. The SysKonnect VPD contains an ID string 345 * resource (the name of the adapter), a read-only area resource 346 * containing various key/data fields and a read/write area which 347 * can be used to store asset management information or log messages. 348 * We read the ID string and read-only into buffers attached to 349 * the controller softc structure for later use. At the moment, 350 * we only use the ID string during sk_attach(). 351 */ 352 u_int8_t 353 sk_vpd_readbyte(struct sk_softc *sc, int addr) 354 { 355 int i; 356 357 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 358 for (i = 0; i < SK_TIMEOUT; i++) { 359 DELAY(1); 360 if (sk_win_read_2(sc, 361 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 362 break; 363 } 364 365 if (i == SK_TIMEOUT) 366 return(0); 367 368 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 369 } 370 371 void 372 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 373 { 374 int i; 375 u_int8_t *ptr; 376 377 ptr = (u_int8_t *)res; 378 for (i = 0; i < sizeof(struct vpd_res); i++) 379 ptr[i] = sk_vpd_readbyte(sc, i + addr); 380 } 381 382 void 383 sk_vpd_read(struct sk_softc *sc) 384 { 385 int pos = 0, i; 386 struct vpd_res res; 387 388 if (sc->sk_vpd_prodname != NULL) 389 free(sc->sk_vpd_prodname, M_DEVBUF); 390 if (sc->sk_vpd_readonly != NULL) 391 free(sc->sk_vpd_readonly, M_DEVBUF); 392 sc->sk_vpd_prodname = NULL; 393 sc->sk_vpd_readonly = NULL; 394 395 sk_vpd_read_res(sc, &res, pos); 396 397 if (res.vr_id != VPD_RES_ID) { 398 printf("%s: bad VPD resource id: expected %x got %x\n", 399 sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 400 return; 401 } 402 403 pos += sizeof(res); 404 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 405 if (sc->sk_vpd_prodname == NULL) 406 panic("sk_vpd_read"); 407 for (i = 0; i < res.vr_len; i++) 408 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 409 sc->sk_vpd_prodname[i] = '\0'; 410 pos += i; 411 412 sk_vpd_read_res(sc, &res, pos); 413 414 if (res.vr_id != VPD_RES_READ) { 415 printf("%s: bad VPD resource id: expected %x got %x\n", 416 sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 417 return; 418 } 419 420 pos += sizeof(res); 421 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 422 if (sc->sk_vpd_readonly == NULL) 423 panic("sk_vpd_read"); 424 for (i = 0; i < res.vr_len ; i++) 425 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 426 } 427 428 int 429 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 430 { 431 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 432 int i; 433 434 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 435 436 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 437 return(0); 438 439 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 440 SK_XM_READ_2(sc_if, XM_PHY_DATA); 441 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 442 for (i = 0; i < SK_TIMEOUT; i++) { 443 DELAY(1); 444 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 445 XM_MMUCMD_PHYDATARDY) 446 break; 447 } 448 449 if (i == SK_TIMEOUT) { 450 printf("%s: phy failed to come ready\n", 451 sc_if->sk_dev.dv_xname); 452 return(0); 453 } 454 } 455 DELAY(1); 456 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 457 } 458 459 void 460 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 461 { 462 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 463 int i; 464 465 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 466 467 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 468 for (i = 0; i < SK_TIMEOUT; i++) { 469 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 470 break; 471 } 472 473 if (i == SK_TIMEOUT) { 474 printf("%s: phy failed to come ready\n", 475 sc_if->sk_dev.dv_xname); 476 return; 477 } 478 479 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 480 for (i = 0; i < SK_TIMEOUT; i++) { 481 DELAY(1); 482 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 483 break; 484 } 485 486 if (i == SK_TIMEOUT) 487 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 488 } 489 490 void 491 sk_xmac_miibus_statchg(struct device *dev) 492 { 493 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 494 struct mii_data *mii = &sc_if->sk_mii; 495 496 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 497 498 /* 499 * If this is a GMII PHY, manually set the XMAC's 500 * duplex mode accordingly. 501 */ 502 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 503 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 504 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 505 } else { 506 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 507 } 508 } 509 } 510 511 int 512 sk_marv_miibus_readreg(dev, phy, reg) 513 struct device *dev; 514 int phy, reg; 515 { 516 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 517 u_int16_t val; 518 int i; 519 520 if (phy != 0 || 521 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 522 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 523 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 524 phy, reg)); 525 return(0); 526 } 527 528 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 529 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 530 531 for (i = 0; i < SK_TIMEOUT; i++) { 532 DELAY(1); 533 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 534 if (val & YU_SMICR_READ_VALID) 535 break; 536 } 537 538 if (i == SK_TIMEOUT) { 539 printf("%s: phy failed to come ready\n", 540 sc_if->sk_dev.dv_xname); 541 return 0; 542 } 543 544 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 545 SK_TIMEOUT)); 546 547 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 548 549 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 550 phy, reg, val)); 551 552 return val; 553 } 554 555 void 556 sk_marv_miibus_writereg(dev, phy, reg, val) 557 struct device *dev; 558 int phy, reg, val; 559 { 560 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 561 int i; 562 563 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 564 phy, reg, val)); 565 566 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 567 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 568 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 569 570 for (i = 0; i < SK_TIMEOUT; i++) { 571 DELAY(1); 572 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 573 break; 574 } 575 } 576 577 void 578 sk_marv_miibus_statchg(dev) 579 struct device *dev; 580 { 581 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 582 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 583 } 584 585 #define SK_HASH_BITS 6 586 587 u_int32_t 588 sk_xmac_hash(caddr_t addr) 589 { 590 u_int32_t crc; 591 592 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 593 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 594 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 595 return (crc); 596 } 597 598 u_int32_t 599 sk_yukon_hash(caddr_t addr) 600 { 601 u_int32_t crc; 602 603 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 604 crc &= ((1 << SK_HASH_BITS) - 1); 605 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 606 return (crc); 607 } 608 609 void 610 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 611 { 612 int base = XM_RXFILT_ENTRY(slot); 613 614 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 615 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 616 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 617 } 618 619 void 620 sk_setmulti(struct sk_if_softc *sc_if) 621 { 622 struct sk_softc *sc = sc_if->sk_softc; 623 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 624 u_int32_t hashes[2] = { 0, 0 }; 625 int h = 0, i; 626 struct ethercom *ec = &sc_if->sk_ethercom; 627 struct ether_multi *enm; 628 struct ether_multistep step; 629 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 630 631 /* First, zot all the existing filters. */ 632 switch(sc->sk_type) { 633 case SK_GENESIS: 634 for (i = 1; i < XM_RXFILT_MAX; i++) 635 sk_setfilt(sc_if, (caddr_t)&dummy, i); 636 637 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 638 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 639 break; 640 case SK_YUKON: 641 case SK_YUKON_LITE: 642 case SK_YUKON_LP: 643 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 644 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 645 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 646 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 647 break; 648 } 649 650 /* Now program new ones. */ 651 allmulti: 652 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 653 hashes[0] = 0xFFFFFFFF; 654 hashes[1] = 0xFFFFFFFF; 655 } else { 656 i = 1; 657 /* First find the tail of the list. */ 658 ETHER_FIRST_MULTI(step, ec, enm); 659 while (enm != NULL) { 660 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 661 ETHER_ADDR_LEN)) { 662 ifp->if_flags |= IFF_ALLMULTI; 663 goto allmulti; 664 } 665 DPRINTFN(2,("multicast address %s\n", 666 ether_sprintf(enm->enm_addrlo))); 667 /* 668 * Program the first XM_RXFILT_MAX multicast groups 669 * into the perfect filter. For all others, 670 * use the hash table. 671 */ 672 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 673 sk_setfilt(sc_if, enm->enm_addrlo, i); 674 i++; 675 } 676 else { 677 switch (sc->sk_type) { 678 case SK_GENESIS: 679 h = sk_xmac_hash(enm->enm_addrlo); 680 break; 681 case SK_YUKON: 682 case SK_YUKON_LITE: 683 case SK_YUKON_LP: 684 h = sk_yukon_hash(enm->enm_addrlo); 685 break; 686 } 687 if (h < 32) 688 hashes[0] |= (1 << h); 689 else 690 hashes[1] |= (1 << (h - 32)); 691 } 692 693 ETHER_NEXT_MULTI(step, enm); 694 } 695 } 696 697 switch(sc->sk_type) { 698 case SK_GENESIS: 699 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 700 XM_MODE_RX_USE_PERFECT); 701 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 702 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 703 break; 704 case SK_YUKON: 705 case SK_YUKON_LITE: 706 case SK_YUKON_LP: 707 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 708 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 709 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 710 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 711 break; 712 } 713 } 714 715 int 716 sk_init_rx_ring(struct sk_if_softc *sc_if) 717 { 718 struct sk_chain_data *cd = &sc_if->sk_cdata; 719 struct sk_ring_data *rd = sc_if->sk_rdata; 720 int i; 721 722 bzero((char *)rd->sk_rx_ring, 723 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 724 725 for (i = 0; i < SK_RX_RING_CNT; i++) { 726 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 727 if (i == (SK_RX_RING_CNT - 1)) { 728 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 729 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if, 0); 730 } else { 731 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 732 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if,i+1); 733 } 734 } 735 736 for (i = 0; i < SK_RX_RING_CNT; i++) { 737 if (sk_newbuf(sc_if, i, NULL, NULL) == ENOBUFS) { 738 printf("%s: failed alloc of %dth mbuf\n", 739 sc_if->sk_dev.dv_xname, i); 740 return(ENOBUFS); 741 } 742 } 743 sc_if->sk_cdata.sk_rx_prod = 0; 744 sc_if->sk_cdata.sk_rx_cons = 0; 745 746 return(0); 747 } 748 749 int 750 sk_init_tx_ring(struct sk_if_softc *sc_if) 751 { 752 struct sk_chain_data *cd = &sc_if->sk_cdata; 753 struct sk_ring_data *rd = sc_if->sk_rdata; 754 int i; 755 756 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 757 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 758 759 for (i = 0; i < SK_TX_RING_CNT; i++) { 760 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 761 if (i == (SK_TX_RING_CNT - 1)) { 762 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 763 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if, 0); 764 } else { 765 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 766 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if,i+1); 767 } 768 } 769 770 sc_if->sk_cdata.sk_tx_prod = 0; 771 sc_if->sk_cdata.sk_tx_cons = 0; 772 sc_if->sk_cdata.sk_tx_cnt = 0; 773 774 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 775 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 776 777 return (0); 778 } 779 780 int 781 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 782 bus_dmamap_t dmamap) 783 { 784 struct sk_softc *sc = sc_if->sk_softc; 785 struct mbuf *m_new = NULL; 786 struct sk_chain *c; 787 struct sk_rx_desc *r; 788 789 if (dmamap == NULL) { 790 /* if (m) panic() */ 791 792 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, MCLBYTES, 793 0, BUS_DMA_NOWAIT, &dmamap)) { 794 printf("%s: can't create recv map\n", 795 sc_if->sk_dev.dv_xname); 796 return(ENOMEM); 797 } 798 } else if (m == NULL) 799 bus_dmamap_unload(sc->sc_dmatag, dmamap); 800 801 sc_if->sk_cdata.sk_rx_map[i] = dmamap; 802 803 if (m == NULL) { 804 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 805 if (m_new == NULL) { 806 printf("%s: no memory for rx list -- " 807 "packet dropped!\n", sc_if->sk_dev.dv_xname); 808 return(ENOBUFS); 809 } 810 811 /* Allocate the jumbo buffer */ 812 MCLGET(m_new, M_DONTWAIT); 813 if (!(m_new->m_flags & M_EXT)) { 814 m_freem(m_new); 815 return (ENOBUFS); 816 } 817 818 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 819 820 m_adj(m_new, ETHER_ALIGN); 821 822 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m_new, 823 BUS_DMA_NOWAIT)) 824 return(ENOBUFS); 825 } else { 826 /* 827 * We're re-using a previously allocated mbuf; 828 * be sure to re-init pointers and lengths to 829 * default values. 830 */ 831 m_new = m; 832 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 833 m_adj(m_new, ETHER_ALIGN); 834 m_new->m_data = m_new->m_ext.ext_buf; 835 } 836 837 c = &sc_if->sk_cdata.sk_rx_chain[i]; 838 r = c->sk_desc; 839 c->sk_mbuf = m_new; 840 r->sk_data_lo = dmamap->dm_segs[0].ds_addr; 841 r->sk_ctl = dmamap->dm_segs[0].ds_len | SK_RXSTAT; 842 843 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 844 845 return(0); 846 } 847 848 /* 849 * Set media options. 850 */ 851 int 852 sk_ifmedia_upd(struct ifnet *ifp) 853 { 854 struct sk_if_softc *sc_if = ifp->if_softc; 855 856 (void) sk_init(ifp); 857 mii_mediachg(&sc_if->sk_mii); 858 return(0); 859 } 860 861 /* 862 * Report current media status. 863 */ 864 void 865 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 866 { 867 struct sk_if_softc *sc_if = ifp->if_softc; 868 869 mii_pollstat(&sc_if->sk_mii); 870 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 871 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 872 } 873 874 int 875 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 876 { 877 struct sk_if_softc *sc_if = ifp->if_softc; 878 struct sk_softc *sc = sc_if->sk_softc; 879 struct ifreq *ifr = (struct ifreq *) data; 880 /* struct ifaddr *ifa = (struct ifaddr *) data; */ 881 struct mii_data *mii; 882 int s, error = 0; 883 884 /* DPRINTFN(2, ("sk_ioctl\n")); */ 885 886 s = splnet(); 887 888 switch(command) { 889 890 case SIOCSIFFLAGS: 891 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 892 if (ifp->if_flags & IFF_UP) { 893 if (ifp->if_flags & IFF_RUNNING && 894 ifp->if_flags & IFF_PROMISC && 895 !(sc_if->sk_if_flags & IFF_PROMISC)) { 896 switch(sc->sk_type) { 897 case SK_GENESIS: 898 SK_XM_SETBIT_4(sc_if, XM_MODE, 899 XM_MODE_RX_PROMISC); 900 break; 901 case SK_YUKON: 902 case SK_YUKON_LITE: 903 case SK_YUKON_LP: 904 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 905 YU_RCR_UFLEN | YU_RCR_MUFLEN); 906 break; 907 } 908 sk_setmulti(sc_if); 909 } else if (ifp->if_flags & IFF_RUNNING && 910 !(ifp->if_flags & IFF_PROMISC) && 911 sc_if->sk_if_flags & IFF_PROMISC) { 912 switch(sc->sk_type) { 913 case SK_GENESIS: 914 SK_XM_CLRBIT_4(sc_if, XM_MODE, 915 XM_MODE_RX_PROMISC); 916 break; 917 case SK_YUKON: 918 case SK_YUKON_LITE: 919 case SK_YUKON_LP: 920 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 921 YU_RCR_UFLEN | YU_RCR_MUFLEN); 922 break; 923 } 924 925 sk_setmulti(sc_if); 926 } else 927 (void) sk_init(ifp); 928 } else { 929 if (ifp->if_flags & IFF_RUNNING) 930 sk_stop(ifp,0); 931 } 932 sc_if->sk_if_flags = ifp->if_flags; 933 error = 0; 934 break; 935 936 case SIOCGIFMEDIA: 937 case SIOCSIFMEDIA: 938 DPRINTFN(2, ("sk_ioctl MEDIA\n")); 939 mii = &sc_if->sk_mii; 940 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 941 break; 942 default: 943 DPRINTFN(2, ("sk_ioctl ETHER\n")); 944 error = ether_ioctl(ifp, command, data); 945 946 if ( error == ENETRESET) { 947 if (ifp->if_flags & IFF_RUNNING) { 948 sk_setmulti(sc_if); 949 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 950 } 951 error = 0; 952 } else if ( error ) { 953 splx(s); 954 return error; 955 } 956 break; 957 } 958 959 splx(s); 960 return(error); 961 } 962 963 void 964 sk_update_int_mod(struct sk_softc *sc) 965 { 966 u_int32_t sk_imtimer_ticks; 967 968 /* 969 * Configure interrupt moderation. The moderation timer 970 * defers interrupts specified in the interrupt moderation 971 * timer mask based on the timeout specified in the interrupt 972 * moderation timer init register. Each bit in the timer 973 * register represents one tick, so to specify a timeout in 974 * microseconds, we have to multiply by the correct number of 975 * ticks-per-microsecond. 976 */ 977 switch (sc->sk_type) { 978 case SK_GENESIS: 979 sk_imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 980 break; 981 case SK_YUKON_EC: 982 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 983 break; 984 default: 985 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 986 } 987 aprint_verbose("%s: interrupt moderation is %d us\n", 988 sc->sk_dev.dv_xname, sc->sk_int_mod); 989 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 990 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 991 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 992 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 993 sc->sk_int_mod_pending = 0; 994 } 995 996 /* 997 * Lookup: Check the PCI vendor and device, and return a pointer to 998 * The structure if the IDs match against our list. 999 */ 1000 1001 static const struct sk_product * 1002 sk_lookup(const struct pci_attach_args *pa) 1003 { 1004 const struct sk_product *psk; 1005 1006 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1007 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1008 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1009 return (psk); 1010 } 1011 return (NULL); 1012 } 1013 1014 /* 1015 * Probe for a SysKonnect GEnesis chip. 1016 */ 1017 1018 int 1019 skc_probe(struct device *parent, struct cfdata *match, void *aux) 1020 { 1021 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1022 const struct sk_product *psk; 1023 pcireg_t subid; 1024 1025 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1026 1027 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1028 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1029 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1030 subid == SK_LINKSYS_EG1032_SUBID) 1031 return(1); 1032 1033 if ((psk = sk_lookup(pa))) { 1034 return(1); 1035 } 1036 return(0); 1037 } 1038 1039 /* 1040 * Force the GEnesis into reset, then bring it out of reset. 1041 */ 1042 void sk_reset(struct sk_softc *sc) 1043 { 1044 DPRINTFN(2, ("sk_reset\n")); 1045 1046 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1047 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1048 if (SK_YUKON_FAMILY(sc->sk_type)) 1049 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1050 1051 DELAY(1000); 1052 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1053 DELAY(2); 1054 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1055 if (SK_YUKON_FAMILY(sc->sk_type)) 1056 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1057 1058 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1059 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1060 CSR_READ_2(sc, SK_LINK_CTRL))); 1061 1062 if (sc->sk_type == SK_GENESIS) { 1063 /* Configure packet arbiter */ 1064 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1065 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1066 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1067 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1068 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1069 } 1070 1071 /* Enable RAM interface */ 1072 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1073 1074 sk_update_int_mod(sc); 1075 } 1076 1077 int 1078 sk_probe(struct device *parent, struct cfdata *match, void *aux) 1079 { 1080 struct skc_attach_args *sa = aux; 1081 1082 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1083 return(0); 1084 1085 return (1); 1086 } 1087 1088 /* 1089 * Each XMAC chip is attached as a separate logical IP interface. 1090 * Single port cards will have only one logical interface of course. 1091 */ 1092 void 1093 sk_attach(struct device *parent, struct device *self, void *aux) 1094 { 1095 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1096 struct sk_softc *sc = (struct sk_softc *)parent; 1097 struct skc_attach_args *sa = aux; 1098 struct sk_txmap_entry *entry; 1099 struct ifnet *ifp; 1100 bus_dma_segment_t seg; 1101 bus_dmamap_t dmamap; 1102 caddr_t kva; 1103 int i, rseg; 1104 1105 sc_if->sk_port = sa->skc_port; 1106 sc_if->sk_softc = sc; 1107 sc->sk_if[sa->skc_port] = sc_if; 1108 1109 if (sa->skc_port == SK_PORT_A) 1110 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1111 if (sa->skc_port == SK_PORT_B) 1112 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1113 1114 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1115 1116 /* 1117 * Get station address for this interface. Note that 1118 * dual port cards actually come with three station 1119 * addresses: one for each port, plus an extra. The 1120 * extra one is used by the SysKonnect driver software 1121 * as a 'virtual' station address for when both ports 1122 * are operating in failover mode. Currently we don't 1123 * use this extra address. 1124 */ 1125 for (i = 0; i < ETHER_ADDR_LEN; i++) 1126 sc_if->sk_enaddr[i] = 1127 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1128 1129 1130 aprint_normal(": Ethernet address %s\n", 1131 ether_sprintf(sc_if->sk_enaddr)); 1132 1133 /* 1134 * Set up RAM buffer addresses. The NIC will have a certain 1135 * amount of SRAM on it, somewhere between 512K and 2MB. We 1136 * need to divide this up a) between the transmitter and 1137 * receiver and b) between the two XMACs, if this is a 1138 * dual port NIC. Our algotithm is to divide up the memory 1139 * evenly so that everyone gets a fair share. 1140 */ 1141 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1142 u_int32_t chunk, val; 1143 1144 chunk = sc->sk_ramsize / 2; 1145 val = sc->sk_rboff / sizeof(u_int64_t); 1146 sc_if->sk_rx_ramstart = val; 1147 val += (chunk / sizeof(u_int64_t)); 1148 sc_if->sk_rx_ramend = val - 1; 1149 sc_if->sk_tx_ramstart = val; 1150 val += (chunk / sizeof(u_int64_t)); 1151 sc_if->sk_tx_ramend = val - 1; 1152 } else { 1153 u_int32_t chunk, val; 1154 1155 chunk = sc->sk_ramsize / 4; 1156 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1157 sizeof(u_int64_t); 1158 sc_if->sk_rx_ramstart = val; 1159 val += (chunk / sizeof(u_int64_t)); 1160 sc_if->sk_rx_ramend = val - 1; 1161 sc_if->sk_tx_ramstart = val; 1162 val += (chunk / sizeof(u_int64_t)); 1163 sc_if->sk_tx_ramend = val - 1; 1164 } 1165 1166 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1167 " tx_ramstart=%#x tx_ramend=%#x\n", 1168 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1169 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1170 1171 /* Read and save PHY type and set PHY address */ 1172 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1173 switch (sc_if->sk_phytype) { 1174 case SK_PHYTYPE_XMAC: 1175 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1176 break; 1177 case SK_PHYTYPE_BCOM: 1178 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1179 break; 1180 case SK_PHYTYPE_MARV_COPPER: 1181 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1182 break; 1183 default: 1184 aprint_error("%s: unsupported PHY type: %d\n", 1185 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1186 return; 1187 } 1188 1189 /* Allocate the descriptor queues. */ 1190 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1191 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1192 aprint_error("%s: can't alloc rx buffers\n", 1193 sc->sk_dev.dv_xname); 1194 goto fail; 1195 } 1196 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1197 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1198 aprint_error("%s: can't map dma buffers (%lu bytes)\n", 1199 sc_if->sk_dev.dv_xname, 1200 (u_long) sizeof(struct sk_ring_data)); 1201 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1202 goto fail; 1203 } 1204 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1205 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1206 &sc_if->sk_ring_map)) { 1207 aprint_error("%s: can't create dma map\n", 1208 sc_if->sk_dev.dv_xname); 1209 bus_dmamem_unmap(sc->sc_dmatag, kva, 1210 sizeof(struct sk_ring_data)); 1211 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1212 goto fail; 1213 } 1214 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1215 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1216 aprint_error("%s: can't load dma map\n", 1217 sc_if->sk_dev.dv_xname); 1218 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1219 bus_dmamem_unmap(sc->sc_dmatag, kva, 1220 sizeof(struct sk_ring_data)); 1221 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1222 goto fail; 1223 } 1224 1225 for (i = 0; i < SK_RX_RING_CNT; i++) 1226 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1227 1228 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1229 for (i = 0; i < SK_TX_RING_CNT; i++) { 1230 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1231 1232 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, SK_NTXSEG, 1233 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap)) { 1234 aprint_error("%s: Can't create TX dmamap\n", 1235 sc_if->sk_dev.dv_xname); 1236 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1237 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1238 bus_dmamem_unmap(sc->sc_dmatag, kva, 1239 sizeof(struct sk_ring_data)); 1240 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1241 goto fail; 1242 } 1243 1244 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1245 if (!entry) { 1246 aprint_error("%s: Can't alloc txmap entry\n", 1247 sc_if->sk_dev.dv_xname); 1248 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1249 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1250 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1251 bus_dmamem_unmap(sc->sc_dmatag, kva, 1252 sizeof(struct sk_ring_data)); 1253 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1254 goto fail; 1255 } 1256 entry->dmamap = dmamap; 1257 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1258 } 1259 1260 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1261 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1262 1263 /* XXX TLS It's not clear what's wrong with the Jumbo MTU 1264 XXX TLS support in this driver, so we don't enable it. */ 1265 1266 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1267 1268 ifp = &sc_if->sk_ethercom.ec_if; 1269 ifp->if_softc = sc_if; 1270 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1271 ifp->if_ioctl = sk_ioctl; 1272 ifp->if_start = sk_start; 1273 ifp->if_stop = sk_stop; 1274 ifp->if_init = sk_init; 1275 ifp->if_watchdog = sk_watchdog; 1276 ifp->if_capabilities = 0; 1277 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1278 IFQ_SET_READY(&ifp->if_snd); 1279 strcpy(ifp->if_xname, sc_if->sk_dev.dv_xname); 1280 1281 /* 1282 * Do miibus setup. 1283 */ 1284 switch (sc->sk_type) { 1285 case SK_GENESIS: 1286 sk_init_xmac(sc_if); 1287 break; 1288 case SK_YUKON: 1289 case SK_YUKON_LITE: 1290 case SK_YUKON_LP: 1291 sk_init_yukon(sc_if); 1292 break; 1293 default: 1294 panic("%s: unknown device type %d", sc->sk_dev.dv_xname, 1295 sc->sk_type); 1296 } 1297 1298 DPRINTFN(2, ("sk_attach: 1\n")); 1299 1300 sc_if->sk_mii.mii_ifp = ifp; 1301 switch (sc->sk_type) { 1302 case SK_GENESIS: 1303 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1304 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1305 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1306 break; 1307 case SK_YUKON: 1308 case SK_YUKON_LITE: 1309 case SK_YUKON_LP: 1310 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1311 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1312 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1313 break; 1314 } 1315 1316 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1317 sk_ifmedia_upd, sk_ifmedia_sts); 1318 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1319 MII_OFFSET_ANY, 0); 1320 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1321 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1322 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1323 0, NULL); 1324 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1325 } 1326 else 1327 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1328 1329 callout_init(&sc_if->sk_tick_ch); 1330 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1331 1332 DPRINTFN(2, ("sk_attach: 1\n")); 1333 1334 /* 1335 * Call MI attach routines. 1336 */ 1337 if_attach(ifp); 1338 1339 ether_ifattach(ifp, sc_if->sk_enaddr); 1340 1341 #if NRND > 0 1342 rnd_attach_source(&sc->rnd_source, sc->sk_dev.dv_xname, 1343 RND_TYPE_NET, 0); 1344 #endif 1345 1346 DPRINTFN(2, ("sk_attach: end\n")); 1347 1348 return; 1349 1350 fail: 1351 sc->sk_if[sa->skc_port] = NULL; 1352 } 1353 1354 int 1355 skcprint(void *aux, const char *pnp) 1356 { 1357 struct skc_attach_args *sa = aux; 1358 1359 if (pnp) 1360 aprint_normal("sk port %c at %s", 1361 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1362 else 1363 aprint_normal(" port %c", 1364 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1365 return (UNCONF); 1366 } 1367 1368 /* 1369 * Attach the interface. Allocate softc structures, do ifmedia 1370 * setup and ethernet/BPF attach. 1371 */ 1372 void 1373 skc_attach(struct device *parent, struct device *self, void *aux) 1374 { 1375 struct sk_softc *sc = (struct sk_softc *)self; 1376 struct pci_attach_args *pa = aux; 1377 struct skc_attach_args skca; 1378 pci_chipset_tag_t pc = pa->pa_pc; 1379 pcireg_t memtype; 1380 pci_intr_handle_t ih; 1381 const char *intrstr = NULL; 1382 bus_addr_t iobase; 1383 bus_size_t iosize; 1384 int s, rc, sk_nodenum; 1385 u_int32_t command; 1386 char *revstr; 1387 struct sysctlnode *node; 1388 1389 DPRINTFN(2, ("begin skc_attach\n")); 1390 1391 s = splnet(); 1392 1393 /* 1394 * Handle power management nonsense. 1395 */ 1396 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1397 1398 if (command == 0x01) { 1399 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1400 if (command & SK_PSTATE_MASK) { 1401 u_int32_t iobase, membase, irq; 1402 1403 /* Save important PCI config data. */ 1404 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1405 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1406 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1407 1408 /* Reset the power state. */ 1409 aprint_normal("%s chip is in D%d power mode " 1410 "-- setting to D0\n", sc->sk_dev.dv_xname, 1411 command & SK_PSTATE_MASK); 1412 command &= 0xFFFFFFFC; 1413 pci_conf_write(pc, pa->pa_tag, 1414 SK_PCI_PWRMGMTCTRL, command); 1415 1416 /* Restore PCI config data. */ 1417 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1418 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1419 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1420 } 1421 } 1422 1423 /* 1424 * Map control/status registers. 1425 */ 1426 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1427 command |= PCI_COMMAND_IO_ENABLE | 1428 PCI_COMMAND_MEM_ENABLE | 1429 PCI_COMMAND_MASTER_ENABLE; 1430 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1431 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1432 1433 #ifdef SK_USEIOSPACE 1434 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1435 aprint_error(": failed to enable I/O ports!\n"); 1436 goto fail; 1437 } 1438 /* 1439 * Map control/status registers. 1440 */ 1441 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1442 &iobase, &iosize)) { 1443 aprint_error(": can't find i/o space\n"); 1444 goto fail; 1445 } 1446 #else 1447 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1448 aprint_error(": failed to enable memory mapping!\n"); 1449 goto fail; 1450 } 1451 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1452 switch (memtype) { 1453 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1454 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1455 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1456 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1457 &iobase, &iosize) == 0) 1458 break; 1459 default: 1460 aprint_error("%s: can't find mem space\n", 1461 sc->sk_dev.dv_xname); 1462 return; 1463 } 1464 1465 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1466 #endif 1467 sc->sc_dmatag = pa->pa_dmat; 1468 1469 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1470 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1471 1472 /* bail out here if chip is not recognized */ 1473 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1474 aprint_error("%s: unknown chip type\n",sc->sk_dev.dv_xname); 1475 goto fail; 1476 } 1477 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1478 1479 /* Allocate interrupt */ 1480 if (pci_intr_map(pa, &ih)) { 1481 aprint_error(": couldn't map interrupt\n"); 1482 goto fail; 1483 } 1484 1485 intrstr = pci_intr_string(pc, ih); 1486 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1487 if (sc->sk_intrhand == NULL) { 1488 aprint_error(": couldn't establish interrupt"); 1489 if (intrstr != NULL) 1490 aprint_normal(" at %s", intrstr); 1491 goto fail; 1492 } 1493 aprint_normal(": %s\n", intrstr); 1494 1495 /* Reset the adapter. */ 1496 sk_reset(sc); 1497 1498 /* Read and save vital product data from EEPROM. */ 1499 sk_vpd_read(sc); 1500 1501 if (sc->sk_type == SK_GENESIS) { 1502 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1503 /* Read and save RAM size and RAMbuffer offset */ 1504 switch(val) { 1505 case SK_RAMSIZE_512K_64: 1506 sc->sk_ramsize = 0x80000; 1507 sc->sk_rboff = SK_RBOFF_0; 1508 break; 1509 case SK_RAMSIZE_1024K_64: 1510 sc->sk_ramsize = 0x100000; 1511 sc->sk_rboff = SK_RBOFF_80000; 1512 break; 1513 case SK_RAMSIZE_1024K_128: 1514 sc->sk_ramsize = 0x100000; 1515 sc->sk_rboff = SK_RBOFF_0; 1516 break; 1517 case SK_RAMSIZE_2048K_128: 1518 sc->sk_ramsize = 0x200000; 1519 sc->sk_rboff = SK_RBOFF_0; 1520 break; 1521 default: 1522 aprint_error("%s: unknown ram size: %d\n", 1523 sc->sk_dev.dv_xname, val); 1524 goto fail; 1525 break; 1526 } 1527 1528 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1529 sc->sk_ramsize, sc->sk_ramsize / 1024, 1530 sc->sk_rboff)); 1531 } else { 1532 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1533 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1534 sc->sk_rboff = SK_RBOFF_0; 1535 1536 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1537 sc->sk_ramsize / 1024, sc->sk_ramsize, 1538 sc->sk_rboff)); 1539 } 1540 1541 /* Read and save physical media type */ 1542 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1543 case SK_PMD_1000BASESX: 1544 sc->sk_pmd = IFM_1000_SX; 1545 break; 1546 case SK_PMD_1000BASELX: 1547 sc->sk_pmd = IFM_1000_LX; 1548 break; 1549 case SK_PMD_1000BASECX: 1550 sc->sk_pmd = IFM_1000_CX; 1551 break; 1552 case SK_PMD_1000BASETX: 1553 case SK_PMD_1000BASETX_ALT: 1554 sc->sk_pmd = IFM_1000_T; 1555 break; 1556 default: 1557 aprint_error("%s: unknown media type: 0x%x\n", 1558 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1559 goto fail; 1560 } 1561 1562 /* determine whether to name it with vpd or just make it up */ 1563 /* Marvell Yukon VPD's can freqently be bogus */ 1564 1565 switch (pa->pa_id) { 1566 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1567 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1568 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1569 case PCI_PRODUCT_3COM_3C940: 1570 case PCI_PRODUCT_DLINK_DGE530T: 1571 case PCI_PRODUCT_DLINK_DGE560T: 1572 case PCI_PRODUCT_DLINK_DGE560T_2: 1573 case PCI_PRODUCT_LINKSYS_EG1032: 1574 case PCI_PRODUCT_LINKSYS_EG1064: 1575 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1576 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1577 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1578 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1579 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T): 1580 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE560T_2): 1581 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1582 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1583 sc->sk_name = sc->sk_vpd_prodname; 1584 break; 1585 case PCI_ID_CODE(PCI_VENDOR_GALILEO,PCI_PRODUCT_GALILEO_SKNET): 1586 /* whoops yukon vpd prodname bears no resemblance to reality */ 1587 switch (sc->sk_type) { 1588 case SK_GENESIS: 1589 sc->sk_name = sc->sk_vpd_prodname; 1590 break; 1591 case SK_YUKON: 1592 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1593 break; 1594 case SK_YUKON_LITE: 1595 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1596 break; 1597 case SK_YUKON_LP: 1598 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1599 break; 1600 default: 1601 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1602 } 1603 1604 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1605 1606 if ( sc->sk_type == SK_YUKON ) { 1607 uint32_t flashaddr; 1608 uint8_t testbyte; 1609 1610 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1611 1612 /* test Flash-Address Register */ 1613 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1614 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1615 1616 if (testbyte != 0) { 1617 /* this is yukon lite Rev. A0 */ 1618 sc->sk_type = SK_YUKON_LITE; 1619 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1620 /* restore Flash-Address Register */ 1621 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1622 } 1623 } 1624 break; 1625 case PCI_ID_CODE(PCI_VENDOR_GALILEO,PCI_PRODUCT_GALILEO_BELKIN): 1626 sc->sk_name = sc->sk_vpd_prodname; 1627 break; 1628 default: 1629 sc->sk_name = "Unkown Marvell"; 1630 } 1631 1632 1633 if ( sc->sk_type == SK_YUKON_LITE ) { 1634 switch (sc->sk_rev) { 1635 case SK_YUKON_LITE_REV_A0: 1636 revstr = "A0"; 1637 break; 1638 case SK_YUKON_LITE_REV_A1: 1639 revstr = "A1"; 1640 break; 1641 case SK_YUKON_LITE_REV_A3: 1642 revstr = "A3"; 1643 break; 1644 default: 1645 revstr = ""; 1646 } 1647 } else { 1648 revstr = ""; 1649 } 1650 1651 /* Announce the product name. */ 1652 aprint_normal("%s: %s rev. %s(0x%x)\n", sc->sk_dev.dv_xname, 1653 sc->sk_name, revstr, sc->sk_rev); 1654 1655 skca.skc_port = SK_PORT_A; 1656 (void)config_found(&sc->sk_dev, &skca, skcprint); 1657 1658 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1659 skca.skc_port = SK_PORT_B; 1660 (void)config_found(&sc->sk_dev, &skca, skcprint); 1661 } 1662 1663 /* Turn on the 'driver is loaded' LED. */ 1664 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1665 1666 /* skc sysctl setup */ 1667 1668 sc->sk_int_mod = SK_IM_DEFAULT; 1669 sc->sk_int_mod_pending = 0; 1670 1671 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1672 0, CTLTYPE_NODE, sc->sk_dev.dv_xname, 1673 SYSCTL_DESCR("skc per-controller controls"), 1674 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1675 CTL_EOL)) != 0) { 1676 aprint_normal("%s: couldn't create sysctl node\n", 1677 sc->sk_dev.dv_xname); 1678 goto fail; 1679 } 1680 1681 sk_nodenum = node->sysctl_num; 1682 1683 /* interrupt moderation time in usecs */ 1684 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1685 CTLFLAG_READWRITE, 1686 CTLTYPE_INT, "int_mod", 1687 SYSCTL_DESCR("sk interrupt moderation timer"), 1688 sk_sysctl_handler, 0, sc, 1689 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1690 CTL_EOL)) != 0) { 1691 aprint_normal("%s: couldn't create int_mod sysctl node\n", 1692 sc->sk_dev.dv_xname); 1693 goto fail; 1694 } 1695 1696 fail: 1697 splx(s); 1698 } 1699 1700 int 1701 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1702 { 1703 struct sk_softc *sc = sc_if->sk_softc; 1704 struct sk_tx_desc *f = NULL; 1705 u_int32_t frag, cur, cnt = 0; 1706 int i; 1707 struct sk_txmap_entry *entry; 1708 bus_dmamap_t txmap; 1709 1710 DPRINTFN(3, ("sk_encap\n")); 1711 1712 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1713 if (entry == NULL) { 1714 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1715 return ENOBUFS; 1716 } 1717 txmap = entry->dmamap; 1718 1719 cur = frag = *txidx; 1720 1721 #ifdef SK_DEBUG 1722 if (skdebug >= 3) 1723 sk_dump_mbuf(m_head); 1724 #endif 1725 1726 /* 1727 * Start packing the mbufs in this chain into 1728 * the fragment pointers. Stop when we run out 1729 * of fragments or hit the end of the mbuf chain. 1730 */ 1731 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1732 BUS_DMA_NOWAIT)) { 1733 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1734 return(ENOBUFS); 1735 } 1736 1737 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1738 1739 /* Sync the DMA map. */ 1740 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1741 BUS_DMASYNC_PREWRITE); 1742 1743 for (i = 0; i < txmap->dm_nsegs; i++) { 1744 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1745 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1746 return(ENOBUFS); 1747 } 1748 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1749 f->sk_data_lo = txmap->dm_segs[i].ds_addr; 1750 f->sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1751 if (cnt == 0) 1752 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1753 else 1754 f->sk_ctl |= SK_TXCTL_OWN; 1755 1756 cur = frag; 1757 SK_INC(frag, SK_TX_RING_CNT); 1758 cnt++; 1759 } 1760 1761 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1762 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1763 1764 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1765 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1766 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1767 1768 /* Sync descriptors before handing to chip */ 1769 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1770 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1771 1772 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1773 1774 /* Sync first descriptor to hand it off */ 1775 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1776 1777 sc_if->sk_cdata.sk_tx_cnt += cnt; 1778 1779 #ifdef SK_DEBUG 1780 if (skdebug >= 3) { 1781 struct sk_tx_desc *desc; 1782 u_int32_t idx; 1783 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1784 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1785 sk_dump_txdesc(desc, idx); 1786 } 1787 } 1788 #endif 1789 1790 *txidx = frag; 1791 1792 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1793 1794 return(0); 1795 } 1796 1797 void 1798 sk_start(struct ifnet *ifp) 1799 { 1800 struct sk_if_softc *sc_if = ifp->if_softc; 1801 struct sk_softc *sc = sc_if->sk_softc; 1802 struct mbuf *m_head = NULL; 1803 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1804 int pkts = 0; 1805 1806 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1807 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1808 1809 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1810 1811 IFQ_POLL(&ifp->if_snd, m_head); 1812 if (m_head == NULL) 1813 break; 1814 1815 /* 1816 * Pack the data into the transmit ring. If we 1817 * don't have room, set the OACTIVE flag and wait 1818 * for the NIC to drain the ring. 1819 */ 1820 if (sk_encap(sc_if, m_head, &idx)) { 1821 ifp->if_flags |= IFF_OACTIVE; 1822 break; 1823 } 1824 1825 /* now we are committed to transmit the packet */ 1826 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1827 pkts++; 1828 1829 /* 1830 * If there's a BPF listener, bounce a copy of this frame 1831 * to him. 1832 */ 1833 #if NBPFILTER > 0 1834 if (ifp->if_bpf) 1835 bpf_mtap(ifp->if_bpf, m_head); 1836 #endif 1837 } 1838 if (pkts == 0) 1839 return; 1840 1841 /* Transmit */ 1842 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1843 sc_if->sk_cdata.sk_tx_prod = idx; 1844 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1845 1846 /* Set a timeout in case the chip goes out to lunch. */ 1847 ifp->if_timer = 5; 1848 } 1849 } 1850 1851 1852 void 1853 sk_watchdog(struct ifnet *ifp) 1854 { 1855 struct sk_if_softc *sc_if = ifp->if_softc; 1856 1857 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1858 (void) sk_init(ifp); 1859 } 1860 1861 void 1862 sk_shutdown(void * v) 1863 { 1864 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 1865 struct sk_softc *sc = sc_if->sk_softc; 1866 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1867 1868 DPRINTFN(2, ("sk_shutdown\n")); 1869 sk_stop(ifp,1); 1870 1871 /* Turn off the 'driver is loaded' LED. */ 1872 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1873 1874 /* 1875 * Reset the GEnesis controller. Doing this should also 1876 * assert the resets on the attached XMAC(s). 1877 */ 1878 sk_reset(sc); 1879 } 1880 1881 void 1882 sk_rxeof(struct sk_if_softc *sc_if) 1883 { 1884 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1885 struct mbuf *m; 1886 struct sk_chain *cur_rx; 1887 struct sk_rx_desc *cur_desc; 1888 int i, cur, total_len = 0; 1889 u_int32_t rxstat; 1890 bus_dmamap_t dmamap; 1891 1892 i = sc_if->sk_cdata.sk_rx_prod; 1893 1894 DPRINTFN(3, ("sk_rxeof %d\n", i)); 1895 1896 for (;;) { 1897 cur = i; 1898 1899 /* Sync the descriptor */ 1900 SK_CDRXSYNC(sc_if, cur, 1901 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1902 1903 if (sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl & SK_RXCTL_OWN) { 1904 /* Invalidate the descriptor -- it's not ready yet */ 1905 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 1906 sc_if->sk_cdata.sk_rx_prod = i; 1907 break; 1908 } 1909 1910 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1911 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 1912 dmamap = sc_if->sk_cdata.sk_rx_map[cur]; 1913 1914 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1915 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1916 1917 rxstat = cur_desc->sk_xmac_rxstat; 1918 m = cur_rx->sk_mbuf; 1919 cur_rx->sk_mbuf = NULL; 1920 total_len = SK_RXBYTES(cur_desc->sk_ctl); 1921 1922 sc_if->sk_cdata.sk_rx_map[cur] = 0; 1923 1924 SK_INC(i, SK_RX_RING_CNT); 1925 1926 if (rxstat & XM_RXSTAT_ERRFRAME) { 1927 ifp->if_ierrors++; 1928 sk_newbuf(sc_if, cur, m, dmamap); 1929 continue; 1930 } 1931 1932 /* 1933 * Try to allocate a new jumbo buffer. If that 1934 * fails, copy the packet to mbufs and put the 1935 * jumbo buffer back in the ring so it can be 1936 * re-used. If allocating mbufs fails, then we 1937 * have to drop the packet. 1938 */ 1939 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1940 struct mbuf *m0; 1941 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1942 total_len + ETHER_ALIGN, 0, ifp, NULL); 1943 sk_newbuf(sc_if, cur, m, dmamap); 1944 if (m0 == NULL) { 1945 printf("%s: no receive buffers " 1946 "available -- packet dropped!\n", 1947 sc_if->sk_dev.dv_xname); 1948 ifp->if_ierrors++; 1949 continue; 1950 } 1951 m_adj(m0, ETHER_ALIGN); 1952 m = m0; 1953 } else { 1954 m->m_pkthdr.rcvif = ifp; 1955 m->m_pkthdr.len = m->m_len = total_len; 1956 } 1957 1958 ifp->if_ipackets++; 1959 1960 #if NBPFILTER > 0 1961 if (ifp->if_bpf) 1962 bpf_mtap(ifp->if_bpf, m); 1963 #endif 1964 /* pass it on. */ 1965 (*ifp->if_input)(ifp, m); 1966 } 1967 } 1968 1969 void 1970 sk_txeof(struct sk_if_softc *sc_if) 1971 { 1972 struct sk_softc *sc = sc_if->sk_softc; 1973 struct sk_tx_desc *cur_tx; 1974 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1975 u_int32_t idx; 1976 struct sk_txmap_entry *entry; 1977 1978 DPRINTFN(3, ("sk_txeof\n")); 1979 1980 /* 1981 * Go through our tx ring and free mbufs for those 1982 * frames that have been sent. 1983 */ 1984 idx = sc_if->sk_cdata.sk_tx_cons; 1985 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1986 SK_CDTXSYNC(sc_if, idx, 1, 1987 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1988 1989 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1990 #ifdef SK_DEBUG 1991 if (skdebug >= 3) 1992 sk_dump_txdesc(cur_tx, idx); 1993 #endif 1994 if (cur_tx->sk_ctl & SK_TXCTL_OWN) { 1995 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 1996 break; 1997 } 1998 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1999 ifp->if_opackets++; 2000 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 2001 entry = sc_if->sk_cdata.sk_tx_map[idx]; 2002 2003 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 2004 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 2005 2006 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2007 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2008 2009 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2010 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2011 link); 2012 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2013 } 2014 sc_if->sk_cdata.sk_tx_cnt--; 2015 SK_INC(idx, SK_TX_RING_CNT); 2016 } 2017 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2018 ifp->if_timer = 0; 2019 else /* nudge chip to keep tx ring moving */ 2020 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2021 2022 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2023 ifp->if_flags &= ~IFF_OACTIVE; 2024 2025 sc_if->sk_cdata.sk_tx_cons = idx; 2026 } 2027 2028 void 2029 sk_tick(void *xsc_if) 2030 { 2031 struct sk_if_softc *sc_if = xsc_if; 2032 struct mii_data *mii = &sc_if->sk_mii; 2033 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2034 int i; 2035 2036 DPRINTFN(3, ("sk_tick\n")); 2037 2038 if (!(ifp->if_flags & IFF_UP)) 2039 return; 2040 2041 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2042 sk_intr_bcom(sc_if); 2043 return; 2044 } 2045 2046 /* 2047 * According to SysKonnect, the correct way to verify that 2048 * the link has come back up is to poll bit 0 of the GPIO 2049 * register three times. This pin has the signal from the 2050 * link sync pin connected to it; if we read the same link 2051 * state 3 times in a row, we know the link is up. 2052 */ 2053 for (i = 0; i < 3; i++) { 2054 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2055 break; 2056 } 2057 2058 if (i != 3) { 2059 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2060 return; 2061 } 2062 2063 /* Turn the GP0 interrupt back on. */ 2064 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2065 SK_XM_READ_2(sc_if, XM_ISR); 2066 mii_tick(mii); 2067 mii_pollstat(mii); 2068 callout_stop(&sc_if->sk_tick_ch); 2069 } 2070 2071 void 2072 sk_intr_bcom(struct sk_if_softc *sc_if) 2073 { 2074 struct mii_data *mii = &sc_if->sk_mii; 2075 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2076 int status; 2077 2078 2079 DPRINTFN(3, ("sk_intr_bcom\n")); 2080 2081 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2082 2083 /* 2084 * Read the PHY interrupt register to make sure 2085 * we clear any pending interrupts. 2086 */ 2087 status = sk_xmac_miibus_readreg((struct device *)sc_if, 2088 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2089 2090 if (!(ifp->if_flags & IFF_RUNNING)) { 2091 sk_init_xmac(sc_if); 2092 return; 2093 } 2094 2095 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2096 int lstat; 2097 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 2098 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2099 2100 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2101 mii_mediachg(mii); 2102 /* Turn off the link LED. */ 2103 SK_IF_WRITE_1(sc_if, 0, 2104 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2105 sc_if->sk_link = 0; 2106 } else if (status & BRGPHY_ISR_LNK_CHG) { 2107 sk_xmac_miibus_writereg((struct device *)sc_if, 2108 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2109 mii_tick(mii); 2110 sc_if->sk_link = 1; 2111 /* Turn on the link LED. */ 2112 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2113 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2114 SK_LINKLED_BLINK_OFF); 2115 mii_pollstat(mii); 2116 } else { 2117 mii_tick(mii); 2118 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2119 } 2120 } 2121 2122 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2123 } 2124 2125 void 2126 sk_intr_xmac(struct sk_if_softc *sc_if) 2127 { 2128 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2129 2130 DPRINTFN(3, ("sk_intr_xmac\n")); 2131 2132 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2133 if (status & XM_ISR_GP0_SET) { 2134 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2135 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2136 } 2137 2138 if (status & XM_ISR_AUTONEG_DONE) { 2139 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2140 } 2141 } 2142 2143 if (status & XM_IMR_TX_UNDERRUN) 2144 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2145 2146 if (status & XM_IMR_RX_OVERRUN) 2147 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2148 } 2149 2150 void 2151 sk_intr_yukon(sc_if) 2152 struct sk_if_softc *sc_if; 2153 { 2154 int status; 2155 2156 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2157 2158 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2159 } 2160 2161 int 2162 sk_intr(void *xsc) 2163 { 2164 struct sk_softc *sc = xsc; 2165 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2166 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2167 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2168 u_int32_t status; 2169 int claimed = 0; 2170 2171 if (sc_if0 != NULL) 2172 ifp0 = &sc_if0->sk_ethercom.ec_if; 2173 if (sc_if1 != NULL) 2174 ifp1 = &sc_if1->sk_ethercom.ec_if; 2175 2176 for (;;) { 2177 status = CSR_READ_4(sc, SK_ISSR); 2178 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2179 2180 if (!(status & sc->sk_intrmask)) 2181 break; 2182 2183 claimed = 1; 2184 2185 /* Handle receive interrupts first. */ 2186 if (status & SK_ISR_RX1_EOF) { 2187 sk_rxeof(sc_if0); 2188 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2189 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2190 } 2191 if (status & SK_ISR_RX2_EOF) { 2192 sk_rxeof(sc_if1); 2193 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2194 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2195 } 2196 2197 /* Then transmit interrupts. */ 2198 if (status & SK_ISR_TX1_S_EOF) { 2199 sk_txeof(sc_if0); 2200 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2201 SK_TXBMU_CLR_IRQ_EOF); 2202 } 2203 if (status & SK_ISR_TX2_S_EOF) { 2204 sk_txeof(sc_if1); 2205 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2206 SK_TXBMU_CLR_IRQ_EOF); 2207 } 2208 2209 /* Then MAC interrupts. */ 2210 if (status & SK_ISR_MAC1 && (ifp0->if_flags & IFF_RUNNING)) { 2211 if (sc->sk_type == SK_GENESIS) 2212 sk_intr_xmac(sc_if0); 2213 else 2214 sk_intr_yukon(sc_if0); 2215 } 2216 2217 if (status & SK_ISR_MAC2 && (ifp1->if_flags & IFF_RUNNING)) { 2218 if (sc->sk_type == SK_GENESIS) 2219 sk_intr_xmac(sc_if1); 2220 else 2221 sk_intr_yukon(sc_if1); 2222 2223 } 2224 2225 if (status & SK_ISR_EXTERNAL_REG) { 2226 if (ifp0 != NULL && 2227 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2228 sk_intr_bcom(sc_if0); 2229 2230 if (ifp1 != NULL && 2231 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2232 sk_intr_bcom(sc_if1); 2233 } 2234 } 2235 2236 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2237 2238 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2239 sk_start(ifp0); 2240 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2241 sk_start(ifp1); 2242 2243 #if NRND > 0 2244 if (RND_ENABLED(&sc->rnd_source)) 2245 rnd_add_uint32(&sc->rnd_source, status); 2246 #endif 2247 2248 if (sc->sk_int_mod_pending) 2249 sk_update_int_mod(sc); 2250 2251 return (claimed); 2252 } 2253 2254 void 2255 sk_init_xmac(struct sk_if_softc *sc_if) 2256 { 2257 struct sk_softc *sc = sc_if->sk_softc; 2258 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2259 static const struct sk_bcom_hack bhack[] = { 2260 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2261 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2262 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2263 { 0, 0 } }; 2264 2265 DPRINTFN(1, ("sk_init_xmac\n")); 2266 2267 /* Unreset the XMAC. */ 2268 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2269 DELAY(1000); 2270 2271 /* Reset the XMAC's internal state. */ 2272 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2273 2274 /* Save the XMAC II revision */ 2275 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2276 2277 /* 2278 * Perform additional initialization for external PHYs, 2279 * namely for the 1000baseTX cards that use the XMAC's 2280 * GMII mode. 2281 */ 2282 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2283 int i = 0; 2284 u_int32_t val; 2285 2286 /* Take PHY out of reset. */ 2287 val = sk_win_read_4(sc, SK_GPIO); 2288 if (sc_if->sk_port == SK_PORT_A) 2289 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2290 else 2291 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2292 sk_win_write_4(sc, SK_GPIO, val); 2293 2294 /* Enable GMII mode on the XMAC. */ 2295 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2296 2297 sk_xmac_miibus_writereg((struct device *)sc_if, 2298 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2299 DELAY(10000); 2300 sk_xmac_miibus_writereg((struct device *)sc_if, 2301 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2302 2303 /* 2304 * Early versions of the BCM5400 apparently have 2305 * a bug that requires them to have their reserved 2306 * registers initialized to some magic values. I don't 2307 * know what the numbers do, I'm just the messenger. 2308 */ 2309 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2310 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2311 while(bhack[i].reg) { 2312 sk_xmac_miibus_writereg((struct device *)sc_if, 2313 SK_PHYADDR_BCOM, bhack[i].reg, 2314 bhack[i].val); 2315 i++; 2316 } 2317 } 2318 } 2319 2320 /* Set station address */ 2321 SK_XM_WRITE_2(sc_if, XM_PAR0, 2322 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2323 SK_XM_WRITE_2(sc_if, XM_PAR1, 2324 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2325 SK_XM_WRITE_2(sc_if, XM_PAR2, 2326 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2327 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2328 2329 if (ifp->if_flags & IFF_PROMISC) { 2330 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2331 } else { 2332 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2333 } 2334 2335 if (ifp->if_flags & IFF_BROADCAST) { 2336 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2337 } else { 2338 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2339 } 2340 2341 /* We don't need the FCS appended to the packet. */ 2342 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2343 2344 /* We want short frames padded to 60 bytes. */ 2345 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2346 2347 /* 2348 * Enable the reception of all error frames. This is is 2349 * a necessary evil due to the design of the XMAC. The 2350 * XMAC's receive FIFO is only 8K in size, however jumbo 2351 * frames can be up to 9000 bytes in length. When bad 2352 * frame filtering is enabled, the XMAC's RX FIFO operates 2353 * in 'store and forward' mode. For this to work, the 2354 * entire frame has to fit into the FIFO, but that means 2355 * that jumbo frames larger than 8192 bytes will be 2356 * truncated. Disabling all bad frame filtering causes 2357 * the RX FIFO to operate in streaming mode, in which 2358 * case the XMAC will start transfering frames out of the 2359 * RX FIFO as soon as the FIFO threshold is reached. 2360 */ 2361 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2362 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2363 XM_MODE_RX_INRANGELEN); 2364 2365 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2366 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2367 else 2368 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2369 2370 /* 2371 * Bump up the transmit threshold. This helps hold off transmit 2372 * underruns when we're blasting traffic from both ports at once. 2373 */ 2374 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2375 2376 /* Set multicast filter */ 2377 sk_setmulti(sc_if); 2378 2379 /* Clear and enable interrupts */ 2380 SK_XM_READ_2(sc_if, XM_ISR); 2381 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2382 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2383 else 2384 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2385 2386 /* Configure MAC arbiter */ 2387 switch(sc_if->sk_xmac_rev) { 2388 case XM_XMAC_REV_B2: 2389 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2390 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2391 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2392 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2393 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2394 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2395 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2396 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2397 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2398 break; 2399 case XM_XMAC_REV_C1: 2400 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2401 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2402 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2403 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2404 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2405 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2406 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2407 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2408 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2409 break; 2410 default: 2411 break; 2412 } 2413 sk_win_write_2(sc, SK_MACARB_CTL, 2414 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2415 2416 sc_if->sk_link = 1; 2417 } 2418 2419 void sk_init_yukon(sc_if) 2420 struct sk_if_softc *sc_if; 2421 { 2422 u_int32_t /*mac, */phy; 2423 u_int16_t reg; 2424 struct sk_softc *sc; 2425 int i; 2426 2427 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2428 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2429 2430 sc = sc_if->sk_softc; 2431 if (sc->sk_type == SK_YUKON_LITE && 2432 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2433 /* Take PHY out of reset. */ 2434 sk_win_write_4(sc, SK_GPIO, 2435 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2436 } 2437 2438 2439 /* GMAC and GPHY Reset */ 2440 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2441 2442 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2443 2444 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2445 DELAY(1000); 2446 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2447 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2448 DELAY(1000); 2449 2450 2451 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2452 2453 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2454 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2455 2456 switch(sc_if->sk_softc->sk_pmd) { 2457 case IFM_1000_SX: 2458 case IFM_1000_LX: 2459 phy |= SK_GPHY_FIBER; 2460 break; 2461 2462 case IFM_1000_CX: 2463 case IFM_1000_T: 2464 phy |= SK_GPHY_COPPER; 2465 break; 2466 } 2467 2468 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2469 2470 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2471 DELAY(1000); 2472 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2473 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2474 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2475 2476 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2477 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2478 2479 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2480 2481 /* unused read of the interrupt source register */ 2482 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2483 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2484 2485 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2486 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2487 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2488 2489 /* MIB Counter Clear Mode set */ 2490 reg |= YU_PAR_MIB_CLR; 2491 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2492 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2493 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2494 2495 /* MIB Counter Clear Mode clear */ 2496 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2497 reg &= ~YU_PAR_MIB_CLR; 2498 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2499 2500 /* receive control reg */ 2501 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2502 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2503 YU_RCR_CRCR); 2504 2505 /* transmit parameter register */ 2506 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2507 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2508 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2509 2510 /* serial mode register */ 2511 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2512 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2513 YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e)); 2514 2515 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2516 /* Setup Yukon's address */ 2517 for (i = 0; i < 3; i++) { 2518 /* Write Source Address 1 (unicast filter) */ 2519 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2520 sc_if->sk_enaddr[i * 2] | 2521 sc_if->sk_enaddr[i * 2 + 1] << 8); 2522 } 2523 2524 for (i = 0; i < 3; i++) { 2525 reg = sk_win_read_2(sc_if->sk_softc, 2526 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2527 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2528 } 2529 2530 /* Set multicast filter */ 2531 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2532 sk_setmulti(sc_if); 2533 2534 /* enable interrupt mask for counter overflows */ 2535 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2536 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2537 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2538 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2539 2540 /* Configure RX MAC FIFO */ 2541 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2542 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2543 2544 /* Configure TX MAC FIFO */ 2545 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2546 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2547 2548 DPRINTFN(6, ("sk_init_yukon: end\n")); 2549 } 2550 2551 /* 2552 * Note that to properly initialize any part of the GEnesis chip, 2553 * you first have to take it out of reset mode. 2554 */ 2555 int 2556 sk_init(struct ifnet *ifp) 2557 { 2558 struct sk_if_softc *sc_if = ifp->if_softc; 2559 struct sk_softc *sc = sc_if->sk_softc; 2560 struct mii_data *mii = &sc_if->sk_mii; 2561 int s; 2562 u_int32_t imr, sk_imtimer_ticks; 2563 2564 DPRINTFN(1, ("sk_init\n")); 2565 2566 s = splnet(); 2567 2568 if (ifp->if_flags & IFF_RUNNING) { 2569 splx(s); 2570 return 0; 2571 } 2572 2573 /* Cancel pending I/O and free all RX/TX buffers. */ 2574 sk_stop(ifp,0); 2575 2576 if (sc->sk_type == SK_GENESIS) { 2577 /* Configure LINK_SYNC LED */ 2578 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2579 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2580 SK_LINKLED_LINKSYNC_ON); 2581 2582 /* Configure RX LED */ 2583 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2584 SK_RXLEDCTL_COUNTER_START); 2585 2586 /* Configure TX LED */ 2587 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2588 SK_TXLEDCTL_COUNTER_START); 2589 } 2590 2591 /* Configure I2C registers */ 2592 2593 /* Configure XMAC(s) */ 2594 switch (sc->sk_type) { 2595 case SK_GENESIS: 2596 sk_init_xmac(sc_if); 2597 break; 2598 case SK_YUKON: 2599 case SK_YUKON_LITE: 2600 case SK_YUKON_LP: 2601 sk_init_yukon(sc_if); 2602 break; 2603 } 2604 mii_mediachg(mii); 2605 2606 if (sc->sk_type == SK_GENESIS) { 2607 /* Configure MAC FIFOs */ 2608 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2609 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2610 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2611 2612 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2613 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2614 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2615 } 2616 2617 /* Configure transmit arbiter(s) */ 2618 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2619 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2620 2621 /* Configure RAMbuffers */ 2622 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2623 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2624 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2625 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2626 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2627 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2628 2629 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2630 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2631 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2632 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2633 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2634 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2635 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2636 2637 /* Configure BMUs */ 2638 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2639 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2640 SK_RX_RING_ADDR(sc_if, 0)); 2641 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2642 2643 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2644 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2645 SK_TX_RING_ADDR(sc_if, 0)); 2646 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2647 2648 /* Init descriptors */ 2649 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2650 printf("%s: initialization failed: no " 2651 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2652 sk_stop(ifp,0); 2653 splx(s); 2654 return(ENOBUFS); 2655 } 2656 2657 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2658 printf("%s: initialization failed: no " 2659 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2660 sk_stop(ifp,0); 2661 splx(s); 2662 return(ENOBUFS); 2663 } 2664 2665 /* Set interrupt moderation if changed via sysctl. */ 2666 switch (sc->sk_type) { 2667 case SK_GENESIS: 2668 sk_imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2669 break; 2670 case SK_YUKON_EC: 2671 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2672 break; 2673 default: 2674 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2675 } 2676 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2677 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2678 sk_win_write_4(sc, SK_IMTIMERINIT, 2679 SK_IM_USECS(sc->sk_int_mod)); 2680 aprint_verbose("%s: interrupt moderation is %d us\n", 2681 sc->sk_dev.dv_xname, sc->sk_int_mod); 2682 } 2683 2684 /* Configure interrupt handling */ 2685 CSR_READ_4(sc, SK_ISSR); 2686 if (sc_if->sk_port == SK_PORT_A) 2687 sc->sk_intrmask |= SK_INTRS1; 2688 else 2689 sc->sk_intrmask |= SK_INTRS2; 2690 2691 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2692 2693 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2694 2695 /* Start BMUs. */ 2696 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2697 2698 if (sc->sk_type == SK_GENESIS) { 2699 /* Enable XMACs TX and RX state machines */ 2700 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2701 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2702 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2703 } 2704 2705 if (SK_YUKON_FAMILY(sc->sk_type)) { 2706 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2707 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2708 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2709 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2710 } 2711 2712 2713 ifp->if_flags |= IFF_RUNNING; 2714 ifp->if_flags &= ~IFF_OACTIVE; 2715 2716 splx(s); 2717 return(0); 2718 } 2719 2720 void 2721 sk_stop(struct ifnet *ifp, int disable) 2722 { 2723 struct sk_if_softc *sc_if = ifp->if_softc; 2724 struct sk_softc *sc = sc_if->sk_softc; 2725 //struct sk_txmap_entry *dma; 2726 int i; 2727 2728 DPRINTFN(1, ("sk_stop\n")); 2729 2730 callout_stop(&sc_if->sk_tick_ch); 2731 2732 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2733 u_int32_t val; 2734 2735 /* Put PHY back into reset. */ 2736 val = sk_win_read_4(sc, SK_GPIO); 2737 if (sc_if->sk_port == SK_PORT_A) { 2738 val |= SK_GPIO_DIR0; 2739 val &= ~SK_GPIO_DAT0; 2740 } else { 2741 val |= SK_GPIO_DIR2; 2742 val &= ~SK_GPIO_DAT2; 2743 } 2744 sk_win_write_4(sc, SK_GPIO, val); 2745 } 2746 2747 /* Turn off various components of this interface. */ 2748 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2749 switch (sc->sk_type) { 2750 case SK_GENESIS: 2751 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2752 SK_TXMACCTL_XMAC_RESET); 2753 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2754 break; 2755 case SK_YUKON: 2756 case SK_YUKON_LITE: 2757 case SK_YUKON_LP: 2758 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2759 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2760 break; 2761 } 2762 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2763 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2764 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2765 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2766 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2767 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2768 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2769 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2770 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2771 2772 /* Disable interrupts */ 2773 if (sc_if->sk_port == SK_PORT_A) 2774 sc->sk_intrmask &= ~SK_INTRS1; 2775 else 2776 sc->sk_intrmask &= ~SK_INTRS2; 2777 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2778 2779 SK_XM_READ_2(sc_if, XM_ISR); 2780 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2781 2782 /* Free RX and TX mbufs still in the queues. */ 2783 for (i = 0; i < SK_RX_RING_CNT; i++) { 2784 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2785 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2786 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2787 } 2788 } 2789 2790 for (i = 0; i < SK_TX_RING_CNT; i++) { 2791 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2792 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2793 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2794 } 2795 } 2796 2797 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2798 } 2799 2800 CFATTACH_DECL(skc,sizeof(struct sk_softc), skc_probe, skc_attach, NULL, NULL); 2801 2802 /* 2803 struct cfdriver skc_cd = { 2804 0, "skc", DV_DULL 2805 }; 2806 */ 2807 2808 CFATTACH_DECL(sk,sizeof(struct sk_if_softc), sk_probe, sk_attach, NULL, NULL); 2809 2810 /* 2811 struct cfdriver sk_cd = { 2812 0, "sk", DV_IFNET 2813 }; 2814 */ 2815 2816 #ifdef SK_DEBUG 2817 void 2818 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2819 { 2820 #define DESC_PRINT(X) \ 2821 if (desc->X) \ 2822 printf("txdesc[%d]." #X "=%#x\n", \ 2823 idx, desc->X); 2824 2825 DESC_PRINT(sk_ctl); 2826 DESC_PRINT(sk_next); 2827 DESC_PRINT(sk_data_lo); 2828 DESC_PRINT(sk_data_hi); 2829 DESC_PRINT(sk_xmac_txstat); 2830 DESC_PRINT(sk_rsvd0); 2831 DESC_PRINT(sk_csum_startval); 2832 DESC_PRINT(sk_csum_startpos); 2833 DESC_PRINT(sk_csum_writepos); 2834 DESC_PRINT(sk_rsvd1); 2835 #undef PRINT 2836 } 2837 2838 void 2839 sk_dump_bytes(const char *data, int len) 2840 { 2841 int c, i, j; 2842 2843 for (i = 0; i < len; i += 16) { 2844 printf("%08x ", i); 2845 c = len - i; 2846 if (c > 16) c = 16; 2847 2848 for (j = 0; j < c; j++) { 2849 printf("%02x ", data[i + j] & 0xff); 2850 if ((j & 0xf) == 7 && j > 0) 2851 printf(" "); 2852 } 2853 2854 for (; j < 16; j++) 2855 printf(" "); 2856 printf(" "); 2857 2858 for (j = 0; j < c; j++) { 2859 int ch = data[i + j] & 0xff; 2860 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2861 } 2862 2863 printf("\n"); 2864 2865 if (c < 16) 2866 break; 2867 } 2868 } 2869 2870 void 2871 sk_dump_mbuf(struct mbuf *m) 2872 { 2873 int count = m->m_pkthdr.len; 2874 2875 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2876 2877 while (count > 0 && m) { 2878 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2879 m, m->m_data, m->m_len); 2880 sk_dump_bytes(mtod(m, char *), m->m_len); 2881 2882 count -= m->m_len; 2883 m = m->m_next; 2884 } 2885 } 2886 #endif 2887 2888 static int 2889 sk_sysctl_handler(SYSCTLFN_ARGS) 2890 { 2891 int error, t; 2892 struct sysctlnode node; 2893 struct sk_softc *sc; 2894 2895 node = *rnode; 2896 sc = node.sysctl_data; 2897 t = sc->sk_int_mod; 2898 node.sysctl_data = &t; 2899 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2900 if (error || newp == NULL) 2901 return (error); 2902 2903 if (t < SK_IM_MIN || t > SK_IM_MAX) 2904 return (EINVAL); 2905 2906 /* update the softc with sysctl-changed value, and mark 2907 for hardware update */ 2908 sc->sk_int_mod = t; 2909 sc->sk_int_mod_pending = 1; 2910 return (0); 2911 } 2912 2913 /* 2914 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 2915 * set up in skc_attach() 2916 */ 2917 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 2918 { 2919 int rc; 2920 struct sysctlnode *node; 2921 2922 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 2923 0, CTLTYPE_NODE, "hw", NULL, 2924 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 2925 goto err; 2926 } 2927 2928 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2929 0, CTLTYPE_NODE, "sk", 2930 SYSCTL_DESCR("sk interface controls"), 2931 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2932 goto err; 2933 } 2934 2935 sk_root_num = node->sysctl_num; 2936 return; 2937 2938 err: 2939 printf("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2940 } 2941
Indexes created Mon Oct 13 15:10:03 GMT 2025