if_sk.c revision 1.18
1 /* $NetBSD: if_sk.c,v 1.18 2005/11/23 18:56:22 riz Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* $OpenBSD: if_sk.c,v 1.33 2003/08/12 05:23:06 nate Exp $ */ 37 38 /* 39 * Copyright (c) 1997, 1998, 1999, 2000 40 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Bill Paul. 53 * 4. Neither the name of the author nor the names of any co-contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 67 * THE POSSIBILITY OF SUCH DAMAGE. 68 * 69 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 70 */ 71 72 /* 73 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 74 * 75 * Permission to use, copy, modify, and distribute this software for any 76 * purpose with or without fee is hereby granted, provided that the above 77 * copyright notice and this permission notice appear in all copies. 78 * 79 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 80 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 81 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 82 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 83 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 84 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 85 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 86 */ 87 88 /* 89 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 90 * the SK-984x series adapters, both single port and dual port. 91 * References: 92 * The XaQti XMAC II datasheet, 93 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * The SysKonnect GEnesis manual, http://www.syskonnect.com 95 * 96 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 97 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 98 * convenience to others until Vitesse corrects this problem: 99 * 100 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 101 * 102 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 103 * Department of Electrical Engineering 104 * Columbia University, New York City 105 */ 106 107 /* 108 * The SysKonnect gigabit ethernet adapters consist of two main 109 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 110 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 111 * components and a PHY while the GEnesis controller provides a PCI 112 * interface with DMA support. Each card may have between 512K and 113 * 2MB of SRAM on board depending on the configuration. 114 * 115 * The SysKonnect GEnesis controller can have either one or two XMAC 116 * chips connected to it, allowing single or dual port NIC configurations. 117 * SysKonnect has the distinction of being the only vendor on the market 118 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 119 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 120 * XMAC registers. This driver takes advantage of these features to allow 121 * both XMACs to operate as independent interfaces. 122 */ 123 124 #include "bpfilter.h" 125 126 #include <sys/param.h> 127 #include <sys/systm.h> 128 #include <sys/sockio.h> 129 #include <sys/mbuf.h> 130 #include <sys/malloc.h> 131 #include <sys/kernel.h> 132 #include <sys/socket.h> 133 #include <sys/device.h> 134 #include <sys/queue.h> 135 #include <sys/callout.h> 136 137 #include <net/if.h> 138 #include <net/if_dl.h> 139 #include <net/if_types.h> 140 141 #ifdef INET 142 #include <netinet/in.h> 143 #include <netinet/in_systm.h> 144 #include <netinet/in_var.h> 145 #include <netinet/ip.h> 146 #include <netinet/if_ether.h> 147 #endif 148 149 #include <net/if_media.h> 150 151 #if NBPFILTER > 0 152 #include <net/bpf.h> 153 #endif 154 155 #include <dev/mii/mii.h> 156 #include <dev/mii/miivar.h> 157 #include <dev/mii/brgphyreg.h> 158 159 #include <dev/pci/pcireg.h> 160 #include <dev/pci/pcivar.h> 161 #include <dev/pci/pcidevs.h> 162 163 #define SK_VERBOSE 164 /* #define SK_USEIOSPACE */ 165 166 #include <dev/pci/if_skreg.h> 167 #include <dev/pci/if_skvar.h> 168 169 int skc_probe(struct device *, struct cfdata *, void *); 170 void skc_attach(struct device *, struct device *self, void *aux); 171 int sk_probe(struct device *, struct cfdata *, void *); 172 void sk_attach(struct device *, struct device *self, void *aux); 173 int skcprint(void *, const char *); 174 int sk_intr(void *); 175 void sk_intr_bcom(struct sk_if_softc *); 176 void sk_intr_xmac(struct sk_if_softc *); 177 void sk_intr_yukon(struct sk_if_softc *); 178 void sk_rxeof(struct sk_if_softc *); 179 void sk_txeof(struct sk_if_softc *); 180 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 181 void sk_start(struct ifnet *); 182 int sk_ioctl(struct ifnet *, u_long, caddr_t); 183 int sk_init(struct ifnet *); 184 void sk_init_xmac(struct sk_if_softc *); 185 void sk_init_yukon(struct sk_if_softc *); 186 void sk_stop(struct ifnet *, int); 187 void sk_watchdog(struct ifnet *); 188 void sk_shutdown(void *); 189 int sk_ifmedia_upd(struct ifnet *); 190 void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 191 void sk_reset(struct sk_softc *); 192 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 193 int sk_init_rx_ring(struct sk_if_softc *); 194 int sk_init_tx_ring(struct sk_if_softc *); 195 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 196 void sk_vpd_read_res(struct sk_softc *, 197 struct vpd_res *, int); 198 void sk_vpd_read(struct sk_softc *); 199 200 int sk_xmac_miibus_readreg(struct device *, int, int); 201 void sk_xmac_miibus_writereg(struct device *, int, int, int); 202 void sk_xmac_miibus_statchg(struct device *); 203 204 int sk_marv_miibus_readreg(struct device *, int, int); 205 void sk_marv_miibus_writereg(struct device *, int, int, int); 206 void sk_marv_miibus_statchg(struct device *); 207 208 u_int32_t sk_xmac_hash(caddr_t); 209 u_int32_t sk_yukon_hash(caddr_t); 210 void sk_setfilt(struct sk_if_softc *, caddr_t, int); 211 void sk_setmulti(struct sk_if_softc *); 212 void sk_tick(void *); 213 214 /* #define SK_DEBUG 2 */ 215 #ifdef SK_DEBUG 216 #define DPRINTF(x) if (skdebug) printf x 217 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 218 int skdebug = SK_DEBUG; 219 220 void sk_dump_txdesc(struct sk_tx_desc *, int); 221 void sk_dump_mbuf(struct mbuf *); 222 void sk_dump_bytes(const char *, int); 223 #else 224 #define DPRINTF(x) 225 #define DPRINTFN(n,x) 226 #endif 227 228 #define SK_SETBIT(sc, reg, x) \ 229 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 230 231 #define SK_CLRBIT(sc, reg, x) \ 232 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 233 234 #define SK_WIN_SETBIT_4(sc, reg, x) \ 235 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 236 237 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 238 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 239 240 #define SK_WIN_SETBIT_2(sc, reg, x) \ 241 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 242 243 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 244 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 245 246 /* supported device vendors */ 247 static const struct sk_product { 248 pci_vendor_id_t sk_vendor; 249 pci_product_id_t sk_product; 250 } sk_products[] = { 251 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 252 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 253 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 254 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 255 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 256 { PCI_VENDOR_GALILEO, PCI_PRODUCT_GALILEO_SKNET, }, 257 { PCI_VENDOR_GALILEO, PCI_PRODUCT_GALILEO_BELKIN, }, 258 { 0, 0, } 259 }; 260 261 #define SK_LINKSYS_EG1032_SUBID 0x00151737 262 263 static inline u_int32_t 264 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 265 { 266 #ifdef SK_USEIOSPACE 267 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 268 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 269 #else 270 return CSR_READ_4(sc, reg); 271 #endif 272 } 273 274 static inline u_int16_t 275 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 276 { 277 #ifdef SK_USEIOSPACE 278 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 279 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 280 #else 281 return CSR_READ_2(sc, reg); 282 #endif 283 } 284 285 static inline u_int8_t 286 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 287 { 288 #ifdef SK_USEIOSPACE 289 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 290 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 291 #else 292 return CSR_READ_1(sc, reg); 293 #endif 294 } 295 296 static inline void 297 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 298 { 299 #ifdef SK_USEIOSPACE 300 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 301 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 302 #else 303 CSR_WRITE_4(sc, reg, x); 304 #endif 305 } 306 307 static inline void 308 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 309 { 310 #ifdef SK_USEIOSPACE 311 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 312 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 313 #else 314 CSR_WRITE_2(sc, reg, x); 315 #endif 316 } 317 318 static inline void 319 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 320 { 321 #ifdef SK_USEIOSPACE 322 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 323 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 324 #else 325 CSR_WRITE_1(sc, reg, x); 326 #endif 327 } 328 329 /* 330 * The VPD EEPROM contains Vital Product Data, as suggested in 331 * the PCI 2.1 specification. The VPD data is separared into areas 332 * denoted by resource IDs. The SysKonnect VPD contains an ID string 333 * resource (the name of the adapter), a read-only area resource 334 * containing various key/data fields and a read/write area which 335 * can be used to store asset management information or log messages. 336 * We read the ID string and read-only into buffers attached to 337 * the controller softc structure for later use. At the moment, 338 * we only use the ID string during sk_attach(). 339 */ 340 u_int8_t 341 sk_vpd_readbyte(struct sk_softc *sc, int addr) 342 { 343 int i; 344 345 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 346 for (i = 0; i < SK_TIMEOUT; i++) { 347 DELAY(1); 348 if (sk_win_read_2(sc, 349 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 350 break; 351 } 352 353 if (i == SK_TIMEOUT) 354 return(0); 355 356 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 357 } 358 359 void 360 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 361 { 362 int i; 363 u_int8_t *ptr; 364 365 ptr = (u_int8_t *)res; 366 for (i = 0; i < sizeof(struct vpd_res); i++) 367 ptr[i] = sk_vpd_readbyte(sc, i + addr); 368 } 369 370 void 371 sk_vpd_read(struct sk_softc *sc) 372 { 373 int pos = 0, i; 374 struct vpd_res res; 375 376 if (sc->sk_vpd_prodname != NULL) 377 free(sc->sk_vpd_prodname, M_DEVBUF); 378 if (sc->sk_vpd_readonly != NULL) 379 free(sc->sk_vpd_readonly, M_DEVBUF); 380 sc->sk_vpd_prodname = NULL; 381 sc->sk_vpd_readonly = NULL; 382 383 sk_vpd_read_res(sc, &res, pos); 384 385 if (res.vr_id != VPD_RES_ID) { 386 printf("%s: bad VPD resource id: expected %x got %x\n", 387 sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 388 return; 389 } 390 391 pos += sizeof(res); 392 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 393 if (sc->sk_vpd_prodname == NULL) 394 panic("sk_vpd_read"); 395 for (i = 0; i < res.vr_len; i++) 396 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 397 sc->sk_vpd_prodname[i] = '\0'; 398 pos += i; 399 400 sk_vpd_read_res(sc, &res, pos); 401 402 if (res.vr_id != VPD_RES_READ) { 403 printf("%s: bad VPD resource id: expected %x got %x\n", 404 sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 405 return; 406 } 407 408 pos += sizeof(res); 409 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 410 if (sc->sk_vpd_readonly == NULL) 411 panic("sk_vpd_read"); 412 for (i = 0; i < res.vr_len ; i++) 413 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 414 } 415 416 int 417 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 418 { 419 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 420 int i; 421 422 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 423 424 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 425 return(0); 426 427 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 428 SK_XM_READ_2(sc_if, XM_PHY_DATA); 429 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 430 for (i = 0; i < SK_TIMEOUT; i++) { 431 DELAY(1); 432 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 433 XM_MMUCMD_PHYDATARDY) 434 break; 435 } 436 437 if (i == SK_TIMEOUT) { 438 printf("%s: phy failed to come ready\n", 439 sc_if->sk_dev.dv_xname); 440 return(0); 441 } 442 } 443 DELAY(1); 444 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 445 } 446 447 void 448 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 449 { 450 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 451 int i; 452 453 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 454 455 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 456 for (i = 0; i < SK_TIMEOUT; i++) { 457 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 458 break; 459 } 460 461 if (i == SK_TIMEOUT) { 462 printf("%s: phy failed to come ready\n", 463 sc_if->sk_dev.dv_xname); 464 return; 465 } 466 467 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 468 for (i = 0; i < SK_TIMEOUT; i++) { 469 DELAY(1); 470 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 471 break; 472 } 473 474 if (i == SK_TIMEOUT) 475 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 476 } 477 478 void 479 sk_xmac_miibus_statchg(struct device *dev) 480 { 481 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 482 struct mii_data *mii = &sc_if->sk_mii; 483 484 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 485 486 /* 487 * If this is a GMII PHY, manually set the XMAC's 488 * duplex mode accordingly. 489 */ 490 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 491 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 492 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 493 } else { 494 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 495 } 496 } 497 } 498 499 int 500 sk_marv_miibus_readreg(dev, phy, reg) 501 struct device *dev; 502 int phy, reg; 503 { 504 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 505 u_int16_t val; 506 int i; 507 508 if (phy != 0 || 509 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 510 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 511 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 512 phy, reg)); 513 return(0); 514 } 515 516 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 517 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 518 519 for (i = 0; i < SK_TIMEOUT; i++) { 520 DELAY(1); 521 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 522 if (val & YU_SMICR_READ_VALID) 523 break; 524 } 525 526 if (i == SK_TIMEOUT) { 527 printf("%s: phy failed to come ready\n", 528 sc_if->sk_dev.dv_xname); 529 return 0; 530 } 531 532 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 533 SK_TIMEOUT)); 534 535 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 536 537 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 538 phy, reg, val)); 539 540 return val; 541 } 542 543 void 544 sk_marv_miibus_writereg(dev, phy, reg, val) 545 struct device *dev; 546 int phy, reg, val; 547 { 548 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 549 int i; 550 551 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 552 phy, reg, val)); 553 554 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 555 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 556 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 557 558 for (i = 0; i < SK_TIMEOUT; i++) { 559 DELAY(1); 560 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 561 break; 562 } 563 } 564 565 void 566 sk_marv_miibus_statchg(dev) 567 struct device *dev; 568 { 569 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 570 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 571 } 572 573 #define SK_HASH_BITS 6 574 575 u_int32_t 576 sk_xmac_hash(caddr_t addr) 577 { 578 u_int32_t crc; 579 580 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 581 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 582 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 583 return (crc); 584 } 585 586 u_int32_t 587 sk_yukon_hash(caddr_t addr) 588 { 589 u_int32_t crc; 590 591 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 592 crc &= ((1 << SK_HASH_BITS) - 1); 593 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 594 return (crc); 595 } 596 597 void 598 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 599 { 600 int base = XM_RXFILT_ENTRY(slot); 601 602 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 603 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 604 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 605 } 606 607 void 608 sk_setmulti(struct sk_if_softc *sc_if) 609 { 610 struct sk_softc *sc = sc_if->sk_softc; 611 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 612 u_int32_t hashes[2] = { 0, 0 }; 613 int h = 0, i; 614 struct ethercom *ec = &sc_if->sk_ethercom; 615 struct ether_multi *enm; 616 struct ether_multistep step; 617 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 618 619 /* First, zot all the existing filters. */ 620 switch(sc->sk_type) { 621 case SK_GENESIS: 622 for (i = 1; i < XM_RXFILT_MAX; i++) 623 sk_setfilt(sc_if, (caddr_t)&dummy, i); 624 625 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 626 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 627 break; 628 case SK_YUKON: 629 case SK_YUKON_LITE: 630 case SK_YUKON_LP: 631 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 632 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 633 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 634 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 635 break; 636 } 637 638 /* Now program new ones. */ 639 allmulti: 640 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 641 hashes[0] = 0xFFFFFFFF; 642 hashes[1] = 0xFFFFFFFF; 643 } else { 644 i = 1; 645 /* First find the tail of the list. */ 646 ETHER_FIRST_MULTI(step, ec, enm); 647 while (enm != NULL) { 648 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 649 ETHER_ADDR_LEN)) { 650 ifp->if_flags |= IFF_ALLMULTI; 651 goto allmulti; 652 } 653 DPRINTFN(2,("multicast address %s\n", 654 ether_sprintf(enm->enm_addrlo))); 655 /* 656 * Program the first XM_RXFILT_MAX multicast groups 657 * into the perfect filter. For all others, 658 * use the hash table. 659 */ 660 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 661 sk_setfilt(sc_if, enm->enm_addrlo, i); 662 i++; 663 } 664 else { 665 switch (sc->sk_type) { 666 case SK_GENESIS: 667 h = sk_xmac_hash(enm->enm_addrlo); 668 break; 669 case SK_YUKON: 670 case SK_YUKON_LITE: 671 case SK_YUKON_LP: 672 h = sk_yukon_hash(enm->enm_addrlo); 673 break; 674 } 675 if (h < 32) 676 hashes[0] |= (1 << h); 677 else 678 hashes[1] |= (1 << (h - 32)); 679 } 680 681 ETHER_NEXT_MULTI(step, enm); 682 } 683 } 684 685 switch(sc->sk_type) { 686 case SK_GENESIS: 687 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 688 XM_MODE_RX_USE_PERFECT); 689 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 690 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 691 break; 692 case SK_YUKON: 693 case SK_YUKON_LITE: 694 case SK_YUKON_LP: 695 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 696 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 697 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 698 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 699 break; 700 } 701 } 702 703 int 704 sk_init_rx_ring(struct sk_if_softc *sc_if) 705 { 706 struct sk_chain_data *cd = &sc_if->sk_cdata; 707 struct sk_ring_data *rd = sc_if->sk_rdata; 708 int i; 709 710 bzero((char *)rd->sk_rx_ring, 711 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 712 713 for (i = 0; i < SK_RX_RING_CNT; i++) { 714 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 715 if (i == (SK_RX_RING_CNT - 1)) { 716 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 717 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if, 0); 718 } else { 719 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 720 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if,i+1); 721 } 722 } 723 724 for (i = 0; i < SK_RX_RING_CNT; i++) { 725 if (sk_newbuf(sc_if, i, NULL, NULL) == ENOBUFS) { 726 printf("%s: failed alloc of %dth mbuf\n", 727 sc_if->sk_dev.dv_xname, i); 728 return(ENOBUFS); 729 } 730 } 731 sc_if->sk_cdata.sk_rx_prod = 0; 732 sc_if->sk_cdata.sk_rx_cons = 0; 733 734 return(0); 735 } 736 737 int 738 sk_init_tx_ring(struct sk_if_softc *sc_if) 739 { 740 struct sk_chain_data *cd = &sc_if->sk_cdata; 741 struct sk_ring_data *rd = sc_if->sk_rdata; 742 int i; 743 744 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 745 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 746 747 for (i = 0; i < SK_TX_RING_CNT; i++) { 748 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 749 if (i == (SK_TX_RING_CNT - 1)) { 750 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 751 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if, 0); 752 } else { 753 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 754 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if,i+1); 755 } 756 } 757 758 sc_if->sk_cdata.sk_tx_prod = 0; 759 sc_if->sk_cdata.sk_tx_cons = 0; 760 sc_if->sk_cdata.sk_tx_cnt = 0; 761 762 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 763 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 764 765 return (0); 766 } 767 768 int 769 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 770 bus_dmamap_t dmamap) 771 { 772 struct sk_softc *sc = sc_if->sk_softc; 773 struct mbuf *m_new = NULL; 774 struct sk_chain *c; 775 struct sk_rx_desc *r; 776 777 if (dmamap == NULL) { 778 /* if (m) panic() */ 779 780 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, MCLBYTES, 781 0, BUS_DMA_NOWAIT, &dmamap)) { 782 printf("%s: can't create recv map\n", 783 sc_if->sk_dev.dv_xname); 784 return(ENOMEM); 785 } 786 } else if (m == NULL) 787 bus_dmamap_unload(sc->sc_dmatag, dmamap); 788 789 sc_if->sk_cdata.sk_rx_map[i] = dmamap; 790 791 if (m == NULL) { 792 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 793 if (m_new == NULL) { 794 printf("%s: no memory for rx list -- " 795 "packet dropped!\n", sc_if->sk_dev.dv_xname); 796 return(ENOBUFS); 797 } 798 799 /* Allocate the jumbo buffer */ 800 MCLGET(m_new, M_DONTWAIT); 801 if (!(m_new->m_flags & M_EXT)) { 802 m_freem(m_new); 803 return (ENOBUFS); 804 } 805 806 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 807 808 m_adj(m_new, ETHER_ALIGN); 809 810 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m_new, 811 BUS_DMA_NOWAIT)) 812 return(ENOBUFS); 813 } else { 814 /* 815 * We're re-using a previously allocated mbuf; 816 * be sure to re-init pointers and lengths to 817 * default values. 818 */ 819 m_new = m; 820 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 821 m_adj(m_new, ETHER_ALIGN); 822 m_new->m_data = m_new->m_ext.ext_buf; 823 } 824 825 c = &sc_if->sk_cdata.sk_rx_chain[i]; 826 r = c->sk_desc; 827 c->sk_mbuf = m_new; 828 r->sk_data_lo = dmamap->dm_segs[0].ds_addr; 829 r->sk_ctl = dmamap->dm_segs[0].ds_len | SK_RXSTAT; 830 831 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 832 833 return(0); 834 } 835 836 /* 837 * Set media options. 838 */ 839 int 840 sk_ifmedia_upd(struct ifnet *ifp) 841 { 842 struct sk_if_softc *sc_if = ifp->if_softc; 843 844 (void) sk_init(ifp); 845 mii_mediachg(&sc_if->sk_mii); 846 return(0); 847 } 848 849 /* 850 * Report current media status. 851 */ 852 void 853 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 854 { 855 struct sk_if_softc *sc_if = ifp->if_softc; 856 857 mii_pollstat(&sc_if->sk_mii); 858 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 859 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 860 } 861 862 int 863 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 864 { 865 struct sk_if_softc *sc_if = ifp->if_softc; 866 struct sk_softc *sc = sc_if->sk_softc; 867 struct ifreq *ifr = (struct ifreq *) data; 868 /* struct ifaddr *ifa = (struct ifaddr *) data; */ 869 struct mii_data *mii; 870 int s, error = 0; 871 872 /* DPRINTFN(2, ("sk_ioctl\n")); */ 873 874 s = splnet(); 875 876 switch(command) { 877 878 case SIOCSIFFLAGS: 879 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 880 if (ifp->if_flags & IFF_UP) { 881 if (ifp->if_flags & IFF_RUNNING && 882 ifp->if_flags & IFF_PROMISC && 883 !(sc_if->sk_if_flags & IFF_PROMISC)) { 884 switch(sc->sk_type) { 885 case SK_GENESIS: 886 SK_XM_SETBIT_4(sc_if, XM_MODE, 887 XM_MODE_RX_PROMISC); 888 break; 889 case SK_YUKON: 890 case SK_YUKON_LITE: 891 case SK_YUKON_LP: 892 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 893 YU_RCR_UFLEN | YU_RCR_MUFLEN); 894 break; 895 } 896 sk_setmulti(sc_if); 897 } else if (ifp->if_flags & IFF_RUNNING && 898 !(ifp->if_flags & IFF_PROMISC) && 899 sc_if->sk_if_flags & IFF_PROMISC) { 900 switch(sc->sk_type) { 901 case SK_GENESIS: 902 SK_XM_CLRBIT_4(sc_if, XM_MODE, 903 XM_MODE_RX_PROMISC); 904 break; 905 case SK_YUKON: 906 case SK_YUKON_LITE: 907 case SK_YUKON_LP: 908 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 909 YU_RCR_UFLEN | YU_RCR_MUFLEN); 910 break; 911 } 912 913 sk_setmulti(sc_if); 914 } else 915 (void) sk_init(ifp); 916 } else { 917 if (ifp->if_flags & IFF_RUNNING) 918 sk_stop(ifp,0); 919 } 920 sc_if->sk_if_flags = ifp->if_flags; 921 error = 0; 922 break; 923 924 case SIOCGIFMEDIA: 925 case SIOCSIFMEDIA: 926 DPRINTFN(2, ("sk_ioctl MEDIA\n")); 927 mii = &sc_if->sk_mii; 928 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 929 break; 930 default: 931 DPRINTFN(2, ("sk_ioctl ETHER\n")); 932 error = ether_ioctl(ifp, command, data); 933 934 if ( error == ENETRESET) { 935 if (ifp->if_flags & IFF_RUNNING) { 936 sk_setmulti(sc_if); 937 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 938 } 939 error = 0; 940 } else if ( error ) { 941 splx(s); 942 return error; 943 } 944 break; 945 } 946 947 splx(s); 948 return(error); 949 } 950 951 /* 952 * Lookup: Check the PCI vendor and device, and return a pointer to 953 * The structure if the IDs match against our list. 954 */ 955 956 static const struct sk_product * 957 sk_lookup(const struct pci_attach_args *pa) 958 { 959 const struct sk_product *psk; 960 961 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 962 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 963 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 964 return (psk); 965 } 966 return (NULL); 967 } 968 969 /* 970 * Probe for a SysKonnect GEnesis chip. 971 */ 972 973 int 974 skc_probe(struct device *parent, struct cfdata *match, void *aux) 975 { 976 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 977 const struct sk_product *psk; 978 pcireg_t subid; 979 980 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 981 982 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 983 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 984 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 985 subid == SK_LINKSYS_EG1032_SUBID) 986 return(1); 987 988 if ((psk = sk_lookup(pa))) { 989 return(1); 990 } 991 return(0); 992 } 993 994 /* 995 * Force the GEnesis into reset, then bring it out of reset. 996 */ 997 void sk_reset(struct sk_softc *sc) 998 { 999 DPRINTFN(2, ("sk_reset\n")); 1000 1001 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1002 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1003 if (SK_YUKON_FAMILY(sc->sk_type)) 1004 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1005 1006 DELAY(1000); 1007 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1008 DELAY(2); 1009 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1010 if (SK_YUKON_FAMILY(sc->sk_type)) 1011 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1012 1013 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1014 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1015 CSR_READ_2(sc, SK_LINK_CTRL))); 1016 1017 if (sc->sk_type == SK_GENESIS) { 1018 /* Configure packet arbiter */ 1019 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1020 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1021 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1022 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1023 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1024 } 1025 1026 /* Enable RAM interface */ 1027 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1028 1029 /* 1030 * Configure interrupt moderation. The moderation timer 1031 * defers interrupts specified in the interrupt moderation 1032 * timer mask based on the timeout specified in the interrupt 1033 * moderation timer init register. Each bit in the timer 1034 * register represents 18.825ns, so to specify a timeout in 1035 * microseconds, we have to multiply by 54. 1036 */ 1037 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(100)); 1038 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1039 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1040 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1041 } 1042 1043 int 1044 sk_probe(struct device *parent, struct cfdata *match, void *aux) 1045 { 1046 struct skc_attach_args *sa = aux; 1047 1048 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1049 return(0); 1050 1051 return (1); 1052 } 1053 1054 /* 1055 * Each XMAC chip is attached as a separate logical IP interface. 1056 * Single port cards will have only one logical interface of course. 1057 */ 1058 void 1059 sk_attach(struct device *parent, struct device *self, void *aux) 1060 { 1061 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1062 struct sk_softc *sc = (struct sk_softc *)parent; 1063 struct skc_attach_args *sa = aux; 1064 struct sk_txmap_entry *entry; 1065 struct ifnet *ifp; 1066 bus_dma_segment_t seg; 1067 bus_dmamap_t dmamap; 1068 caddr_t kva; 1069 int i, rseg; 1070 1071 sc_if->sk_port = sa->skc_port; 1072 sc_if->sk_softc = sc; 1073 sc->sk_if[sa->skc_port] = sc_if; 1074 1075 if (sa->skc_port == SK_PORT_A) 1076 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1077 if (sa->skc_port == SK_PORT_B) 1078 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1079 1080 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1081 1082 /* 1083 * Get station address for this interface. Note that 1084 * dual port cards actually come with three station 1085 * addresses: one for each port, plus an extra. The 1086 * extra one is used by the SysKonnect driver software 1087 * as a 'virtual' station address for when both ports 1088 * are operating in failover mode. Currently we don't 1089 * use this extra address. 1090 */ 1091 for (i = 0; i < ETHER_ADDR_LEN; i++) 1092 sc_if->sk_enaddr[i] = 1093 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1094 1095 1096 aprint_normal(": Ethernet address %s\n", 1097 ether_sprintf(sc_if->sk_enaddr)); 1098 1099 /* 1100 * Set up RAM buffer addresses. The NIC will have a certain 1101 * amount of SRAM on it, somewhere between 512K and 2MB. We 1102 * need to divide this up a) between the transmitter and 1103 * receiver and b) between the two XMACs, if this is a 1104 * dual port NIC. Our algotithm is to divide up the memory 1105 * evenly so that everyone gets a fair share. 1106 */ 1107 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1108 u_int32_t chunk, val; 1109 1110 chunk = sc->sk_ramsize / 2; 1111 val = sc->sk_rboff / sizeof(u_int64_t); 1112 sc_if->sk_rx_ramstart = val; 1113 val += (chunk / sizeof(u_int64_t)); 1114 sc_if->sk_rx_ramend = val - 1; 1115 sc_if->sk_tx_ramstart = val; 1116 val += (chunk / sizeof(u_int64_t)); 1117 sc_if->sk_tx_ramend = val - 1; 1118 } else { 1119 u_int32_t chunk, val; 1120 1121 chunk = sc->sk_ramsize / 4; 1122 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1123 sizeof(u_int64_t); 1124 sc_if->sk_rx_ramstart = val; 1125 val += (chunk / sizeof(u_int64_t)); 1126 sc_if->sk_rx_ramend = val - 1; 1127 sc_if->sk_tx_ramstart = val; 1128 val += (chunk / sizeof(u_int64_t)); 1129 sc_if->sk_tx_ramend = val - 1; 1130 } 1131 1132 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1133 " tx_ramstart=%#x tx_ramend=%#x\n", 1134 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1135 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1136 1137 /* Read and save PHY type and set PHY address */ 1138 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1139 switch (sc_if->sk_phytype) { 1140 case SK_PHYTYPE_XMAC: 1141 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1142 break; 1143 case SK_PHYTYPE_BCOM: 1144 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1145 break; 1146 case SK_PHYTYPE_MARV_COPPER: 1147 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1148 break; 1149 default: 1150 aprint_error("%s: unsupported PHY type: %d\n", 1151 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1152 return; 1153 } 1154 1155 /* Allocate the descriptor queues. */ 1156 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1157 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1158 aprint_error("%s: can't alloc rx buffers\n", 1159 sc->sk_dev.dv_xname); 1160 goto fail; 1161 } 1162 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1163 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1164 aprint_error("%s: can't map dma buffers (%lu bytes)\n", 1165 sc_if->sk_dev.dv_xname, 1166 (u_long) sizeof(struct sk_ring_data)); 1167 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1168 goto fail; 1169 } 1170 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1171 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1172 &sc_if->sk_ring_map)) { 1173 aprint_error("%s: can't create dma map\n", 1174 sc_if->sk_dev.dv_xname); 1175 bus_dmamem_unmap(sc->sc_dmatag, kva, 1176 sizeof(struct sk_ring_data)); 1177 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1178 goto fail; 1179 } 1180 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1181 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1182 aprint_error("%s: can't load dma map\n", 1183 sc_if->sk_dev.dv_xname); 1184 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1185 bus_dmamem_unmap(sc->sc_dmatag, kva, 1186 sizeof(struct sk_ring_data)); 1187 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1188 goto fail; 1189 } 1190 1191 for (i = 0; i < SK_RX_RING_CNT; i++) 1192 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1193 1194 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1195 for (i = 0; i < SK_TX_RING_CNT; i++) { 1196 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1197 1198 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, SK_NTXSEG, 1199 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap)) { 1200 aprint_error("%s: Can't create TX dmamap\n", 1201 sc_if->sk_dev.dv_xname); 1202 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1203 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1204 bus_dmamem_unmap(sc->sc_dmatag, kva, 1205 sizeof(struct sk_ring_data)); 1206 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1207 goto fail; 1208 } 1209 1210 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1211 if (!entry) { 1212 aprint_error("%s: Can't alloc txmap entry\n", 1213 sc_if->sk_dev.dv_xname); 1214 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1215 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1216 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1217 bus_dmamem_unmap(sc->sc_dmatag, kva, 1218 sizeof(struct sk_ring_data)); 1219 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1220 goto fail; 1221 } 1222 entry->dmamap = dmamap; 1223 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1224 } 1225 1226 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1227 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1228 1229 /* XXX TLS It's not clear what's wrong with the Jumbo MTU 1230 XXX TLS support in this driver, so we don't enable it. */ 1231 1232 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1233 1234 ifp = &sc_if->sk_ethercom.ec_if; 1235 ifp->if_softc = sc_if; 1236 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1237 ifp->if_ioctl = sk_ioctl; 1238 ifp->if_start = sk_start; 1239 ifp->if_stop = sk_stop; 1240 ifp->if_init = sk_init; 1241 ifp->if_watchdog = sk_watchdog; 1242 ifp->if_capabilities = 0; 1243 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1244 IFQ_SET_READY(&ifp->if_snd); 1245 strcpy(ifp->if_xname, sc_if->sk_dev.dv_xname); 1246 1247 /* 1248 * Do miibus setup. 1249 */ 1250 switch (sc->sk_type) { 1251 case SK_GENESIS: 1252 sk_init_xmac(sc_if); 1253 break; 1254 case SK_YUKON: 1255 case SK_YUKON_LITE: 1256 case SK_YUKON_LP: 1257 sk_init_yukon(sc_if); 1258 break; 1259 default: 1260 panic("%s: unknown device type %d", sc->sk_dev.dv_xname, 1261 sc->sk_type); 1262 } 1263 1264 DPRINTFN(2, ("sk_attach: 1\n")); 1265 1266 sc_if->sk_mii.mii_ifp = ifp; 1267 switch (sc->sk_type) { 1268 case SK_GENESIS: 1269 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1270 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1271 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1272 break; 1273 case SK_YUKON: 1274 case SK_YUKON_LITE: 1275 case SK_YUKON_LP: 1276 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1277 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1278 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1279 break; 1280 } 1281 1282 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1283 sk_ifmedia_upd, sk_ifmedia_sts); 1284 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1285 MII_OFFSET_ANY, 0); 1286 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1287 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1288 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1289 0, NULL); 1290 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1291 } 1292 else 1293 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1294 1295 callout_init(&sc_if->sk_tick_ch); 1296 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1297 1298 DPRINTFN(2, ("sk_attach: 1\n")); 1299 1300 /* 1301 * Call MI attach routines. 1302 */ 1303 if_attach(ifp); 1304 1305 ether_ifattach(ifp, sc_if->sk_enaddr); 1306 1307 #if NRND > 0 1308 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1309 RND_TYPE_NET, 0); 1310 #endif 1311 1312 DPRINTFN(2, ("sk_attach: end\n")); 1313 1314 return; 1315 1316 fail: 1317 sc->sk_if[sa->skc_port] = NULL; 1318 } 1319 1320 int 1321 skcprint(void *aux, const char *pnp) 1322 { 1323 struct skc_attach_args *sa = aux; 1324 1325 if (pnp) 1326 aprint_normal("sk port %c at %s", 1327 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1328 else 1329 aprint_normal(" port %c", 1330 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1331 return (UNCONF); 1332 } 1333 1334 /* 1335 * Attach the interface. Allocate softc structures, do ifmedia 1336 * setup and ethernet/BPF attach. 1337 */ 1338 void 1339 skc_attach(struct device *parent, struct device *self, void *aux) 1340 { 1341 struct sk_softc *sc = (struct sk_softc *)self; 1342 struct pci_attach_args *pa = aux; 1343 struct skc_attach_args skca; 1344 pci_chipset_tag_t pc = pa->pa_pc; 1345 pcireg_t memtype; 1346 pci_intr_handle_t ih; 1347 const char *intrstr = NULL; 1348 bus_addr_t iobase; 1349 bus_size_t iosize; 1350 int s; 1351 u_int32_t command; 1352 const char *revstr; 1353 1354 DPRINTFN(2, ("begin skc_attach\n")); 1355 1356 s = splnet(); 1357 1358 /* 1359 * Handle power management nonsense. 1360 */ 1361 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1362 1363 if (command == 0x01) { 1364 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1365 if (command & SK_PSTATE_MASK) { 1366 u_int32_t xiobase, membase, irq; 1367 1368 /* Save important PCI config data. */ 1369 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1370 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1371 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1372 1373 /* Reset the power state. */ 1374 aprint_normal("%s chip is in D%d power mode " 1375 "-- setting to D0\n", sc->sk_dev.dv_xname, 1376 command & SK_PSTATE_MASK); 1377 command &= 0xFFFFFFFC; 1378 pci_conf_write(pc, pa->pa_tag, 1379 SK_PCI_PWRMGMTCTRL, command); 1380 1381 /* Restore PCI config data. */ 1382 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1383 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1384 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1385 } 1386 } 1387 1388 /* 1389 * Map control/status registers. 1390 */ 1391 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1392 command |= PCI_COMMAND_IO_ENABLE | 1393 PCI_COMMAND_MEM_ENABLE | 1394 PCI_COMMAND_MASTER_ENABLE; 1395 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1396 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1397 1398 #ifdef SK_USEIOSPACE 1399 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1400 aprint_error(": failed to enable I/O ports!\n"); 1401 goto fail; 1402 } 1403 /* 1404 * Map control/status registers. 1405 */ 1406 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1407 &iobase, &iosize)) { 1408 aprint_error(": can't find i/o space\n"); 1409 goto fail; 1410 } 1411 #else 1412 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1413 aprint_error(": failed to enable memory mapping!\n"); 1414 goto fail; 1415 } 1416 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1417 switch (memtype) { 1418 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1419 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1420 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1421 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1422 &iobase, &iosize) == 0) 1423 break; 1424 default: 1425 aprint_error("%s: can't find mem space\n", 1426 sc->sk_dev.dv_xname); 1427 return; 1428 } 1429 1430 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1431 #endif 1432 sc->sc_dmatag = pa->pa_dmat; 1433 1434 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1435 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1436 1437 /* bail out here if chip is not recognized */ 1438 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1439 aprint_error("%s: unknown chip type\n",sc->sk_dev.dv_xname); 1440 goto fail; 1441 } 1442 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1443 1444 /* Allocate interrupt */ 1445 if (pci_intr_map(pa, &ih)) { 1446 aprint_error(": couldn't map interrupt\n"); 1447 goto fail; 1448 } 1449 1450 intrstr = pci_intr_string(pc, ih); 1451 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1452 if (sc->sk_intrhand == NULL) { 1453 aprint_error(": couldn't establish interrupt"); 1454 if (intrstr != NULL) 1455 aprint_normal(" at %s", intrstr); 1456 goto fail; 1457 } 1458 aprint_normal(": %s\n", intrstr); 1459 1460 /* Reset the adapter. */ 1461 sk_reset(sc); 1462 1463 /* Read and save vital product data from EEPROM. */ 1464 sk_vpd_read(sc); 1465 1466 if (sc->sk_type == SK_GENESIS) { 1467 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1468 /* Read and save RAM size and RAMbuffer offset */ 1469 switch(val) { 1470 case SK_RAMSIZE_512K_64: 1471 sc->sk_ramsize = 0x80000; 1472 sc->sk_rboff = SK_RBOFF_0; 1473 break; 1474 case SK_RAMSIZE_1024K_64: 1475 sc->sk_ramsize = 0x100000; 1476 sc->sk_rboff = SK_RBOFF_80000; 1477 break; 1478 case SK_RAMSIZE_1024K_128: 1479 sc->sk_ramsize = 0x100000; 1480 sc->sk_rboff = SK_RBOFF_0; 1481 break; 1482 case SK_RAMSIZE_2048K_128: 1483 sc->sk_ramsize = 0x200000; 1484 sc->sk_rboff = SK_RBOFF_0; 1485 break; 1486 default: 1487 aprint_error("%s: unknown ram size: %d\n", 1488 sc->sk_dev.dv_xname, val); 1489 goto fail; 1490 break; 1491 } 1492 1493 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1494 sc->sk_ramsize, sc->sk_ramsize / 1024, 1495 sc->sk_rboff)); 1496 } else { 1497 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1498 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1499 sc->sk_rboff = SK_RBOFF_0; 1500 1501 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1502 sc->sk_ramsize / 1024, sc->sk_ramsize, 1503 sc->sk_rboff)); 1504 } 1505 1506 /* Read and save physical media type */ 1507 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1508 case SK_PMD_1000BASESX: 1509 sc->sk_pmd = IFM_1000_SX; 1510 break; 1511 case SK_PMD_1000BASELX: 1512 sc->sk_pmd = IFM_1000_LX; 1513 break; 1514 case SK_PMD_1000BASECX: 1515 sc->sk_pmd = IFM_1000_CX; 1516 break; 1517 case SK_PMD_1000BASETX: 1518 sc->sk_pmd = IFM_1000_T; 1519 break; 1520 default: 1521 aprint_error("%s: unknown media type: 0x%x\n", 1522 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1523 goto fail; 1524 } 1525 1526 /* determine whether to name it with vpd or just make it up */ 1527 /* Marvell Yukon VPD's can freqently be bogus */ 1528 1529 switch (pa->pa_id) { 1530 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1531 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1532 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1533 case PCI_PRODUCT_3COM_3C940: 1534 case PCI_PRODUCT_DLINK_DGE530T: 1535 case PCI_PRODUCT_LINKSYS_EG1032: 1536 case PCI_PRODUCT_LINKSYS_EG1064: 1537 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1538 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1539 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1540 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1541 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1542 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1543 sc->sk_name = sc->sk_vpd_prodname; 1544 break; 1545 case PCI_ID_CODE(PCI_VENDOR_GALILEO,PCI_PRODUCT_GALILEO_SKNET): 1546 /* whoops yukon vpd prodname bears no resemblance to reality */ 1547 switch (sc->sk_type) { 1548 case SK_GENESIS: 1549 sc->sk_name = sc->sk_vpd_prodname; 1550 break; 1551 case SK_YUKON: 1552 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1553 break; 1554 case SK_YUKON_LITE: 1555 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1556 break; 1557 case SK_YUKON_LP: 1558 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1559 break; 1560 default: 1561 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1562 } 1563 1564 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1565 1566 if ( sc->sk_type == SK_YUKON ) { 1567 uint32_t flashaddr; 1568 uint8_t testbyte; 1569 1570 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1571 1572 /* test Flash-Address Register */ 1573 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1574 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1575 1576 if (testbyte != 0) { 1577 /* this is yukon lite Rev. A0 */ 1578 sc->sk_type = SK_YUKON_LITE; 1579 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1580 /* restore Flash-Address Register */ 1581 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1582 } 1583 } 1584 break; 1585 case PCI_ID_CODE(PCI_VENDOR_GALILEO,PCI_PRODUCT_GALILEO_BELKIN): 1586 sc->sk_name = sc->sk_vpd_prodname; 1587 break; 1588 default: 1589 sc->sk_name = "Unkown Marvell"; 1590 } 1591 1592 1593 if ( sc->sk_type == SK_YUKON_LITE ) { 1594 switch (sc->sk_rev) { 1595 case SK_YUKON_LITE_REV_A0: 1596 revstr = "A0"; 1597 break; 1598 case SK_YUKON_LITE_REV_A1: 1599 revstr = "A1"; 1600 break; 1601 case SK_YUKON_LITE_REV_A3: 1602 revstr = "A3"; 1603 break; 1604 default: 1605 revstr = ""; 1606 } 1607 } else { 1608 revstr = ""; 1609 } 1610 1611 /* Announce the product name. */ 1612 aprint_normal("%s: %s rev. %s(0x%x)\n", sc->sk_dev.dv_xname, 1613 sc->sk_name, revstr, sc->sk_rev); 1614 1615 skca.skc_port = SK_PORT_A; 1616 (void)config_found(&sc->sk_dev, &skca, skcprint); 1617 1618 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1619 skca.skc_port = SK_PORT_B; 1620 (void)config_found(&sc->sk_dev, &skca, skcprint); 1621 } 1622 1623 /* Turn on the 'driver is loaded' LED. */ 1624 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1625 1626 fail: 1627 splx(s); 1628 } 1629 1630 int 1631 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1632 { 1633 struct sk_softc *sc = sc_if->sk_softc; 1634 struct sk_tx_desc *f = NULL; 1635 u_int32_t frag, cur, cnt = 0; 1636 int i; 1637 struct sk_txmap_entry *entry; 1638 bus_dmamap_t txmap; 1639 1640 DPRINTFN(3, ("sk_encap\n")); 1641 1642 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1643 if (entry == NULL) { 1644 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1645 return ENOBUFS; 1646 } 1647 txmap = entry->dmamap; 1648 1649 cur = frag = *txidx; 1650 1651 #ifdef SK_DEBUG 1652 if (skdebug >= 3) 1653 sk_dump_mbuf(m_head); 1654 #endif 1655 1656 /* 1657 * Start packing the mbufs in this chain into 1658 * the fragment pointers. Stop when we run out 1659 * of fragments or hit the end of the mbuf chain. 1660 */ 1661 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1662 BUS_DMA_NOWAIT)) { 1663 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1664 return(ENOBUFS); 1665 } 1666 1667 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1668 1669 /* Sync the DMA map. */ 1670 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1671 BUS_DMASYNC_PREWRITE); 1672 1673 for (i = 0; i < txmap->dm_nsegs; i++) { 1674 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1675 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1676 return(ENOBUFS); 1677 } 1678 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1679 f->sk_data_lo = txmap->dm_segs[i].ds_addr; 1680 f->sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1681 if (cnt == 0) 1682 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1683 else 1684 f->sk_ctl |= SK_TXCTL_OWN; 1685 1686 cur = frag; 1687 SK_INC(frag, SK_TX_RING_CNT); 1688 cnt++; 1689 } 1690 1691 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1692 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1693 1694 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1695 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1696 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1697 1698 /* Sync descriptors before handing to chip */ 1699 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1700 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1701 1702 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1703 1704 /* Sync first descriptor to hand it off */ 1705 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1706 1707 sc_if->sk_cdata.sk_tx_cnt += cnt; 1708 1709 #ifdef SK_DEBUG 1710 if (skdebug >= 3) { 1711 struct sk_tx_desc *desc; 1712 u_int32_t idx; 1713 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1714 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1715 sk_dump_txdesc(desc, idx); 1716 } 1717 } 1718 #endif 1719 1720 *txidx = frag; 1721 1722 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1723 1724 return(0); 1725 } 1726 1727 void 1728 sk_start(struct ifnet *ifp) 1729 { 1730 struct sk_if_softc *sc_if = ifp->if_softc; 1731 struct sk_softc *sc = sc_if->sk_softc; 1732 struct mbuf *m_head = NULL; 1733 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1734 int pkts = 0; 1735 1736 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1737 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1738 1739 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1740 1741 IFQ_POLL(&ifp->if_snd, m_head); 1742 if (m_head == NULL) 1743 break; 1744 1745 /* 1746 * Pack the data into the transmit ring. If we 1747 * don't have room, set the OACTIVE flag and wait 1748 * for the NIC to drain the ring. 1749 */ 1750 if (sk_encap(sc_if, m_head, &idx)) { 1751 ifp->if_flags |= IFF_OACTIVE; 1752 break; 1753 } 1754 1755 /* now we are committed to transmit the packet */ 1756 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1757 pkts++; 1758 1759 /* 1760 * If there's a BPF listener, bounce a copy of this frame 1761 * to him. 1762 */ 1763 #if NBPFILTER > 0 1764 if (ifp->if_bpf) 1765 bpf_mtap(ifp->if_bpf, m_head); 1766 #endif 1767 } 1768 if (pkts == 0) 1769 return; 1770 1771 /* Transmit */ 1772 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1773 sc_if->sk_cdata.sk_tx_prod = idx; 1774 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1775 1776 /* Set a timeout in case the chip goes out to lunch. */ 1777 ifp->if_timer = 5; 1778 } 1779 } 1780 1781 1782 void 1783 sk_watchdog(struct ifnet *ifp) 1784 { 1785 struct sk_if_softc *sc_if = ifp->if_softc; 1786 1787 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1788 (void) sk_init(ifp); 1789 } 1790 1791 void 1792 sk_shutdown(void * v) 1793 { 1794 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 1795 struct sk_softc *sc = sc_if->sk_softc; 1796 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1797 1798 DPRINTFN(2, ("sk_shutdown\n")); 1799 sk_stop(ifp,1); 1800 1801 /* Turn off the 'driver is loaded' LED. */ 1802 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1803 1804 /* 1805 * Reset the GEnesis controller. Doing this should also 1806 * assert the resets on the attached XMAC(s). 1807 */ 1808 sk_reset(sc); 1809 } 1810 1811 void 1812 sk_rxeof(struct sk_if_softc *sc_if) 1813 { 1814 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1815 struct mbuf *m; 1816 struct sk_chain *cur_rx; 1817 struct sk_rx_desc *cur_desc; 1818 int i, cur, total_len = 0; 1819 u_int32_t rxstat; 1820 bus_dmamap_t dmamap; 1821 1822 i = sc_if->sk_cdata.sk_rx_prod; 1823 1824 DPRINTFN(3, ("sk_rxeof %d\n", i)); 1825 1826 for (;;) { 1827 cur = i; 1828 1829 /* Sync the descriptor */ 1830 SK_CDRXSYNC(sc_if, cur, 1831 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1832 1833 if (sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl & SK_RXCTL_OWN) { 1834 /* Invalidate the descriptor -- it's not ready yet */ 1835 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 1836 sc_if->sk_cdata.sk_rx_prod = i; 1837 break; 1838 } 1839 1840 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1841 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 1842 dmamap = sc_if->sk_cdata.sk_rx_map[cur]; 1843 1844 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1845 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1846 1847 rxstat = cur_desc->sk_xmac_rxstat; 1848 m = cur_rx->sk_mbuf; 1849 cur_rx->sk_mbuf = NULL; 1850 total_len = SK_RXBYTES(cur_desc->sk_ctl); 1851 1852 sc_if->sk_cdata.sk_rx_map[cur] = 0; 1853 1854 SK_INC(i, SK_RX_RING_CNT); 1855 1856 if (rxstat & XM_RXSTAT_ERRFRAME) { 1857 ifp->if_ierrors++; 1858 sk_newbuf(sc_if, cur, m, dmamap); 1859 continue; 1860 } 1861 1862 /* 1863 * Try to allocate a new jumbo buffer. If that 1864 * fails, copy the packet to mbufs and put the 1865 * jumbo buffer back in the ring so it can be 1866 * re-used. If allocating mbufs fails, then we 1867 * have to drop the packet. 1868 */ 1869 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1870 struct mbuf *m0; 1871 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1872 total_len + ETHER_ALIGN, 0, ifp, NULL); 1873 sk_newbuf(sc_if, cur, m, dmamap); 1874 if (m0 == NULL) { 1875 printf("%s: no receive buffers " 1876 "available -- packet dropped!\n", 1877 sc_if->sk_dev.dv_xname); 1878 ifp->if_ierrors++; 1879 continue; 1880 } 1881 m_adj(m0, ETHER_ALIGN); 1882 m = m0; 1883 } else { 1884 m->m_pkthdr.rcvif = ifp; 1885 m->m_pkthdr.len = m->m_len = total_len; 1886 } 1887 1888 ifp->if_ipackets++; 1889 1890 #if NBPFILTER > 0 1891 if (ifp->if_bpf) 1892 bpf_mtap(ifp->if_bpf, m); 1893 #endif 1894 /* pass it on. */ 1895 (*ifp->if_input)(ifp, m); 1896 } 1897 } 1898 1899 void 1900 sk_txeof(struct sk_if_softc *sc_if) 1901 { 1902 struct sk_softc *sc = sc_if->sk_softc; 1903 struct sk_tx_desc *cur_tx; 1904 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1905 u_int32_t idx; 1906 struct sk_txmap_entry *entry; 1907 1908 DPRINTFN(3, ("sk_txeof\n")); 1909 1910 /* 1911 * Go through our tx ring and free mbufs for those 1912 * frames that have been sent. 1913 */ 1914 idx = sc_if->sk_cdata.sk_tx_cons; 1915 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1916 SK_CDTXSYNC(sc_if, idx, 1, 1917 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1918 1919 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1920 #ifdef SK_DEBUG 1921 if (skdebug >= 3) 1922 sk_dump_txdesc(cur_tx, idx); 1923 #endif 1924 if (cur_tx->sk_ctl & SK_TXCTL_OWN) { 1925 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 1926 break; 1927 } 1928 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1929 ifp->if_opackets++; 1930 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1931 entry = sc_if->sk_cdata.sk_tx_map[idx]; 1932 1933 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1934 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1935 1936 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1937 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1938 1939 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1940 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1941 link); 1942 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 1943 } 1944 sc_if->sk_cdata.sk_tx_cnt--; 1945 SK_INC(idx, SK_TX_RING_CNT); 1946 } 1947 if (sc_if->sk_cdata.sk_tx_cnt == 0) 1948 ifp->if_timer = 0; 1949 else /* nudge chip to keep tx ring moving */ 1950 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1951 1952 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 1953 ifp->if_flags &= ~IFF_OACTIVE; 1954 1955 sc_if->sk_cdata.sk_tx_cons = idx; 1956 } 1957 1958 void 1959 sk_tick(void *xsc_if) 1960 { 1961 struct sk_if_softc *sc_if = xsc_if; 1962 struct mii_data *mii = &sc_if->sk_mii; 1963 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1964 int i; 1965 1966 DPRINTFN(3, ("sk_tick\n")); 1967 1968 if (!(ifp->if_flags & IFF_UP)) 1969 return; 1970 1971 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1972 sk_intr_bcom(sc_if); 1973 return; 1974 } 1975 1976 /* 1977 * According to SysKonnect, the correct way to verify that 1978 * the link has come back up is to poll bit 0 of the GPIO 1979 * register three times. This pin has the signal from the 1980 * link sync pin connected to it; if we read the same link 1981 * state 3 times in a row, we know the link is up. 1982 */ 1983 for (i = 0; i < 3; i++) { 1984 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1985 break; 1986 } 1987 1988 if (i != 3) { 1989 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 1990 return; 1991 } 1992 1993 /* Turn the GP0 interrupt back on. */ 1994 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1995 SK_XM_READ_2(sc_if, XM_ISR); 1996 mii_tick(mii); 1997 mii_pollstat(mii); 1998 callout_stop(&sc_if->sk_tick_ch); 1999 } 2000 2001 void 2002 sk_intr_bcom(struct sk_if_softc *sc_if) 2003 { 2004 struct mii_data *mii = &sc_if->sk_mii; 2005 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2006 int status; 2007 2008 2009 DPRINTFN(3, ("sk_intr_bcom\n")); 2010 2011 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2012 2013 /* 2014 * Read the PHY interrupt register to make sure 2015 * we clear any pending interrupts. 2016 */ 2017 status = sk_xmac_miibus_readreg((struct device *)sc_if, 2018 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2019 2020 if (!(ifp->if_flags & IFF_RUNNING)) { 2021 sk_init_xmac(sc_if); 2022 return; 2023 } 2024 2025 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2026 int lstat; 2027 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 2028 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2029 2030 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2031 mii_mediachg(mii); 2032 /* Turn off the link LED. */ 2033 SK_IF_WRITE_1(sc_if, 0, 2034 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2035 sc_if->sk_link = 0; 2036 } else if (status & BRGPHY_ISR_LNK_CHG) { 2037 sk_xmac_miibus_writereg((struct device *)sc_if, 2038 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2039 mii_tick(mii); 2040 sc_if->sk_link = 1; 2041 /* Turn on the link LED. */ 2042 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2043 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2044 SK_LINKLED_BLINK_OFF); 2045 mii_pollstat(mii); 2046 } else { 2047 mii_tick(mii); 2048 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2049 } 2050 } 2051 2052 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2053 } 2054 2055 void 2056 sk_intr_xmac(struct sk_if_softc *sc_if) 2057 { 2058 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2059 2060 DPRINTFN(3, ("sk_intr_xmac\n")); 2061 2062 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2063 if (status & XM_ISR_GP0_SET) { 2064 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2065 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2066 } 2067 2068 if (status & XM_ISR_AUTONEG_DONE) { 2069 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2070 } 2071 } 2072 2073 if (status & XM_IMR_TX_UNDERRUN) 2074 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2075 2076 if (status & XM_IMR_RX_OVERRUN) 2077 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2078 } 2079 2080 void 2081 sk_intr_yukon(sc_if) 2082 struct sk_if_softc *sc_if; 2083 { 2084 int status; 2085 2086 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2087 2088 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2089 } 2090 2091 int 2092 sk_intr(void *xsc) 2093 { 2094 struct sk_softc *sc = xsc; 2095 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2096 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2097 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2098 u_int32_t status; 2099 int claimed = 0; 2100 2101 if (sc_if0 != NULL) 2102 ifp0 = &sc_if0->sk_ethercom.ec_if; 2103 if (sc_if1 != NULL) 2104 ifp1 = &sc_if1->sk_ethercom.ec_if; 2105 2106 for (;;) { 2107 status = CSR_READ_4(sc, SK_ISSR); 2108 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2109 2110 if (!(status & sc->sk_intrmask)) 2111 break; 2112 2113 claimed = 1; 2114 2115 /* Handle receive interrupts first. */ 2116 if (status & SK_ISR_RX1_EOF) { 2117 sk_rxeof(sc_if0); 2118 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2119 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2120 } 2121 if (status & SK_ISR_RX2_EOF) { 2122 sk_rxeof(sc_if1); 2123 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2124 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2125 } 2126 2127 /* Then transmit interrupts. */ 2128 if (status & SK_ISR_TX1_S_EOF) { 2129 sk_txeof(sc_if0); 2130 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2131 SK_TXBMU_CLR_IRQ_EOF); 2132 } 2133 if (status & SK_ISR_TX2_S_EOF) { 2134 sk_txeof(sc_if1); 2135 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2136 SK_TXBMU_CLR_IRQ_EOF); 2137 } 2138 2139 /* Then MAC interrupts. */ 2140 if (status & SK_ISR_MAC1 && (ifp0->if_flags & IFF_RUNNING)) { 2141 if (sc->sk_type == SK_GENESIS) 2142 sk_intr_xmac(sc_if0); 2143 else 2144 sk_intr_yukon(sc_if0); 2145 } 2146 2147 if (status & SK_ISR_MAC2 && (ifp1->if_flags & IFF_RUNNING)) { 2148 if (sc->sk_type == SK_GENESIS) 2149 sk_intr_xmac(sc_if1); 2150 else 2151 sk_intr_yukon(sc_if1); 2152 2153 } 2154 2155 if (status & SK_ISR_EXTERNAL_REG) { 2156 if (ifp0 != NULL && 2157 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2158 sk_intr_bcom(sc_if0); 2159 2160 if (ifp1 != NULL && 2161 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2162 sk_intr_bcom(sc_if1); 2163 } 2164 } 2165 2166 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2167 2168 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2169 sk_start(ifp0); 2170 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2171 sk_start(ifp1); 2172 2173 return (claimed); 2174 } 2175 2176 void 2177 sk_init_xmac(struct sk_if_softc *sc_if) 2178 { 2179 struct sk_softc *sc = sc_if->sk_softc; 2180 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2181 static const struct sk_bcom_hack bhack[] = { 2182 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2183 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2184 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2185 { 0, 0 } }; 2186 2187 DPRINTFN(1, ("sk_init_xmac\n")); 2188 2189 /* Unreset the XMAC. */ 2190 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2191 DELAY(1000); 2192 2193 /* Reset the XMAC's internal state. */ 2194 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2195 2196 /* Save the XMAC II revision */ 2197 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2198 2199 /* 2200 * Perform additional initialization for external PHYs, 2201 * namely for the 1000baseTX cards that use the XMAC's 2202 * GMII mode. 2203 */ 2204 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2205 int i = 0; 2206 u_int32_t val; 2207 2208 /* Take PHY out of reset. */ 2209 val = sk_win_read_4(sc, SK_GPIO); 2210 if (sc_if->sk_port == SK_PORT_A) 2211 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2212 else 2213 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2214 sk_win_write_4(sc, SK_GPIO, val); 2215 2216 /* Enable GMII mode on the XMAC. */ 2217 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2218 2219 sk_xmac_miibus_writereg((struct device *)sc_if, 2220 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2221 DELAY(10000); 2222 sk_xmac_miibus_writereg((struct device *)sc_if, 2223 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2224 2225 /* 2226 * Early versions of the BCM5400 apparently have 2227 * a bug that requires them to have their reserved 2228 * registers initialized to some magic values. I don't 2229 * know what the numbers do, I'm just the messenger. 2230 */ 2231 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2232 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2233 while(bhack[i].reg) { 2234 sk_xmac_miibus_writereg((struct device *)sc_if, 2235 SK_PHYADDR_BCOM, bhack[i].reg, 2236 bhack[i].val); 2237 i++; 2238 } 2239 } 2240 } 2241 2242 /* Set station address */ 2243 SK_XM_WRITE_2(sc_if, XM_PAR0, 2244 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2245 SK_XM_WRITE_2(sc_if, XM_PAR1, 2246 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2247 SK_XM_WRITE_2(sc_if, XM_PAR2, 2248 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2249 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2250 2251 if (ifp->if_flags & IFF_PROMISC) { 2252 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2253 } else { 2254 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2255 } 2256 2257 if (ifp->if_flags & IFF_BROADCAST) { 2258 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2259 } else { 2260 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2261 } 2262 2263 /* We don't need the FCS appended to the packet. */ 2264 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2265 2266 /* We want short frames padded to 60 bytes. */ 2267 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2268 2269 /* 2270 * Enable the reception of all error frames. This is is 2271 * a necessary evil due to the design of the XMAC. The 2272 * XMAC's receive FIFO is only 8K in size, however jumbo 2273 * frames can be up to 9000 bytes in length. When bad 2274 * frame filtering is enabled, the XMAC's RX FIFO operates 2275 * in 'store and forward' mode. For this to work, the 2276 * entire frame has to fit into the FIFO, but that means 2277 * that jumbo frames larger than 8192 bytes will be 2278 * truncated. Disabling all bad frame filtering causes 2279 * the RX FIFO to operate in streaming mode, in which 2280 * case the XMAC will start transfering frames out of the 2281 * RX FIFO as soon as the FIFO threshold is reached. 2282 */ 2283 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2284 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2285 XM_MODE_RX_INRANGELEN); 2286 2287 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2288 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2289 else 2290 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2291 2292 /* 2293 * Bump up the transmit threshold. This helps hold off transmit 2294 * underruns when we're blasting traffic from both ports at once. 2295 */ 2296 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2297 2298 /* Set multicast filter */ 2299 sk_setmulti(sc_if); 2300 2301 /* Clear and enable interrupts */ 2302 SK_XM_READ_2(sc_if, XM_ISR); 2303 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2304 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2305 else 2306 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2307 2308 /* Configure MAC arbiter */ 2309 switch(sc_if->sk_xmac_rev) { 2310 case XM_XMAC_REV_B2: 2311 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2312 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2313 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2314 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2315 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2316 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2317 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2318 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2319 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2320 break; 2321 case XM_XMAC_REV_C1: 2322 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2323 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2324 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2325 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2326 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2327 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2328 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2329 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2330 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2331 break; 2332 default: 2333 break; 2334 } 2335 sk_win_write_2(sc, SK_MACARB_CTL, 2336 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2337 2338 sc_if->sk_link = 1; 2339 } 2340 2341 void sk_init_yukon(sc_if) 2342 struct sk_if_softc *sc_if; 2343 { 2344 u_int32_t /*mac, */phy; 2345 u_int16_t reg; 2346 struct sk_softc *sc; 2347 int i; 2348 2349 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2350 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2351 2352 sc = sc_if->sk_softc; 2353 if (sc->sk_type == SK_YUKON_LITE && 2354 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2355 /* Take PHY out of reset. */ 2356 sk_win_write_4(sc, SK_GPIO, 2357 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2358 } 2359 2360 2361 /* GMAC and GPHY Reset */ 2362 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2363 2364 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2365 2366 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2367 DELAY(1000); 2368 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2369 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2370 DELAY(1000); 2371 2372 2373 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2374 2375 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2376 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2377 2378 switch(sc_if->sk_softc->sk_pmd) { 2379 case IFM_1000_SX: 2380 case IFM_1000_LX: 2381 phy |= SK_GPHY_FIBER; 2382 break; 2383 2384 case IFM_1000_CX: 2385 case IFM_1000_T: 2386 phy |= SK_GPHY_COPPER; 2387 break; 2388 } 2389 2390 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2391 2392 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2393 DELAY(1000); 2394 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2395 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2396 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2397 2398 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2399 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2400 2401 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2402 2403 /* unused read of the interrupt source register */ 2404 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2405 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2406 2407 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2408 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2409 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2410 2411 /* MIB Counter Clear Mode set */ 2412 reg |= YU_PAR_MIB_CLR; 2413 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2414 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2415 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2416 2417 /* MIB Counter Clear Mode clear */ 2418 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2419 reg &= ~YU_PAR_MIB_CLR; 2420 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2421 2422 /* receive control reg */ 2423 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2424 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2425 YU_RCR_CRCR); 2426 2427 /* transmit parameter register */ 2428 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2429 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2430 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2431 2432 /* serial mode register */ 2433 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2434 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2435 YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e)); 2436 2437 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2438 /* Setup Yukon's address */ 2439 for (i = 0; i < 3; i++) { 2440 /* Write Source Address 1 (unicast filter) */ 2441 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2442 sc_if->sk_enaddr[i * 2] | 2443 sc_if->sk_enaddr[i * 2 + 1] << 8); 2444 } 2445 2446 for (i = 0; i < 3; i++) { 2447 reg = sk_win_read_2(sc_if->sk_softc, 2448 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2449 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2450 } 2451 2452 /* Set multicast filter */ 2453 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2454 sk_setmulti(sc_if); 2455 2456 /* enable interrupt mask for counter overflows */ 2457 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2458 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2459 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2460 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2461 2462 /* Configure RX MAC FIFO */ 2463 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2464 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2465 2466 /* Configure TX MAC FIFO */ 2467 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2468 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2469 2470 DPRINTFN(6, ("sk_init_yukon: end\n")); 2471 } 2472 2473 /* 2474 * Note that to properly initialize any part of the GEnesis chip, 2475 * you first have to take it out of reset mode. 2476 */ 2477 int 2478 sk_init(struct ifnet *ifp) 2479 { 2480 struct sk_if_softc *sc_if = ifp->if_softc; 2481 struct sk_softc *sc = sc_if->sk_softc; 2482 struct mii_data *mii = &sc_if->sk_mii; 2483 int s; 2484 2485 DPRINTFN(1, ("sk_init\n")); 2486 2487 s = splnet(); 2488 2489 if (ifp->if_flags & IFF_RUNNING) { 2490 splx(s); 2491 return 0; 2492 } 2493 2494 /* Cancel pending I/O and free all RX/TX buffers. */ 2495 sk_stop(ifp,0); 2496 2497 if (sc->sk_type == SK_GENESIS) { 2498 /* Configure LINK_SYNC LED */ 2499 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2500 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2501 SK_LINKLED_LINKSYNC_ON); 2502 2503 /* Configure RX LED */ 2504 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2505 SK_RXLEDCTL_COUNTER_START); 2506 2507 /* Configure TX LED */ 2508 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2509 SK_TXLEDCTL_COUNTER_START); 2510 } 2511 2512 /* Configure I2C registers */ 2513 2514 /* Configure XMAC(s) */ 2515 switch (sc->sk_type) { 2516 case SK_GENESIS: 2517 sk_init_xmac(sc_if); 2518 break; 2519 case SK_YUKON: 2520 case SK_YUKON_LITE: 2521 case SK_YUKON_LP: 2522 sk_init_yukon(sc_if); 2523 break; 2524 } 2525 mii_mediachg(mii); 2526 2527 if (sc->sk_type == SK_GENESIS) { 2528 /* Configure MAC FIFOs */ 2529 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2530 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2531 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2532 2533 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2534 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2535 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2536 } 2537 2538 /* Configure transmit arbiter(s) */ 2539 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2540 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2541 2542 /* Configure RAMbuffers */ 2543 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2544 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2545 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2546 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2547 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2548 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2549 2550 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2551 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2552 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2553 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2554 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2555 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2556 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2557 2558 /* Configure BMUs */ 2559 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2560 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2561 SK_RX_RING_ADDR(sc_if, 0)); 2562 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2563 2564 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2565 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2566 SK_TX_RING_ADDR(sc_if, 0)); 2567 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2568 2569 /* Init descriptors */ 2570 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2571 printf("%s: initialization failed: no " 2572 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2573 sk_stop(ifp,0); 2574 splx(s); 2575 return(ENOBUFS); 2576 } 2577 2578 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2579 printf("%s: initialization failed: no " 2580 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2581 sk_stop(ifp,0); 2582 splx(s); 2583 return(ENOBUFS); 2584 } 2585 2586 /* Configure interrupt handling */ 2587 CSR_READ_4(sc, SK_ISSR); 2588 if (sc_if->sk_port == SK_PORT_A) 2589 sc->sk_intrmask |= SK_INTRS1; 2590 else 2591 sc->sk_intrmask |= SK_INTRS2; 2592 2593 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2594 2595 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2596 2597 /* Start BMUs. */ 2598 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2599 2600 if (sc->sk_type == SK_GENESIS) { 2601 /* Enable XMACs TX and RX state machines */ 2602 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2603 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2604 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2605 } 2606 2607 if (SK_YUKON_FAMILY(sc->sk_type)) { 2608 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2609 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2610 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2611 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2612 } 2613 2614 2615 ifp->if_flags |= IFF_RUNNING; 2616 ifp->if_flags &= ~IFF_OACTIVE; 2617 2618 splx(s); 2619 return(0); 2620 } 2621 2622 void 2623 sk_stop(struct ifnet *ifp, int disable) 2624 { 2625 struct sk_if_softc *sc_if = ifp->if_softc; 2626 struct sk_softc *sc = sc_if->sk_softc; 2627 int i; 2628 2629 DPRINTFN(1, ("sk_stop\n")); 2630 2631 callout_stop(&sc_if->sk_tick_ch); 2632 2633 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2634 u_int32_t val; 2635 2636 /* Put PHY back into reset. */ 2637 val = sk_win_read_4(sc, SK_GPIO); 2638 if (sc_if->sk_port == SK_PORT_A) { 2639 val |= SK_GPIO_DIR0; 2640 val &= ~SK_GPIO_DAT0; 2641 } else { 2642 val |= SK_GPIO_DIR2; 2643 val &= ~SK_GPIO_DAT2; 2644 } 2645 sk_win_write_4(sc, SK_GPIO, val); 2646 } 2647 2648 /* Turn off various components of this interface. */ 2649 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2650 switch (sc->sk_type) { 2651 case SK_GENESIS: 2652 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2653 SK_TXMACCTL_XMAC_RESET); 2654 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2655 break; 2656 case SK_YUKON: 2657 case SK_YUKON_LITE: 2658 case SK_YUKON_LP: 2659 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2660 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2661 break; 2662 } 2663 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2664 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2665 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2666 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2667 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2668 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2669 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2670 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2671 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2672 2673 /* Disable interrupts */ 2674 if (sc_if->sk_port == SK_PORT_A) 2675 sc->sk_intrmask &= ~SK_INTRS1; 2676 else 2677 sc->sk_intrmask &= ~SK_INTRS2; 2678 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2679 2680 SK_XM_READ_2(sc_if, XM_ISR); 2681 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2682 2683 /* Free RX and TX mbufs still in the queues. */ 2684 for (i = 0; i < SK_RX_RING_CNT; i++) { 2685 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2686 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2687 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2688 } 2689 } 2690 2691 for (i = 0; i < SK_TX_RING_CNT; i++) { 2692 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2693 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2694 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2695 } 2696 } 2697 2698 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2699 } 2700 2701 CFATTACH_DECL(skc,sizeof(struct sk_softc), skc_probe, skc_attach, NULL, NULL); 2702 2703 /* 2704 struct cfdriver skc_cd = { 2705 0, "skc", DV_DULL 2706 }; 2707 */ 2708 2709 CFATTACH_DECL(sk,sizeof(struct sk_if_softc), sk_probe, sk_attach, NULL, NULL); 2710 2711 /* 2712 struct cfdriver sk_cd = { 2713 0, "sk", DV_IFNET 2714 }; 2715 */ 2716 2717 #ifdef SK_DEBUG 2718 void 2719 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2720 { 2721 #define DESC_PRINT(X) \ 2722 if (desc->X) \ 2723 printf("txdesc[%d]." #X "=%#x\n", \ 2724 idx, desc->X); 2725 2726 DESC_PRINT(sk_ctl); 2727 DESC_PRINT(sk_next); 2728 DESC_PRINT(sk_data_lo); 2729 DESC_PRINT(sk_data_hi); 2730 DESC_PRINT(sk_xmac_txstat); 2731 DESC_PRINT(sk_rsvd0); 2732 DESC_PRINT(sk_csum_startval); 2733 DESC_PRINT(sk_csum_startpos); 2734 DESC_PRINT(sk_csum_writepos); 2735 DESC_PRINT(sk_rsvd1); 2736 #undef PRINT 2737 } 2738 2739 void 2740 sk_dump_bytes(const char *data, int len) 2741 { 2742 int c, i, j; 2743 2744 for (i = 0; i < len; i += 16) { 2745 printf("%08x ", i); 2746 c = len - i; 2747 if (c > 16) c = 16; 2748 2749 for (j = 0; j < c; j++) { 2750 printf("%02x ", data[i + j] & 0xff); 2751 if ((j & 0xf) == 7 && j > 0) 2752 printf(" "); 2753 } 2754 2755 for (; j < 16; j++) 2756 printf(" "); 2757 printf(" "); 2758 2759 for (j = 0; j < c; j++) { 2760 int ch = data[i + j] & 0xff; 2761 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2762 } 2763 2764 printf("\n"); 2765 2766 if (c < 16) 2767 break; 2768 } 2769 } 2770 2771 void 2772 sk_dump_mbuf(struct mbuf *m) 2773 { 2774 int count = m->m_pkthdr.len; 2775 2776 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2777 2778 while (count > 0 && m) { 2779 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2780 m, m->m_data, m->m_len); 2781 sk_dump_bytes(mtod(m, char *), m->m_len); 2782 2783 count -= m->m_len; 2784 m = m->m_next; 2785 } 2786 } 2787 #endif 2788
Indexes created Wed Sep 24 05:09:52 GMT 2025