if_sk.c revision 1.19
1 /* $NetBSD: if_sk.c,v 1.19 2006/02/11 13:04:44 rpaulo Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* $OpenBSD: if_sk.c,v 1.33 2003/08/12 05:23:06 nate Exp $ */ 37 38 /* 39 * Copyright (c) 1997, 1998, 1999, 2000 40 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Bill Paul. 53 * 4. Neither the name of the author nor the names of any co-contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 67 * THE POSSIBILITY OF SUCH DAMAGE. 68 * 69 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 70 */ 71 72 /* 73 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 74 * 75 * Permission to use, copy, modify, and distribute this software for any 76 * purpose with or without fee is hereby granted, provided that the above 77 * copyright notice and this permission notice appear in all copies. 78 * 79 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 80 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 81 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 82 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 83 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 84 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 85 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 86 */ 87 88 /* 89 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 90 * the SK-984x series adapters, both single port and dual port. 91 * References: 92 * The XaQti XMAC II datasheet, 93 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * The SysKonnect GEnesis manual, http://www.syskonnect.com 95 * 96 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 97 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 98 * convenience to others until Vitesse corrects this problem: 99 * 100 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 101 * 102 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 103 * Department of Electrical Engineering 104 * Columbia University, New York City 105 */ 106 107 /* 108 * The SysKonnect gigabit ethernet adapters consist of two main 109 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 110 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 111 * components and a PHY while the GEnesis controller provides a PCI 112 * interface with DMA support. Each card may have between 512K and 113 * 2MB of SRAM on board depending on the configuration. 114 * 115 * The SysKonnect GEnesis controller can have either one or two XMAC 116 * chips connected to it, allowing single or dual port NIC configurations. 117 * SysKonnect has the distinction of being the only vendor on the market 118 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 119 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 120 * XMAC registers. This driver takes advantage of these features to allow 121 * both XMACs to operate as independent interfaces. 122 */ 123 124 #include "bpfilter.h" 125 #include "rnd.h" 126 127 #include <sys/param.h> 128 #include <sys/systm.h> 129 #include <sys/sockio.h> 130 #include <sys/mbuf.h> 131 #include <sys/malloc.h> 132 #include <sys/kernel.h> 133 #include <sys/socket.h> 134 #include <sys/device.h> 135 #include <sys/queue.h> 136 #include <sys/callout.h> 137 138 #include <net/if.h> 139 #include <net/if_dl.h> 140 #include <net/if_types.h> 141 142 #ifdef INET 143 #include <netinet/in.h> 144 #include <netinet/in_systm.h> 145 #include <netinet/in_var.h> 146 #include <netinet/ip.h> 147 #include <netinet/if_ether.h> 148 #endif 149 150 #include <net/if_media.h> 151 152 #if NBPFILTER > 0 153 #include <net/bpf.h> 154 #endif 155 #if NRND > 0 156 #include <sys/rnd.h> 157 #endif 158 159 #include <dev/mii/mii.h> 160 #include <dev/mii/miivar.h> 161 #include <dev/mii/brgphyreg.h> 162 163 #include <dev/pci/pcireg.h> 164 #include <dev/pci/pcivar.h> 165 #include <dev/pci/pcidevs.h> 166 167 #define SK_VERBOSE 168 /* #define SK_USEIOSPACE */ 169 170 #include <dev/pci/if_skreg.h> 171 #include <dev/pci/if_skvar.h> 172 173 int skc_probe(struct device *, struct cfdata *, void *); 174 void skc_attach(struct device *, struct device *self, void *aux); 175 int sk_probe(struct device *, struct cfdata *, void *); 176 void sk_attach(struct device *, struct device *self, void *aux); 177 int skcprint(void *, const char *); 178 int sk_intr(void *); 179 void sk_intr_bcom(struct sk_if_softc *); 180 void sk_intr_xmac(struct sk_if_softc *); 181 void sk_intr_yukon(struct sk_if_softc *); 182 void sk_rxeof(struct sk_if_softc *); 183 void sk_txeof(struct sk_if_softc *); 184 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 185 void sk_start(struct ifnet *); 186 int sk_ioctl(struct ifnet *, u_long, caddr_t); 187 int sk_init(struct ifnet *); 188 void sk_init_xmac(struct sk_if_softc *); 189 void sk_init_yukon(struct sk_if_softc *); 190 void sk_stop(struct ifnet *, int); 191 void sk_watchdog(struct ifnet *); 192 void sk_shutdown(void *); 193 int sk_ifmedia_upd(struct ifnet *); 194 void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 195 void sk_reset(struct sk_softc *); 196 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 197 int sk_init_rx_ring(struct sk_if_softc *); 198 int sk_init_tx_ring(struct sk_if_softc *); 199 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 200 void sk_vpd_read_res(struct sk_softc *, 201 struct vpd_res *, int); 202 void sk_vpd_read(struct sk_softc *); 203 204 int sk_xmac_miibus_readreg(struct device *, int, int); 205 void sk_xmac_miibus_writereg(struct device *, int, int, int); 206 void sk_xmac_miibus_statchg(struct device *); 207 208 int sk_marv_miibus_readreg(struct device *, int, int); 209 void sk_marv_miibus_writereg(struct device *, int, int, int); 210 void sk_marv_miibus_statchg(struct device *); 211 212 u_int32_t sk_xmac_hash(caddr_t); 213 u_int32_t sk_yukon_hash(caddr_t); 214 void sk_setfilt(struct sk_if_softc *, caddr_t, int); 215 void sk_setmulti(struct sk_if_softc *); 216 void sk_tick(void *); 217 218 /* #define SK_DEBUG 2 */ 219 #ifdef SK_DEBUG 220 #define DPRINTF(x) if (skdebug) printf x 221 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 222 int skdebug = SK_DEBUG; 223 224 void sk_dump_txdesc(struct sk_tx_desc *, int); 225 void sk_dump_mbuf(struct mbuf *); 226 void sk_dump_bytes(const char *, int); 227 #else 228 #define DPRINTF(x) 229 #define DPRINTFN(n,x) 230 #endif 231 232 #define SK_SETBIT(sc, reg, x) \ 233 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 234 235 #define SK_CLRBIT(sc, reg, x) \ 236 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 237 238 #define SK_WIN_SETBIT_4(sc, reg, x) \ 239 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 240 241 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 242 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 243 244 #define SK_WIN_SETBIT_2(sc, reg, x) \ 245 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 246 247 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 248 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 249 250 /* supported device vendors */ 251 static const struct sk_product { 252 pci_vendor_id_t sk_vendor; 253 pci_product_id_t sk_product; 254 } sk_products[] = { 255 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 256 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 257 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 258 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 259 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 260 { PCI_VENDOR_GALILEO, PCI_PRODUCT_GALILEO_SKNET, }, 261 { PCI_VENDOR_GALILEO, PCI_PRODUCT_GALILEO_BELKIN, }, 262 { 0, 0, } 263 }; 264 265 #define SK_LINKSYS_EG1032_SUBID 0x00151737 266 267 static inline u_int32_t 268 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 269 { 270 #ifdef SK_USEIOSPACE 271 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 272 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 273 #else 274 return CSR_READ_4(sc, reg); 275 #endif 276 } 277 278 static inline u_int16_t 279 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 280 { 281 #ifdef SK_USEIOSPACE 282 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 283 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 284 #else 285 return CSR_READ_2(sc, reg); 286 #endif 287 } 288 289 static inline u_int8_t 290 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 291 { 292 #ifdef SK_USEIOSPACE 293 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 294 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 295 #else 296 return CSR_READ_1(sc, reg); 297 #endif 298 } 299 300 static inline void 301 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 302 { 303 #ifdef SK_USEIOSPACE 304 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 305 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 306 #else 307 CSR_WRITE_4(sc, reg, x); 308 #endif 309 } 310 311 static inline void 312 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 313 { 314 #ifdef SK_USEIOSPACE 315 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 316 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 317 #else 318 CSR_WRITE_2(sc, reg, x); 319 #endif 320 } 321 322 static inline void 323 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 324 { 325 #ifdef SK_USEIOSPACE 326 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 327 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 328 #else 329 CSR_WRITE_1(sc, reg, x); 330 #endif 331 } 332 333 /* 334 * The VPD EEPROM contains Vital Product Data, as suggested in 335 * the PCI 2.1 specification. The VPD data is separared into areas 336 * denoted by resource IDs. The SysKonnect VPD contains an ID string 337 * resource (the name of the adapter), a read-only area resource 338 * containing various key/data fields and a read/write area which 339 * can be used to store asset management information or log messages. 340 * We read the ID string and read-only into buffers attached to 341 * the controller softc structure for later use. At the moment, 342 * we only use the ID string during sk_attach(). 343 */ 344 u_int8_t 345 sk_vpd_readbyte(struct sk_softc *sc, int addr) 346 { 347 int i; 348 349 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 350 for (i = 0; i < SK_TIMEOUT; i++) { 351 DELAY(1); 352 if (sk_win_read_2(sc, 353 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 354 break; 355 } 356 357 if (i == SK_TIMEOUT) 358 return(0); 359 360 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 361 } 362 363 void 364 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 365 { 366 int i; 367 u_int8_t *ptr; 368 369 ptr = (u_int8_t *)res; 370 for (i = 0; i < sizeof(struct vpd_res); i++) 371 ptr[i] = sk_vpd_readbyte(sc, i + addr); 372 } 373 374 void 375 sk_vpd_read(struct sk_softc *sc) 376 { 377 int pos = 0, i; 378 struct vpd_res res; 379 380 if (sc->sk_vpd_prodname != NULL) 381 free(sc->sk_vpd_prodname, M_DEVBUF); 382 if (sc->sk_vpd_readonly != NULL) 383 free(sc->sk_vpd_readonly, M_DEVBUF); 384 sc->sk_vpd_prodname = NULL; 385 sc->sk_vpd_readonly = NULL; 386 387 sk_vpd_read_res(sc, &res, pos); 388 389 if (res.vr_id != VPD_RES_ID) { 390 printf("%s: bad VPD resource id: expected %x got %x\n", 391 sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 392 return; 393 } 394 395 pos += sizeof(res); 396 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 397 if (sc->sk_vpd_prodname == NULL) 398 panic("sk_vpd_read"); 399 for (i = 0; i < res.vr_len; i++) 400 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 401 sc->sk_vpd_prodname[i] = '\0'; 402 pos += i; 403 404 sk_vpd_read_res(sc, &res, pos); 405 406 if (res.vr_id != VPD_RES_READ) { 407 printf("%s: bad VPD resource id: expected %x got %x\n", 408 sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 409 return; 410 } 411 412 pos += sizeof(res); 413 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 414 if (sc->sk_vpd_readonly == NULL) 415 panic("sk_vpd_read"); 416 for (i = 0; i < res.vr_len ; i++) 417 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 418 } 419 420 int 421 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 422 { 423 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 424 int i; 425 426 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 427 428 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 429 return(0); 430 431 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 432 SK_XM_READ_2(sc_if, XM_PHY_DATA); 433 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 434 for (i = 0; i < SK_TIMEOUT; i++) { 435 DELAY(1); 436 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 437 XM_MMUCMD_PHYDATARDY) 438 break; 439 } 440 441 if (i == SK_TIMEOUT) { 442 printf("%s: phy failed to come ready\n", 443 sc_if->sk_dev.dv_xname); 444 return(0); 445 } 446 } 447 DELAY(1); 448 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 449 } 450 451 void 452 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 453 { 454 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 455 int i; 456 457 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 458 459 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 460 for (i = 0; i < SK_TIMEOUT; i++) { 461 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 462 break; 463 } 464 465 if (i == SK_TIMEOUT) { 466 printf("%s: phy failed to come ready\n", 467 sc_if->sk_dev.dv_xname); 468 return; 469 } 470 471 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 472 for (i = 0; i < SK_TIMEOUT; i++) { 473 DELAY(1); 474 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 475 break; 476 } 477 478 if (i == SK_TIMEOUT) 479 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 480 } 481 482 void 483 sk_xmac_miibus_statchg(struct device *dev) 484 { 485 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 486 struct mii_data *mii = &sc_if->sk_mii; 487 488 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 489 490 /* 491 * If this is a GMII PHY, manually set the XMAC's 492 * duplex mode accordingly. 493 */ 494 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 495 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 496 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 497 } else { 498 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 499 } 500 } 501 } 502 503 int 504 sk_marv_miibus_readreg(dev, phy, reg) 505 struct device *dev; 506 int phy, reg; 507 { 508 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 509 u_int16_t val; 510 int i; 511 512 if (phy != 0 || 513 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 514 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 515 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 516 phy, reg)); 517 return(0); 518 } 519 520 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 521 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 522 523 for (i = 0; i < SK_TIMEOUT; i++) { 524 DELAY(1); 525 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 526 if (val & YU_SMICR_READ_VALID) 527 break; 528 } 529 530 if (i == SK_TIMEOUT) { 531 printf("%s: phy failed to come ready\n", 532 sc_if->sk_dev.dv_xname); 533 return 0; 534 } 535 536 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 537 SK_TIMEOUT)); 538 539 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 540 541 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 542 phy, reg, val)); 543 544 return val; 545 } 546 547 void 548 sk_marv_miibus_writereg(dev, phy, reg, val) 549 struct device *dev; 550 int phy, reg, val; 551 { 552 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 553 int i; 554 555 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 556 phy, reg, val)); 557 558 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 559 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 560 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 561 562 for (i = 0; i < SK_TIMEOUT; i++) { 563 DELAY(1); 564 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 565 break; 566 } 567 } 568 569 void 570 sk_marv_miibus_statchg(dev) 571 struct device *dev; 572 { 573 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 574 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 575 } 576 577 #define SK_HASH_BITS 6 578 579 u_int32_t 580 sk_xmac_hash(caddr_t addr) 581 { 582 u_int32_t crc; 583 584 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 585 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 586 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 587 return (crc); 588 } 589 590 u_int32_t 591 sk_yukon_hash(caddr_t addr) 592 { 593 u_int32_t crc; 594 595 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 596 crc &= ((1 << SK_HASH_BITS) - 1); 597 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 598 return (crc); 599 } 600 601 void 602 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 603 { 604 int base = XM_RXFILT_ENTRY(slot); 605 606 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 607 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 608 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 609 } 610 611 void 612 sk_setmulti(struct sk_if_softc *sc_if) 613 { 614 struct sk_softc *sc = sc_if->sk_softc; 615 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 616 u_int32_t hashes[2] = { 0, 0 }; 617 int h = 0, i; 618 struct ethercom *ec = &sc_if->sk_ethercom; 619 struct ether_multi *enm; 620 struct ether_multistep step; 621 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 622 623 /* First, zot all the existing filters. */ 624 switch(sc->sk_type) { 625 case SK_GENESIS: 626 for (i = 1; i < XM_RXFILT_MAX; i++) 627 sk_setfilt(sc_if, (caddr_t)&dummy, i); 628 629 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 630 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 631 break; 632 case SK_YUKON: 633 case SK_YUKON_LITE: 634 case SK_YUKON_LP: 635 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 636 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 637 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 638 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 639 break; 640 } 641 642 /* Now program new ones. */ 643 allmulti: 644 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 645 hashes[0] = 0xFFFFFFFF; 646 hashes[1] = 0xFFFFFFFF; 647 } else { 648 i = 1; 649 /* First find the tail of the list. */ 650 ETHER_FIRST_MULTI(step, ec, enm); 651 while (enm != NULL) { 652 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 653 ETHER_ADDR_LEN)) { 654 ifp->if_flags |= IFF_ALLMULTI; 655 goto allmulti; 656 } 657 DPRINTFN(2,("multicast address %s\n", 658 ether_sprintf(enm->enm_addrlo))); 659 /* 660 * Program the first XM_RXFILT_MAX multicast groups 661 * into the perfect filter. For all others, 662 * use the hash table. 663 */ 664 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 665 sk_setfilt(sc_if, enm->enm_addrlo, i); 666 i++; 667 } 668 else { 669 switch (sc->sk_type) { 670 case SK_GENESIS: 671 h = sk_xmac_hash(enm->enm_addrlo); 672 break; 673 case SK_YUKON: 674 case SK_YUKON_LITE: 675 case SK_YUKON_LP: 676 h = sk_yukon_hash(enm->enm_addrlo); 677 break; 678 } 679 if (h < 32) 680 hashes[0] |= (1 << h); 681 else 682 hashes[1] |= (1 << (h - 32)); 683 } 684 685 ETHER_NEXT_MULTI(step, enm); 686 } 687 } 688 689 switch(sc->sk_type) { 690 case SK_GENESIS: 691 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 692 XM_MODE_RX_USE_PERFECT); 693 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 694 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 695 break; 696 case SK_YUKON: 697 case SK_YUKON_LITE: 698 case SK_YUKON_LP: 699 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 700 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 701 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 702 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 703 break; 704 } 705 } 706 707 int 708 sk_init_rx_ring(struct sk_if_softc *sc_if) 709 { 710 struct sk_chain_data *cd = &sc_if->sk_cdata; 711 struct sk_ring_data *rd = sc_if->sk_rdata; 712 int i; 713 714 bzero((char *)rd->sk_rx_ring, 715 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 716 717 for (i = 0; i < SK_RX_RING_CNT; i++) { 718 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 719 if (i == (SK_RX_RING_CNT - 1)) { 720 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 721 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if, 0); 722 } else { 723 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 724 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if,i+1); 725 } 726 } 727 728 for (i = 0; i < SK_RX_RING_CNT; i++) { 729 if (sk_newbuf(sc_if, i, NULL, NULL) == ENOBUFS) { 730 printf("%s: failed alloc of %dth mbuf\n", 731 sc_if->sk_dev.dv_xname, i); 732 return(ENOBUFS); 733 } 734 } 735 sc_if->sk_cdata.sk_rx_prod = 0; 736 sc_if->sk_cdata.sk_rx_cons = 0; 737 738 return(0); 739 } 740 741 int 742 sk_init_tx_ring(struct sk_if_softc *sc_if) 743 { 744 struct sk_chain_data *cd = &sc_if->sk_cdata; 745 struct sk_ring_data *rd = sc_if->sk_rdata; 746 int i; 747 748 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 749 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 750 751 for (i = 0; i < SK_TX_RING_CNT; i++) { 752 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 753 if (i == (SK_TX_RING_CNT - 1)) { 754 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 755 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if, 0); 756 } else { 757 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 758 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if,i+1); 759 } 760 } 761 762 sc_if->sk_cdata.sk_tx_prod = 0; 763 sc_if->sk_cdata.sk_tx_cons = 0; 764 sc_if->sk_cdata.sk_tx_cnt = 0; 765 766 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 767 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 768 769 return (0); 770 } 771 772 int 773 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 774 bus_dmamap_t dmamap) 775 { 776 struct sk_softc *sc = sc_if->sk_softc; 777 struct mbuf *m_new = NULL; 778 struct sk_chain *c; 779 struct sk_rx_desc *r; 780 781 if (dmamap == NULL) { 782 /* if (m) panic() */ 783 784 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, MCLBYTES, 785 0, BUS_DMA_NOWAIT, &dmamap)) { 786 printf("%s: can't create recv map\n", 787 sc_if->sk_dev.dv_xname); 788 return(ENOMEM); 789 } 790 } else if (m == NULL) 791 bus_dmamap_unload(sc->sc_dmatag, dmamap); 792 793 sc_if->sk_cdata.sk_rx_map[i] = dmamap; 794 795 if (m == NULL) { 796 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 797 if (m_new == NULL) { 798 printf("%s: no memory for rx list -- " 799 "packet dropped!\n", sc_if->sk_dev.dv_xname); 800 return(ENOBUFS); 801 } 802 803 /* Allocate the jumbo buffer */ 804 MCLGET(m_new, M_DONTWAIT); 805 if (!(m_new->m_flags & M_EXT)) { 806 m_freem(m_new); 807 return (ENOBUFS); 808 } 809 810 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 811 812 m_adj(m_new, ETHER_ALIGN); 813 814 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m_new, 815 BUS_DMA_NOWAIT)) 816 return(ENOBUFS); 817 } else { 818 /* 819 * We're re-using a previously allocated mbuf; 820 * be sure to re-init pointers and lengths to 821 * default values. 822 */ 823 m_new = m; 824 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 825 m_adj(m_new, ETHER_ALIGN); 826 m_new->m_data = m_new->m_ext.ext_buf; 827 } 828 829 c = &sc_if->sk_cdata.sk_rx_chain[i]; 830 r = c->sk_desc; 831 c->sk_mbuf = m_new; 832 r->sk_data_lo = dmamap->dm_segs[0].ds_addr; 833 r->sk_ctl = dmamap->dm_segs[0].ds_len | SK_RXSTAT; 834 835 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 836 837 return(0); 838 } 839 840 /* 841 * Set media options. 842 */ 843 int 844 sk_ifmedia_upd(struct ifnet *ifp) 845 { 846 struct sk_if_softc *sc_if = ifp->if_softc; 847 848 (void) sk_init(ifp); 849 mii_mediachg(&sc_if->sk_mii); 850 return(0); 851 } 852 853 /* 854 * Report current media status. 855 */ 856 void 857 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 858 { 859 struct sk_if_softc *sc_if = ifp->if_softc; 860 861 mii_pollstat(&sc_if->sk_mii); 862 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 863 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 864 } 865 866 int 867 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 868 { 869 struct sk_if_softc *sc_if = ifp->if_softc; 870 struct sk_softc *sc = sc_if->sk_softc; 871 struct ifreq *ifr = (struct ifreq *) data; 872 /* struct ifaddr *ifa = (struct ifaddr *) data; */ 873 struct mii_data *mii; 874 int s, error = 0; 875 876 /* DPRINTFN(2, ("sk_ioctl\n")); */ 877 878 s = splnet(); 879 880 switch(command) { 881 882 case SIOCSIFFLAGS: 883 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 884 if (ifp->if_flags & IFF_UP) { 885 if (ifp->if_flags & IFF_RUNNING && 886 ifp->if_flags & IFF_PROMISC && 887 !(sc_if->sk_if_flags & IFF_PROMISC)) { 888 switch(sc->sk_type) { 889 case SK_GENESIS: 890 SK_XM_SETBIT_4(sc_if, XM_MODE, 891 XM_MODE_RX_PROMISC); 892 break; 893 case SK_YUKON: 894 case SK_YUKON_LITE: 895 case SK_YUKON_LP: 896 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 897 YU_RCR_UFLEN | YU_RCR_MUFLEN); 898 break; 899 } 900 sk_setmulti(sc_if); 901 } else if (ifp->if_flags & IFF_RUNNING && 902 !(ifp->if_flags & IFF_PROMISC) && 903 sc_if->sk_if_flags & IFF_PROMISC) { 904 switch(sc->sk_type) { 905 case SK_GENESIS: 906 SK_XM_CLRBIT_4(sc_if, XM_MODE, 907 XM_MODE_RX_PROMISC); 908 break; 909 case SK_YUKON: 910 case SK_YUKON_LITE: 911 case SK_YUKON_LP: 912 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 913 YU_RCR_UFLEN | YU_RCR_MUFLEN); 914 break; 915 } 916 917 sk_setmulti(sc_if); 918 } else 919 (void) sk_init(ifp); 920 } else { 921 if (ifp->if_flags & IFF_RUNNING) 922 sk_stop(ifp,0); 923 } 924 sc_if->sk_if_flags = ifp->if_flags; 925 error = 0; 926 break; 927 928 case SIOCGIFMEDIA: 929 case SIOCSIFMEDIA: 930 DPRINTFN(2, ("sk_ioctl MEDIA\n")); 931 mii = &sc_if->sk_mii; 932 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 933 break; 934 default: 935 DPRINTFN(2, ("sk_ioctl ETHER\n")); 936 error = ether_ioctl(ifp, command, data); 937 938 if ( error == ENETRESET) { 939 if (ifp->if_flags & IFF_RUNNING) { 940 sk_setmulti(sc_if); 941 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 942 } 943 error = 0; 944 } else if ( error ) { 945 splx(s); 946 return error; 947 } 948 break; 949 } 950 951 splx(s); 952 return(error); 953 } 954 955 /* 956 * Lookup: Check the PCI vendor and device, and return a pointer to 957 * The structure if the IDs match against our list. 958 */ 959 960 static const struct sk_product * 961 sk_lookup(const struct pci_attach_args *pa) 962 { 963 const struct sk_product *psk; 964 965 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 966 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 967 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 968 return (psk); 969 } 970 return (NULL); 971 } 972 973 /* 974 * Probe for a SysKonnect GEnesis chip. 975 */ 976 977 int 978 skc_probe(struct device *parent, struct cfdata *match, void *aux) 979 { 980 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 981 const struct sk_product *psk; 982 pcireg_t subid; 983 984 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 985 986 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 987 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 988 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 989 subid == SK_LINKSYS_EG1032_SUBID) 990 return(1); 991 992 if ((psk = sk_lookup(pa))) { 993 return(1); 994 } 995 return(0); 996 } 997 998 /* 999 * Force the GEnesis into reset, then bring it out of reset. 1000 */ 1001 void sk_reset(struct sk_softc *sc) 1002 { 1003 DPRINTFN(2, ("sk_reset\n")); 1004 1005 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1006 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1007 if (SK_YUKON_FAMILY(sc->sk_type)) 1008 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1009 1010 DELAY(1000); 1011 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1012 DELAY(2); 1013 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1014 if (SK_YUKON_FAMILY(sc->sk_type)) 1015 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1016 1017 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1018 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1019 CSR_READ_2(sc, SK_LINK_CTRL))); 1020 1021 if (sc->sk_type == SK_GENESIS) { 1022 /* Configure packet arbiter */ 1023 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1024 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1025 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1026 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1027 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1028 } 1029 1030 /* Enable RAM interface */ 1031 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1032 1033 /* 1034 * Configure interrupt moderation. The moderation timer 1035 * defers interrupts specified in the interrupt moderation 1036 * timer mask based on the timeout specified in the interrupt 1037 * moderation timer init register. Each bit in the timer 1038 * register represents 18.825ns, so to specify a timeout in 1039 * microseconds, we have to multiply by 54. 1040 */ 1041 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(100)); 1042 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1043 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1044 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1045 } 1046 1047 int 1048 sk_probe(struct device *parent, struct cfdata *match, void *aux) 1049 { 1050 struct skc_attach_args *sa = aux; 1051 1052 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1053 return(0); 1054 1055 return (1); 1056 } 1057 1058 /* 1059 * Each XMAC chip is attached as a separate logical IP interface. 1060 * Single port cards will have only one logical interface of course. 1061 */ 1062 void 1063 sk_attach(struct device *parent, struct device *self, void *aux) 1064 { 1065 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1066 struct sk_softc *sc = (struct sk_softc *)parent; 1067 struct skc_attach_args *sa = aux; 1068 struct sk_txmap_entry *entry; 1069 struct ifnet *ifp; 1070 bus_dma_segment_t seg; 1071 bus_dmamap_t dmamap; 1072 caddr_t kva; 1073 int i, rseg; 1074 1075 sc_if->sk_port = sa->skc_port; 1076 sc_if->sk_softc = sc; 1077 sc->sk_if[sa->skc_port] = sc_if; 1078 1079 if (sa->skc_port == SK_PORT_A) 1080 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1081 if (sa->skc_port == SK_PORT_B) 1082 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1083 1084 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1085 1086 /* 1087 * Get station address for this interface. Note that 1088 * dual port cards actually come with three station 1089 * addresses: one for each port, plus an extra. The 1090 * extra one is used by the SysKonnect driver software 1091 * as a 'virtual' station address for when both ports 1092 * are operating in failover mode. Currently we don't 1093 * use this extra address. 1094 */ 1095 for (i = 0; i < ETHER_ADDR_LEN; i++) 1096 sc_if->sk_enaddr[i] = 1097 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1098 1099 1100 aprint_normal(": Ethernet address %s\n", 1101 ether_sprintf(sc_if->sk_enaddr)); 1102 1103 /* 1104 * Set up RAM buffer addresses. The NIC will have a certain 1105 * amount of SRAM on it, somewhere between 512K and 2MB. We 1106 * need to divide this up a) between the transmitter and 1107 * receiver and b) between the two XMACs, if this is a 1108 * dual port NIC. Our algotithm is to divide up the memory 1109 * evenly so that everyone gets a fair share. 1110 */ 1111 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1112 u_int32_t chunk, val; 1113 1114 chunk = sc->sk_ramsize / 2; 1115 val = sc->sk_rboff / sizeof(u_int64_t); 1116 sc_if->sk_rx_ramstart = val; 1117 val += (chunk / sizeof(u_int64_t)); 1118 sc_if->sk_rx_ramend = val - 1; 1119 sc_if->sk_tx_ramstart = val; 1120 val += (chunk / sizeof(u_int64_t)); 1121 sc_if->sk_tx_ramend = val - 1; 1122 } else { 1123 u_int32_t chunk, val; 1124 1125 chunk = sc->sk_ramsize / 4; 1126 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1127 sizeof(u_int64_t); 1128 sc_if->sk_rx_ramstart = val; 1129 val += (chunk / sizeof(u_int64_t)); 1130 sc_if->sk_rx_ramend = val - 1; 1131 sc_if->sk_tx_ramstart = val; 1132 val += (chunk / sizeof(u_int64_t)); 1133 sc_if->sk_tx_ramend = val - 1; 1134 } 1135 1136 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1137 " tx_ramstart=%#x tx_ramend=%#x\n", 1138 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1139 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1140 1141 /* Read and save PHY type and set PHY address */ 1142 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1143 switch (sc_if->sk_phytype) { 1144 case SK_PHYTYPE_XMAC: 1145 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1146 break; 1147 case SK_PHYTYPE_BCOM: 1148 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1149 break; 1150 case SK_PHYTYPE_MARV_COPPER: 1151 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1152 break; 1153 default: 1154 aprint_error("%s: unsupported PHY type: %d\n", 1155 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1156 return; 1157 } 1158 1159 /* Allocate the descriptor queues. */ 1160 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1161 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1162 aprint_error("%s: can't alloc rx buffers\n", 1163 sc->sk_dev.dv_xname); 1164 goto fail; 1165 } 1166 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1167 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1168 aprint_error("%s: can't map dma buffers (%lu bytes)\n", 1169 sc_if->sk_dev.dv_xname, 1170 (u_long) sizeof(struct sk_ring_data)); 1171 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1172 goto fail; 1173 } 1174 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1175 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1176 &sc_if->sk_ring_map)) { 1177 aprint_error("%s: can't create dma map\n", 1178 sc_if->sk_dev.dv_xname); 1179 bus_dmamem_unmap(sc->sc_dmatag, kva, 1180 sizeof(struct sk_ring_data)); 1181 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1182 goto fail; 1183 } 1184 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1185 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1186 aprint_error("%s: can't load dma map\n", 1187 sc_if->sk_dev.dv_xname); 1188 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1189 bus_dmamem_unmap(sc->sc_dmatag, kva, 1190 sizeof(struct sk_ring_data)); 1191 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1192 goto fail; 1193 } 1194 1195 for (i = 0; i < SK_RX_RING_CNT; i++) 1196 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1197 1198 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1199 for (i = 0; i < SK_TX_RING_CNT; i++) { 1200 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1201 1202 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, SK_NTXSEG, 1203 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap)) { 1204 aprint_error("%s: Can't create TX dmamap\n", 1205 sc_if->sk_dev.dv_xname); 1206 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1207 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1208 bus_dmamem_unmap(sc->sc_dmatag, kva, 1209 sizeof(struct sk_ring_data)); 1210 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1211 goto fail; 1212 } 1213 1214 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1215 if (!entry) { 1216 aprint_error("%s: Can't alloc txmap entry\n", 1217 sc_if->sk_dev.dv_xname); 1218 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1219 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1220 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1221 bus_dmamem_unmap(sc->sc_dmatag, kva, 1222 sizeof(struct sk_ring_data)); 1223 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1224 goto fail; 1225 } 1226 entry->dmamap = dmamap; 1227 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1228 } 1229 1230 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1231 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1232 1233 /* XXX TLS It's not clear what's wrong with the Jumbo MTU 1234 XXX TLS support in this driver, so we don't enable it. */ 1235 1236 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1237 1238 ifp = &sc_if->sk_ethercom.ec_if; 1239 ifp->if_softc = sc_if; 1240 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1241 ifp->if_ioctl = sk_ioctl; 1242 ifp->if_start = sk_start; 1243 ifp->if_stop = sk_stop; 1244 ifp->if_init = sk_init; 1245 ifp->if_watchdog = sk_watchdog; 1246 ifp->if_capabilities = 0; 1247 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1248 IFQ_SET_READY(&ifp->if_snd); 1249 strcpy(ifp->if_xname, sc_if->sk_dev.dv_xname); 1250 1251 /* 1252 * Do miibus setup. 1253 */ 1254 switch (sc->sk_type) { 1255 case SK_GENESIS: 1256 sk_init_xmac(sc_if); 1257 break; 1258 case SK_YUKON: 1259 case SK_YUKON_LITE: 1260 case SK_YUKON_LP: 1261 sk_init_yukon(sc_if); 1262 break; 1263 default: 1264 panic("%s: unknown device type %d", sc->sk_dev.dv_xname, 1265 sc->sk_type); 1266 } 1267 1268 DPRINTFN(2, ("sk_attach: 1\n")); 1269 1270 sc_if->sk_mii.mii_ifp = ifp; 1271 switch (sc->sk_type) { 1272 case SK_GENESIS: 1273 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1274 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1275 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1276 break; 1277 case SK_YUKON: 1278 case SK_YUKON_LITE: 1279 case SK_YUKON_LP: 1280 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1281 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1282 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1283 break; 1284 } 1285 1286 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1287 sk_ifmedia_upd, sk_ifmedia_sts); 1288 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1289 MII_OFFSET_ANY, 0); 1290 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1291 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1292 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1293 0, NULL); 1294 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1295 } 1296 else 1297 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1298 1299 callout_init(&sc_if->sk_tick_ch); 1300 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1301 1302 DPRINTFN(2, ("sk_attach: 1\n")); 1303 1304 /* 1305 * Call MI attach routines. 1306 */ 1307 if_attach(ifp); 1308 1309 ether_ifattach(ifp, sc_if->sk_enaddr); 1310 1311 #if NRND > 0 1312 rnd_attach_source(&sc->rnd_source, sc->sk_dev.dv_xname, 1313 RND_TYPE_NET, 0); 1314 #endif 1315 1316 DPRINTFN(2, ("sk_attach: end\n")); 1317 1318 return; 1319 1320 fail: 1321 sc->sk_if[sa->skc_port] = NULL; 1322 } 1323 1324 int 1325 skcprint(void *aux, const char *pnp) 1326 { 1327 struct skc_attach_args *sa = aux; 1328 1329 if (pnp) 1330 aprint_normal("sk port %c at %s", 1331 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1332 else 1333 aprint_normal(" port %c", 1334 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1335 return (UNCONF); 1336 } 1337 1338 /* 1339 * Attach the interface. Allocate softc structures, do ifmedia 1340 * setup and ethernet/BPF attach. 1341 */ 1342 void 1343 skc_attach(struct device *parent, struct device *self, void *aux) 1344 { 1345 struct sk_softc *sc = (struct sk_softc *)self; 1346 struct pci_attach_args *pa = aux; 1347 struct skc_attach_args skca; 1348 pci_chipset_tag_t pc = pa->pa_pc; 1349 pcireg_t memtype; 1350 pci_intr_handle_t ih; 1351 const char *intrstr = NULL; 1352 bus_addr_t iobase; 1353 bus_size_t iosize; 1354 int s; 1355 u_int32_t command; 1356 const char *revstr; 1357 1358 DPRINTFN(2, ("begin skc_attach\n")); 1359 1360 s = splnet(); 1361 1362 /* 1363 * Handle power management nonsense. 1364 */ 1365 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1366 1367 if (command == 0x01) { 1368 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1369 if (command & SK_PSTATE_MASK) { 1370 u_int32_t xiobase, membase, irq; 1371 1372 /* Save important PCI config data. */ 1373 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1374 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1375 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1376 1377 /* Reset the power state. */ 1378 aprint_normal("%s chip is in D%d power mode " 1379 "-- setting to D0\n", sc->sk_dev.dv_xname, 1380 command & SK_PSTATE_MASK); 1381 command &= 0xFFFFFFFC; 1382 pci_conf_write(pc, pa->pa_tag, 1383 SK_PCI_PWRMGMTCTRL, command); 1384 1385 /* Restore PCI config data. */ 1386 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1387 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1388 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1389 } 1390 } 1391 1392 /* 1393 * Map control/status registers. 1394 */ 1395 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1396 command |= PCI_COMMAND_IO_ENABLE | 1397 PCI_COMMAND_MEM_ENABLE | 1398 PCI_COMMAND_MASTER_ENABLE; 1399 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1400 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1401 1402 #ifdef SK_USEIOSPACE 1403 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1404 aprint_error(": failed to enable I/O ports!\n"); 1405 goto fail; 1406 } 1407 /* 1408 * Map control/status registers. 1409 */ 1410 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1411 &iobase, &iosize)) { 1412 aprint_error(": can't find i/o space\n"); 1413 goto fail; 1414 } 1415 #else 1416 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1417 aprint_error(": failed to enable memory mapping!\n"); 1418 goto fail; 1419 } 1420 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1421 switch (memtype) { 1422 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1423 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1424 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1425 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1426 &iobase, &iosize) == 0) 1427 break; 1428 default: 1429 aprint_error("%s: can't find mem space\n", 1430 sc->sk_dev.dv_xname); 1431 return; 1432 } 1433 1434 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1435 #endif 1436 sc->sc_dmatag = pa->pa_dmat; 1437 1438 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1439 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1440 1441 /* bail out here if chip is not recognized */ 1442 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1443 aprint_error("%s: unknown chip type\n",sc->sk_dev.dv_xname); 1444 goto fail; 1445 } 1446 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1447 1448 /* Allocate interrupt */ 1449 if (pci_intr_map(pa, &ih)) { 1450 aprint_error(": couldn't map interrupt\n"); 1451 goto fail; 1452 } 1453 1454 intrstr = pci_intr_string(pc, ih); 1455 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1456 if (sc->sk_intrhand == NULL) { 1457 aprint_error(": couldn't establish interrupt"); 1458 if (intrstr != NULL) 1459 aprint_normal(" at %s", intrstr); 1460 goto fail; 1461 } 1462 aprint_normal(": %s\n", intrstr); 1463 1464 /* Reset the adapter. */ 1465 sk_reset(sc); 1466 1467 /* Read and save vital product data from EEPROM. */ 1468 sk_vpd_read(sc); 1469 1470 if (sc->sk_type == SK_GENESIS) { 1471 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1472 /* Read and save RAM size and RAMbuffer offset */ 1473 switch(val) { 1474 case SK_RAMSIZE_512K_64: 1475 sc->sk_ramsize = 0x80000; 1476 sc->sk_rboff = SK_RBOFF_0; 1477 break; 1478 case SK_RAMSIZE_1024K_64: 1479 sc->sk_ramsize = 0x100000; 1480 sc->sk_rboff = SK_RBOFF_80000; 1481 break; 1482 case SK_RAMSIZE_1024K_128: 1483 sc->sk_ramsize = 0x100000; 1484 sc->sk_rboff = SK_RBOFF_0; 1485 break; 1486 case SK_RAMSIZE_2048K_128: 1487 sc->sk_ramsize = 0x200000; 1488 sc->sk_rboff = SK_RBOFF_0; 1489 break; 1490 default: 1491 aprint_error("%s: unknown ram size: %d\n", 1492 sc->sk_dev.dv_xname, val); 1493 goto fail; 1494 break; 1495 } 1496 1497 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1498 sc->sk_ramsize, sc->sk_ramsize / 1024, 1499 sc->sk_rboff)); 1500 } else { 1501 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1502 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1503 sc->sk_rboff = SK_RBOFF_0; 1504 1505 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1506 sc->sk_ramsize / 1024, sc->sk_ramsize, 1507 sc->sk_rboff)); 1508 } 1509 1510 /* Read and save physical media type */ 1511 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1512 case SK_PMD_1000BASESX: 1513 sc->sk_pmd = IFM_1000_SX; 1514 break; 1515 case SK_PMD_1000BASELX: 1516 sc->sk_pmd = IFM_1000_LX; 1517 break; 1518 case SK_PMD_1000BASECX: 1519 sc->sk_pmd = IFM_1000_CX; 1520 break; 1521 case SK_PMD_1000BASETX: 1522 sc->sk_pmd = IFM_1000_T; 1523 break; 1524 default: 1525 aprint_error("%s: unknown media type: 0x%x\n", 1526 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1527 goto fail; 1528 } 1529 1530 /* determine whether to name it with vpd or just make it up */ 1531 /* Marvell Yukon VPD's can freqently be bogus */ 1532 1533 switch (pa->pa_id) { 1534 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1535 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1536 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1537 case PCI_PRODUCT_3COM_3C940: 1538 case PCI_PRODUCT_DLINK_DGE530T: 1539 case PCI_PRODUCT_LINKSYS_EG1032: 1540 case PCI_PRODUCT_LINKSYS_EG1064: 1541 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1542 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1543 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1544 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1545 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1546 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1547 sc->sk_name = sc->sk_vpd_prodname; 1548 break; 1549 case PCI_ID_CODE(PCI_VENDOR_GALILEO,PCI_PRODUCT_GALILEO_SKNET): 1550 /* whoops yukon vpd prodname bears no resemblance to reality */ 1551 switch (sc->sk_type) { 1552 case SK_GENESIS: 1553 sc->sk_name = sc->sk_vpd_prodname; 1554 break; 1555 case SK_YUKON: 1556 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1557 break; 1558 case SK_YUKON_LITE: 1559 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1560 break; 1561 case SK_YUKON_LP: 1562 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1563 break; 1564 default: 1565 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1566 } 1567 1568 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1569 1570 if ( sc->sk_type == SK_YUKON ) { 1571 uint32_t flashaddr; 1572 uint8_t testbyte; 1573 1574 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1575 1576 /* test Flash-Address Register */ 1577 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1578 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1579 1580 if (testbyte != 0) { 1581 /* this is yukon lite Rev. A0 */ 1582 sc->sk_type = SK_YUKON_LITE; 1583 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1584 /* restore Flash-Address Register */ 1585 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1586 } 1587 } 1588 break; 1589 case PCI_ID_CODE(PCI_VENDOR_GALILEO,PCI_PRODUCT_GALILEO_BELKIN): 1590 sc->sk_name = sc->sk_vpd_prodname; 1591 break; 1592 default: 1593 sc->sk_name = "Unkown Marvell"; 1594 } 1595 1596 1597 if ( sc->sk_type == SK_YUKON_LITE ) { 1598 switch (sc->sk_rev) { 1599 case SK_YUKON_LITE_REV_A0: 1600 revstr = "A0"; 1601 break; 1602 case SK_YUKON_LITE_REV_A1: 1603 revstr = "A1"; 1604 break; 1605 case SK_YUKON_LITE_REV_A3: 1606 revstr = "A3"; 1607 break; 1608 default: 1609 revstr = ""; 1610 } 1611 } else { 1612 revstr = ""; 1613 } 1614 1615 /* Announce the product name. */ 1616 aprint_normal("%s: %s rev. %s(0x%x)\n", sc->sk_dev.dv_xname, 1617 sc->sk_name, revstr, sc->sk_rev); 1618 1619 skca.skc_port = SK_PORT_A; 1620 (void)config_found(&sc->sk_dev, &skca, skcprint); 1621 1622 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1623 skca.skc_port = SK_PORT_B; 1624 (void)config_found(&sc->sk_dev, &skca, skcprint); 1625 } 1626 1627 /* Turn on the 'driver is loaded' LED. */ 1628 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1629 1630 fail: 1631 splx(s); 1632 } 1633 1634 int 1635 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1636 { 1637 struct sk_softc *sc = sc_if->sk_softc; 1638 struct sk_tx_desc *f = NULL; 1639 u_int32_t frag, cur, cnt = 0; 1640 int i; 1641 struct sk_txmap_entry *entry; 1642 bus_dmamap_t txmap; 1643 1644 DPRINTFN(3, ("sk_encap\n")); 1645 1646 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1647 if (entry == NULL) { 1648 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1649 return ENOBUFS; 1650 } 1651 txmap = entry->dmamap; 1652 1653 cur = frag = *txidx; 1654 1655 #ifdef SK_DEBUG 1656 if (skdebug >= 3) 1657 sk_dump_mbuf(m_head); 1658 #endif 1659 1660 /* 1661 * Start packing the mbufs in this chain into 1662 * the fragment pointers. Stop when we run out 1663 * of fragments or hit the end of the mbuf chain. 1664 */ 1665 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1666 BUS_DMA_NOWAIT)) { 1667 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1668 return(ENOBUFS); 1669 } 1670 1671 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1672 1673 /* Sync the DMA map. */ 1674 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1675 BUS_DMASYNC_PREWRITE); 1676 1677 for (i = 0; i < txmap->dm_nsegs; i++) { 1678 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1679 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1680 return(ENOBUFS); 1681 } 1682 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1683 f->sk_data_lo = txmap->dm_segs[i].ds_addr; 1684 f->sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1685 if (cnt == 0) 1686 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1687 else 1688 f->sk_ctl |= SK_TXCTL_OWN; 1689 1690 cur = frag; 1691 SK_INC(frag, SK_TX_RING_CNT); 1692 cnt++; 1693 } 1694 1695 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1696 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1697 1698 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1699 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1700 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1701 1702 /* Sync descriptors before handing to chip */ 1703 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1704 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1705 1706 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1707 1708 /* Sync first descriptor to hand it off */ 1709 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1710 1711 sc_if->sk_cdata.sk_tx_cnt += cnt; 1712 1713 #ifdef SK_DEBUG 1714 if (skdebug >= 3) { 1715 struct sk_tx_desc *desc; 1716 u_int32_t idx; 1717 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1718 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1719 sk_dump_txdesc(desc, idx); 1720 } 1721 } 1722 #endif 1723 1724 *txidx = frag; 1725 1726 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1727 1728 return(0); 1729 } 1730 1731 void 1732 sk_start(struct ifnet *ifp) 1733 { 1734 struct sk_if_softc *sc_if = ifp->if_softc; 1735 struct sk_softc *sc = sc_if->sk_softc; 1736 struct mbuf *m_head = NULL; 1737 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1738 int pkts = 0; 1739 1740 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1741 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1742 1743 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1744 1745 IFQ_POLL(&ifp->if_snd, m_head); 1746 if (m_head == NULL) 1747 break; 1748 1749 /* 1750 * Pack the data into the transmit ring. If we 1751 * don't have room, set the OACTIVE flag and wait 1752 * for the NIC to drain the ring. 1753 */ 1754 if (sk_encap(sc_if, m_head, &idx)) { 1755 ifp->if_flags |= IFF_OACTIVE; 1756 break; 1757 } 1758 1759 /* now we are committed to transmit the packet */ 1760 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1761 pkts++; 1762 1763 /* 1764 * If there's a BPF listener, bounce a copy of this frame 1765 * to him. 1766 */ 1767 #if NBPFILTER > 0 1768 if (ifp->if_bpf) 1769 bpf_mtap(ifp->if_bpf, m_head); 1770 #endif 1771 } 1772 if (pkts == 0) 1773 return; 1774 1775 /* Transmit */ 1776 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1777 sc_if->sk_cdata.sk_tx_prod = idx; 1778 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1779 1780 /* Set a timeout in case the chip goes out to lunch. */ 1781 ifp->if_timer = 5; 1782 } 1783 } 1784 1785 1786 void 1787 sk_watchdog(struct ifnet *ifp) 1788 { 1789 struct sk_if_softc *sc_if = ifp->if_softc; 1790 1791 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1792 (void) sk_init(ifp); 1793 } 1794 1795 void 1796 sk_shutdown(void * v) 1797 { 1798 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 1799 struct sk_softc *sc = sc_if->sk_softc; 1800 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1801 1802 DPRINTFN(2, ("sk_shutdown\n")); 1803 sk_stop(ifp,1); 1804 1805 /* Turn off the 'driver is loaded' LED. */ 1806 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1807 1808 /* 1809 * Reset the GEnesis controller. Doing this should also 1810 * assert the resets on the attached XMAC(s). 1811 */ 1812 sk_reset(sc); 1813 } 1814 1815 void 1816 sk_rxeof(struct sk_if_softc *sc_if) 1817 { 1818 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1819 struct mbuf *m; 1820 struct sk_chain *cur_rx; 1821 struct sk_rx_desc *cur_desc; 1822 int i, cur, total_len = 0; 1823 u_int32_t rxstat; 1824 bus_dmamap_t dmamap; 1825 1826 i = sc_if->sk_cdata.sk_rx_prod; 1827 1828 DPRINTFN(3, ("sk_rxeof %d\n", i)); 1829 1830 for (;;) { 1831 cur = i; 1832 1833 /* Sync the descriptor */ 1834 SK_CDRXSYNC(sc_if, cur, 1835 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1836 1837 if (sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl & SK_RXCTL_OWN) { 1838 /* Invalidate the descriptor -- it's not ready yet */ 1839 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 1840 sc_if->sk_cdata.sk_rx_prod = i; 1841 break; 1842 } 1843 1844 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1845 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 1846 dmamap = sc_if->sk_cdata.sk_rx_map[cur]; 1847 1848 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1849 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1850 1851 rxstat = cur_desc->sk_xmac_rxstat; 1852 m = cur_rx->sk_mbuf; 1853 cur_rx->sk_mbuf = NULL; 1854 total_len = SK_RXBYTES(cur_desc->sk_ctl); 1855 1856 sc_if->sk_cdata.sk_rx_map[cur] = 0; 1857 1858 SK_INC(i, SK_RX_RING_CNT); 1859 1860 if (rxstat & XM_RXSTAT_ERRFRAME) { 1861 ifp->if_ierrors++; 1862 sk_newbuf(sc_if, cur, m, dmamap); 1863 continue; 1864 } 1865 1866 /* 1867 * Try to allocate a new jumbo buffer. If that 1868 * fails, copy the packet to mbufs and put the 1869 * jumbo buffer back in the ring so it can be 1870 * re-used. If allocating mbufs fails, then we 1871 * have to drop the packet. 1872 */ 1873 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1874 struct mbuf *m0; 1875 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1876 total_len + ETHER_ALIGN, 0, ifp, NULL); 1877 sk_newbuf(sc_if, cur, m, dmamap); 1878 if (m0 == NULL) { 1879 printf("%s: no receive buffers " 1880 "available -- packet dropped!\n", 1881 sc_if->sk_dev.dv_xname); 1882 ifp->if_ierrors++; 1883 continue; 1884 } 1885 m_adj(m0, ETHER_ALIGN); 1886 m = m0; 1887 } else { 1888 m->m_pkthdr.rcvif = ifp; 1889 m->m_pkthdr.len = m->m_len = total_len; 1890 } 1891 1892 ifp->if_ipackets++; 1893 1894 #if NBPFILTER > 0 1895 if (ifp->if_bpf) 1896 bpf_mtap(ifp->if_bpf, m); 1897 #endif 1898 /* pass it on. */ 1899 (*ifp->if_input)(ifp, m); 1900 } 1901 } 1902 1903 void 1904 sk_txeof(struct sk_if_softc *sc_if) 1905 { 1906 struct sk_softc *sc = sc_if->sk_softc; 1907 struct sk_tx_desc *cur_tx; 1908 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1909 u_int32_t idx; 1910 struct sk_txmap_entry *entry; 1911 1912 DPRINTFN(3, ("sk_txeof\n")); 1913 1914 /* 1915 * Go through our tx ring and free mbufs for those 1916 * frames that have been sent. 1917 */ 1918 idx = sc_if->sk_cdata.sk_tx_cons; 1919 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1920 SK_CDTXSYNC(sc_if, idx, 1, 1921 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1922 1923 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1924 #ifdef SK_DEBUG 1925 if (skdebug >= 3) 1926 sk_dump_txdesc(cur_tx, idx); 1927 #endif 1928 if (cur_tx->sk_ctl & SK_TXCTL_OWN) { 1929 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 1930 break; 1931 } 1932 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1933 ifp->if_opackets++; 1934 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1935 entry = sc_if->sk_cdata.sk_tx_map[idx]; 1936 1937 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1938 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1939 1940 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1941 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1942 1943 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1944 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 1945 link); 1946 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 1947 } 1948 sc_if->sk_cdata.sk_tx_cnt--; 1949 SK_INC(idx, SK_TX_RING_CNT); 1950 } 1951 if (sc_if->sk_cdata.sk_tx_cnt == 0) 1952 ifp->if_timer = 0; 1953 else /* nudge chip to keep tx ring moving */ 1954 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1955 1956 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 1957 ifp->if_flags &= ~IFF_OACTIVE; 1958 1959 sc_if->sk_cdata.sk_tx_cons = idx; 1960 } 1961 1962 void 1963 sk_tick(void *xsc_if) 1964 { 1965 struct sk_if_softc *sc_if = xsc_if; 1966 struct mii_data *mii = &sc_if->sk_mii; 1967 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1968 int i; 1969 1970 DPRINTFN(3, ("sk_tick\n")); 1971 1972 if (!(ifp->if_flags & IFF_UP)) 1973 return; 1974 1975 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1976 sk_intr_bcom(sc_if); 1977 return; 1978 } 1979 1980 /* 1981 * According to SysKonnect, the correct way to verify that 1982 * the link has come back up is to poll bit 0 of the GPIO 1983 * register three times. This pin has the signal from the 1984 * link sync pin connected to it; if we read the same link 1985 * state 3 times in a row, we know the link is up. 1986 */ 1987 for (i = 0; i < 3; i++) { 1988 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1989 break; 1990 } 1991 1992 if (i != 3) { 1993 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 1994 return; 1995 } 1996 1997 /* Turn the GP0 interrupt back on. */ 1998 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1999 SK_XM_READ_2(sc_if, XM_ISR); 2000 mii_tick(mii); 2001 mii_pollstat(mii); 2002 callout_stop(&sc_if->sk_tick_ch); 2003 } 2004 2005 void 2006 sk_intr_bcom(struct sk_if_softc *sc_if) 2007 { 2008 struct mii_data *mii = &sc_if->sk_mii; 2009 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2010 int status; 2011 2012 2013 DPRINTFN(3, ("sk_intr_bcom\n")); 2014 2015 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2016 2017 /* 2018 * Read the PHY interrupt register to make sure 2019 * we clear any pending interrupts. 2020 */ 2021 status = sk_xmac_miibus_readreg((struct device *)sc_if, 2022 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2023 2024 if (!(ifp->if_flags & IFF_RUNNING)) { 2025 sk_init_xmac(sc_if); 2026 return; 2027 } 2028 2029 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2030 int lstat; 2031 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 2032 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2033 2034 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2035 mii_mediachg(mii); 2036 /* Turn off the link LED. */ 2037 SK_IF_WRITE_1(sc_if, 0, 2038 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2039 sc_if->sk_link = 0; 2040 } else if (status & BRGPHY_ISR_LNK_CHG) { 2041 sk_xmac_miibus_writereg((struct device *)sc_if, 2042 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2043 mii_tick(mii); 2044 sc_if->sk_link = 1; 2045 /* Turn on the link LED. */ 2046 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2047 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2048 SK_LINKLED_BLINK_OFF); 2049 mii_pollstat(mii); 2050 } else { 2051 mii_tick(mii); 2052 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2053 } 2054 } 2055 2056 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2057 } 2058 2059 void 2060 sk_intr_xmac(struct sk_if_softc *sc_if) 2061 { 2062 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2063 2064 DPRINTFN(3, ("sk_intr_xmac\n")); 2065 2066 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2067 if (status & XM_ISR_GP0_SET) { 2068 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2069 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2070 } 2071 2072 if (status & XM_ISR_AUTONEG_DONE) { 2073 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2074 } 2075 } 2076 2077 if (status & XM_IMR_TX_UNDERRUN) 2078 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2079 2080 if (status & XM_IMR_RX_OVERRUN) 2081 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2082 } 2083 2084 void 2085 sk_intr_yukon(sc_if) 2086 struct sk_if_softc *sc_if; 2087 { 2088 int status; 2089 2090 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2091 2092 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2093 } 2094 2095 int 2096 sk_intr(void *xsc) 2097 { 2098 struct sk_softc *sc = xsc; 2099 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2100 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2101 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2102 u_int32_t status; 2103 int claimed = 0; 2104 2105 if (sc_if0 != NULL) 2106 ifp0 = &sc_if0->sk_ethercom.ec_if; 2107 if (sc_if1 != NULL) 2108 ifp1 = &sc_if1->sk_ethercom.ec_if; 2109 2110 for (;;) { 2111 status = CSR_READ_4(sc, SK_ISSR); 2112 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2113 2114 if (!(status & sc->sk_intrmask)) 2115 break; 2116 2117 claimed = 1; 2118 2119 /* Handle receive interrupts first. */ 2120 if (status & SK_ISR_RX1_EOF) { 2121 sk_rxeof(sc_if0); 2122 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2123 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2124 } 2125 if (status & SK_ISR_RX2_EOF) { 2126 sk_rxeof(sc_if1); 2127 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2128 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2129 } 2130 2131 /* Then transmit interrupts. */ 2132 if (status & SK_ISR_TX1_S_EOF) { 2133 sk_txeof(sc_if0); 2134 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2135 SK_TXBMU_CLR_IRQ_EOF); 2136 } 2137 if (status & SK_ISR_TX2_S_EOF) { 2138 sk_txeof(sc_if1); 2139 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2140 SK_TXBMU_CLR_IRQ_EOF); 2141 } 2142 2143 /* Then MAC interrupts. */ 2144 if (status & SK_ISR_MAC1 && (ifp0->if_flags & IFF_RUNNING)) { 2145 if (sc->sk_type == SK_GENESIS) 2146 sk_intr_xmac(sc_if0); 2147 else 2148 sk_intr_yukon(sc_if0); 2149 } 2150 2151 if (status & SK_ISR_MAC2 && (ifp1->if_flags & IFF_RUNNING)) { 2152 if (sc->sk_type == SK_GENESIS) 2153 sk_intr_xmac(sc_if1); 2154 else 2155 sk_intr_yukon(sc_if1); 2156 2157 } 2158 2159 if (status & SK_ISR_EXTERNAL_REG) { 2160 if (ifp0 != NULL && 2161 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2162 sk_intr_bcom(sc_if0); 2163 2164 if (ifp1 != NULL && 2165 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2166 sk_intr_bcom(sc_if1); 2167 } 2168 } 2169 2170 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2171 2172 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2173 sk_start(ifp0); 2174 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2175 sk_start(ifp1); 2176 2177 #if NRND > 0 2178 if (RND_ENABLED(&sc->rnd_source)) 2179 rnd_add_uint32(&sc->rnd_source, status); 2180 #endif 2181 2182 return (claimed); 2183 } 2184 2185 void 2186 sk_init_xmac(struct sk_if_softc *sc_if) 2187 { 2188 struct sk_softc *sc = sc_if->sk_softc; 2189 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2190 static const struct sk_bcom_hack bhack[] = { 2191 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2192 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2193 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2194 { 0, 0 } }; 2195 2196 DPRINTFN(1, ("sk_init_xmac\n")); 2197 2198 /* Unreset the XMAC. */ 2199 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2200 DELAY(1000); 2201 2202 /* Reset the XMAC's internal state. */ 2203 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2204 2205 /* Save the XMAC II revision */ 2206 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2207 2208 /* 2209 * Perform additional initialization for external PHYs, 2210 * namely for the 1000baseTX cards that use the XMAC's 2211 * GMII mode. 2212 */ 2213 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2214 int i = 0; 2215 u_int32_t val; 2216 2217 /* Take PHY out of reset. */ 2218 val = sk_win_read_4(sc, SK_GPIO); 2219 if (sc_if->sk_port == SK_PORT_A) 2220 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2221 else 2222 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2223 sk_win_write_4(sc, SK_GPIO, val); 2224 2225 /* Enable GMII mode on the XMAC. */ 2226 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2227 2228 sk_xmac_miibus_writereg((struct device *)sc_if, 2229 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2230 DELAY(10000); 2231 sk_xmac_miibus_writereg((struct device *)sc_if, 2232 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2233 2234 /* 2235 * Early versions of the BCM5400 apparently have 2236 * a bug that requires them to have their reserved 2237 * registers initialized to some magic values. I don't 2238 * know what the numbers do, I'm just the messenger. 2239 */ 2240 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2241 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2242 while(bhack[i].reg) { 2243 sk_xmac_miibus_writereg((struct device *)sc_if, 2244 SK_PHYADDR_BCOM, bhack[i].reg, 2245 bhack[i].val); 2246 i++; 2247 } 2248 } 2249 } 2250 2251 /* Set station address */ 2252 SK_XM_WRITE_2(sc_if, XM_PAR0, 2253 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2254 SK_XM_WRITE_2(sc_if, XM_PAR1, 2255 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2256 SK_XM_WRITE_2(sc_if, XM_PAR2, 2257 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2258 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2259 2260 if (ifp->if_flags & IFF_PROMISC) { 2261 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2262 } else { 2263 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2264 } 2265 2266 if (ifp->if_flags & IFF_BROADCAST) { 2267 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2268 } else { 2269 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2270 } 2271 2272 /* We don't need the FCS appended to the packet. */ 2273 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2274 2275 /* We want short frames padded to 60 bytes. */ 2276 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2277 2278 /* 2279 * Enable the reception of all error frames. This is is 2280 * a necessary evil due to the design of the XMAC. The 2281 * XMAC's receive FIFO is only 8K in size, however jumbo 2282 * frames can be up to 9000 bytes in length. When bad 2283 * frame filtering is enabled, the XMAC's RX FIFO operates 2284 * in 'store and forward' mode. For this to work, the 2285 * entire frame has to fit into the FIFO, but that means 2286 * that jumbo frames larger than 8192 bytes will be 2287 * truncated. Disabling all bad frame filtering causes 2288 * the RX FIFO to operate in streaming mode, in which 2289 * case the XMAC will start transfering frames out of the 2290 * RX FIFO as soon as the FIFO threshold is reached. 2291 */ 2292 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2293 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2294 XM_MODE_RX_INRANGELEN); 2295 2296 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2297 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2298 else 2299 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2300 2301 /* 2302 * Bump up the transmit threshold. This helps hold off transmit 2303 * underruns when we're blasting traffic from both ports at once. 2304 */ 2305 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2306 2307 /* Set multicast filter */ 2308 sk_setmulti(sc_if); 2309 2310 /* Clear and enable interrupts */ 2311 SK_XM_READ_2(sc_if, XM_ISR); 2312 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2313 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2314 else 2315 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2316 2317 /* Configure MAC arbiter */ 2318 switch(sc_if->sk_xmac_rev) { 2319 case XM_XMAC_REV_B2: 2320 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2321 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2322 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2323 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2324 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2325 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2326 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2327 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2328 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2329 break; 2330 case XM_XMAC_REV_C1: 2331 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2332 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2333 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2334 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2335 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2336 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2337 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2338 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2339 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2340 break; 2341 default: 2342 break; 2343 } 2344 sk_win_write_2(sc, SK_MACARB_CTL, 2345 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2346 2347 sc_if->sk_link = 1; 2348 } 2349 2350 void sk_init_yukon(sc_if) 2351 struct sk_if_softc *sc_if; 2352 { 2353 u_int32_t /*mac, */phy; 2354 u_int16_t reg; 2355 struct sk_softc *sc; 2356 int i; 2357 2358 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2359 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2360 2361 sc = sc_if->sk_softc; 2362 if (sc->sk_type == SK_YUKON_LITE && 2363 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2364 /* Take PHY out of reset. */ 2365 sk_win_write_4(sc, SK_GPIO, 2366 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2367 } 2368 2369 2370 /* GMAC and GPHY Reset */ 2371 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2372 2373 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2374 2375 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2376 DELAY(1000); 2377 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2378 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2379 DELAY(1000); 2380 2381 2382 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2383 2384 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2385 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2386 2387 switch(sc_if->sk_softc->sk_pmd) { 2388 case IFM_1000_SX: 2389 case IFM_1000_LX: 2390 phy |= SK_GPHY_FIBER; 2391 break; 2392 2393 case IFM_1000_CX: 2394 case IFM_1000_T: 2395 phy |= SK_GPHY_COPPER; 2396 break; 2397 } 2398 2399 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2400 2401 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2402 DELAY(1000); 2403 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2404 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2405 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2406 2407 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2408 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2409 2410 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2411 2412 /* unused read of the interrupt source register */ 2413 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2414 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2415 2416 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2417 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2418 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2419 2420 /* MIB Counter Clear Mode set */ 2421 reg |= YU_PAR_MIB_CLR; 2422 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2423 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2424 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2425 2426 /* MIB Counter Clear Mode clear */ 2427 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2428 reg &= ~YU_PAR_MIB_CLR; 2429 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2430 2431 /* receive control reg */ 2432 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2433 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2434 YU_RCR_CRCR); 2435 2436 /* transmit parameter register */ 2437 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2438 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2439 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2440 2441 /* serial mode register */ 2442 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2443 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2444 YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e)); 2445 2446 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2447 /* Setup Yukon's address */ 2448 for (i = 0; i < 3; i++) { 2449 /* Write Source Address 1 (unicast filter) */ 2450 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2451 sc_if->sk_enaddr[i * 2] | 2452 sc_if->sk_enaddr[i * 2 + 1] << 8); 2453 } 2454 2455 for (i = 0; i < 3; i++) { 2456 reg = sk_win_read_2(sc_if->sk_softc, 2457 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2458 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2459 } 2460 2461 /* Set multicast filter */ 2462 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2463 sk_setmulti(sc_if); 2464 2465 /* enable interrupt mask for counter overflows */ 2466 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2467 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2468 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2469 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2470 2471 /* Configure RX MAC FIFO */ 2472 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2473 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2474 2475 /* Configure TX MAC FIFO */ 2476 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2477 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2478 2479 DPRINTFN(6, ("sk_init_yukon: end\n")); 2480 } 2481 2482 /* 2483 * Note that to properly initialize any part of the GEnesis chip, 2484 * you first have to take it out of reset mode. 2485 */ 2486 int 2487 sk_init(struct ifnet *ifp) 2488 { 2489 struct sk_if_softc *sc_if = ifp->if_softc; 2490 struct sk_softc *sc = sc_if->sk_softc; 2491 struct mii_data *mii = &sc_if->sk_mii; 2492 int s; 2493 2494 DPRINTFN(1, ("sk_init\n")); 2495 2496 s = splnet(); 2497 2498 if (ifp->if_flags & IFF_RUNNING) { 2499 splx(s); 2500 return 0; 2501 } 2502 2503 /* Cancel pending I/O and free all RX/TX buffers. */ 2504 sk_stop(ifp,0); 2505 2506 if (sc->sk_type == SK_GENESIS) { 2507 /* Configure LINK_SYNC LED */ 2508 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2509 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2510 SK_LINKLED_LINKSYNC_ON); 2511 2512 /* Configure RX LED */ 2513 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2514 SK_RXLEDCTL_COUNTER_START); 2515 2516 /* Configure TX LED */ 2517 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2518 SK_TXLEDCTL_COUNTER_START); 2519 } 2520 2521 /* Configure I2C registers */ 2522 2523 /* Configure XMAC(s) */ 2524 switch (sc->sk_type) { 2525 case SK_GENESIS: 2526 sk_init_xmac(sc_if); 2527 break; 2528 case SK_YUKON: 2529 case SK_YUKON_LITE: 2530 case SK_YUKON_LP: 2531 sk_init_yukon(sc_if); 2532 break; 2533 } 2534 mii_mediachg(mii); 2535 2536 if (sc->sk_type == SK_GENESIS) { 2537 /* Configure MAC FIFOs */ 2538 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2539 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2540 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2541 2542 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2543 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2544 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2545 } 2546 2547 /* Configure transmit arbiter(s) */ 2548 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2549 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2550 2551 /* Configure RAMbuffers */ 2552 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2553 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2554 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2555 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2556 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2557 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2558 2559 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2560 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2561 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2562 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2563 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2564 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2565 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2566 2567 /* Configure BMUs */ 2568 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2569 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2570 SK_RX_RING_ADDR(sc_if, 0)); 2571 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2572 2573 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2574 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2575 SK_TX_RING_ADDR(sc_if, 0)); 2576 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2577 2578 /* Init descriptors */ 2579 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2580 printf("%s: initialization failed: no " 2581 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2582 sk_stop(ifp,0); 2583 splx(s); 2584 return(ENOBUFS); 2585 } 2586 2587 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2588 printf("%s: initialization failed: no " 2589 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2590 sk_stop(ifp,0); 2591 splx(s); 2592 return(ENOBUFS); 2593 } 2594 2595 /* Configure interrupt handling */ 2596 CSR_READ_4(sc, SK_ISSR); 2597 if (sc_if->sk_port == SK_PORT_A) 2598 sc->sk_intrmask |= SK_INTRS1; 2599 else 2600 sc->sk_intrmask |= SK_INTRS2; 2601 2602 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2603 2604 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2605 2606 /* Start BMUs. */ 2607 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2608 2609 if (sc->sk_type == SK_GENESIS) { 2610 /* Enable XMACs TX and RX state machines */ 2611 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2612 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2613 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2614 } 2615 2616 if (SK_YUKON_FAMILY(sc->sk_type)) { 2617 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2618 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2619 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2620 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2621 } 2622 2623 2624 ifp->if_flags |= IFF_RUNNING; 2625 ifp->if_flags &= ~IFF_OACTIVE; 2626 2627 splx(s); 2628 return(0); 2629 } 2630 2631 void 2632 sk_stop(struct ifnet *ifp, int disable) 2633 { 2634 struct sk_if_softc *sc_if = ifp->if_softc; 2635 struct sk_softc *sc = sc_if->sk_softc; 2636 int i; 2637 2638 DPRINTFN(1, ("sk_stop\n")); 2639 2640 callout_stop(&sc_if->sk_tick_ch); 2641 2642 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2643 u_int32_t val; 2644 2645 /* Put PHY back into reset. */ 2646 val = sk_win_read_4(sc, SK_GPIO); 2647 if (sc_if->sk_port == SK_PORT_A) { 2648 val |= SK_GPIO_DIR0; 2649 val &= ~SK_GPIO_DAT0; 2650 } else { 2651 val |= SK_GPIO_DIR2; 2652 val &= ~SK_GPIO_DAT2; 2653 } 2654 sk_win_write_4(sc, SK_GPIO, val); 2655 } 2656 2657 /* Turn off various components of this interface. */ 2658 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2659 switch (sc->sk_type) { 2660 case SK_GENESIS: 2661 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2662 SK_TXMACCTL_XMAC_RESET); 2663 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2664 break; 2665 case SK_YUKON: 2666 case SK_YUKON_LITE: 2667 case SK_YUKON_LP: 2668 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2669 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2670 break; 2671 } 2672 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2673 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2674 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2675 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2676 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2677 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2678 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2679 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2680 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2681 2682 /* Disable interrupts */ 2683 if (sc_if->sk_port == SK_PORT_A) 2684 sc->sk_intrmask &= ~SK_INTRS1; 2685 else 2686 sc->sk_intrmask &= ~SK_INTRS2; 2687 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2688 2689 SK_XM_READ_2(sc_if, XM_ISR); 2690 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2691 2692 /* Free RX and TX mbufs still in the queues. */ 2693 for (i = 0; i < SK_RX_RING_CNT; i++) { 2694 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2695 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2696 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2697 } 2698 } 2699 2700 for (i = 0; i < SK_TX_RING_CNT; i++) { 2701 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2702 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2703 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2704 } 2705 } 2706 2707 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2708 } 2709 2710 CFATTACH_DECL(skc,sizeof(struct sk_softc), skc_probe, skc_attach, NULL, NULL); 2711 2712 /* 2713 struct cfdriver skc_cd = { 2714 0, "skc", DV_DULL 2715 }; 2716 */ 2717 2718 CFATTACH_DECL(sk,sizeof(struct sk_if_softc), sk_probe, sk_attach, NULL, NULL); 2719 2720 /* 2721 struct cfdriver sk_cd = { 2722 0, "sk", DV_IFNET 2723 }; 2724 */ 2725 2726 #ifdef SK_DEBUG 2727 void 2728 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2729 { 2730 #define DESC_PRINT(X) \ 2731 if (desc->X) \ 2732 printf("txdesc[%d]." #X "=%#x\n", \ 2733 idx, desc->X); 2734 2735 DESC_PRINT(sk_ctl); 2736 DESC_PRINT(sk_next); 2737 DESC_PRINT(sk_data_lo); 2738 DESC_PRINT(sk_data_hi); 2739 DESC_PRINT(sk_xmac_txstat); 2740 DESC_PRINT(sk_rsvd0); 2741 DESC_PRINT(sk_csum_startval); 2742 DESC_PRINT(sk_csum_startpos); 2743 DESC_PRINT(sk_csum_writepos); 2744 DESC_PRINT(sk_rsvd1); 2745 #undef PRINT 2746 } 2747 2748 void 2749 sk_dump_bytes(const char *data, int len) 2750 { 2751 int c, i, j; 2752 2753 for (i = 0; i < len; i += 16) { 2754 printf("%08x ", i); 2755 c = len - i; 2756 if (c > 16) c = 16; 2757 2758 for (j = 0; j < c; j++) { 2759 printf("%02x ", data[i + j] & 0xff); 2760 if ((j & 0xf) == 7 && j > 0) 2761 printf(" "); 2762 } 2763 2764 for (; j < 16; j++) 2765 printf(" "); 2766 printf(" "); 2767 2768 for (j = 0; j < c; j++) { 2769 int ch = data[i + j] & 0xff; 2770 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2771 } 2772 2773 printf("\n"); 2774 2775 if (c < 16) 2776 break; 2777 } 2778 } 2779 2780 void 2781 sk_dump_mbuf(struct mbuf *m) 2782 { 2783 int count = m->m_pkthdr.len; 2784 2785 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2786 2787 while (count > 0 && m) { 2788 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2789 m, m->m_data, m->m_len); 2790 sk_dump_bytes(mtod(m, char *), m->m_len); 2791 2792 count -= m->m_len; 2793 m = m->m_next; 2794 } 2795 } 2796 #endif 2797
Indexes created Wed Sep 24 02:09:48 GMT 2025