if_sk.c revision 1.2
1 /* $NetBSD: if_sk.c,v 1.2 2003/09/08 19:17:29 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* $OpenBSD: if_sk.c,v 1.33 2003/08/12 05:23:06 nate Exp $ */ 37 38 /* 39 * Copyright (c) 1997, 1998, 1999, 2000 40 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Bill Paul. 53 * 4. Neither the name of the author nor the names of any co-contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 67 * THE POSSIBILITY OF SUCH DAMAGE. 68 * 69 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 70 */ 71 72 /* 73 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 74 * 75 * Permission to use, copy, modify, and distribute this software for any 76 * purpose with or without fee is hereby granted, provided that the above 77 * copyright notice and this permission notice appear in all copies. 78 * 79 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 80 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 81 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 82 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 83 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 84 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 85 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 86 */ 87 88 /* 89 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 90 * the SK-984x series adapters, both single port and dual port. 91 * References: 92 * The XaQti XMAC II datasheet, 93 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * The SysKonnect GEnesis manual, http://www.syskonnect.com 95 * 96 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 97 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 98 * convenience to others until Vitesse corrects this problem: 99 * 100 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 101 * 102 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 103 * Department of Electrical Engineering 104 * Columbia University, New York City 105 */ 106 107 /* 108 * The SysKonnect gigabit ethernet adapters consist of two main 109 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 110 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 111 * components and a PHY while the GEnesis controller provides a PCI 112 * interface with DMA support. Each card may have between 512K and 113 * 2MB of SRAM on board depending on the configuration. 114 * 115 * The SysKonnect GEnesis controller can have either one or two XMAC 116 * chips connected to it, allowing single or dual port NIC configurations. 117 * SysKonnect has the distinction of being the only vendor on the market 118 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 119 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 120 * XMAC registers. This driver takes advantage of these features to allow 121 * both XMACs to operate as independent interfaces. 122 */ 123 124 #include "bpfilter.h" 125 126 #include <sys/param.h> 127 #include <sys/systm.h> 128 #include <sys/sockio.h> 129 #include <sys/mbuf.h> 130 #include <sys/malloc.h> 131 #include <sys/kernel.h> 132 #include <sys/socket.h> 133 #include <sys/device.h> 134 #include <sys/queue.h> 135 #include <sys/callout.h> 136 137 #include <net/if.h> 138 #include <net/if_dl.h> 139 #include <net/if_types.h> 140 141 #ifdef INET 142 #include <netinet/in.h> 143 #include <netinet/in_systm.h> 144 #include <netinet/in_var.h> 145 #include <netinet/ip.h> 146 #include <netinet/if_ether.h> 147 #endif 148 149 #include <net/if_media.h> 150 151 #if NBPFILTER > 0 152 #include <net/bpf.h> 153 #endif 154 155 #include <dev/mii/mii.h> 156 #include <dev/mii/miivar.h> 157 #include <dev/mii/brgphyreg.h> 158 159 #include <dev/pci/pcireg.h> 160 #include <dev/pci/pcivar.h> 161 #include <dev/pci/pcidevs.h> 162 163 #define SK_VERBOSE 164 /* #define SK_USEIOSPACE */ 165 166 #include <dev/pci/if_skreg.h> 167 #include <dev/pci/if_skvar.h> 168 169 int skc_probe(struct device *, struct cfdata *, void *); 170 void skc_attach(struct device *, struct device *self, void *aux); 171 int sk_probe(struct device *, struct cfdata *, void *); 172 void sk_attach(struct device *, struct device *self, void *aux); 173 int skcprint(void *, const char *); 174 int sk_intr(void *); 175 void sk_intr_bcom(struct sk_if_softc *); 176 void sk_intr_xmac(struct sk_if_softc *); 177 void sk_intr_yukon(struct sk_if_softc *); 178 void sk_rxeof(struct sk_if_softc *); 179 void sk_txeof(struct sk_if_softc *); 180 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 181 void sk_start(struct ifnet *); 182 int sk_ioctl(struct ifnet *, u_long, caddr_t); 183 int sk_init(struct ifnet *); 184 void sk_init_xmac(struct sk_if_softc *); 185 void sk_init_yukon(struct sk_if_softc *); 186 void sk_stop(struct ifnet *, int); 187 void sk_watchdog(struct ifnet *); 188 void sk_shutdown(void *); 189 int sk_ifmedia_upd(struct ifnet *); 190 void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 191 void sk_reset(struct sk_softc *); 192 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 193 int sk_init_rx_ring(struct sk_if_softc *); 194 int sk_init_tx_ring(struct sk_if_softc *); 195 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 196 void sk_vpd_read_res(struct sk_softc *, 197 struct vpd_res *, int); 198 void sk_vpd_read(struct sk_softc *); 199 200 int sk_xmac_miibus_readreg(struct device *, int, int); 201 void sk_xmac_miibus_writereg(struct device *, int, int, int); 202 void sk_xmac_miibus_statchg(struct device *); 203 204 int sk_marv_miibus_readreg(struct device *, int, int); 205 void sk_marv_miibus_writereg(struct device *, int, int, int); 206 void sk_marv_miibus_statchg(struct device *); 207 208 u_int32_t sk_calchash(caddr_t); 209 void sk_setfilt(struct sk_if_softc *, caddr_t, int); 210 void sk_setmulti(struct sk_if_softc *); 211 void sk_tick(void *); 212 213 /* #define SK_DEBUG 2 */ 214 #ifdef SK_DEBUG 215 #define DPRINTF(x) if (skdebug) printf x 216 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 217 int skdebug = SK_DEBUG; 218 219 void sk_dump_txdesc(struct sk_tx_desc *, int); 220 void sk_dump_mbuf(struct mbuf *); 221 void sk_dump_bytes(const char *, int); 222 #else 223 #define DPRINTF(x) 224 #define DPRINTFN(n,x) 225 #endif 226 227 #define SK_SETBIT(sc, reg, x) \ 228 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 229 230 #define SK_CLRBIT(sc, reg, x) \ 231 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 232 233 #define SK_WIN_SETBIT_4(sc, reg, x) \ 234 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 235 236 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 237 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 238 239 #define SK_WIN_SETBIT_2(sc, reg, x) \ 240 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 241 242 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 243 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 244 245 /* supported device vendors */ 246 static const struct sk_product { 247 pci_vendor_id_t sk_vendor; 248 pci_product_id_t sk_product; 249 } sk_products[] = { 250 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 251 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 252 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 253 { 0, 0, } 254 }; 255 256 static inline u_int32_t 257 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 258 { 259 #ifdef SK_USEIOSPACE 260 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 261 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 262 #else 263 return CSR_READ_4(sc, reg); 264 #endif 265 } 266 267 static inline u_int16_t 268 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 269 { 270 #ifdef SK_USEIOSPACE 271 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 272 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 273 #else 274 return CSR_READ_2(sc, reg); 275 #endif 276 } 277 278 static inline u_int8_t 279 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 280 { 281 #ifdef SK_USEIOSPACE 282 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 283 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 284 #else 285 return CSR_READ_1(sc, reg); 286 #endif 287 } 288 289 static inline void 290 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 291 { 292 #ifdef SK_USEIOSPACE 293 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 294 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 295 #else 296 CSR_WRITE_4(sc, reg, x); 297 #endif 298 } 299 300 static inline void 301 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 302 { 303 #ifdef SK_USEIOSPACE 304 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 305 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 306 #else 307 CSR_WRITE_2(sc, reg, x); 308 #endif 309 } 310 311 static inline void 312 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 313 { 314 #ifdef SK_USEIOSPACE 315 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 316 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 317 #else 318 CSR_WRITE_1(sc, reg, x); 319 #endif 320 } 321 322 /* 323 * The VPD EEPROM contains Vital Product Data, as suggested in 324 * the PCI 2.1 specification. The VPD data is separared into areas 325 * denoted by resource IDs. The SysKonnect VPD contains an ID string 326 * resource (the name of the adapter), a read-only area resource 327 * containing various key/data fields and a read/write area which 328 * can be used to store asset management information or log messages. 329 * We read the ID string and read-only into buffers attached to 330 * the controller softc structure for later use. At the moment, 331 * we only use the ID string during sk_attach(). 332 */ 333 u_int8_t 334 sk_vpd_readbyte(struct sk_softc *sc, int addr) 335 { 336 int i; 337 338 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 339 for (i = 0; i < SK_TIMEOUT; i++) { 340 DELAY(1); 341 if (sk_win_read_2(sc, 342 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 343 break; 344 } 345 346 if (i == SK_TIMEOUT) 347 return(0); 348 349 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 350 } 351 352 void 353 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 354 { 355 int i; 356 u_int8_t *ptr; 357 358 ptr = (u_int8_t *)res; 359 for (i = 0; i < sizeof(struct vpd_res); i++) 360 ptr[i] = sk_vpd_readbyte(sc, i + addr); 361 } 362 363 void 364 sk_vpd_read(struct sk_softc *sc) 365 { 366 int pos = 0, i; 367 struct vpd_res res; 368 369 if (sc->sk_vpd_prodname != NULL) 370 free(sc->sk_vpd_prodname, M_DEVBUF); 371 if (sc->sk_vpd_readonly != NULL) 372 free(sc->sk_vpd_readonly, M_DEVBUF); 373 sc->sk_vpd_prodname = NULL; 374 sc->sk_vpd_readonly = NULL; 375 376 sk_vpd_read_res(sc, &res, pos); 377 378 if (res.vr_id != VPD_RES_ID) { 379 printf("%s: bad VPD resource id: expected %x got %x\n", 380 sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 381 return; 382 } 383 384 pos += sizeof(res); 385 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 386 if (sc->sk_vpd_prodname == NULL) 387 panic("sk_vpd_read"); 388 for (i = 0; i < res.vr_len; i++) 389 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 390 sc->sk_vpd_prodname[i] = '\0'; 391 pos += i; 392 393 sk_vpd_read_res(sc, &res, pos); 394 395 if (res.vr_id != VPD_RES_READ) { 396 printf("%s: bad VPD resource id: expected %x got %x\n", 397 sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 398 return; 399 } 400 401 pos += sizeof(res); 402 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 403 if (sc->sk_vpd_readonly == NULL) 404 panic("sk_vpd_read"); 405 for (i = 0; i < res.vr_len + 1; i++) 406 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 407 } 408 409 int 410 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 411 { 412 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 413 int i; 414 415 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 416 417 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 418 return(0); 419 420 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 421 SK_XM_READ_2(sc_if, XM_PHY_DATA); 422 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 423 for (i = 0; i < SK_TIMEOUT; i++) { 424 DELAY(1); 425 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 426 XM_MMUCMD_PHYDATARDY) 427 break; 428 } 429 430 if (i == SK_TIMEOUT) { 431 printf("%s: phy failed to come ready\n", 432 sc_if->sk_dev.dv_xname); 433 return(0); 434 } 435 } 436 DELAY(1); 437 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 438 } 439 440 void 441 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 442 { 443 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 444 int i; 445 446 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 447 448 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 449 for (i = 0; i < SK_TIMEOUT; i++) { 450 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 451 break; 452 } 453 454 if (i == SK_TIMEOUT) { 455 printf("%s: phy failed to come ready\n", 456 sc_if->sk_dev.dv_xname); 457 return; 458 } 459 460 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 461 for (i = 0; i < SK_TIMEOUT; i++) { 462 DELAY(1); 463 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 464 break; 465 } 466 467 if (i == SK_TIMEOUT) 468 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 469 } 470 471 void 472 sk_xmac_miibus_statchg(struct device *dev) 473 { 474 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 475 struct mii_data *mii = &sc_if->sk_mii; 476 477 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 478 479 /* 480 * If this is a GMII PHY, manually set the XMAC's 481 * duplex mode accordingly. 482 */ 483 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 484 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 485 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 486 } else { 487 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 488 } 489 } 490 } 491 492 int 493 sk_marv_miibus_readreg(dev, phy, reg) 494 struct device *dev; 495 int phy, reg; 496 { 497 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 498 u_int16_t val; 499 int i; 500 501 if (phy != 0 || 502 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 503 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 504 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 505 phy, reg)); 506 return(0); 507 } 508 509 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 510 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 511 512 for (i = 0; i < SK_TIMEOUT; i++) { 513 DELAY(1); 514 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 515 if (val & YU_SMICR_READ_VALID) 516 break; 517 } 518 519 if (i == SK_TIMEOUT) { 520 printf("%s: phy failed to come ready\n", 521 sc_if->sk_dev.dv_xname); 522 return 0; 523 } 524 525 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 526 SK_TIMEOUT)); 527 528 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 529 530 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 531 phy, reg, val)); 532 533 return val; 534 } 535 536 void 537 sk_marv_miibus_writereg(dev, phy, reg, val) 538 struct device *dev; 539 int phy, reg, val; 540 { 541 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 542 int i; 543 544 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 545 phy, reg, val)); 546 547 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 548 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 549 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 550 551 for (i = 0; i < SK_TIMEOUT; i++) { 552 DELAY(1); 553 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 554 break; 555 } 556 } 557 558 void 559 sk_marv_miibus_statchg(dev) 560 struct device *dev; 561 { 562 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 563 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 564 } 565 566 #define SK_BITS 6 567 #define SK_POLY 0xEDB88320 568 569 u_int32_t 570 sk_calchash(caddr_t addr) 571 { 572 u_int32_t crc; 573 574 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 575 crc = ~crc & ((1<< SK_BITS) - 1); 576 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 577 return (crc); 578 } 579 580 void 581 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 582 { 583 int base = XM_RXFILT_ENTRY(slot); 584 585 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 586 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 587 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 588 } 589 590 void 591 sk_setmulti(struct sk_if_softc *sc_if) 592 { 593 struct sk_softc *sc = sc_if->sk_softc; 594 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 595 u_int32_t hashes[2] = { 0, 0 }; 596 int h, i; 597 struct ethercom *ec = &sc_if->sk_ethercom; 598 struct ether_multi *enm; 599 struct ether_multistep step; 600 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 601 602 /* First, zot all the existing filters. */ 603 switch(sc->sk_type) { 604 case SK_GENESIS: 605 for (i = 1; i < XM_RXFILT_MAX; i++) 606 sk_setfilt(sc_if, (caddr_t)&dummy, i); 607 608 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 609 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 610 break; 611 case SK_YUKON: 612 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 613 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 614 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 615 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 616 break; 617 } 618 619 /* Now program new ones. */ 620 allmulti: 621 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 622 hashes[0] = 0xFFFFFFFF; 623 hashes[1] = 0xFFFFFFFF; 624 } else { 625 i = 1; 626 /* First find the tail of the list. */ 627 ETHER_FIRST_MULTI(step, ec, enm); 628 while (enm != NULL) { 629 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 630 ETHER_ADDR_LEN)) { 631 ifp->if_flags |= IFF_ALLMULTI; 632 goto allmulti; 633 } 634 DPRINTFN(2,("multicast address %s\n", 635 ether_sprintf(enm->enm_addrlo))); 636 /* 637 * Program the first XM_RXFILT_MAX multicast groups 638 * into the perfect filter. For all others, 639 * use the hash table. 640 */ 641 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 642 sk_setfilt(sc_if, enm->enm_addrlo, i); 643 i++; 644 } 645 else { 646 h = sk_calchash(enm->enm_addrlo); 647 if (h < 32) 648 hashes[0] |= (1 << h); 649 else 650 hashes[1] |= (1 << (h - 32)); 651 } 652 653 ETHER_NEXT_MULTI(step, enm); 654 } 655 } 656 657 switch(sc->sk_type) { 658 case SK_GENESIS: 659 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 660 XM_MODE_RX_USE_PERFECT); 661 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 662 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 663 break; 664 case SK_YUKON: 665 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 666 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 667 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 668 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 669 break; 670 } 671 } 672 673 int 674 sk_init_rx_ring(struct sk_if_softc *sc_if) 675 { 676 struct sk_chain_data *cd = &sc_if->sk_cdata; 677 struct sk_ring_data *rd = sc_if->sk_rdata; 678 int i; 679 680 bzero((char *)rd->sk_rx_ring, 681 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 682 683 for (i = 0; i < SK_RX_RING_CNT; i++) { 684 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 685 if (i == (SK_RX_RING_CNT - 1)) { 686 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 687 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if, 0); 688 } else { 689 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 690 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if,i+1); 691 } 692 } 693 694 for (i = 0; i < SK_RX_RING_CNT; i++) { 695 if (sk_newbuf(sc_if, i, NULL, NULL) == ENOBUFS) { 696 printf("%s: failed alloc of %dth mbuf\n", 697 sc_if->sk_dev.dv_xname, i); 698 return(ENOBUFS); 699 } 700 } 701 sc_if->sk_cdata.sk_rx_prod = 0; 702 sc_if->sk_cdata.sk_rx_cons = 0; 703 704 return(0); 705 } 706 707 int 708 sk_init_tx_ring(struct sk_if_softc *sc_if) 709 { 710 struct sk_softc *sc = sc_if->sk_softc; 711 struct sk_chain_data *cd = &sc_if->sk_cdata; 712 struct sk_ring_data *rd = sc_if->sk_rdata; 713 bus_dmamap_t dmamap; 714 struct sk_txmap_entry *entry; 715 int i; 716 717 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 718 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 719 720 SLIST_INIT(&sc_if->sk_txmap_listhead); 721 for (i = 0; i < SK_TX_RING_CNT; i++) { 722 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 723 if (i == (SK_TX_RING_CNT - 1)) { 724 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 725 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if, 0); 726 } else { 727 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 728 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if,i+1); 729 } 730 731 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, SK_NTXSEG, 732 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap)) 733 return (ENOBUFS); 734 735 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 736 if (!entry) { 737 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 738 return (ENOBUFS); 739 } 740 entry->dmamap = dmamap; 741 SLIST_INSERT_HEAD(&sc_if->sk_txmap_listhead, entry, link); 742 } 743 744 sc_if->sk_cdata.sk_tx_prod = 0; 745 sc_if->sk_cdata.sk_tx_cons = 0; 746 sc_if->sk_cdata.sk_tx_cnt = 0; 747 748 return (0); 749 } 750 751 int 752 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 753 bus_dmamap_t dmamap) 754 { 755 struct sk_softc *sc = sc_if->sk_softc; 756 struct mbuf *m_new = NULL; 757 struct sk_chain *c; 758 struct sk_rx_desc *r; 759 760 if (dmamap == NULL) { 761 /* if (m) panic() */ 762 763 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, MCLBYTES, 764 0, BUS_DMA_NOWAIT, &dmamap)) { 765 printf("%s: can't create recv map\n", 766 sc_if->sk_dev.dv_xname); 767 return(ENOMEM); 768 } 769 } else if (m == NULL) 770 bus_dmamap_unload(sc->sc_dmatag, dmamap); 771 772 sc_if->sk_cdata.sk_rx_map[i] = dmamap; 773 774 if (m == NULL) { 775 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 776 if (m_new == NULL) { 777 printf("%s: no memory for rx list -- " 778 "packet dropped!\n", sc_if->sk_dev.dv_xname); 779 return(ENOBUFS); 780 } 781 782 /* Allocate the jumbo buffer */ 783 MCLGET(m_new, M_DONTWAIT); 784 if (!(m_new->m_flags & M_EXT)) { 785 m_freem(m_new); 786 return (ENOBUFS); 787 } 788 789 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 790 791 m_adj(m_new, ETHER_ALIGN); 792 793 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m_new, 794 BUS_DMA_NOWAIT)) 795 return(ENOBUFS); 796 } else { 797 /* 798 * We're re-using a previously allocated mbuf; 799 * be sure to re-init pointers and lengths to 800 * default values. 801 */ 802 m_new = m; 803 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 804 m_adj(m_new, ETHER_ALIGN); 805 m_new->m_data = m_new->m_ext.ext_buf; 806 } 807 808 c = &sc_if->sk_cdata.sk_rx_chain[i]; 809 r = c->sk_desc; 810 c->sk_mbuf = m_new; 811 r->sk_data_lo = dmamap->dm_segs[0].ds_addr; 812 r->sk_ctl = dmamap->dm_segs[0].ds_len | SK_RXSTAT; 813 814 return(0); 815 } 816 817 /* 818 * Set media options. 819 */ 820 int 821 sk_ifmedia_upd(struct ifnet *ifp) 822 { 823 struct sk_if_softc *sc_if = ifp->if_softc; 824 825 (void) sk_init(ifp); 826 mii_mediachg(&sc_if->sk_mii); 827 return(0); 828 } 829 830 /* 831 * Report current media status. 832 */ 833 void 834 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 835 { 836 struct sk_if_softc *sc_if = ifp->if_softc; 837 838 mii_pollstat(&sc_if->sk_mii); 839 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 840 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 841 } 842 843 int 844 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 845 { 846 struct sk_if_softc *sc_if = ifp->if_softc; 847 struct sk_softc *sc = sc_if->sk_softc; 848 struct ifreq *ifr = (struct ifreq *) data; 849 /* struct ifaddr *ifa = (struct ifaddr *) data; */ 850 struct mii_data *mii; 851 int s, error = 0; 852 853 /* DPRINTFN(2, ("sk_ioctl\n")); */ 854 855 s = splnet(); 856 857 switch(command) { 858 859 case SIOCSIFFLAGS: 860 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 861 if (ifp->if_flags & IFF_UP) { 862 if (ifp->if_flags & IFF_RUNNING && 863 ifp->if_flags & IFF_PROMISC && 864 !(sc_if->sk_if_flags & IFF_PROMISC)) { 865 switch(sc->sk_type) { 866 case SK_GENESIS: 867 SK_XM_SETBIT_4(sc_if, XM_MODE, 868 XM_MODE_RX_PROMISC); 869 break; 870 case SK_YUKON: 871 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 872 YU_RCR_UFLEN | YU_RCR_MUFLEN); 873 break; 874 } 875 sk_setmulti(sc_if); 876 } else if (ifp->if_flags & IFF_RUNNING && 877 !(ifp->if_flags & IFF_PROMISC) && 878 sc_if->sk_if_flags & IFF_PROMISC) { 879 switch(sc->sk_type) { 880 case SK_GENESIS: 881 SK_XM_CLRBIT_4(sc_if, XM_MODE, 882 XM_MODE_RX_PROMISC); 883 break; 884 case SK_YUKON: 885 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 886 YU_RCR_UFLEN | YU_RCR_MUFLEN); 887 break; 888 } 889 890 sk_setmulti(sc_if); 891 } else 892 (void) sk_init(ifp); 893 } else { 894 if (ifp->if_flags & IFF_RUNNING) 895 sk_stop(ifp,0); 896 } 897 sc_if->sk_if_flags = ifp->if_flags; 898 error = 0; 899 break; 900 901 case SIOCGIFMEDIA: 902 case SIOCSIFMEDIA: 903 DPRINTFN(2, ("sk_ioctl MEDIA\n")); 904 mii = &sc_if->sk_mii; 905 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 906 break; 907 default: 908 DPRINTFN(2, ("sk_ioctl ETHER\n")); 909 error = ether_ioctl(ifp, command, data); 910 911 if ( error == ENETRESET) { 912 sk_setmulti(sc_if); 913 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 914 error = 0; 915 } else if ( error ) { 916 splx(s); 917 return error; 918 } 919 break; 920 } 921 922 splx(s); 923 return(error); 924 } 925 926 /* 927 * Lookup: Check the PCI vendor and device, and return a pointer to 928 * The structure if the IDs match against our list. 929 */ 930 931 static const struct sk_product * 932 sk_lookup(const struct pci_attach_args *pa) 933 { 934 const struct sk_product *psk; 935 936 for ( psk = &sk_products[0]; psk->sk_vendor != NULL; psk++ ) { 937 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 938 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 939 return (psk); 940 } 941 return (NULL); 942 } 943 944 /* 945 * Probe for a SysKonnect GEnesis chip. 946 */ 947 948 int 949 skc_probe(struct device *parent, struct cfdata *match, void *aux) 950 { 951 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 952 const struct sk_product *psk; 953 954 if ((psk = sk_lookup(pa))) { 955 return(1); 956 } 957 return(0); 958 } 959 960 /* 961 * Force the GEnesis into reset, then bring it out of reset. 962 */ 963 void sk_reset(struct sk_softc *sc) 964 { 965 DPRINTFN(2, ("sk_reset\n")); 966 967 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 968 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 969 if (sc->sk_type == SK_YUKON) 970 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 971 972 DELAY(1000); 973 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 974 DELAY(2); 975 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 976 if (sc->sk_type == SK_YUKON) 977 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 978 979 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 980 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 981 CSR_READ_2(sc, SK_LINK_CTRL))); 982 983 if (sc->sk_type == SK_GENESIS) { 984 /* Configure packet arbiter */ 985 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 986 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 987 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 988 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 989 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 990 } 991 992 /* Enable RAM interface */ 993 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 994 995 /* 996 * Configure interrupt moderation. The moderation timer 997 * defers interrupts specified in the interrupt moderation 998 * timer mask based on the timeout specified in the interrupt 999 * moderation timer init register. Each bit in the timer 1000 * register represents 18.825ns, so to specify a timeout in 1001 * microseconds, we have to multiply by 54. 1002 */ 1003 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200)); 1004 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 1005 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 1006 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 1007 } 1008 1009 int 1010 sk_probe(struct device *parent, struct cfdata *match, void *aux) 1011 { 1012 struct skc_attach_args *sa = aux; 1013 1014 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1015 return(0); 1016 1017 return (1); 1018 } 1019 1020 /* 1021 * Each XMAC chip is attached as a separate logical IP interface. 1022 * Single port cards will have only one logical interface of course. 1023 */ 1024 void 1025 sk_attach(struct device *parent, struct device *self, void *aux) 1026 { 1027 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1028 struct sk_softc *sc = (struct sk_softc *)parent; 1029 struct skc_attach_args *sa = aux; 1030 struct ifnet *ifp; 1031 caddr_t kva; 1032 bus_dma_segment_t seg; 1033 int i, rseg; 1034 1035 sc_if->sk_port = sa->skc_port; 1036 sc_if->sk_softc = sc; 1037 sc->sk_if[sa->skc_port] = sc_if; 1038 1039 if (sa->skc_port == SK_PORT_A) 1040 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1041 if (sa->skc_port == SK_PORT_B) 1042 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1043 1044 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1045 1046 /* 1047 * Get station address for this interface. Note that 1048 * dual port cards actually come with three station 1049 * addresses: one for each port, plus an extra. The 1050 * extra one is used by the SysKonnect driver software 1051 * as a 'virtual' station address for when both ports 1052 * are operating in failover mode. Currently we don't 1053 * use this extra address. 1054 */ 1055 for (i = 0; i < ETHER_ADDR_LEN; i++) 1056 sc_if->sk_enaddr[i] = 1057 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1058 1059 1060 printf(": Ethernet address %s\n", 1061 ether_sprintf(sc_if->sk_enaddr)); 1062 1063 /* 1064 * Set up RAM buffer addresses. The NIC will have a certain 1065 * amount of SRAM on it, somewhere between 512K and 2MB. We 1066 * need to divide this up a) between the transmitter and 1067 * receiver and b) between the two XMACs, if this is a 1068 * dual port NIC. Our algotithm is to divide up the memory 1069 * evenly so that everyone gets a fair share. 1070 */ 1071 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1072 u_int32_t chunk, val; 1073 1074 chunk = sc->sk_ramsize / 2; 1075 val = sc->sk_rboff / sizeof(u_int64_t); 1076 sc_if->sk_rx_ramstart = val; 1077 val += (chunk / sizeof(u_int64_t)); 1078 sc_if->sk_rx_ramend = val - 1; 1079 sc_if->sk_tx_ramstart = val; 1080 val += (chunk / sizeof(u_int64_t)); 1081 sc_if->sk_tx_ramend = val - 1; 1082 } else { 1083 u_int32_t chunk, val; 1084 1085 chunk = sc->sk_ramsize / 4; 1086 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1087 sizeof(u_int64_t); 1088 sc_if->sk_rx_ramstart = val; 1089 val += (chunk / sizeof(u_int64_t)); 1090 sc_if->sk_rx_ramend = val - 1; 1091 sc_if->sk_tx_ramstart = val; 1092 val += (chunk / sizeof(u_int64_t)); 1093 sc_if->sk_tx_ramend = val - 1; 1094 } 1095 1096 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1097 " tx_ramstart=%#x tx_ramend=%#x\n", 1098 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1099 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1100 1101 /* Read and save PHY type and set PHY address */ 1102 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1103 switch (sc_if->sk_phytype) { 1104 case SK_PHYTYPE_XMAC: 1105 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1106 break; 1107 case SK_PHYTYPE_BCOM: 1108 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1109 break; 1110 case SK_PHYTYPE_MARV_COPPER: 1111 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1112 break; 1113 default: 1114 printf("%s: unsupported PHY type: %d\n", 1115 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1116 return; 1117 } 1118 1119 /* Allocate the descriptor queues. */ 1120 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1121 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1122 printf("%s: can't alloc rx buffers\n", sc->sk_dev.dv_xname); 1123 goto fail; 1124 } 1125 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1126 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1127 printf("%s: can't map dma buffers (%lu bytes)\n", 1128 sc_if->sk_dev.dv_xname, 1129 (u_long) sizeof(struct sk_ring_data)); 1130 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1131 goto fail; 1132 } 1133 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1134 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1135 &sc_if->sk_ring_map)) { 1136 printf("%s: can't create dma map\n", sc_if->sk_dev.dv_xname); 1137 bus_dmamem_unmap(sc->sc_dmatag, kva, 1138 sizeof(struct sk_ring_data)); 1139 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1140 goto fail; 1141 } 1142 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1143 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1144 printf("%s: can't load dma map\n", sc_if->sk_dev.dv_xname); 1145 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1146 bus_dmamem_unmap(sc->sc_dmatag, kva, 1147 sizeof(struct sk_ring_data)); 1148 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1149 goto fail; 1150 } 1151 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1152 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1153 1154 ifp = &sc_if->sk_ethercom.ec_if; 1155 ifp->if_softc = sc_if; 1156 ifp->if_mtu = ETHERMTU; 1157 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1158 ifp->if_ioctl = sk_ioctl; 1159 ifp->if_start = sk_start; 1160 ifp->if_stop = sk_stop; 1161 ifp->if_init = sk_init; 1162 ifp->if_watchdog = sk_watchdog; 1163 ifp->if_baudrate = 1000000000; 1164 ifp->if_capabilities |= ETHERCAP_VLAN_MTU; 1165 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1166 IFQ_SET_READY(&ifp->if_snd); 1167 bcopy(sc_if->sk_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 1168 1169 /* 1170 * Do miibus setup. 1171 */ 1172 switch (sc->sk_type) { 1173 case SK_GENESIS: 1174 sk_init_xmac(sc_if); 1175 break; 1176 case SK_YUKON: 1177 sk_init_yukon(sc_if); 1178 break; 1179 default: 1180 panic("%s: unknown device type %d", sc->sk_dev.dv_xname, 1181 sc->sk_type); 1182 } 1183 1184 DPRINTFN(2, ("sk_attach: 1\n")); 1185 1186 sc_if->sk_mii.mii_ifp = ifp; 1187 switch (sc->sk_type) { 1188 case SK_GENESIS: 1189 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1190 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1191 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1192 break; 1193 case SK_YUKON: 1194 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1195 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1196 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1197 break; 1198 } 1199 1200 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1201 sk_ifmedia_upd, sk_ifmedia_sts); 1202 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1203 MII_OFFSET_ANY, 0); 1204 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1205 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1206 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1207 0, NULL); 1208 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1209 } 1210 else 1211 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1212 1213 callout_init(&sc_if->sk_tick_ch); 1214 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1215 1216 DPRINTFN(2, ("sk_attach: 1\n")); 1217 1218 /* 1219 * Call MI attach routines. 1220 */ 1221 if_attach(ifp); 1222 1223 ether_ifattach(ifp, sc_if->sk_enaddr); 1224 1225 #if NRND > 0 1226 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1227 RND_TYPE_NET, 0); 1228 #endif 1229 1230 DPRINTFN(2, ("sk_attach: end\n")); 1231 1232 return; 1233 1234 fail: 1235 sc->sk_if[sa->skc_port] = NULL; 1236 } 1237 1238 int 1239 skcprint(void *aux, const char *pnp) 1240 { 1241 struct skc_attach_args *sa = aux; 1242 1243 if (pnp) 1244 printf("sk port %c at %s", 1245 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1246 else 1247 printf(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1248 return (UNCONF); 1249 } 1250 1251 /* 1252 * Attach the interface. Allocate softc structures, do ifmedia 1253 * setup and ethernet/BPF attach. 1254 */ 1255 void 1256 skc_attach(struct device *parent, struct device *self, void *aux) 1257 { 1258 struct sk_softc *sc = (struct sk_softc *)self; 1259 struct pci_attach_args *pa = aux; 1260 struct skc_attach_args skca; 1261 pci_chipset_tag_t pc = pa->pa_pc; 1262 pcireg_t memtype; 1263 pci_intr_handle_t ih; 1264 const char *intrstr = NULL; 1265 bus_addr_t iobase; 1266 bus_size_t iosize; 1267 int s; 1268 u_int32_t command; 1269 1270 DPRINTFN(2, ("begin skc_attach\n")); 1271 1272 s = splnet(); 1273 1274 /* 1275 * Handle power management nonsense. 1276 */ 1277 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1278 1279 if (command == 0x01) { 1280 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1281 if (command & SK_PSTATE_MASK) { 1282 u_int32_t iobase, membase, irq; 1283 1284 /* Save important PCI config data. */ 1285 iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1286 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1287 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1288 1289 /* Reset the power state. */ 1290 printf("%s chip is in D%d power mode " 1291 "-- setting to D0\n", sc->sk_dev.dv_xname, 1292 command & SK_PSTATE_MASK); 1293 command &= 0xFFFFFFFC; 1294 pci_conf_write(pc, pa->pa_tag, 1295 SK_PCI_PWRMGMTCTRL, command); 1296 1297 /* Restore PCI config data. */ 1298 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase); 1299 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1300 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1301 } 1302 } 1303 1304 /* 1305 * Map control/status registers. 1306 */ 1307 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1308 command |= PCI_COMMAND_IO_ENABLE | 1309 PCI_COMMAND_MEM_ENABLE | 1310 PCI_COMMAND_MASTER_ENABLE; 1311 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1312 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1313 1314 switch (PCI_PRODUCT(pa->pa_id)) { 1315 case PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE: 1316 sc->sk_type = SK_GENESIS; 1317 break; 1318 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1319 case PCI_PRODUCT_3COM_3C940: 1320 sc->sk_type = SK_YUKON; 1321 break; 1322 default: 1323 printf(": unknown device!\n"); 1324 goto fail; 1325 } 1326 1327 #ifdef SK_USEIOSPACE 1328 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1329 printf(": failed to enable I/O ports!\n"); 1330 goto fail; 1331 } 1332 /* 1333 * Map control/status registers. 1334 */ 1335 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1336 &iobase, &iosize)) { 1337 printf(": can't find i/o space\n"); 1338 goto fail; 1339 } 1340 #else 1341 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1342 printf(": failed to enable memory mapping!\n"); 1343 goto fail; 1344 } 1345 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1346 switch (memtype) { 1347 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1348 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1349 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1350 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1351 &iobase, &iosize) == 0) 1352 break; 1353 default: 1354 printf("%s: can't find mem space\n", 1355 sc->sk_dev.dv_xname); 1356 return; 1357 } 1358 1359 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1360 #endif 1361 sc->sc_dmatag = pa->pa_dmat; 1362 1363 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1364 1365 /* Allocate interrupt */ 1366 if (pci_intr_map(pa, &ih)) { 1367 printf(": couldn't map interrupt\n"); 1368 goto fail; 1369 } 1370 1371 intrstr = pci_intr_string(pc, ih); 1372 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1373 if (sc->sk_intrhand == NULL) { 1374 printf(": couldn't establish interrupt"); 1375 if (intrstr != NULL) 1376 printf(" at %s", intrstr); 1377 goto fail; 1378 } 1379 printf(": %s\n", intrstr); 1380 1381 /* Reset the adapter. */ 1382 sk_reset(sc); 1383 1384 /* Read and save vital product data from EEPROM. */ 1385 sk_vpd_read(sc); 1386 1387 if (sc->sk_type == SK_GENESIS) { 1388 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1389 /* Read and save RAM size and RAMbuffer offset */ 1390 switch(val) { 1391 case SK_RAMSIZE_512K_64: 1392 sc->sk_ramsize = 0x80000; 1393 sc->sk_rboff = SK_RBOFF_0; 1394 break; 1395 case SK_RAMSIZE_1024K_64: 1396 sc->sk_ramsize = 0x100000; 1397 sc->sk_rboff = SK_RBOFF_80000; 1398 break; 1399 case SK_RAMSIZE_1024K_128: 1400 sc->sk_ramsize = 0x100000; 1401 sc->sk_rboff = SK_RBOFF_0; 1402 break; 1403 case SK_RAMSIZE_2048K_128: 1404 sc->sk_ramsize = 0x200000; 1405 sc->sk_rboff = SK_RBOFF_0; 1406 break; 1407 default: 1408 printf("%s: unknown ram size: %d\n", 1409 sc->sk_dev.dv_xname, val); 1410 goto fail; 1411 break; 1412 } 1413 1414 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1415 sc->sk_ramsize, sc->sk_ramsize / 1024, 1416 sc->sk_rboff)); 1417 } else { 1418 sc->sk_ramsize = 0x20000; 1419 sc->sk_rboff = SK_RBOFF_0; 1420 1421 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1422 sc->sk_ramsize / 1024, sc->sk_ramsize, 1423 sc->sk_rboff)); 1424 } 1425 1426 /* Read and save physical media type */ 1427 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1428 case SK_PMD_1000BASESX: 1429 sc->sk_pmd = IFM_1000_SX; 1430 break; 1431 case SK_PMD_1000BASELX: 1432 sc->sk_pmd = IFM_1000_LX; 1433 break; 1434 case SK_PMD_1000BASECX: 1435 sc->sk_pmd = IFM_1000_CX; 1436 break; 1437 case SK_PMD_1000BASETX: 1438 sc->sk_pmd = IFM_1000_T; 1439 break; 1440 default: 1441 printf("%s: unknown media type: 0x%x\n", 1442 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1443 goto fail; 1444 } 1445 1446 /* Announce the product name. */ 1447 printf("%s: %s\n", sc->sk_dev.dv_xname, sc->sk_vpd_prodname); 1448 1449 skca.skc_port = SK_PORT_A; 1450 (void)config_found(&sc->sk_dev, &skca, skcprint); 1451 1452 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1453 skca.skc_port = SK_PORT_B; 1454 (void)config_found(&sc->sk_dev, &skca, skcprint); 1455 } 1456 1457 /* Turn on the 'driver is loaded' LED. */ 1458 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1459 1460 fail: 1461 splx(s); 1462 } 1463 1464 int 1465 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1466 { 1467 struct sk_softc *sc = sc_if->sk_softc; 1468 struct sk_tx_desc *f = NULL; 1469 u_int32_t frag, cur, cnt = 0; 1470 int i; 1471 struct sk_txmap_entry *entry; 1472 bus_dmamap_t txmap; 1473 1474 DPRINTFN(3, ("sk_encap\n")); 1475 1476 entry = SLIST_FIRST(&sc_if->sk_txmap_listhead); 1477 if (entry == NULL) { 1478 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1479 return ENOBUFS; 1480 } 1481 txmap = entry->dmamap; 1482 1483 cur = frag = *txidx; 1484 1485 #ifdef SK_DEBUG 1486 if (skdebug >= 3) 1487 sk_dump_mbuf(m_head); 1488 #endif 1489 1490 /* 1491 * Start packing the mbufs in this chain into 1492 * the fragment pointers. Stop when we run out 1493 * of fragments or hit the end of the mbuf chain. 1494 */ 1495 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1496 BUS_DMA_NOWAIT)) { 1497 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1498 return(ENOBUFS); 1499 } 1500 1501 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1502 1503 for (i = 0; i < txmap->dm_nsegs; i++) { 1504 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1505 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1506 return(ENOBUFS); 1507 } 1508 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1509 f->sk_data_lo = txmap->dm_segs[i].ds_addr; 1510 f->sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1511 if (cnt == 0) 1512 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1513 else 1514 f->sk_ctl |= SK_TXCTL_OWN; 1515 1516 cur = frag; 1517 SK_INC(frag, SK_TX_RING_CNT); 1518 cnt++; 1519 } 1520 1521 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1522 SLIST_REMOVE_HEAD(&sc_if->sk_txmap_listhead, link); 1523 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1524 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1525 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1526 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1527 sc_if->sk_cdata.sk_tx_cnt += cnt; 1528 1529 #ifdef SK_DEBUG 1530 if (skdebug >= 3) { 1531 struct sk_tx_desc *desc; 1532 u_int32_t idx; 1533 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1534 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1535 sk_dump_txdesc(desc, idx); 1536 } 1537 } 1538 #endif 1539 1540 *txidx = frag; 1541 1542 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1543 1544 return(0); 1545 } 1546 1547 void 1548 sk_start(struct ifnet *ifp) 1549 { 1550 struct sk_if_softc *sc_if = ifp->if_softc; 1551 struct sk_softc *sc = sc_if->sk_softc; 1552 struct mbuf *m_head = NULL; 1553 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1554 int pkts = 0; 1555 1556 DPRINTFN(3, ("sk_start\n")); 1557 1558 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1559 IFQ_POLL(&ifp->if_snd, m_head); 1560 if (m_head == NULL) 1561 break; 1562 1563 /* 1564 * Pack the data into the transmit ring. If we 1565 * don't have room, set the OACTIVE flag and wait 1566 * for the NIC to drain the ring. 1567 */ 1568 if (sk_encap(sc_if, m_head, &idx)) { 1569 ifp->if_flags |= IFF_OACTIVE; 1570 break; 1571 } 1572 1573 /* now we are committed to transmit the packet */ 1574 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1575 pkts++; 1576 1577 /* 1578 * If there's a BPF listener, bounce a copy of this frame 1579 * to him. 1580 */ 1581 #if NBPFILTER > 0 1582 if (ifp->if_bpf) 1583 bpf_mtap(ifp->if_bpf, m_head); 1584 #endif 1585 } 1586 if (pkts == 0) 1587 return; 1588 1589 /* Transmit */ 1590 sc_if->sk_cdata.sk_tx_prod = idx; 1591 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1592 1593 /* Set a timeout in case the chip goes out to lunch. */ 1594 ifp->if_timer = 5; 1595 } 1596 1597 1598 void 1599 sk_watchdog(struct ifnet *ifp) 1600 { 1601 struct sk_if_softc *sc_if = ifp->if_softc; 1602 1603 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1604 (void) sk_init(ifp); 1605 } 1606 1607 void 1608 sk_shutdown(void * v) 1609 { 1610 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 1611 struct sk_softc *sc = sc_if->sk_softc; 1612 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1613 1614 DPRINTFN(2, ("sk_shutdown\n")); 1615 sk_stop(ifp,1); 1616 1617 /* Turn off the 'driver is loaded' LED. */ 1618 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1619 1620 /* 1621 * Reset the GEnesis controller. Doing this should also 1622 * assert the resets on the attached XMAC(s). 1623 */ 1624 sk_reset(sc); 1625 } 1626 1627 void 1628 sk_rxeof(struct sk_if_softc *sc_if) 1629 { 1630 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1631 struct mbuf *m; 1632 struct sk_chain *cur_rx; 1633 struct sk_rx_desc *cur_desc; 1634 int i, cur, total_len = 0; 1635 u_int32_t rxstat; 1636 bus_dmamap_t dmamap; 1637 1638 DPRINTFN(3, ("sk_rxeof\n")); 1639 1640 i = sc_if->sk_cdata.sk_rx_prod; 1641 1642 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) { 1643 cur = i; 1644 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1645 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 1646 1647 rxstat = cur_desc->sk_xmac_rxstat; 1648 m = cur_rx->sk_mbuf; 1649 cur_rx->sk_mbuf = NULL; 1650 total_len = SK_RXBYTES(cur_desc->sk_ctl); 1651 1652 dmamap = sc_if->sk_cdata.sk_rx_map[cur]; 1653 sc_if->sk_cdata.sk_rx_map[cur] = 0; 1654 1655 SK_INC(i, SK_RX_RING_CNT); 1656 1657 if (rxstat & XM_RXSTAT_ERRFRAME) { 1658 ifp->if_ierrors++; 1659 sk_newbuf(sc_if, cur, m, dmamap); 1660 continue; 1661 } 1662 1663 /* 1664 * Try to allocate a new jumbo buffer. If that 1665 * fails, copy the packet to mbufs and put the 1666 * jumbo buffer back in the ring so it can be 1667 * re-used. If allocating mbufs fails, then we 1668 * have to drop the packet. 1669 */ 1670 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1671 struct mbuf *m0; 1672 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1673 total_len + ETHER_ALIGN, 0, ifp, NULL); 1674 sk_newbuf(sc_if, cur, m, dmamap); 1675 if (m0 == NULL) { 1676 printf("%s: no receive buffers " 1677 "available -- packet dropped!\n", 1678 sc_if->sk_dev.dv_xname); 1679 ifp->if_ierrors++; 1680 continue; 1681 } 1682 m_adj(m0, ETHER_ALIGN); 1683 m = m0; 1684 } else { 1685 m->m_pkthdr.rcvif = ifp; 1686 m->m_pkthdr.len = m->m_len = total_len; 1687 } 1688 1689 ifp->if_ipackets++; 1690 1691 #if NBPFILTER > 0 1692 if (ifp->if_bpf) 1693 bpf_mtap(ifp->if_bpf, m); 1694 #endif 1695 /* pass it on. */ 1696 (*ifp->if_input)(ifp, m); 1697 } 1698 1699 sc_if->sk_cdata.sk_rx_prod = i; 1700 } 1701 1702 void 1703 sk_txeof(struct sk_if_softc *sc_if) 1704 { 1705 struct sk_softc *sc = sc_if->sk_softc; 1706 struct sk_tx_desc *cur_tx = NULL; 1707 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1708 u_int32_t idx; 1709 struct sk_txmap_entry *entry; 1710 1711 DPRINTFN(3, ("sk_txeof\n")); 1712 1713 /* 1714 * Go through our tx ring and free mbufs for those 1715 * frames that have been sent. 1716 */ 1717 idx = sc_if->sk_cdata.sk_tx_cons; 1718 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1719 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1720 #ifdef SK_DEBUG 1721 if (skdebug >= 3) 1722 sk_dump_txdesc(cur_tx, idx); 1723 #endif 1724 if (cur_tx->sk_ctl & SK_TXCTL_OWN) 1725 break; 1726 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1727 ifp->if_opackets++; 1728 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1729 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1730 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1731 1732 entry = sc_if->sk_cdata.sk_tx_map[idx]; 1733 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 1734 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1735 1736 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 1737 SLIST_INSERT_HEAD(&sc_if->sk_txmap_listhead, entry, 1738 link); 1739 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 1740 } 1741 sc_if->sk_cdata.sk_tx_cnt--; 1742 SK_INC(idx, SK_TX_RING_CNT); 1743 ifp->if_timer = 0; 1744 } 1745 1746 sc_if->sk_cdata.sk_tx_cons = idx; 1747 1748 if (cur_tx != NULL) 1749 ifp->if_flags &= ~IFF_OACTIVE; 1750 } 1751 1752 void 1753 sk_tick(void *xsc_if) 1754 { 1755 struct sk_if_softc *sc_if = xsc_if; 1756 struct mii_data *mii = &sc_if->sk_mii; 1757 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1758 int i; 1759 1760 DPRINTFN(3, ("sk_tick\n")); 1761 1762 if (!(ifp->if_flags & IFF_UP)) 1763 return; 1764 1765 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1766 sk_intr_bcom(sc_if); 1767 return; 1768 } 1769 1770 /* 1771 * According to SysKonnect, the correct way to verify that 1772 * the link has come back up is to poll bit 0 of the GPIO 1773 * register three times. This pin has the signal from the 1774 * link sync pin connected to it; if we read the same link 1775 * state 3 times in a row, we know the link is up. 1776 */ 1777 for (i = 0; i < 3; i++) { 1778 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 1779 break; 1780 } 1781 1782 if (i != 3) { 1783 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 1784 return; 1785 } 1786 1787 /* Turn the GP0 interrupt back on. */ 1788 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1789 SK_XM_READ_2(sc_if, XM_ISR); 1790 mii_tick(mii); 1791 mii_pollstat(mii); 1792 callout_stop(&sc_if->sk_tick_ch); 1793 } 1794 1795 void 1796 sk_intr_bcom(struct sk_if_softc *sc_if) 1797 { 1798 struct mii_data *mii = &sc_if->sk_mii; 1799 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1800 int status; 1801 1802 1803 DPRINTFN(3, ("sk_intr_bcom\n")); 1804 1805 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1806 1807 /* 1808 * Read the PHY interrupt register to make sure 1809 * we clear any pending interrupts. 1810 */ 1811 status = sk_xmac_miibus_readreg((struct device *)sc_if, 1812 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 1813 1814 if (!(ifp->if_flags & IFF_RUNNING)) { 1815 sk_init_xmac(sc_if); 1816 return; 1817 } 1818 1819 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 1820 int lstat; 1821 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 1822 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 1823 1824 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 1825 mii_mediachg(mii); 1826 /* Turn off the link LED. */ 1827 SK_IF_WRITE_1(sc_if, 0, 1828 SK_LINKLED1_CTL, SK_LINKLED_OFF); 1829 sc_if->sk_link = 0; 1830 } else if (status & BRGPHY_ISR_LNK_CHG) { 1831 sk_xmac_miibus_writereg((struct device *)sc_if, 1832 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 1833 mii_tick(mii); 1834 sc_if->sk_link = 1; 1835 /* Turn on the link LED. */ 1836 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 1837 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 1838 SK_LINKLED_BLINK_OFF); 1839 mii_pollstat(mii); 1840 } else { 1841 mii_tick(mii); 1842 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 1843 } 1844 } 1845 1846 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 1847 } 1848 1849 void 1850 sk_intr_xmac(struct sk_if_softc *sc_if) 1851 { 1852 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 1853 1854 DPRINTFN(3, ("sk_intr_xmac\n")); 1855 1856 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 1857 if (status & XM_ISR_GP0_SET) { 1858 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 1859 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 1860 } 1861 1862 if (status & XM_ISR_AUTONEG_DONE) { 1863 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 1864 } 1865 } 1866 1867 if (status & XM_IMR_TX_UNDERRUN) 1868 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 1869 1870 if (status & XM_IMR_RX_OVERRUN) 1871 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 1872 } 1873 1874 void 1875 sk_intr_yukon(sc_if) 1876 struct sk_if_softc *sc_if; 1877 { 1878 int status; 1879 1880 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 1881 1882 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 1883 } 1884 1885 int 1886 sk_intr(void *xsc) 1887 { 1888 struct sk_softc *sc = xsc; 1889 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 1890 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 1891 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 1892 u_int32_t status; 1893 int claimed = 0; 1894 1895 if (sc_if0 != NULL) 1896 ifp0 = &sc_if0->sk_ethercom.ec_if; 1897 if (sc_if1 != NULL) 1898 ifp1 = &sc_if1->sk_ethercom.ec_if; 1899 1900 for (;;) { 1901 status = CSR_READ_4(sc, SK_ISSR); 1902 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 1903 1904 if (!(status & sc->sk_intrmask)) 1905 break; 1906 1907 claimed = 1; 1908 1909 /* Handle receive interrupts first. */ 1910 if (status & SK_ISR_RX1_EOF) { 1911 sk_rxeof(sc_if0); 1912 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 1913 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1914 } 1915 if (status & SK_ISR_RX2_EOF) { 1916 sk_rxeof(sc_if1); 1917 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 1918 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 1919 } 1920 1921 /* Then transmit interrupts. */ 1922 if (status & SK_ISR_TX1_S_EOF) { 1923 sk_txeof(sc_if0); 1924 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 1925 SK_TXBMU_CLR_IRQ_EOF); 1926 } 1927 if (status & SK_ISR_TX2_S_EOF) { 1928 sk_txeof(sc_if1); 1929 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 1930 SK_TXBMU_CLR_IRQ_EOF); 1931 } 1932 1933 /* Then MAC interrupts. */ 1934 if (status & SK_ISR_MAC1 && (ifp0->if_flags & IFF_RUNNING)) { 1935 if (sc->sk_type == SK_GENESIS) 1936 sk_intr_xmac(sc_if0); 1937 else 1938 sk_intr_yukon(sc_if0); 1939 } 1940 1941 if (status & SK_ISR_MAC2 && (ifp1->if_flags & IFF_RUNNING)) { 1942 if (sc->sk_type == SK_GENESIS) 1943 sk_intr_xmac(sc_if1); 1944 else 1945 sk_intr_yukon(sc_if1); 1946 1947 } 1948 1949 if (status & SK_ISR_EXTERNAL_REG) { 1950 if (ifp0 != NULL && 1951 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 1952 sk_intr_bcom(sc_if0); 1953 1954 if (ifp1 != NULL && 1955 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 1956 sk_intr_bcom(sc_if1); 1957 } 1958 } 1959 1960 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 1961 1962 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 1963 sk_start(ifp0); 1964 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 1965 sk_start(ifp1); 1966 1967 return (claimed); 1968 } 1969 1970 void 1971 sk_init_xmac(struct sk_if_softc *sc_if) 1972 { 1973 struct sk_softc *sc = sc_if->sk_softc; 1974 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1975 static const struct sk_bcom_hack bhack[] = { 1976 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 1977 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 1978 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 1979 { 0, 0 } }; 1980 1981 DPRINTFN(1, ("sk_init_xmac\n")); 1982 1983 /* Unreset the XMAC. */ 1984 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 1985 DELAY(1000); 1986 1987 /* Reset the XMAC's internal state. */ 1988 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 1989 1990 /* Save the XMAC II revision */ 1991 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 1992 1993 /* 1994 * Perform additional initialization for external PHYs, 1995 * namely for the 1000baseTX cards that use the XMAC's 1996 * GMII mode. 1997 */ 1998 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 1999 int i = 0; 2000 u_int32_t val; 2001 2002 /* Take PHY out of reset. */ 2003 val = sk_win_read_4(sc, SK_GPIO); 2004 if (sc_if->sk_port == SK_PORT_A) 2005 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2006 else 2007 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2008 sk_win_write_4(sc, SK_GPIO, val); 2009 2010 /* Enable GMII mode on the XMAC. */ 2011 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2012 2013 sk_xmac_miibus_writereg((struct device *)sc_if, 2014 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2015 DELAY(10000); 2016 sk_xmac_miibus_writereg((struct device *)sc_if, 2017 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2018 2019 /* 2020 * Early versions of the BCM5400 apparently have 2021 * a bug that requires them to have their reserved 2022 * registers initialized to some magic values. I don't 2023 * know what the numbers do, I'm just the messenger. 2024 */ 2025 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2026 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2027 while(bhack[i].reg) { 2028 sk_xmac_miibus_writereg((struct device *)sc_if, 2029 SK_PHYADDR_BCOM, bhack[i].reg, 2030 bhack[i].val); 2031 i++; 2032 } 2033 } 2034 } 2035 2036 /* Set station address */ 2037 SK_XM_WRITE_2(sc_if, XM_PAR0, 2038 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2039 SK_XM_WRITE_2(sc_if, XM_PAR1, 2040 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2041 SK_XM_WRITE_2(sc_if, XM_PAR2, 2042 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2043 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2044 2045 if (ifp->if_flags & IFF_PROMISC) { 2046 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2047 } else { 2048 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2049 } 2050 2051 if (ifp->if_flags & IFF_BROADCAST) { 2052 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2053 } else { 2054 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2055 } 2056 2057 /* We don't need the FCS appended to the packet. */ 2058 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2059 2060 /* We want short frames padded to 60 bytes. */ 2061 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2062 2063 /* 2064 * Enable the reception of all error frames. This is is 2065 * a necessary evil due to the design of the XMAC. The 2066 * XMAC's receive FIFO is only 8K in size, however jumbo 2067 * frames can be up to 9000 bytes in length. When bad 2068 * frame filtering is enabled, the XMAC's RX FIFO operates 2069 * in 'store and forward' mode. For this to work, the 2070 * entire frame has to fit into the FIFO, but that means 2071 * that jumbo frames larger than 8192 bytes will be 2072 * truncated. Disabling all bad frame filtering causes 2073 * the RX FIFO to operate in streaming mode, in which 2074 * case the XMAC will start transfering frames out of the 2075 * RX FIFO as soon as the FIFO threshold is reached. 2076 */ 2077 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2078 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2079 XM_MODE_RX_INRANGELEN); 2080 2081 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2082 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2083 else 2084 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2085 2086 /* 2087 * Bump up the transmit threshold. This helps hold off transmit 2088 * underruns when we're blasting traffic from both ports at once. 2089 */ 2090 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2091 2092 /* Set multicast filter */ 2093 sk_setmulti(sc_if); 2094 2095 /* Clear and enable interrupts */ 2096 SK_XM_READ_2(sc_if, XM_ISR); 2097 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2098 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2099 else 2100 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2101 2102 /* Configure MAC arbiter */ 2103 switch(sc_if->sk_xmac_rev) { 2104 case XM_XMAC_REV_B2: 2105 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2106 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2107 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2108 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2109 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2110 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2111 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2112 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2113 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2114 break; 2115 case XM_XMAC_REV_C1: 2116 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2117 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2118 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2119 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2120 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2121 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2122 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2123 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2124 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2125 break; 2126 default: 2127 break; 2128 } 2129 sk_win_write_2(sc, SK_MACARB_CTL, 2130 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2131 2132 sc_if->sk_link = 1; 2133 } 2134 2135 void sk_init_yukon(sc_if) 2136 struct sk_if_softc *sc_if; 2137 { 2138 u_int32_t /*mac, */phy; 2139 u_int16_t reg; 2140 int i; 2141 2142 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2143 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2144 2145 /* GMAC and GPHY Reset */ 2146 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2147 2148 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2149 2150 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2151 DELAY(1000); 2152 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2153 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2154 DELAY(1000); 2155 2156 2157 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2158 2159 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2160 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2161 2162 switch(sc_if->sk_softc->sk_pmd) { 2163 case IFM_1000_SX: 2164 case IFM_1000_LX: 2165 phy |= SK_GPHY_FIBER; 2166 break; 2167 2168 case IFM_1000_CX: 2169 case IFM_1000_T: 2170 phy |= SK_GPHY_COPPER; 2171 break; 2172 } 2173 2174 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2175 2176 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2177 DELAY(1000); 2178 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2179 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2180 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2181 2182 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2183 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2184 2185 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2186 2187 /* unused read of the interrupt source register */ 2188 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2189 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2190 2191 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2192 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2193 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2194 2195 /* MIB Counter Clear Mode set */ 2196 reg |= YU_PAR_MIB_CLR; 2197 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2198 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2199 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2200 2201 /* MIB Counter Clear Mode clear */ 2202 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2203 reg &= ~YU_PAR_MIB_CLR; 2204 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2205 2206 /* receive control reg */ 2207 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2208 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2209 YU_RCR_CRCR); 2210 2211 /* transmit parameter register */ 2212 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2213 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2214 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2215 2216 /* serial mode register */ 2217 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2218 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2219 YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e)); 2220 2221 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2222 /* Setup Yukon's address */ 2223 for (i = 0; i < 3; i++) { 2224 /* Write Source Address 1 (unicast filter) */ 2225 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2226 sc_if->sk_enaddr[i * 2] | 2227 sc_if->sk_enaddr[i * 2 + 1] << 8); 2228 } 2229 2230 for (i = 0; i < 3; i++) { 2231 reg = sk_win_read_2(sc_if->sk_softc, 2232 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2233 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2234 } 2235 2236 /* clear all Multicast filter hash registers */ 2237 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2238 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 2239 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 2240 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 2241 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 2242 2243 /* enable interrupt mask for counter overflows */ 2244 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2245 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2246 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2247 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2248 2249 /* Configure RX MAC FIFO */ 2250 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2251 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2252 2253 /* Configure TX MAC FIFO */ 2254 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2255 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2256 2257 DPRINTFN(6, ("sk_init_yukon: end\n")); 2258 } 2259 2260 /* 2261 * Note that to properly initialize any part of the GEnesis chip, 2262 * you first have to take it out of reset mode. 2263 */ 2264 int 2265 sk_init(struct ifnet *ifp) 2266 { 2267 struct sk_if_softc *sc_if = ifp->if_softc; 2268 struct sk_softc *sc = sc_if->sk_softc; 2269 struct mii_data *mii = &sc_if->sk_mii; 2270 int s; 2271 2272 DPRINTFN(1, ("sk_init\n")); 2273 2274 s = splnet(); 2275 2276 /* Cancel pending I/O and free all RX/TX buffers. */ 2277 sk_stop(ifp,0); 2278 2279 if (sc->sk_type == SK_GENESIS) { 2280 /* Configure LINK_SYNC LED */ 2281 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2282 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2283 SK_LINKLED_LINKSYNC_ON); 2284 2285 /* Configure RX LED */ 2286 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2287 SK_RXLEDCTL_COUNTER_START); 2288 2289 /* Configure TX LED */ 2290 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2291 SK_TXLEDCTL_COUNTER_START); 2292 } 2293 2294 /* Configure I2C registers */ 2295 2296 /* Configure XMAC(s) */ 2297 switch (sc->sk_type) { 2298 case SK_GENESIS: 2299 sk_init_xmac(sc_if); 2300 break; 2301 case SK_YUKON: 2302 sk_init_yukon(sc_if); 2303 break; 2304 } 2305 mii_mediachg(mii); 2306 2307 if (sc->sk_type == SK_GENESIS) { 2308 /* Configure MAC FIFOs */ 2309 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2310 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2311 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2312 2313 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2314 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2315 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2316 } 2317 2318 /* Configure transmit arbiter(s) */ 2319 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2320 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2321 2322 /* Configure RAMbuffers */ 2323 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2324 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2325 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2326 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2327 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2328 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2329 2330 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2331 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2332 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2333 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2334 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2335 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2336 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2337 2338 /* Configure BMUs */ 2339 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2340 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2341 SK_RX_RING_ADDR(sc_if, 0)); 2342 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2343 2344 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2345 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2346 SK_TX_RING_ADDR(sc_if, 0)); 2347 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2348 2349 /* Init descriptors */ 2350 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2351 printf("%s: initialization failed: no " 2352 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2353 sk_stop(ifp,0); 2354 splx(s); 2355 return(ENOBUFS); 2356 } 2357 2358 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2359 printf("%s: initialization failed: no " 2360 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2361 sk_stop(ifp,0); 2362 splx(s); 2363 return(ENOBUFS); 2364 } 2365 2366 /* Configure interrupt handling */ 2367 CSR_READ_4(sc, SK_ISSR); 2368 if (sc_if->sk_port == SK_PORT_A) 2369 sc->sk_intrmask |= SK_INTRS1; 2370 else 2371 sc->sk_intrmask |= SK_INTRS2; 2372 2373 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2374 2375 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2376 2377 /* Start BMUs. */ 2378 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2379 2380 if (sc->sk_type == SK_GENESIS) { 2381 /* Enable XMACs TX and RX state machines */ 2382 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2383 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2384 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2385 } 2386 2387 if (sc->sk_type == SK_YUKON) { 2388 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2389 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2390 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2391 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2392 } 2393 2394 2395 ifp->if_flags |= IFF_RUNNING; 2396 ifp->if_flags &= ~IFF_OACTIVE; 2397 2398 splx(s); 2399 return(0); 2400 } 2401 2402 void 2403 sk_stop(struct ifnet *ifp, int disable) 2404 { 2405 struct sk_if_softc *sc_if = ifp->if_softc; 2406 struct sk_softc *sc = sc_if->sk_softc; 2407 int i; 2408 2409 DPRINTFN(1, ("sk_stop\n")); 2410 2411 callout_stop(&sc_if->sk_tick_ch); 2412 2413 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2414 u_int32_t val; 2415 2416 /* Put PHY back into reset. */ 2417 val = sk_win_read_4(sc, SK_GPIO); 2418 if (sc_if->sk_port == SK_PORT_A) { 2419 val |= SK_GPIO_DIR0; 2420 val &= ~SK_GPIO_DAT0; 2421 } else { 2422 val |= SK_GPIO_DIR2; 2423 val &= ~SK_GPIO_DAT2; 2424 } 2425 sk_win_write_4(sc, SK_GPIO, val); 2426 } 2427 2428 /* Turn off various components of this interface. */ 2429 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2430 switch (sc->sk_type) { 2431 case SK_GENESIS: 2432 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2433 SK_TXMACCTL_XMAC_RESET); 2434 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2435 break; 2436 case SK_YUKON: 2437 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2438 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2439 break; 2440 } 2441 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2442 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2443 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2444 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2445 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2446 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2447 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2448 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2449 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2450 2451 /* Disable interrupts */ 2452 if (sc_if->sk_port == SK_PORT_A) 2453 sc->sk_intrmask &= ~SK_INTRS1; 2454 else 2455 sc->sk_intrmask &= ~SK_INTRS2; 2456 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2457 2458 SK_XM_READ_2(sc_if, XM_ISR); 2459 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2460 2461 /* Free RX and TX mbufs still in the queues. */ 2462 if ( disable ) { 2463 for (i = 0; i < SK_RX_RING_CNT; i++) { 2464 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2465 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2466 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2467 } 2468 } 2469 2470 for (i = 0; i < SK_TX_RING_CNT; i++) { 2471 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2472 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2473 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2474 } 2475 } 2476 } 2477 2478 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2479 } 2480 2481 CFATTACH_DECL(skc,sizeof(struct sk_softc), skc_probe, skc_attach, NULL, NULL); 2482 2483 /* 2484 struct cfdriver skc_cd = { 2485 0, "skc", DV_DULL 2486 }; 2487 */ 2488 2489 CFATTACH_DECL(sk,sizeof(struct sk_if_softc), sk_probe, sk_attach, NULL, NULL); 2490 2491 /* 2492 struct cfdriver sk_cd = { 2493 0, "sk", DV_IFNET 2494 }; 2495 */ 2496 2497 #ifdef SK_DEBUG 2498 void 2499 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2500 { 2501 #define DESC_PRINT(X) \ 2502 if (desc->X) \ 2503 printf("txdesc[%d]." #X "=%#x\n", \ 2504 idx, desc->X); 2505 2506 DESC_PRINT(sk_ctl); 2507 DESC_PRINT(sk_next); 2508 DESC_PRINT(sk_data_lo); 2509 DESC_PRINT(sk_data_hi); 2510 DESC_PRINT(sk_xmac_txstat); 2511 DESC_PRINT(sk_rsvd0); 2512 DESC_PRINT(sk_csum_startval); 2513 DESC_PRINT(sk_csum_startpos); 2514 DESC_PRINT(sk_csum_writepos); 2515 DESC_PRINT(sk_rsvd1); 2516 #undef PRINT 2517 } 2518 2519 void 2520 sk_dump_bytes(const char *data, int len) 2521 { 2522 int c, i, j; 2523 2524 for (i = 0; i < len; i += 16) { 2525 printf("%08x ", i); 2526 c = len - i; 2527 if (c > 16) c = 16; 2528 2529 for (j = 0; j < c; j++) { 2530 printf("%02x ", data[i + j] & 0xff); 2531 if ((j & 0xf) == 7 && j > 0) 2532 printf(" "); 2533 } 2534 2535 for (; j < 16; j++) 2536 printf(" "); 2537 printf(" "); 2538 2539 for (j = 0; j < c; j++) { 2540 int ch = data[i + j] & 0xff; 2541 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2542 } 2543 2544 printf("\n"); 2545 2546 if (c < 16) 2547 break; 2548 } 2549 } 2550 2551 void 2552 sk_dump_mbuf(struct mbuf *m) 2553 { 2554 int count = m->m_pkthdr.len; 2555 2556 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2557 2558 while (count > 0 && m) { 2559 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2560 m, m->m_data, m->m_len); 2561 sk_dump_bytes(mtod(m, char *), m->m_len); 2562 2563 count -= m->m_len; 2564 m = m->m_next; 2565 } 2566 } 2567 #endif 2568
Indexes created Tue Sep 23 20:09:58 GMT 2025