if_sk.c revision 1.21
1 /* $NetBSD: if_sk.c,v 1.21 2006/02/25 02:28:58 wiz Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* $OpenBSD: if_sk.c,v 1.33 2003/08/12 05:23:06 nate Exp $ */ 37 38 /* 39 * Copyright (c) 1997, 1998, 1999, 2000 40 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Bill Paul. 53 * 4. Neither the name of the author nor the names of any co-contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 67 * THE POSSIBILITY OF SUCH DAMAGE. 68 * 69 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $ 70 */ 71 72 /* 73 * Copyright (c) 2003 Nathan L. Binkert <binkertn (at) umich.edu> 74 * 75 * Permission to use, copy, modify, and distribute this software for any 76 * purpose with or without fee is hereby granted, provided that the above 77 * copyright notice and this permission notice appear in all copies. 78 * 79 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 80 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 81 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 82 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 83 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 84 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 85 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 86 */ 87 88 /* 89 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports 90 * the SK-984x series adapters, both single port and dual port. 91 * References: 92 * The XaQti XMAC II datasheet, 93 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 94 * The SysKonnect GEnesis manual, http://www.syskonnect.com 95 * 96 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the 97 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a 98 * convenience to others until Vitesse corrects this problem: 99 * 100 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf 101 * 102 * Written by Bill Paul <wpaul (at) ee.columbia.edu> 103 * Department of Electrical Engineering 104 * Columbia University, New York City 105 */ 106 107 /* 108 * The SysKonnect gigabit ethernet adapters consist of two main 109 * components: the SysKonnect GEnesis controller chip and the XaQti Corp. 110 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC 111 * components and a PHY while the GEnesis controller provides a PCI 112 * interface with DMA support. Each card may have between 512K and 113 * 2MB of SRAM on board depending on the configuration. 114 * 115 * The SysKonnect GEnesis controller can have either one or two XMAC 116 * chips connected to it, allowing single or dual port NIC configurations. 117 * SysKonnect has the distinction of being the only vendor on the market 118 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs, 119 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the 120 * XMAC registers. This driver takes advantage of these features to allow 121 * both XMACs to operate as independent interfaces. 122 */ 123 124 #include "bpfilter.h" 125 #include "rnd.h" 126 127 #include <sys/param.h> 128 #include <sys/systm.h> 129 #include <sys/sockio.h> 130 #include <sys/mbuf.h> 131 #include <sys/malloc.h> 132 #include <sys/kernel.h> 133 #include <sys/socket.h> 134 #include <sys/device.h> 135 #include <sys/queue.h> 136 #include <sys/callout.h> 137 #include <sys/sysctl.h> 138 139 #include <net/if.h> 140 #include <net/if_dl.h> 141 #include <net/if_types.h> 142 143 #ifdef INET 144 #include <netinet/in.h> 145 #include <netinet/in_systm.h> 146 #include <netinet/in_var.h> 147 #include <netinet/ip.h> 148 #include <netinet/if_ether.h> 149 #endif 150 151 #include <net/if_media.h> 152 153 #if NBPFILTER > 0 154 #include <net/bpf.h> 155 #endif 156 #if NRND > 0 157 #include <sys/rnd.h> 158 #endif 159 160 #include <dev/mii/mii.h> 161 #include <dev/mii/miivar.h> 162 #include <dev/mii/brgphyreg.h> 163 164 #include <dev/pci/pcireg.h> 165 #include <dev/pci/pcivar.h> 166 #include <dev/pci/pcidevs.h> 167 168 #define SK_VERBOSE 169 /* #define SK_USEIOSPACE */ 170 171 #include <dev/pci/if_skreg.h> 172 #include <dev/pci/if_skvar.h> 173 174 int skc_probe(struct device *, struct cfdata *, void *); 175 void skc_attach(struct device *, struct device *self, void *aux); 176 int sk_probe(struct device *, struct cfdata *, void *); 177 void sk_attach(struct device *, struct device *self, void *aux); 178 int skcprint(void *, const char *); 179 int sk_intr(void *); 180 void sk_intr_bcom(struct sk_if_softc *); 181 void sk_intr_xmac(struct sk_if_softc *); 182 void sk_intr_yukon(struct sk_if_softc *); 183 void sk_rxeof(struct sk_if_softc *); 184 void sk_txeof(struct sk_if_softc *); 185 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *); 186 void sk_start(struct ifnet *); 187 int sk_ioctl(struct ifnet *, u_long, caddr_t); 188 int sk_init(struct ifnet *); 189 void sk_init_xmac(struct sk_if_softc *); 190 void sk_init_yukon(struct sk_if_softc *); 191 void sk_stop(struct ifnet *, int); 192 void sk_watchdog(struct ifnet *); 193 void sk_shutdown(void *); 194 int sk_ifmedia_upd(struct ifnet *); 195 void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 196 void sk_reset(struct sk_softc *); 197 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t); 198 int sk_init_rx_ring(struct sk_if_softc *); 199 int sk_init_tx_ring(struct sk_if_softc *); 200 u_int8_t sk_vpd_readbyte(struct sk_softc *, int); 201 void sk_vpd_read_res(struct sk_softc *, 202 struct vpd_res *, int); 203 void sk_vpd_read(struct sk_softc *); 204 205 void sk_update_int_mod(struct sk_softc *); 206 207 int sk_xmac_miibus_readreg(struct device *, int, int); 208 void sk_xmac_miibus_writereg(struct device *, int, int, int); 209 void sk_xmac_miibus_statchg(struct device *); 210 211 int sk_marv_miibus_readreg(struct device *, int, int); 212 void sk_marv_miibus_writereg(struct device *, int, int, int); 213 void sk_marv_miibus_statchg(struct device *); 214 215 u_int32_t sk_xmac_hash(caddr_t); 216 u_int32_t sk_yukon_hash(caddr_t); 217 void sk_setfilt(struct sk_if_softc *, caddr_t, int); 218 void sk_setmulti(struct sk_if_softc *); 219 void sk_tick(void *); 220 221 /* #define SK_DEBUG 2 */ 222 #ifdef SK_DEBUG 223 #define DPRINTF(x) if (skdebug) printf x 224 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x 225 int skdebug = SK_DEBUG; 226 227 void sk_dump_txdesc(struct sk_tx_desc *, int); 228 void sk_dump_mbuf(struct mbuf *); 229 void sk_dump_bytes(const char *, int); 230 #else 231 #define DPRINTF(x) 232 #define DPRINTFN(n,x) 233 #endif 234 235 #define SK_SETBIT(sc, reg, x) \ 236 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 237 238 #define SK_CLRBIT(sc, reg, x) \ 239 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 240 241 #define SK_WIN_SETBIT_4(sc, reg, x) \ 242 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x) 243 244 #define SK_WIN_CLRBIT_4(sc, reg, x) \ 245 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x) 246 247 #define SK_WIN_SETBIT_2(sc, reg, x) \ 248 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x) 249 250 #define SK_WIN_CLRBIT_2(sc, reg, x) \ 251 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x) 252 253 static int sk_sysctl_handler(SYSCTLFN_PROTO); 254 static int sk_root_num; 255 256 /* supported device vendors */ 257 static const struct sk_product { 258 pci_vendor_id_t sk_vendor; 259 pci_product_id_t sk_product; 260 } sk_products[] = { 261 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940, }, 262 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T, }, 263 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064, }, 264 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE, }, 265 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2, }, 266 { PCI_VENDOR_GALILEO, PCI_PRODUCT_GALILEO_SKNET, }, 267 { PCI_VENDOR_GALILEO, PCI_PRODUCT_GALILEO_BELKIN, }, 268 { 0, 0, } 269 }; 270 271 #define SK_LINKSYS_EG1032_SUBID 0x00151737 272 273 static inline u_int32_t 274 sk_win_read_4(struct sk_softc *sc, u_int32_t reg) 275 { 276 #ifdef SK_USEIOSPACE 277 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 278 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)); 279 #else 280 return CSR_READ_4(sc, reg); 281 #endif 282 } 283 284 static inline u_int16_t 285 sk_win_read_2(struct sk_softc *sc, u_int32_t reg) 286 { 287 #ifdef SK_USEIOSPACE 288 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 289 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)); 290 #else 291 return CSR_READ_2(sc, reg); 292 #endif 293 } 294 295 static inline u_int8_t 296 sk_win_read_1(struct sk_softc *sc, u_int32_t reg) 297 { 298 #ifdef SK_USEIOSPACE 299 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 300 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)); 301 #else 302 return CSR_READ_1(sc, reg); 303 #endif 304 } 305 306 static inline void 307 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x) 308 { 309 #ifdef SK_USEIOSPACE 310 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 311 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 312 #else 313 CSR_WRITE_4(sc, reg, x); 314 #endif 315 } 316 317 static inline void 318 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x) 319 { 320 #ifdef SK_USEIOSPACE 321 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 322 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x); 323 #else 324 CSR_WRITE_2(sc, reg, x); 325 #endif 326 } 327 328 static inline void 329 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x) 330 { 331 #ifdef SK_USEIOSPACE 332 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 333 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x); 334 #else 335 CSR_WRITE_1(sc, reg, x); 336 #endif 337 } 338 339 /* 340 * The VPD EEPROM contains Vital Product Data, as suggested in 341 * the PCI 2.1 specification. The VPD data is separared into areas 342 * denoted by resource IDs. The SysKonnect VPD contains an ID string 343 * resource (the name of the adapter), a read-only area resource 344 * containing various key/data fields and a read/write area which 345 * can be used to store asset management information or log messages. 346 * We read the ID string and read-only into buffers attached to 347 * the controller softc structure for later use. At the moment, 348 * we only use the ID string during sk_attach(). 349 */ 350 u_int8_t 351 sk_vpd_readbyte(struct sk_softc *sc, int addr) 352 { 353 int i; 354 355 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr); 356 for (i = 0; i < SK_TIMEOUT; i++) { 357 DELAY(1); 358 if (sk_win_read_2(sc, 359 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG) 360 break; 361 } 362 363 if (i == SK_TIMEOUT) 364 return(0); 365 366 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA))); 367 } 368 369 void 370 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr) 371 { 372 int i; 373 u_int8_t *ptr; 374 375 ptr = (u_int8_t *)res; 376 for (i = 0; i < sizeof(struct vpd_res); i++) 377 ptr[i] = sk_vpd_readbyte(sc, i + addr); 378 } 379 380 void 381 sk_vpd_read(struct sk_softc *sc) 382 { 383 int pos = 0, i; 384 struct vpd_res res; 385 386 if (sc->sk_vpd_prodname != NULL) 387 free(sc->sk_vpd_prodname, M_DEVBUF); 388 if (sc->sk_vpd_readonly != NULL) 389 free(sc->sk_vpd_readonly, M_DEVBUF); 390 sc->sk_vpd_prodname = NULL; 391 sc->sk_vpd_readonly = NULL; 392 393 sk_vpd_read_res(sc, &res, pos); 394 395 if (res.vr_id != VPD_RES_ID) { 396 printf("%s: bad VPD resource id: expected %x got %x\n", 397 sc->sk_dev.dv_xname, VPD_RES_ID, res.vr_id); 398 return; 399 } 400 401 pos += sizeof(res); 402 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 403 if (sc->sk_vpd_prodname == NULL) 404 panic("sk_vpd_read"); 405 for (i = 0; i < res.vr_len; i++) 406 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos); 407 sc->sk_vpd_prodname[i] = '\0'; 408 pos += i; 409 410 sk_vpd_read_res(sc, &res, pos); 411 412 if (res.vr_id != VPD_RES_READ) { 413 printf("%s: bad VPD resource id: expected %x got %x\n", 414 sc->sk_dev.dv_xname, VPD_RES_READ, res.vr_id); 415 return; 416 } 417 418 pos += sizeof(res); 419 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 420 if (sc->sk_vpd_readonly == NULL) 421 panic("sk_vpd_read"); 422 for (i = 0; i < res.vr_len ; i++) 423 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos); 424 } 425 426 int 427 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg) 428 { 429 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 430 int i; 431 432 DPRINTFN(9, ("sk_xmac_miibus_readreg\n")); 433 434 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0) 435 return(0); 436 437 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 438 SK_XM_READ_2(sc_if, XM_PHY_DATA); 439 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 440 for (i = 0; i < SK_TIMEOUT; i++) { 441 DELAY(1); 442 if (SK_XM_READ_2(sc_if, XM_MMUCMD) & 443 XM_MMUCMD_PHYDATARDY) 444 break; 445 } 446 447 if (i == SK_TIMEOUT) { 448 printf("%s: phy failed to come ready\n", 449 sc_if->sk_dev.dv_xname); 450 return(0); 451 } 452 } 453 DELAY(1); 454 return(SK_XM_READ_2(sc_if, XM_PHY_DATA)); 455 } 456 457 void 458 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val) 459 { 460 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 461 int i; 462 463 DPRINTFN(9, ("sk_xmac_miibus_writereg\n")); 464 465 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8)); 466 for (i = 0; i < SK_TIMEOUT; i++) { 467 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 468 break; 469 } 470 471 if (i == SK_TIMEOUT) { 472 printf("%s: phy failed to come ready\n", 473 sc_if->sk_dev.dv_xname); 474 return; 475 } 476 477 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val); 478 for (i = 0; i < SK_TIMEOUT; i++) { 479 DELAY(1); 480 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY)) 481 break; 482 } 483 484 if (i == SK_TIMEOUT) 485 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname); 486 } 487 488 void 489 sk_xmac_miibus_statchg(struct device *dev) 490 { 491 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 492 struct mii_data *mii = &sc_if->sk_mii; 493 494 DPRINTFN(9, ("sk_xmac_miibus_statchg\n")); 495 496 /* 497 * If this is a GMII PHY, manually set the XMAC's 498 * duplex mode accordingly. 499 */ 500 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) { 501 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 502 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 503 } else { 504 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX); 505 } 506 } 507 } 508 509 int 510 sk_marv_miibus_readreg(dev, phy, reg) 511 struct device *dev; 512 int phy, reg; 513 { 514 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 515 u_int16_t val; 516 int i; 517 518 if (phy != 0 || 519 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER && 520 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) { 521 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n", 522 phy, reg)); 523 return(0); 524 } 525 526 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 527 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); 528 529 for (i = 0; i < SK_TIMEOUT; i++) { 530 DELAY(1); 531 val = SK_YU_READ_2(sc_if, YUKON_SMICR); 532 if (val & YU_SMICR_READ_VALID) 533 break; 534 } 535 536 if (i == SK_TIMEOUT) { 537 printf("%s: phy failed to come ready\n", 538 sc_if->sk_dev.dv_xname); 539 return 0; 540 } 541 542 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i, 543 SK_TIMEOUT)); 544 545 val = SK_YU_READ_2(sc_if, YUKON_SMIDR); 546 547 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 548 phy, reg, val)); 549 550 return val; 551 } 552 553 void 554 sk_marv_miibus_writereg(dev, phy, reg, val) 555 struct device *dev; 556 int phy, reg, val; 557 { 558 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev; 559 int i; 560 561 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n", 562 phy, reg, val)); 563 564 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val); 565 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | 566 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE); 567 568 for (i = 0; i < SK_TIMEOUT; i++) { 569 DELAY(1); 570 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) 571 break; 572 } 573 } 574 575 void 576 sk_marv_miibus_statchg(dev) 577 struct device *dev; 578 { 579 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n", 580 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR))); 581 } 582 583 #define SK_HASH_BITS 6 584 585 u_int32_t 586 sk_xmac_hash(caddr_t addr) 587 { 588 u_int32_t crc; 589 590 crc = ether_crc32_le(addr,ETHER_ADDR_LEN); 591 crc = ~crc & ((1<< SK_HASH_BITS) - 1); 592 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 593 return (crc); 594 } 595 596 u_int32_t 597 sk_yukon_hash(caddr_t addr) 598 { 599 u_int32_t crc; 600 601 crc = ether_crc32_be(addr,ETHER_ADDR_LEN); 602 crc &= ((1 << SK_HASH_BITS) - 1); 603 DPRINTFN(2,("multicast hash for %s is %x\n",ether_sprintf(addr),crc)); 604 return (crc); 605 } 606 607 void 608 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot) 609 { 610 int base = XM_RXFILT_ENTRY(slot); 611 612 SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0])); 613 SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2])); 614 SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4])); 615 } 616 617 void 618 sk_setmulti(struct sk_if_softc *sc_if) 619 { 620 struct sk_softc *sc = sc_if->sk_softc; 621 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if; 622 u_int32_t hashes[2] = { 0, 0 }; 623 int h = 0, i; 624 struct ethercom *ec = &sc_if->sk_ethercom; 625 struct ether_multi *enm; 626 struct ether_multistep step; 627 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 628 629 /* First, zot all the existing filters. */ 630 switch(sc->sk_type) { 631 case SK_GENESIS: 632 for (i = 1; i < XM_RXFILT_MAX; i++) 633 sk_setfilt(sc_if, (caddr_t)&dummy, i); 634 635 SK_XM_WRITE_4(sc_if, XM_MAR0, 0); 636 SK_XM_WRITE_4(sc_if, XM_MAR2, 0); 637 break; 638 case SK_YUKON: 639 case SK_YUKON_LITE: 640 case SK_YUKON_LP: 641 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0); 642 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0); 643 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0); 644 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0); 645 break; 646 } 647 648 /* Now program new ones. */ 649 allmulti: 650 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 651 hashes[0] = 0xFFFFFFFF; 652 hashes[1] = 0xFFFFFFFF; 653 } else { 654 i = 1; 655 /* First find the tail of the list. */ 656 ETHER_FIRST_MULTI(step, ec, enm); 657 while (enm != NULL) { 658 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 659 ETHER_ADDR_LEN)) { 660 ifp->if_flags |= IFF_ALLMULTI; 661 goto allmulti; 662 } 663 DPRINTFN(2,("multicast address %s\n", 664 ether_sprintf(enm->enm_addrlo))); 665 /* 666 * Program the first XM_RXFILT_MAX multicast groups 667 * into the perfect filter. For all others, 668 * use the hash table. 669 */ 670 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) { 671 sk_setfilt(sc_if, enm->enm_addrlo, i); 672 i++; 673 } 674 else { 675 switch (sc->sk_type) { 676 case SK_GENESIS: 677 h = sk_xmac_hash(enm->enm_addrlo); 678 break; 679 case SK_YUKON: 680 case SK_YUKON_LITE: 681 case SK_YUKON_LP: 682 h = sk_yukon_hash(enm->enm_addrlo); 683 break; 684 } 685 if (h < 32) 686 hashes[0] |= (1 << h); 687 else 688 hashes[1] |= (1 << (h - 32)); 689 } 690 691 ETHER_NEXT_MULTI(step, enm); 692 } 693 } 694 695 switch(sc->sk_type) { 696 case SK_GENESIS: 697 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH| 698 XM_MODE_RX_USE_PERFECT); 699 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]); 700 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]); 701 break; 702 case SK_YUKON: 703 case SK_YUKON_LITE: 704 case SK_YUKON_LP: 705 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff); 706 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff); 707 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff); 708 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff); 709 break; 710 } 711 } 712 713 int 714 sk_init_rx_ring(struct sk_if_softc *sc_if) 715 { 716 struct sk_chain_data *cd = &sc_if->sk_cdata; 717 struct sk_ring_data *rd = sc_if->sk_rdata; 718 int i; 719 720 bzero((char *)rd->sk_rx_ring, 721 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT); 722 723 for (i = 0; i < SK_RX_RING_CNT; i++) { 724 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i]; 725 if (i == (SK_RX_RING_CNT - 1)) { 726 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0]; 727 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if, 0); 728 } else { 729 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1]; 730 rd->sk_rx_ring[i].sk_next = SK_RX_RING_ADDR(sc_if,i+1); 731 } 732 } 733 734 for (i = 0; i < SK_RX_RING_CNT; i++) { 735 if (sk_newbuf(sc_if, i, NULL, NULL) == ENOBUFS) { 736 printf("%s: failed alloc of %dth mbuf\n", 737 sc_if->sk_dev.dv_xname, i); 738 return(ENOBUFS); 739 } 740 } 741 sc_if->sk_cdata.sk_rx_prod = 0; 742 sc_if->sk_cdata.sk_rx_cons = 0; 743 744 return(0); 745 } 746 747 int 748 sk_init_tx_ring(struct sk_if_softc *sc_if) 749 { 750 struct sk_chain_data *cd = &sc_if->sk_cdata; 751 struct sk_ring_data *rd = sc_if->sk_rdata; 752 int i; 753 754 bzero((char *)sc_if->sk_rdata->sk_tx_ring, 755 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT); 756 757 for (i = 0; i < SK_TX_RING_CNT; i++) { 758 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i]; 759 if (i == (SK_TX_RING_CNT - 1)) { 760 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0]; 761 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if, 0); 762 } else { 763 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1]; 764 rd->sk_tx_ring[i].sk_next = SK_TX_RING_ADDR(sc_if,i+1); 765 } 766 } 767 768 sc_if->sk_cdata.sk_tx_prod = 0; 769 sc_if->sk_cdata.sk_tx_cons = 0; 770 sc_if->sk_cdata.sk_tx_cnt = 0; 771 772 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT, 773 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 774 775 return (0); 776 } 777 778 int 779 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m, 780 bus_dmamap_t dmamap) 781 { 782 struct sk_softc *sc = sc_if->sk_softc; 783 struct mbuf *m_new = NULL; 784 struct sk_chain *c; 785 struct sk_rx_desc *r; 786 787 if (dmamap == NULL) { 788 /* if (m) panic() */ 789 790 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, MCLBYTES, 791 0, BUS_DMA_NOWAIT, &dmamap)) { 792 printf("%s: can't create recv map\n", 793 sc_if->sk_dev.dv_xname); 794 return(ENOMEM); 795 } 796 } else if (m == NULL) 797 bus_dmamap_unload(sc->sc_dmatag, dmamap); 798 799 sc_if->sk_cdata.sk_rx_map[i] = dmamap; 800 801 if (m == NULL) { 802 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 803 if (m_new == NULL) { 804 printf("%s: no memory for rx list -- " 805 "packet dropped!\n", sc_if->sk_dev.dv_xname); 806 return(ENOBUFS); 807 } 808 809 /* Allocate the jumbo buffer */ 810 MCLGET(m_new, M_DONTWAIT); 811 if (!(m_new->m_flags & M_EXT)) { 812 m_freem(m_new); 813 return (ENOBUFS); 814 } 815 816 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 817 818 m_adj(m_new, ETHER_ALIGN); 819 820 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m_new, 821 BUS_DMA_NOWAIT)) 822 return(ENOBUFS); 823 } else { 824 /* 825 * We're re-using a previously allocated mbuf; 826 * be sure to re-init pointers and lengths to 827 * default values. 828 */ 829 m_new = m; 830 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 831 m_adj(m_new, ETHER_ALIGN); 832 m_new->m_data = m_new->m_ext.ext_buf; 833 } 834 835 c = &sc_if->sk_cdata.sk_rx_chain[i]; 836 r = c->sk_desc; 837 c->sk_mbuf = m_new; 838 r->sk_data_lo = dmamap->dm_segs[0].ds_addr; 839 r->sk_ctl = dmamap->dm_segs[0].ds_len | SK_RXSTAT; 840 841 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 842 843 return(0); 844 } 845 846 /* 847 * Set media options. 848 */ 849 int 850 sk_ifmedia_upd(struct ifnet *ifp) 851 { 852 struct sk_if_softc *sc_if = ifp->if_softc; 853 854 (void) sk_init(ifp); 855 mii_mediachg(&sc_if->sk_mii); 856 return(0); 857 } 858 859 /* 860 * Report current media status. 861 */ 862 void 863 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 864 { 865 struct sk_if_softc *sc_if = ifp->if_softc; 866 867 mii_pollstat(&sc_if->sk_mii); 868 ifmr->ifm_active = sc_if->sk_mii.mii_media_active; 869 ifmr->ifm_status = sc_if->sk_mii.mii_media_status; 870 } 871 872 int 873 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 874 { 875 struct sk_if_softc *sc_if = ifp->if_softc; 876 struct sk_softc *sc = sc_if->sk_softc; 877 struct ifreq *ifr = (struct ifreq *) data; 878 /* struct ifaddr *ifa = (struct ifaddr *) data; */ 879 struct mii_data *mii; 880 int s, error = 0; 881 882 /* DPRINTFN(2, ("sk_ioctl\n")); */ 883 884 s = splnet(); 885 886 switch(command) { 887 888 case SIOCSIFFLAGS: 889 DPRINTFN(2, ("sk_ioctl IFFLAGS\n")); 890 if (ifp->if_flags & IFF_UP) { 891 if (ifp->if_flags & IFF_RUNNING && 892 ifp->if_flags & IFF_PROMISC && 893 !(sc_if->sk_if_flags & IFF_PROMISC)) { 894 switch(sc->sk_type) { 895 case SK_GENESIS: 896 SK_XM_SETBIT_4(sc_if, XM_MODE, 897 XM_MODE_RX_PROMISC); 898 break; 899 case SK_YUKON: 900 case SK_YUKON_LITE: 901 case SK_YUKON_LP: 902 SK_YU_CLRBIT_2(sc_if, YUKON_RCR, 903 YU_RCR_UFLEN | YU_RCR_MUFLEN); 904 break; 905 } 906 sk_setmulti(sc_if); 907 } else if (ifp->if_flags & IFF_RUNNING && 908 !(ifp->if_flags & IFF_PROMISC) && 909 sc_if->sk_if_flags & IFF_PROMISC) { 910 switch(sc->sk_type) { 911 case SK_GENESIS: 912 SK_XM_CLRBIT_4(sc_if, XM_MODE, 913 XM_MODE_RX_PROMISC); 914 break; 915 case SK_YUKON: 916 case SK_YUKON_LITE: 917 case SK_YUKON_LP: 918 SK_YU_SETBIT_2(sc_if, YUKON_RCR, 919 YU_RCR_UFLEN | YU_RCR_MUFLEN); 920 break; 921 } 922 923 sk_setmulti(sc_if); 924 } else 925 (void) sk_init(ifp); 926 } else { 927 if (ifp->if_flags & IFF_RUNNING) 928 sk_stop(ifp,0); 929 } 930 sc_if->sk_if_flags = ifp->if_flags; 931 error = 0; 932 break; 933 934 case SIOCGIFMEDIA: 935 case SIOCSIFMEDIA: 936 DPRINTFN(2, ("sk_ioctl MEDIA\n")); 937 mii = &sc_if->sk_mii; 938 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 939 break; 940 default: 941 DPRINTFN(2, ("sk_ioctl ETHER\n")); 942 error = ether_ioctl(ifp, command, data); 943 944 if ( error == ENETRESET) { 945 if (ifp->if_flags & IFF_RUNNING) { 946 sk_setmulti(sc_if); 947 DPRINTFN(2, ("sk_ioctl setmulti called\n")); 948 } 949 error = 0; 950 } else if ( error ) { 951 splx(s); 952 return error; 953 } 954 break; 955 } 956 957 splx(s); 958 return(error); 959 } 960 961 void 962 sk_update_int_mod(struct sk_softc *sc) 963 { 964 u_int32_t sk_imtimer_ticks; 965 966 /* 967 * Configure interrupt moderation. The moderation timer 968 * defers interrupts specified in the interrupt moderation 969 * timer mask based on the timeout specified in the interrupt 970 * moderation timer init register. Each bit in the timer 971 * register represents one tick, so to specify a timeout in 972 * microseconds, we have to multiply by the correct number of 973 * ticks-per-microsecond. 974 */ 975 switch (sc->sk_type) { 976 case SK_GENESIS: 977 sk_imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 978 break; 979 case SK_YUKON_EC: 980 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 981 break; 982 default: 983 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 984 } 985 aprint_verbose("%s: interrupt moderation is %d us\n", 986 sc->sk_dev.dv_xname, sc->sk_int_mod); 987 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod)); 988 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF| 989 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF); 990 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START); 991 sc->sk_int_mod_pending = 0; 992 } 993 994 /* 995 * Lookup: Check the PCI vendor and device, and return a pointer to 996 * The structure if the IDs match against our list. 997 */ 998 999 static const struct sk_product * 1000 sk_lookup(const struct pci_attach_args *pa) 1001 { 1002 const struct sk_product *psk; 1003 1004 for ( psk = &sk_products[0]; psk->sk_vendor != 0; psk++ ) { 1005 if (PCI_VENDOR(pa->pa_id) == psk->sk_vendor && 1006 PCI_PRODUCT(pa->pa_id) == psk->sk_product) 1007 return (psk); 1008 } 1009 return (NULL); 1010 } 1011 1012 /* 1013 * Probe for a SysKonnect GEnesis chip. 1014 */ 1015 1016 int 1017 skc_probe(struct device *parent, struct cfdata *match, void *aux) 1018 { 1019 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1020 const struct sk_product *psk; 1021 pcireg_t subid; 1022 1023 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 1024 1025 /* special-case Linksys EG1032, since rev 3 uses re(4) */ 1026 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 1027 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 1028 subid == SK_LINKSYS_EG1032_SUBID) 1029 return(1); 1030 1031 if ((psk = sk_lookup(pa))) { 1032 return(1); 1033 } 1034 return(0); 1035 } 1036 1037 /* 1038 * Force the GEnesis into reset, then bring it out of reset. 1039 */ 1040 void sk_reset(struct sk_softc *sc) 1041 { 1042 DPRINTFN(2, ("sk_reset\n")); 1043 1044 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); 1045 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); 1046 if (SK_YUKON_FAMILY(sc->sk_type)) 1047 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); 1048 1049 DELAY(1000); 1050 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); 1051 DELAY(2); 1052 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); 1053 if (SK_YUKON_FAMILY(sc->sk_type)) 1054 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); 1055 1056 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR))); 1057 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n", 1058 CSR_READ_2(sc, SK_LINK_CTRL))); 1059 1060 if (sc->sk_type == SK_GENESIS) { 1061 /* Configure packet arbiter */ 1062 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET); 1063 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT); 1064 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT); 1065 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT); 1066 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT); 1067 } 1068 1069 /* Enable RAM interface */ 1070 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET); 1071 1072 sk_update_int_mod(sc); 1073 } 1074 1075 int 1076 sk_probe(struct device *parent, struct cfdata *match, void *aux) 1077 { 1078 struct skc_attach_args *sa = aux; 1079 1080 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B) 1081 return(0); 1082 1083 return (1); 1084 } 1085 1086 /* 1087 * Each XMAC chip is attached as a separate logical IP interface. 1088 * Single port cards will have only one logical interface of course. 1089 */ 1090 void 1091 sk_attach(struct device *parent, struct device *self, void *aux) 1092 { 1093 struct sk_if_softc *sc_if = (struct sk_if_softc *) self; 1094 struct sk_softc *sc = (struct sk_softc *)parent; 1095 struct skc_attach_args *sa = aux; 1096 struct sk_txmap_entry *entry; 1097 struct ifnet *ifp; 1098 bus_dma_segment_t seg; 1099 bus_dmamap_t dmamap; 1100 caddr_t kva; 1101 int i, rseg; 1102 1103 sc_if->sk_port = sa->skc_port; 1104 sc_if->sk_softc = sc; 1105 sc->sk_if[sa->skc_port] = sc_if; 1106 1107 if (sa->skc_port == SK_PORT_A) 1108 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0; 1109 if (sa->skc_port == SK_PORT_B) 1110 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1; 1111 1112 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port)); 1113 1114 /* 1115 * Get station address for this interface. Note that 1116 * dual port cards actually come with three station 1117 * addresses: one for each port, plus an extra. The 1118 * extra one is used by the SysKonnect driver software 1119 * as a 'virtual' station address for when both ports 1120 * are operating in failover mode. Currently we don't 1121 * use this extra address. 1122 */ 1123 for (i = 0; i < ETHER_ADDR_LEN; i++) 1124 sc_if->sk_enaddr[i] = 1125 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i); 1126 1127 1128 aprint_normal(": Ethernet address %s\n", 1129 ether_sprintf(sc_if->sk_enaddr)); 1130 1131 /* 1132 * Set up RAM buffer addresses. The NIC will have a certain 1133 * amount of SRAM on it, somewhere between 512K and 2MB. We 1134 * need to divide this up a) between the transmitter and 1135 * receiver and b) between the two XMACs, if this is a 1136 * dual port NIC. Our algotithm is to divide up the memory 1137 * evenly so that everyone gets a fair share. 1138 */ 1139 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) { 1140 u_int32_t chunk, val; 1141 1142 chunk = sc->sk_ramsize / 2; 1143 val = sc->sk_rboff / sizeof(u_int64_t); 1144 sc_if->sk_rx_ramstart = val; 1145 val += (chunk / sizeof(u_int64_t)); 1146 sc_if->sk_rx_ramend = val - 1; 1147 sc_if->sk_tx_ramstart = val; 1148 val += (chunk / sizeof(u_int64_t)); 1149 sc_if->sk_tx_ramend = val - 1; 1150 } else { 1151 u_int32_t chunk, val; 1152 1153 chunk = sc->sk_ramsize / 4; 1154 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) / 1155 sizeof(u_int64_t); 1156 sc_if->sk_rx_ramstart = val; 1157 val += (chunk / sizeof(u_int64_t)); 1158 sc_if->sk_rx_ramend = val - 1; 1159 sc_if->sk_tx_ramstart = val; 1160 val += (chunk / sizeof(u_int64_t)); 1161 sc_if->sk_tx_ramend = val - 1; 1162 } 1163 1164 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n" 1165 " tx_ramstart=%#x tx_ramend=%#x\n", 1166 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend, 1167 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend)); 1168 1169 /* Read and save PHY type and set PHY address */ 1170 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF; 1171 switch (sc_if->sk_phytype) { 1172 case SK_PHYTYPE_XMAC: 1173 sc_if->sk_phyaddr = SK_PHYADDR_XMAC; 1174 break; 1175 case SK_PHYTYPE_BCOM: 1176 sc_if->sk_phyaddr = SK_PHYADDR_BCOM; 1177 break; 1178 case SK_PHYTYPE_MARV_COPPER: 1179 sc_if->sk_phyaddr = SK_PHYADDR_MARV; 1180 break; 1181 default: 1182 aprint_error("%s: unsupported PHY type: %d\n", 1183 sc->sk_dev.dv_xname, sc_if->sk_phytype); 1184 return; 1185 } 1186 1187 /* Allocate the descriptor queues. */ 1188 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data), 1189 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1190 aprint_error("%s: can't alloc rx buffers\n", 1191 sc->sk_dev.dv_xname); 1192 goto fail; 1193 } 1194 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 1195 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) { 1196 aprint_error("%s: can't map dma buffers (%lu bytes)\n", 1197 sc_if->sk_dev.dv_xname, 1198 (u_long) sizeof(struct sk_ring_data)); 1199 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1200 goto fail; 1201 } 1202 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1, 1203 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT, 1204 &sc_if->sk_ring_map)) { 1205 aprint_error("%s: can't create dma map\n", 1206 sc_if->sk_dev.dv_xname); 1207 bus_dmamem_unmap(sc->sc_dmatag, kva, 1208 sizeof(struct sk_ring_data)); 1209 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1210 goto fail; 1211 } 1212 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva, 1213 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) { 1214 aprint_error("%s: can't load dma map\n", 1215 sc_if->sk_dev.dv_xname); 1216 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1217 bus_dmamem_unmap(sc->sc_dmatag, kva, 1218 sizeof(struct sk_ring_data)); 1219 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1220 goto fail; 1221 } 1222 1223 for (i = 0; i < SK_RX_RING_CNT; i++) 1224 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 1225 1226 SIMPLEQ_INIT(&sc_if->sk_txmap_head); 1227 for (i = 0; i < SK_TX_RING_CNT; i++) { 1228 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 1229 1230 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, SK_NTXSEG, 1231 MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap)) { 1232 aprint_error("%s: Can't create TX dmamap\n", 1233 sc_if->sk_dev.dv_xname); 1234 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1235 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1236 bus_dmamem_unmap(sc->sc_dmatag, kva, 1237 sizeof(struct sk_ring_data)); 1238 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1239 goto fail; 1240 } 1241 1242 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT); 1243 if (!entry) { 1244 aprint_error("%s: Can't alloc txmap entry\n", 1245 sc_if->sk_dev.dv_xname); 1246 bus_dmamap_destroy(sc->sc_dmatag, dmamap); 1247 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map); 1248 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map); 1249 bus_dmamem_unmap(sc->sc_dmatag, kva, 1250 sizeof(struct sk_ring_data)); 1251 bus_dmamem_free(sc->sc_dmatag, &seg, rseg); 1252 goto fail; 1253 } 1254 entry->dmamap = dmamap; 1255 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link); 1256 } 1257 1258 sc_if->sk_rdata = (struct sk_ring_data *)kva; 1259 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data)); 1260 1261 /* XXX TLS It's not clear what's wrong with the Jumbo MTU 1262 XXX TLS support in this driver, so we don't enable it. */ 1263 1264 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU; 1265 1266 ifp = &sc_if->sk_ethercom.ec_if; 1267 ifp->if_softc = sc_if; 1268 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1269 ifp->if_ioctl = sk_ioctl; 1270 ifp->if_start = sk_start; 1271 ifp->if_stop = sk_stop; 1272 ifp->if_init = sk_init; 1273 ifp->if_watchdog = sk_watchdog; 1274 ifp->if_capabilities = 0; 1275 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1); 1276 IFQ_SET_READY(&ifp->if_snd); 1277 strcpy(ifp->if_xname, sc_if->sk_dev.dv_xname); 1278 1279 /* 1280 * Do miibus setup. 1281 */ 1282 switch (sc->sk_type) { 1283 case SK_GENESIS: 1284 sk_init_xmac(sc_if); 1285 break; 1286 case SK_YUKON: 1287 case SK_YUKON_LITE: 1288 case SK_YUKON_LP: 1289 sk_init_yukon(sc_if); 1290 break; 1291 default: 1292 panic("%s: unknown device type %d", sc->sk_dev.dv_xname, 1293 sc->sk_type); 1294 } 1295 1296 DPRINTFN(2, ("sk_attach: 1\n")); 1297 1298 sc_if->sk_mii.mii_ifp = ifp; 1299 switch (sc->sk_type) { 1300 case SK_GENESIS: 1301 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg; 1302 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg; 1303 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg; 1304 break; 1305 case SK_YUKON: 1306 case SK_YUKON_LITE: 1307 case SK_YUKON_LP: 1308 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg; 1309 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg; 1310 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg; 1311 break; 1312 } 1313 1314 ifmedia_init(&sc_if->sk_mii.mii_media, 0, 1315 sk_ifmedia_upd, sk_ifmedia_sts); 1316 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY, 1317 MII_OFFSET_ANY, 0); 1318 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) { 1319 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname); 1320 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1321 0, NULL); 1322 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1323 } 1324 else 1325 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO); 1326 1327 callout_init(&sc_if->sk_tick_ch); 1328 callout_reset(&sc_if->sk_tick_ch,hz,sk_tick,sc_if); 1329 1330 DPRINTFN(2, ("sk_attach: 1\n")); 1331 1332 /* 1333 * Call MI attach routines. 1334 */ 1335 if_attach(ifp); 1336 1337 ether_ifattach(ifp, sc_if->sk_enaddr); 1338 1339 #if NRND > 0 1340 rnd_attach_source(&sc->rnd_source, sc->sk_dev.dv_xname, 1341 RND_TYPE_NET, 0); 1342 #endif 1343 1344 DPRINTFN(2, ("sk_attach: end\n")); 1345 1346 return; 1347 1348 fail: 1349 sc->sk_if[sa->skc_port] = NULL; 1350 } 1351 1352 int 1353 skcprint(void *aux, const char *pnp) 1354 { 1355 struct skc_attach_args *sa = aux; 1356 1357 if (pnp) 1358 aprint_normal("sk port %c at %s", 1359 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp); 1360 else 1361 aprint_normal(" port %c", 1362 (sa->skc_port == SK_PORT_A) ? 'A' : 'B'); 1363 return (UNCONF); 1364 } 1365 1366 /* 1367 * Attach the interface. Allocate softc structures, do ifmedia 1368 * setup and ethernet/BPF attach. 1369 */ 1370 void 1371 skc_attach(struct device *parent, struct device *self, void *aux) 1372 { 1373 struct sk_softc *sc = (struct sk_softc *)self; 1374 struct pci_attach_args *pa = aux; 1375 struct skc_attach_args skca; 1376 pci_chipset_tag_t pc = pa->pa_pc; 1377 pcireg_t memtype; 1378 pci_intr_handle_t ih; 1379 const char *intrstr = NULL; 1380 bus_addr_t iobase; 1381 bus_size_t iosize; 1382 int s, rc, sk_nodenum; 1383 u_int32_t command; 1384 const char *revstr; 1385 const struct sysctlnode *node; 1386 1387 DPRINTFN(2, ("begin skc_attach\n")); 1388 1389 s = splnet(); 1390 1391 /* 1392 * Handle power management nonsense. 1393 */ 1394 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF; 1395 1396 if (command == 0x01) { 1397 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL); 1398 if (command & SK_PSTATE_MASK) { 1399 u_int32_t xiobase, membase, irq; 1400 1401 /* Save important PCI config data. */ 1402 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO); 1403 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM); 1404 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE); 1405 1406 /* Reset the power state. */ 1407 aprint_normal("%s chip is in D%d power mode " 1408 "-- setting to D0\n", sc->sk_dev.dv_xname, 1409 command & SK_PSTATE_MASK); 1410 command &= 0xFFFFFFFC; 1411 pci_conf_write(pc, pa->pa_tag, 1412 SK_PCI_PWRMGMTCTRL, command); 1413 1414 /* Restore PCI config data. */ 1415 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase); 1416 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase); 1417 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq); 1418 } 1419 } 1420 1421 /* 1422 * Map control/status registers. 1423 */ 1424 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1425 command |= PCI_COMMAND_IO_ENABLE | 1426 PCI_COMMAND_MEM_ENABLE | 1427 PCI_COMMAND_MASTER_ENABLE; 1428 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1429 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1430 1431 #ifdef SK_USEIOSPACE 1432 if (!(command & PCI_COMMAND_IO_ENABLE)) { 1433 aprint_error(": failed to enable I/O ports!\n"); 1434 goto fail; 1435 } 1436 /* 1437 * Map control/status registers. 1438 */ 1439 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 1440 &iobase, &iosize)) { 1441 aprint_error(": can't find i/o space\n"); 1442 goto fail; 1443 } 1444 #else 1445 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1446 aprint_error(": failed to enable memory mapping!\n"); 1447 goto fail; 1448 } 1449 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM); 1450 switch (memtype) { 1451 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1452 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1453 if (pci_mapreg_map(pa, SK_PCI_LOMEM, 1454 memtype, 0, &sc->sk_btag, &sc->sk_bhandle, 1455 &iobase, &iosize) == 0) 1456 break; 1457 default: 1458 aprint_error("%s: can't find mem space\n", 1459 sc->sk_dev.dv_xname); 1460 return; 1461 } 1462 1463 DPRINTFN(2, ("skc_attach: iobase=%lx, iosize=%lx\n", iobase, iosize)); 1464 #endif 1465 sc->sc_dmatag = pa->pa_dmat; 1466 1467 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER); 1468 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4); 1469 1470 /* bail out here if chip is not recognized */ 1471 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) { 1472 aprint_error("%s: unknown chip type\n",sc->sk_dev.dv_xname); 1473 goto fail; 1474 } 1475 DPRINTFN(2, ("skc_attach: allocate interrupt\n")); 1476 1477 /* Allocate interrupt */ 1478 if (pci_intr_map(pa, &ih)) { 1479 aprint_error(": couldn't map interrupt\n"); 1480 goto fail; 1481 } 1482 1483 intrstr = pci_intr_string(pc, ih); 1484 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc); 1485 if (sc->sk_intrhand == NULL) { 1486 aprint_error(": couldn't establish interrupt"); 1487 if (intrstr != NULL) 1488 aprint_normal(" at %s", intrstr); 1489 goto fail; 1490 } 1491 aprint_normal(": %s\n", intrstr); 1492 1493 /* Reset the adapter. */ 1494 sk_reset(sc); 1495 1496 /* Read and save vital product data from EEPROM. */ 1497 sk_vpd_read(sc); 1498 1499 if (sc->sk_type == SK_GENESIS) { 1500 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1501 /* Read and save RAM size and RAMbuffer offset */ 1502 switch(val) { 1503 case SK_RAMSIZE_512K_64: 1504 sc->sk_ramsize = 0x80000; 1505 sc->sk_rboff = SK_RBOFF_0; 1506 break; 1507 case SK_RAMSIZE_1024K_64: 1508 sc->sk_ramsize = 0x100000; 1509 sc->sk_rboff = SK_RBOFF_80000; 1510 break; 1511 case SK_RAMSIZE_1024K_128: 1512 sc->sk_ramsize = 0x100000; 1513 sc->sk_rboff = SK_RBOFF_0; 1514 break; 1515 case SK_RAMSIZE_2048K_128: 1516 sc->sk_ramsize = 0x200000; 1517 sc->sk_rboff = SK_RBOFF_0; 1518 break; 1519 default: 1520 aprint_error("%s: unknown ram size: %d\n", 1521 sc->sk_dev.dv_xname, val); 1522 goto fail; 1523 break; 1524 } 1525 1526 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n", 1527 sc->sk_ramsize, sc->sk_ramsize / 1024, 1528 sc->sk_rboff)); 1529 } else { 1530 u_int8_t val = sk_win_read_1(sc, SK_EPROM0); 1531 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024); 1532 sc->sk_rboff = SK_RBOFF_0; 1533 1534 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n", 1535 sc->sk_ramsize / 1024, sc->sk_ramsize, 1536 sc->sk_rboff)); 1537 } 1538 1539 /* Read and save physical media type */ 1540 switch(sk_win_read_1(sc, SK_PMDTYPE)) { 1541 case SK_PMD_1000BASESX: 1542 sc->sk_pmd = IFM_1000_SX; 1543 break; 1544 case SK_PMD_1000BASELX: 1545 sc->sk_pmd = IFM_1000_LX; 1546 break; 1547 case SK_PMD_1000BASECX: 1548 sc->sk_pmd = IFM_1000_CX; 1549 break; 1550 case SK_PMD_1000BASETX: 1551 sc->sk_pmd = IFM_1000_T; 1552 break; 1553 default: 1554 aprint_error("%s: unknown media type: 0x%x\n", 1555 sc->sk_dev.dv_xname, sk_win_read_1(sc, SK_PMDTYPE)); 1556 goto fail; 1557 } 1558 1559 /* determine whether to name it with vpd or just make it up */ 1560 /* Marvell Yukon VPD's can freqently be bogus */ 1561 1562 switch (pa->pa_id) { 1563 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1564 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE): 1565 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2: 1566 case PCI_PRODUCT_3COM_3C940: 1567 case PCI_PRODUCT_DLINK_DGE530T: 1568 case PCI_PRODUCT_LINKSYS_EG1032: 1569 case PCI_PRODUCT_LINKSYS_EG1064: 1570 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH, 1571 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2): 1572 case PCI_ID_CODE(PCI_VENDOR_3COM,PCI_PRODUCT_3COM_3C940): 1573 case PCI_ID_CODE(PCI_VENDOR_DLINK,PCI_PRODUCT_DLINK_DGE530T): 1574 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1032): 1575 case PCI_ID_CODE(PCI_VENDOR_LINKSYS,PCI_PRODUCT_LINKSYS_EG1064): 1576 sc->sk_name = sc->sk_vpd_prodname; 1577 break; 1578 case PCI_ID_CODE(PCI_VENDOR_GALILEO,PCI_PRODUCT_GALILEO_SKNET): 1579 /* whoops yukon vpd prodname bears no resemblance to reality */ 1580 switch (sc->sk_type) { 1581 case SK_GENESIS: 1582 sc->sk_name = sc->sk_vpd_prodname; 1583 break; 1584 case SK_YUKON: 1585 sc->sk_name = "Marvell Yukon Gigabit Ethernet"; 1586 break; 1587 case SK_YUKON_LITE: 1588 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet"; 1589 break; 1590 case SK_YUKON_LP: 1591 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet"; 1592 break; 1593 default: 1594 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet"; 1595 } 1596 1597 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */ 1598 1599 if ( sc->sk_type == SK_YUKON ) { 1600 uint32_t flashaddr; 1601 uint8_t testbyte; 1602 1603 flashaddr = sk_win_read_4(sc,SK_EP_ADDR); 1604 1605 /* test Flash-Address Register */ 1606 sk_win_write_1(sc,SK_EP_ADDR+3, 0xff); 1607 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3); 1608 1609 if (testbyte != 0) { 1610 /* this is yukon lite Rev. A0 */ 1611 sc->sk_type = SK_YUKON_LITE; 1612 sc->sk_rev = SK_YUKON_LITE_REV_A0; 1613 /* restore Flash-Address Register */ 1614 sk_win_write_4(sc,SK_EP_ADDR,flashaddr); 1615 } 1616 } 1617 break; 1618 case PCI_ID_CODE(PCI_VENDOR_GALILEO,PCI_PRODUCT_GALILEO_BELKIN): 1619 sc->sk_name = sc->sk_vpd_prodname; 1620 break; 1621 default: 1622 sc->sk_name = "Unknown Marvell"; 1623 } 1624 1625 1626 if ( sc->sk_type == SK_YUKON_LITE ) { 1627 switch (sc->sk_rev) { 1628 case SK_YUKON_LITE_REV_A0: 1629 revstr = "A0"; 1630 break; 1631 case SK_YUKON_LITE_REV_A1: 1632 revstr = "A1"; 1633 break; 1634 case SK_YUKON_LITE_REV_A3: 1635 revstr = "A3"; 1636 break; 1637 default: 1638 revstr = ""; 1639 } 1640 } else { 1641 revstr = ""; 1642 } 1643 1644 /* Announce the product name. */ 1645 aprint_normal("%s: %s rev. %s(0x%x)\n", sc->sk_dev.dv_xname, 1646 sc->sk_name, revstr, sc->sk_rev); 1647 1648 skca.skc_port = SK_PORT_A; 1649 (void)config_found(&sc->sk_dev, &skca, skcprint); 1650 1651 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) { 1652 skca.skc_port = SK_PORT_B; 1653 (void)config_found(&sc->sk_dev, &skca, skcprint); 1654 } 1655 1656 /* Turn on the 'driver is loaded' LED. */ 1657 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); 1658 1659 /* skc sysctl setup */ 1660 1661 sc->sk_int_mod = SK_IM_DEFAULT; 1662 sc->sk_int_mod_pending = 0; 1663 1664 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1665 0, CTLTYPE_NODE, sc->sk_dev.dv_xname, 1666 SYSCTL_DESCR("skc per-controller controls"), 1667 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE, 1668 CTL_EOL)) != 0) { 1669 aprint_normal("%s: couldn't create sysctl node\n", 1670 sc->sk_dev.dv_xname); 1671 goto fail; 1672 } 1673 1674 sk_nodenum = node->sysctl_num; 1675 1676 /* interrupt moderation time in usecs */ 1677 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node, 1678 CTLFLAG_READWRITE, 1679 CTLTYPE_INT, "int_mod", 1680 SYSCTL_DESCR("sk interrupt moderation timer"), 1681 sk_sysctl_handler, 0, sc, 1682 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE, 1683 CTL_EOL)) != 0) { 1684 aprint_normal("%s: couldn't create int_mod sysctl node\n", 1685 sc->sk_dev.dv_xname); 1686 goto fail; 1687 } 1688 1689 fail: 1690 splx(s); 1691 } 1692 1693 int 1694 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx) 1695 { 1696 struct sk_softc *sc = sc_if->sk_softc; 1697 struct sk_tx_desc *f = NULL; 1698 u_int32_t frag, cur, cnt = 0; 1699 int i; 1700 struct sk_txmap_entry *entry; 1701 bus_dmamap_t txmap; 1702 1703 DPRINTFN(3, ("sk_encap\n")); 1704 1705 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head); 1706 if (entry == NULL) { 1707 DPRINTFN(3, ("sk_encap: no txmap available\n")); 1708 return ENOBUFS; 1709 } 1710 txmap = entry->dmamap; 1711 1712 cur = frag = *txidx; 1713 1714 #ifdef SK_DEBUG 1715 if (skdebug >= 3) 1716 sk_dump_mbuf(m_head); 1717 #endif 1718 1719 /* 1720 * Start packing the mbufs in this chain into 1721 * the fragment pointers. Stop when we run out 1722 * of fragments or hit the end of the mbuf chain. 1723 */ 1724 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head, 1725 BUS_DMA_NOWAIT)) { 1726 DPRINTFN(1, ("sk_encap: dmamap failed\n")); 1727 return(ENOBUFS); 1728 } 1729 1730 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1731 1732 /* Sync the DMA map. */ 1733 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize, 1734 BUS_DMASYNC_PREWRITE); 1735 1736 for (i = 0; i < txmap->dm_nsegs; i++) { 1737 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) { 1738 DPRINTFN(1, ("sk_encap: too few descriptors free\n")); 1739 return(ENOBUFS); 1740 } 1741 f = &sc_if->sk_rdata->sk_tx_ring[frag]; 1742 f->sk_data_lo = txmap->dm_segs[i].ds_addr; 1743 f->sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT; 1744 if (cnt == 0) 1745 f->sk_ctl |= SK_TXCTL_FIRSTFRAG; 1746 else 1747 f->sk_ctl |= SK_TXCTL_OWN; 1748 1749 cur = frag; 1750 SK_INC(frag, SK_TX_RING_CNT); 1751 cnt++; 1752 } 1753 1754 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head; 1755 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link); 1756 1757 sc_if->sk_cdata.sk_tx_map[cur] = entry; 1758 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |= 1759 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR; 1760 1761 /* Sync descriptors before handing to chip */ 1762 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs, 1763 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1764 1765 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN; 1766 1767 /* Sync first descriptor to hand it off */ 1768 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1769 1770 sc_if->sk_cdata.sk_tx_cnt += cnt; 1771 1772 #ifdef SK_DEBUG 1773 if (skdebug >= 3) { 1774 struct sk_tx_desc *desc; 1775 u_int32_t idx; 1776 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) { 1777 desc = &sc_if->sk_rdata->sk_tx_ring[idx]; 1778 sk_dump_txdesc(desc, idx); 1779 } 1780 } 1781 #endif 1782 1783 *txidx = frag; 1784 1785 DPRINTFN(3, ("sk_encap: completed successfully\n")); 1786 1787 return(0); 1788 } 1789 1790 void 1791 sk_start(struct ifnet *ifp) 1792 { 1793 struct sk_if_softc *sc_if = ifp->if_softc; 1794 struct sk_softc *sc = sc_if->sk_softc; 1795 struct mbuf *m_head = NULL; 1796 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod; 1797 int pkts = 0; 1798 1799 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx, 1800 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf)); 1801 1802 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) { 1803 1804 IFQ_POLL(&ifp->if_snd, m_head); 1805 if (m_head == NULL) 1806 break; 1807 1808 /* 1809 * Pack the data into the transmit ring. If we 1810 * don't have room, set the OACTIVE flag and wait 1811 * for the NIC to drain the ring. 1812 */ 1813 if (sk_encap(sc_if, m_head, &idx)) { 1814 ifp->if_flags |= IFF_OACTIVE; 1815 break; 1816 } 1817 1818 /* now we are committed to transmit the packet */ 1819 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1820 pkts++; 1821 1822 /* 1823 * If there's a BPF listener, bounce a copy of this frame 1824 * to him. 1825 */ 1826 #if NBPFILTER > 0 1827 if (ifp->if_bpf) 1828 bpf_mtap(ifp->if_bpf, m_head); 1829 #endif 1830 } 1831 if (pkts == 0) 1832 return; 1833 1834 /* Transmit */ 1835 if (idx != sc_if->sk_cdata.sk_tx_prod) { 1836 sc_if->sk_cdata.sk_tx_prod = idx; 1837 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 1838 1839 /* Set a timeout in case the chip goes out to lunch. */ 1840 ifp->if_timer = 5; 1841 } 1842 } 1843 1844 1845 void 1846 sk_watchdog(struct ifnet *ifp) 1847 { 1848 struct sk_if_softc *sc_if = ifp->if_softc; 1849 1850 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname); 1851 (void) sk_init(ifp); 1852 } 1853 1854 void 1855 sk_shutdown(void * v) 1856 { 1857 struct sk_if_softc *sc_if = (struct sk_if_softc *)v; 1858 struct sk_softc *sc = sc_if->sk_softc; 1859 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1860 1861 DPRINTFN(2, ("sk_shutdown\n")); 1862 sk_stop(ifp,1); 1863 1864 /* Turn off the 'driver is loaded' LED. */ 1865 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); 1866 1867 /* 1868 * Reset the GEnesis controller. Doing this should also 1869 * assert the resets on the attached XMAC(s). 1870 */ 1871 sk_reset(sc); 1872 } 1873 1874 void 1875 sk_rxeof(struct sk_if_softc *sc_if) 1876 { 1877 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1878 struct mbuf *m; 1879 struct sk_chain *cur_rx; 1880 struct sk_rx_desc *cur_desc; 1881 int i, cur, total_len = 0; 1882 u_int32_t rxstat; 1883 bus_dmamap_t dmamap; 1884 1885 i = sc_if->sk_cdata.sk_rx_prod; 1886 1887 DPRINTFN(3, ("sk_rxeof %d\n", i)); 1888 1889 for (;;) { 1890 cur = i; 1891 1892 /* Sync the descriptor */ 1893 SK_CDRXSYNC(sc_if, cur, 1894 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1895 1896 if (sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl & SK_RXCTL_OWN) { 1897 /* Invalidate the descriptor -- it's not ready yet */ 1898 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD); 1899 sc_if->sk_cdata.sk_rx_prod = i; 1900 break; 1901 } 1902 1903 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur]; 1904 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur]; 1905 dmamap = sc_if->sk_cdata.sk_rx_map[cur]; 1906 1907 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0, 1908 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1909 1910 rxstat = cur_desc->sk_xmac_rxstat; 1911 m = cur_rx->sk_mbuf; 1912 cur_rx->sk_mbuf = NULL; 1913 total_len = SK_RXBYTES(cur_desc->sk_ctl); 1914 1915 sc_if->sk_cdata.sk_rx_map[cur] = 0; 1916 1917 SK_INC(i, SK_RX_RING_CNT); 1918 1919 if (rxstat & XM_RXSTAT_ERRFRAME) { 1920 ifp->if_ierrors++; 1921 sk_newbuf(sc_if, cur, m, dmamap); 1922 continue; 1923 } 1924 1925 /* 1926 * Try to allocate a new jumbo buffer. If that 1927 * fails, copy the packet to mbufs and put the 1928 * jumbo buffer back in the ring so it can be 1929 * re-used. If allocating mbufs fails, then we 1930 * have to drop the packet. 1931 */ 1932 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) { 1933 struct mbuf *m0; 1934 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1935 total_len + ETHER_ALIGN, 0, ifp, NULL); 1936 sk_newbuf(sc_if, cur, m, dmamap); 1937 if (m0 == NULL) { 1938 printf("%s: no receive buffers " 1939 "available -- packet dropped!\n", 1940 sc_if->sk_dev.dv_xname); 1941 ifp->if_ierrors++; 1942 continue; 1943 } 1944 m_adj(m0, ETHER_ALIGN); 1945 m = m0; 1946 } else { 1947 m->m_pkthdr.rcvif = ifp; 1948 m->m_pkthdr.len = m->m_len = total_len; 1949 } 1950 1951 ifp->if_ipackets++; 1952 1953 #if NBPFILTER > 0 1954 if (ifp->if_bpf) 1955 bpf_mtap(ifp->if_bpf, m); 1956 #endif 1957 /* pass it on. */ 1958 (*ifp->if_input)(ifp, m); 1959 } 1960 } 1961 1962 void 1963 sk_txeof(struct sk_if_softc *sc_if) 1964 { 1965 struct sk_softc *sc = sc_if->sk_softc; 1966 struct sk_tx_desc *cur_tx; 1967 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 1968 u_int32_t idx; 1969 struct sk_txmap_entry *entry; 1970 1971 DPRINTFN(3, ("sk_txeof\n")); 1972 1973 /* 1974 * Go through our tx ring and free mbufs for those 1975 * frames that have been sent. 1976 */ 1977 idx = sc_if->sk_cdata.sk_tx_cons; 1978 while(idx != sc_if->sk_cdata.sk_tx_prod) { 1979 SK_CDTXSYNC(sc_if, idx, 1, 1980 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1981 1982 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx]; 1983 #ifdef SK_DEBUG 1984 if (skdebug >= 3) 1985 sk_dump_txdesc(cur_tx, idx); 1986 #endif 1987 if (cur_tx->sk_ctl & SK_TXCTL_OWN) { 1988 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD); 1989 break; 1990 } 1991 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG) 1992 ifp->if_opackets++; 1993 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) { 1994 entry = sc_if->sk_cdata.sk_tx_map[idx]; 1995 1996 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf); 1997 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL; 1998 1999 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0, 2000 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2001 2002 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap); 2003 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry, 2004 link); 2005 sc_if->sk_cdata.sk_tx_map[idx] = NULL; 2006 } 2007 sc_if->sk_cdata.sk_tx_cnt--; 2008 SK_INC(idx, SK_TX_RING_CNT); 2009 } 2010 if (sc_if->sk_cdata.sk_tx_cnt == 0) 2011 ifp->if_timer = 0; 2012 else /* nudge chip to keep tx ring moving */ 2013 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2014 2015 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2) 2016 ifp->if_flags &= ~IFF_OACTIVE; 2017 2018 sc_if->sk_cdata.sk_tx_cons = idx; 2019 } 2020 2021 void 2022 sk_tick(void *xsc_if) 2023 { 2024 struct sk_if_softc *sc_if = xsc_if; 2025 struct mii_data *mii = &sc_if->sk_mii; 2026 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2027 int i; 2028 2029 DPRINTFN(3, ("sk_tick\n")); 2030 2031 if (!(ifp->if_flags & IFF_UP)) 2032 return; 2033 2034 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2035 sk_intr_bcom(sc_if); 2036 return; 2037 } 2038 2039 /* 2040 * According to SysKonnect, the correct way to verify that 2041 * the link has come back up is to poll bit 0 of the GPIO 2042 * register three times. This pin has the signal from the 2043 * link sync pin connected to it; if we read the same link 2044 * state 3 times in a row, we know the link is up. 2045 */ 2046 for (i = 0; i < 3; i++) { 2047 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET) 2048 break; 2049 } 2050 2051 if (i != 3) { 2052 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2053 return; 2054 } 2055 2056 /* Turn the GP0 interrupt back on. */ 2057 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2058 SK_XM_READ_2(sc_if, XM_ISR); 2059 mii_tick(mii); 2060 mii_pollstat(mii); 2061 callout_stop(&sc_if->sk_tick_ch); 2062 } 2063 2064 void 2065 sk_intr_bcom(struct sk_if_softc *sc_if) 2066 { 2067 struct mii_data *mii = &sc_if->sk_mii; 2068 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2069 int status; 2070 2071 2072 DPRINTFN(3, ("sk_intr_bcom\n")); 2073 2074 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2075 2076 /* 2077 * Read the PHY interrupt register to make sure 2078 * we clear any pending interrupts. 2079 */ 2080 status = sk_xmac_miibus_readreg((struct device *)sc_if, 2081 SK_PHYADDR_BCOM, BRGPHY_MII_ISR); 2082 2083 if (!(ifp->if_flags & IFF_RUNNING)) { 2084 sk_init_xmac(sc_if); 2085 return; 2086 } 2087 2088 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) { 2089 int lstat; 2090 lstat = sk_xmac_miibus_readreg((struct device *)sc_if, 2091 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS); 2092 2093 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) { 2094 mii_mediachg(mii); 2095 /* Turn off the link LED. */ 2096 SK_IF_WRITE_1(sc_if, 0, 2097 SK_LINKLED1_CTL, SK_LINKLED_OFF); 2098 sc_if->sk_link = 0; 2099 } else if (status & BRGPHY_ISR_LNK_CHG) { 2100 sk_xmac_miibus_writereg((struct device *)sc_if, 2101 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00); 2102 mii_tick(mii); 2103 sc_if->sk_link = 1; 2104 /* Turn on the link LED. */ 2105 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2106 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF| 2107 SK_LINKLED_BLINK_OFF); 2108 mii_pollstat(mii); 2109 } else { 2110 mii_tick(mii); 2111 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick,sc_if); 2112 } 2113 } 2114 2115 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2116 } 2117 2118 void 2119 sk_intr_xmac(struct sk_if_softc *sc_if) 2120 { 2121 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR); 2122 2123 DPRINTFN(3, ("sk_intr_xmac\n")); 2124 2125 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) { 2126 if (status & XM_ISR_GP0_SET) { 2127 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET); 2128 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2129 } 2130 2131 if (status & XM_ISR_AUTONEG_DONE) { 2132 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if); 2133 } 2134 } 2135 2136 if (status & XM_IMR_TX_UNDERRUN) 2137 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO); 2138 2139 if (status & XM_IMR_RX_OVERRUN) 2140 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO); 2141 } 2142 2143 void 2144 sk_intr_yukon(sc_if) 2145 struct sk_if_softc *sc_if; 2146 { 2147 int status; 2148 2149 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2150 2151 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status)); 2152 } 2153 2154 int 2155 sk_intr(void *xsc) 2156 { 2157 struct sk_softc *sc = xsc; 2158 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A]; 2159 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B]; 2160 struct ifnet *ifp0 = NULL, *ifp1 = NULL; 2161 u_int32_t status; 2162 int claimed = 0; 2163 2164 if (sc_if0 != NULL) 2165 ifp0 = &sc_if0->sk_ethercom.ec_if; 2166 if (sc_if1 != NULL) 2167 ifp1 = &sc_if1->sk_ethercom.ec_if; 2168 2169 for (;;) { 2170 status = CSR_READ_4(sc, SK_ISSR); 2171 DPRINTFN(3, ("sk_intr: status=%#x\n", status)); 2172 2173 if (!(status & sc->sk_intrmask)) 2174 break; 2175 2176 claimed = 1; 2177 2178 /* Handle receive interrupts first. */ 2179 if (status & SK_ISR_RX1_EOF) { 2180 sk_rxeof(sc_if0); 2181 CSR_WRITE_4(sc, SK_BMU_RX_CSR0, 2182 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2183 } 2184 if (status & SK_ISR_RX2_EOF) { 2185 sk_rxeof(sc_if1); 2186 CSR_WRITE_4(sc, SK_BMU_RX_CSR1, 2187 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START); 2188 } 2189 2190 /* Then transmit interrupts. */ 2191 if (status & SK_ISR_TX1_S_EOF) { 2192 sk_txeof(sc_if0); 2193 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, 2194 SK_TXBMU_CLR_IRQ_EOF); 2195 } 2196 if (status & SK_ISR_TX2_S_EOF) { 2197 sk_txeof(sc_if1); 2198 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, 2199 SK_TXBMU_CLR_IRQ_EOF); 2200 } 2201 2202 /* Then MAC interrupts. */ 2203 if (status & SK_ISR_MAC1 && (ifp0->if_flags & IFF_RUNNING)) { 2204 if (sc->sk_type == SK_GENESIS) 2205 sk_intr_xmac(sc_if0); 2206 else 2207 sk_intr_yukon(sc_if0); 2208 } 2209 2210 if (status & SK_ISR_MAC2 && (ifp1->if_flags & IFF_RUNNING)) { 2211 if (sc->sk_type == SK_GENESIS) 2212 sk_intr_xmac(sc_if1); 2213 else 2214 sk_intr_yukon(sc_if1); 2215 2216 } 2217 2218 if (status & SK_ISR_EXTERNAL_REG) { 2219 if (ifp0 != NULL && 2220 sc_if0->sk_phytype == SK_PHYTYPE_BCOM) 2221 sk_intr_bcom(sc_if0); 2222 2223 if (ifp1 != NULL && 2224 sc_if1->sk_phytype == SK_PHYTYPE_BCOM) 2225 sk_intr_bcom(sc_if1); 2226 } 2227 } 2228 2229 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2230 2231 if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd)) 2232 sk_start(ifp0); 2233 if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd)) 2234 sk_start(ifp1); 2235 2236 #if NRND > 0 2237 if (RND_ENABLED(&sc->rnd_source)) 2238 rnd_add_uint32(&sc->rnd_source, status); 2239 #endif 2240 2241 if (sc->sk_int_mod_pending) 2242 sk_update_int_mod(sc); 2243 2244 return (claimed); 2245 } 2246 2247 void 2248 sk_init_xmac(struct sk_if_softc *sc_if) 2249 { 2250 struct sk_softc *sc = sc_if->sk_softc; 2251 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if; 2252 static const struct sk_bcom_hack bhack[] = { 2253 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, 2254 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, 2255 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 2256 { 0, 0 } }; 2257 2258 DPRINTFN(1, ("sk_init_xmac\n")); 2259 2260 /* Unreset the XMAC. */ 2261 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET); 2262 DELAY(1000); 2263 2264 /* Reset the XMAC's internal state. */ 2265 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2266 2267 /* Save the XMAC II revision */ 2268 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID)); 2269 2270 /* 2271 * Perform additional initialization for external PHYs, 2272 * namely for the 1000baseTX cards that use the XMAC's 2273 * GMII mode. 2274 */ 2275 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2276 int i = 0; 2277 u_int32_t val; 2278 2279 /* Take PHY out of reset. */ 2280 val = sk_win_read_4(sc, SK_GPIO); 2281 if (sc_if->sk_port == SK_PORT_A) 2282 val |= SK_GPIO_DIR0|SK_GPIO_DAT0; 2283 else 2284 val |= SK_GPIO_DIR2|SK_GPIO_DAT2; 2285 sk_win_write_4(sc, SK_GPIO, val); 2286 2287 /* Enable GMII mode on the XMAC. */ 2288 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE); 2289 2290 sk_xmac_miibus_writereg((struct device *)sc_if, 2291 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET); 2292 DELAY(10000); 2293 sk_xmac_miibus_writereg((struct device *)sc_if, 2294 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0); 2295 2296 /* 2297 * Early versions of the BCM5400 apparently have 2298 * a bug that requires them to have their reserved 2299 * registers initialized to some magic values. I don't 2300 * know what the numbers do, I'm just the messenger. 2301 */ 2302 if (sk_xmac_miibus_readreg((struct device *)sc_if, 2303 SK_PHYADDR_BCOM, 0x03) == 0x6041) { 2304 while(bhack[i].reg) { 2305 sk_xmac_miibus_writereg((struct device *)sc_if, 2306 SK_PHYADDR_BCOM, bhack[i].reg, 2307 bhack[i].val); 2308 i++; 2309 } 2310 } 2311 } 2312 2313 /* Set station address */ 2314 SK_XM_WRITE_2(sc_if, XM_PAR0, 2315 *(u_int16_t *)(&sc_if->sk_enaddr[0])); 2316 SK_XM_WRITE_2(sc_if, XM_PAR1, 2317 *(u_int16_t *)(&sc_if->sk_enaddr[2])); 2318 SK_XM_WRITE_2(sc_if, XM_PAR2, 2319 *(u_int16_t *)(&sc_if->sk_enaddr[4])); 2320 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION); 2321 2322 if (ifp->if_flags & IFF_PROMISC) { 2323 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2324 } else { 2325 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC); 2326 } 2327 2328 if (ifp->if_flags & IFF_BROADCAST) { 2329 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2330 } else { 2331 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD); 2332 } 2333 2334 /* We don't need the FCS appended to the packet. */ 2335 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS); 2336 2337 /* We want short frames padded to 60 bytes. */ 2338 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD); 2339 2340 /* 2341 * Enable the reception of all error frames. This is is 2342 * a necessary evil due to the design of the XMAC. The 2343 * XMAC's receive FIFO is only 8K in size, however jumbo 2344 * frames can be up to 9000 bytes in length. When bad 2345 * frame filtering is enabled, the XMAC's RX FIFO operates 2346 * in 'store and forward' mode. For this to work, the 2347 * entire frame has to fit into the FIFO, but that means 2348 * that jumbo frames larger than 8192 bytes will be 2349 * truncated. Disabling all bad frame filtering causes 2350 * the RX FIFO to operate in streaming mode, in which 2351 * case the XMAC will start transfering frames out of the 2352 * RX FIFO as soon as the FIFO threshold is reached. 2353 */ 2354 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES| 2355 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS| 2356 XM_MODE_RX_INRANGELEN); 2357 2358 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2359 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2360 else 2361 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK); 2362 2363 /* 2364 * Bump up the transmit threshold. This helps hold off transmit 2365 * underruns when we're blasting traffic from both ports at once. 2366 */ 2367 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH); 2368 2369 /* Set multicast filter */ 2370 sk_setmulti(sc_if); 2371 2372 /* Clear and enable interrupts */ 2373 SK_XM_READ_2(sc_if, XM_ISR); 2374 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) 2375 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS); 2376 else 2377 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2378 2379 /* Configure MAC arbiter */ 2380 switch(sc_if->sk_xmac_rev) { 2381 case XM_XMAC_REV_B2: 2382 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2); 2383 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2); 2384 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2); 2385 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2); 2386 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2); 2387 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2); 2388 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2); 2389 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2); 2390 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2391 break; 2392 case XM_XMAC_REV_C1: 2393 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1); 2394 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1); 2395 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1); 2396 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1); 2397 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1); 2398 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1); 2399 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1); 2400 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1); 2401 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2); 2402 break; 2403 default: 2404 break; 2405 } 2406 sk_win_write_2(sc, SK_MACARB_CTL, 2407 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF); 2408 2409 sc_if->sk_link = 1; 2410 } 2411 2412 void sk_init_yukon(sc_if) 2413 struct sk_if_softc *sc_if; 2414 { 2415 u_int32_t /*mac, */phy; 2416 u_int16_t reg; 2417 struct sk_softc *sc; 2418 int i; 2419 2420 DPRINTFN(1, ("sk_init_yukon: start: sk_csr=%#x\n", 2421 CSR_READ_4(sc_if->sk_softc, SK_CSR))); 2422 2423 sc = sc_if->sk_softc; 2424 if (sc->sk_type == SK_YUKON_LITE && 2425 sc->sk_rev >= SK_YUKON_LITE_REV_A3) { 2426 /* Take PHY out of reset. */ 2427 sk_win_write_4(sc, SK_GPIO, 2428 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9) & ~SK_GPIO_DAT9); 2429 } 2430 2431 2432 /* GMAC and GPHY Reset */ 2433 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET); 2434 2435 DPRINTFN(6, ("sk_init_yukon: 1\n")); 2436 2437 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2438 DELAY(1000); 2439 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR); 2440 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET); 2441 DELAY(1000); 2442 2443 2444 DPRINTFN(6, ("sk_init_yukon: 2\n")); 2445 2446 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP | 2447 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE; 2448 2449 switch(sc_if->sk_softc->sk_pmd) { 2450 case IFM_1000_SX: 2451 case IFM_1000_LX: 2452 phy |= SK_GPHY_FIBER; 2453 break; 2454 2455 case IFM_1000_CX: 2456 case IFM_1000_T: 2457 phy |= SK_GPHY_COPPER; 2458 break; 2459 } 2460 2461 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy)); 2462 2463 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET); 2464 DELAY(1000); 2465 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR); 2466 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF | 2467 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR); 2468 2469 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n", 2470 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL))); 2471 2472 DPRINTFN(6, ("sk_init_yukon: 3\n")); 2473 2474 /* unused read of the interrupt source register */ 2475 DPRINTFN(6, ("sk_init_yukon: 4\n")); 2476 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR); 2477 2478 DPRINTFN(6, ("sk_init_yukon: 4a\n")); 2479 reg = SK_YU_READ_2(sc_if, YUKON_PAR); 2480 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2481 2482 /* MIB Counter Clear Mode set */ 2483 reg |= YU_PAR_MIB_CLR; 2484 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg)); 2485 DPRINTFN(6, ("sk_init_yukon: 4b\n")); 2486 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2487 2488 /* MIB Counter Clear Mode clear */ 2489 DPRINTFN(6, ("sk_init_yukon: 5\n")); 2490 reg &= ~YU_PAR_MIB_CLR; 2491 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg); 2492 2493 /* receive control reg */ 2494 DPRINTFN(6, ("sk_init_yukon: 7\n")); 2495 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN | 2496 YU_RCR_CRCR); 2497 2498 /* transmit parameter register */ 2499 DPRINTFN(6, ("sk_init_yukon: 8\n")); 2500 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) | 2501 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) ); 2502 2503 /* serial mode register */ 2504 DPRINTFN(6, ("sk_init_yukon: 9\n")); 2505 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) | 2506 YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e)); 2507 2508 DPRINTFN(6, ("sk_init_yukon: 10\n")); 2509 /* Setup Yukon's address */ 2510 for (i = 0; i < 3; i++) { 2511 /* Write Source Address 1 (unicast filter) */ 2512 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 2513 sc_if->sk_enaddr[i * 2] | 2514 sc_if->sk_enaddr[i * 2 + 1] << 8); 2515 } 2516 2517 for (i = 0; i < 3; i++) { 2518 reg = sk_win_read_2(sc_if->sk_softc, 2519 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8); 2520 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg); 2521 } 2522 2523 /* Set multicast filter */ 2524 DPRINTFN(6, ("sk_init_yukon: 11\n")); 2525 sk_setmulti(sc_if); 2526 2527 /* enable interrupt mask for counter overflows */ 2528 DPRINTFN(6, ("sk_init_yukon: 12\n")); 2529 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0); 2530 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0); 2531 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0); 2532 2533 /* Configure RX MAC FIFO */ 2534 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR); 2535 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON); 2536 2537 /* Configure TX MAC FIFO */ 2538 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR); 2539 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON); 2540 2541 DPRINTFN(6, ("sk_init_yukon: end\n")); 2542 } 2543 2544 /* 2545 * Note that to properly initialize any part of the GEnesis chip, 2546 * you first have to take it out of reset mode. 2547 */ 2548 int 2549 sk_init(struct ifnet *ifp) 2550 { 2551 struct sk_if_softc *sc_if = ifp->if_softc; 2552 struct sk_softc *sc = sc_if->sk_softc; 2553 struct mii_data *mii = &sc_if->sk_mii; 2554 int s; 2555 u_int32_t imr, sk_imtimer_ticks; 2556 2557 DPRINTFN(1, ("sk_init\n")); 2558 2559 s = splnet(); 2560 2561 if (ifp->if_flags & IFF_RUNNING) { 2562 splx(s); 2563 return 0; 2564 } 2565 2566 /* Cancel pending I/O and free all RX/TX buffers. */ 2567 sk_stop(ifp,0); 2568 2569 if (sc->sk_type == SK_GENESIS) { 2570 /* Configure LINK_SYNC LED */ 2571 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON); 2572 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, 2573 SK_LINKLED_LINKSYNC_ON); 2574 2575 /* Configure RX LED */ 2576 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, 2577 SK_RXLEDCTL_COUNTER_START); 2578 2579 /* Configure TX LED */ 2580 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, 2581 SK_TXLEDCTL_COUNTER_START); 2582 } 2583 2584 /* Configure I2C registers */ 2585 2586 /* Configure XMAC(s) */ 2587 switch (sc->sk_type) { 2588 case SK_GENESIS: 2589 sk_init_xmac(sc_if); 2590 break; 2591 case SK_YUKON: 2592 case SK_YUKON_LITE: 2593 case SK_YUKON_LP: 2594 sk_init_yukon(sc_if); 2595 break; 2596 } 2597 mii_mediachg(mii); 2598 2599 if (sc->sk_type == SK_GENESIS) { 2600 /* Configure MAC FIFOs */ 2601 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET); 2602 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END); 2603 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON); 2604 2605 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET); 2606 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END); 2607 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON); 2608 } 2609 2610 /* Configure transmit arbiter(s) */ 2611 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, 2612 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON); 2613 2614 /* Configure RAMbuffers */ 2615 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET); 2616 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart); 2617 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart); 2618 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart); 2619 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend); 2620 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON); 2621 2622 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET); 2623 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON); 2624 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart); 2625 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart); 2626 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart); 2627 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend); 2628 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON); 2629 2630 /* Configure BMUs */ 2631 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE); 2632 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO, 2633 SK_RX_RING_ADDR(sc_if, 0)); 2634 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0); 2635 2636 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE); 2637 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO, 2638 SK_TX_RING_ADDR(sc_if, 0)); 2639 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0); 2640 2641 /* Init descriptors */ 2642 if (sk_init_rx_ring(sc_if) == ENOBUFS) { 2643 printf("%s: initialization failed: no " 2644 "memory for rx buffers\n", sc_if->sk_dev.dv_xname); 2645 sk_stop(ifp,0); 2646 splx(s); 2647 return(ENOBUFS); 2648 } 2649 2650 if (sk_init_tx_ring(sc_if) == ENOBUFS) { 2651 printf("%s: initialization failed: no " 2652 "memory for tx buffers\n", sc_if->sk_dev.dv_xname); 2653 sk_stop(ifp,0); 2654 splx(s); 2655 return(ENOBUFS); 2656 } 2657 2658 /* Set interrupt moderation if changed via sysctl. */ 2659 switch (sc->sk_type) { 2660 case SK_GENESIS: 2661 sk_imtimer_ticks = SK_IMTIMER_TICKS_GENESIS; 2662 break; 2663 case SK_YUKON_EC: 2664 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC; 2665 break; 2666 default: 2667 sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON; 2668 } 2669 imr = sk_win_read_4(sc, SK_IMTIMERINIT); 2670 if (imr != SK_IM_USECS(sc->sk_int_mod)) { 2671 sk_win_write_4(sc, SK_IMTIMERINIT, 2672 SK_IM_USECS(sc->sk_int_mod)); 2673 aprint_verbose("%s: interrupt moderation is %d us\n", 2674 sc->sk_dev.dv_xname, sc->sk_int_mod); 2675 } 2676 2677 /* Configure interrupt handling */ 2678 CSR_READ_4(sc, SK_ISSR); 2679 if (sc_if->sk_port == SK_PORT_A) 2680 sc->sk_intrmask |= SK_INTRS1; 2681 else 2682 sc->sk_intrmask |= SK_INTRS2; 2683 2684 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG; 2685 2686 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2687 2688 /* Start BMUs. */ 2689 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START); 2690 2691 if (sc->sk_type == SK_GENESIS) { 2692 /* Enable XMACs TX and RX state machines */ 2693 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE); 2694 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, 2695 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB); 2696 } 2697 2698 if (SK_YUKON_FAMILY(sc->sk_type)) { 2699 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR); 2700 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN; 2701 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN); 2702 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg); 2703 } 2704 2705 2706 ifp->if_flags |= IFF_RUNNING; 2707 ifp->if_flags &= ~IFF_OACTIVE; 2708 2709 splx(s); 2710 return(0); 2711 } 2712 2713 void 2714 sk_stop(struct ifnet *ifp, int disable) 2715 { 2716 struct sk_if_softc *sc_if = ifp->if_softc; 2717 struct sk_softc *sc = sc_if->sk_softc; 2718 //struct sk_txmap_entry *dma; 2719 int i; 2720 2721 DPRINTFN(1, ("sk_stop\n")); 2722 2723 callout_stop(&sc_if->sk_tick_ch); 2724 2725 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) { 2726 u_int32_t val; 2727 2728 /* Put PHY back into reset. */ 2729 val = sk_win_read_4(sc, SK_GPIO); 2730 if (sc_if->sk_port == SK_PORT_A) { 2731 val |= SK_GPIO_DIR0; 2732 val &= ~SK_GPIO_DAT0; 2733 } else { 2734 val |= SK_GPIO_DIR2; 2735 val &= ~SK_GPIO_DAT2; 2736 } 2737 sk_win_write_4(sc, SK_GPIO, val); 2738 } 2739 2740 /* Turn off various components of this interface. */ 2741 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC); 2742 switch (sc->sk_type) { 2743 case SK_GENESIS: 2744 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, 2745 SK_TXMACCTL_XMAC_RESET); 2746 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET); 2747 break; 2748 case SK_YUKON: 2749 case SK_YUKON_LITE: 2750 case SK_YUKON_LP: 2751 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET); 2752 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET); 2753 break; 2754 } 2755 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE); 2756 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2757 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE); 2758 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF); 2759 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF); 2760 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2761 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP); 2762 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF); 2763 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF); 2764 2765 /* Disable interrupts */ 2766 if (sc_if->sk_port == SK_PORT_A) 2767 sc->sk_intrmask &= ~SK_INTRS1; 2768 else 2769 sc->sk_intrmask &= ~SK_INTRS2; 2770 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2771 2772 SK_XM_READ_2(sc_if, XM_ISR); 2773 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF); 2774 2775 /* Free RX and TX mbufs still in the queues. */ 2776 for (i = 0; i < SK_RX_RING_CNT; i++) { 2777 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) { 2778 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf); 2779 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL; 2780 } 2781 } 2782 2783 for (i = 0; i < SK_TX_RING_CNT; i++) { 2784 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) { 2785 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf); 2786 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL; 2787 } 2788 } 2789 2790 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 2791 } 2792 2793 CFATTACH_DECL(skc,sizeof(struct sk_softc), skc_probe, skc_attach, NULL, NULL); 2794 2795 /* 2796 struct cfdriver skc_cd = { 2797 0, "skc", DV_DULL 2798 }; 2799 */ 2800 2801 CFATTACH_DECL(sk,sizeof(struct sk_if_softc), sk_probe, sk_attach, NULL, NULL); 2802 2803 /* 2804 struct cfdriver sk_cd = { 2805 0, "sk", DV_IFNET 2806 }; 2807 */ 2808 2809 #ifdef SK_DEBUG 2810 void 2811 sk_dump_txdesc(struct sk_tx_desc *desc, int idx) 2812 { 2813 #define DESC_PRINT(X) \ 2814 if (desc->X) \ 2815 printf("txdesc[%d]." #X "=%#x\n", \ 2816 idx, desc->X); 2817 2818 DESC_PRINT(sk_ctl); 2819 DESC_PRINT(sk_next); 2820 DESC_PRINT(sk_data_lo); 2821 DESC_PRINT(sk_data_hi); 2822 DESC_PRINT(sk_xmac_txstat); 2823 DESC_PRINT(sk_rsvd0); 2824 DESC_PRINT(sk_csum_startval); 2825 DESC_PRINT(sk_csum_startpos); 2826 DESC_PRINT(sk_csum_writepos); 2827 DESC_PRINT(sk_rsvd1); 2828 #undef PRINT 2829 } 2830 2831 void 2832 sk_dump_bytes(const char *data, int len) 2833 { 2834 int c, i, j; 2835 2836 for (i = 0; i < len; i += 16) { 2837 printf("%08x ", i); 2838 c = len - i; 2839 if (c > 16) c = 16; 2840 2841 for (j = 0; j < c; j++) { 2842 printf("%02x ", data[i + j] & 0xff); 2843 if ((j & 0xf) == 7 && j > 0) 2844 printf(" "); 2845 } 2846 2847 for (; j < 16; j++) 2848 printf(" "); 2849 printf(" "); 2850 2851 for (j = 0; j < c; j++) { 2852 int ch = data[i + j] & 0xff; 2853 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); 2854 } 2855 2856 printf("\n"); 2857 2858 if (c < 16) 2859 break; 2860 } 2861 } 2862 2863 void 2864 sk_dump_mbuf(struct mbuf *m) 2865 { 2866 int count = m->m_pkthdr.len; 2867 2868 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len); 2869 2870 while (count > 0 && m) { 2871 printf("m=%p, m->m_data=%p, m->m_len=%d\n", 2872 m, m->m_data, m->m_len); 2873 sk_dump_bytes(mtod(m, char *), m->m_len); 2874 2875 count -= m->m_len; 2876 m = m->m_next; 2877 } 2878 } 2879 #endif 2880 2881 static int 2882 sk_sysctl_handler(SYSCTLFN_ARGS) 2883 { 2884 int error, t; 2885 struct sysctlnode node; 2886 struct sk_softc *sc; 2887 2888 node = *rnode; 2889 sc = node.sysctl_data; 2890 t = sc->sk_int_mod; 2891 node.sysctl_data = &t; 2892 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 2893 if (error || newp == NULL) 2894 return (error); 2895 2896 if (t < SK_IM_MIN || t > SK_IM_MAX) 2897 return (EINVAL); 2898 2899 /* update the softc with sysctl-changed value, and mark 2900 for hardware update */ 2901 sc->sk_int_mod = t; 2902 sc->sk_int_mod_pending = 1; 2903 return (0); 2904 } 2905 2906 /* 2907 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be 2908 * set up in skc_attach() 2909 */ 2910 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup") 2911 { 2912 int rc; 2913 const struct sysctlnode *node; 2914 2915 if ((rc = sysctl_createv(clog, 0, NULL, NULL, 2916 0, CTLTYPE_NODE, "hw", NULL, 2917 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) { 2918 goto err; 2919 } 2920 2921 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2922 0, CTLTYPE_NODE, "sk", 2923 SYSCTL_DESCR("sk interface controls"), 2924 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2925 goto err; 2926 } 2927 2928 sk_root_num = node->sysctl_num; 2929 return; 2930 2931 err: 2932 printf("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2933 } 2934
Indexes created Mon Sep 22 21:09:42 GMT 2025